Component documentation

Component name - Name of the component.
Channel - The channel used for serial asynchronous communication.
Interrupt service/event - The component may or may not be implemented using interrupts. If this property is set to "Enabled", the component functionality (e.g. sending and receiving data) depends on the interrupt service and will not operate if the CPU interrupts are disabled. For details please refer to chapter "interrupt service in the component's generated code".
The following items are available only if the group is enabled (the value is "Enabled"):
- Interrupt RxD - Interrupt from serial receiver.
- Interrupt RxD priority - The priority of the interrupt associated with the asynchronous communication.
- Interrupt TxD - Interrupt from serial transmitter.
- Interrupt TxD priority - Priority of the interrupt associated with the asynchronous communication.
- Settings supported for Freescale 56800/E, ColdFireV1, HC08, HCS08, HCS12, HCS12X, MCF and RS08 derivatives only.
  - Interrupt Error - Error interrupt from serial receiver.
  - Interrupt Error priority - Priority of the interrupt associated with the asynchronous communication.
- Input buffer size - Input buffer size in bytes.
- Output buffer size - Output buffer size in bytes.
- Handshake - Communication handshake. The handshake can be supported by HW (special pins) or implemented by SW (any pins). SW handshake can be safely used only when the system is not heavily loaded. If SW handshake is used and the system is overloaded then overrun errors may occur.
  - CTS - Clear to send handshake. To use this feature the Transmitter must be enabled.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - HW support required - User may select this when the CPU has a special pin reserved for the CTS signal. This pin will service the CTS.
    - CTS Pin - Clear-to-send pin.
    - CTS pin signal - Signal name of CTS pin.
    - Interrupt CTS - Interrupt from the CTS.
    - Interrupt CTS priority - Priority of the interrupt associated with the asynchronous communication.
  - RTS - Ready to send handshake. To use this feature the Receiver must be enabled.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - HW support required - User may select this when the CPU has a special pin reserved for the RTS signal. This pin will service the RTS.
    - RTS Pin - Ready-to-send pin
    - RTS pin signal - Signal name of RTS pin
    - RTS enabled - If an input buffer is enabled and a SW handshake is used then the given number denotes a number of received characters in the buffer when the signal RTS is activated. If a SW handshake is used then the maximum efficiency can be achieved by using the input buffer of a greater size than the specified number for RTS enabled. This item is not accessible if the input buffer is disabled.
Settings - Common component setting.
- Parity - The type of the parity bit (none, hardware odd, hardware even, even (hw or sw), odd (hw or sw)). If odd [even] is selected and the number of “ones” (bits) in the transmitted byte is odd, then the parity bit is 0 [1]. If none is selected, there is no parity bit. The parity bit can be implemented by hardware (if it is supported by the device) or by software.
- Settings not supported for MCF derivatives.
  - Width - Number of information bits.
- Settings not supported for MCF derivatives.
  - Stop bit - Number of stop bits (signaling the end of data transmission).
- Settings supported for Freescale 56800/E, ColdFireV1, HCS08, HCS12, HCS12X and RS08 derivatives only.
  - SCI output mode - Selects the output mode of the SCI device. If the Loop or Single-wire mode is selected the output pin TxD is internally connect to RxD pin. In the Single-wire mode interrconnection is affected by the Transmitter pin direction. If the Output direction is selected, theTxD and RxD pins are internally connected.
    There are 3 modes:
    - Normal - Normal transmission using TxD and RxD pins There are no items in this mode.
    - Loop - TxD and RxD pins are internally connected. There are no items in this mode.
    - Single-wire - Transmission using one bidirectional pin. If the Output direction is selected, theTxD and RxD pins are internally connected. The following items are displayed in this mode:
      - Settings supported for Freescale ColdFireV1, HCS08, HCS12, HCS12X and RS08 derivatives only.
        
        Transmitter pin direction - Direction of the transmitter pin when the single-wire mode is selected.
        
        There are 2 options:
        
        input: TxD pin is an input in single-wire mode
        
        output: TxD pin is an output in single-wire mode
- Receiver - Enable/Disable the receiver.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - RxD - Input pin used for the communication.
  - RxD pin signal - Signal name of RxD pin.
- Transmitter - Enable/Disable the transmitter.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - TxD - Output pin used for the communication.
  - TxD pin signal - Signal name of TxD pin.
- Baud rate - Communication baud rate. It is necessary to enter both a value and an unit (see Timing Setting Syntax). The setting may be made with the help of the Timing dialog box that opens when clicking on (...)button.
- Break signal - Enables/disables a communication break - special state used to cause a communication reset.
- Settings supported for Freescale 56800/E, ColdFireV1, HC08, HCS08, HCS12, HCS12X and RS08 derivatives only.
  - Settings not supported for SLIC module on Freescale HC08 QL3/4 derivatives.
    - Wakeup condition - Selects the condition of wake up the SCI.
      
      There are 2 options:
      - Address mark wakeup: a 1 in MSB position of received character wakes the receiver.
      - Idle line wakeup: An idle character on RxD pin wakes the receiver.
- Settings supported for Freescale 56800/E and HCS08 AC, AW, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LC, LG, LH, LL, MM, MP, QB, QE, QG, SC, SE, SG, SH and SV and HC08 and RS08 and HCS12 HY, P, UF, E256, HN64, HZ256, HZ64 and HCS12X and ColdFireV1 derivatives only.
  - Transmitter output - Reverses the polarity of transmitted data.
- Settings supported for Freescale HCS08 AC, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LG, LH, LL, MM, MP, QB, QE, SC, SE, SG, SH and SV and RS08 and HCS12 HY, P, UF, E256, HN64, HZ256, HZ64 and HCS12X and ColdFireV1 derivatives only.
  - Receiver input - Reverses the polarity of received data.
- Settings supported for Freescale 56800/E, ColdFireV1, HCS08, HCS12, HCS12X and RS08 derivatives only.
  - Stop in wait mode - Determines if the component is stopped in wait mode.
- Settings supported for Freescale ColdFireV1, HC08, HCS08, HCS12, HCS12X and RS08 derivatives only.
  - Settings not supported for SLIC module on Freescale HC08 QL3/4 derivatives.
    - Idle line mode - Idle line mode determines when the counter of idle character starts (after a start bit or stop bit).
      
      There are 2 options:
      - starts after start bit: Idle character bit count starts after start bit
      - starts after stop bit: Idle character bit count starts after stop bit
- Settings for Freescale HC08 EY16, EY16A, GR16, GR16A, GR32A, GR60A, GT16, GZ16, GZ32, GZ60, QB8 and QC16 derivatives.
  - Break detection length - The length of detected break characters. The actual length is determined by the selected data width (e.g. value '10/11 bits' means that for 8bit data the break length is 10bits and for 9bit data the break length is 11bits).
  - Arbiter mode - Mode of the arbiter.
  - Arbiter counter clock source - Clock source for the arbiter counter. In the Bit Time Measurement mode the clock source also determines a measuring method (one half of bus clock – the measured time is between the falling edges, one half of ESCI prescaler – the measured time is during the low level).
    
    There are 2 options:
    - derived from the ESCI clock: Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler.
    - derived from the bus clock: Arbiter counter is clocked with one half or one fourth of the bus clock (in dependence on the selected CPU).
- Settings supported for Freescale HCS08 AC, AW, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LC, LG, LH, LL, MM, MP, QB, QE, QG, SC, SE, SG, SH and SV and HC08 EY16A, GZ, QC, GR16, GR16A, GR32A, GR60A, QB8 and RS08 and HCS12 and HCS12X and ColdFireV1 derivatives only.
  - Break generation length - The length of generated break characters. The actual length is determined by the selected data width (e.g. value '10/11 bits' means that for 8bit data the break length is 10bits and for 9bit data the break length is 11bits).
- Settings supported for Freescale HC08 AP, LJ, LK and HCS12 HY, HA, P, E, NE, UF, HN64, HZ256, HZ64 and HCS12X derivatives only.
  - Infrared SCI output - Infrared SCI output enable/disable.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - SCI transmits - Infrared narrow pulse selection
- Setting supported for Freescale HC08 EY16A derivative only.
  - Slew rate control - The property enables or disables slew rate control for TxD.
- Settings supported for Freescale HCS08 AC, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LG, LH, LL, MM, MP, QB, QE, SC, SE, SG, SH and SV and RS08 and HCS12 HY and P and HCS12X and ColdFireV1 derivatives only.
  - Active edge detection - Enables receive input active edge detection.
    This property is enabled only when the Interrupt service/event property is enabled and either the Receiver property or the SCI output mode property is set to another value than the Normal mode.
- Settings only if SCI support TX modulation.
  - Modulated TX output - Enable/disable TX output modulation with the time base selected via TX modulation time base property.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - TX modulation time base - Select the source of TX modulation time base.
Initialization - Initial settings (after power-on or reset).
- Enabled in init. code - The component is enabled after power-on or reset (in initialization code).
- Events enabled in init. - Events enabled in initialization.
CPU clock/speed selection - Settings for the CPU speed modes: specifies whether the component is supported or not.
For details about speed modes please refer to page Speed Modes Support.
- High speed mode - The component is enabled/disabled in the high speed mode.
- Low speed mode - The component is enabled/disabled in the low speed mode.
- Slow speed mode - The component is enabled/disabled in the slow speed mode.

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