InternalI2C
 
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Component InternalI2C
Internal I2C Communication Interface
Component Level: High
Category: CPU Internal Peripherals-Communication
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • I2C channel - Channel used for I2C communication.
  • Mode selection - This property determines an operating mode of this component. When selected as "MASTER - SLAVE", this component is switchable between MASTER and SLAVE mode using method "SetMode" (MASTER mode is default after initialization).
    The SLAVE mode requires an interrupt service.
  • Interrupt service/event - Component uses the interrupt service for the communication. The interrupt service is required in SLAVE mode. If this property is set to "Enabled", the component functionality (e.g. sending and receiving data) depends on the interrupt service and will not operate if the CPU interrupts are disabled. For details please refer to chapter "interrupt service in the component's generated code".
    The following items are available only if the group is enabled (the value is "Enabled"):
  • MASTER mode - Settings for MASTER mode
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Polling trials - This property determines how many times an interrupt flag is tested during communication started by method SendChar, SendBlock, RecvChar or RecvBlock methods in polling mode. If the interrupt flag is not detected as set during the trial loop, these methods return ERR_BUSOFF. This property is not available when interrupt service is enabled.
    • Automatic stop condition - If "yes" is selected, the stop condition is automatically sent at the end of the send methods to terminate the communication.
      If "no" is selected, the stop condition for send methods has to be sent by the "SendStop" method. This allows to make a combined format of communication on the I2C bus, i.e., the send methods are not automatically terminated by the stop condition. In this case, after any send method it is necessary to call another send or receive method or the "SendStop" method. Warning: it's also necessary to call the SendStop when the MASTER lost the arbitration.
      The stop condition is always sent at the end of receive methods.
      If HW peripheral doesn't support a repeated start sending, the property is not available in all modes.
      Note: Start condition is generated at the beginning of each send/receive method (either start or repeated start).
    • Initialization - Slave initial settings (after power-on or reset).
      • Address mode - This item controls whether the I2C module begins its transfers in 7- or 10-bit addressing mode when acting as a master.
      • Target slave address init - This property determines 7-bit or 10-bit (if supported by HW) slave address initialization value of a slave device to be communicated with in MASTER mode. The address may be changed by SelectSlave or SelectSlave10 method.
  • SLAVE mode - Settings for SLAVE mode
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Address mode - When acting as a slave, this item controls whether the I2C module responds to 7- or 10-bit addresses.
    • Slave address - This property determines slave identification address of this I2C interface. The component in slave mode uses 7-bit or 10-bit (if supported by HW) slave addressing. The other values are reserved for other purposes of I2C bus, for further information see I2C bus specification.
    • General call address - Slave accepts a general call address (zero address byte)
    • Empty character - A character being sent when no data is ready to be transmitted.
    • Settings only if IIC support Slave baudrate control.
      • Slave baud rate control - If enabled, slave baud rate is independent from Mater baud rate. This will force clock stretching on SCL line on very fast IIC modes.
  • Data and Clock - Data and clock signals
    • SDA pin - Data pin used for communication.
    • SDA pin signal - Signal name of SDA pin.
    • SCL pin - Clock pin used for communication.
    • SCL pin signal - Signal name of SCL pin.
    • Settings only if IIC supports High drive select on the PAD.
    • Settings supported for HC08 SR12 AP64 derivatives only.
      • CRC generation / decoding - Enables / disables generation and decoding of CRC. In MASTER mode a CRC is sent after the number of bytes specified in SendBlock method or after one byte sending in case of SendChar method. It means that the total number of bytes sent to the bus equals to the number of bytes specified in SendBlock method + one CRC byte. When receiving in MASTER mode, RecvBlock method specifies number of bytes including one CRC byte. The CRC is checked after the last byte reception. It means, that the shortest received message is 2 bytes long. RecvChar method is always disabled when this property is enabled in MASTER mode. If the Automatic stop condition property is set to "no", the CRC is not sent. In SLAVE mode the CRC is sent/checked after the transmission of the number of bytes specified by "CRC after number of bytes" property.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • CRC after number of bytes - The property specifies after how many bytes of the data the CRC will be sent/checked in SLAVE mode. The property has no meaning in MASTER mode because that is specified by SendBlock/RecvBlock method.
  • Settings not supported for Freescale 56800/E, ColdFireV1, HCS08, HCS12, HCS12X and RS08 derivatives.
  • Settings supported for Freescale 56800/E 56F800x, 56F801x and 56F82xx and HCS08 and RS08 and HCS12 and HCS12X and ColdFireV1 derivatives only.
    • Internal frequency (multiplier factor) - Select an internal frequency of IIC device. The property affects the SCL frequency and the SDA hold value. According to this property bits 6 and 7 of Frequency divider register are set. The highest frequency of the property means the lowest multiplier factor (mul) and vice versa.
    • Bits 0-2 of Frequency divider register - Select the shift register tap point (bits 0-2 of Frequency divider register). The property affects the SCL frequency and the SDA hold value.
    • Bits 3-5 of Frequency divider register - Select the prescaler divider (Bits 3-5 of Frequency divider register). The property affects the SCL frequency and the SDA hold value.
    • SCL frequency - Calculated SCL frequency from an internal frequency regarding 'bits 0-2 of Frequency divider register' and 'bits 3-5 of Frequency divider register' settings (for information only).
    • SDA Hold - Calculated SDA Hold from an internal frequency regarding 'bits 0-2 of Frequency divider register' and 'bits 3-5 of Frequency divider register' settings (for information only).
  • Settings only if IIC supports noise or glitch filter.
    • Noise (glitch) filter - The Noise Filter is inserted to intercept and process the SCL and SDA input signals before the module processes the interface sequence. When an input signal changes state, the Noise Filter will pass the state change after the signal has been stable (not changed) for Noise filter value counts. If the input signal returns to the original state prior to the Noise filter value counts, the counter will clear and the state sent to the module will not change. The Filter Clock frequency and Noise filter value counts dictate the size of glitch suppression. The filter can be completely bypassed by setting the Noise Filter to 0.
  • Settings only if IIC supports Wakeup from stop mode.
    • Wake-up - The module can wake-up from low power mode.
  • Settings for HC08 LD64 BD48 derivatives.
    • DDC2BI protocol support - Enables / disables support for DDC2BI protocol (second slave address). The property is available only if DDC12AB is selected as the I2C channel.
      The following items are available only if the group is enabled (the value is "Enabled"):
  • Initialization - Initial settings (after power-on or reset).
  • CPU clock/speed selection - Settings for the CPU speed modes: identifies whether the component is supported or not

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