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Component
InternalI2C
Internal I2C Communication Interface
Component Level: High
Category:
CPU Internal Peripherals-Communication
This component encapsulates the internal I2C communication interface. The implementation of the
interface is based on the Philips I2C-bus specification. Interface features:
MASTER mode
NOTE: I2C bus lines are open collector (open drain), therefore a pull-up resistor is necessary on both lines.
MASTER mode
- Multi master communication
- The combined format of communication possible (see "Automatic stop condition" property)
- 7-bit and 10-bit (if supported by HW) slave addressing
- Acknowledge polling provided
- Holding of the SCL line low by slave device is recognized as 'bus busy'
- Lost of arbitration and no-ACK detected
- 7-bit and 10-bit (if supported by HW) slave addressing
- General call address detection provided
NOTE: I2C bus lines are open collector (open drain), therefore a pull-up resistor is necessary on both lines.
Version specific information for HCS08 and ColdFire V1 derivatives:
After reset value of IO pin features "Drive strength" and "Slew rate" (some HCS08 derivatives - Drive strenght = Low and Slew rate = yes) may affect the output signal so, that communication is unreliable or does not work at all depending on a characteristics of the circuitry connected to the pin. It is possible to change these features in Component Inspector of the CPU component -> Internal peripherals -> I/O module.
After reset value of IO pin features "Drive strength" and "Slew rate" (some HCS08 derivatives - Drive strenght = Low and Slew rate = yes) may affect the output signal so, that communication is unreliable or does not work at all depending on a characteristics of the circuitry connected to the pin. It is possible to change these features in Component Inspector of the CPU component -> Internal peripherals -> I/O module.
Version specific information for HCS08 and ColdFire V1 derivatives and peripherals supporting 10-bit addressing feature:
If 10-bit addressing feature is used and the component is set to the SLAVE mode, data values that agrees to the mask '11110xxx' cannot be transmitted/received. These values are reserved for address transmission.
When the SLAVE is about to transmit data using 10-bit addresing mode, both OnWriteReq and OnReadReq occurs. First OnWriteReq event is called after 10-bit address transmission, then after repeat start and high address byte transmission OnReadReq event comes and data are read out from SLAVE (SLAVE sends data). When the SLAVE is about to receive data, only OnWriteReq event occurs.
If 10-bit addressing feature is used and the component is set to the SLAVE mode, data values that agrees to the mask '11110xxx' cannot be transmitted/received. These values are reserved for address transmission.
When the SLAVE is about to transmit data using 10-bit addresing mode, both OnWriteReq and OnReadReq occurs. First OnWriteReq event is called after 10-bit address transmission, then after repeat start and high address byte transmission OnReadReq event comes and data are read out from SLAVE (SLAVE sends data). When the SLAVE is about to receive data, only OnWriteReq event occurs.
Version specific information for HC08 derivatives:
OnByteTransfer event is not invoked in MASTER receive mode after address tranmission, because MCU does not support this feature. The event is invoked only after a byte transmission or reception.
OnByteTransfer event is not invoked in MASTER receive mode after address tranmission, because MCU does not support this feature. The event is invoked only after a byte transmission or reception.