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This special component implements a pulse-width modulation (PWM) generator with binary rate multiplier (BRM). Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and the N is the content of the 3-bit BRM portion.
Examples of generated signal:
Embedded Bean specific for Freescale HC08 family SR12 derivative
This special component implements a pulse-width modulation (PWM) generator with three 8-bit channels.
The automatic phase control feature allows phase delays between the channels.
When automatic phase control is enabled, the PWM channel 2 will start immediately,
but the channel 1 and channel 0 will be held in zero. After the counter of channel 2 reaches
the phase value, the counter of channel 1 is released and starts counting. Finally, when the
counter of channel 1 reaches the phase value, channel 0 is released and starts counting.
It is possible to change the phase value for the channel 0 when the channel 1 has
started its operation, before start of
the channel 0 (use method SetPhaseReg).
Examples of generated signal:
