RV64I Core (ABI) Core integer registers 64 RW unsigned long long pc Program counter 0x1080 x0 zero zero zero 0x1000 x1 ra ra return address 0x1001 x2 sp sp Stack pointer 0x1002 x3 gp gp Global pointer 0x1003 x4 tp tp Thread pointer 0x1004 x10 a0 a0 Function argument / return value register 0 0x100A x11 a1 a1 Function argument / return value register 1 0x100B x12 a2 a2 Function argument register 2 0x100C x13 a3 a3 Function argument register 3 0x100D x14 a4 a4 Function argument register 4 0x100E x15 a5 a5 Function argument register 5 0x100F x16 a6 a6 Function argument register 6 0x1010 x17 a7 a7 Function argument register 7 0x1011 x5 t0 t0 Temporary register 0 0x1005 x6 t1 t1 Temporary register 1 0x1006 x7 t2 t2 Temporary register 2 0x1007 x28 t3 t3 Temporary register 3 0x101C x29 t4 t4 Temporary register 4 0x101D x30 t5 t5 Temporary register 5 0x101E x31 t6 t6 Temporary register 6 0x101F x8 s0 s0 Frame pointer 0x1008 x9 s1 s1 Saved register 1 0x1009 x18 s2 s2 Saved register 2 0x1012 x19 s3 s3 Saved register 3 0x1013 x20 s4 s4 Saved register 4 0x1014 x21 s5 s5 Saved register 5 0x1015 x22 s6 s6 Saved register 6 0x1016 x23 s7 s7 Saved register 7 0x1017 x24 s8 s8 Saved register 8 0x1018 x25 s9 s9 Saved register 9 0x1019 x26 s10 s10 Saved register 10 0x101A x27 s11 s11 Saved register 11 0x101B Core (Numerical) Core integer registers 64 RW unsigned long long pc Program counter 0x1080 x0 zero zero 0x1000 x1 ra return address 0x1001 x2 sp Stack pointer 0x1002 x3 gp Global pointer 0x1003 x4 tp Thread pointer 0x1004 x5 t0 Temporary register 0 0x1005 x6 t1 Temporary register 1 0x1006 x7 t2 Temporary register 2 0x1007 x8 fp Frame pointer 0x1008 x9 s1 Saved register 1 0x1009 x10 a0 Function argument / return value register 0 0x100A x11 a1 Function argument / return value register 1 0x100B x12 a2 Function argument register 2 0x100C x13 a3 Function argument register 3 0x100D x14 a4 Function argument register 4 0x100E x15 a5 Function argument register 5 0x100F x16 a6 Function argument register 6 0x1010 x17 a7 Function argument register 7 0x1011 x18 s2 Saved register 2 0x1012 x19 s3 Saved register 3 0x1013 x20 s4 Saved register 4 0x1014 x21 s5 Saved register 5 0x1015 x22 s6 Saved register 6 0x1016 x23 s7 Saved register 7 0x1017 x24 s8 Saved register 8 0x1018 x25 s9 Saved register 9 0x1019 x26 s10 Saved register 10 0x101A x27 s11 Saved register 11 0x101B x28 t3 Temporary register 3 0x101C x29 t4 Temporary register 4 0x101D x30 t5 Temporary register 5 0x101E x31 t6 Temporary register 6 0x101F Machine Information Registers Machine Information Registers 64 RW unsigned long long mvendorid Vendor ID register 0xF11 marchid Architecture ID register 0xF12 mimpid Implementation ID register 0xF13 mhartid Hardware thread ID register 0xF14 Machine Trap Setup Machine Trap Setup Registers 64 RW unsigned long long mstatus Machine status register 0x300 UIE Interrupt enable, user mode [0:0] SIE Interrupt enable, supervisor mode [1:1] MIE Interrupt enable, machine mode [3:3] UPIE Interrupt enable prior to trap, user mode [4:4] SPIE Interrupt enable prior to trap, supervisor mode [5:5] MPIE Interrupt enable prior to trap, machine mode [7:7] SPP Previous priviledge level, supervisor mode [8:8] MPP Previous priviledge level, machine mode [12:11] FS Floating point unit status [14:13] Off 0 Initial 1 Clean 2 Dirty 3 XS Status of user mode extensions [16:15] Off 0 Initial 1 Clean 2 Dirty 3 MPRV Modify priviledge bits [17:17] SUM Permit supervisor memory access [18:18] MXR Make executable readable [19:19] TVM Trap virtual memory [20:20] TW Timeout wait [21:21] TSR Trap SRET instruction [22:22] SD Extended user context save required [31:31] misa Machine ISA register 0x301 A Atomic instruction extension implemented [0:0] C Compressed instruction extension implemented [2:2] D Double-precision floating point extension implemented [3:3] E Reduced integer ISA for embedded systems implemented [4:4] F Single-precision floating point extension implemented [5:5] G IMAFD extensions implemented [6:6] I Base integer ISA implemented [8:8] M Integer multiply and divide extension implemented [12:12] N User level interrupts extension implemented [13:13] Q Quad-precision floating point extension implemented [16:16] S Supervisor priviledge level implemented [18:18] U User priviledge level implemented [20:20] X Non-standard extension present [23:23] MXL Machine XLEN [31:30] 32 bit 1 64 bit 2 128 bit 3 medeleg Machine exception delegetion register 0x302 mideleg Machine interrupt delegation register 0x303 mie Machine interrupt enable register 0x304 USIE Interupt delegation to supervisor enable [0:0] SSIE Interupt delegation to supervisor enable [1:1] MSIE Interupt delegation to supervisor enable [3:3] UTIE User timer interrupt enable [4:4] STIE Supervisor timer interrupt enable [5:5] MTIE Machine timer interrupt enable [7:7] UEIE User external interrupt enable [8:8] SEIE Supervisor external interrupt enable [9:9] MEIE Machine external interrupt enable [11:11] mtvec Machine trap vector base address register 0x305 mcounteren 32 unsigned int Machine counter enable register 0x306 Machine Trap Handling Machine Trap Handling Registers 64 RW unsigned long long mscratch Machine scratch register 0x340 mepc Machine exception program counter 0x341 mcause Machine trap cause register 0x342 Cause Cause bit [31:31] Cause=Exception 0 Cause=Interrupt 1 Exception Exception Code [30:0] Instruction address misaligned 0 Instruction access fault 1 Illegal instruction 2 Breakpoint 3 Load address misaligned 4 Load access fault 5 Store/AMO address misaligned 6 Store/AMO access fault 7 Environment call from user mode 8 Environment call from supervisor mode 9 Environment call from machine mode 11 Instruction page fault 12 Load page fault 13 Store/AMO page fault 15 Interrupt Interrupt Code [30:0] User software interrupt 0 Supervisor software interrupt 1 Machine software interrupt 3 User timer interrupt 4 Supervisor timer interrupt 5 Machine timer interrupt 7 User external interrupt 8 Supervisor external interrupt 9 Machine external interrupt 11 mtval Machine trap value register 0x343 mip Machine interrupt pending register 0x344 USIP Interupt delegation to supervisor pending (U-Mode) [0:0] SSIP Interupt delegation to supervisor pending (S-Mode) [1:1] MSIP Interupt delegation to supervisor pending (M-Mode) [3:3] UTIP User timer interrupt pending [4:4] STIP Supervisor timer interrupt pending [5:5] MTIP Machine timer interrupt pending [7:7] UEIP User external interrupt pending [8:8] SEIP Supervisor external interrupt pending [9:9] MEIP Machine external interrupt pending [11:11] Machine Protection and Translation Machine Protection and translation registers 64 RW unsigned long long pmpcfg0 32 unsigned int Physical memory protection configuration register 0 0x3A0 pmpcfg1 32 unsigned int Physical memory protection configuration register 1 0x3A1 pmpcfg2 32 unsigned int Physical memory protection configuration register 2 0x3A2 pmpcfg3 32 unsigned int Physical memory protection configuration register 3 0x3A3 pmpaddr0 Physical memory protection address register 0 0x3B0 pmpaddr1 Physical memory protection address register 1 0x3B1 pmpaddr2 Physical memory protection address register 1 0x3B2 pmpaddr3 Physical memory protection address register 1 0x3B3 pmpaddr4 Physical memory protection address register 1 0x3B4 pmpaddr5 Physical memory protection address register 1 0x3B5 pmpaddr6 Physical memory protection address register 1 0x3B6 pmpaddr7 Physical memory protection address register 1 0x3B7 pmpaddr8 Physical memory protection address register 1 0x3B8 pmpaddr9 Physical memory protection address register 1 0x3B9 pmpaddr10 Physical memory protection address register 1 0x3BA pmpaddr11 Physical memory protection address register 1 0x3BB pmpaddr12 Physical memory protection address register 1 0x3BC pmpaddr13 Physical memory protection address register 1 0x3BD pmpaddr14 Physical memory protection address register 1 0x3BE pmpaddr15 Physical memory protection address register 1 0x3BF Machine Counters/Timers Machine counter and timer registers 64 RW unsigned long long mcycle Cycle counter 0xB00 minstret Number of instructions retired 0xB02 mhpmcounter3 Event counter register 3 0xB03 mhpmcounter4 Event counter register 4 0xB04 mhpmcounter5 Event counter register 5 0xB05 mhpmcounter6 Event counter register 6 0xB06 mhpmcounter7 Event counter register 7 0xB07 mhpmcounter8 Event counter register 8 0xB08 mhpmcounter9 Event counter register 9 0xB09 mhpmcounter10 Event counter register 10 0xB0A mhpmcounter11 Event counter register 11 0xB0B mhpmcounter12 Event counter register 12 0xB0C mhpmcounter13 Event counter register 13 0xB0D mhpmcounter14 Event counter register 14 0xB0E mhpmcounter15 Event counter register 15 0xB0F mhpmcounter16 Event counter register 16 0xB10 mhpmcounter17 Event counter register 17 0xB11 mhpmcounter18 Event counter register 18 0xB12 mhpmcounter19 Event counter register 19 0xB13 mhpmcounter20 Event counter register 20 0xB14 mhpmcounter21 Event counter register 21 0xB15 mhpmcounter22 Event counter register 22 0xB16 mhpmcounter23 Event counter register 23 0xB17 mhpmcounter24 Event counter register 24 0xB18 mhpmcounter25 Event counter register 25 0xB19 mhpmcounter26 Event counter register 26 0xB1A mhpmcounter27 Event counter register 27 0xB1B mhpmcounter28 Event counter register 28 0xB1C mhpmcounter29 Event counter register 29 0xB1D mhpmcounter30 Event counter register 30 0xB1E mhpmcounter31 Event counter register 31 0xB1F User Counters/Timers User counter and timer registers 64 RW unsigned long long cycle Cycle counter 0xC00 time Number of instructions retired 0xC01 instret Number of instructions retired 0xC02 hpmcounter3 Event counter register 3 0xC03 hpmcounter4 Event counter register 4 0xC04 hpmcounter5 Event counter register 5 0xC05 hpmcounter6 Event counter register 6 0xC06 hpmcounter7 Event counter register 7 0xC07 hpmcounter8 Event counter register 8 0xC08 hpmcounter9 Event counter register 9 0xC09 hpmcounter10 Event counter register 10 0xC0A hpmcounter11 Event counter register 11 0xC0B hpmcounter12 Event counter register 12 0xC0C hpmcounter13 Event counter register 13 0xC0D hpmcounter14 Event counter register 14 0xC0E hpmcounter15 Event counter register 15 0xC0F hpmcounter16 Event counter register 16 0xC10 hpmcounter17 Event counter register 17 0xC11 hpmcounter18 Event counter register 18 0xC12 hpmcounter19 Event counter register 19 0xC13 hpmcounter20 Event counter register 20 0xC14 hpmcounter21 Event counter register 21 0xC15 hpmcounter22 Event counter register 22 0xC16 hpmcounter23 Event counter register 23 0xC17 hpmcounter24 Event counter register 24 0xC18 hpmcounter25 Event counter register 25 0xC19 hpmcounter26 Event counter register 26 0xC1A hpmcounter27 Event counter register 27 0xC1B hpmcounter28 Event counter register 28 0xC1C hpmcounter29 Event counter register 29 0xC1D hpmcounter30 Event counter register 30 0xC1E hpmcounter31 Event counter register 31 0xC1F