RV32EFD Core (ABI) Core integer registers 32 RW unsigned int pc Program counter 0x1080 x0 zero zero General purpose register 0 (zero) 0x1000 x1 ra ra General purpose register 1 (return address) 0x1001 x2 sp sp General purpose register 2 (Stack pointer) 0x1002 x3 gp gp General purpose register 3 (Global pointer) 0x1003 x4 tp tp General purpose register 4 (Thread pointer) 0x1004 x10 a0 a0 General purpose register 10 (Function argument / return value register 0) 0x100A x11 a1 a1 General purpose register 11 (Function argument / return value register 1) 0x100B x12 a2 a2 General purpose register 12 (Function argument register 2) 0x100C x13 a3 a3 General purpose register 13 (Function argument register 3) 0x100D x14 a4 a4 General purpose register 14 (Function argument register 4) 0x100E x15 a5 a5 General purpose register 15 (Function argument register 5) 0x100F x5 t0 t0 General purpose register 5 (Temporary register 0) 0x1005 x6 t1 t1 General purpose register 6 (Temporary register 1) 0x1006 x7 t2 t2 General purpose register 7 (Temporary register 2) 0x1007 x8 s0 s0 General purpose register 8 (Frame pointer) 0x1008 x9 s1 s1 General purpose register 9 (Saved register 1) 0x1009 Core (Numerical) Core integer registers 32 RW unsigned int pc Program counter 0x1080 x0 zero zero 0x1000 x1 ra return address 0x1001 x2 sp Stack pointer 0x1002 x3 gp Global pointer 0x1003 x4 tp Thread pointer 0x1004 x5 t0 Temporary register 0 0x1005 x6 t1 Temporary register 1 0x1006 x7 t2 Temporary register 2 0x1007 x8 fp Frame pointer 0x1008 x9 s1 Saved register 1 0x1009 x10 a0 Function argument / return value register 0 0x100A x11 a1 Function argument / return value register 1 0x100B x12 a2 Function argument register 2 0x100C x13 a3 Function argument register 3 0x100D x14 a4 Function argument register 4 0x100E x15 a5 Function argument register 5 0x100F FPU 32 (ABI) Single-precision floating point registers 32 RW float f10 fa0 fa0 Floating point argument/return value register 0 0x102A f11 fa1 fa1 Floating point argument/return value register 1 0x102B f12 fa2 fa2 Floating point argument register 2 0x102C f13 fa3 fa3 Floating point argument register 3 0x102D f14 fa4 fa4 Floating point argument register 4 0x102E f15 fa5 fa5 Floating point argument register 5 0x102F f16 fa6 fa6 Floating point argument register 6 0x1030 f17 fa7 fa7 Floating point argument register 7 0x1031 f0 ft0 ft0 Floating point temporary register 0 0x1020 f1 ft1 ft1 Floating point temporary register 1 0x1021 f2 ft2 ft2 Floating point temporary register 2 0x1022 f3 ft3 ft3 Floating point temporary register 3 0x1023 f4 ft4 ft4 Floating point temporary register 4 0x1024 f5 ft5 ft5 Floating point temporary register 5 0x1025 f6 ft6 ft6 Floating point temporary register 6 0x1026 f7 ft7 ft7 Floating point temporary register 7 0x1027 f28 ft8 ft8 Floating point temporary register 8 0x103C f29 ft9 ft9 Floating point temporary register 9 0x103D f30 ft10 ft10 Floating point temporary register 10 0x103E f31 ft11 ft11 Floating point temporary register 11 0x103F f8 fs0 fs0 Floating point saved register 0 0x1028 f9 fs1 fs1 Floating point saved register 1 0x1029 f18 fs2 fs2 Floating point saved register 2 0x1032 f19 fs3 fs3 Floating point saved register 3 0x1033 f20 fs4 fs4 Floating point saved register 4 0x1034 f21 fs5 fs5 Floating point saved register 5 0x1035 f22 fs6 fs6 Floating point saved register 6 0x1036 f23 fs7 fs7 Floating point saved register 7 0x1037 f24 fs8 fs8 Floating point saved register 8 0x1038 f25 fs9 fs9 Floating point saved register 9 0x1039 f26 fs10 fs10 Floating point saved register 10 0x103A f27 fs11 fs11 Floating point saved register 11 0x103B fcsr Floating point control and status register 0x3 NX Inexact [0:0] UF Underflow [1:1] OF Overflow [2:2] DZ Divide by zero [3:3] NV Invalid Operation [4:4] FRM Rounding Mode [7:5] Round to nearest, ties to even 0 Round towards zero 1 Round down 2 Round up 3 Round to nearest, ties to max. magnitude 4 FPU 32 (Numerical) Single-precision floating point registers 32 RW float f0 ft0 Floating point temporary register 0 0x1020 f1 ft1 Floating point temporary register 1 0x1021 f2 ft2 Floating point temporary register 2 0x1022 f3 ft3 Floating point temporary register 3 0x1023 f4 ft4 Floating point temporary register 4 0x1024 f5 ft5 Floating point temporary register 5 0x1025 f6 ft6 Floating point temporary register 6 0x1026 f7 ft7 Floating point temporary register 7 0x1027 f8 fs0 Floating point saved register 0 0x1028 f9 fs1 Floating point saved register 1 0x1029 f10 fa0 Floating point argument/return value register 0 0x102A f11 fa1 Floating point argument/return value register 1 0x102B f12 fa2 Floating point argument register 2 0x102C f13 fa3 Floating point argument register 3 0x102D f14 fa4 Floating point argument register 4 0x102E f15 fa5 Floating point argument register 5 0x102F f16 fa6 Floating point argument register 6 0x1030 f17 fa7 Floating point argument register 7 0x1031 f18 fs2 Floating point saved register 2 0x1032 f19 fs3 Floating point saved register 3 0x1033 f20 fs4 Floating point saved register 4 0x1034 f21 fs5 Floating point saved register 5 0x1035 f22 fs6 Floating point saved register 6 0x1036 f23 fs7 Floating point saved register 7 0x1037 f24 fs8 Floating point saved register 8 0x1038 f25 fs9 Floating point saved register 9 0x1039 f26 fs10 Floating point saved register 10 0x103A f27 fs11 Floating point saved register 11 0x103B f28 ft8 Floating point temporary register 8 0x103C f29 ft9 Floating point temporary register 9 0x103D f30 ft10 Floating point temporary register 10 0x103E f31 ft11 Floating point temporary register 11 0x103F fcsr Floating point control and status register 0x3 NX Inexact [0:0] UF Underflow [1:1] OF Overflow [2:2] DZ Divide by zero [3:3] NV Invalid Operation [4:4] FRM Rounding Mode [7:5] Round to nearest, ties to even 0 Round towards zero 1 Round down 2 Round up 3 Round to nearest, ties to max. magnitude 4 FPU 64 (ABI) Double-precision floating point registers 64 RW double f10 fa0 fa0 Floating point argument/return value register 0 0x102A f11 fa1 fa1 Floating point argument/return value register 1 0x102B f12 fa2 fa2 Floating point argument register 2 0x102C f13 fa3 fa3 Floating point argument register 3 0x102D f14 fa4 fa4 Floating point argument register 4 0x102E f15 fa5 fa5 Floating point argument register 5 0x102F f16 fa6 fa6 Floating point argument register 6 0x1030 f17 fa7 fa7 Floating point argument register 7 0x1031 f0 ft0 ft0 Floating point temporary register 0 0x1020 f1 ft1 ft1 Floating point temporary register 1 0x1021 f2 ft2 ft2 Floating point temporary register 2 0x1022 f3 ft3 ft3 Floating point temporary register 3 0x1023 f4 ft4 ft4 Floating point temporary register 4 0x1024 f5 ft5 ft5 Floating point temporary register 5 0x1025 f6 ft6 ft6 Floating point temporary register 6 0x1026 f7 ft7 ft7 Floating point temporary register 7 0x1027 f28 ft8 ft8 Floating point temporary register 8 0x103C f29 ft9 ft9 Floating point temporary register 9 0x103D f30 ft10 ft10 Floating point temporary register 10 0x103E f31 ft11 ft11 Floating point temporary register 11 0x103F f8 fs0 fs0 Floating point saved register 0 0x1028 f9 fs1 fs1 Floating point saved register 1 0x1029 f18 fs2 fs2 Floating point saved register 2 0x1032 f19 fs3 fs3 Floating point saved register 3 0x1033 f20 fs4 fs4 Floating point saved register 4 0x1034 f21 fs5 fs5 Floating point saved register 5 0x1035 f22 fs6 fs6 Floating point saved register 6 0x1036 f23 fs7 fs7 Floating point saved register 7 0x1037 f24 fs8 fs8 Floating point saved register 8 0x1038 f25 fs9 fs9 Floating point saved register 9 0x1039 f26 fs10 fs10 Floating point saved register 10 0x103A f27 fs11 fs11 Floating point saved register 11 0x103B fcsr Floating point control and status register 32 0x3 NX Inexact [0:0] UF Underflow [1:1] OF Overflow [2:2] DZ Divide by zero [3:3] NV Invalid Operation [4:4] FRM Rounding Mode [7:5] Round to nearest, ties to even 0 Round towards zero 1 Round down 2 Round up 3 Round to nearest, ties to max. magnitude 4 FPU 64 (Numerical) Double-precision floating point registers 64 RW double f0 ft0 Floating point temporary register 0 0x1020 f1 ft1 Floating point temporary register 1 0x1021 f2 ft2 Floating point temporary register 2 0x1022 f3 ft3 Floating point temporary register 3 0x1023 f4 ft4 Floating point temporary register 4 0x1024 f5 ft5 Floating point temporary register 5 0x1025 f6 ft6 Floating point temporary register 6 0x1026 f7 ft7 Floating point temporary register 7 0x1027 f8 fs0 Floating point saved register 0 0x1028 f9 fs1 Floating point saved register 1 0x1029 f10 fa0 Floating point argument/return value register 0 0x102A f11 fa1 Floating point argument/return value register 1 0x102B f12 fa2 Floating point argument register 2 0x102C f13 fa3 Floating point argument register 3 0x102D f14 fa4 Floating point argument register 4 0x102E f15 fa5 Floating point argument register 5 0x102F f16 fa6 Floating point argument register 6 0x1030 f17 fa7 Floating point argument register 7 0x1031 f18 fs2 Floating point saved register 2 0x1032 f19 fs3 Floating point saved register 3 0x1033 f20 fs4 Floating point saved register 4 0x1034 f21 fs5 Floating point saved register 5 0x1035 f22 fs6 Floating point saved register 6 0x1036 f23 fs7 Floating point saved register 7 0x1037 f24 fs8 Floating point saved register 8 0x1038 f25 fs9 Floating point saved register 9 0x1039 f26 fs10 Floating point saved register 10 0x103A f27 fs11 Floating point saved register 11 0x103B f28 ft8 Floating point temporary register 8 0x103C f29 ft9 Floating point temporary register 9 0x103D f30 ft10 Floating point temporary register 10 0x103E f31 ft11 Floating point temporary register 11 0x103F fcsr Floating point control and status register 32 0x3 NX Inexact [0:0] UF Underflow [1:1] OF Overflow [2:2] DZ Divide by zero [3:3] NV Invalid Operation [4:4] FRM Rounding Mode [7:5] Round to nearest, ties to even 0 Round towards zero 1 Round down 2 Round up 3 Round to nearest, ties to max. magnitude 4 Machine Information Registers Machine Information Registers 32 RW unsigned int mvendorid Vendor ID register 0xF11 marchid Architecture ID register 0xF12 mimpid Implementation ID register 0xF13 mhartid Hardware thread ID register 0xF14 Machine Trap Setup Machine Trap Setup Registers 32 RW unsigned int mstatus Machine status register 0x300 UIE Interrupt enable, user mode [0:0] SIE Interrupt enable, supervisor mode [1:1] MIE Interrupt enable, machine mode [3:3] UPIE Interrupt enable prior to trap, user mode [4:4] SPIE Interrupt enable prior to trap, supervisor mode [5:5] MPIE Interrupt enable prior to trap, machine mode [7:7] SPP Previous priviledge level, supervisor mode [8:8] MPP Previous priviledge level, machine mode [12:11] FS Floating point unit status [14:13] Off 0 Initial 1 Clean 2 Dirty 3 XS Status of user mode extensions [16:15] Off 0 Initial 1 Clean 2 Dirty 3 MPRV Modify priviledge bits [17:17] SUM Permit supervisor memory access [18:18] MXR Make executable readable [19:19] TVM Trap virtual memory [20:20] TW Timeout wait [21:21] TSR Trap SRET instruction [22:22] SD Extended user context save required [31:31] misa Machine ISA register 0x301 A Atomic instruction extension implemented [0:0] C Compressed instruction extension implemented [2:2] D Double-precision floating point extension implemented [3:3] E Reduced integer ISA for embedded systems implemented [4:4] F Single-precision floating point extension implemented [5:5] G IMAFD extensions implemented [6:6] I Base integer ISA implemented [8:8] M Integer multiply and divide extension implemented [12:12] N User level interrupts extension implemented [13:13] Q Quad-precision floating point extension implemented [16:16] S Supervisor priviledge level implemented [18:18] U User priviledge level implemented [20:20] X Non-standard extension present [23:23] MXL Machine XLEN [31:30] 32 bit 1 64 bit 2 128 bit 3 medeleg Machine exception delegetion register 0x302 mideleg Machine interrupt delegation register 0x303 mie Machine interrupt enable register 0x304 USIE Interupt delegation to supervisor enable [0:0] SSIE Interupt delegation to supervisor enable [1:1] MSIE Interupt delegation to supervisor enable [3:3] UTIE User timer interrupt enable [4:4] STIE Supervisor timer interrupt enable [5:5] MTIE Machine timer interrupt enable [7:7] UEIE User external interrupt enable [8:8] SEIE Supervisor external interrupt enable [9:9] MEIE Machine external interrupt enable [11:11] mtvec Machine trap vector base address register 0x305 mcounteren Machine counter enable register 0x306 Machine Trap Handling Machine Trap Handling Registers 32 RW unsigned int mscratch Machine scratch register 0x340 mepc Machine exception program counter 0x341 mcause Machine trap cause register 0x342 Cause Cause bit [31:31] Cause=Exception 0 Cause=Interrupt 1 Exception Exception Code [30:0] Instruction address misaligned 0 Instruction access fault 1 Illegal instruction 2 Breakpoint 3 Load address misaligned 4 Load access fault 5 Store/AMO address misaligned 6 Store/AMO access fault 7 Environment call from user mode 8 Environment call from supervisor mode 9 Environment call from machine mode 11 Instruction page fault 12 Load page fault 13 Store/AMO page fault 15 Interrupt Interrupt Code [30:0] User software interrupt 0 Supervisor software interrupt 1 Machine software interrupt 3 User timer interrupt 4 Supervisor timer interrupt 5 Machine timer interrupt 7 User external interrupt 8 Supervisor external interrupt 9 Machine external interrupt 11 mtval Machine trap value register 0x343 mip Machine interrupt pending register 0x344 USIP Interupt delegation to supervisor pending (U-Mode) [0:0] SSIP Interupt delegation to supervisor pending (S-Mode) [1:1] MSIP Interupt delegation to supervisor pending (M-Mode) [3:3] UTIP User timer interrupt pending [4:4] STIP Supervisor timer interrupt pending [5:5] MTIP Machine timer interrupt pending [7:7] UEIP User external interrupt pending [8:8] SEIP Supervisor external interrupt pending [9:9] MEIP Machine external interrupt pending [11:11] Machine Protection and Translation Machine Protection and translation registers 32 RW unsigned int pmpcfg0 Physical memory protection configuration register 0 0x3A0 pmpcfg1 Physical memory protection configuration register 1 0x3A1 pmpcfg2 Physical memory protection configuration register 2 0x3A2 pmpcfg3 Physical memory protection configuration register 3 0x3A3 pmpaddr0 Physical memory protection address register 0 0x3B0 pmpaddr1 Physical memory protection address register 1 0x3B1 pmpaddr2 Physical memory protection address register 1 0x3B2 pmpaddr3 Physical memory protection address register 1 0x3B3 pmpaddr4 Physical memory protection address register 1 0x3B4 pmpaddr5 Physical memory protection address register 1 0x3B5 pmpaddr6 Physical memory protection address register 1 0x3B6 pmpaddr7 Physical memory protection address register 1 0x3B7 pmpaddr8 Physical memory protection address register 1 0x3B8 pmpaddr9 Physical memory protection address register 1 0x3B9 pmpaddr10 Physical memory protection address register 1 0x3BA pmpaddr11 Physical memory protection address register 1 0x3BB pmpaddr12 Physical memory protection address register 1 0x3BC pmpaddr13 Physical memory protection address register 1 0x3BD pmpaddr14 Physical memory protection address register 1 0x3BE pmpaddr15 Physical memory protection address register 1 0x3BF Machine Counters/Timers Machine counter and timer registers 32 RW unsigned int mcycle Cycle counter 0xB00 minstret Number of instructions retired 0xB02 mhpmcounter3 Event counter register 3 0xB03 mhpmcounter4 Event counter register 4 0xB04 mhpmcounter5 Event counter register 5 0xB05 mhpmcounter6 Event counter register 6 0xB06 mhpmcounter7 Event counter register 7 0xB07 mhpmcounter8 Event counter register 8 0xB08 mhpmcounter9 Event counter register 9 0xB09 mhpmcounter10 Event counter register 10 0xB0A mhpmcounter11 Event counter register 11 0xB0B mhpmcounter12 Event counter register 12 0xB0C mhpmcounter13 Event counter register 13 0xB0D mhpmcounter14 Event counter register 14 0xB0E mhpmcounter15 Event counter register 15 0xB0F mhpmcounter16 Event counter register 16 0xB10 mhpmcounter17 Event counter register 17 0xB11 mhpmcounter18 Event counter register 18 0xB12 mhpmcounter19 Event counter register 19 0xB13 mhpmcounter20 Event counter register 20 0xB14 mhpmcounter21 Event counter register 21 0xB15 mhpmcounter22 Event counter register 22 0xB16 mhpmcounter23 Event counter register 23 0xB17 mhpmcounter24 Event counter register 24 0xB18 mhpmcounter25 Event counter register 25 0xB19 mhpmcounter26 Event counter register 26 0xB1A mhpmcounter27 Event counter register 27 0xB1B mhpmcounter28 Event counter register 28 0xB1C mhpmcounter29 Event counter register 29 0xB1D mhpmcounter30 Event counter register 30 0xB1E mhpmcounter31 Event counter register 31 0xB1F mcycleh Cycle counter, high bits 0xB80 minstreth Number of instructions retired, high bits 0xB82 mhpmcounter3h Event counter register 3, high bits 0xB03 mhpmcounter4h Event counter register 4, high bits 0xB04 mhpmcounter5h Event counter register 5, high bits 0xB05 mhpmcounter6h Event counter register 6, high bits 0xB06 mhpmcounter7h Event counter register 7, high bits 0xB07 mhpmcounter8h Event counter register 8, high bits 0xB08 mhpmcounter9h Event counter register 9, high bits 0xB09 mhpmcounter10h Event counter register 10, high bits 0xB0A mhpmcounter11h Event counter register 11, high bits 0xB0B mhpmcounter12h Event counter register 12, high bits 0xB0C mhpmcounter13h Event counter register 13, high bits 0xB0D mhpmcounter14h Event counter register 14, high bits 0xB0E mhpmcounter15h Event counter register 15, high bits 0xB0F mhpmcounter16h Event counter register 16, high bits 0xB10 mhpmcounter17h Event counter register 17, high bits 0xB11 mhpmcounter18h Event counter register 18, high bits 0xB12 mhpmcounter19h Event counter register 19, high bits 0xB13 mhpmcounter20h Event counter register 20, high bits 0xB14 mhpmcounter21h Event counter register 21, high bits 0xB15 mhpmcounter22h Event counter register 22, high bits 0xB16 mhpmcounter23h Event counter register 23, high bits 0xB17 mhpmcounter24h Event counter register 24, high bits 0xB18 mhpmcounter25h Event counter register 25, high bits 0xB19 mhpmcounter26h Event counter register 26, high bits 0xB1A mhpmcounter27h Event counter register 27, high bits 0xB1B mhpmcounter28h Event counter register 28, high bits 0xB1C mhpmcounter29h Event counter register 29, high bits 0xB1D mhpmcounter30h Event counter register 30, high bits 0xB1E mhpmcounter31h Event counter register 31, high bits 0xB1F User Counters/Timers User counter and timer registers 32 RW unsigned int cycle Cycle counter 0xC00 time Number of instructions retired 0xC01 instret Number of instructions retired 0xC02 hpmcounter3 Event counter register 3 0xC03 hpmcounter4 Event counter register 4 0xC04 hpmcounter5 Event counter register 5 0xC05 hpmcounter6 Event counter register 6 0xC06 hpmcounter7 Event counter register 7 0xC07 hpmcounter8 Event counter register 8 0xC08 hpmcounter9 Event counter register 9 0xC09 hpmcounter10 Event counter register 10 0xC0A hpmcounter11 Event counter register 11 0xC0B hpmcounter12 Event counter register 12 0xC0C hpmcounter13 Event counter register 13 0xC0D hpmcounter14 Event counter register 14 0xC0E hpmcounter15 Event counter register 15 0xC0F hpmcounter16 Event counter register 16 0xC10 hpmcounter17 Event counter register 17 0xC11 hpmcounter18 Event counter register 18 0xC12 hpmcounter19 Event counter register 19 0xC13 hpmcounter20 Event counter register 20 0xC14 hpmcounter21 Event counter register 21 0xC15 hpmcounter22 Event counter register 22 0xC16 hpmcounter23 Event counter register 23 0xC17 hpmcounter24 Event counter register 24 0xC18 hpmcounter25 Event counter register 25 0xC19 hpmcounter26 Event counter register 26 0xC1A hpmcounter27 Event counter register 27 0xC1B hpmcounter28 Event counter register 28 0xC1C hpmcounter29 Event counter register 29 0xC1D hpmcounter30 Event counter register 30 0xC1E hpmcounter31 Event counter register 31 0xC1F cycleh Cycle counter, high bits 0xC80 timeh Time, high bits 0xC81 instreth Number of instructions retired, high bits 0xC82 hpmcounter3h Event counter register 3, high bits 0xC03 hpmcounter4h Event counter register 4, high bits 0xC04 hpmcounter5h Event counter register 5, high bits 0xC05 hpmcounter6h Event counter register 6, high bits 0xC06 hpmcounter7h Event counter register 7, high bits 0xC07 hpmcounter8h Event counter register 8, high bits 0xC08 hpmcounter9h Event counter register 9, high bits 0xC09 hpmcounter10h Event counter register 10, high bits 0xC0A hpmcounter11h Event counter register 11, high bits 0xC0B hpmcounter12h Event counter register 12, high bits 0xC0C hpmcounter13h Event counter register 13, high bits 0xC0D hpmcounter14h Event counter register 14, high bits 0xC0E hpmcounter15h Event counter register 15, high bits 0xC0F hpmcounter16h Event counter register 16, high bits 0xC10 hpmcounter17h Event counter register 17, high bits 0xC11 hpmcounter18h Event counter register 18, high bits 0xC12 hpmcounter19h Event counter register 19, high bits 0xC13 hpmcounter20h Event counter register 20, high bits 0xC14 hpmcounter21h Event counter register 21, high bits 0xC15 hpmcounter22h Event counter register 22, high bits 0xC16 hpmcounter23h Event counter register 23, high bits 0xC17 hpmcounter24h Event counter register 24, high bits 0xC18 hpmcounter25h Event counter register 25, high bits 0xC19 hpmcounter26h Event counter register 26, high bits 0xC1A hpmcounter27h Event counter register 27, high bits 0xC1B hpmcounter28h Event counter register 28, high bits 0xC1C hpmcounter29h Event counter register 29, high bits 0xC1D hpmcounter30h Event counter register 30, high bits 0xC1E hpmcounter31h Event counter register 31, high bits 0xC1F