CR5_D16 Cortex-R5 (D16) State Current CPU State 1 Core (Now) Current State CPU Registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 74 R9 General purpose register 9 75 R10 General purpose register 10 76 R11 General purpose register 11 77 R12 General purpose register 12 78 R13 SP R13 (SP) Stack pointer (SP) 79 R14 LR R14 (LR) Link register (LR) 80 R15 PC R15 (PC) Program counter (PC) 9 CPSR Current program status register 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 FPU Floating Point Registers 32 RW float S0 Floating point register 0 40 S1 Floating point register 1 41 S2 Floating point register 2 42 S3 Floating point register 3 43 S4 Floating point register 4 44 S5 Floating point register 5 45 S6 Floating point register 6 46 S7 Floating point register 7 47 S8 Floating point register 8 48 S9 Floating point register 9 49 S10 Floating point register 10 50 S11 Floating point register 11 51 S12 Floating point register 12 52 S13 Floating point register 13 53 S14 Floating point register 14 54 S15 Floating point register 15 55 S16 Floating point register 16 56 S17 Floating point register 17 57 S18 Floating point register 18 58 S19 Floating point register 19 59 S20 Floating point register 20 60 S21 Floating point register 21 61 S22 Floating point register 22 62 S23 Floating point register 23 63 S24 Floating point register 24 64 S25 Floating point register 25 65 S26 Floating point register 26 66 S27 Floating point register 27 67 S28 Floating point register 28 68 S29 Floating point register 29 69 S30 Floating point register 30 70 S31 Floating point register 31 71 FPSID Floating point system information register RO 0x41023150 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 0x0 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 IOE Invalid operation exception enable bit 8 1 DZE Division by zero exception enable bit 9 1 OFE Overflow exception enable bit 10 1 UFE Underflow exception enable bit 11 1 IXE Inexact exception enable bit 12 1 IDE Input Subnormal exception enable bit 15 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 QC Saturation cumulative flag 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 0x0 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 0x10110221 32 72 RB Sixteen 64-bir registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 0x00000011 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 FPU (Double) Floating Point Registers (double-precision) 64 RW double D0 Floating point register 0 40 41 D1 Floating point register 1 42 43 D2 Floating point register 2 44 45 D3 Floating point register 3 46 47 D4 Floating point register 4 48 49 D5 Floating point register 5 50 51 D6 Floating point register 6 52 53 D7 Floating point register 7 54 55 D8 Floating point register 8 56 57 D9 Floating point register 9 58 59 D10 Floating point register 10 60 61 D11 Floating point register 11 62 63 D12 Floating point register 12 64 65 D13 Floating point register 13 66 67 D14 Floating point register 14 68 69 D15 Floating point register 15 70 71 FPSID Floating point system information register RO 32 0x41023140 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 32 0x0 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 IOE Invalid operation exception enable bit 8 1 DZE Division by zero exception enable bit 9 1 OFE Overflow exception enable bit 10 1 UFE Underflow exception enable bit 11 1 IXE Inexact exception enable bit 12 1 IDE Input Subnormal exception enable bit 15 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 QC Saturation cumulative flag 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 32 0x0 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 32 0x10110221 72 RB Sixteen 64-bir registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 32 0x00000011 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 Core (All) All CPU Registers 32 RW unsigned int R0_USR General purpose register 0 (User Mode) 0 R1_USR General purpose register 1 (User Mode) 1 R2_USR General purpose register 2 (User Mode) 2 R3_USR General purpose register 3 (User Mode) 3 R4_USR General purpose register 4 (User Mode) 4 R5_USR General purpose register 5 (User Mode) 5 R6_USR General purpose register 6 (User Mode) 6 R7_USR General purpose register 7 (User Mode) 7 R8_USR General purpose register 8 (User Mode) 10 R9_USR General purpose register 9 (User Mode) 11 R10_USR General purpose register 10 (User Mode) 12 R11_USR General purpose register 11 (User Mode) 13 R12_USR General purpose register 12 (User Mode) 14 R13_USR Stack pointer (User Mode) 15 R14_USR Link register (User Mode) 16 R15_USR Program counter (User Mode) 9 SPSR_USR Current program status register (User Mode) 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R8_FIQ General purpose register 8 (Fast Interrupt Mode) 18 R9_FIQ General purpose register 9 (Fast Interrupt Mode) 19 R10_FIQ General purpose register 10 (Fast Interrupt Mode) 20 R11_FIQ General purpose register 11 (Fast Interrupt Mode) 21 R12_FIQ General purpose register 12 (Fast Interrupt Mode) 22 R13_FIQ Stack pointer (Fast Interrupt Mode) 23 R14_FIQ Link register (Fast Interrupt Mode) 24 SPSR_FIQ Current program status register (Fast Interrupt Mode) 17 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_SVC Stack pointer (Supervisor Mode) 26 R14_SVC Link register (Supervisor Mode) 27 SPSR_SVC Current program status register (Supervisor Mode) 25 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_ABT Stack pointer (Abort Mode) 29 R14_ABT Link register (Abort Mode) 30 SPSR_ABT Current program status register (Abort Mode) 28 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_IRQ Stack pointer (Interrupt Mode) 32 R14_IRQ Link register (Interrupt Mode) 33 SPSR_IRQ Current program status register (Interrupt Mode) 31 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_UND Stack pointer (Undefined Mode) 35 R14_UND Link register (Undefined Mode) 36 SPSR_UND Current program status register (Undefined Mode) 34 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Interruptible-continuable instruction bits 10 6 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 CP15 Coprocessor 15 Registers 32 RW unsigned int MIDR Main ID Register ID Regs RO 0x410FC150 15,0,0,0,0 IMPLEMENTOR Implementor 24 8 REV_MAJOR Major revision number of the rnpn revision status 20 4 ARCHITECTURE Architecture Code 16 4 PART_NBR Part number 4 12 REV_MINOR Minor revision number of the rnpn revision status 0 4 CTR Cache Type Register ID Regs RO 0x8003C003 15,0,0,0,1 CWG Cache Write-Back Granule 24 4 ERG Exclusives Reservation Granule 20 4 D_MIN_LINE Log2 of the number of words in the smalles cache line of all the data and unified caches under the core control 16 4 I_MIN_LINE Log2 of the number of words in the smallest cache line of all the instruction caches under the control of the processor 0 4 TCMTR Tightly Coupled Memory (TCM) Type Register ID Regs RO 0x00010001 15,0,0,0,2 BTCM Number of BTCMs implemented 16 3 ATCM Number of ATCMs implemented 0 3 MPUTR MPU Type Register ID Regs RO 0x00000000 15,0,0,0,4 DREGION Number of unified MPU regions 8 8 S Type of MPU regions 0 1 MPIDR Multiprocessor Affinity Register ID Regs RO 0x00000000 15,0,0,0,5 AFF2 Affinity Level 2 16 8 AFF1 Affinity Level 2 8 8 AFF0 Affinity Level 2 0 8 ID_PFR0 Processor Feature Register 0 ID Regs RO 0x00000131 15,0,1,0,0 STATE_3 ThumbEE instruction set supported 12 4 STATE_2 Jazelle extension interface supported 8 4 STATE_1 Thumb-2 Instruction Set supported (0x3) 4 4 STATE_0 32-bit ARM instruction set supported 0 4 ID_PFR1 Processor Feature Register 1 ID Regs RO 0x00000001 15,0,1,0,1 M_PROFILE M profile programmers model supported 8 4 SECURITY_EXT Security extension architecture v1 supported 4 4 PROG_MODEL Standard ARMv4 programmers model supported 0 4 ID_DFR0 Debug Feature Register 0 ID Regs RO 0x00010400 15,0,1,0,2 M_PROFILE Memory-mapped debug model for M Profile processors supported 20 4 MM_TRACE_MODEL Memory-mapped trace debug model supported 16 4 CP_TRACE_MODEL Coprocessor Trace Debug Model supported 12 4 MM_DEBUG_MODEL Memory-Mapped Debug Model supported 8 4 CP_SEC_DBG_MODEL Coprocessor-based secure debug model supported 4 4 CP_DBG_MODEL Coprocessor based core debug model supported 0 4 ID_AFR0 Auxiliary Feature Register 0 ID Regs RO 0x00000000 15,0,1,0,3 ID_MMFR0 Memory Model Features Register 0 ID Regs RO 0x00210030 15,0,1,0,4 IN_SHARE Innermost shareability domain supported 28 4 FCSE Fast Context Switching Extension (FCSE) supported 24 4 AUX_CTRL_REG Auxiliary Control Registers supported 20 4 TCM Tight Coupled Memory (TCM) supported 16 4 SHAREABILITY_LEVELS Number of Shareability Levels Implemented (0x1: two levels implemented) 12 4 OUTER_SHRABILITY Indicates the outermost Shareability Level Implemented (0x1: Processor supports hardware coherency) 8 4 PMSA Protected Memory System Architecture supported 4 4 VMSA Virtual Memory System Architecture supported 0 4 ID_MMFR1 Memory Model Features Register 1 ID Regs RO 0x00000000 15,0,1,0,5 BRANCH_PREDICT Branch Predictor Management Requirements 28 4 L1_CACHE_TNC L1 data cache test and clean operations supported 24 4 L1_UNIFIED_CACHE L1 unified cache clean/invalidate-all operations supported 20 4 L1_HARVARD_CACHE L1 data cache clean/invalidate-all operations supported 16 4 L1_UNIFIED_CACHE_SW L1 unified cache maintencance operations by set/way supported 12 4 L1_HARVARD_CACHE_SW L1 Hardvard cache maintenance operations by set/way supported 8 4 L1_UNIFIED_CACHE_VA L1 unified cache maintenance operations by VA supported 4 4 L1_HARVARD_CACHE_VA L1 Harvard cache maintenance operations by VA supported 0 4 ID_MMFR2 Memory Model Features Register 2 ID Regs RO 0x01200000 15,0,1,0,6 HW_ACCESS Hardware access supported 28 4 WFI_STALL Wait For Interrupt (WFI) stalling supported 24 4 MEM_BARRIER Memory Barrier Operations supported 20 4 UNIFIED_TLB Unified TLB maintenance operations supported 16 4 HARVARD_TLB Harvard TLB maintenance operations supported 12 4 L1_HARVARD_RANGE L1 Hardvard range supported 8 4 L1_HBP L1 Harvard background prefetch operations supported 4 4 L1_HFP L1 Harvard foreground prefetch operations supported 0 4 ID_MMFR3 Memory Model Features Register 3 ID Regs RO 0x00000211 15,0,1,0,7 SS_SUPPORT 16 MB supersections supported 28 4 COHRERENT_WALK Coherent walk supported. 0x1: updates to translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks 20 4 MAINTENANCE_BC Cache, TLB and Branch prediction operations broadcast supported 12 4 BP_MAINTENANCE Branch Predictor (BP) maintenance operations supported 8 4 CACHE MAINTENANCE_SW Set/Way cache maintenance supported 4 4 CACHE_MAINTENANCE_MVA MVA cache maintenance supported 0 4 ID_ISAR0 Instruction Set Attributes Register 0 ID Regs RO 0x01101111 15,0,2,0,0 DIVIDE_INSTR Integer hardware divide supported 24 4 DBG_INSTR BKPT instruction supported 20 4 CP_INSTRS CP14, CP15 and VFPv4 Coprocessor instructions supported 16 4 CNB_INSTRS Compare-and-branch instructions CBZ and CBNZ supported 12 4 BF_INSTRS Bit-Field instructions BFC, BFI, SBFX and UBFX supported 8 4 BC_INSTRS Bit count instruction CLZ supported 4 4 SWAP_INSTRS Swap instructions SWP and SWPB supported 0 4 ID_ISAR1 Instruction Set Attributes Register 1 ID Regs RO 0x13112111 15,0,2,0,1 JAZELLE_INSTRS Jazelle instructions supported 28 4 INTERW_INSTRS ARM/Thumb interworking instructions supported 24 4 IMM_INSTRS Special immediate-generating instructions supported 20 4 ITE_INSTRS Thumb IT blocks supported 16 4 EXTEND_INSTRS Extend instructions supported 12 4 EXCPT2_INSTRS Exception2-instructions SRS, RFE and CPS supported 8 4 EXCPT1_INSTRS Exception1-instructions LDM(2), LDM(3) and STM(2) supported 4 4 ENDIAN_INSTRS BE8 endian change supported with SETEND 0 4 ID_ISAR2 Instruction Set Attributes Register 2 ID Regs RO 0x21232131 15,0,2,0,2 REV_INSTRS Reversal instructions REV, REV16, REVSH and RBIT supported 28 4 PSR_INSTRS PSR instructions MRS and MSR and exception return data-processing instructions supported 24 4 MULT_U_INSTRS Long multiply instructions and UMAAL supported 20 4 MULT_S_INSTRS Signed-Multiply instructions and Q flag in PSRs supported 16 4 MULTIPLY_INSTRS Multiply instructions MUL, MLA and MLS supported 12 4 MAI_INSTRS Multi-access interruptible instructions (MAI) supported 8 4 MEM_HINT_INSTRS Memory hint instructions PLD, PLI and PLDW supported 4 4 LS_INSTRS Load and Store instructions LDRD and STRD supported 0 4 ID_ISAR3 Instruction Set Attributes Register 3 ID Regs RO 0x01112131 15,0,2,0,3 THUMB2_INSTRS Thumb-2 Executable Environment Extension instructions supported 28 4 TRUE_NOP_INSTR True no-operation instruction NOP32 supported 24 4 THUMB_CPY_INSTRS Thumb copy instructions MOV(3) and CPY alias supported 20 4 TBL_BRANCH_INSTRS Thumb table branch instruction TBB and TBH supported 16 4 EXCLUSIVE_INSTRS Exclusive Instructions supported 12 4 SVC_INSTRS SVC instructions supported 8 4 SIMD_INSTRS All SIMD instructions supported 4 4 SAT_INSTRS Saturate instructions QADD, QDADD, QDSUB, QSUB and Q flag in PSRs supported 0 4 ID_ISAR4 Instruction Set Attributes Register 4 ID Regs RO 0x00010142 15,0,2,0,4 PSM_M_INSTRS M-profile instructions for modifying the PSRs Supported 24 4 EXCL_INSTRS Exclusive Instructions 20 4 BARRIER_INSTRS Barrier instructions DMB, DSB and ISB supported 16 4 SMC_INSTRS Secure Monitor Call (SMC) instructions supported 12 4 WRITE_BACK_INSTRS All defined write-back addressing modes supported 8 4 WITH_SHIFT_INSTRS Immediate and register control shifted operations supported 4 4 UNPRIVILEGED_INSTRS Unpriviledges load/store instructions LDRT and STRT supported 0 4 ID_ISAR5 Instruction Set Attributes Register 5 ID Regs RO 0x00000000 15,0,2,0,5 CCSIDR Cache Size Identification Register ID Regs RO 15,0,0,1,0 WT Write-Through supported 31 1 WB Write-Back supported for (0x0) L1 data cache, (0x1) L1 instruction cache 30 1 RA Cache read allocation supported 29 1 WA Write allocation supported for: 1: L1 data cache, 0: L1 instruction cache 28 1 NUM_SETS Number of cache sets 13 15 ASSOCIATIVITY Cache associativity. 0x3: 4-way data cache, 0x1: 2-way instruction cache 3 10 LINE_SIZE Number of words per line. 0x1: eight words per line 0 3 CLIDR Cache Level ID Register ID Regs RO 15,0,0,1,1 LoU Level of Unification 27 3 LoC Level of Coherency 24 3 LoUIS Level of Unification Inner Shareable 21 3 CL 7 Cache at Level 7 present 18 3 CL 6 Cache at Level 6 present 15 3 CL 5 Cache at Level 5 present 12 3 CL 4 Cache at Level 4 present 9 3 CL 3 Cache at Level 3 present 6 3 CL 2 Cache at Level 2 present 3 3 CL 1 Separate instruction and data caches at Level 1 0 3 AIDR Auxiliary ID Register ID Regs RO 0x00000000 15,0,0,1,7 CSSELR Cache Size Selection Register Cache RW 15,0,0,2,0 LEVEL Cache level selected 1 3 InD Selected Cache. 0x1: instruction cache, 0x0: data cache 0 1 SCTLR System Control Register System RW 15,1,0,0,0 IE Identifies little (0) or big (1) instruction endianess in use 31 1 TE Thumb exception enable bit. 0: exceptions including reset are handled in ARM state, 1: exceptions including reset are handled in Thumb state 30 1 AFE Access Flag Enable bit. 0: full access permissions behaviour, 1: simplified access permissions behaviour 29 1 TRE TEX remap enable bit 28 1 NMFI non-maskable fast interrupt (NMFI) enable 27 1 EE Determines the value the CPSR E bit is set to on an exception. 0: set to 0, little-endian, 1: set to 1, big endian 25 1 VE Configures vectored interrupt 24 1 FI Fast Interrupts enable 21 1 DZ Raise undifined exception on Divide By Zero 21 1 BR MPU background region enable 21 1 RR Replacement strategy for instruction and data caches. 0:random, 1:round-robin 21 1 V Location of exception vectors. 0:normal, 1:high 13 1 I Instruction caching at any available cache level enabled 12 1 Z Branch Predictions enabled 11 1 SW SWP and SWPB enabled 10 1 C Data caching enabled 2 1 A Strict alignment fault checking enabled 1 1 M MMU enabled 0 1 ACTLR Auxiliary Control Register System RW 15,1,0,0,1 DICDI Case C dual issue control Disabled 31 1 DIB2DI Case B2 dual issue control Disabled 30 1 DIB1DI Case B1 dual issue control Disabled 29 1 DIADI Case A dual issue control Disable 28 1 B1TCMPCEN B1TCM parity or ECC check enable 27 1 B0TCMPCEN B0TCM parity or ECC check enable 26 1 ATCMPCEN ATCM parity or ECC check enable 25 1 AXISCEN AXI slave cache RAM access enable 24 1 AXISCUEN AXI slave cache RAM non-privileged access enable 23 1 DILSM Disable Low Interrupt Latency (LIL) on load/store multiples 22 1 DEOLP Disable end of loop prediction 21 1 DBHE Disable Branch History (BH) extension 20 1 FRCDIS Fetch rate control disabled 19 1 RSDIS Return stack disable 17 1 BP Branch Prediction Policy 16 2 DBWR Disable write burst in the AXI master 14 1 DLFO Disable linefill optimization in the AXI master 13 1 ERPEG Enable random parity error generation in the cache RAMs 12 1 DNCH Disable data forwarding for Non-cacheable accesses 11 1 FORA Force outer read allocate (ORA) for outer write allocate (OWA) regions 10 1 FWT Force write-through (WT) for write-back (WB) regions 9 1 FDSnS Data side normal Non-cacheable forced to Non-shared when MPU is off 8 1 sMOV sMOV out of order disabled 7 1 DILS Disable low interrupt latency on all load/store instructions 6 1 CEC Cache error control for cache parity and ECC errors 3 3 B1TCMECEN B1TCM external error enable 2 1 B0TCMCEN B0TCM external error enable 1 1 ATCMECEN ATCM external error enable 0 1 CPACR Coprocessor Access Control Register System RW 0x00000000 15,1,0,0,2 ASEDIS Advanced-SIMD disable 31 1 D32DIS VFP registers D16-D31 Disable 30 1 CP13 Access permission for coprocessor 13. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 26 3 CP12 Access permission for coprocessor 12. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 24 3 CP11 Access permission for coprocessor 11. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 22 2 CP10 Access permissions for coprocessor 10. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 20 2 CP9 Access permissions for coprocessor 9. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 18 2 CP8 Access permissions for coprocessor 8. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 16 2 CP7 Access permissions for coprocessor 7. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 14 2 CP6 Access permissions for coprocessor 6. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 12 2 CP5 Access permissions for coprocessor 5. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 10 2 CP4 Access permissions for coprocessor 4. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 8 2 CP3 Access permissions for coprocessor 3. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 6 2 CP2 Access permissions for coprocessor 2. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 4 2 CP1 Access permissions for coprocessor 1. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 2 2 CP0 Access permissions for coprocessor 0. 00: Access denied, 01: Priviledged mode access only, 11: Priviledged and User mode access 0 2 DFSR Data Fault Status Register Fault Handling RW 15,5,0,0,0 SD External Abort Qualifier. 0: AXI Decode error, 1: AXI Slave error 12 1 RW write (1) / read (0) access caused the abort 11 1 FS[4] Bit 4 of the Fault Status field 10 1 Domain Domain where the Fault was generated (SBZ) 4 4 FAULT_STATUS Type of Fault generated 0 4 IFSR Instruction Fault Status Register Fault Handling RW 15,5,0,0,1 SD External Abort Qualifier. 0: AXI Decode error, 1: AXI Slave error 12 1 FS[4] Bit 4 of the Fault Status Field 10 1 Domain Domain where the Fault was Generated (SBZ) 4 4 FAULT_STATUS Type of Fault Generated 0 4 ADFSR Auxilary Data Fault Status Register MPU RW 15,5,1,0,0 CACHE_WAY Cache way or ways in which the error occurred 24 4 SIDE Source of the error. Used together with field SIDE_EXT 22 2 RECOVERABLE_ERR Recoverable error attribute 21 1 SIDE_EXT Error Source Identifer 20 1 INDEX Index value for the access giving the error 5 9 AIFSR Auxilary Instruction Fault Status Register MPU RW 15,5,1,0,1 DFAR Data Fault Address Register Fault Handling RW 15,6,0,0,0 IFAR Instruction Fault Address Register Fault Handling RW 15,6,0,0,2 DRBAR MPU Region Base Address Register MPU RW 0x00000000 15,6,1,0,0 BASE_ADDR Defines bits [31:5] of the base address of a region 5 27 DRSR MPU Region Size And Enable Register MPU RW 0x00000000 15,6,1,0,2 SUB_REG_DISABLE Bit i set: address range is not part of region i 8 8 REGION_SZ Region Size Selector 1 5 ENABLE Memory region enabled 0 1 DRACR MPU Region Access Control Register MPU RW 0x00000000 15,6,1,0,4 XN No instruction fetches enabled (execute never) 12 1 AP Data Access Permissions 8 3 TEX Type Extension Attribute 3 3 S Memory Region is Shared 2 1 C C Bit (use with TEX field) 1 1 B B Bit (use with TEX field) 0 1 RGNR MPU Memory Region Number Register MPU RW 0x00000000 15,6,2,0,0 Region Group of registers to be accessed 0 4 NOP No Operation Cache WO 15,7,0,0,4 ICIALLUIS Invalidate All Instruction Caches Cache WO 15,7,5,0,0 ADDR Address to invalidate or clean 5 27 ICIMVAU Invalidate instruction cache line by MVA to Point of Unification (PoU) Cache WO 15,7,5,0,1 ADDR Address to invalidate or clean 5 27 FPB Flush Prefetch Buffer Cache WO 15,7,5,0,4 BPIALL Invalidate entire branch predictor array Cache WO 15,7,5,0,6 BPIMVA Invalidate Virtual Address (VA) from branch predictor array Cache WO 15,7,5,0,7 ADDR Address to invalidate or clean 5 27 DCIMVAC Invalidate data cache line to Point of Coherency by MVA Cache WO 15,7,6,0,1 ADDR Address to invalidate or clean 5 27 DCISW Invalidate data cache line by Set/Way Cache WO 15,7,6,0,2 WAY Cache way to invalidate or clean 30 2 SET Cache set to invalidate or clean 5 9 DCCMVAC Clean Data cache line to Point of Coherency by MVA Cache WO 15,7,10,0,1 ADDR Address to invalidate or clean 5 27 DCCSW Clean data cache line by Set/Way Cache WO 15,7,10,0,2 WAY Cache way to invalidate or clean 30 2 SET Cache set to invalidate or clean 5 9 DSB Data Synchronization Barrier Cache WO 15,7,10,0,4 DMB Data Memory Barrier Cache WO 15,7,10,0,5 DCCMVAU Clean data cache line by MVA to Point of Unification (PoU) Cache WO 15,7,11,0,1 ADDR Address to invalidate or clean 5 27 DCCIMVAC Clean and invalidate data cache line by MVA to Point of Unifciation (PoU) Cache WO 15,7,14,0,1 ADDR Address to invalidate or clean 5 27 DCCISW Clean and invalidate data cache line by Set/Way Cache WO 15,7,14,0,2 WAY Cache way to invalidate or clean 30 2 SET Cache set to invalidate or clean 5 9 BTCMRR BTCM Region Register System RW 15,9,1,0,0 BASE_ADDR Base Address of the BTCM 12 20 SIZE Size of the BTCM on reads 1 5 ENABLE BTCM Enabled 0 1 ATCMRR ATCM Region Register System RW 15,9,1,0,1 BASE_ADDR Base Address of the ATCM 12 20 SIZE Size of the ATCM on reads 1 5 ENABLE ATCM Enabled 0 1 TCMSR TCM Selection Register System RW 0x00000000 15,9,2,0,0 PMCR Performance Monitor Control Register PMU RW 0x41151800 15,9,12,0,0 IMP Implementor Code. 0x41: arm 24 8 ID_CODE Identification Code 16 8 N Number of Counters Implemented 11 4 DP Disable Cycle Counter PMCCNTR in prohibited regions 5 1 X Export of the events from the event bus to an external monitoring block enabled 4 1 D Cycle Count Divider. 0: count every clock cycle when enabled. 1: count every 64th clock cycle when enabled 3 1 C Cycle Counter Reset 2 1 P Reset all Performance Counters, including PMCCNTR 1 1 E Enable All Counters including PMCCNTR 0 1 PMCNTENSET Count Enable Set Register PMU RW 15,9,12,0,1 C Cycle Counter Enabled 31 1 P2 Counter 2 Enabled 2 1 P1 Counter 1 Enabled 1 1 P0 Counter 0 Enabled 0 1 PMCNTENCLR Count Enable Clear Register PMU RW 15,9,12,0,2 C PMCCNTR overflow interrupt clear bit 31 1 P2 Clear interrupt request on PMC2 overflow 2 1 P1 Clear interrupt request on PMC1 overflow 1 1 P0 Clear interrupt request on PMC0 overflow 0 1 PMSOVSR Overflow Flag Status Register PMU RW 15,9,12,0,3 C Cycle Counter Overflow Flag 31 1 P2 Counter 2 Overflow Flag 2 1 P1 Counter 1 Overflow Flag 1 1 P0 Counter 0 Overflow Flag 0 1 PMSWINC Software Increment Register PMU WO 15,9,12,0,4 P2 Increment Counter 2 2 1 P1 Increment Counter 1 1 1 P0 Increment Counter 0 0 1 PMSELR Performance Counter Selection Register PMU RW 0x00000000 15,9,12,0,5 SEL Counter Select 31 1 PMCCNTR Cycle Count Register PMU RW 0x00000000 15,9,13,0,0 PMXEVTYPER Event Type Select Register PMU RW 15,9,13,0,1 SEL Selected Event Number 0 8 PMXEVCNTR Counts Instances of an event selected by PMXEVTYPER PMU 0x00000000 RW 15,9,13,0,2 PMUSERENR User Enable Register PMU RW 0x00000000 15,9,14,0,0 EN User mode enable bit 0 1 PMINTENSET Interrupt Enable Set Register PMU RW 15,9,14,0,1 C PMCCNTR overflow interrupt request enable 31 1 P2 PMC2 overflow interrupt request enable 2 1 P1 PMC1 overflow interrupt request enable 1 1 P0 PMC0 overflow interrupt request enable 0 1 PMINTENCLR Interrupt Enable Clear Register PMU RW 15,9,14,0,2 C PMCCNTR overflow interrupt clear bit 31 1 P2 Clear interrupt request on PMC2 overflow 2 1 P1 Clear interrupt request on PMC1 overflow 1 1 P0 Clear interrupt request on PMC0 overflow 0 1 SPCR Slave Port Control Register System RW 0x00000000 15,11,0,0,0 PRIVLGD_ACCESS Privileged TCM accesses only 1 1 AXI_SLAVE_DISABLE AXI slave port disable 0 1 FCSEPIDR Fast Context Switch Extension (FCSE) Process ID Register ID Regs RO 0x00000000 15,13,0,0,0 CONTEXTIDR Context ID Register ID Regs RW 0x00000000 15,13,0,0,1 PROCID Processor Identifier 0 32 TPIDRURW User-RW Thread and Process ID Register ID Regs RW 0x00000000 15,13,0,0,2 TPIDRURO User Read-Only Thread and Process ID Register ID Regs RO 0x00000000 15,13,0,0,3 TPIDRPRW Priviledged Only Thread and Process ID Register ID Regs RW 0x00000000 15,13,0,0,4 SACR Secondary Auxiliary Control Register System RW 15,15,0,0,0 DCHE Disable hard-error support in the caches 22 1 DR2B Enable random 2-bit error generation in cache RAMs 21 1 DF6DI F6 dual issue control Disabled 20 1 DF2DI F2_Id/F2_st/F2D dual issue control Disabled 19 1 DDI F1/F3/F4dual issue control Disabled 18 1 DOODPFP Out-of-order Double Precision Floating Point instruction control Disabled 17 1 DOOFMACS Out-of-order FMACS control Disabled 16 1 IXC Propagate floating point inexact exception flag FPSCR.IXC to output FPIXC 13 1 OFC Propagate floating-point overflow exception flag FPSCR.OFC to output FPOFC 12 1 UFC Propagate floating-point underflow exception flag FPSCR.UFC to output FPUFC 11 1 IOC Propagate floating-point invalid operation exception flag FPSCR.IOC to output FPIOC 10 1 DZC Propagate floating-point divide-by-zero exception flag FPSCR.DZC to output FPDZC 9 1 IDC Propagate floating-point input denormal exception flag FPSCR.IDC to output FPIDC 8 1 BTCMECC Correction for internal ECC logic on BTCM ports Disabled 3 1 ATCMECC Correction for internal ECC logic on ATCM port Disabled 2 1 BTCMRMW 64-bit stores for the BTCMs Enabled 1 1 ATCMRMW 64-bit stores for the ATCM Enabled 0 1 NVAL_IRQ_SET nVAL IRQ Enable Set Validation RW 15,15,1,0,0 C PMCCNTR overflow IRQ request 31 1 P2 PMC2 overflow IRQ request 2 1 P1 PMC1 overflow IRQ request 1 1 P0 PMC0 overflow IRQ request 0 1 NVAL_FIQ_SET nVAL FIQ Enable Set Validation RW 15,15,1,0,1 C PMCCNTR overflow FIQ request 31 1 P2 PMC2 overflow FIQ request 2 1 P1 PMC1 overflow FIQ request 1 1 P0 PMC0 overflow FIQ request 0 1 NVAL_RESET_SET nVAL Reset Enable Set Validation RW 15,15,1,0,2 C PMCCNTR overflow Reset request 31 1 P2 PMC2 overflow Reset request 2 1 P1 PMC1 overflow Reset request 1 1 P0 PMC0 overflow Reset request 0 1 NVAL_DEBUG_REQ_SET nVAL Debug Request Enable Set Validation RW 15,15,1,0,3 C PMCCNTR overflow Debug request 31 1 P2 PMC2 overflow Debug request 2 1 P1 PMC1 overflow Debug request 1 1 P0 PMC0 overflow Debug request 0 1 NVAL_IRQ_CLR nVAL IRQ Request Enable Clear Validation RW 15,15,1,0,4 C PMCCNTR overflow IRQ request 31 1 P2 PMC2 overflow IRQ request 2 1 P1 PMC1 overflow IRQ request 1 1 P0 PMC0 overflow IRQ request 0 1 NVAL_FIQ_CLR nVAL FIQ Enable Clear Validation RW 15,15,1,0,5 C PMCCNTR overflow FIQ request 31 1 P2 PMC2 overflow FIQ request 2 1 P1 PMC1 overflow FIQ request 1 1 P0 PMC0 overflow FIQ request 0 1 NVAL_RESET_CLR nVAL Reset Enable Clear Validation RW 15,15,1,0,6 C PMCCNTR overflow Reset request 31 1 P2 PMC2 overflow Reset request 2 1 P1 PMC1 overflow Reset request 1 1 P0 PMC0 overflow Reset request 0 1 NVAL_DBG_REQ_CLR nVAL Debug Request Enable Clear Validation RW 15,15,1,0,7 C PMCCNTR overflow Debug request 31 1 P2 PMC2 overflow Debug request 2 1 P1 PMC1 overflow Debug request 1 1 P0 PMC0 overflow Debug request 0 1 BUILD_OPTS1 Build Options Register 1 System RO 0x00000000 15,15,2,0,0 TCM_HI_INIT_ADDR Default high address for the TCM 12 20 BUILD_OPTS2 Build Options Register 2 System RO 0x00000000 15,15,2,0,1 DUAL_CORE Default high address for the TCM 31 1 DUAL_NCLK Default high address for the TCM 30 1 NO_ICACHE Default high address for the TCM 29 1 NO_DCACHE Default high address for the TCM 28 1 ATCM_ES Default high address for the TCM 26 2 BTCM_ES Default high address for the TCM 24 2 NO_IE Default high address for the TCM 23 1 NO_FPU Default high address for the TCM 22 1 NO_MPU Default high address for the TCM 21 1 MPU_REGIONS Default high address for the TCM 20 1 BREAK_POINTS Default high address for the TCM 17 3 WATCH_POINTS Default high address for the TCM 14 3 NO_A_TCM_INF Default high address for the TCM 13 1 NO_B0_TCM_INF Default high address for the TCM 12 1 NO_B1_TCM_INF Default high address for the TCM 11 1 TCMBUSPARITY Default high address for the TCM 10 1 NO_SLAVE Default high address for the TCM 9 1 ICACHE_ES Default high address for the TCM 7 2 DCACHE_ES Default high address for the TCM 5 2 NO_HARD_ERR_CACHE Default high address for the TCM 4 1 AXIBUSPARITY Default high address for the TCM 3 1 PIN_OPTIONS Pin Options Register System RO 0x00000000 15,15,2,0,7 DBGNOCLKSTOP Value of the DBGNOCLKSTOP pin 4 1 INTSYNCEN Value of the INTSYNCEN pin 3 1 IRQADDRVSYNCEN Value of the IRQADDVSYNCEN pin 2 1 SLBTCMSB Value of the SLBTCMSBm pin 1 1 PARITYLEVEL Value of the PARITYLEVEL pin 0 1 CFLR Correctable Fault Location Register MPU RW 0x00000000 15,15,3,0,0 SIDE Cache side where the error occurred 24 2 ADDRESS Address in the TCM where the error occurred 3 20 TYPE Type of access that caused the error. 00: instruction cache, 01: data cache 0 2 IADCR Invalidate All Data Caches Register Cache WO 0x00000000 15,15,5,0,0 CZOR Cache Size Override Register Cache WO 0x00000000 15,15,14,0,0 DCACHE Data cache size override value 4 4 ICACHE Instruction cache size override value 0 4