CM55 Cortex-M55 (with FPU) Core CPU registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 8 R9 General purpose register 9 9 R10 General purpose register 10 10 R11 General purpose register 11 11 R12 General purpose register 12 12 R13 SP R13 (SP) Stack pointer 13 R14 LR R14 (LR) Link register 14 R15 PC R15 (PC) Program counter 15 xPSR Program status register 16 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 T Thumb state bit 24 1 GE Greater than or equal flags 16 4 IT/ICI/ECI HighBits Interruptible-continuable instruction bits (high bits) 25 2 IT/ICI/ECI LowBits Interruptible-continuable instruction bits (low bits) 10 6 Exception Number Interrupt service routine number 0 9 Control Control register 27 SFPA Indicates that the floating-point registers contain active state that belongs to the Secure state 3 1 0 The floating-point registers do not contain state that belongs to the Secure state 1 The floating-point registers contain state that belongs to the Secure state FPCA Indicates whether floating-point context is active 2 1 0 No floating-point context active 1 Floating-point context active SPSEL Defines the currently active stack pointer 1 1 0 MSP is the current stack pointer 1 PSP is the current stack pointer nPRIV Defines the Thread mode privilege level 0 1 0 Privileged 1 Unprivileged BasePri Base priority mask register 25 BASEPRI Change the priority level that is required for exception preemption 0 8 FaultMask Fault mask register 26 FM Prevent the activation of all exceptions with configurable priority and also some exceptions with fixed priority 16 1 PriMask Priority mask register 24 PM Disable interrupts by preventing activation of all exceptions with configurable priority 0 1 MSPLIM Main stack limit register 86 PSPLIM Process stack limit register 87 Core_S Secure CPU registers 32 RW unsigned int Control_S Banked secure control register 84 SFPA Indicates that the floating-point registers contain active state that belongs to the Secure state 3 1 0 The floating-point registers do not contain state that belongs to the Secure state 1 The floating-point registers contain state that belongs to the Secure state FPCA Indicates whether floating-point context is active 2 1 0 No floating-point context active 1 Floating-point context active SPSEL Defines the currently active stack pointer 1 1 0 MSP is the current stack pointer 1 PSP is the current stack pointer nPRIV Defines the Thread mode privilege level 0 1 0 Privileged 1 Unprivileged BasePri_S Banked secure base priority mask register 82 BASEPRI change the priority level that is required for exception preemption 0 8 FaultMask_S Banked secure fault mask register 83 FaultMask Prevent the activation of all exceptions except for NMI ##### 16 1 PriMask_S Banked secure priority mask register 81 PM Disable interrupts by preventing activation of all exceptions with configurable priority 0 1 MSP_S MSP_S Banked secure main stack pointer 68 PSP_S PSP_S Banked secure process stack pointer 69 MSPLIM_S Banked secure main stack limit register 70 PSPLIM_S Banked secure process stack limit register 71 Core_NS Non-Secure CPU registers 32 RW unsigned int Control_NS Banked non-secure control register 79 SFPA Indicates that the floating-point registers contain active state that belongs to the Secure state 3 1 0 The floating-point registers do not contain state that belongs to the Secure state 1 The floating-point registers contain state that belongs to the Secure state FPCA Indicates whether floating-point context is active 2 1 0 No floating-point context active 1 Floating-point context active SPSEL Defines the currently active stack pointer 1 1 0 MSP is the current stack pointer 1 PSP is the current stack pointer nPRIV Defines the Thread mode privilege level 0 1 0 Privileged 1 Unprivileged BasePri_NS Banked non-secure base priority mask register ##### 77 BASEPRI Change the priority level that is required for exception preemption 0 8 FaultMask_NS Banked non-secure fault mask register 78 FaultMask Prevent the activation of all exceptions except for NMI ##### 16 1 PriMask_NS Banked non-secure priority mask register 76 PM Disable interrupts by preventing activation of all exceptions with configurable priority 0 1 MSP_NS MSP_NS Banked non-secure main stack pointer 66 PSP_NS PSP_NS Banked non-secure process stack pointer 67 MSPLIM_NS Banked non-secure main stack limit register 72 PSPLIM_NS Banked non-secure process stack limit register 73 Peripherals Memory-Mapped CPU Registers 32 RW unsigned int NVIC Nested Vectored Interrupt Controller 0xE000E100 0x0 0xF00 registers Interrupt Set Enable Register %s NVIC_ISER_%s Enables, or reads the enable state of a group of interrupts 0x0 16 4 read-write SETENA_%s Interrupt set-enable bits. For SETENA[m] in NVIC_ISERn, allows interrupt 32n+m to be accessed. [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Clear Enable Register %s NVIC_ICER_%s Clears, or reads the enable state of, a group of registers 0x80 16 4 read-write CLRENA_%s Interrupt clear-enable bits. For SETENA[m] in NVIC_ICERn, allows interrupt 32n+m to be accessed. [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Set-Pending Register %s NVIC_ISPR_%s For a group of interrupts, changes interrupt status to pending, or shows the current pending status 0x100 16 4 read-write SETPEND_%s Interrupt set-pending bits. For SETPEND[m] in NVIC_ISPRn, allows interrupt 32n + m to be accessed. [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending 1 Interrupt Clear Pending Register %s NVIC_ICPR_%s For a group of interrupts, clears the interrupt pending status, or shows the current pending status 0x180 16 4 read-write CLRPEND_%s Interrupt clear-pending bits. Clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending; on writes, clear pending state 1 Interrupt Active Bit Register %s NVIC_IABR_%s For a group of interrupts, shows whether each interrupt is active 0x200 16 4 read-only ACTIVE_%s For ACTIVE[m] in NVIC_IABRn, indicates the active state for interrupt 32n+m. [0:0] 32 1 Interrupt not active 0 Interrupt active 1 Interrupt Targete Non-Secure Register %s NVIC_ITNS_%s For a group of interrupts, specifies or reads whether each interrupt targets non-secure or secure state 0x280 16 4 read-write ITNS_%s For ITNS[m] in NVIC_ITNSn, this field indicates and allows modification of the target Security state for interrupt 32n+m. [0:0] 32 1 Interrupt targets secure state 0 Interrupt targets non-secure state 1 Interrupt Priority Register %s NVIC_IPR_%s Sets or reads interrupt priorities 0x300 120 4 read-write PRI_N3 For register NVIC_IPRn, priority of interrupt number 4n+3 [31:24] PRI_N2 For register NVIC_IPRn, priority of interrupt number 4n+2 [23:16] PRI_N1 For register NVIC_IPRn, priority of interrupt number 4n+1 [15:8] PRI_N0 For register NVIC_IPRn, priority of interrupt number 4n [7:0] Software Trigger Interrupt Register STIR Write to the STIR to generate an interrupt from software. 0xE00 write-only INTID Interrupt ID of the interrupt to trigger, in the range 0-479. [0:8] SCB System Control Block 0xE000ECFC 0x0 0x90 registers Revision ID Register REVIDR Provides additional implementation-specific minor revision that can be interpreted with the CPUID register 0x0 read-only IMPLEMENTATION_SPECIFIC Implementation-specific minor revision information that can be interpreted with the CPUID register. [31:0] CPUID Base Register CPUID Contains the processor part number, version, and implementation information 0x4 read-only Implementer Implementer code [31:24] Variant Variant number, the n value in the rnpm product revision identifier [23:20] Architecture Reads as 0xF [19:16] 15 Armv8.1-M with Main Extension PartNo Part number of the processor [15:4] Revision Revision number, the m value in the rnpm product revision identifier [3:0] Interrupt Control and State Register ICSR Provides a set-pending bit for the non-maskable interrupt exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions 0x8 read-write PENDNMISET On writes, makes the NMI exception pending [31:31] 0 On writes, ignored; on reads, NMI exception is not pending 1 On writes, Changes NMI exception state to pending; on reads, NMI exception is pending PENDNMICLR Pend NMI clear bit (write-only) [30:30] 0 No effect 1 Clear pending status PENDSVSET PendSV set-pending bit [28:28] 0 On writes, ignored; on reads, PendSV exception is not pending 1 On writes, Changes PendSV exception state to pending; on reads, PendSV exception is pending PENDSVCLR PendSV clear-pending bit (write-only) [27:27] 0 No effect 1 Clear pending status PENDSTSET SysTick exception set-pending bit [26:26] 0 On writes, ignored; on reads, SysTick exception is not pending 1 On writes, Changes SysTick exception state to pending; on reads, SysTick exception is pending PENDSTCLR SysTick exception clear-pending bit [25:25] 0 No effect 1 Clear pending status ISRPREEMPT Indicates whether a pending exception is handled on exit from debug state. [23:23] 0 Pending exception is not handled on exit from debug state 1 Pending exception is handled on exit from debug state ISRPENDING Interrupt pending flag, excluding NMI and Faults [22:22] 0 Interrupt not pending 1 Interrupt pending VECTPENDING Indicates the exception number of the highest priority pending enabled exception [20:12] RETTOBASE Indicates whether there are pre-empted active exceptions [11:11] 0 There are pre-empted active exceptions to execute 1 There are no active exceptions, or the currently executing exception is the only active exception VECTACTIVE Contains the active exception number [8:0] Vector Table Offset Register VTOR Indicates the offset of the vector table base address from memory address 0x00000000 0xC read-write TBLOFF Bits[31:7] of the vector table address [31:7] Application Interrupt and Reset Control Register AIRCR Sets or returns interrupt control data 0x10 read-write VECTKEY/VECTKEYSTAT Register key. Reads as 0x0FA05, On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. [31:16] ENDIANNESS Data endianness [15:15] 0 Little endian 1 Big endian PRIS Prioritize Secure exceptions [14:14] 0 Priority ranges of Secure and Non-secure exceptions are identical 1 Non-secure exceptions are de-prioritized BFHFNMINS BusFault, HardFault, and NMI Non-secure enable [13:13] 0 BusFault, HardFault, and NMI are Secure 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault PRIGROUP Interrupt priority grouping [10:8] SYSRESETREQS System reset request, Secure state only [3:3] SYSRESETREQ functionality is available to both Security states 0 SYSRESETREQ functionality is only available to Secure state 1 SYSRESETREQ System Reset Request [2:2] Do not request a reset 0 Request reset 1 VECTCLRACTIVE Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE [1:1] System Control Register SCR Controls features of entry to and exit from low-power state 0x14 read-only SEVONPEND Determines whether an interrupt assigned to the same Security state as the SEVONPEND bit transitioning from inactive state to pending state generates a wakeup event [4:4] 0 Transitions from inactive to pending are not wakeup events 1 Transitions from inactive to pending are wakeup events SLEEPDEEPS Controls whether the SLEEPDEEP bit is only accessible from the Secure state [3:3] 0 The SLEEPDEEP bit accessible from both Security states 1 The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state SLEEPDEEP Indicates whether the processor uses sleep or deep sleep as its low-power mode [2:2] 0 Sleep 1 Deep sleep SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode [1:1] 0 Do not sleep when returning to Thread mode 1 Enter sleep, or deep sleep, on return from an ISR Configuration and Control Register CCR indicates some aspects of the behavior of the processor 0x18 read-write TRD Thread reentrancy disabled [20:20] 0 Integrity signature checking not performed 1 Integrity signature checking performed LOB Loop and branch info cache enable [19:19] 0 Branch cache disabled for the selected Security state 1 Branch cache enabled for the selected Security state IC Instruction cache enable [17:17] 0 Instruction caches disabled for the selected Security state 1 Instruction caches enabled for the selected Security state DC Data cache enable [16:16] 0 Data caching disabled 1 Data caching enabled STKOFHFNMIGN Controls the effect of a stack limit violation while executing at a requested priority less than 0 [10:10] 0 Stack limit faults not ignored 1 Stack limit faults at requested priorities of less than 0 ignored BFHFNMIGN Determines the effect of precise bus faults on handlers running at a requested priority less than 0 [8:8] 0 Precise bus faults are not ignored 1 Precise bus faults at requested priorities of less than 0 are ignored DIV_0_TRP Divide by zero trap. Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero. [4:4] 0 Trapping disabled 1 Trapping enabled UNALIGN_TRP Controls the trapping of unaligned word or halfword accesses [3:3] 0 Trapping disabled 1 Trapping enabled USERSETMPEND User set main pending. Determines whether unprivileged accesses are permitted to pend interrupts from the STIR. [1:1] 0 Unprivileged accesses to the STIR generate a fault 1 Unprivileged accesses to the STIR are permitted System Handler Priority Register 1 SHPR1 Sets or returns priority for system handlers 4-7 0x1C read-write PRI_7 Priority of system handler 7, SecureFault [31:24] PRI_6 Priority of system handler 6, UsageFault [23:16] PRI_5 Priority of system handler 5, BusFault [15:8] PRI_4 Priority of system handler 4, MemManage [7:0] System Handler Priority Register 2 SHPR2 Sets or returns priority for system handler 8-11 0x20 read-write PRI_11 Priority of system handler 11, SVCall [31:24] System Handler Priority Register 3 SHPR3 Sets or returns priority for system handlers 12-15 0x24 read-write PRI_15 Priority of system handler 15, SysTick [31:24] PRI_14 Priority of system handler 14, PendSV [23:16] PRI_12 Priority of system handler 12, DebugMonitor [7:0] System Handler Control and State Register SHCSR Enables the system handlers and indicates the pending status of the BusFault, MemManage fault, and SVC exceptions, and indicates the active status of the system handlers 0x28 read-write HARDFAULTPENDED HardFault exception pended state bit, set to 1 to allow exception modification [21:21] SECUREFAULTPENDED SecureFault exception pended state bit, set to 1 to allow exception modification [20:20] SECUREFAULTENA RES0 [19:19] USGFAULTENA UsageFault enable [18:18] 0 Disable the exception 1 Enable the exception BUSFAULTENA BusFault enable [17:17] 0 Disable the exception 1 Enable the exception MEMFAULTENA MemManage enable [16:16] 0 Disable the exception 1 Enable the exception SVCALLPENDED SVCall pending [15:15] 0 SVCall execption is not pending 1 SVCall execption is pending BUSFAULTPENDED BusFault pending [14:14] 0 SVCall execption is not pending 1 SVCall execption is pending MEMFAULTPENDED MemManage exception pending [13:13] 0 SVCall execption is not pending 1 SVCall execption is pending USGFAULTPENDED UsageFault exception pending [12:12] 0 SVCall execption is not pending 1 SVCall execption is pending SYSTICKACT SysTick exception active [11:11] 0 SVCall execption is not active 1 SVCall execption is active PENDSVACT PendSV exception active [10:10] 0 PendSV exception is not active 1 PendSV exception is active MONITORACT Debug monitor active [8:8] 0 DebugMonitor not active 1 DebugMonitor is active SVCALLACT SVCall active [7:7] 0 SVCall is not active 1 SVCall is active NMIACT NMI exception active [5:5] 0 NMI exception is not active 1 NMI exception is active SECUREFAULTACT SecureFault exception active state [4:4] 0 SecureFault exception is not active 1 SecureFault exception is active USGFAULTACT UsageFault exception active [3:3] 0 UsageFault exception is not active 1 UsageFault exception is active HARDFAULTACT HardFault exception active [2:2] 0 HardFault exception is not active 1 HardFault exception is active BUSFAULTACT BusFault exception active [1:1] 0 BusFault exception is not active 1 BusFault exception is active MEMFAULTACT MemManage exception active [0:0] 0 MemManage exception is not active 1 MemManage exception is active Configurable Fault Status Register CFSR Indicates the cause of a MemManage fault, BusFault, or UsageFault 0x2C read-write UsageFault Provides information on UsageFault exceptions [31:16] BusFault Provides information on BusFault exceptions [15:8] MemManage Provides information on MemManage exceptions [7:0] MemManage Fault Status Register MMFSR Indicates the cause of memory access faults 0x2C read-write 8 MMARVALID MemManage Fault Address Register (MMFAR) valid flag [7:7] 0 MMFAR content not valid 1 MMFAR content valid MLSPERR MemManage lazy state preservation error flag [5:5] 0 No MemManage fault occurred during floating-point lazy state preservation 1 A MemManage fault occurred during floating-point lazy state preservation MSTKERR MemManage fault on stacking for exception entry [4:4] 0 No stacking fault 1 Stacking for an exception entry has caused one or more access violations MUNSTKERR MemManage fault on unstacking for a return from exception [3:3] 0 No unstacking fault 1 Unstack for an exception return has caused one or more access violations DACCVIOL Data access violation flag [1:1] 0 No data access violation fault 1 data access violation fault occurred IACCVIOL Instruction access violation flag [0:0] 0 No instruction access violation fault 1 Instruction acce ss violation fault occurred Bus Fault Status Register BFSR Indicate the cause of a bus access fault 0x2D read-write 8 BFARVALID BusFault Address Register (BFAR) valid flag. [7:7] 0 BFAR content not valid 1 BFAR content valid LSPERR Lazy state preservation error [5:5] 0 No BusFault occurred during FP lazy state preservation 1 BusFault occurred during FP lazy state preservation STKERR BusFault on stacking for exception entry [4:4] 0 No stacking fault 1 Stacking for an exception entry has caused one or more BusFaults UNSTKERR BusFault on unstacking for a return from exception [3:3] 0 No unstacking fault 1 Unstack for an exception return has caused one or more BusFaults PRECISERR Precise data bus error [1:1] 0 No precise data bus error 1 Precise data bus error occurred IBUSERR Instruction bus error [0:0] 0 No instruction bus error 1 Instruction bus error has occurred Usage Fault Status Register UFSR Indicates the cause of a UsageFault 0x2E read-write 16 DIVBYZERO Divide by zero flag. Sticky flag indicating whether an integer division by zero error has occurred. [9:9] 0 Error has not occurred 1 Error has occurred UNALIGNED Unaligned access flag. Sticky flag indicating whether an unaligned access error has occurred. [8:8] 0 Error has not occurred 1 Error has occurred STKOF Stack overflow flag. Sticky flag indicating whether a stack overflow error has occurred. [4:4] 0 Error has not occurred 1 Error has occurred NOCP No coprocessor flag. Sticky flag indicating whether a coprocessor disabled or not present error has occurred. [3:3] 0 Error has not occurred 1 Error has occurred INVPC Invalid PC flag. Sticky flag indicating whether an integrity check error has occurred. [2:2] 0 Error has not occurred 1 Error has occurred INVSTATE Invalid state flag. Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred. [1:1] 0 Error has not occurred 1 Error has occurred UNDEFINSTR Undefined instruction flag. Sticky flag indicating whether an undefined instruction error has occurred. [0:0] 0 Error has not occurred 1 Error has occurred HardFault Status Register HFSR Gives information about events that activate the HardFault handler 0x30 read-write DEBUGEVT Reserved for Debug use. When writing to the register you must write 1 to this bit, otherwise behavior is unpredictable. [31:31] FORCED Indicates a forced HardFault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled [30:30] 0 No forced HardFault 1 Forced HardFault VECTTBL Indicates a HardFault on a vector table read during exception processing [1:1] 0 No HardFault on vector table read 1 HardFault on vector table read MemManage Fault Address Register MMFAR Shows the address of the memory location that caused a Memory Protection Unit (MPU) fault 0x38 read-write BusFault Address Register BFAR Shows the address associated with a precise data access BusFault 0x3C read-write Auxiliary Fault Status Register AFSR provides fault status information 0x40 read-only IITCM Imprecise fault on ITCM interface 0 1 IDTCM Imprecise fault on DTCM interface 1 1 IPAHB Imprecise fault on P-AHB interface 2 1 IMAXI Imprecise fault on M-AXI interface 3 1 IEPPB Imprecise fault on EPPB interface 4 1 IMAXITYPE AXI response that caused the imprecise fault. Only valid when AFSR.IMAXI is 1. 6 1 0 SLVERR 1 DECERR IECC Imprecise fault caused by uncorrectable ECC error 7 1 IPOISON Imprecise BusFault because of RPOISON 9 1 PITCM Precise fault on ITCM interface 10 1 PDTCM Precise fault on DTCM interface 11 1 PPAHB Precise fault on Peripheral AHB (P-AHB) interface 12 1 PMAXI Precise fault on M-AXI interface 13 1 PEPPB Precise fault on External Private Peripheral Bus (EPPB) interface 14 1 PIPPB Precise fault on Internal Private Peripheral Bus (EPPB) interface 15 1 PMAXITYPE AXI response that caused the precise fault. Only valid when AFSR.PMAXI is 1. 16 1 0 SLVERR 1 DECERR PECC Precise fault caused by uncorrectable ECC error 17 1 PTGU Precise fault caused by TGU security violation 18 1 PPOISON Precise fault caused by RPOISON or TEBRx.POISON 19 1 FITCM Fetch fault on Instruction Tightly Coupled Memory (ITCM) interface 21 1 FDTCM Fetch fault on Data Tightly Coupled Memory (DTCM) interface 22 1 FMAXI Fetch fault on Master AXI (M-AXI) interface 24 1 FMAXITYPE AXI response that caused the fetch fault. Only valid when AFSR.FMAXI is 1. 27 1 0 SLVERR 1 DECERR FECC Fetch fault caused by uncorrectable Error Correcting Code (ECC) error 28 1 FTGU Fetch fault caused by TCM Gate Unit (TGU) security violation 29 1 FPOISON Fetch fault caused by RPOISON or TEBRx.POISON 30 1 Processor Feature Register 0 ID_PFR0 Indicates the version of the Reliability, Availability, and Serviceability (RAS) extension supported 0x44 read-only RAS Identifies which version of the RAS architecture is implemented [31:28] 2 Version 1 State1 T32 instruction set support [7:4] 3 T32 instruction set including Thumb-2 technology is implemented State0 A32 instruction set support [3:0] 0 A32 instruction set is not implemented Processor Feature Register 1 ID_PFR1 Gives information about the programmers' model and Extensions support 0x48 read-only MProgMod M-profile programmers' model [11:8] 2 Two-stack programmers' model Security Identifies whether the Security Extension in implemented [7:4] 0 Security Extension is not implemented 3 Security Extension implemented with state handling instructions Debug Feature Register 0 ID_DFR0 no information available 0x4C read-only Auxiliary Feature Register 0 ID_AFR0 The ID_AFR0 is fully Reserved, RES0 0x50 read-only Memory Model Feature Register 0 ID_MMFR0 Gives information about the implemented memory model and memory management support 0x54 read-only AuxReg Indicates support for Auxiliary Control registers [23:20] 1 Auxiliary Control registers are supported TCM Indicates support for TCMs [19:16] 1 TCMs are supported ShareLvl Indicates the number of Shareability levels implemented [15:12] 1 Two levels of Shareability implemented OuterShr Indicates the outermost Shareability domain implemented [11:8] Implemented as Non-cacheable 0 PMSA Indicates support for the protected memory system architecture (PMSA) [7:4] Supports PMSAv8 4 Memory Model Feature Register 1 ID_MMFR1 Gives information about the IMPLEMENTATION DEFINED memory model and memory management support. This register is Reserved, RES0. 0x58 read-only Memory Model Feature Register 2 ID_MMFR2 Gives information about the implemented memory model and memory management support 0x5C read-only WFIStall Indicates the support for Wait For Interrupt (WFI) stalling [27:24] 1 WFI has the ability to stall Memory Model Feature Register 3 ID_MMFR3 Gives information about the implemented memory model and memory management support 0x60 read-only BPMaint Indicates the supported branch predictor maintenance [11:8] 0 Branch predictor maintenance is not supported CMaintSW Indicates the supported cache maintenance operations by set/way [7:4] 1 Cache maintenance operations by set/way are supported CMaintVA Indicates the supported cache maintenance operations by address [3:0] 1 Cache maintenance operations by address are supported Instruction Set Attribute Register 0 ID_ISAR0 Gives information about the implemented instruction set 0x64 read-only Divide Indicates the supported divide instructions [27:24] 1 Supports SDIV and UDIV instructions Debug Indicates the implemented debug instructions [23:20] 1 Supports BKPT instruction Coproc Indicates the supported coprocessor instructions [19:16] 0 Coprocessor instructions are not supported, except for, floating-point or MVE Coprocessor instructions are supported. 4 CmpBranch Indicates the supported combined Compare and Branch instructions [15:12] Supports CBNZ and CBZ instructions along with non-predicated low-overhead looping and branch future instructions. Branch future instructions behave as NOPs 3 BitField Indicates the supported bit field instructions [11:8] 1 BFC, BFI, SBFX, and UBFX are supported BitCount Indicates the supported bit count instructions [7:4] CLZ supported 1 Instruction Set Attribute Register 1 ID_ISAR1 Gives information about the implemented instruction set 0x68 read-only Interwork Indicates the implemented interworking instructions [27:24] 2 BLX, BX, and loads to PC network Immediate Indicates the implemented data-processing instructions with long immediates [23:20] 2 ADDW, MOVW, MOVT, and SUBW are supported IfThen Indicates the implemented If-Then instructions [19:16] IT instruction supported 1 Extend Indicates the implemented Extend instructions [15:12] Adds SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH DSP Extension only 2 Instruction Set Attribute Register 2 ID_ISAR2 Gives information about the implemented instruction set 0x6C read-only Reversal Indicates the implemented reversal instructions [31:28] 2 REV, REV16, REVSH, and RBIT instructions are supported MultU Indicates the implemented Advanced Unsigned Multiple instructions [23:20] 2 Adds UMAAL, DSP Extension only MultS Indicates the implemented Advanced Signed Multiple instructions [19:16] 3 Adds all saturating and DSP signed multiplies, DSP Extension only Mult Indicates the implemented additional Multiply instructions [15:12] 2 MUL, MLA, and MLS instructions MultiAccessInt Multi-access instructions. Indicates the support for interruptible multi-access instructions [11:8] 2 LDM, STM, and CLRM instructions are continuable MemHint Memory hint. Indicates the implemented memory hint instructions [7:4] 3 PLI and PLD instructions implemented LoadStore Indicates the implemented additional load/store instructions [3:0] 2 Supports load-acquire, store-release, and exclusive load and store instructions Instruction Set Attribute Register 3 ID_ISAR3 Gives information about the implemented instruction set 0x70 read-only TrueNOP Indicates the implemented true NOP instructions [27:24] 1 NOP instruction and compatible hints are implemented T32Copy Indicates the support for T32 non-flag setting MOV instructions [23:20] 1 Encoding T1 of MOV (register) supports copying a low register to a low register TabBranch Indicates the implemented table branch instructions [19:16] 1 TBB and TBH are implemented SynchPrim Used with ID_ISAR4.SynchPrim_frac to indicate the implemented synchronization primitive instructions [15:12] 1 LDREX, STREX, LDREXB, STREXB, LDREXH, STREXH, and CLREX are implemented SVC Indicates the implemented SVC instructions [11:8] 1 SVC instruction implemented SIMD Indicates the implemented SIMD instructions [7:4] 3 SSAT, USAT, Q-bit, packed arithmetic, and GE-bits are implemented Saturate Indicates the implemented saturating instructions [3:0] 1 QADD, QDADD, QDSUB, QSUB, and Q-bit implemented, DSP Extension only Instruction Set Attribute Register 4 ID_ISAR4 Gives information about the implemented instruction set 0x74 read-only PSR_M Indicates the implemented M-profile instructions to modify the PSRs [27:24] 1 M-profile forms of CPS, MRS, and MSR instructions are implemented SynchPrim_frac Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented synchronization primitive instructions [23:20] 1 LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions are implemented Barrier Indicates the implemented Barrier instructions [19:16] 1 CSDB, DMB, DSB, ISB, PSSBB, and SSBB barrier instructions implemented Writeback Indicates the support for writeback addressing modes [11:8] 1 All writeback addressing modes supported WithShifts Indicates the support for writeback addressing modes [7:4] 3 Support for constant shifts on load/store and other instructions Unpriv Indicates the implemented unprivileged instructions [3:0] 2 LDRBT, LDRHT, LDRSBT, LDRSHT, LDRT, STRBT, STRHT, and STRT implemented Instruction Set Attribute Register 5 ID_ISAR5 Gives information about the implemented instruction set. This register is Reserved, RES0 0x78 read-only Cache Level ID Register CLIDR The CLIDR identifies the type of caches implemented and the level of coherency and unification 0x78 read-only ICB Inner cache boundary. The Cortex-M55 processor supports inner cacheability on the bus. Therefore, this field cannot disclose any information. [31:30] LoUU Level of Unification Uniprocessor [29:27] 0 No cache 1 L1 data cache or instruction cache is implemented LoC Level of Coherency [26:24] 0 No cache 1 L1 data cache or instruction cache is implemented LoUIS Level of Unification Inner Shareable [23:21] 0 No cache 1 L1 data cache or instruction cache is implemented CType_1 L1 cache type [2:0] 0 No cache 1 Instruction cache only 2 Data cache only 3 instruction and data caches Cache Type Register CTR The CTR provides information about the architecture of the caches 0x80 read-only Format Cache type register format [31:29] 4 Cache type information is provided CWG Cache Write-Back Granule [27:24] ERG Exclusives Reservation Granule [23:20] DminLine Data cache minimum line length. Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. [19:16] IminLine Instruction cache minimum line length. Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. [3:0] Current Cache Size ID Register CCSIDR Provides information about the architecture of the Level 1 (L1) instruction or data cache that the CSSELR selects. 0x84 read-only WT Indicates support available for Write-Through 0 Not available 1 Available WB Indicates support available for Write-Back [30:30] 0 Not available 1 Available RA Indicates support available for read allocation [29:29] 0 Not available 1 Available WA Indicates support available for write allocation [28:28] 0 Not available 1 Available NumSet Indicates the number of sets [27:13] Associativity Indicates associativity [12:3] LineSize Indicates the number of words in each cache line [2:0] 0 16 bytes 1 32 bytes Cache Size Selection Register CSSELR The CSSELR selects the current CCSIDR by specifying the cache level and the type of cache 0x88 read-write Level Cache level of required cache [3:1] 0 L1 cache InD Instruction not data bit [0:0] 0 L1 data cache 1 L1 instruction cache Coprocessor Access Control Register CPACR Specifies the access privileges for coprocessors 0x8C read-write CP_%s Coprocessor %s privilege [1:0] 8 1 0 Access denied. Any attempted access generates a NOCP UsageFault 1 Privileged access only. An unprivileged access generates a NOCP UsageFault 3 Full access CP_10 CP10 Privilege. Defines the access rights for the floating-point functionality. [21:20] 0 All accesses to the FP Extension result in NOCP UsageFault 1 Unprivileged accesses to the FP Extension result in NOCP UsageFault 3 Full access to the FP Extension CP_11 CP11 Privilege. The value in this field is ignored. [23:22] Non-secure Access Control Register NSACR In an implementation with the Security Extension, the NSACR register defines the Non-secure access permissions for both the Floating-point and MVE and coprocessors CP m, bit[ m], for m = 0-7. If MVE is implemented, this register specifies the Non-secure permissions for MVE 0x90 read-write CP_%s Enables Non-secure access to this coprocessor [0:0] 8 1 Non-secure accesses to this coprocessor generate a NOCP UsageFault 0 Non-secure access to this coprocessor permitted 1 CP_10 Enables non-secure access to the Floating-point and MVE [10:10] Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault 0 Non-secure access to the Floating-point and MVE permitted 1 CP_11 Enables non-secure access to the Floating-point and MVE. Programming with a different value other than that used for CP10 is unpredictable. [11:1] ICB Implementation Control Block 0xE000E004 0x0 0xC registers Interrupt Controller Type Register ICTR Provides information about the interrupt controller 0x0 read-only INTLINESNUM_%s The total number of interrupt lines supported by an implementation, defined in groups of 32 [3:0] 2 16 Auxiliary Control Register ACTLR Allow software to control the processor features and functionality 0x4 read-write DISCRITAXIRUW Disable-Critical-AXI-Read-Under-Write [27:27] 0 Normal operation 1 AXI reads to Device memory and exclusive reads to shared memory are not initiated on the M-AXI read address channel until all outstanding writes on the M- AXI interface are complete DISGSO Disable gather and scatter optimization for contiguous accesses [18:18] DISDI Disable dual-issue features [17:16] 0 Full dual-issue, if DISFOLD is set to 0 1 Disable dual-issue of arithmetic instructions 2 Disable lane swapping 3 Disable dual-issue of arithmetic instructions and lane swapping DISCRITAXIRUR Disable critical AXI Read-Under-Read [15:15] 0 Normal operation 1 AXI reads to Device memory and exclusive reads to shared memory are not initiated on the M-AXI read address channels if there are any outstanding reads on the M-AXI DISITMATBFLUSH Determines whether Instrumentation Trace Macrocell (ITM) or Data Watchpoint and Trace (DWT) ATB flush is disabled [12:12] 0 Normal operation 1 ITM or DWT ATB flush is disabled DISNWAMODE Determines whether no write allocate mode is disabled [11:11] 0 Normal operation 1 No write allocate mode is disabled FPEXCODIS Determines whether floating-point exception outputs are disabled [10:10] 0 Normal operation 1 Floating-point exception outputs are disabled DISOLAP Disable overlapping of all instructions [7:7] DISOLAPS Disable overlapping of scalar-only instructions [6:6] DISLO Disable low overhead loops [4:4] 0 Low overhead loops enabled 1 Low overhead loops disabled DISFOLD Determines whether dual-issue functionality is disabled [2:2] 0 Normal operation 1 Dual-issue functionality is disabled DISMCYCINT Disables interruption of multi-cycle instructions [0:0] 0 Normal operation 1 Disables interruption of multi-cycle instructions Coprocessor Power Control Register CPPWR Specifies whether coprocessors are permitted to enter a non-retentive power state 0x8 read-write SUS11 If the value of this bit is not programmed to the same value as the SUS10 field, then the value is unknown. [23:23] SU11 If the value of this bit is not programmed to the same value as the SU10 field, then the value is unknown. [22:22] SUS10 This bit indicates and allows modification of whether the SU10 field can be modified from Non-secure state. [21:21] 0 The SU10 field is accessible from both Security states 1 The SU10 field is only accessible from the Secure state SU10 This bit indicates and allows modification of whether the state associated with the floating-point and M-profile Vector Extension (MVE) functionality is permitted to become UNKNOWN. [20:20] 0 The floating-point and M-profile Vector Extension (MVE) state is not permitted to become unknown 1 The floating-point and M-profile Vector Extension (MVE) state is permitted to become unknown SUS7 This field indicates and allows modification of whether the SU7 field can be modified from Non-secure state [15:15] 0 The SU7 field is accessible from both Security states 1 The SU7 field is only accessible from the Secure state SU7 This field indicates and allows modification of whether the state associated with coprocessor 7 is permitted to become unknown [14:14] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS6 This field indicates and allows modification of whether the SU6 field can be modified from Non-secure state [13:13] 0 The SU6 field is accessible from both Security states 1 The SU6 field is only accessible from the Secure state SU6 This field indicates and allows modification of whether the state associated with coprocessor 6 is permitted to become unknown [12:12] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS5 This field indicates and allows modification of whether the SU5 field can be modified from Non-secure state [11:11] 0 The SU5 field is accessible from both Security states 1 The SU5 field is only accessible from the Secure state SU5 This field indicates and allows modification of whether the state associated with coprocessor 5 is permitted to become unknown [10:10] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS4 This field indicates and allows modification of whether the SU4 field can be modified from Non-secure state [9:9] 0 The SU4 field is accessible from both Security states 1 The SU4 field is only accessible from the Secure state SU4 This field indicates and allows modification of whether the state associated with coprocessor 4 is permitted to become unknown [8:8] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS3 This field indicates and allows modification of whether the SU3 field can be modified from Non-secure state [7:7] 0 The SU3 field is accessible from both Security states 1 The SU3 field is only accessible from the Secure state SU3 This field indicates and allows modification of whether the state associated with coprocessor 3 is permitted to become unknown [6:6] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS2 This field indicates and allows modification of whether the SU2 field can be modified from Non-secure state [5:5] 0 The SU2 field is accessible from both Security states 1 The SU2 field is only accessible from the Secure state SU2 This field indicates and allows modification of whether the state associated with coprocessor 2 is permitted to become unknown [4:4] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS1 This field indicates and allows modification of whether the SU1 field can be modified from Non-secure state [3:3] 0 The SU1 field is accessible from both Security states 1 The SU1 field is only accessible from the Secure state SU1 This field indicates and allows modification of whether the state associated with coprocessor 1 is permitted to become unknown [2:2] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SUS0 This field indicates and allows modification of whether the SU0 field can be modified from Non-secure state [1:1] 0 The SU0 field is accessible from both Security states 1 The SU0 field is only accessible from the Secure state SU0 This field indicates and allows modification of whether the state associated with coprocessor 0 is permitted to become unknown [0:0] 0 The coprocessor state is not permitted to become unknown 1 The coprocessor state is permitted to become unknown SYSTICK SysTick Timer 0xE000E010 0x0 0x10 registers SysTick Control and Status Register SYST_CSR Controls and provides status date for the SysTick timer 0x0 read-write COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register [16:16] 0 Timer has not counted to 0 1 Timer has counted to 0 CLKSOURCE Selects the SysTick timer clock source [2:2] 0 External reference clock 1 Processor clock TICKINT Enables SysTick exception request [1:1] 0 Counting down to zero does not assert the SysTick exception request 1 Counting down to zero asserts the SysTick exception request ENABLE Enables the counter [0:0] 0 Counter disabled 1 Counter enabled SysTick Reload Value Register SYST_RVR Specifies the SysTick timer counter reload value 0x4 read-write RELOAD Value to load into the SYST_CVR when the counter is enabled and when it reaches 0 [23:0] SysTick Current Value Register SYST_CVR Contains the current value of the SysTick counter 0x8 read-write CURRENT Current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0. [23:0] SysTick Calibration value Register SYST_CALIB Indicates the SysTick calibration value and parameters for the selected Security state 0xC read-only NOREF Indicates whether the device provides a reference clock to the processor [31:31] 0 Reference clock provided 1 No reference clock provided SKEW Indicates whether the TENMS value is exact [30:30] 0 TENMS value is exact 1 TENMS value is inexact, and has a rounding error of +/- 0.5 of one LSB TENMS Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. [23:0] CMO Cache Maintenance Operations 0xE000EF50 0x0 0x2C registers Instruction Cache Invalidate All to PoU ICIALLU Invalidates all instruction caches to Point of Unification (PoU) 0x0 write-only Ignored The value written to this field is ignored [31:0] Instruction Cache line Invalidate by Address to PoU ICIMVAU Invalidates instruction cache lines by address to Point of Unification (PoU) 0x8 write-only ADDRESS Writing to this field initiates the maintenance operation for the address that is written [31:0] Data Cache line Invalidate by Address to PoC DCIMVAC Invalidates data or unified cache lines by address to Point of Coherency (PoC) 0xC write-only ADDRESS Writing to this field initiates the maintenance operation for the address that is written [31:0] Data Cache line Invalidate by Set/Way DCISW Invalidates instruction cache lines by address to Point of Unification (PoU) 0x10 write-only SetWay Cache set/way. Contains two fields: Way, bits[31:32-A], the number of the way to operate on. Set, bits[B-1:L], the number of the set to operate on. [31:4] Level Cache level. This field is 0b000. [3:1] Data cache clean by address to the PoU DCCMVAU Cleans data or unified cache lines by address to Point of Unification (PoU) 0x14 write-only ADDRESS Writing to this field initiates the maintenance operation for the address that is written [31:0] Data cache line clean by address to the PoC DCCMVAC Cleans data or unified cache lines by address to Point of Unification (PoC) 0x18 write-only ADDRESS Writing to this field initiates the maintenance operation for the address that is written [31:0] Data Cache Clean line by Set/Way DCCSW Cleans data or unified cache line by set/way 0x1C write-only SetWay Contains two fields: Way, bits [31:32-A], the number of the way to operate on. Set, bits [B-1:L], the number of the set to operate on. [31:4] Level Cache level. This field is 0b000 [3:1] Data Cache Clean and Invalidate by Address to the PoC DCCIMVAC Cleans data or unified cache lines by address to Point of Coherency (PoC) 0x20 write-only ADDRESS Writing to this field initiates the maintenance operation for the address that is written [31:0] Data Cache Clean and Invalidate by Set/Way DCCISW Cleans and invalidates data or unified cache line by set/way 0x24 write-only SetWay Contains two fields: Way, bits[31:32-A], the number of the way to operate on. Set, bits[B-1:L], the number of the set to operate on. [31:4] Level Cache level. This field is 0b000. [3:1] Branch Predictor Invalidate All BPIALL Invalidates all entries from branch predictors 0x28 write-only Ignored The value written to this field is ignored [31:0] SAU Security Attribution Unit 0xE000EDD0 0x0 0x1C registers Security Attribution Unit Control Register SAU_CTRL Allows enabling of the Security Attribution Unit (SAU) 0x0 read-write ALLNS When SAU_CTRL.ENABLE is 0 this bit controls whether the memory is marked as Non-secure or Secure [1:1] 0 Memory is marked as Secure and is not Non-secure callable 1 Memory is marked as Non-secure ENABLE Enables the (SAU) [0:0] 0 Unit is disabled 1 Unit is enabled Security Attribution Unit Type Register SAU_TYPE Indicates the number of regions implemented by the Security Attribution Unit (SAU) 0x4 read-only SREGION The number of implemented (SAU) regions [7:0] Security Attribution Unit Region Number Register SAU_RNR Selects the region currently accessed by SAU_RBAR and SAU_RLAR 0x8 read-write REGION Indicates the Security Attribution Unit (SAU) region accessed by SAU_RBAR and SAU_RLAR [7:0] Security Attribution Unit Region Base Address Register SAU_RBAR Provides indirect read and write access to the base address of the currently selected Security Attribution Unit (SAU) region 0xC read-write BADDR Holds bits[31:5] of the base address for the selected (SAU) region [31:5] Security Attribution Unit Region Limit Address Register SAU_RLAR Provides indirect read and write access to the limit address of the currently selected Security Attribution Unit (SAU) region 0x10 read-write LADDR Holds bits[31:5] of the limit address for the selected (SAU) region [31:5] NSC Controls whether Non-secure state is permitted to execute an SG instruction from this region [31:5] 0 Region is not Non-secure callable 1 Region is Non-secure callable ENABLE (SAU) region enable [31:5] 0 Region is disabled 1 Region is enabled Secure Fault Status Register SFSR Provides information about any security related faults 0x14 read-write LSERR Sticky flag indicating that an error occurred during lazy state activation or deactivation [7:7] 0 Error has not occurred 1 Error has occurred SFARVALID This bit is set when the SFAR register contains a valid value [6:6] 0 SFAR content not valid 1 SFAR content valid LSPERR Sticky flag indicating that an Security Attribution Unit (SAU) or Implementation Defined Attribution Unit (IDAU) violation occurred during the lazy preservation of floating-point state [5:5] 0 Error has not occurred 1 Error has occurred INVTRAN Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory [4:4] 0 Error has not occurred 1 Error has occurred AUVIOL Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure [3:3] 0 Error has not occurred 1 Error has occurred INVER Indicates EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state [2:2] 0 Error has not occurred 1 Error has occurred INVIS Indicates the integrity signature in an exception stack frame is found to be invalid during the unstacking operation [1:1] 0 Error has not occurred 1 Error has occurred INVEP Inidcates a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state [0:0] 0 Error has not occurred 1 Error has occurred Secure Fault Address Register SFAR Shows the address of the memory location that caused a security violation 0x18 read-write MPU Memory Protection Unit 0xE000ED90 0x0 0x34 registers MPU Type Register MPU_TYPE Indicates whether the MPU is present, and if so, how many regions it supports 0x0 read-only DREGION Number of regions supported by the MPU [15:8] 0 0 regions if your device does not include the MPU 4 4 regions if your device includes the MPU 8 8 regions if your device includes the MPU 12 12 regions if your device includes the MPU 16 16 regions if your device includes the MPU SEPARATE Indicates support for unified or separate instructions and data address regions [0:0] 0 Unified MPU Control Register MPU_CTRL Enables the MPU 0x4 read-write PRIVDEFENA Enables privileged software access to the default memory map [2:2] 0 Disables use of the default memory map. Any memory access to a location that is not covered by any enabled region causes a fault. 1 Enables use of the default memory map as a background region for privileged software accesses. HFNMIENA Enables the operation of MPU during HardFault and NMI handlers [1:1] 0 MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit 1 The MPU is enabled during HardFault and NMI handlers ENABLE Enables the MPU [0:0] MPU is disabled 0 MPU is enabled 1 MPU Region Number Register MPU_RNR Selects the region currently accessed by MPU_RBAR and MPU_RLAR 0x8 read-write REGION Indicates the memory region accessed by MPU_RBAR and PMU_RLAR [7:0] MPU Region Base Address Register MPU_RBAR Defines the base address of the MPU region selected by the MPU_RNR 0xC read-write BASE Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against. [31:5] SH Defines the shareability domain of this region for Normal memory [4:3] 0 Non-shareable 1 unpredictable 2 Outer shareable 3 Inner Shareable AP Access permissions [2:1] 0 Read/write by privileged code only 1 Read/write by any privilege level 2 Read-only by privileged code only 3 Read-only by any privilege level XN Defines whether code can be executed from this region [0:0] 0 Execution only permitted if read permitted 1 Execution not permitted MPU Region Base Address Register Alias 1 MPU_RBAR_A1 Provides indirect read and write access to the MPU base address register 0x14 read-write MPU Region Base Address Register Alias 2 MPU_RBAR_A2 Provides indirect read and write access to the MPU base address register 0x18 read-write MPU Region Base Address Register Alias 3 MPU_RBAR_A3 Provides indirect read and write access to the MPU base address register 0x1C read-write MPU Region Limit Address Register MPU_RLAR Defines the limit address of the MPU region selected by the MPU_RNR 0x10 read-write LIMIT Contains bits[31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against. [31:5] PXN Defines whether code can be executed from this privileged region [4:4] 0 Execution only permitted if read permitted 1 Execution from a privileged mode is not permitted AttrIndx Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] EN Region enable [0:0] 0 Region disabled 1 Region enabled MPU Region Limit Address Register Alias 1 MPU_RLAR_A1 Provides indirect read and write access to the MPU limit address register 0x20 read-write MPU Region Limit Address Register Alias 2 MPU_RLAR_A2 Provides indirect read and write access to the MPU limit address register 0x24 read-write MPU Region Limit Address Register Alias 3 MPU_RLAR_A3 Provides indirect read and write access to the MPU limit address register 0x28 read-write MPU Memory Attribute Indirection Register 0 MPU_MAIR0 Provides the memory attribute encodings corresponding to the AttrIndex values 0x30 read-write Attr3 Memory attribute encoding for MPU regions with an AttrIndex of 3 [31:24] Attr2 Memory attribute encoding for MPU regions with an AttrIndex of 2 [23:16] Attr1 Memory attribute encoding for MPU regions with an AttrIndex of 1 [15:8] Attr0 Memory attribute encoding for MPU regions with an AttrIndex of 0 [7:0] MPU Memory Attribute Indirection Register 1 MPU_MAIR1 Provides the memory attribute encodings corresponding to the AttrIndex values 0x34 read-write Attr7 Memory attribute encoding for MPU regions with an AttrIndex of 7 [31:24] Attr6 Memory attribute encoding for MPU regions with an AttrIndex of 6 [23:16] Attr5 Memory attribute encoding for MPU regions with an AttrIndex of 5 [15:8] Attr4 Memory attribute encoding for MPU regions with an AttrIndex of 4 [7:0] MSC Memory System Control Registers 0xE001E000 0x0 0x19D00 registers Memory System Control Register MSCR Controls the memory system features specific to the processor 0x0 read-write DCCLEAN Indicates whether the data cache contains any dirty lines [16:16] 0 Level 1 (L1) data cache contains at least one dirty line 1 L1 data cache does not contain any dirty lines ICACTIVE Indicates whether the L1 instruction cache is active [13:13] 0 L1 instruction cache is inactive 1 L1 instruction cache is active DCACTIVE Indicates whether the L1 data cache is active [12:12] 0 L1 data cache is inactive 1 L1 data cache is active EVECCFAULT Enables asynchronous BusFault exceptions when data is lost on evictions [3:3] 0 Asynchronous BusFaults are not generated when evicting lines with multi-bit errors in the data 1 Asynchronous aborts are generated when evicting lines with multi-errors in the data FORCEWT Enables Forced Write-Through in the L1 data cache [2:2] 0 Force Write-Through is disabled 1 Force Write-Through is enabled ECCEN Indicates whether Error Correcting Code (ECC) is present and enabled [1:1] 0 ECC not present or not enabled 1 ECC present and enabled Prefetcher Control Register PFCR Controls the prefetcher 0x4 read-write MAX_LA This bit field is not used, and is RES0 [6:4] MIN_LA This bit field is not used, and is RES0 [3:1] ENABLE Prefetcher enable [0:0] 0 Prefetcher is disabled 1 Prefetcher is enabled ITCM Control Register ITCMCR Enable access to the Tightly Coupled Memories (TCMs) by software running on the processor 0x10 read-write SZ Indicates the size of the relevant TCM [6:3] 0 No TCM implemented 3 4KB 4 8KB 5 16KB 6 32KB 7 64KB 8 128KB 9 256KB 10 512KB 11 1MB 12 2MB 13 4MB 14 8MB 15 16MB EN TCM enable [0:0] 0 TCM disabled 1 TCM enabled DTCM Control Register DTCMCR Enable access to the Tightly Coupled Memories (TCMs) by software running on the processor 0x14 read-write SZ Indicates the size of the relevant TCM [6:3] 0 No TCM implemented 3 4KB 4 8KB 5 16KB 6 32KB 7 64KB 8 128KB 9 256KB 10 512KB 11 1MB 12 2MB 13 4MB 14 8MB 15 16MB EN TCM enable [0:0] 0 TCM disabled 1 TCM enabled P-AHB Control Register PAHBCR Enables accesses to Peripheral AHB (P-AHB) interface from software running on the processor 0x18 read-write SZ P-AHB size [3:1] 0 0MB. This implies that P-AHB disabled. 1 64MB 2 128MB 3 256MB 4 512MB EN P-AHB enable [0:0] 0 P-AHB disabled. 1 P-AHB enabled DCA Direct Cache Access 0xE001E200 0x0 0x10 registers Direct Data Cache Access Read Registers DCADCRR Read the data from the Level 1 (L1) data cache from the location that is determined by the DCADCLR registers 0x0 read-only VALID Valid state of the cache line [21:21] TAG Tag address. The number of significant bits of TAG depends on the cache size. [20:0] Direct Instruction Cache Access Read Registers DCAICRR Read the data from the Level 1 (L1) instruction cache from the location that is determined by the DCAICLR registers 0x4 read-only VALID Valid state of the cache line [21:21] TAG Tag address. The number of significant bits of TAG depends on the cache size. [20:0] Direct Data Cache Access Location Registers DCADCLR Set the location to be read from the Level 1 (L1) data cache 0x10 read-write WAY Cache way [31:30] SET Set index. The number of significant bits of SET depends on the cache size. [13:5] OFFSET Data offset [4:2] RAMTYPE RAM type [0:0] Tag RAM 0 Data RAM 1 Direct Instruction Cache Access Location Registers DCAICLR Set the location to be read from the Level 1 (L1) instruction cache 0x14 read-write WAY Cache way [30:30] SET Set index. The number of significant bits of SET depends on the cache size. [14:5] OFFSET Data offset [4:2] RAMTYPE RAM type [0:0] Tag RAM 0 Data RAM 1 TCM SecGate TCM Security Gate 0xE001E500 0x0 0x150 registers ITGU Control Registers ITGU_CTRL Main TCM Gate Unit (TGU) control registers for the ITCM 0x0 read-write DEREN Enable Slave AHB (S-AHB) error response for TGU fault [1:1] 0 Error response not enabled 1 Error response enabled DBFEN Enable data side BusFault for TGU fault [0:0] 0 BusFault not enabled 1 BusFault enabled ITGU Configuration Registers ITGU_CFG Provides access to configuration values for the ITGU 0x4 read-only PRESENT Determines if the TGU is present [31:31] 0 TGU not present 1 TGU is present NUMBLKS This value is used to calculate the number of TCM blocks [11:8] BLKSZ TGU block size in bytes [3:0] ITGU Look Up Table Registers ITGU_LUT%s Identifying the ITGU blocks as being Secure or Non-secure 0x10 read-write 16 4 DTGU Control Registers DTGU_CTRL Main TCM Gate Unit (TGU) control registers for the DTCM 0x100 read-write DEREN Enable Slave AHB (S-AHB) error response for TGU fault [1:1] 0 Error response not enabled 1 Error response enabled DBFEN Enable data side BusFault for TGU fault [0:0] 0 BusFault not enabled 1 BusFault enabled DTGU Configuration Registers DTGU_CFG Provides access to configuration values for the DTGU 0x104 read-only PRESENT Determines if the TGU is present [31:31] 0 TGU not present 1 TGU is present NUMBLKS This value is used to calculate the number of TCM blocks [11:8] BLKSZ TGU block size in bytes [3:0] DTGU Look Up Table Registers DTGU_LUT%s Identifying the DTGU blocks as being Secure or Non-secure 0x110 read-write 16 4 PMC Implementation defined power mode control 0xE001E300 0x0 0x8 registers Core Power Domain Low Power State Register CPDLPSTATE Specifies the desired low-power states for core (PDCORE), Extension Processing Unit (PDEPU), and RAM (PDRAMS) power domains 0x0 read-write RLPSTATE Power-on state for PDRAMS power domain [9:8] 0 On 3 Off ELPSTATE Type of low-power state for PDEPU [5:4] 0 On 1 On, but the clock is off 2 Ret 3 Off CLPSTATE Type of low-power state for PDCORE [1:0] 0 On 1 On, but the clock is off 2 Ret 3 Off Debug Power Domain Low Power State Register DPDLPSTATE Specifies the desired low-power states for the debug (PDDEBUG) power domain 0x4 read-write DLPSTATE Type of low-power state for PDDEBUG [1:0] 0 On 1 On, but the clock is off 2 Reserved. Treated as ON, but clock OFF. 3 Off ERRBNK Implementation defined error banking 0xE001E100 0x0 0x8 registers Instruction Cache Error Bank Register IEBR0 Record errors that occur during memory accesses to the L1 instruction cache 0x0 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] BANK Indicates which RAM bank to use [16:16] Tag RAM 0 Data RAM 1 LOCATION.WAY Indicates the location in the L1 instruction cache RAM, way [15:15] LOCATION.INDEX Indicates the location in the L1 instruction cache RAM, index [14:5] LOCATION.LWO Indicates the location in the L1 instruction cache RAM, line word offset [4:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid Instruction Cache Error Bank Register IEBR1 Record errors that occur during memory accesses to the L1 instruction cache 0x4 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] BANK Indicates which RAM bank to use [16:16] 0 Tag RAM 1 Data RAM LOCATION.WAY Indicates the location in the L1 instruction cache RAM, way [15:15] LOCATION.INDEX Indicates the location in the L1 instruction cache RAM, index [14:5] LOCATION.LWO Indicates the location in the L1 instruction cache RAM, line word offset [4:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid Data Cache Error Bank Register DEBR0 Record errors that occur during memory accesses to the L1 data cache 0x10 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] TYPE Indicates the error type [17:17] 0 Single-bit error 1 Multi-bit error BANK Indicates which RAM bank to use [16:16] 0 Tag RAM 1 Data RAM LOCATION.WAY Indicates the location in the L1 instruction cache RAM, way [15:14] LOCATION.INDEX Indicates the location in the L1 instruction cache RAM, index [13:5] LOCATION.LWO Indicates the location in the L1 instruction cache RAM, line doubleword offset [4:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid Data Cache Error Bank Register DEBR1 Record errors that occur during memory accesses to the L1 data cache 0x14 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] TYPE Indicates the error type [17:17] 0 Single-bit error 1 Multi-bit error BANK Indicates which RAM bank to use [16:16] 0 Tag RAM 1 Data RAM LOCATION.WAY Indicates the location in the L1 instruction cache RAM, way [15:14] LOCATION.INDEX Indicates the location in the L1 instruction cache RAM, index [13:5] LOCATION.LWO Indicates the location in the L1 instruction cache RAM, line doubleword offset [4:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid TCM Error Bank Register TEBR0 Record the location of errors in the TCM 0x20 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] POISON Indicates whether a BusFault is generated or not [28:28] 0 Load or non-word store to an address that hits this TEBR gets a BusFault 1 Load or non-word store to an address that hits this TEBR accesses the corresponding TEBRDATA register and does not get a BusFault TYPE Indicates the error type [27:27] 0 Single-bit error 1 Multi-bit error BANK Indicates which RAM bank to use [26:24] 0 DTCM0 1 DTCM1 2 DTCM2 3 DTCM3 4 ITCM LOCATION Indicates the physical location in the data cache RAM [23:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid Data for TCU Error Bank Register 0 TEBRDATA0 Provides storage for corrected data that is associated with an error 0x24 read-only TCM Error Bank Register 1 TEBR1 Record the location of errors in the TCM 0x28 read-write SWDEF Error detection logic sets this field to 0b00 on a new allocation and on Cold reset [31:30] POISON Indicates whether a BusFault is generated or not [28:28] 0 Load or non-word store to an address that hits this TEBR gets a BusFault 1 Load or non-word store to an address that hits this TEBR accesses the corresponding TEBRDATA register and does not get a BusFault TYPE Indicates the error type [27:27] 0 Single-bit error 1 Multi-bit error BANK Indicates which RAM bank to use [26:24] 0 DTCM0 1 DTCM1 2 DTCM2 3 DTCM3 4 ITCM LOCATION Indicates the physical location in the data cache RAM [23:2] LOCKED Indicates whether the location is locked or not [1:1] 0 Location is not locked and available for hardware to allocate 1 Software has locked the location and hardware is not allowed to allocate to this entry VALID Indicates whether the entry is valid or not [0:0] 0 Entry is invalid 1 Entry is valid Data for TCU Error Bank Register 1 TEBRDATA1 Provides storage for corrected data that is associated with an error 0x2C read-only PCI Implementation defined processor configuration information 0xE001E700 0x0 0x8 registers Processor configuration information selection register CFGINFOSEL Selects the configuration information which can then be read back using CFGINFORD 0x0 write-only Processor configuration information read data register CFGINFORD Displays the configuration information that the CFGINFOSEL register selects 0x4 read-only RAS Ext Reliability, Availability, and Serviceability (RAS) Extension 0xE0005000 0x0 0x9F08 registers Error Record Feature Register ERRFR0 Describes the RAS features that are supported 0x0 read-only UE Enable Uncorrected error (UE) reporting as an external abort [9:8] 1 External abort response for uncorrected errors enabled ED Error reporting and logging [1:0] 1 Reporting and logging always enabled ERRCTRL0 ERRCTRL0 This register is RES0 0x8 read-only Error Record Primary Status Register ERRSTATUS0 Contains information about the Reliability, Availability, and Serviceability (RAS) event that is currently logged in record 0 0x10 read-write AV Address valid [31:31] 0 ERRADDR0 is not valid 1 ERRADDR0 is valid V Status valid [30:30] 0 ERRSTATUS0 is not valid 1 ERRSTATUS0 is valid UE Uncorrected errors (UEs) [29:29] 0 No uncorrectable errors detected 1 At least one uncorrectable error is detected ER BusFault caused by RAS event [28:28] 0 No BusFault caused by RAS event has occurred 1 BusFault caused by RAS event has occurred OF RAS events occurred since the last time ERRSTATUS0.V was cleared [27:27] 0 At most one RAS event has occurred since the last time ERRSTATUS0.V was cleared 1 At least two RAS events have occurred since the last time ERRSTATUS.V was cleared MV Miscellaneous registers valid [26:26] 0 ERRMISC0 is not valid 1 ERRMISC0 is valid CE Corrected errors [25:24] 0 Corrected errors (CEs) have not been detected 1 At least one Corrected error (CE) has been detected DE Deferred errors [23:23] 0 No errors were deferred 1 At least one error was deferred UET Uncorrectable error type [21:20] 0 Uncontainable error, Unrecoverable error (UC) 1 Uncorrectable, Recoverable error (UER) SERR Architecturally-defined primary error code [7:0] 0 No error 2 TCM ECC error 6 L1 data cache or instruction cache data RAM ECC error 7 L1 data cache or instruction cache tag RAM ECC error Error Record Address Registers ERRADDR0 Contains information about the address of the Reliability, Availability, and Serviceability (RAS) event in record 0 0x18 read-only Error Record Address Registers ERRADDR20 Contains information about the address of the Reliability, Availability, and Serviceability (RAS) event in record 0 0x1C read-only SI Security information incorrect [30:30] 1 NS bit is not valid AI Address incorrect [29:29] 0 PADDR is valid 1 PADDR is not valid Error Record Miscellaneous Register 0 ERRMISC00 This register is RES0 0x20 read-only Error Record Miscellaneous Register 10 ERRMISC10 Error syndrome register for the event in record 0 0x24 read-only TYPE type of Reliability, Availability, and Serviceability (RAS) event logged [1:0] 0 Level 1 (L1) instruction cache Error Correcting Code (ECC) 1 L1 data cache ECC 2 TCM ECC found by load or store executed by the processor 3 TCM ECC found by access from Slave AHB (S-AHB) Error Record Miscellaneous Register 20 ERRMISC20 This register is RES0 0x28 read-only Error Record Miscellaneous Register 30 ERRMISC30 This register is RES0 0x2C read-only Error Record Miscellaneous Register 40 ERRMISC40 This register is RES0 0x30 read-only Error Record Miscellaneous Register 50 ERRMISC50 This register is RES0 0x34 read-only Error Record Miscellaneous Register 60 ERRMISC60 This register is RES0 0x38 read-only Error Record Miscellaneous Register 70 ERRMISC70 This register is RES0 0x3C read-only Fault Group Status Register ERRGSR0 Summarizes the valid error records 0xE00 read-only ERR0 Error record 0 is valid [0:0] Error Record Device ID Register ERRDEVID Contains the number of error records that an implementation supports 0xFC8 read-only NUM Maximum Error Record Index+1 [15:0] Fault Status Register RFSR Reports the fault status of Reliability, Availability, and Serviceability (RAS) related faults from Error Correcting Code (ECC) errors that are detected in the Level 1 (L1) instruction cache, data cache, and TCM 0x9F04 read-write Valid Indicates whether the register is valid [31:31] IS Indicates the type of RAS exception that has occurred [30:16] 0 L1 instruction cache ECC 1 L1 data cache ECC 2 TCM ECC UET Error type [1:0] 0 Uncontainable error (UC). RAS exception is imprecise. 1 Recoverable error (UER). RAS exception is precise. PMU Ext Performance Monitoring Unit Extension 0xE0003000 0x0 0x4000 registers Performance Monitoring Unit Event Counter Register PMU_EVCNTR%s Holds performance counter, which count events 0x0 read-write 8 4 Counter The counter counts whenever the selected event occurs, and either of the following conditions are met: SecureNoninvasiveDebugAllowed()==TRUE; The source of the event is Non-secure and NoninvasiveDebugAllowed()==TRUE. [15:0] Performance Monitoring Unit Cycle Counter Register PMU_CCNTR Holds the value of the cycle counter, which counts processor clock cycles 0x7C read-write Performance Monitoring Unit Event Type and Filter Register PMU_EVTYPER%s Configures the event counter 0x400 read-write 8 4 evtCount The event number of the event that is counted by event counter PMU_EVCNTR0-7 [15:0] PMU_CCFILTR PMU_CCFILTR This register is RES0 0x47C read-write Performance Monitoring Unit Count Enable Set Register PMU_CNTENSET Enables the PMU_CCNTR register and PMU_EVCNTR0-7 registers 0xC00 read-write C PMU_CCNTR enable bit [31:8] Pn Event counter PMU_EVCNTR0-7 enable bit [7:0] Performance Monitoring Unit Count Enable Clear Register PMU_CNTENCLR Disables the PMU_CCNTR register and PMU_EVCNTR0-7 registers 0xC20 read-write C PMU_CCNTR disable bit [31:8] Pn Event counter PMU_EVCNTR0-7 enable bit [7:0] Performance Monitoring Unit Interrupt Enable Set Register PMU_INTENSET Enables the generation of interrupt requests on overflows from the PMU_CCNTR, and the event counter, PMU_EVCNTR. 0xC40 read-write C PMU_CCNTR interrupt request enable bit [31:8] Pn Event counter overflow interrupt request disable bit for PMU_EVCNTR0-7 [7:0] Performance Monitoring Unit Interrupt Enable Clear Register PMU_INTENCLR Disables the generation of interrupt requests on overflows from the PMU_CCNTR, and the event counters, PMU_EVCNTR 0xC60 read-write C PMU_CCNTR overflow interrupt request disable bit [31:8] Pn Event counter overflow interrupt request enable bit for PMU_EVCNTRn. Enable the overflow interrupt for PMU_EVCNTR0-7 [7:0] Performance Monitoring Unit Overflow Flag Status Clear Register PMU_OVSCLR Contains the state of the overflow bit for the PMU_CCNTR, and each of the implemented event counters, PMU_EVCNTRn. Writing to this register clears these bits. 0xC80 read-write C PMU_CCNTR overflow bit. Clears the PMU_CCNTR overflow bit. [31:31] Pn Event counter overflow clear bit for PMU_EVCNTRn. Clears the PMU_EVCNTRn overflow bit [30:0] Performance Monitoring Unit Software Increment Register PMU_SWINC Increments a counter that is configured to count the software increment event, event 0x00 0xCA0 write-only Pn Event counter software increment bit for PMU_EVCNTRn. An event counter n, configured for SW_INCR events, increments on every write to bit n of this field. [7:0] Performance Monitoring Unit Overflow Flag Status Set Register PMU_OVSSET Performance Monitoring Unit Overflow Flag Status Set Register 0xCC0 read-write C PMU_CCNTR overflow bit. Sets the overflow status for PMU_CCNTR. [31:31] Pn Event counter overflow set bit for PMU_EVCNTRn. Sets the overflow status for PMU_EVCNTRn. [30:0] Performance Monitoring Unit Type Register PMU_TYPE Contains information regarding what the PMU supports 0xE00 read-only TRO Trace-on-overflow not supported. This bit is 0b0. [23:23] FZO Freeze-on-overflow is supported. This bit is 0b1. [21:21] CC A dedicated cycle counter is present. This bit is 0b1. [14:14] SIZE Size of counters. This field determines the spacing of counters in the memory-map. This field is 0b011111. [13:8] N Number of counters implemented in addition to the cycle counter, PMU_CCNTR. This field is set to 0b00001000, indicating that 8 16-bit event counters are present in addition to PMU_CCNTR. [7:0] Performance Monitoring Unit Control Register PMU_CTRL Configures and controls the PMU 0xE04 read-write TRO Trace-on-overflow not supported in Cortex-M55. Therefore, this bit is 0b0. [11:11] FZO Freeze-on-overflow. Stops events being counted once PMU_OVSCLR or PMU_OVSSET is non-zero. [9:9] 0 No effect 1 While PMU_OVSCLR or PMU_OVSSET is non-zero, event counters do not count events. DP Disable cycle counter when event counting is prohibited [5:5] C Cycle counter reset. Reset the PMU_CCNTR counter. [2:2] 0 No action 1 Reset PMU_CCNTR to zero P Event counter reset [1:1] 0 No action 1 Reset all event counters, except PMU_CCNTR, to zero E Enable. Enable the event counters. [0:0] 0 All counters, including PMU_CCNTR, are disabled 1 PMU_CNTENSET enable all counters Performance Monitoring Unit Authentication Status Register PMU_AUTHSTATUS Provides information about the state of the implementation defined authentication interface for the PMU 0xFB8 read-only SUNID Secure Unprivileged Non-invasive Debug Allowed. Indicates that Unprivileged Non-invasive Debug is allowed for the Secure state. [23:22] 0 Unprivileged Non-invasive debug not implemented 2 Secure Non-invasive debug prohibited 3 Secure Non-invasive debug allowed in unprivileged mode SUID Secure Unprivileged Invasive Debug Allowed. Indicates that Unprivileged Invasive Debug is allowed for the Secure state. [21:20] 0 Unprivileged Invasive debug not implemented 2 Secure Invasive debug prohibited 3 Secure Invasive debug allowed in unprivileged mode NSUNID Non-secure Unprivileged Non-invasive Debug Allowed. Indicates that Unprivileged Non-invasive Debug is allowed for the Non-secure state. [19:18] 0 Unprivileged Non-invasive debug not implemented 2 Non-secure Non-invasive debug prohibited 3 Non-secure Non-invasive debug allowed in unprivileged mode NSUID Non-secure Unprivileged Invasive Debug Allowed. Indicates that Unprivileged Halting Debug is allowed for the Non-secure state. [17:16] 0 Unprivileged halting debug not implemented 2 Non-secure halting debug prohibited 3 Non-secure halting debug allowed in unprivileged mode SNID Secure Non-invasive Debug. Indicates whether Secure Non-invasive debug is implemented and allowed. [7:6] 0 Security Extension not implemented 2 Security Extension implemented and Secure Non-invasive debug not allowed 3 Security Extension implemented and Secure Non-invasive debug allowed SID Secure Invasive Debug. Indicates whether Secure invasive debug is implemented and allowed. [5:4] 0 Security Extension not implemented 2 Security Extension implemented and Secure invasive debug not allowed 3 Security Extension implemented and Secure invasive debug allowed NSNID Non-secure Non-invasive Debug. Indicates whether Non-secure Non-invasive debug is allowed. [3:2] 2 Non-secure Non-invasive debug not allowed 3 Non-secure Non-invasive debug allowed NSID Non-secure Invasive Debug. Indicates whether Non-secure invasive debug is allowed. [1:0] 2 Non-secure invasive debug not allowed 3 Non-secure invasive debug allowed Performance Monitoring Unit Device Architecture Register PMU_DEVARCH Identifies the programmers model architecture of the PMU 0xFBC read-only ARCHITECT Defines the architecture of the component. For the PMU, it is Arm Limited. Bits[31:28] are the JEP 106 continuation code, 0x4, and bits [27:21] are the JEP 106 ID code, 0x3B. [31:21] PRESENT Determines the presence of DEVARCH. When set to 1, indicates that the DEVARCH is present. This bit reads as 0x1. [20:20] REVISION Defines the architecture revision. For the PMU, the revision defined by Armv8.1‑M is 0x2. [19:16] ARCHID Defines this part to be an Armv8‑M debug component. For the PMU, bits [15:12] are 0x0, bits [11:0] are 0xA06. [15:0] Performance Monitoring Unit Device Type Register PMU_DEVTYPE Indicates to a debugger that the PMU is a part of the processor interface 0xFCC read-only SUB Subtype. This field reads as 0x1. [7:4] MAJOR Major type. This field reads as 0x6. [3:0] Performance Monitoring Unit Peripheral Identification Register 4 PMU_PIDR4 Provides information to identify the PMU. 0xFD0 read-only SIZE Size of the component. This field is RAZ. [7:4] DES_2 Designer, JEP 106 continuation code, least significant nibble. For Arm Limited, this field is 0x4. [3:0] Performance Monitoring Unit Peripheral Identification Register 0 PMU_PIDR0 Provides information to identify the PMU 0xFE0 read-only PART_0 Part number, least significant byte. This field reads 0x22. [7:4] Performance Monitoring Unit Peripheral Identification Register 1 PMU_PIDR1 Provides information to identify the PMU 0xFE4 read-only DES_0 Designer, least significant nibble of JEP 106 ID code. For Arm Limited, this field 0xB. [7:4] PART_1 Part number, most significant nibble. This field is 0xD. [3:0] Performance Monitoring Unit Peripheral Identification Register 2 PMU_PIDR2 Provides information to identify the PMU. 0xFE8 read-only REVISION Part major revision. Parts can also use this field to extend Part number to 16-bits. This field reads as 0x0000. [7:4] JEDEC Indicates a JEP10 identity code. This is RAO. [3:3] DES_1 Designer, most significant bits of JEP 106 ID code. For Arm Limited, this field reas as 0b011. [2:0] Performance Monitoring Unit Peripheral Identification Register 3 PMU_PIDR3 Provides information to identify the PMU 0xFEC read-only REVAND Part minor revision. This field is 0x0000. [7:4] CMOD Customer modified. This field is 0x0000. [2:0] Performance Monitoring Unit Component Identification Register 0 PMU_CIDR0 Provides information to identify a PMU component 0xFF0 read-only PRMBL_0 Preamble. This field reads 0x0D. [7:0] Performance Monitoring Unit Component Identification Register 1 PMU_CIDR1 Provides information to identify a PMU component 0xFF4 read-only CLASS Component class. This field reads 0x0. [7:4] PRMBL_1 Preamble. This field reads 0x0. [3:0] Performance Monitoring Unit Component Identification Register 2 PMU_CIDR2 Provides information to identify a PMU component 0xFF8 read-only PRMBL_2 Preamble. This field reads 0x05. [3:0] Performance Monitoring Unit Component Identification Register 3 PMU_CIDR3 Provides information to identify a PMU component 0xFFC read-only PRMBL_3 Preamble. This field reads 0xB1. [3:0] EWIC Ctrl External Wakeup Interrupt Controller 0xE0047000 0x0 0x800 registers EWIC Control Register EWIC_CR The main External Wakeup Interrupt Controller (EWIC) control register 0x0 read-write EN Enable [0:0] 0 EWIC is disabled, events are not pended, and WAKEUP is not signaled 1 EWIC is enabled, events are pended, and WAKEUP is signaled EWIC Automatic Sequence Control Register EWIC_ASCR Determines whether the processor generates APB transactions on entry and exit from Wakeup Interrupt Controller (WIC) sleep to set up the wakeup state in the External Wakeup Interrupt Controller (EWIC) 0x4 read-write ASPU The processor must use this value to decide whether any automatic EWIC accesses must be performed on transitioning from a low-power state [1:1] 0 No automatic sequence on power up 1 Automatic sequence on powerup ASPD The processor must use this value to decide whether any automatic EWIC accesses must be performed on transitioning to a low-power state [0:0] 0 No automatic sequence on entry to a low-power state 1 Automatic sequence on entry to a low-power state EWIC Clear Mask Register EWIC_CLRMASK Causes EWIC_MASKA and all the EWIC_MASKn registers to be cleared. The write data is ignored. This register is RAZ. 0x8 write-only EWIC Event Number ID Register EWIC_NUMID Returns the total number of events supported in the External Wakeup Interrupt Controller (EWIC) that have been configured during synthesis 0xC read-only NUMEVENT The number of events supported [15:0] EWIC Mask Registers EWIC_MASKA Defines the mask for special events and the EWIC_MASKn registers for external interrupt (IRQ) events 0x200 read-write EDBGREQ Mask for external debug request [2:2] NMI Mask for Non-Maskable Interrupt (NMI) [1:1] EVENT Mask for Wait For Exception (WFE) wakeup event [0:0] EWIC Mask Registers EWIC_MASK%s Defines the mask for special events and the EWIC_MASKn registers for external interrupt (IRQ) events 0x204 read-write 15 4 IRQ Masks for interrupts (nx32) to ((n+1)x32)-1 [31:0] EWIC Pend Event Registers EWIC_PENDA Indicate which events have been pended 0x400 read-only EDBGREQ External debug request is pended [2:2] NMI Non-Maskable Interrupt (NMI) is pended [1:1] EVENT Wait For Exception (WFE) wakeup event is pended [0:0] EWIC Pend Event Registers EWIC_PEND%s Indicate which events have been pended 0x404 read-write 15 4 IRQ Interrupts (nx32) to ((n+1)x32)-1 are pended. A write of zero to this field is ignored. [31:0] EWIC Pend Summary Register EWIC_PSR Indicates which EWIC_PENDn registers are non-zero 0x600 read-only NZ If EWIC_PSR.NZ[n+1] is set, then EWIC_PENDn is non-zero [15:1] NZA If EWIC_PSR.NZA set, then EWIC_PENDA is non-zero [0:0] EWIC IStat External Wakeup Interrupt Controller Interrupt Status Access 0xE001E400 0x0 0x504 registers Event Set Pending Register EVENTSPR Set pending events at wakeup that cannot be directly set in the Nested Vectored Interrupt Controller (NVIC) using the architecture programming model 0x0 write-only EDBGREQ Causes the processor to behave like an external debug request has occurred [2:2] 0 Ignored 1 Processor to behave like an external debug request has occurred NMI Causes the processor to behave like a Non-maskable Interrupt (NMI) has occurred [1:1] 0 Ignored 1 Processor to behave like a Non-maskable Interrupt (NMI) has occurred EVENT Causes the processor to behave like an RXEV event has occurred [1:1] 0 Ignored 1 Processor to behave like an RXEV event has occurred Wake-up Event Mask Register A EVENTMASKA Provides the events on sleep entry which cause the processor to wake up, including information about internal events 0x80 read-only EDBGREQ Mask for external debug request [2:2] NMI Mask for Non-Maskable Interrupt (NMI) [1:1] EVENT Sensitive to RXEV when in WFE sleep [0:0] Wake-up Event Mask Register %s EVENTMASK%s Provides the events on sleep entry which cause the processor to wake up, including information about external events 0x84 read-only 32 4 IRQ Masks for interrupts ((n-1)x32) to (nx32)-1. [31:0] EWIC CoreSight External Wakeup Interrupt Controller CoreSight registers 0xE0047F00 0x0 0x1000 registers EWIC Integration Mode Control Register EWIC_ITCTRL Used to dynamically switch between functional mode and integration mode. The EWIC does not support integration mode, and this register is RAZ. 0x0 read-only EWIC Claim Tag Set Register EWIC_CLAIMSET The EWIC_CLAIMSET register is used to set whether functionality is in use by a debug agent. The EWIC does not have any associated debug functionality, and this register is 0xF. 0xA0 read-write EWIC Claim Tag Clear Register EWIC_CLAIMCLR The EWIC_CLAIMCLR register is used to set whether functionality is in use by a debug agent. The EWIC does not have any associated debug functionality, and this register is 0x0. 0xA4 read-write EWIC Device Affinity Register 0 EWIC_DEVAFF0 The EWIC_DEVAFF0 register enables a debugger to determine whether the EWIC and the processor have an affinity with each other. The EWIC does not have any associated debug functionality, and this register is 0x80000000. 0xA8 read-only EWIC Device Affinity Register 1 EWIC_DEVAFF1 The EWIC_DEVAFF1 register enables a debugger to determine whether the EWIC and the processor have an affinity with each other. The EWIC does not have any associated debug functionality, and this register is 0x0. 0xAC read-only EWIC Software Lock Access Register EWIC_LAR The EWIC_LAR register controls software access to CoreSight components to reduce the likelihood of accidental access to the EWIC. The EWIC does not support software locking, and writing to this register has no affect. 0xB0 write-only EWIC Software Lock Status Register EWIC_LSR The EWIC_LSR register controls software access to CoreSight components to reduce the likelihood of accidental access to the EWIC. The EWIC does not support software locking, and this register is RAZ. 0xB4 read-only EWIC Authentication Status Register EWIC_AUTHSTATUS The EWIC_AUTHSTATUS register indicates whether the EWIC includes debug functionality. The EWIC is not a debug component, therefore, the EWIC_AUTHSTATIS register is RAZ. 0xB8 read-only EWIC Device Architecture Register EWIC_DEVARCH Identifies the architecture of the EWIC 0xBC read-only ARCHITECT_JEP106C Defines the architect of the component, JEP106 continuation code [31:28] ARCHITECT_JEP106I Defines the architect of the component, JEP106 identification code [27:21] PRESENT Indicates the presence of this register. This value is 0b1. [20:20] REVISION Architecture revision. This value is 0b0000. [19:16] ARCHID Returns a value that identifies the architecture of the component. This value is 0x0A07 corresponding to EWIC architecture. [15:0] EWIC Device Configuration Register 2 EWIC_DEVID2 The EWIC_DEVID2 indicates some capabilities of the EWIC. This register is RAZ/WI. 0xC0 read-only EWIC Device Configuration Register 1 EWIC_DEVID1 The EWIC_DEVID1 indicates some capabilities of the EWIC. This register is RAZ/WI. 0xC4 read-only EWIC Device Configuration Register EWIC_DEVID The EWIC_DEVID indicates some capabilities of the EWIC. This register is RAZ/WI. 0xC8 read-only EWIC Device Type Identifier Register, EWIC_DEVTYPE EWIC_DEVTYPE Provides part number information about the EWIC component to the debugger. 0xCC read-only SUB Sub type for the component device type. This field is set to 0b0000. [7:4] MAJOR Major type for the component device type. This field is set to 0b0000. [3:0] Peripheral Identification Register 4 EWIC_PIDR4 provides information about the memory size and JEP106 continuation code that the External Wakeup Interrupt Controller (EWIC) component uses 0xD0 read-only SIZE This field indicates the memory size that the EWIC uses. This field returns 0x0 indicating that the component uses an UNKNOWN number of 4KB blocks. [7:4] DES_2 JEP106 continuation code. Together with EWIC_PIDR2.DES_1 and EWIC_PIDR1.DES_0, they indicate the designer of the component, not the implementer, except where the two are the same. The reset value of this field is 0x4. [3:0] Peripheral Identification Register 5 EWIC_PIDR5 The register is reserved, RES0 0xD4 read-only Peripheral Identification Register 6 EWIC_PIDR6 The register is reserved, RES0 0xD8 read-only Peripheral Identification Register 7 EWIC_PIDR7 The register is reserved, RES0 0xDC read-only Peripheral Identification Register 0 EWIC_PIDR0 Indicates the EWIC component part number 0xE0 read-only PART_0 This field indicates the part number. When taken together with EWIC_PIDR1.PART_1, it indicates the component. The part number is selected by the designer of the component. [7:0] Peripheral Identification Register 1 EWIC_PIDR1 Indicates the EWIC component JEP106 continuation code and part number 0xE4 read-only DES_0 This field indicates the JEP106 identification code, bits[3:0]. Together, with EWIC_PIDR4.DES_2 and EWIC_PIDR2.DES_1, they indicate the designer of the component and not the implementer, except where the two are the same. The reset value is 0xB. [7:4] PART_1 This field indicates the part number, bits[11:8]. Taken together with EWIC_PIDR0.PART_0 it indicates the component. The part number is selected by the designer of the component. The reset value is 0xD. [3:0] Peripheral Identification Register 2 EWIC_PIDR2 Indicates the EWIC component revision number, JEDEC value, and part of the JEP106 continuation code 0xE8 read-only REVISION This field indicates the revision number of the EWIC component. It is an incremental value starting at 0x0 for the first design. The reset value is 0x0. [7:4] JEDEC This field is always 1, indicating that a JEDEC assigned value is used. [3:3] DES_1 This field is the JEP106 identification code, bits[6:4]. Together, with CTI_PIDR4.DES_2 and CTI_PIDR1.DES_0, they indicate the designer of the component and not the implementer, except where the two are the same. The reset value is 0b011. [2:0] Peripheral Identification Register 3 EWIC_PIDR3 Indicates minor errata fixes of the Cross Trigger Interface (CTI) component and if you have modified the behavior of the component 0xEC read-only REVAND This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is 0x0. [7:4] CMOD Customer modified. Where the component is reusable IP, this value indicates whether you have modified the behavior of the component. In most cases, this field is 0x0. [3:0] Component Identification Register 0 EWIC_CIDR0 Indicates the preamble 0xF0 read-only PRMBL_0 Preamble. This field returns 0x0D. [7:0] Component Identification Register 1 EWIC_CIDR1 indicates the component class and preamble 0xF4 read-only CLASS Component class. Returns 0x9, indicating this is a CoreSight component. [7:0] PRMBL_1 Preamble. This field returns 0x0. [7:0] Component Identification Register 2 EWIC_CIDR2 Indicates the preamble 0xF8 read-only PRMBL_2 Preamble. This field returns 0x05. [7:0] Component Identification Register 3 EWIC_CIDR3 Indicates the preamble 0xFC read-only PRMBL_3 Preamble. This field returns 0xB1. [7:0]