CM23 Cortex-M23 Core (Now) Current State CPU Registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 8 R9 General purpose register 9 9 R10 General purpose register 10 10 R11 General purpose register 11 11 R12 General purpose register 12 12 R13 SP R13 (SP) Stack pointer (SP) 13 R14 LR R14 (LR) Link register (LR) 14 R15 PC R15 (PC) Program counter (PC) 15 APSR Application program status register 21 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 GE Greater-than or equal flag 16 4 EPSR Exception program status register 22 ICI/IT HighBits Interruptible-continuable instruction bits (high bits) 25 2 ICI/IT LowBits Interruptible-continuable instruction bits (low bits) 10 6 T Thumb state bit 24 1 IPSR Interrupt program status register 23 ISR Number Interrupt service routine number 0 9 PriMask Priority mask register 24 PriMask Prevent the activation of all exceptions with configurable priority 0 1 BasePri Base priority mask register 25 BasePri Priority mask bits 8 8 FaultMask Fault mask register 26 FaultMask Prevent the activation of all exceptions except for NMI 16 1 Control Control register 27 SFPA Secure floating-point active 27 1 FPCA Context floating-point active 26 1 SPSEL Active stack pointer 25 1 nPRIV Thread mode privilege level 24 1 CycleCount Cycle count 65 Core (All) All CPU registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 8 R9 General purpose register 9 9 R10 General purpose register 10 10 R11 General purpose register 11 11 R12 General purpose register 12 12 R13 Stack pointer 13 R14 Link register 14 R15 Program counter 15 xPSR Program status register 16 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 T Thumb state bit 24 1 GE Greater-than or equal flag 16 4 ICI/IT HighBits Interruptible-continuable instruction bits (high bits) 25 2 ICI/IT LowBits Interruptible-continuable instruction bits (low bits) 10 6 ISR Number Interrupt service routine number 0 9 APSR Application program status register 21 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 GE Greater-than or equal flag 16 4 EPSR Exception program status register 22 ICI/IT HighBits Interruptible-continuable instruction bits (high bits) 25 2 ICI/IT LowBits Interruptible-continuable instruction bits (low bits) 10 6 T Thumb state bit 24 1 IPSR Interrupt program status register 23 ISR Number Interrupt service routine number 0 9 MSP_NS Main stack pointer (non-secure) 66 MSP_S Main stack pointer (secure) 68 PSP_NS Process stack pointer (non-secure) 67 PSP_S Process stack pointer (secure) 69 MSPLIM_NS Main stack pointer limit register (non-secure) 72 LIMIT Stack limit bits 3 29 MSPLIM_S Main stack pointer limit register (secure) 70 LIMIT Stack limit bits 3 29 PSPLIM_NS Process stack pointer limit register (non-secure) 73 LIMIT Stack limit bits 3 29 PSPLIM_S Process stack pointer limit register (secure) 71 LIMIT Stack limit bits 3 29 PRIMASK_NS Priority mask register (non-secure) 76 PriMask Prevent the activation of all exceptions with configurable priority 0 1 PRIMASK_S Priority mask register (secure) 81 PriMask Prevent the activation of all exceptions with configurable priority 0 1 BASEPRI_NS Base priority mask register (non-secure) 77 BasePri Priority mask bits 0 8 BASEPRI_S Base priority mask register (secure) 82 BasePri Priority mask bits 0 8 FAULTMASK_NS Fault mask register (non-secure) 78 FaultMask Prevent the activation of all exceptions except for NMI 0 1 FAULTMASK_S Fault mask register (secure) 83 FaultMask Prevent the activation of all exceptions except for NMI 0 1 CONTROL_NS Control register (non-secure) 79 SFPA Secure floating-point active 3 1 FPCA Context floating-point active 2 1 SPSEL Active stack pointer 1 1 nPRIV Thread mode privilege level 0 1 CONTROL_S Control register (secure) 84 SFPA Secure floating-point active 3 1 FPCA Context floating-point active 2 1 SPSEL Active stack pointer 1 1 nPRIV Thread mode privilege level 0 1 CycleCount Cycle count 65 Peripherals Memory-Mapped CPU Registers 32 RW unsigned int ITM Instrumentation Macrocell 0xE0000000 0x0 0x1000 registers ITM Component Identification Register 0 ITM_CIDR0 Provides CoreSight discovery information for the ITM 0xFF0 read-only PRMBL_0 CoreSight component identification preamble [7:0] ITM Component Identification Register 1 ITM_CIDR1 Provides CoreSight discovery information for the ITM 0xFF4 read-only CLASS CoreSight component class. See the CoreSight Architecture Specification [7:4] PRMBL_1 CoreSight component identification preamble [3:0] ITM Component Identification Register 2 ITM_CIDR2 Provides CoreSight discovery information for the ITM 0xFF8 read-only PRMBL_2 CoreSight component identification preamble [7:0] ITM Component Identification Register 3 ITM_CIDR3 Provides CoreSight discovery information for the ITM 0xFFC read-only PRMBL_3 CoreSight component identification preamble [7:0] ITM Device Architecture Register ITM_DEVARCH Provides CoreSight discovery information for the ITM 0xFBC read-only ARCHITECT Architect. Defines the architect of the component [31:21] JEP106 continuation code 0x4, ID code 0x3B. ARM Limited 571 PRESENT DEVARCH Present. Defines that the DEVARCH register is present [20:20] DEVARCH information present 1 REVISION Revision. Defines the architecture revision of the component [19:16] ITM architecture v2.0 0 ARCHVER Architecture Version. Defines the architecture version of the component [15:12] ITM architecture v2 1 ARCHPART Architecture Part. Defines the architecture of the component [11:0] ITM architecture 2561 ITM Device Type Register ITM_DEVTYPE Provides CoreSight discovery information for the ITM 0xFCC read-only SUB Subtype. Component subtype [7:4] Other. Only permitted if the MAJOR field reads as 0x0 0 Associated with a Bus, stimulus derived from bus activity 4 MAJOR Major type. Component major type [3:0] Miscellaneous 0 Trace Source 3 ITM Software Lock Access Register ITM_LAR Provides CoreSight Software Lock control for the ITM, see the CoreSight Architecture Specification for details 0xFB0 write-only KEY Lock Access control [31:0] ITM Software Lock Status Register ITM_LSR Provides CoreSight Software Lock status information for the ITM, see the CoreSight Architecture Specification for details 0xFB4 read-only nTT Not thirty-two bit. See the CoreSight Architecture Specification [2:2] SLK Software Lock status. See the CoreSight Architecture Specification [1:1] Lock clear. Software writes are permitted to this component's registers 0 Lock set 1 SLI Software Lock implemented. See the CoreSight Architecture Specification [0:0] Software Lock not implemented or debugger access 0 Software Lock is implemented and software access 1 ITM Peripheral Identification Register 0 ITM_PIDR0 Provides CoreSight discovery information for the ITM 0xFE0 read-only PART_0 Part number bits [7:0]. See the CoreSight Architecture Specification [7:0] ITM Peripheral Identification Register 1 ITM_PIDR1 Provides CoreSight discovery information for the ITM 0xFE4 read-only DES_0 JEP106 identification code bits [3:0]. See the CoreSight Architecture Specification [7:4] PART_1 Part number bits [11:8]. See the CoreSight Architecture Specification [3:0] ITM Peripheral Identification Register 2 ITM_PIDR2 Provides CoreSight discovery information for the ITM 0xFE8 read-only REVISION Component revision. See the CoreSight Architecture Specification [7:4] JEDEC JEDEC assignee value is used. See the CoreSight Architecture Specification [3:3] DES_1 JEP106 identification code bits [6:4]. See the CoreSight Architecture Specification [2:0] ITM Peripheral Identification Register 3 ITM_PIDR3 Provides CoreSight discovery information for the ITM 0xFEC read-only REVAND RevAnd. See the CoreSight Architecture Specification [7:4] CMOD Customer Modified. See the CoreSight Architecture Specification [3:0] ITM Peripheral Identification Register 4 ITM_PIDR4 Provides CoreSight discovery information for the ITM 0xFD0 read-only SIZE 4KB count. See the CoreSight Architecture Specification [7:4] DES_2 JEP106 continuation code. See the CoreSight Architecture Specification [3:0] ITM Peripheral Identification Register 5 ITM_PIDR5 Provides CoreSight discovery information for the ITM 0xFD4 read-only ITM Peripheral Identification Register 6 ITM_PIDR6 Provides CoreSight discovery information for the ITM 0xFD8 read-only ITM Peripheral Identification Register 7 ITM_PIDR7 Provides CoreSight discovery information for the ITM 0xFDC read-only ITM Stimulus Port Register ITM_STIM Provides the interface for generating Instrumentation packets 0x0 read-write STIMULUS Stimulus data [31:0] DISABLED Disabled. Indicates whether the stimulus port is enabled or disabled [1:1] Stimulus port and ITM are enabled 0 Stimulus port or ITM is disabled 1 FIFOREADY FIFO ready. Indicates whether the stimulus port can accept data [0:0] Stimulus port cannot accept data 0 Stimulus port can accept at least one word 1 ITM Trace Control Register ITM_TCR Configures and controls transfers through the ITM interface 0xE80 read-write BUSY ITM busy. Indicates whether the ITM is currently processing events [23:23] ITM is not processing any events 0 Events present and being drained 1 TraceBusID Trace bus identity. Identifier for multi-source trace stream formatting [22:16] Multi-source trace not in use 0 GTSFREQ Global timestamp frequency [11:10] Disable generation of Global Timestamp packets 0 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:7] 1 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [47:13] 2 Generate a timestamp after every packet, if the output FIFO is empty 3 TSPrescale Timestamp prescale. Local timestamp prescaler, used with the trace packet reference clock [9:8] No prescaling 0 Divide by 4 1 Divide by 16 2 Divide by 64 3 STALLENA Stall enable. Stall the PE to guarantee delivery of Data Trace packets [5:5] Drop Hardware Source packets and generate an Overflow packet if the ITM output is stalled 0 Stall the PE to guarantee delivery of Data Trace packets 1 SWOENA SWO enable. Enables asynchronous clocking of the timestamp counter [4:4] Timestamp counter uses the processor system clock 0 Timestamp counter uses asynchronous clock from the TPIU interface 1 TXENA Transmit enable [3:3] Disabled 0 Enabled 1 SYNCENA Synchronization enable. Enables Synchronization packet transmission for a synchronous TPIU [2:2] Disabled 0 Enabled 1 TSENA Timestamp enable. Enables Local timestamp generation [1:1] Disabled 0 Enabled 1 ITMENA ITM enable. Enables the ITM [0:0] Disabled 0 Enabled 1 ITM Trace Enable Register %s ITM_TER_%s Provide an individual enable bit for each ITM_STIM register 0xE00 7 4 read-write STIMENA_%s Stimulus enable [31:0] 32 1 Stimulus port (32n + m) disabled 0 Stimulus port (32n + m) enabled 1 ITM Trace Privilege Register ITM_TPR Controls which stimulus ports can be accessed by unprivileged code 0xE40 read-write PRIVMASK Privilege mask [31:0] Unprivileged access permitted 0 Privileged access only 1 DWT Data Watchpoint and Trace 0xE0001000 0x0 0x1000 registers DWT Component Identification Register 0 DWT_CIDR0 Provides CoreSight discovery information for the DWT 0xFF0 read-only PRMBL_0 CoreSight component identification preamble [7:0] DWT Component Identification Register 1 DWT_CIDR1 Provides CoreSight discovery information for the DWT 0xFF4 read-only CLASS CoreSight component class. See the CoreSight Architecture Specification [7:4] PRMBL_1 CoreSight component identification preamble [3:0] DWT Component Identification Register 2 DWT_CIDR2 Provides CoreSight discovery information for the DWT 0xFF8 read-only PRMBL_2 CoreSight component identification preamble [7:0] DWT Component Identification Register 3 DWT_CIDR3 Provides CoreSight discovery information for the DWT 0xFFC read-only PRMBL_3 CoreSight component identification preamble [7:0] DWT Comparator Register %s DWT_COMP_%s Provides a reference value for use by watchpoint comparator n 0x20 14 16 read-write CYCVALUE Cycle value. Reference value for comparison with cycle count [31:0] PCVALUE PC value. Reference value for comparison with program counter [31:1] DADDR Data address. Reference value for comparison with load or store address [31:0] DVALUE Data value. Reference value for comparison with load or store data [31:0] DWT CPI Count Register DWT_CPICNT Counts additional cycles required to execute multicycle instructions and instruction fetch stalls 0x8 read-write CPICNT Base instruction overhead counter [7:0] DWT Control Register DWT_CTRL Provides configuration and status information for the DWT unit, and used to control features of the unit 0x0 read-write NUMCOMP Number of comparators. Number of DWT comparators implemented [31:28] NOTRCPKT No trace packets. Indicates whether the implementation does not support trace [27:27] Trace supported 0 Trace not supported 1 NOEXTTRIG No External Triggers. Shows whether the implementation does not support external triggers [26:26] NOCYCCNT No cycle count. Indicates whether the implementation does not include a cycle counter [25:25] Cycle counter implemented 0 Cycle counter not implemented 1 NOPRFCNT No profile counters. Indicates whether the implementation does not include the profiling counters [24:24] Profiling counters implemented 0 Profiling counters not implemented 1 CYCDISS Cycle counter disabled secure. Controls whether the cycle counter is disabled in Secure state [23:23] No effect 0 Disable incrementing of the cycle counter when the PE is in Secure state 1 CYCEVTENA Cycle event enable. Enables Event Counter packet generation on POSTCNT underflow [22:22] No Event Counter packets generated when POSTCNT underflows 0 If PCSAMPLENA set to 0, an Event Counter packet is generated when POSTCNT underflows 1 FOLDEVTENA Fold event enable. Enables DWT_FOLDCNT counter [21:21] DWT_FOLDCNT disabled 0 DWT_FOLDCNT enabled 1 LSUEVTENA LSU event enable. Enables DWT_LSUCNT counter [20:20] DWT_LSUCNT disabled 0 DWT_LSUCNT enabled 1 SLEEPEVTENA Sleep event enable. Enable DWT_SLEEPCNT counter [19:19] DWT_SLEEPCNT disabled 0 DWT_SLEEPCNT enabled 1 EXCEVTENA Exception event enable. Enables DWT_EXCCNT counter [18:18] DWT_EXCCNT disabled 0 DWT_EXCCNT enabled 1 CPIEVTENA CPI event enable. Enables DWT_CPICNT counter [17:17] DWT_CPICNT disabled 0 DWT_CPICNT enabled 1 EXCTRCENA Exception trace enable. Enables generation of Exception Trace packets [16:16] Exception Trace packet generation disabled 0 Exception Trace packet generation enabled 1 PCSAMPLENA PC sample enable [12:12] Periodic PC Sample packet generation disabled 0 Periodic PC Sample packet generated on POSTCNT underflow 1 SYNCTAP Synchronization tap [11:10] Synchronization packet generation disabled 0 Synchronization counter tap at CYCCNT[24] 1 Synchronization counter tap at CYCCNT[26] 2 Synchronization counter tap at CYCCNT[28] 3 CYCTAP Cycle count tap. Selects the position of the POSTCNT tap on the CYCCNT counter [9:9] POSTCNT tap at CYCCNT[6] 0 POSTCNT tap at CYCCNT[10] 1 POSTINIT POSTCNT initial. Initial value for the POSTCNT counter [8:5] POSTPRESET POSTCNT preset. Reload value for the POSTCNT counter [4:1] CYCCNTENA CYCCNT enable. Enables CYCCNT [0:0] CYCCNT disabled 0 CYCCNT enabled 1 DWT Cycle Count Register DWT_CYCCNT Shows or sets the value of the processor cycle counter, CYCCNT 0x4 read-write CYCCNT Incrementing cycle counter value [31:0] DWT Device Architecture Register DWT_DEVARCH Provides CoreSight discovery information for the DWT 0xFBC read-only ARCHITECT Architect. Defines the architect of the component [31:21] JEP106 continuation code 0x4, ID code 0x3B. ARM Limited 571 PRESENT DEVARCH Present. Defines that the DEVARCH register is present [20:20] DEVARCH information present 1 REVISION Revision. Defines the architecture revision of the component [19:16] DWT architecture v2.0 0 ARCHVER Architecture Version. Defines the architecture version of the component [15:12] DWT architecture v2 1 ARCHPART Architecture Part. Defines the architecture of the component [11:0] DWT architecture 2562 DWT Device Type Register DWT_DEVTYPE Provides CoreSight discovery information for the DWT 0xFCC read-only SUB Subtype. Component subtype [7:4] Other 0 MAJOR Major type. Component major type [3:0] Miscellaneous 0 DWT Exception Overhead Count Register DWT_EXCCNT Counts the total cycles spent in exception processing 0xC read-write EXCCNT The exception overhead counter [7:0] DWT Folded Instruction Count Register DWT_FOLDCNT Increments on the additional cycles required to execute all load or store instructions 0x18 read-write FOLDCNT Folded instruction counter [7:0] DWT Comparator Function Register %s DWT_FUNCTION_%s Controls the operation of watchpoint comparator n 0x28 14 16 read-write ID Identify capability. Identifies the capabilities for MATCH for comparator n [31:27] Reserved 0 Data Address, and Data Address With Value 8 Cycle Counter, Data Address, and Data Address With Value 9 Instruction Address, Data Address, and Data Address With Value 10 Cycle Counter, Instruction Address, Data Address and Data Address With Value 11 Data Address, Data Address Limit, and Data Address With Value 24 Instruction Address, Instruction Address Limit, Data Address, Data Address Limit, and Data Address With Value 26 Data Address, Data Address Limit, Data Value, Linked Data Value, and Data Address With Value 28 Instruction Address, Instruction Address Limit, Data Address, Data Address Limit, Data value, Linked Data Value, and Data Addre 30 MATCHED Comparator matched. Set to 1 when the comparator matches [24:24] No match 0 Match. The comparator has matched since the last read of this register 1 DATAVSIZE Data value size [11:10] 1 byte 0 2 bytes 1 4 bytes 2 ACTION Action on match. Defines the action on a match [5:4] Trigger only 0 Generate debug event 1 For a Cycle Counter, Instruction Address, Data Address, Data Value or Linked Data Value comparator, generate a Data Trace Match 2 MATCH Match type. Controls the type of match generated by this comparator [3:0] Disabled. Never generates a match 0 Cycle Counter. Matches if DWT_CYCCNT equals the comparator value 1 DWT Software Lock Access Register DWT_LAR Provides CoreSight Software Lock control for the DWT, see the CoreSight Architecture Specification for details 0xFB0 write-only KEY Lock Access control [31:0] DWT Software Lock Status Register DWT_LSR Provides CoreSight Software Lock status information for the DWT, see the CoreSight Architecture Specification for details 0xFB4 read-only nTT Not thirty-two bit. See the CoreSight Architecture Specification [2:2] SLK Software Lock status. See the CoreSight Architecture Specification [1:1] Lock clear. Software writes are permitted to this component's registers 0 Lock set 1 SLI Software Lock implemented. See the CoreSight Architecture Specification [0:0] Software Lock not implemented or debugger access 0 Software Lock is implemented and software access 1 DWT LSU Count Register DWT_LSUCNT Increments on the additional cycles required to execute all load or store instructions 0x14 read-write LSUCNT Load-store overhead counter [7:0] DWT Program Counter Sample Register DWT_PCSR Samples the current value of the program counter 0x1C read-only EIASAMPLE Executed instruction address sample. Recently executed instruction address sample value [31:0] DWT Peripheral Identification Register 0 DWT_PIDR0 Provides CoreSight discovery information for the DWT 0xFE0 read-only PART_0 Part number bits [7:0]. See the CoreSight Architecture Specification [7:0] DWT Peripheral Identification Register 1 DWT_PIDR1 Provides CoreSight discovery information for the DWT 0xFE4 read-only DES_0 JEP106 identification code bits [3:0]. See the CoreSight Architecture Specification [7:4] PART_1 Part number bits [11:8]. See the CoreSight Architecture Specification [3:0] DWT Peripheral Identification Register 2 DWT_PIDR2 Provides CoreSight discovery information for the DWT 0xFE8 read-only REVISION Component revision. See the CoreSight Architecture Specification [7:4] JEDEC JEDEC assignee value is used. See the CoreSight Architecture Specification [3:3] DES_1 JEP106 identification code bits [6:4]. See the CoreSight Architecture Specification [2:0] DWT Peripheral Identification Register 3 DWT_PIDR3 Provides CoreSight discovery information for the DWT 0xFEC read-only REVAND RevAnd. See the CoreSight Architecture Specification [7:4] CMOD Customer Modified. See the CoreSight Architecture Specification [3:0] DWT Peripheral Identification Register 4 DWT_PIDR4 Provides CoreSight discovery information for the DWT 0xFD0 read-only SIZE 4KB count. See the CoreSight Architecture Specification [7:4] DES_2 JEP106 continuation code. See the CoreSight Architecture Specification [3:0] DWT Peripheral Identification Register 5 DWT_PIDR5 Provides CoreSight discovery information for the DWT 0xFD4 read-only DWT Peripheral Identification Register 6 DWT_PIDR6 Provides CoreSight discovery information for the DWT 0xFD8 read-only DWT Peripheral Identification Register 7 DWT_PIDR7 Provides CoreSight discovery information for the DWT 0xFDC read-only DWT Sleep Count Register DWT_SLEEPCNT Counts the total number of cycles that the processor is sleeping 0x10 read-write SLEEPCNT Sleep counter [7:0] DPB Flash Patch and Breakpoint 0xE0002000 0x0 0x1000 registers FP Component Identification Register 0 FP_CIDR0 Provides CoreSight discovery information for the FP 0xFF0 read-only PRMBL_0 CoreSight component identification preamble [7:0] FP Component Identification Register 1 FP_CIDR1 Provides CoreSight discovery information for the FP 0xFF4 read-only CLASS CoreSight component class. See the CoreSight Architecture Specification [7:4] PRMBL_1 CoreSight component identification preamble [3:0] FP Component Identification Register 2 FP_CIDR2 Provides CoreSight discovery information for the FP 0xFF8 read-only PRMBL_2 CoreSight component identification preamble [7:0] FP Component Identification Register 3 FP_CIDR3 Provides CoreSight discovery information for the FP 0xFFC read-only PRMBL_3 CoreSight component identification preamble [7:0] Flash Patch Comparator Register %s FP_COMP_%s Holds an address for comparison 0x8 141 4 read-write BPADDR Breakpoint address. Specifies bits[31:1] of the breakpoint instruction address [31:1] FE Flash Patch enable. Specifies if Flash Patch enabled [31:31] Flash Patch disabled 0 Flash Patch enabled 1 FPADDR Flash Patch address. Specifies bits[28:2] of the Flash Patch address [28:2] BE Breakpoint enable. Selects between Flash Patch and breakpoint functionality [0:0] Breakpoint disabled, Flash Patch mode selected 0 Breakpoint enabled, Flash Patch mode de-selected 1 Flash Patch Control Register FP_CTRL Provides FPB implementation information, and the global enable for the FPB unit 0x0 read-write REV Revision. Flash Patch and Breakpoint Unit architecture revision [31:28] Flash Patch Breakpoint version 2 implemented 1 NUM_CODE Number of implemented code comparators [0:0] NUM_LIT Number of literal comparators. Indicates the number of implemented literal address comparators [11:8] KEY FP_CTRL write-enable key [1:1] Concurrent write to FP_CTRL ignored 0 Concurrent write to FP_CTRL permitted 1 ENABLE Flash Patch global enable. Enables the FPB [0:0] All FPB functionality disabled 0 FPB enabled 1 FPB Device Architecture Register FP_DEVARCH Provides CoreSight discovery information for the FPB 0xFBC read-only ARCHITECT Architect. Defines the architect of the component [31:21] JEP106 continuation code 0x4, ID code 0x3B. ARM Limited 571 PRESENT DEVARCH Present. Defines that the DEVARCH register is present [20:20] DEVARCH information present 1 REVISION Revision. Defines the architecture revision of the component [19:16] FPB architecture v2.0 0 ARCHVER Architecture Version. Defines the architecture version of the component [15:12] FPB architecture v2 1 11ARCHPART12 15ARCHVER16 19REVISION20 21 31ARCHITECTPRESENTD1 Register Specification D1 0 ARCHPART Architecture Part. Defines the architecture of the component [11:0] FPB architecture 2563 FPB Device Type Register FP_DEVTYPE Provides CoreSight discovery information for the FPB 0xFCC read-only SUB Subtype. Component subtype [7:4] Other 0 MAJOR Major type. Component major type [3:0] Miscellaneous 0 FPB Software Lock Access Register FP_LAR Provides CoreSight Software Lock control for the FPB, see the CoreSight Architecture Specification for details 0xFB0 write-only KEY Lock Access control [31:0] FPB Software Lock Status Register FP_LSR Provides CoreSight Software Lock status information for the FPB, see the CoreSight Architecture Specification for details 0xFB4 read-only nTT Not thirty-two bit. See the CoreSight Architecture Specification [2:2] SLK Software Lock status. See the CoreSight Architecture Specification [1:1] Lock clear. Software writes are permitted to this component's registers 0 Lock set 1 SLI Software Lock implemented. See the CoreSight Architecture Specification [0:0] Software Lock not implemented or debugger access 0 Software Lock is implemented and software access 1 FP Peripheral Identification Register 0 FP_PIDR0 Provides CoreSight discovery information for the FP 0xFE0 read-only PART_0 Part number bits [7:0]. See the CoreSight Architecture Specification [7:0] FP Peripheral Identification Register 1 FP_PIDR1 Provides CoreSight discovery information for the FP 0xFE4 read-only DES_0 JEP106 identification code bits [3:0]. See the CoreSight Architecture Specification [7:4] PART_1 Part number bits [11:8]. See the CoreSight Architecture Specification [3:0] FP Peripheral Identification Register 2 FP_PIDR2 Provides CoreSight discovery information for the FP 0xFE8 read-only REVISION Component revision. See the CoreSight Architecture Specification [7:4] JEDEC JEDEC assignee value is used. See the CoreSight Architecture Specification [3:3] DES_1 JEP106 identification code bits [6:4]. See the CoreSight Architecture Specification [2:0] FP Peripheral Identification Register 3 FP_PIDR3 Provides CoreSight discovery information for the FP 0xFEC read-only REVAND RevAnd. See the CoreSight Architecture Specification [7:4] CMOD Customer Modified. See the CoreSight Architecture Specification [3:0] FP Peripheral Identification Register 4 FP_PIDR4 Provides CoreSight discovery information for the FP 0xFD0 read-only SIZE 4KB count. See the CoreSight Architecture Specification [7:4] DES_2 JEP106 continuation code. See the CoreSight Architecture Specification [3:0] FP Peripheral Identification Register 5 FP_PIDR5 Provides CoreSight discovery information for the FP 0xFD4 read-only FP Peripheral Identification Register 6 FP_PIDR6 Provides CoreSight discovery information for the FP 0xFD8 read-only FP Peripheral Identification Register 7 FP_PIDR7 Provides CoreSight discovery information for the FP 0xFDC read-only Flash Patch Remap Register FP_REMAP Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap 0x4 read-only RMPSPT Remap supported. Indicates whether the FPB unit supports the Flash Patch remap function [29:29] Flash Patch remap function is not implemented 0 Flash Patch remap function is implemented 1 REMAP Remap address. Holds the bits[28:5] of the Flash Patch remap address [28:5] ICB Implementation Control Block 0xE000E004 0x0 0xC registers Auxiliary Control Register ACTLR Provides IMPLEMENTATION DEFINED configuration and control options 0x4 read-write IMPLEMENTATION DEFINED IMPLEMENTATION DEFINED. The contents of this field are IMPLEMENTATION DEFINED [31:0] Coprocessor Power Control Register CPPWR Specifies whether coprocessors are permitted to enter a non-retentive power state 0x8 read-write SUS11 State UNKNOWN Secure only 11. The value in this field is ignored [23:23] SU11 State UNKNOWN 11. The value in this field is ignored [22:22] SUS10 State UNKNOWN Secure only 10 [21:21] The SU10 field is accessible from both Security states 0 The SU10 field is only accessible from the Secure state 1 SU10 State UNKNOWN 10 [20:20] The floating-point state is not permitted to become UNKNOWN 0 The floating-point state is permitted to become UNKNOWN 1 SUSm State UNKNOWN Secure only m [0:0] The SUm field is accessible from both Security states 0 The SUm field is only accessible from the Secure state 1 SUm State UNKNOWN m [0:0] The coprocessor state is not permitted to become UNKNOWN 0 The coprocessor state is permitted to become UNKNOWN 1 Interrupt Controller Type Register ICTR Provides information about the interrupt controller 0x0 read-only INTLINESNUM Interrupt line set number [3:0] SYSTICK SysTick Timer 0xE000E010 0x0 0x20 registers SysTick Calibration Value Register SYST_CALIB Reads the SysTick timer calibration value and parameters for the selected Security state 0xC read-only NOREF No reference. Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented [31:31] Reference clock is implemented 0 Reference clock is not implemented 1 SKEW Skew. Indicates whether the 10ms calibration value is exact [30:30] TENMS calibration value is exact 0 TENMS calibration value is inexact 1 TENMS Ten milliseconds [23:0] SysTick Control and Status Register SYST_CSR Controls the SysTick timer and provides status data for the selected Security state 0x0 read-write COUNTFLAG Count flag. Indicates whether the counter has counted to zero since the last read of this register [16:16] Timer has not counted to 0 0 Timer has counted to 0 1 CLKSOURCE Clock source. Indicates the SysTick clock source [2:2] Uses the IMPLEMENTATION DEFINED external reference clock 0 Uses the PE clock 1 TICKINT Tick interrupt [1:1] Count to 0 does not affect the SysTick exception status 0 Count to 0 changes the SysTick exception status to pending 1 ENABLE SysTick enable. Indicates the enabled status of the SysTick counter [0:0] Counter is disabled 0 Counter is enabled 1 SysTick Current Value Register SYST_CVR Reads or clears the SysTick timer current counter value for the selected Security state 0x8 read-write CURRENT Current counter value [23:0] CURRENT Reset counter value [23:0] SysTick Reload Value Register SYST_RVR Provides access SysTick timer counter reload value for the selected Security state 0x4 read-write RELOAD Counter reload value [23:0] NVIC Nested Vectored Interrupt Controller 0xE000E100 0x0 0x380 registers Interrupt Active Bit Register %s NVIC_IABR_%s For each group of 32 interrupts, shows the active state of each interrupt 0x200 15 4 read-only ACTIVE_%s Active state. For ACTIVE[m] in NVIC_IABRn, indicates the active state for interrupt 32n+m [31:0] 32 1 Interrupt not active 0 Interrupt is active 1 Interrupt Clear Enable Register %s NVIC_ICER_%s Clears or reads the enabled state of each group of 32 interrupts 0x80 15 4 read-write CLRENA_%s Clear enable. For CLRENA[m] in NVIC_ICERn, allows interrupt 32n + m to be disabled [31:0] 32 1 No effect 0 Disable interrupt 32n + m 1 Interrupt Clear Pending Register %s NVIC_ICPR_%s Clears or reads the pending state of each group of 32 interrupts 0x180 15 4 read-write CLRPEND_%s Clear pending. For CLRPEND[m] in NVIC_ICPRn, allows interrupt 32n + m to be unpended [31:0] 32 1 No effect 0 Clear pending state of interrupt 32n + m 1 Interrupt Priority Register %s NVIC_IPR_%s Sets or reads interrupt priorities 0x300 123 4 read-write PRI_Nm Priority 'N'+m [0:0] Interrupt Set Enable Register %s NVIC_ISER_%s Enables or reads the enabled state of each group of 32 interrupts 0x0 15 4 read-write SETENA_%s Set enable. For SETENA[m] in NVIC_ISERn, allows interrupt 32n + m to be set enabled [31:0] 32 1 No effect 0 Enable interrupt 32n + m 1 Interrupt Set Pending Register %s NVIC_ISPR_%s Enables or reads the pending state of each group of 32 interrupts 0x100 15 4 read-write SETPEND_%s Set pending. For SETPEND[m] in NVIC_ISPRn, allows interrupt 32n + m to be set pending [31:0] 32 1 No effect 0 Pend interrupt 32n + m 1 Interrupt Target Non-secure Register %s NVIC_ITNS_%s For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state 0x280 15 4 read-write ITNS_%s Interrupt Targets Non-secure [31:0] 32 1 Interrupt targets Secure state 0 Interrupt targets Non-secure state 1 SCB System Control Block 0xE000ED00 0x0 0x90 registers CPUID Base Register CPUID Provides identification information for the PE, including an implementer code for the device and a device ID number 0x0 read-only Implementer Implementer code. This field must hold an implementer code that has been assigned by ARM [31:24] 'A': ARM Limited 65 Variant Variant number. IMPLEMENTATION DEFINED variant number [23:20] Architecture Architecture version. Defines the Architecture implemented by the PE [19:16] ARMv8-M architecture without Main Extension 12 ARMv8-M architecture with Main Extension 15 PartNo Part number. IMPLEMENTATION DEFINED primary part number for the device [15:4] Revision Revision number. IMPLEMENTATION DEFINED revision number for the device [3:0] Interrupt Control and State Register ICSR Controls and provides status information for NMI, PendSV, SysTick and interrupts 0x4 read-write PENDNMISET Pend NMI set. Allows the NMI exception to be set as pending [31:31] No effect 0 Sets the NMI exception pending 1 PENDNMISET Pend NMI set. Indicates whether the NMI exception is pending [31:31] NMI exception not pending 0 NMI exception pending 1 PENDNMICLR Pend NMI clear. Allows the NMI exception pend state to be cleared [30:30] No effect 0 Clear pending status 1 PENDSVSET Pend PendSV set. Allows the PendSV exception for the selected Security state to be set as pending [28:28] No effect 0 Sets the PendSV exception pending 1 PENDSVSET Pend PendSV set. Indicates whether the PendSV for the selected Security state exception is pending [28:28] PendSV exception not pending 0 PendSV exception pending 1 PENDSVCLR Pend PendSV clear [27:27] No effect 0 Clear pending status 1 PENDSTSET Pend SysTick set. Allows the SysTick for the selected Security state exception to be set as pending [26:26] No effect 0 Sets the SysTick exception for the selected Security state pending 1 PENDSTSET Pend SysTick set. Indicates whether the SysTick for the selected Security state exception is pending [26:26] SysTick exception not pending 0 SysTick exception pending 1 PENDSTCLR Pend SysTick clear [25:25] No effect 0 Clear pending status 1 STTNS SysTick Targets Non-secure [24:24] SysTick is Secure 0 SysTick is Non-secure 1 ISRPREEMPT Interrupt preempt [23:23] Will not service 0 Will service a pending exception 1 ISRPENDING Interrupt pending. Indicates whether an external interrupt, generated by the NVIC, is pending [22:22] No external interrupt pending 0 External interrupt pending 1 VECTPENDING Vector pending. The exception number of the highest priority pending and enabled interrupt [20:12] RETTOBASE Return to base. In Handler mode, indicates whether there is more than one active exception [11:11] There is more than one active exception 0 There is only one active exception 1 VECTACTIVE Vector active. The exception number of the current executing exception [8:0] Vector Table Offset Register VTOR Holds the vector table address for the selected Security state 0x8 read-write Application Interrupt and Reset Control Register AIRCR Sets or returns interrupt control and reset configuration 0xC read-write VECTKEY Vector key. Writes to the AIRCR must be accompanied by a write of the value 0x05FA to this field [31:16] Permit write to AIRCR fields 1530 VECTKEYSTAT Vector key status. Returns the bitwise inverse of the value required to be written to VECTKEY [31:16] ENDIANNESS Data endianness. Indicates how the PE interprets the memory system data endianness [15:15] Little-endian 0 Big-endian 1 PRIS Prioritize Secure exceptions [14:14] Priority ranges of Secure and Non-secure exceptions are identical 0 Non-secure exceptions are de-prioritized 1 BFHFNMINS BusFault, HardFault, and NMI Non-secure enable [13:13] BusFault, HardFault, and NMI are Secure 0 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault 1 PRIGROUP Priority grouping [10:8] Group priority [7:1], subpriority [0] 0 Group priority [7:2], subpriority [1:0] 1 Group priority [7:3], subpriority [2:0] 2 Group priority [7:4], subpriority [3:0] 3 Group priority [7:5], subpriority [4:0] 4 Group priority [7:6], subpriority [5:0] 5 SYSRESETREQS System reset request Secure only [3:3] SYSRESETREQ functionality is available to both Security states 0 SYSRESETREQ functionality is only available to Secure state 1 SYSRESETREQ System reset request. This bit allows software or a debugger to request a system reset [2:2] Do not request a system reset 0 Request a system reset 1 VECTCLRACTIVE Clear active state [1:1] Do not clear active state 0 Clear active state 1 System Control Register SCR Sets or returns system control data 0x10 read-write SEVONPEND Send event on pend [4:4] Transitions from inactive to pending are not wakeup events 0 Transitions from inactive to pending are wakeup events 1 SLEEPDEEPS Sleep deep secure [3:3] The SLEEPDEEP bit accessible from both Security states 0 The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state 1 SLEEPDEEP Sleep deep. Provides a qualifying hint indicating that waking from sleep might take longer [2:2] Selected sleep state is not deep sleep 0 Selected sleep state is deep sleep 1 SLEEPONEXIT Sleep on exit [1:1] Enter sleep state disabled 0 Enter sleep state permitted 1 Configuration and Control Register CCR Sets or returns configuration and control data 0x14 read-write BP Branch prediction enable. Enables program flow prediction for the selected Security state [18:18] Program flow prediction disabled for the selected Security state 0 Program flow prediction enabled for the selected Security state 1 IC Instruction cache enable. This is a global enable bit for instruction caches in the selected Security state. [17:17] Instruction caches disabled for the selected Security state 0 Instruction caches enabled for the selected Security state 1 DC Data cache enable. Enables data caching of all data accesses to Normal memory for the selected security state [16:16] Data caching disabled for the selected Security state 0 Data caching enabled for the selected Security state 1 STKOFHFNMIGN Stack overflow in HardFault and NMI ignore. Controls the effect of a stack limit violation while executing at a requested priority less than 0 for the Security state with which the stack limit register is associated [10:10] Stack limit faults not ignored 0 Stack limit faults at requested priorities of less than 0 ignored 1 BFHFNMIGN BusFault in HardFault or NMI ignore. Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 [8:8] Precise BusFaults not ignored 0 Precise BusFaults at requested priorities of less than 0 ignored 1 DIV_0_TRP Divide by zero trap. Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero [4:4] DIVBYZERO UsageFault generation disabled 0 DIVBYZERO UsageFault generation enabled 1 UNALIGN_TRP Unaligned trap. Controls the trapping of unaligned word or halfword accesses [3:3] Unaligned accesses permitted from LDR, LDRH, STR, and STRH 0 Any unaligned transaction generates an UNALIGNED UsageFault 1 USERSETMPEND User set main pending. Determines whether unprivileged accesses are permitted to pend interrupts via the STIR [1:1] Unprivileged accesses to the STIR generate a fault 0 Unprivileged accesses to the STIR are permitted 1 System Handler Priority Register 1 SHPR1 Sets or returns priority for system handlers 4 - 7 0x18 read-write PRI_7 Priority 7. Priority of system handler 7, SecureFault [31:24] PRI_6 Priority 6. Priority of system handler 6, UsageFault [23:16] PRI_5 Priority 5. Priority of system handler 5, BusFault [15:8] PRI_4 Priority 4. Priority of system handler 4, MemManage [7:0] System Handler Priority Register 2 SHPR2 Sets or returns priority for system handlers 8 - 11 0x1C read-write PRI_11 Priority 11. Priority of system handler 11, SVCall [31:24] PRI_10 Reserved, RES0 [23:16] PRI_9 Reserved, RES0 [15:8] PRI_8 Reserved, RES0 [7:0] System Handler Priority Register 3 SHPR3 Sets or returns priority for system handlers 12 - 15 0x20 read-write PRI_15 Priority 15. Priority of system handler 15, SysTick [31:24] PRI_14 Priority 14. Priority of system handler 14, PendSV [23:16] PRI_13 Reserved, RES0 [15:8] PRI_12 Priority 12. Priority of system handler 12, DebugMonitor [7:0] System Handler Control and State Register SHCSR Provides access to the active and pending status of system exceptions 0x24 read-write HARDFAULTPENDED HardFault exception pended state [21:21] HardFault exception not pending for the selected Security state 0 HardFault exception pending for the selected Security state 1 SECUREFAULTPENDED SecureFault exception pended state [20:20] SecureFault exception not pending 0 SecureFault exception pending 1 SECUREFAULTENA SecureFault exception enable [19:19] SecureFault exception disabled 0 SecureFault exception enabled 1 USGFAULTENA UsageFault exception enable [18:18] UsageFault exception disabled for the selected Security state 0 UsageFault exception enabled for the selected Security state 1 BUSFAULTENA BusFault exception enable. The value of this bit defines whether the BusFault exception is enabled [17:17] BusFault exception disabled 0 BusFault exception enabled 1 MEMFAULTENA MemManage exception enable [16:16] MemManage exception disabled for the selected Security state 0 MemManage exception enabled for the selected Security state 1 SVCALLPENDED SVCall exception pended state [15:15] SVCall exception not pending for the selected Security state 0 SVCall exception pending for the selected Security state 1 BUSFAULTPENDED BusFault exception pended state [14:14] BusFault exception not pending 0 BusFault exception pending 1 MEMFAULTPENDED MemManage exception pended state [13:13] MemManage exception not pending for the selected Security state 0 MemManage exception pending for the selected Security state 1 USGFAULTPENDED UsageFault exception pended state [12:12] UsageFault exception not pending for the selected Security state 0 UsageFault exception pending for the selected Security state 1 SYSTICKACT SysTick exception active state [11:11] SysTick exception not active for the selected Security state 0 SysTick exception active for the selected Security state 1 PENDSVACT PendSV exception active state [10:10] PendSV exception not active for the selected Security state 0 PendSV exception active for the selected Security state 1 MONITORACT DebugMonitor exception active state [8:8] DebugMonitor exception not active 0 DebugMonitor exception active 1 SVCALLACT SVCall exception active state [7:7] SVCall exception not active for the selected Security state 0 SVCall exception active for the selected Security state 1 NMIACT NMI exception active state [5:5] NMI exception not active 0 NMI exception active 1 SECUREFAULTACT SecureFault exception active state [4:4] SecureFault exception not active 0 SecureFault exception active 1 USGFAULTACT UsageFault exception active state for the selected Security state [3:3] UsageFault exception not active for the selected Security state 0 UsageFault exception active for the selected Security state 1 HARDFAULTACT HardFault exception active state [2:2] HardFault exception not active for the selected Security state 0 HardFault exception active for the selected Security state 1 BUSFAULTACT BusFault exception active state [1:1] BusFault exception not active 0 BusFault exception active 1 MEMFAULTACT MemManage exception active state for the selected Security state [0:0] MemManage exception not active for the selected Security state 0 MemManage exception active for the selected Security state 1 Configurable Fault Status Register CFSR Contains the three Configurable Fault Status Registers 0x28 read-write UFSR UsageFault Status Register. Provides information on UsageFault exceptions [31:16] BFSR BusFault Status Register. Provides information on BusFault exceptions [15:8] MMFSR MemManage Fault Status Register. Provides information on MemManage exceptions [7:0] Usage Fault Status Register UFSR Provides information on UsageFault exceptions 0x28 read-write DIVBYZERO Divide by zero flag. Indicates whether an integer division by zero error has occurred [25:25] Error has not occurred 0 Error has occurred 1 UNALIGNED Unaligned access flag. Indicates whether an unaligned access error has occurred [24:24] Error has not occurred 0 Error has occurred 1 STKOF Stack overflow flag. Indicates whether a stack overflow error has occurred [20:20] Error has not occurred 0 Error has occurred 1 NOCP No coprocessor flag. Indicates whether a coprocessor disabled or not present error has occurred [19:19] Error has not occurred 0 Error has occurred 1 INVPC Invalid PC flag. Indicates whether an integrity check error has occurred [18:18] Error has not occurred 0 Error has occurred 1 INVSTATE Invalid state flag. Indicates whether an EPSR.T or EPSR.IT validity error has occurred [17:17] Error has not occurred 0 Error has occurred 1 UNDEFINSTR Undefined instruction flag. Indicates whether an undefined instruction error has occurred [16:16] Error has not occurred 0 Error has occurred 1 Bus Fault Status Register BFSR Provides information on BusFault exceptions 0x28 read-write BFARVALID BFAR valid. Indicates validity of the contents of the BFAR register [15:15] BFAR content not valid 0 BFAR content valid 1 LSPERR Lazy state preservation error. Records whether a BusFault occurred during FP lazy state preservation [13:13] No BusFault occurred during FP lazy state preservation 0 BusFault occurred during FP lazy state preservation 1 STKERR Stack error. Records whether a derived BusFault occurred during exception entry stacking [12:12] No derived BusFault occurred 0 Derived BusFault occurred during exception entry 1 UNSTKERR Unstack error. Records whether a derived BusFault occurred during exception return unstacking [11:11] No derived BusFault occurred 0 Derived BusFault occurred during exception return 1 IMPRECISERR Imprecise error. Records whether an imprecise data access error has occurred [10:10] No imprecise data access error has occurred 0 Imprecise data access error has occurred 1 PRECISERR Precise error. Records whether a precise data access error has occurred [9:9] No precise data access error has occurred 0 Precise data access error has occurred 1 IBUSERR Instruction bus error. Records whether a BusFault on an instruction prefetch has occurred [8:8] No BusFault on instruction prefetch has occurred 0 A BusFault on an instruction prefetch has occurred 1 MemManage Fault Status Register MMFSR Provides information on MemManage exceptions 0x28 read-write MMARVALID MMFAR valid flag. Indicates validity of the MMFAR register [7:7] MMFAR content not valid 0 MMFAR content valid 1 MLSPERR MemManage lazy state preservation error flag. Records whether a MemManage fault occurred during FP lazy state preservation [5:5] No MemManage occurred during FP lazy state preservation 0 MemManage occurred during FP lazy state preservation 1 MSTKERR MemManage stacking error flag. Records whether a derived MemManage fault occurred during exception entry stacking [4:4] No derived MemManage occurred 0 Derived MemManage occurred during exception entry 1 MUNSTKERR MemManage unstacking error flag. Records whether a derived MemManage fault occurred during exception return unstacking [3:3] No derived MemManage fault occurred 0 Derived MemManage fault occurred during exception return 1 DACCVIOL Data access violation flag. Records whether a data access violation has occurred [1:1] No MemManage fault on data access has occurred 0 MemManage fault on data access has occurred 1 IACCVIOL Instruction access violation. Records whether an instruction related memory access violation has occurred [0:0] No MemManage fault on instruction access has occurred 0 MemManage fault on instruction access has occurred 1 HardFault Status Register HFSR Shows the cause of any HardFaults 0x2C read-write DEBUGEVT Debug event. Indicates when a debug event has occurred [31:31] No debug event has occurred 0 Debug event has occurred. The Debug Fault Status Register has been updated 1 FORCED Forced [30:30] No priority escalation has occurred 0 Processor has escalated a configurable-priority exception to HardFault 1 VECTTBL Vector table [1:1] No vector table read fault has occurred 0 Debug Fault Status Register DFSR Shows which debug event occurred 0x30 read-write EXTERNAL External event. Indicates whether an External debug request debug event has occurred [4:4] Debug event has not occurred 0 Debug event has occurred 1 VCATCH Vector Catch event. Indicates whether a Vector catch debug event has occurred [3:3] Debug event has not occurred 0 Debug event has occurred 1 DWTTRAP Watchpoint event. Indicates whether a Watchpoint debug event has occurred [2:2] Debug event has not occurred 0 Debug event has occurred 1 BKPT Breakpoint event. Indicates whether a breakpoint debug event has occurred [1:1] Debug event has not occurred 0 Debug event has occurred 1 HALTED Halt or step event [0:0] Debug event has not occurred 0 Debug event has occurred 1 MemManage Fault Address Register MMFAR Shows the address of the memory location that caused an MPU fault 0x34 read-write ADDRESS Data address for an MemManage fault [31:0] BusFault Address Register BFAR Shows the address associated with a precise data access BusFault 0x38 read-write Auxiliary Fault Status Register AFSR Provides IMPLEMENTATION DEFINED fault status information 0x3C read-write IMPLEMENTATION DEFINED IMPLEMENTATION DEFINED. The contents of this field are IMPLEMENTATION DEFINED [31:0] Processor Feature Register 0 ID_PFR0 Gives top-level information about the instruction set supported by the PE 0x40 read-only State1 State one. T32 instruction set support [7:4] T32 instruction set including Thumb-2 Technology implemented 3 State0 State two. A32 instruction set support [3:0] A32 instruction set not implemented 0 Processor Feature Register 1 ID_PFR1 Gives information about the programmers' model and Extensions support 0x44 read-only MProgMod M programmers' model. Identifies support for the M-Profile programmers' model support [11:8] Two-stack programmers' model 2 Security Security. Identifies whether the Security Extension is implemented [7:4] Security Extension not implemented 0 Security Extension implemented 1 Debug Feature Register 0 ID_DFR0 Provides top level information about the debug system 0x48 read-only MProfDbg M-profile debug. Indicates the supported M-profile debug architecture [23:20] Halting debug is not implemented 0 ARMv8-M Debug architecture 2 Auxiliary Feature Register 0 ID_AFR0 Provides information about the IMPLEMENTATION DEFINED features of the PE 0x4C read-only IMPDEFm IMPLEMENTATION DEFINED. IMPLEMENTATION DEFINED meaning [0:0] Memory Model Feature Register 0 ID_MMFR0 Provides information about the implemented memory model and memory management support 0x50 read-only AuxReg Auxiliary Registers. Indicates support for Auxiliary Control Registers [23:20] No Auxiliary Control Registers 0 Auxiliary Control Registers supported 1 TCM Tightly coupled memories. Indicates support for tightly coupled memories (TCMs) [19:16] None supported 0 TCMs supported with IMPLEMENTATION DEFINED control 1 ShareLvl Shareability Levels. Indicates the number of shareability levels implemented [15:12] One level of shareability implemented 0 Two levels of shareability implemented 1 OuterShr Outermost Shareability. Indicates the outermost shareability domain implemented [11:8] Implemented as Non-cacheable 0 Implemented with hardware coherency support 1 Shareability ignored 15 PMSA Protected memory system architecture [7:4] Supports PMSAv8 4 Memory Model Feature Register 1 ID_MMFR1 Provides information about the implemented memory model and memory management support 0x54 read-only Memory Model Feature Register 2 ID_MMFR2 Provides information about the implemented memory model and memory management support 0x58 read-only WFIStall WFI stall. Indicates the support for Wait For Interrupt (WFI) stalling [27:24] WFI never stalls 0 WFI has the ability to stall 1 Memory Model Feature Register 3 ID_MMFR3 Provides information about the implemented memory model and memory management support 0x5C read-only BPMaint Branch predictor maintenance. Indicates the supported branch predictor maintenance [11:8] None supported 0 Support for invalidate all of branch predictors 1 CMaintSW Cache maintenance set/way. Indicates the supported cache maintenance operations by set/way [7:4] None supported 0 Maintenance by set/way operations supported 1 CMaintVA Cache maintenance by address. Indicates the supported cache maintenance operations by address [3:0] None supported 0 Maintenance by address and instruction cache invalidate all supported 1 Instruction Set Attribute Register 0 ID_ISAR0 Provides information about the instruction set implemented by the PE 0x60 read-only Divide Divide. Indicates the supported Divide instructions [27:24] Supports SDIV and UDIV instructions 1 Debug Debug. Indicates the implemented Debug instructions [23:20] Supports BKPT instruction 1 Coproc Coprocessor. Indicates the supported Coprocessor instructions [19:16] No coprocessor instructions support other than FPU 0 Coprocessor instructions supported 4 3RES04 7BitCount8 11BitField12 15CmpBranch16 19Coproc20 23Debug24 27Divide28 31RES0D1 Register Specification D1 0 CmpBranch Compare and branch. Indicates the supported combined Compare and Branch instructions [15:12] Supports CBNZ and CBZ instructions 1 BitField Bit field. Indicates the supported bit field instructions [11:8] BFC, BFI, SBFX, and UBFX supported 1 BitCount Bit count. Indicates the supported bit count instructions [7:4] CLZ supported 1 Instruction Set Attribute Register 1 ID_ISAR1 Provides information about the instruction set implemented by the PE 0x64 read-only Interwork Interworking. Indicates the implemented interworking instructions [27:24] BLX, BX, and loads to PC interwork 2 Immediate Immediate. Indicates the implemented for data-processing instructions with long immediates [23:20] ADDW, MOVW, MOVT, and SUBW supported 2 IfThen If-Then. Indicates the implemented If-Then instructions [19:16] IT instruction supported 1 Extend Extend. Indicates the implemented Extend instructions [15:12] SXTB, SXTH, UXTB, and UXTH 1 Adds SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH, DSP Extension only 2 Instruction Set Attribute Register 2 ID_ISAR2 Provides information about the instruction set implemented by the PE 0x68 read-only Reversal Reversal. Indicates the implemented Reversal instructions [31:28] REV, REV16, REVSH and RBIT instructions supported 2 MultU Multiply unsigned. Indicates the implemented advanced unsigned Multiply instructions [23:20] UMULL and UMLAL 1 Adds UMAAL, DSP Extension only 2 MultS Multiply signed. Indicates the implemented advanced signed Multiply instructions [19:16] SMULL and SMLAL 1 Adds all saturating and DSP signed multiplies, DSP Extension only 3 Mult Multiplies. Indicates the implemented additional Multiply instructions [15:12] MUL, MLA, and MLS 2 MultiAccessInt Multi-access instructions. Indicates the support for interruptible multi-access instructions [11:8] No support. LDM and STM instructions are not interruptible 0 LDM and STM instructions are restartable 1 LDM and STM instructions are continuable 2 MemHint Memory hints. Indicates the implemented Memory hint instructions [7:4] PLI and PLD instructions implemented 3 LoadStore Load/store. Indicates the implemented additional load/store instructions [3:0] Supports load-acquire, store-release, and exclusive load and store instructions 2 Instruction Set Attribute Register 3 ID_ISAR3 Provides information about the instruction set implemented by the PE 0x6C read-only TrueNOP True no-operation. Indicates the implemented true NOP instructions [27:24] NOP instruction and compatible hints implemented 1 T32Copy T32 copy. Indicates the support for T32 non flag-setting MOV instructions [23:20] Encoding T1 of MOV (register) supports copying low register to low register 1 TabBranch Table branch. Indicates the implemented Table Branch instructions [19:16] TBB and TBH implemented 1 SynchPrim Synchronization primitives. Used in conjunction with ID_ISAR4 [15:12] LDREX, STREX, LDREXB, STREXB, LDREXH, STREXH, and CLREX implemented 1 SVC Supervisor call. Indicates the implemented SVC instructions [11:8] SVC instruction implemented 1 SIMD Single-instruction, multiple-data. Indicates the implemented SIMD instructions [7:4] SSAT, USAT, and Q-bit implemented 1 Adds all packed arithmetic and GE-bits, DSP Extension only 3 Saturate Saturate. Indicates the implemented saturating instructions [3:0] None implemented 0 QADD, QDADD, QDSUB, QSUB, and Q-bit implemented, DSP Extension only 1 Instruction Set Attribute Register 4 ID_ISAR4 Provides information about the instruction set implemented by the PE 0x70 read-only PSR_M Program Status Registers M. Indicates the implemented M profile instructions to modify the PSRs [27:24] M profile forms of CPS, MRS, and MSR implemented 1 SyncPrim_frac Synchronization primitives fractional. Used in conjunction with ID_ISAR3 [23:20] LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH implemented 3 Barrier Barrier. Indicates the implemented Barrier instructions [19:16] DMB, DSB, and ISB barrier instructions implemented 1 Writeback Writeback. Indicates the support for writeback addressing modes [11:8] All writeback addressing modes supported 1 WithShifts With shifts. Indicates the support for writeback addressing modes [7:4] Support for constant shifts on load/store and other instructions 3 Unpriv Unprivileged. Indicates the implemented unprivileged instructions [3:0] LDRBT, LDRHT, LDRSBT, LDRSHT, LDRT, STRBT, STRHT, and STRT implemented 2 Instruction Set Attribute Register 5 ID_ISAR5 Provides information about the instruction set implemented by the PE 0x74 read-only Cache Level ID Register CLIDR Identifies the type of caches implemented and the level of coherency and unification 0x78 read-only ICB Inner cache boundary. This field indicates the boundary between inner and outer domain [31:30] Not disclosed in this mechanism 0 L1 cache is the highest inner level 1 L2 cache is the highest inner level 2 L3 cache is the highest inner level 3 LoUU Level of Unification Uniprocessor [29:27] LoC Level of Coherence. This field indicates the Level of Coherence for the cache hierarchy [26:24] LoUIS Level of Unification Inner Shareable [23:21] Ctypem Cache type field m. Indicates the type of cache implemented at level m [0:0] No cache 0 Instruction cache only 1 Data cache only 2 Separate Instruction And Data Caches 3 Unified cache 4 Cache Type Register CTR Provides information about the architecture of the caches 0x7C read-only CWG Cache Writeback Granule [27:24] Indicates that this register does not provide Cache Writeback Granule information and either the architectural maximum of 512 w 0 ERG Exclusives Reservation Granule [23:20] Indicates that this register does not provide Exclusives Reservation Granule information and the architectural maximum of 512 w 0 DminLine Data cache minimum line length [19:16] IminLine Instruction cache minimum line length [3:0] Current Cache Size ID register CCSIDR The CCSIDR provides information about the architecture of the currently selected cache 0x80 read-only WT Write-Through. Indicates whether the currently selected cache level supports Write-Through [31:31] Not supported 0 Supported 1 WB Writeback. Indicates whether the currently selected cache level supports writeback [30:30] Not supported 0 Supported 1 RA Read-allocate. Indicates whether the currently selected cache level supports read-allocation [29:29] Not supported 0 Supported 1 WA Write-Allocate. Indicates whether the currently selected cache level supports write-allocation [28:28] Not supported 0 Supported 1 NumSets Number of sets. Indicates (Number of sets in the currently selected cache) - 1 [27:13] LineSize Line size. Indicates (Log2(Number of words per line in the currently selected cache)) - 2 [2:0] Cache Size Selection Register CSSELR Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache type (either instruction or data cache) 0x84 read-write Level Cache level. Selects which cache level is to be identified [3:1] Level 1 cache 0 Level 2 cache 1 Level 3 cache 2 Level 4 cache 3 Level 5 cache 4 Level 6 cache 5 Level 7 cache 6 InD Instruction not data. Selects whether the instruction or the data cache is to be identified [0:0] Data or unified cache 0 Instruction cache 1 Coprocessor Access Control Register CPACR Specifies the access privileges for coprocessors and the FP Extension 0x88 read-write CP11 CP11 Privilege. The value in this field is ignored [23:22] CP10 CP10 Privilege. Defines the access rights for the floating-point functionality [21:20] All accesses to the FP Extension result in NOCP UsageFault 0 Unprivileged accesses to the FP Extension result in NOCP UsageFault 1 Full access to the FP Extension 3 CPm Coprocessor m privilege. Controls access privileges for coprocessor m [0:0] Access denied. Any attempted access generates a NOCP UsageFault 0 Privileged access only. An unprivileged access generates a NOCP UsageFault 1 Full Access 3 Non-secure Access Control Register NSACR Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 0x8C read-write CP11 CP11 access. Enables Non-secure access to the Floating-point Extension [11:11] CP10 CP10 access. Enables Non-secure access to the Floating-point Extension [10:10] Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault 0 Non-secure access to the Floating-point Extension permitted 1 CPm CPm access. Enables Non-secure access to coprocessor CPm [0:0] Non-secure accesses to this coprocessor generate a NOCP UsageFault 0 Non-secure access to this coprocessor permitted 1 MPU Memory Protection Unit 0xE000ED90 0x0 0x40 registers MPU Control Register MPU_CTRL Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NM 0x4 read-write PRIVDEFENA Privileged default enable [2:2] Use of default memory map disabled 0 Use of default memory map enabled for privilege code 1 HFNMIENA HardFault, NMI enable [1:1] MPU disabled for these handlers 0 MPU enabled for these handlers 1 ENABLE Enable. Enables the MPU [0:0] The MPU is disabled 0 The MPU is enabled 1 MPU Memory Attribute Indirection Register 0 MPU_MAIR0 Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndx values 0x30 read-write Attrm Attribute m. Memory attribute encoding for MPU regions with an AttrIndx of m [0:0] MPU Memory Attribute Indirection Register 1 MPU_MAIR1 Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndx values 0x34 read-write Attrm Attribute m. Memory attribute encoding for MPU regions with an AttrIndx of m [0:0] MPU Region Base Address Register MPU_RBAR Provides indirect read and write access to the base address of the currently selected MPU region for the selected Security state 0xC read-write BASE Base address. Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region [31:5] SH Shareability. Defines the Shareability domain of this region for Normal memory [4:3] Non-shareable 0 Outer Shareable 2 Inner Shareable 3 AP[2:1] Access permissions. Defines the access permissions for this region [2:1] Read/write by privileged code only 0 Read/write by any privilege level 1 Read-only by privileged code only 2 Read-only by any privilege level 3 XN Execute Never. Defines whether code can be executed from this region [0:0] Execution only permitted if read permitted 0 Execution not permitted 1 MPU Region Base Address Register Alias %s MPU_RBAR_A_%s Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(n[1:0]) for the selected Security state 0x14 3 8 read-write BASE Base address. Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region [31:5] SH Shareability. Defines the Shareability domain of this region for Normal memory [4:3] Non-shareable 0 Outer Shareable 2 Inner Shareable 3 AP[2:1] Access permissions. Defines the access permissions for this region [2:1] Read/write by privileged code only 0 Read/write by any privilege level 1 Read-only by privileged code only 2 XN Execute Never. Defines whether code can be executed from this region [0:0] Execution only permitted if read permitted 0 Execution not permitted 1 MPU Region Limit Address Register MPU_RLAR Provides indirect read and write access to the limit address of the currently selected MPU region for the selected Security state 0x10 read-write LIMIT Limit address. Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region [31:5] AttrIndx Attribute index. Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] EN Enable. Region enable [0:0] Region disabled 0 Region enabled 1 MPU Region Limit Address Register Alias %s MPU_RLAR_A_%s Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(n[1:0]) for the selected Security state 0x18 3 8 read-write LIMIT Limit address. Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region [31:5] AttrIndx Attribute index. Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] EN Enable. Region enable [0:0] Region disabled 0 Region enabled 1 MPU Region Number Register MPU_RNR Selects the region currently accessed by MPU_RBAR and MPU_RLAR 0x8 read-write REGION Region number. Indicates the memory region accessed by MPU_RBAR and MPU_RLAR [7:0] MPU Type Register MPU_TYPE The MPU Type Register indicates how many regions the MPU for the selected Security state supports 0x0 read-only DREGION Data regions. Number of regions supported by the MPU [15:8] SEPARATE Separate. Indicates support for separate instructions and data address regions [0:0] SAU Security Attribution Unit 0xE000EDD0 0x0 0x1C registers SAU Control Register SAU_CTRL Allows enabling of the Security Attribution Unit 0x0 read-write ALLNS All Non-secure. When SAU_CTRL [1:1] Memory is marked as Secure and is not Non-secure callable 0 Memory is marked as Non-secure 1 ENABLE Enable. Enables the SAU [0:0] The SAU is disabled 0 The SAU is enabled 1 SAU Region Base Address Register SAU_RBAR Provides indirect read and write access to the base address of the currently selected SAU region 0xC read-write BADDR Base address. Holds bits [31:5] of the base address for the selected SAU region [31:5] SAU Region Limit Address Register SAU_RLAR Provides indirect read and write access to the limit address of the currently selected SAU region 0x10 read-write LADDR Limit address. Holds bits [31:5] of the limit address for the selected SAU region [31:5] NSC Non-secure callable [1:1] Region is not Non-secure callable 0 Region is Non-secure callable 1 ENABLE Enable. SAU region enable [0:0] SAU region is disabled 0 SAU region is enabled 1 SAU Region Number Register SAU_RNR Selects the region currently accessed by SAU_RBAR and SAU_RLAR 0x8 read-write REGION Region number. Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR [7:0] SAU Type Register SAU_TYPE Indicates the number of regions implemented by the Security Attribution Unit 0x4 read-only SREGION SAU regions. The number of implemented SAU regions [7:0] Secure Fault Address Register SFAR Shows the address of the memory location that caused a Security violation 0x18 read-write ADDRESS Address. The address of an access that caused an attribution unit violation [31:0] Secure Fault Status Register SFSR Provides information about any security related faults 0x14 read-write LSERR Lazy state error flag [7:7] Error has not occurred 0 Error has occurred 1 SFARVALID Secure fault address valid. This bit is set when the SFAR register contains a valid value [6:6] SFAR content not valid 0 SFAR content valid 1 LSPERR Lazy state preservation error flag [5:5] Error has not occurred 0 Error has occurred 1 INVTRAN Invalid transition flag [4:4] Error has not occurred 0 Error has occurred 1 AUVIOL Attribution unit violation flag [3:3] Error has not occurred 0 Error has occurred 1 INVER Invalid exception return flag. This can be caused by EXC_RETURN [2:2] Error has not occurred 0 Error has occurred 1 INVIS Invalid integrity signature flag [1:1] Error has not occurred 0 Error has occurred 1 INVEP Invalid entry point [0:0] Error has not occurred 0 Error has occurred 1 DCB Debug Control Block 0xE000EDF0 0x0 0x1C registers Debug Authentication Control Register DAUTHCTRL This register allows the IMPLEMENTATION DEFINED authentication interface to be overridden from software 0x14 read-write INTSPNIDEN Internal Secure non-invasive debug enable [3:3] Secure Non-invasive debug prohibited 0 Secure Non-invasive debug allowed 1 SPNIDENSEL Secure non-invasive debug enable select [2:2] Secure non-invasive debug controlled by the IMPLEMENTATION DEFINED external authentication interface 0 INTSPIDEN Internal Secure invasive debug enable [1:1] Secure halting and self-hosted debug prohibited 0 Secure halting and self-hosted debug allowed 1 SPIDENSEL Secure invasive debug enable select [0:0] Secure halting and self-hosted debug controlled by the IMPLEMENTATION DEFINED external authentication interface 0 Debug Core Register Data Register DCRDR provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers 0x8 read-write DBGTMP Data temporary buffer [31:0] Debug Core Register Select Register DCRSR provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers 0x4 write-only REGWnR Register write/not-read. Specifies the access type for the transfer [16:16] Read 0 Write 1 REGSEL Register selector [6:0] If the Main Extension is not implemented 0b0011000 Non-secure main stack pointer, MSP_NS [23:8] If the Main Extension is not implemented the Security Extension is not implemented, this value is reserved [23:8] If the Main Extension is not implemented the Security Extension is not implemented, this value is reserved [23:8] Debug Exception and Monitor Control Register DEMCR Manages vector catch behavior and DebugMonitor handling when debugging 0xC read-write TRCENA Trace enable. Global enable for all DWT and ITM features [24:24] DWT and ITM features disabled 0 DWT and ITM features enabled 1 SDME Secure DebugMonitor enable [20:20] Debug events prohibited in Secure state and the DebugMonitor exception targets Non-secure state 0 Debug events allowed in Secure state and the DebugMonitor exception targets Secure state 1 MON_REQ Monitor request. DebugMonitor semaphore bit [19:19] MON_STEP Monitor step. Enable DebugMonitor stepping [18:18] Stepping disabled 0 Stepping enabled 1 MON_PEND Monitor pend. Sets or clears the pending state of the DebugMonitor exception [17:17] Clear the status of the DebugMonitor exception to not pending 0 Set the status of the DebugMonitor exception to pending 1 MON_EN Monitor enable. Enable the DebugMonitor exception [16:16] DebugMonitor exception disabled 0 DebugMonitor exception enabled 1 VC_SFERR Vector Catch SecureFault. SecureFault exception Halting debug vector catch enable [11:11] Halting debug trap on SecureFault disabled 0 Halting debug trap on SecureFault enabled 1 VC_HARDERR Vector Catch HardFault errors. HardFault exception Halting debug vector catch enable [10:10] Halting debug trap on HardFault disabled 0 Halting debug trap on HardFault enabled 1 VC_INTERR Vector Catch interrupt errors [9:9] Halting debug trap on faults during exception entry and return disabled 0 Halting debug trap on faults during exception entry and return enabled 1 VC_BUSERR Vector Catch BusFault errors. BusFault exception Halting debug vector catch enable [8:8] Halting debug trap on BusFault disabled 0 Halting debug trap on BusFault enabled 1 VC_STATERR Vector Catch state errors [7:7] Halting debug trap on UsageFault caused by state information error disabled 0 Halting debug trap on UsageFault caused by state information error enabled 1 VC_CHKERR Vector Catch check errors [6:6] Halting debug trap on UsageFault caused by checking error disabled 0 Halting debug trap on UsageFault caused by checking error enabled 1 VC_NOCPERR Vector Catch NOCP errors [5:5] Halting debug trap on UsageFault caused by access to a coprocessor disabled 0 Halting debug trap on UsageFault caused by access to a coprocessor enabled 1 VC_MMERR Vector Catch MemManage errors. Enable Halting debug trap on a MemManage exception [4:4] Halting debug trap on MemManage disabled 0 Halting debug trap on MemManage enabled 1 VC_CORERESET Vector Catch core reset. Enable Reset Vector Catch [0:0] Halting debug trap on reset disabled 0 Halting debug trap on reset enabled 1 Debug Halting Control and Status Register DHCSR Controls Halting debug 0x0 read-write DBGKEY Debug key [31:16] Writes accompanied by this value update bits[15:0] 41055 S_RESTART_ST Restart sticky status. Indicates the PE has processed a request to clear DHCSR.C_HALT to 0 [26:26] PE has not left Debug state since the last read of DHCSR 0 PE has left Debug state since the last read of DHCSR 1 S_RESET_ST Reset sticky status. Indicates whether the PE has been reset since the last read of the DHCSR [25:25] No reset since last DHCSR read 0 At least one reset since last DHCSR read 1 S_RETIRE_ST Retire sticky status. Set to 1 every time the PE retires one of more instructions [24:24] No instruction retired since last DHCSR read 0 At least one instruction retired since last DHCSR read 1 S_SDE Secure debug enabled. Indicates whether Secure invasive debug is allowed [20:20] Secure invasive debug prohibited 0 Secure invasive debug allowed 1 S_LOCKUP Lockup status. Indicates whether the PE is in Lockup state [19:19] Not locked up 0 Locked up 1 S_SLEEP Sleeping status. Indicates whether the PE is sleeping [18:18] Not sleeping 0 Sleeping 1 S_HALT Halted status. Indicates whether the PE is in Debug state [17:17] In Non-debug state 0 In Debug state 1 S_REGRDY Register ready status. Handshake flag to transfers through the DCRDR [16:16] Write to DCRSR performed, but transfer not yet complete 0 Transfer complete, or no outstanding transfer 1 C_SNAPSTALL Snap stall control. Allow imprecise entry to Debug state [5:5] No action 0 Allow imprecise entry to Debug state, for example by forcing any stalled load or store instruction to be abandoned 1 C_MASKINTS Mask interrupts control [3:3] Do not mask 0 Mask PendSV, SysTick and external configurable interrupts 1 C_STEP Step control. Enable single instruction step [2:2] No effect 0 Single step enabled 1 C_HALT Halt control. PE enter Debug state halt request [1:1] Causes the PE to leave Debug state, if in Debug state 0 Halt the PE 1 C_DEBUGEN Debug enable control. Enable Halting debug [0:0] Disabled 0 Enabled 1 Debug Security Control and Status Register DSCSR Provides control and status information for Secure debug 0x18 read-write CDSKEY CDS write-enable key [17:17] Concurrent write to CDS not ignored 0 Concurrent write to CDS ignored 1 CDS Current domain Secure. This field indicates the current Security state of the processor [16:16] PE is in Non-secure state 0 PE is in Secure state 1 SBRSEL Secure Banked register select [1:1] Selects the Non-secure versions 0 Selects the Secure versions 1 SBRSELEN Secure Banked register select enable [0:0] The current Security state of the PE determines which memory-mapped banked registers are accessed by the debugger 0 DSCSR 1 SIG Software Interrupt Generation 0xE000EF00 0x0 0x4 registers Software Triggered Interrupt Register STIR Provides a mechanism for software to generate an interrupt 0x0 write-only INTID Interrupt ID. Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) [8:0] INTID This field reads as zero [8:0] FP Floating-Point Extension 0xE000EF34 0x0 0x18 registers Floating-Point Context Address Register FPCAR Holds the location of the unpopulated floating-point register space allocated on an exception stack frame 0x4 read-write ADDRESS Address [31:3] Floating-Point Context Control Register FPCCR Holds control data for the Floating-point extension 0x0 read-write ASPEN Automatic state preservation enable [31:31] Executing a floating-point instruction has no effect on CONTROL.FPCA 0 Executing a floating-point instruction sets CONTROL.FPCA to 1 1 LSPEN Lazy state preservation enable. Enables lazy context save of floating-point state [30:30] Disable automatic lazy context save 0 Enable automatic lazy context save 1 LSPENS Lazy state preservation enable Secure only [29:29] LSPEN is readable and writeable from both Security states 0 LSPEN is readable from both Security states, but writes to LSPEN are ignored from the Non-secure state 1 CLRONRET Clear on return. Clear floating-point caller saved registers on exception return [28:28] Disabled 0 Enabled 1 CLRONRETS Clear on return Secure only [27:27] The CLRONRET field is accessibly from both Security states 0 The Non-secure view of the CLRONRET field is read-only 1 TS Treat as Secure. Treat floating-point registers as Secure enable [26:26] Disabled 0 Enabled 1 UFRDY UsageFault ready [10:10] Not able to set the UsageFault exception to pending 0 Able to set the UsageFault exception to pending 1 SPLIMVIOL Stack pointer limit violation [9:9] The existing behavior is retained 0 The memory accesses associated with the floating-point state preservation are not performed 1 MONRDY DebugMonitor ready [8:8] Not able to set the DebugMonitor exception to pending 0 Able to set the DebugMonitor exception to pending 1 SFRDY SecureFault ready [7:7] BFRDY BusFault ready [6:6] Not able to set the BusFault exception to pending 0 Able to set the BusFault exception to pending 1 MMRDY MemManage ready [5:5] Not able to set the MemManage exception to pending 0 Able to set the MemManage exception to pending 1 HFRDY HardFault ready [4:4] Not able to set the HardFault exception to pending 0 Able to set the HardFault exception to pending 1 THREAD Thread mode. Indicates the PE mode when it allocated the floating-point stack frame [3:3] Handler mode 0 Thread mode 1 S Security. Security status of the floating-point context [2:2] Indicates the floating-point context belongs to the Non-secure state 0 Indicates the floating-point context belongs to the Secure state 1 USER User privilege [1:1] Privileged 0 Unprivileged 1 LSPACT Lazy state preservation active [0:0] Lazy state preservation is not active 0 Lazy state preservation is active 1 Floating-Point Default Status Control Register FPDSCR Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context 0x8 read-write AHP Alternative half-precision. Default value for FPSCR.AHP [26:26] DN Default NaN. Default value for FPSCR.DN [25:25] FZ Flush-to-zero. Default value for FPSCR.FZ [24:24] RMode Rounding mode. Default value for FPSCR.RMode [23:22] Media and VFP Feature Register 0 MVFR0 Describes the features provided by the Floating-point Extension 0xC read-only FPRound Floating-point rounding modes. Indicates the rounding modes supported by the FP Extension [31:28] All rounding modes supported 1 FPSqrt Floating-point square root. Indicates the support for FP square root operations [23:20] Supported 1 FPDivide Floating-point divide. Indicates the support for FP divide operations [19:16] Supported 1 3SIMDReg4 7FPSP8 11FPDP12 15RES016 19FPDivide20 23FPSqrt24 27RES028 31FPRoundD1 Register Specification D1 0 FPDP Floating-point double-precision. Indicates support for FP double-precision operations [11:8] Not supported 0 Supported 2 FPSP Floating-point single-precision. Indicates support for FP single-precision operations [7:4] Supported 2 SIMDReg SIMD registers. Indicates size of FP register file [3:0] 16 × 64-bit registers 1 Media and VFP Feature Register 1 MVFR1 Describes the features provided by the Floating-point Extension 0x10 read-only FMAC Fused multiply accumulate [31:28] Implemented 1 FPHP Floating-point half-precision [27:24] Half-precision to single-precision implemented 1 Half-precision to single and double-precision implemented 2 FPDNaN Floating-point default NaN [7:4] Propagation of NaN values supported 1 FPFtZ Floating-point flush-to-zero. Indicates whether subnormals are always flushed-to-zero [3:0] Full denormalized numbers arithmetic supported 1 Media and VFP Feature Register 2 MVFR2 Describes the features provided by the Floating-point Extension 0x14 read-only FPMisc Floating-point miscellaneous. Indicates support for miscellaneous FP features [7:4] Selection, directed conversion to integer, VMINNM and VMAXNM supported 4 CMO Cache Maintenance Operations 0xE000EF50 0x0 0x2C registers Branch Predictor Invalidate All BPIALL Invalidate all entries from branch predictors 0x28 write-only Ignored Ignored. The value written to this field is ignored [31:0] Data Cache line Clean and Invalidate by Address to PoC DCCIMVAC Clean and invalidate data or unified cache line by address to PoC 0x20 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Clean and Invalidate by Set/Way DCCISW Clean and invalidate data or unified cache line by set/way 0x24 write-only SetWay Cache set/way. Contains two fields: Way, bits[31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Data Cache line Clean by Address to PoC DCCMVAC Clean data or unified cache line by address to PoC 0x18 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Clean by address to PoU DCCMVAU Clean data or unified cache line by address to PoU 0x14 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache Clean line by Set/Way DCCSW Clean data or unified cache line by set/way 0x1C write-only SetWay Cache set/way. Contains two fields: Way, bits [31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Data Cache line Invalidate by Address to PoC DCIMVAC Invalidate data or unified cache line by address to PoC 0xC write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Invalidate by Set/Way DCISW Invalidate data or unified cache line by set/way 0x10 write-only SetWay Cache set/way. Contains two fields: Way, bits[31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Instruction Cache Invalidate All to PoU ICIALLU Invalidate all instruction caches to PoU 0x0 write-only Ignored The value written to this field is ignored. Ignored [31:0] Instruction Cache line Invalidate by Address to PoU ICIMVAU Invalidate instruction cache line by address to PoU 0x8 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] DIB Debug Identification Block 0xE000EFB0 0x0 0x50 registers Debug Authentication Status Register DAUTHSTATUS Provides information about the state of the IMPLEMENTATION DEFINED authentication interface for debug 0x8 read-only SNID Secure Non-invasive Debug. Indicates whether Secure non-invasive debug is allowed [7:6] Security Extension not implemented 0 Reserved 1 Security Extension implemented and Secure non-invasive debug prohibited 2 Security Extension implemented and Secure non-invasive debug allowed 3 SID Secure Invasive Debug. Indicates whether Secure invasive debug is allowed [5:4] Security Extension not implemented 0 Reserved 1 Security Extension implemented and Secure invasive debug prohibited 2 Security Extension implemented and Secure invasive debug allowed 3 NSNID Non-secure Non-invasive Debug. Indicates whether Non-secure non-invasive debug is allowed [3:2] NSID Non-secure Invasive Debug. Indicates whether Non-secure invasive debug is allowed [1:0] SCS Component Identification Register 0 DCIDR0 Provides CoreSight discovery information for the SCS 0x40 read-only PRMBL_0 CoreSight component identification preamble [7:0] SCS Component Identification Register 1 DCIDR1 Provides CoreSight discovery information for the SCS 0x44 read-only CLASS CoreSight component class. See the CoreSight Architecture Specification [7:4] PRMBL_1 CoreSight component identification preamble [3:0] SCS Component Identification Register 2 DCIDR2 Provides CoreSight discovery information for the SCS 0x48 read-only PRMBL_2 CoreSight component identification preamble [7:0] SCS Component Identification Register 3 DCIDR3 Provides CoreSight discovery information for the SCS 0x4C read-only PRMBL_3 CoreSight component identification preamble [7:0] SCS Device Architecture Register DDEVARCH Provides CoreSight discovery information for the SCS 0xC read-only ARCHITECT Architect. Defines the architect of the component [31:21] JEP106 continuation code 0x4, ID code 0x3B. ARM Limited 571 PRESENT DEVARCH Present. Defines that the DEVARCH register is present [20:20] DEVARCH information present 1 REVISION Revision. Defines the architecture revision of the component [19:16] M-profile debug architecture v3.0 0 ARCHVER Architecture Version. Defines the architecture version of the component [15:12] M-profile debug architecture v3 2 ARCHPART Architecture Part. Defines the architecture of the component [11:0] M-profile debug architecture 2564 SCS Device Type Register DDEVTYPE Provides CoreSight discovery information for the SCS 0x1C read-only SUB Subtype. Component subtype [7:4] Other 0 MAJOR Major type. CoreSight major type [3:0] Miscellaneous 0 SCS Software Lock Access Register DLAR Provides CoreSight Software Lock control for the SCS, see the CoreSight Architecture Specification for details 0x0 write-only KEY Lock Access control [31:0] SCS Software Lock Status Register DLSR Provides CoreSight Software Lock status information for the SCS, see the CoreSight Architecture Specification for details 0x4 read-only nTT Not thirty-two bit. See the CoreSight Architecture Specification [2:2] SLK Software Lock status. See the CoreSight Architecture Specification [1:1] Lock clear. Software writes are permitted to this component's registers 0 Lock set 1 SLI Software Lock implemented. See the CoreSight Architecture Specification [0:0] Software Lock not implemented or debugger access 0 Software Lock is implemented and software access 1 SCS Peripheral Identification Register 0 DPIDR0 Provides CoreSight discovery information for the SCS 0x30 read-only PART_0 Part number bits [7:0]. See the CoreSight Architecture Specification [7:0] SCS Peripheral Identification Register 1 DPIDR1 Provides CoreSight discovery information for the SCS 0x34 read-only DES_0 JEP106 identification code bits [3:0]. See the CoreSight Architecture Specification [7:4] PART_1 Part number bits [11:8]. See the CoreSight Architecture Specification [3:0] SCS Peripheral Identification Register 2 DPIDR2 Provides CoreSight discovery information for the SCS 0x38 read-only REVISION Component revision. See the CoreSight Architecture Specification [7:4] JEDEC JEDEC assignee value is used. See the CoreSight Architecture Specification [3:3] DES_1 JEP106 identification code bits [6:4]. See the CoreSight Architecture Specification [2:0] SCS Peripheral Identification Register 3 DPIDR3 Provides CoreSight discovery information for the SCS 0x3C read-only REVAND RevAnd. See the CoreSight Architecture Specification [7:4] CMOD Customer Modified. See the CoreSight Architecture Specification [3:0] SCS Peripheral Identification Register 4 DPIDR4 Provides CoreSight discovery information for the SCS 0x20 read-only SIZE 4KB count. See the CoreSight Architecture Specification [7:4] DES_2 JEP106 continuation code. See the CoreSight Architecture Specification [3:0] SCS Peripheral Identification Register 5 DPIDR5 Provides CoreSight discovery information for the SCS 0x24 read-only SCS Peripheral Identification Register 6 DPIDR6 Provides CoreSight discovery information for the SCS 0x28 read-only SCS Peripheral Identification Register 7 DPIDR7 Provides CoreSight discovery information for the SCS 0x2C read-only TPIU Trace Port Interface Unit 0xE0040000 0x0 0x1000 registers TPIU Asynchronous Clock Prescaler Register TPIU_ACPR Defines a prescaler value for the baud rate of the Serial Wire Output (SWO) 0x10 read-write SWOSCALER SWO baud rate prescalar [15:0] TPIU Component Identification Register 0 TPIU_CIDR0 Provides CoreSight discovery information for the TPIU 0xFF0 read-only PRMBL_0 CoreSight component identification preamble [7:0] TPIU Component Identification Register 1 TPIU_CIDR1 Provides CoreSight discovery information for the TPIU 0xFF4 read-only CLASS CoreSight component class. See the CoreSight Architecture Specification [7:4] PRMBL_1 CoreSight component identification preamble [3:0] TPIU Component Identification Register 2 TPIU_CIDR2 Provides CoreSight discovery information for the TPIU 0xFF8 read-only PRMBL_2 CoreSight component identification preamble [7:0] TPIU Component Identification Register 3 TPIU_CIDR3 Provides CoreSight discovery information for the TPIU 0xFFC read-only PRMBL_3 CoreSight component identification preamble [7:0] TPIU Current Parallel Port Sizes Register TPIU_CSPSR Controls the width of the parallel trace port 0x4 read-write CWIDTH Current width. CWIDTH[m] represents a parallel trace port width of (m+1) [31:0] Width (N+1) is not the current parallel trace port width 0 Width (N+1) is the current parallel trace port width 1 debugger must set only one bit is set to 1, and all others must be zero 2 TPIU Device Type Register TPIU_DEVTYPE Provides CoreSight discovery information for the TPIU 0xFCC read-only SUB Subtype. Component subtype [7:4] Other. Only permitted if the MAJOR field reads as 0x0 0 Trace port. Only permitted if the MAJOR field reads as 0x1 1 MAJOR Major type. Component major type [3:0] Miscellaneous 0 Trace sink 1 TPIU Formatter and Flush Control Register TPIU_FFCR Controls the TPIU formatter 0x304 read-write TrigIn Trigger input asserted [8:8] FOnMan Flush On Manual. Setting this bit to 1 generates a flush [6:6] EnFmt Formatter control. Selects the output formatting mode [1:0] Bypass. Disable formatting. Only supported when SWO mode is selected 0 TPIU Formatter and Flush Status Register TPIU_FFSR Shows the status and capabilities of the TPIU formatter 0x300 read-only FtNonStop Non-stop formatter. Indicates the formatter cannot be stopped [3:3] Formatter can be stopped 0 Formatter cannot be stopped 1 TCPresent TRACECTL present. Indicates presence of the TRACECTL pin [2:2] No TRACECTL pin is available 0 FtStopped Formatter stopped. Indicates the formatter is stopped [1:1] Formatter is enabled 0 Formatter is stopped 1 FInProg Flush in progress [0:0] TPIU Software Lock Access Register TPIU_LAR Provides CoreSight Software Lock control for the TPIU, see the CoreSight Architecture Specification for details 0xFB0 write-only KEY Lock Access control [31:0] TPIU Software Lock Status Register TPIU_LSR Provides CoreSight Software Lock status information for the TPIU, see the CoreSight Architecture Specification for details 0xFB4 read-only nTT Not thirty-two bit. See the CoreSight Architecture Specification [2:2] SLK Software Lock status. See the CoreSight Architecture Specification [1:1] Lock clear. Software writes are permitted to this component's registers 0 Lock set 1 SLI Software Lock implemented. See the CoreSight Architecture Specification [0:0] Software Lock not implemented or debugger access 0 Software Lock is implemented and software access 1 TPIU Peripheral Identification Register 0 TPIU_PIDR0 Provides CoreSight discovery information for the TPIU 0xFE0 read-only PART_0 Part number bits [7:0]. See the CoreSight Architecture Specification [7:0] TPIU Peripheral Identification Register 1 TPIU_PIDR1 Provides CoreSight discovery information for the TPIU 0xFE4 read-only DES_0 JEP106 identification code bits [3:0]. See the CoreSight Architecture Specification [7:4] PART_1 Part number bits [11:8]. See the CoreSight Architecture Specification [3:0] TPIU Peripheral Identification Register 2 TPIU_PIDR2 Provides CoreSight discovery information for the TPIU 0xFE8 read-only REVISION Component revision. See the CoreSight Architecture Specification [7:4] JEDEC JEDEC assignee value is used. See the CoreSight Architecture Specification [3:3] DES_1 JEP106 identification code bits [6:4]. See the CoreSight Architecture Specification [2:0] TPIU Peripheral Identification Register 3 TPIU_PIDR3 Provides CoreSight discovery information for the TPIU 0xFEC read-only REVAND RevAnd. See the CoreSight Architecture Specification [7:4] CMOD Customer Modified. See the CoreSight Architecture Specification [3:0] TPIU Peripheral Identification Register 4 TPIU_PIDR4 Provides CoreSight discovery information for the TPIU 0xFD0 read-only SIZE 4KB count. See the CoreSight Architecture Specification [7:4] DES_2 JEP106 continuation code. See the CoreSight Architecture Specification [3:0] TPIU Peripheral Identification Register 5 TPIU_PIDR5 Provides CoreSight discovery information for the TPIU 0xFD4 read-only TPIU Peripheral Identification Register 6 TPIU_PIDR6 Provides CoreSight discovery information for the TPIU 0xFD8 read-only TPIU Peripheral Identification Register 7 TPIU_PIDR7 Provides CoreSight discovery information for the TPIU 0xFDC read-only TPIU Periodic Synchronization Control Register TPIU_PSCR Defines the reload value for the Periodic Synchronization Counter register 0x308 read-write PSCount Periodic Synchronization Count [4:0] Synchronization disabled 0 128 bytes 7 256 bytes 8 TPIU Selected Pin Protocol Register TPIU_SPPR Selects the protocol used for trace output 0xF0 read-write TXMODE Transmit mode. Specifies the protocol for trace output from the TPIU [1:0] Parallel trace port mode. This value is reserved if TPIU_TYPE.PTINVALID == 1 0 Asynchronous SWO, using Manchester encoding 1 TPIU Supported Parallel Port Sizes Register TPIU_SSPSR Indicates the supported parallel trace port sizes 0x0 read-only SWIDTH Supported width. SWIDTH[m] indicates whether a parallel trace port width of (m+1) is supported [31:0] Parallel trace port width (m+1) not supported 0 Parallel trace port width (m+1) supported 1 TPIU Device Identifier Register TPIU_TYPE Describes the TPIU to a debugger 0xFC8 read-only NRZVALID NRZ valid. Indicates support for SWO using UART/NRZ encoding [11:11] Not supported 0 Supported 1 MANCVALID Manchester valid. Indicates support for SWO using Manchester encoding [10:10] Not supported 0 Supported 1 PTINVALID Parallel Trace Interface invalid. Indicates support for parallel trace port operation [9:9] Supported 0 Not supported 1 FIFOSZ FIFO depth. Indicates the minimum implemented size of the TPIU output FIFO for trace data [8:6] IMPLEMENTATION DEFINED FIFO depth 0