CM0 Cortex-M0 State Current CPU State 1 Core CPU registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 8 R9 General purpose register 9 9 R10 General purpose register 10 10 R11 General purpose register 11 11 R12 General purpose register 12 12 R13 SP R13 (SP) Stack pointer (SP) 13 R14 LR R14 (LR) Link register (LR) 14 R15 PC R15 (PC) Program counter (PC) 15 xPSR Program status register 16 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 T Thumb state bit 24 1 ISR Number Interrupt service routine number 0 6 MSP Main stack pointer 17 PSP Process stack pointer 18 APSR Application program status register 21 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 EPSR Exception program status register 22 T Thumb state bit 24 1 IPSR Interrupt program status register 23 ISR Number Interrupt service routine number 0 6 PriMask Priority mask register 24 PriMask Prevent the activation of all exceptions with configurable priority 0 1 Control Control register 27 SPSEL Active stack pointer 24 1 CycleCount Cycle count 65 Peripherals Memory-Mapped CPU Registers 32 RW unsigned int DWT Data Watchpoint and Trace 0xE0001000 0x0 0x1000 registers Control register DWT_CTRL Provides configuration and status information for the DWT unit, and used to control features of the unit 0x0 read-only NUMCOMP Number of comparators implemented [31:28] Program Counter Sample Register DWT_PCSR Samples the current value of the program counter 0x1C read-only EIASAMPLE Executed Instruction Address sample value [31:0] Comparator register DWT_COMP_%s Provides a reference value for use by comparator n 0x20 read-write 8 4 COMP Reference value for comparison [31:0] Comparator Mask register %s DWT_MASK_%s Provides the size of the ignore mask applied to the access address for address range matching by comparator n 0x24 read-write 8 4 MASK The size of the ignore mask, 0-31 bits, applied to address range matching [4:0] Comparator Function register %s DWT_FUNCTION_%s Controls the operation of comparator n 0x28 read-write 8 4 MATCHED Comparator match [24:24] No match 0 Match 1 FUNCTION Selects action taken on comparator match [3:0] BPU Breakpoint Unit 0xE0002000 0x0 0x1000 registers Breakpoint Control Register BP_CTRL Provides BPU implementation information, and the global enable for the BPU 0x0 read-write NUM_CODE The number of breakpoint comparators [7:4] KEY On any write to FP_CTRL, this bit must be 1 [1:1] ENABLE Enable bit for the FPB [0:0] Flash Patch Breakpoint disabled 0 Flash Patch Breakpoint enabled 1 Breakpoint Comparator Register %s BP_COMP_%s Holds a breakpoint address for comparison with instruction addresses in the Code memory region 0x8 read-write 8 4 BP_MATCH defines the behavior when the COMP address is matched [31:30] no breakpoint matching 0 Breakpoint on lower halfword, upper is unaffected 1 Breakpoint on upper halfword, lower is unaffected 2 Breakpoint on both lower and upper halfwords 3 COMP Stores bits [28:2] of the comparison address [28:2] BE enables the comperator [0:0] Disabled 0 Enabled 1 ICB Implementation Control Block 0xE000E008 0x0 0xC registers Auxiliary Control Register ACTLR Provides IMPLEMENTATION DEFINED configuration and control options 0x0 read-write SYSTICK SysTick Timer 0xE000E010 0x0 0x10 registers SysTick Control and Status Register SYST_CSR Controls the system timer and provides status data 0x0 read-write COUNTFLAG Indicates whether the counter has counted to 0 since the last read of this register [16:16] Timer has not counted to 0 0 Timer has counted to 0 1 CLKSOURCE Indicates the SysTick clock source [2:2] SysTick uses the IMPLEMENTATION DEFINED external reference clock 0 SysTick uses the processor clock 1 TICKINT Indicates whether counting to 0 causes the status of the SysTick exception to change to pending [1:1] Count to 0 does not affect the SysTick exception status 0 Count to 0 changes the SysTick exception status to pending 1 ENABLE Indicates the enabled status of the SysTick counter [0:0] Counter is disabled 0 Counter is operating 1 SysTick Reload Value Register SYST_RVR Holds the reload value of the SYST_CVR 0x4 read-write RELOAD The value to load into the SYST_CVR when the counter reaches 0 [23:0] SysTick Current Value Register SYST_CVR Reads or clears the current counter value 0x8 read-write CURRENT Current counter value [31:0] SysTick Calibration value Register SYST_CALIB Reads the calibration value and parameters for SysTick 0xC read-only NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented [31:31] The reference clock is implemented 0 The reference clock is not implemented 1 SKEW Indicates whether the 10ms calibration value is exact [30:30] 10ms calibration value is exact 0 10ms calibration value is inexact, because of the clock frequency 1 TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors [23:0] NVIC Nested Vectored Interrupt Controller 0xE000E100 0x0 0x4F0 registers Interrupt Set-Enable Register %s NVIC_ISER_%s Enables, or reads the enable state of a group of interrupts 0x0 16 4 read-write SETENA_%s For register NVIC_ISERn, enables or shows the current enabled state of interrupt (m+(32*n)) [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Clear-Enable Register %s NVIC_ICER_%s Disables, or reads the enable state of, a group of registers 0x80 16 4 read-write CLRENA_%s For register NVIC_ICERn, disables or shows the current enabled state of interrupt (m+(32*n)) [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Set-Pending Register %s NVIC_ISPR_%s For a group of interrupts, changes interrupt status to pending, or shows the current pending status 0x100 16 4 read-write SETPEND_%s For register NVIC_ISPRn, changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending 1 Interrupt Clear-Pending Register %s NVIC_ICPR_%s For a group of interrupts, clears the interrupt pending status, or shows the current pending status 0x180 16 4 read-write CLRPEND_%s For register NVIC_ICPRn, clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending 1 Interrupt Priority Register %s NVIC_IPR_%s Sets or reads interrupt priorities 0x300 124 4 read-write PRI_N3 For register NVIC_IPRn, priority of interrupt number 4n+3 [31:24] PRI_N2 For register NVIC_IPRn, priority of interrupt number 4n+2 [23:16] PRI_N1 For register NVIC_IPRn, priority of interrupt number 4n+1 [15:8] PRI_N0 For register NVIC_IPRn, priority of interrupt number 4n [7:0] SCB System Control Block 0xE000ED00 0x0 0x90 registers CPUID Base Register CPUID Provides identification information for the processor 0x0 read-only IMPLEMENTER Implementer code assigned by ARM [31:24] VARIANT IMPLEMENTATION DEFINED variant number [23:20] ARCHITECTURE Reads as 0xF [19:16] PARTNO IMPLEMENTATION DEFINED part number [15:4] REVISION IMPLEMENTATION DEFINED revision number [3:0] Interrupt Control and State Register ICSR Provides software control of the NMI, PendSV, and SysTick exceptions, and provides interrupt status information 0x4 read-write NMIPENDSET On writes, makes the NMI exception active [31:31] On writes, has no effect. On reads, NMI is inactive 0 On writes, make the NMI exception active. On reads, NMI is active 1 PENDSVSET On writes, sets the PendSV exception as pending [28:28] On writes, has no effect. On reads, PendSV is not pending 0 On writes, make PendSV exception pending. On reads, PendSV is pending 1 PENDSVCLR Removes the pending status of the PendSV exception [27:27] No effect 0 Remove pending status 1 PENDSTSET On writes, sets the SysTick exception as pending [26:26] On writes, has no effect. On reads, SysTick is not pending 0 On writes, make SysTick exception pending. On reads, SysTick is pending 1 PENDSTCLR Removes the pending status of the SysTick exception [25:25] No effect 0 Remove pending status 1 ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state [23:23] Will not service 0 Will service a pending exception 1 ISRPENDING Indicates whether an external interrupt, generated by the NVIC, is pending [22:22] No external interrupt pending 0 External interrupt pending 1 VECTPENDING The exception number of the highest priority pending and enabled interrupt [20:12] RETTOBASE In Handler mode, indicates whether there is an active exception other than the exception indicated by the current value of the IPSR [11:11] There is an active exception other than the exception shown by IPSR 0 There is no active exception other than any exception shown by IPSR 1 VECTACTIVE The exception number of the current executing exception [8:0] Vector Table Offset Register VTOR Holds the vector table address 0x8 read-write TBLOFF Bits[31:7] of the vector table address [31:7] Application Interrupt and Reset Control Register AIRCR Sets or returns interrupt control data 0xC read-write VECTKEY Vector Key. The value 0x05FA must be written to this register. [31:16] Do not request a reset 0 Request reset 1 ENDIANNESS Indicates the memory system endianness [15:15] Little endian 0 Big endian 1 SYSRESETREQ System Reset Request [2:2] Do not request a reset 0 Request reset 1 VECTCLRACTIVE Writing 1 to this bit clears all active state information for fixed and configurable exceptions [1:1] System Control Register SCR Sets or returns system control data 0x10 read-write SEVONPEND Determines whether an interrupt transition from inactive state to pending state is a wakeup event [4:4] Transitions from inactive to pending are not wakeup events 0 Transitions from inactive to pending are wakeup events 1 SLEEPDEEP Provides a qualifying hint indicating that waking from sleep might take longer [2:2] Selected sleep state is not deep sleep 0 Selected sleep state is deep sleep 1 SLEEPONEXIT Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state [1:1] Do not enter sleep state 0 Enter sleep state 1 Configuration and Control Register CCR Sets or returns configuration and control data, and provides control over caching and branch prediction 0x14 read-write STKALIGN Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state [9:9] Guaranteed SP alignment is 4-byte, no SP adjustment is performed 0 8-byte alignment guaranteed, SP adjusted if necessary 1 UNALIGN_TRP Controls the trapping of unaligned word or halfword accesses [3:3] Trapping disabled 0 Trapping enabled 1 System Handler Priority Register 2 SHPR2 Sets or returns priority for system handlers 8-11 0x1C read-write PRI_11 Priority of system handler 11, SVCall [31:24] System Handler Priority Register 3 SHPR3 Sets or returns priority for system handlers 12-15 0x20 read-write PRI_15 Priority of system handler 15, SysTick [31:24] PRI_14 Priority of system handler 14, PendSV [23:16] System Handler Control and State Register SHCSR Controls and provides the active and pending status of system exceptions 0x24 read-write SVCALLPENDED [15:15] SVCall is not pending 0 SVCall is pending 1 Debug Fault Status Register DFSR Shows which debug event occurred 0x30 read-write EXTERNAL Indicates a debug event generated because of the assertion of an external debug request [4:4] No external debug request debug event 0 External debug request debug event 1 VCATCH Indicates triggering of a Vector catch [3:3] No Vector catch triggered 0 Vector catch triggered 1 DWTTRAP Indicates a debug event generated by the DWT [2:2] No debug events generated by the DWT 0 At least one debug event generated by the DWT 1 BKPT Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB [1:1] No breakpoint debug event 0 At least one breakpoint debug event 1 HALTED Indicates a debug event generated by either a halt or step request [0:0] No halt request debug event 0 Halt request debug event 1 MPU Memory Protection Unit 0xE000ED90 0x0 0x2C registers MPU Type Register MPU_TYPE The MPU Type Register indicates how many regions the MPU support 0x0 read-only IREGION Instruction region [23:16] DREGION Number of regions supported by the MPU [15:8] SEPARATE Indicates support for separate instruction and data address maps. RAZ. ARMv6-M only supports a unified MPU [0:0] MPU Control Register MPU_CTRL Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs 0x4 read-write PRIVDEFENA When the ENABLE bit is set to 1, the meaning of this bit is [2:2] Disables the default memory map 0 Enables the default memory map as a background region for privileged access 1 HFNMIENA When the ENABLE bit is set to 1, controls whether handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled [1:1] Disables the MPU for these handlers 0 Use the MPU for memory accesses by these handlers 1 ENABLE Enables the MPU [0:0] The MPU is disabled 0 The MPU is enabled 1 MPU Region Number Register MPU_RNR Selects the region currently accessed by MPU_RBAR and MPU_RASR 0x8 read-write REGION Indicates the memory region accessed by MPU_RBAR and MPU_RASR [7:0] MPU Region Base Address Register MPU_RBAR Holds the base address of the region identified by MPU_RNR 0xC read-write ADDR Base address of the region [31:5] VALID On writes, indicates whether the region to update is specified by MPU_RNR [4:4] Apply the base address update to the region specified by MPU_RNR.REGION 0 Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write 1 REGION On writes, can specify the number of the region to update [3:0] MPU Region Attribute and Size Register MPU_RASR Defines the size and access behavior of the region identified by MPU_RNR, and enables that region 0x10 read-write ATTRS The MPU Region Attribute field [31:16] SRD Subregion Disable [15:8] Subregion enabled 0 Subregion disabled 1 SIZE Indicates the region size [5:1] ENABLE Enables this region [0:0] When the MPU is enabled, this region is disabled 0 When the MPU is enabled, this region is enabled 1 DCB Debug Control Block 0xE000EDF0 0x0 0x10 registers Debug Halting Control and Status Register DHCSR Controls halting debug 0x0 read-write DBGKEY Debug key [31:16] S_RESET_ST Indicates whether the processor has been reset since the last read of DHCSR [25:25] No reset since last DHCSR read 0 At least one reset since last DHCSR read 1 S_RETIRE_ST Set to 1 every time the processor retires one or more instructions [24:24] No instruction retired since last DHCSR read 0 At least one instruction retired since last DHCSR read 1 S_LOCKUP Indicates whether the processor is locked up because of an unrecoverable exception [19:19] Not locked up 0 Locked up 1 S_SLEEP Indicates whether the processor is sleeping [18:18] Not sleeping 0 Sleeping 1 S_HALT Indicates whether the processor is in Debug state [17:17] In Non-debug state 0 In Debug state 1 S_REGRDY A handshake flag for transfers through the DCRDR [16:16] There has been a write to the DCRDR, but the transfer is not complete 0 The transfer to or from the DCRDR is complete 1 C_SNAPSTALL Allow imprecise entry to Debug state [5:5] No action 0 Allow imprecise entry to Debug state, for example by forcing any stalled load or store instruction to complete 1 C_MASKINTS When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts [3:3] Do not mask 0 Mask PendSV, SysTick and external configurable interrupts 1 C_STEP Processor step bit [2:2] No effect 0 Single step enabled 1 C_HALT Processor halt bit [1:1] Causes the processor to leave Debug state, if in Debug state 0 Halt the processor 1 C_DEBUGEN Halting debug enable bit [0:0] Disabled 0 Enabled 1 Debug Core Register Selector Register DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension regi 0x4 write-only REGWnR Specifies the access type for the transfer [16:16] Read 0 Write 1 REGSEL Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer [6:0] The current SP 13 LR 14 DebugReturnAddress 15 xPSR 16 Main stack pointer, MSP 17 Process stack pointer, PSP 18 Control, Faultmask, Basepri and Primask 20 Floating-point Status and Control Register, FPSCR 33 Debug Core Register Data Register DCRDR the DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extensio 0x8 read-write DBGTMP Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers [31:0] Debug Exception and Monitor Control Register DEMCR Manages vector catch behavior and DebugMonitor handling when debugging 0xC read-write TRCENA Global enable for all DWT and ITM features [24:24] DWT and ITM units disabled 0 DWT and ITM units enabled 1 MON_REQ DebugMonitor semaphore bit [19:19] MON_STEP When MON_EN is set to 0, this feature is disabled and the processor ignores MON_STEP [18:18] Do not step the processor 0 Step the processor 1 MON_PEND Sets or clears the pending state of the DebugMonitor exception [17:17] Clear the status of the DebugMonitor exception to not pending 0 Set the status of the DebugMonitor exception to pending 1 MON_EN Enable the DebugMonitor exception [16:16] DebugMonitor exception disabled 0 DebugMonitor exception enabled 1 VC_HARDERR Enable halting debug trap on a HardFault exception [10:10] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_INTERR Enable halting debug trap on a fault occurring during exception entry or exception return [9:9] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_BUSERR Enable halting debug trap on a BusFault exception [8:8] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_STATERR Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception [7:7] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_CHKERR Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error [6:6] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_NOCPERR Enable halting debug trap on a UsageFault caused by an access to a Coprocessor [5:5] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_MMERR Enable halting debug trap on a MemManage exception [4:4] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_CORERESET Enable Reset Vector Catch [0:0] Reset Vector Catch disabled 0 Reset Vector Catch enabled 1