CA9_D16 Cortex-A9 (D16) State Current CPU State 1 Core (Now) Current State CPU Registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 74 R9 General purpose register 9 75 R10 General purpose register 10 76 R11 General purpose register 11 77 R12 General purpose register 12 78 R13 SP R13 (SP) Stack pointer (SP) 79 R14 LR R14 (LR) Link register (LR) 80 R15 PC R15 (PC) Program counter (PC) 9 CPSR Current program status register 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 FPU Floating Point Registers 32 RW float S0 Floating point register 0 40 S1 Floating point register 1 41 S2 Floating point register 2 42 S3 Floating point register 3 43 S4 Floating point register 4 44 S5 Floating point register 5 45 S6 Floating point register 6 46 S7 Floating point register 7 47 S8 Floating point register 8 48 S9 Floating point register 9 49 S10 Floating point register 10 50 S11 Floating point register 11 51 S12 Floating point register 12 52 S13 Floating point register 13 53 S14 Floating point register 14 54 S15 Floating point register 15 55 S16 Floating point register 16 56 S17 Floating point register 17 57 S18 Floating point register 18 58 S19 Floating point register 19 59 S20 Floating point register 20 60 S21 Floating point register 21 61 S22 Floating point register 22 62 S23 Floating point register 23 63 S24 Floating point register 24 64 S25 Floating point register 25 65 S26 Floating point register 26 66 S27 Floating point register 27 67 S28 Floating point register 28 68 S29 Floating point register 29 69 S30 Floating point register 30 70 S31 Floating point register 31 71 FPSID Floating point system information register RO 0x41033094 unsigned int 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 0x0 unsigned int 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 AHP Alternative half-precision control bit 26 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 0x0 unsigned int 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 0x10110221 unsigned int 72 RB Sixteen 64-bit registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 0x01000011 unsigned int 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 FMAC Fused multiply accumulate operations supported 28 4 FPU (Double) Floating Point Registers (double-precision) 64 RW double D0 Floating point register 0 40 41 D1 Floating point register 1 42 43 D2 Floating point register 2 44 45 D3 Floating point register 3 46 47 D4 Floating point register 4 48 49 D5 Floating point register 5 50 51 D6 Floating point register 6 52 53 D7 Floating point register 7 54 55 D8 Floating point register 8 56 57 D9 Floating point register 9 58 59 D10 Floating point register 10 60 61 D11 Floating point register 11 62 63 D12 Floating point register 12 64 65 D13 Floating point register 13 66 67 D14 Floating point register 14 68 69 D15 Floating point register 15 70 71 FPSID Floating point system information register RO 32 0x41023140 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 32 0x0 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 IOE Invalid operation exception enable bit 8 1 DZE Division by zero exception enable bit 9 1 OFE Overflow exception enable bit 10 1 UFE Underflow exception enable bit 11 1 IXE Inexact exception enable bit 12 1 IDE Input Subnormal exception enable bit 15 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 QC Saturation cumulative flag 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 32 0x0 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 32 0x10110221 72 RB Sixteen 64-bir registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 32 0x00000011 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 Core (All) All CPU Registers 32 RW unsigned int R0_USR General purpose register 0 (User Mode) 0 R1_USR General purpose register 1 (User Mode) 1 R2_USR General purpose register 2 (User Mode) 2 R3_USR General purpose register 3 (User Mode) 3 R4_USR General purpose register 4 (User Mode) 4 R5_USR General purpose register 5 (User Mode) 5 R6_USR General purpose register 6 (User Mode) 6 R7_USR General purpose register 7 (User Mode) 7 R8_USR General purpose register 8 (User Mode) 10 R9_USR General purpose register 9 (User Mode) 11 R10_USR General purpose register 10 (User Mode) 12 R11_USR General purpose register 11 (User Mode) 13 R12_USR General purpose register 12 (User Mode) 14 R13_USR Stack pointer (User Mode) 15 R14_USR Link register (User Mode) 16 R15_USR Program counter (User Mode) 9 SPSR_USR Current program status register (User Mode) 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R8_FIQ General purpose register 8 (Fast Interrupt Mode) 18 R9_FIQ General purpose register 9 (Fast Interrupt Mode) 19 R10_FIQ General purpose register 10 (Fast Interrupt Mode) 20 R11_FIQ General purpose register 11 (Fast Interrupt Mode) 21 R12_FIQ General purpose register 12 (Fast Interrupt Mode) 22 R13_FIQ Stack pointer (Fast Interrupt Mode) 23 R14_FIQ Link register (Fast Interrupt Mode) 24 SPSR_FIQ Current program status register (Fast Interrupt Mode) 17 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_SVC Stack pointer (Supervisor Mode) 26 R14_SVC Link register (Supervisor Mode) 27 SPSR_SVC Current program status register (Supervisor Mode) 25 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_ABT Stack pointer (Abort Mode) 29 R14_ABT Link register (Abort Mode) 30 SPSR_ABT Current program status register (Abort Mode) 28 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_IRQ Stack pointer (Interrupt Mode) 32 R14_IRQ Link register (Interrupt Mode) 33 SPSR_IRQ Current program status register (Interrupt Mode) 31 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_UND Stack pointer (Undefined Mode) 35 R14_UND Link register (Undefined Mode) 36 SPSR_UND Current program status register (Undefined Mode) 34 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 CP15 Coprocessor 15 Registers 32 RW unsigned int MIDR Main ID Register ID Regs RO 0x413FC082 15,0,0,0,0 IMPLEMENTOR Implementor 24 8 REV_MAJOR Major revision number of the rnpn revision status 20 4 ARCHITECTURE Architecture Code. 0xF: ARMv7 16 4 PART_NBR Primary Part number. 0xC07: Cortex-A7 MPCore part number 4 12 REV_MINOR Minor revision number of the rnpn revision status 0 4 CTR Cache Type Register ID Regs RO 0x83338003 15,0,0,0,1 CWG Cache Write-Back Granule 24 4 D_MIN_LINE Log2 of the number of words in the smalles cache line of all the data and unified caches under the core control 16 4 L1_POLICY L1 instruction cache policy 14 2 I_MIN_LINE Log2 of the number of words in the smallest cache line of all the instruction caches under the control of the processor 0 4 TCMTR Tightly Coupled Memory (TCM) Type Register ID Regs RO 0x00000000 15,0,0,0,2 TLBTR Translation Lookaside Buffer (TLB) Type Register ID Regs RO 0x00202001 15,0,0,0,3 IL_SIZE Number of Instruction TLB Lockable Entries 16 8 DL_SIZE Number of Data Lockable Entries 8 8 TLB_SIZE Number of Table Entries (00=64, 01=128, 10=256, 11=512) 1 2 U TLB is Unified 0 1 MPIDR Multiprocessor Affinity Register ID Regs RO 15,0,0,0,5 U Uniprocessor System Present 30 1 CLUSTER_ID Value read in CLUSTERID configuration pins. 8 4 CPU_ID ID of the Processor 0 2 REVDIR Revision ID Register ID Regs 0x00000000 RO 15,0,0,0,6 ID_NUMBER Implementation-specific Revision Number 0 32 ID_PFR0 Processor Feature Register 0 ID Regs RO 0x00001231 15,0,1,0,0 STATE_3 ThumbEE instruction set supported 12 4 STATE_2 Jazelle extension interface supported 8 4 STATE_1 Thumb-2 Instruction Set supported (0x3) 4 4 STATE_0 32-bit ARM instruction set supported 0 4 ID_PFR1 Processor Feature Register 1 ID Regs RO 0x00000011 15,0,1,0,1 M_PROFILE M profile programmers model supported 8 4 SECURITY_EXT Security extension architecture v1 supported 4 4 PROG_MODEL Standard ARMv4 programmers model supported 0 4 ID_DFR0 Debug Feature Register 0 ID Regs RO 0x00010400 15,0,1,0,2 M_PROFILE Memory-mapped debug model for M Profile processors supported 20 4 MM_TRACE_MODEL Memory-mapped trace debug model supported 16 4 CP_TRACE_MODEL Coprocessor Trace Model supported 12 4 MM_DEBUG_MODEL Memory-mapped Debug Model supported 8 4 CP_SEC_DBG_MODEL Coprocessor-based secure debug model supported 4 4 CP_DBG_MODEL Coprocessor based core debug model supported 0 4 ID_AFR0 Auxiliary Feature Register 0 ID Regs RO 0x00000000 15,0,1,0,3 ID_MMFR0 Memory Model Features Register 0 ID Regs RO 0x01100103 15,0,1,0,4 FCSE Fast Context Switching Extension (FCSE) supported 24 4 AUX_CTRL_REG Auxiliary Control Registers supported 20 4 TCM Tight Coupled Memory (TCM) supported 16 4 OUTER_SHAREABLE Indicates support for outer shareable attribute 12 4 CACHE_COHERENCE Cache Coherency Maintenance supported 8 4 PMSA Protected Memory System Architecture supported 4 4 VMSA Virtual Memory System Architecture supported 0 4 ID_MMFR1 Memory Model Features Register 1 ID Regs RO 0x20000000 15,0,1,0,5 BTB Branch Target Buffer Supported 28 4 L1_CACHE_TNC L1 data cache test and clean operations supported 24 4 L1_UNIFIED_CACHE L1 unified cache clean/invalidate-all operations supported 20 4 L1_HARVARD_CACHE L1 data operations, harvard architecture, supported 16 4 L1_UNIFIED_CACHE_SW L1 unfied cache maintencance operations by set/way supported 12 4 L1_HARVARD_CACHE_SW L1 Hardvard cache maintenance operations by set/way supported 8 4 L1_UNIFIED_CACHE_MVA L1 unified cache maintenance operations by MVA supported 4 4 L1_HARVARD_CACHE_MVA L1 Harvard cache maintenance operations by MVA supported 0 4 ID_MMFR2 Memory Model Features Register 2 ID Regs RO 0x01230000 15,0,1,0,6 HW_ACCESS Hardware access supported 28 4 WFI_STALL Wait For Interrupt (WFI) stalling supported 24 4 MEM_BARRIER Memory Barrier Operations supported 20 4 UNIFIED_TLB Unified TLB maintenance operations supported 16 4 HARVARD_TLB Harvard TLB maintenance operations supported 12 4 L1_HARVARD_RANGE L1 Hardvard range supported 8 4 L1_HBP L1 Harvard background prefetch operations supported 4 4 L1_HFP L1 Harvard foreground prefetch operations supported 0 4 ID_MMFR3 Memory Model Features Register 3 ID Regs RO 0x00102111 15,0,1,0,7 SS_SUPPORT 16 MB supersections supported 28 4 BP_MAINTAIN Branch Predictor (BP) maintenance operations supported 8 4 CACHE MT_SW Set/Way cache maintenance supported 4 4 CACHE_MT_MVA MVA cache maintenance supported 0 4 ID_ISAR0 Instruction Set Attributes Register 0 ID Regs RO 0x00101111 15,0,2,0,0 DIVIDE_INSTR Integer hardware divide supported 24 4 DBG_INSTR BKPT instruction supported 20 4 CP_INSTRS CP14, CP15 and VFPv4 Coprocessor instructions supported 16 4 CAB_INSTRS Compare-and-branch instructions CBZ and CBNZ supported 12 4 BF_INSTRS Bit-Field instructions BFC, BFI, SBFX and UBFX supported 8 4 BC_INSTRS Bit count instruction CLZ supported 4 4 SWAP_INSTRS Swap instructions SWP and SWPB supported 0 4 ID_ISAR1 Instruction Set Attributes Register 1 ID Regs RO 0x13112111 15,0,2,0,1 JAZELLE_INSTRS Jazelle instructions supported 28 4 INTERW_INSTRS ARM/Thumb interworking instructions supported 24 4 IMM_INSTRS Special immediate-generating instructions supported 20 4 ITE_INSTRS Thumb IT blocks supported 16 4 EXTEND_INSTRS Extend instructions supported 12 4 EXCPT2_INSTRS Exception2-instructions SRS, RFE and CPS supported 8 4 EXCPT1_INSTRS Exception1-instructions LDM(2), LDM(3) and STM(2) supported 4 4 ENDIAN_INSTRS BE8 endian change supported with SETEND 0 4 ID_ISAR2 Instruction Set Attributes Register 2 ID Regs RO 0x21232041 15,0,2,0,2 REV_INSTRS Reversal instructions REV, REV16, REVSH and RBIT supported 28 4 PSR_INSTRS PSR instructions MRS and MSR and exception return data-processing instructions supported 24 4 MULT_INSTRS_AU Long multiply instructions and UMAAL supported 20 4 MULT_INSTRS_AS Signed-Multiply instructions and Q flag in PSRs supported 16 4 MULTIPLY_INSTRS Multiply instructions MUL, MLA and MLS supported 12 4 MAI_INSTRS Multi-access interruptible instructions (MAI) supported 8 4 MEM_HINT_INSTRS Memory hint instructions PLD, PLI and PLDW supported 4 4 LS_INSTRS Load and Store instructions LDRD and STRD supported 0 4 ID_ISAR3 Instruction Set Attributes Register 3 ID Regs RO 0x11112131 15,0,2,0,3 THUMB2_INSTRS Thumb-2 Executable Environment Extension instructions supported 28 4 TRUE_NOP_INSTR True no-operation instruction NOP32 supported 24 4 THUMB_CPY_INSTRS Thumb copy instructions MOV(3) and CPY alias supported 20 4 TBL_BRANCH_INSTRS Thumb table branch instruction TBB and TBH supported 16 4 SYNC_PRIMITIVES Synchronization Orimitive Instructions Supported 12 4 SVC_INSTRS SVC instructions supported 8 4 SIMD_INSTRS All SIMD instructions supported 4 4 SAT_INSTRS Saturate instructions QADD, QDADD, QDSUB, QSUB and Q flag in PSRs supported 0 4 ID_ISAR4 Instruction Set Attributes Register 4 ID Regs RO 0x00011142 15,0,2,0,4 EXCLUSIVE_INSTRS Exclusive instructions CLREX, LDREX, STREX, supported 20 4 BARRIER_INSTRS Barrier instructions DMB, DSB and ISB supported 16 4 SMC_INSTRS Secure Monitor Call (SMC) instructions supported 12 4 WRITE_BACK_INSTRS All defined write-back addressing instructions supported 8 4 WITH_SHIFT_INSTRS Immediate and register control shifted operations supported 4 4 UNPRIVILEGED_INSTRS Unpriviledges load/store instructions LDRT and STRT supported 0 4 CCSIDR Cache Size Identification Register ID Regs RO 15,0,0,1,0 WT Write-Through supported 31 1 WB Write-Back supported for (0x1) L1 data cache, (0x0) L1 instruction cache 30 1 RA Cache read allocation supported 29 1 WA Write allocation supported for: 1: L1 data cache, 0: L1 instruction cache 28 1 NUM_SETS Number of cache sets 13 15 ASSOCIATIVITY Cache associativity. 0x3: 4-way data cache, 0x1: 2-way instruction cache 3 10 LINE_SIZE Number of words per line. 0x1: eight words per line 0 3 CLIDR Cache Level ID Register ID Regs RO 0x09000003 15,0,0,1,1 LoU Level of Unification Uniprocessor 27 3 LoC Level of Coherency 24 3 LoUIS Level of Unifcation Inner Shareable 21 3 CTYPE_7 Type of Cache implemented at Level 7 18 3 CTYPE_6 Type of Cache implemented at Level 6 15 3 CTYPE_5 Type of Cache implemented at Level 5 12 3 CTYPE_4 Type of Cache implemented at Level 4 9 3 CTYPE_3 Type of Cache implemented at Level 3 6 3 CTYPE_2 Type of Cache implemented at Level 2 3 3 CTYPE_1 Type of Cache implemented at Level 1 0 3 AIDR Auxilary ID Register ID Regs RO 0x00000000 15,0,0,1,7 IMPLEMENTOR Silicon Manufacturer ID 24 8 FEATURE Implementation-Defines Field 16 8 MAJOR_REV Major Revision Number 4 4 MINOR_REV Minor Revision Number 0 4 CSSELR Cache Size Selection Register Cache RW 15,0,0,2,0 LEVEL Cache level selected 1 3 InD Selected Cache. 0x1: instruction cache, 0x0: data cache 0 1 SCTLR System Control Register System RW 0x00C50078 15,1,0,0,0 TE Thumb exception enable bit. 0: exceptions including reset are handled in ARM state, 1: exceptions including reset are handled in Thumb state 30 1 AFE Access Flag Enable bit. 0: full access permissions behaviour, 1: simplified access permissions behaviour 29 1 TRE TEX remap enable bit 28 1 NMFI FIQ-exceptions cannot be masked by software 27 1 EE Value the CPSR E bit is set to on an exception. 0: set to 0, little-endian, 1: set to 1, big endian 25 1 RR Replacement strategy for instruction and data caches. 0:random, 1:round-robin 14 1 V Location of exception vectors. 0:normal, 1:high 13 1 I Instruction caching at any available cache level enabled 12 1 Z Branch Predictions enabled 11 1 SW SWP and SWPB Instructions enabled 11 1 C Data caching enabled 2 1 A Strict alignment fault checking enabled 1 1 M MMU enabled 0 1 ACTLR Auxiliary Control Register System RW 0x00000002 15,1,0,0,1 PARITY_ON Parity Checking Enabled 9 1 ALLOC_1W Enable allocation in one cache way only 8 1 EXCL Exclusive Cache Bit 7 1 SMP Coherency enabled 6 1 WFLOZ Write Full line of zeros mode enabled 3 2 L1_PREFETCH L1 Prefetch enabled 2 1 L2_PREFETCH L2 Prefetch enabled 1 1 FW Cache and TLB maintenance broadcasts 0 1 CPACR Coprocessor Access Control Register System RW 0x00000000 15,1,0,0,2 ASEDIS Disable Advanced SIMD Extension Functionality 31 1 D32DIS Disable use of D16-D31 of the VFP Register File 30 1 CP11 Access Permissions for Coprocessor 11: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 22 2 CP10 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 20 2 CP9 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 18 2 CP8 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 16 2 CP7 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 14 2 CP6 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 12 2 CP5 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 10 2 CP4 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 8 2 CP3 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 6 2 CP2 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 4 2 CP1 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 2 2 CP0 Access Permissions for Coprocessor 10: 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 0 2 SCR Secure Configuration Register Security Extensions RW 0x00000000 15,1,1,0,0 AW Enable Modification of the A bit in the CPSR in the non-secure state 5 1 FW Enable Modification of the F bit in the CPSR in the non-secure state 4 1 EA Branch to Monitor Mode on an External Abort Exception 3 1 FIQ Branch to Monitor Mode on an FIQ Exception 2 1 IRQ Branch to Montor Mode on an IRQ Exception 1 1 NS Enable Non-Secure Operation Enable 0 1 SDER Secure Debug Enable Register Security Extensions RW 0x00000000 15,1,1,0,1 SUNIDEN Secure user non-invasive debug enable 1 1 SUIDEN Secure user invasive debug enable 0 1 NSACR Non-secure Access Control Register Security Extensions RW 0x00000000 15,1,1,0,2 NS_SMP SMP bit of the Auxiliary Control Register is writable in Non-secure state 18 1 TL Lockable table entries can be allocated in non-secure state 17 1 PLE PLE Registers can be accessed in both Secure and Nonsecure state (1) , or are Disabled (0) 16 1 NSASEDIS Disable non-secure Advanced SIMD Extension Functionality 15 1 NSD32DIS Disable non-secure use of D16-D31 of the VFP Register File 4 1 CP11 Access Permission for Coprocessor 11 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 11 1 CP10 Access Permission for Coprocessor 10 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 10 1 CP9 Access Permission for Coprocessor 9 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 9 1 CP8 Access Permission for Coprocessor 8 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 8 1 CP7 Access Permission for Coprocessor 7 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 7 1 CP6 Access Permission for Coprocessor 6 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 6 1 CP5 Access Permission for Coprocessor 5 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 5 1 CP4 Access Permission for Coprocessor 4 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 4 1 CP3 Access Permission for Coprocessor 3 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 3 1 CP2 Access Permission for Coprocessor 2 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 2 1 CP1 Access Permission for Coprocessor 1 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 1 1 CP0 Access Permission for Coprocessor 0 in the Non-Secure State: 0: Secure Access only, 1: Secure and Non-Secure Access 0 1 VCR Virtualization Control Register Misc RW 0x00000000 15,1,1,0,3 AMO Asynchroneous Abort Mask Override 8 1 IMO IRQ Mask Override 7 1 IFO FIQ Mask Override 6 1 TTBR0 Translation Table Base Register 0 VMC RW 15,2,0,0,0 TTB_0 Physical Address of the first-Level Translation Table 14 18 RGN Outer Cacheable attributes for translation table walking 3 2 P Read-As-Zero and ignore writes. 2 1 S Translation table walk to 0: non-shared memory, 1: shared memory 1 1 C Translation table walk is inner (0) or non-inner (1) cacheable 0 1 TTBR1 Translation Table Base Register 1 VMC RW 15,2,0,0,1 TTB_1 Physical Address of the First Level Translation Table 14 18 RGN Outer Cacheable attributes for translation table walking 3 2 P Read-As-Zero and ignore writes. 2 1 S Translation table walk to 0: non-shared memory, 1: shared memory 1 1 C Translation table walk is inner (0) or non-inner (1) cacheable 0 1 TTBCR Translation Table Base Control Register VMC RW 0x00000000 15,2,0,0,2 PD1 Translation table walk on TLB miss disable when using TTBR1 5 1 PD0 Translation table walk on TLB miss disable when using TTBR0 4 1 N Boundary Size of TTBR0 0 3 DACR Domain Access Control Register VMC RW 15,3,0,0,0 D0 Domain 0 access permissions. 00: no access, 01: client access, 11: manager access 0 2 D1 Domain 1 access permissions. 00: no access, 01: client access, 11: manager access 2 2 D2 Domain 2 access permissions. 00: no access, 01: client access, 11: manager access 4 2 D3 Domain 3 access permissions. 00: no access, 01: client access, 11: manager access 6 2 D4 Domain 4 access permissions. 00: no access, 01: client access, 11: manager access 8 2 D5 Domain 5 access permissions. 00: no access, 01: client access, 11: manager access 10 2 D6 Domain 6 access permissions. 00: no access, 01: client access, 11: manager access 12 2 D7 Domain 7 access permissions. 00: no access, 01: client access, 11: manager access 14 2 D8 Domain 8 access permissions. 00: no access, 01: client access, 11: manager access 16 2 D9 Domain 9 access permissions. 00: no access, 01: client access, 11: manager access 18 2 D10 Domain 10 access permissions. 00: no access, 01: client access, 11: manager access 20 2 D11 Domain 11 access permissions. 00: no access, 01: client access, 11: manager access 22 2 D12 Domain 12 access permissions. 00: no access, 01: client access, 11: manager access 24 2 D13 Domain 13 access permissions. 00: no access, 01: client access, 11: manager access 26 2 D14 Domain 14 access permissions. 00: no access, 01: client access, 11: manager access 28 2 D15 Domain 15 access permissions. 00: no access, 01: client access, 11: manager access 30 2 DFSR Data Fault Status Register Fault Handling RW 15,5,0,0,0 ExT External Abort Qualifier. 0: AXI Decode error, 1: AXI Slave error 12 1 RW Indicated weather a read (0) or write (1) access caused an abort 11 1 FS[4] Bit 4 of the Fault Status Field 10 1 DOMAIN The domain (D15-D0) of the fault address 5 4 FAULT_STATUS Type of Fault Generated 0 4 IFSR Instruction Fault Status Register Fault Handling RW 15,5,0,0,1 ExT External Abort Qualifier. 0: AXI Decode error, 1: AXI Slave error 12 1 FS[4] Bit 4 of the Fault Status Field 10 1 FAULT_STATUS Type of Fault Generated 0 4 ADFSR Auxilary Data Fault Status Register Fault Handling RW 15,5,1,0,0 AIFSR Auxilary Instruction Fault Status Register Fault Handling RW 0x00000000 15,5,1,0,1 DFAR Data Fault Address Register Fault Handling RW 15,6,0,0,0 IFAR Instruction Fault Address Register Fault Handling RW 15,6,0,0,2 NOP None Misc WO 15,7,0,0,4 ICIALLUIS Instruction cache invalidate all to Point of Unifcation (POU) Inner Shareable Cache WO 15,7,5,0,0 BPIALLIS Branch predictor invalidate all Inner Shareable Cache WO 15,7,5,0,6 PAR Physical Address Register Address Translation RW 0x00000000 15,7,4,0,0 PA Physical address after successfull translation 12 20 NS Translation Table Non-Secure Bit 9 1 SH Physical memory is shareable 7 1 INNER Signals region inner attributes 4 3 OUTER Signals region outer attributes for normal memory type 2 2 SS Indicates if the translation is a supersection 1 1 F Result of translation. 1: successfull 0 1 ICIALLU Invalidate all instruction caches to Point of Unification (POU) Cache WO 15,7,5,0,0 ICIMVAU Invalidate instruction cache line by MVA to Point of Unification (PoU) Cache WO 15,7,5,0,1 ADDR Address to invalidate or clean 12 20 ISB Instruction Synchronization Barrier Misc WO 15,7,5,0,4 BPIALL Invalidate entire branch predictor array Cache WO 15,7,5,0,6 DCIMVAC Invalidate data cache line to Point of Coherency by MVA Cache WO 15,7,6,0,1 ADDR Address to invalidate or clean 12 20 DCISW Invalidate data cache line by Set/Way Cache WO 15,7,6,0,2 WAY Cache way to invalidate or clean 29 3 SET Cache set to invalidate or clean 6 9 ATS1CPR Stage 1 current state EL1 read Address Translation WO 15,7,8,0,0 ATS1CPW State 1 current state EL1 write Address Translation WO 15,7,8,0,1 ATS1CUR Stage 1 current state unpriviledged read Address Translation WO 15,7,8,0,2 ATS1CUW Stage 1 current state unpriviledged write Address Translation WO 15,7,8,0,3 ATS12NSOPR Stages 1 and 2 Non-secure EL1 read Address Translation WO 15,7,8,0,4 ATS12NSOPW Stages 1 and 2 non-secure EL1 write Address Translation WO 15,7,8,0,5 ATS12NSOUR Stages 1 and 2 non-secure unpriviledged read Address Translation WO 15,7,8,0,6 ATS12NSOUW Stages 1 and 2 non-secure unpriviledged write Address Translation WO 15,7,8,0,7 DCCMVAC Clean Data cache line to Point of Coherency by MVA Cache WO 15,7,10,0,1 ADDR Address to invalidate or clean 12 20 DCCSW Clean data cache line by Set/Way Cache WO 15,7,10,0,2 WAY Cache way to invalidate or clean 29 3 SET Cache set to invalidate or clean 6 9 DSB Data Synchronization Barrier Cache WO 15,7,10,0,4 DMB Data Memory Barrier Cache WO 15,7,10,0,5 DCCMVAU Clean data cache line by MVA to Point of Unification (PoU) Cache WO 15,7,11,0,1 ADDR Address to invalidate or clean 12 20 DCCIMVAC Clean and invalidate data cache line by MVA to Point of Unifciation (PoU) Cache WO 15,7,14,0,1 ADDR Address to invalidate or clean 12 20 DCCISW Clean and invalidate data cache line by Set/Way Cache WO 15,7,14,0,2 WAY Cache way to invalidate or clean 29 3 SET Cache set to invalidate or clean 6 9 ITLBIALLIS Invalidate Instruction TLB TLB WO 15,8,3,0,0 ITLBIMVAIS Invalidate Instruction TLB by MVA TLB WO 15,8,3,0,1 ITLBIASIDIS Invalidate Instruction TLB by ASID TLB WO 15,8,3,0,2 DTLBIMVAIS Invalidate Data TLB TLB WO 15,8,3,0,3 TLBIALL Invalidate unified TLB TLB WO 15,8,7,0,0 TLBIMVA Invalidate unified TLB by MVA TLB WO 15,8,7,0,1 TLBIASID Invalidate TLB entries on ASID match TLB WO 15,8,7,0,2 TLBIMVAA Invalidate TLB entries on ASID match TLB WO 15,8,7,0,3 PMCR Performance Monitor Control Register PMU RW 0x41093000 15,9,12,0,0 IMP Implementor Code. 0x41: arm 24 8 ID_CODE Identification Code 16 8 N Number of Counters Implemented 11 4 DP Disable Cycle Counter PMCCNTR in prohibited regions 5 1 X Export of the events from the event bus to an external monitoring block enabled 4 1 D Cycle Count Divider. 0: count every clock cycle when enabled. 1: count every 64th clock cycle when enabled. 3 1 C Cycle Counter Reset 2 1 P Reset all Performance Counters, including PMCCNTR 1 1 E Enable All Counters including PMCCNTR 0 1 PMNCNTENSET Count Enable Set Register PMU 0x00000000 RW 15,9,12,0,1 C Enable Cycle Counter 31 1 P0 Enable Counter 0 0 1 P1 Enable Counter 1 1 1 P2 Enable Counter 2 2 1 P3 Enable Counter 3 3 1 PMNCNTENCLR Count Enable Clear Register PMU RW 0x00000000 15,9,12,0,2 C Disable Cycle Counter 31 1 P0 Disable Counter 0 0 1 P1 Disable Counter 1 1 1 P2 Disable Counter 2 2 1 P3 Disable Counter 3 3 1 PMSOVSR Overflow Flag Status Register PMU 0x00000000 RW 15,9,12,0,3 C Cycle Counter Overflow Flag 31 1 P0 Counter 0 Overflow Flag 0 1 P1 Counter 1 Overflow Flag 1 1 P2 Counter 2 Overflow Flag 2 1 P3 Counter 3 Overflow Flag 3 1 PMSWINC Software Increment Register PMU WO 15,9,12,0,4 P0 Increment Counter 0 0 1 P1 Increment Counter 1 1 1 P2 Increment Counter 2 2 1 P3 Increment Counter 3 3 1 PMSELR Performance Counter Selection Register PMU RW 0x00000000 15,9,12,0,5 SEL Counter Selected Register 0 5 PMCCNTR Cycle Count Register PMU RW 0x00000000 15,9,13,0,0 PMXEVTYPER Event Type Select Register PMU RW 15,9,13,0,1 SEL Selected Event Specificator 0 8 PMEVCNTR Performance Montor Event Count Register PMU RW 15,9,13,0,2 PMUSERENR User Enable Register PMU RW 0x00000000 15,9,14,0,0 EN User Mode Enabled 0 1 PMINTENSET Interrupt Enable Set Register PMU 0x00000000 RW 15,9,14,0,1 C PMCCNTR overflow interrupt request enable. 31 1 P0 PMCNT0 overflow interrupt request enable. 0 1 P1 PMCNT1 overflow interrupt request enable. 1 1 P2 PMCNT2 overflow interrupt request enable. 2 1 P3 PMCNT3 overflow interrupt request enable. 3 1 PMINTENCLR Interrupt Enable Clear Register PMU 0x00000000 RW 15,9,14,0,2 C PMCCNTR overflow interrupt clear bit 31 1 P0 Clear interrupt request on PMCNT1 overflow 0 1 P1 Clear interrupt request on PMCNT1 overflow 1 1 P2 Clear interrupt request on PMCNT1 overflow 2 1 P3 Clear interrupt request on PMCNT0 overflow 3 1 TLB_LOCKDOWN TLB Lockdown Register TLB RW 0x00000000 15,10,0,0,0 VICTIM Specifies the entry where the next hardware translation table walk can place a TLB entry 28 2 P Determines if TLB entries allocated by subsequent translation table walks are not invalidated by the Invalidate TLB unlocked entries operation 0 1 PRRR Primary Memory Region Remap Register VMC RW 0x00098AA4 15,10,2,0,0 NS1 Mapping of S=1 attribute for normal memory 19 1 NS0 Mapping of S=1 attribute for normal memory 18 1 DS1 Mapping of S=1 attribute for device memory 17 1 DS0 Mapping of S=0 attribute for device memory 16 1 TR7 Primary TEX mapping for memory attributes 7 14 2 TR6 Primary TEX mapping for memory attributes 6 12 2 TR5 Primary TEX mapping for memory attributes 5 10 2 TR4 Primary TEX mapping for memory attributes 4 8 2 TR3 Primary TEX mapping for memory attributes 3 6 2 TR2 Primary TEX mapping for memory attributes 2 4 2 TR1 Primary TEX mapping for memory attributes 1 2 2 TR0 Primary TEX mapping for memory attributes 0 0 2 NMRR Normal Memory Remap Register VMC RW 0x44E048E0 15,10,2,0,1 OR3 Outer Cacheable property mapping for memory attributes 3 22 2 OR2 Outer Cacheable property mapping for memory attributes 2 20 2 OR1 Outer Cacheable property mapping for memory attributes 1 18 2 OR0 Outer Cacheable property mapping for memory attributes 0 16 2 IR7 Inner Cacheable property mapping for memory attributes 7 14 2 IR6 Inner Cacheable property mapping for memory attributes 6 12 2 IR5 Inner Cacheable property mapping for memory attributes 5 10 2 IR4 Inner Cacheable property mapping for memory attributes 4 8 2 IR3 Inner Cacheable property mapping for memory attributes 3 6 2 IR2 Inner Cacheable property mapping for memory attributes 2 4 2 IR1 Inner Cacheable property mapping for memory attributes 1 2 2 IR0 Inner Cacheable property mapping for memory attributes 0 0 2 PLEIDR Preload Engine (PLE) Identification and Status Register Preload Engine RO 15,11,0,0,0 PLE FIFO size PLE Fifo Size (00000: PLE not present, 00100: size 4, 01000: size 8, 10000: size 16) 0 1 PLE_PRESENT Preload Engine present 1 1 PLEASR Preload Engine (PLE) Activity Status Register 0 Preload Engine RO 15,11,0,0,2 R Preload Engine is handling a PLE request 0 1 PLEFSR Preload Engine (PLE) FIFO Status Register 0 Preload Engine RO 15,11,0,0,4 AVAIL_ENTRIES Number of Available Entries in the PLE FIFO 4 5 PLEUAR Preload Engine (PLE) User Accessibility Register Preload Engine RW 15,11,1,0,0 U User Mode Can Execute PLE Ops 0 1 PLECR Preload Engine (PLE) Control Register Preload Engine RW 15,11,4,0,0 BSZM Maximum Block Size per PLE transfere 16 14 BNM Maximum Block Number per PLE transfere 8 8 PLE_WAIT_STATES Restrict PLD issue requests to every 256 cycle 0 8 VBAR Vector Base Address Register Security Extensions RW 0x00000000 15,12,0,0,0 VECT_BASE_ADDR The base address of normal exception vectors 5 27 MVBAR Monitor Vector Base Address Register 0x00000000 Security Extensions RW 15,12,0,0,1 MONITOR_VBA The base address of the exception vectors for exceptions that are handled in monitor mode 5 27 ISR Interrupt Status Register Security Extensions 0x00000000 RO 15,12,1,0,0 A External abort pending 8 1 I Interrupt pending 7 1 F Fast interrupt pending 6 1 VIR Virtualization Interrupt Register Security Extensions 0x00000000 RW 15,12,1,0,1 VA Virtual Abort Bit 8 1 VI Virtual IRQ Bit 7 1 VF Virtual FIQ Bit 6 1 FCSEIDR Fast Context Switching Extension Register ID Regs RW 0x00000000 15,13,0,0,0 FCSE_PID Fast Context Switch Extension ID 25 7 CONTEXTIDR Context ID Register ID Regs RW 15,13,0,0,1 PROCID Current Process Identifier 8 24 ASID Address Space Identifier (ASID) of the Current Process 0 8 TPIDRURW Software Thread ID Register 1 ID Regs RW 15,13,0,0,2 TPIDRURO Software Thread ID Register 2 ID Regs RO 15,13,0,0,3 TPIDRPRW Software Thread ID Register 3 ID Regs RW 15,13,0,0,4 f POWER Power Control Register System RW 15,15,0,0,0 MAX_CLK_LATENCY Samples the value present on the MAXCLKLATENCY pins on exit from reset 8 3 EDCG Dynamic Clock Gating Enabled 0 1 NEON_BUSY 0x00000000 NEON Busy Register System RW 15,15,1,0,0 NEON_BUSY Neon instruction present within the NEON pipeline 0 1 CBAR Configuration Base Address Register System RO 0x00000000 15,15,0,4,0 PERIPH_BASE Peripheral Base Address 0 32 TLB_LD_READ Select Lockdown TLB Entry for Read System WO 15,15,4,5,2 INDEX Main TLB index 0 2 TLB_LD_WRITE Select Lockdown TLB Entry for Write System WO 15,15,4,5,4 INDEX Main TLB index 0 2 MTLBVAR Main TLB VA Register TLB WO 15,15,5,5,2 VPN Virtual Page Number 12 20 NS Non-Secure Bit 10 1 PROCESS Memory Space Identifer 0 10 MTLBPAR Main TLB PA Register TLB WO 15,15,6,5,2 PPN Physical Page Number 12 20 REGION_SZ Region Size 6 2 ACCESS_PERM Access Permissions 1 4 VALID The Entry is Locked and Valid 0 1 MTLBAR Main TLB Attribute Register TLB WO 15,15,7,5,2 NON-SECURE Non-Secure Description Attribute 11 1 DOMAIN_NBR TLB-entry domain number 7 4 EXEC_NEVER Execute Never Attribute 6 1 TEX Region Type Encoding 1 3 3 CB Region Type Encoding 2 1 2 SHARED Shared Attribute 0 1