CA17_D16 Cortex-A17 (D16) State Current CPU State 1 Core (Now) Current State CPU Registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 74 R9 General purpose register 9 75 R10 General purpose register 10 76 R11 General purpose register 11 77 R12 General purpose register 12 78 R13 SP R13 (SP) Stack pointer (SP) 79 R14 LR R14 (LR) Link register (LR) 80 R15 PC R15 (PC) Program counter (PC) 9 CPSR Current program status register 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 FPU Floating Point Registers 32 RW float S0 Floating point register 0 40 S1 Floating point register 1 41 S2 Floating point register 2 42 S3 Floating point register 3 43 S4 Floating point register 4 44 S5 Floating point register 5 45 S6 Floating point register 6 46 S7 Floating point register 7 47 S8 Floating point register 8 48 S9 Floating point register 9 49 S10 Floating point register 10 50 S11 Floating point register 11 51 S12 Floating point register 12 52 S13 Floating point register 13 53 S14 Floating point register 14 54 S15 Floating point register 15 55 S16 Floating point register 16 56 S17 Floating point register 17 57 S18 Floating point register 18 58 S19 Floating point register 19 59 S20 Floating point register 20 60 S21 Floating point register 21 61 S22 Floating point register 22 62 S23 Floating point register 23 63 S24 Floating point register 24 64 S25 Floating point register 25 65 S26 Floating point register 26 66 S27 Floating point register 27 67 S28 Floating point register 28 68 S29 Floating point register 29 69 S30 Floating point register 30 70 S31 Floating point register 31 71 FPSID Floating point system information register RO 0x410330D0 unsigned int 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 0x0 unsigned int 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 AHP Alternative half-precision control bit 26 1 QC Cumulative saturation exception bit 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 0x0 unsigned int 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 0x10110222 unsigned int 72 RB thirty-two 64-bit registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 0x11111111 unsigned int 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 FMAC Fused multiply accumulate operations supported 28 4 FPU (Double) Floating Point Registers (double-precision) 64 RW double D0 Floating point register 0 40 41 D1 Floating point register 1 42 43 D2 Floating point register 2 44 45 D3 Floating point register 3 46 47 D4 Floating point register 4 48 49 D5 Floating point register 5 50 51 D6 Floating point register 6 52 53 D7 Floating point register 7 54 55 D8 Floating point register 8 56 57 D9 Floating point register 9 58 59 D10 Floating point register 10 60 61 D11 Floating point register 11 62 63 D12 Floating point register 12 64 65 D13 Floating point register 13 66 67 D14 Floating point register 14 68 69 D15 Floating point register 15 70 71 FPSID Floating point system information register RO 32 0x41023140 37 Implementer Implementer ID 24 8 SW Software emulation support flag 23 1 Architecture Architecture version 16 7 PartNumber Part number 8 8 Variant Variant ID 4 4 Revision Revision number 0 4 FPSCR Floating point status and control register RW 32 0x0 38 IOC Invalid operation cumulative exception flag 0 1 DZC Division by zero cumulative exception flag 1 1 OFC Overflow cumulative exception flag 2 1 UFC Underflow cumulative exception flag 3 1 IXC Inexact cumulative exception flag 4 1 IDC Input denormal cumulative exception flag 7 1 IOE Invalid operation exception enable bit 8 1 DZE Division by zero exception enable bit 9 1 OFE Overflow exception enable bit 10 1 UFE Underflow exception enable bit 11 1 IXE Inexact exception enable bit 12 1 IDE Input Subnormal exception enable bit 15 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 QC Saturation cumulative flag 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 N Set if comparison produces a less than result 31 1 FPEXC Floating point exception register RW 32 0x0 39 DEX Undefined instruction exception flag 29 1 EN VFP enable bit 30 1 MVFR0 Media and VFP feature register 0 RO 32 0x10110221 72 RB Sixteen 64-bir registers supported 0 4 SP Single-precision operations supported 4 4 DP Double-precision operations supported 8 4 TE VFP exception trapping not supported 12 4 D VFP divide operation supported 16 4 SR VFP square root operation supported 20 4 SV VFP short vectors not supported 24 4 RM All VFP rounding modes supported 28 4 MVFR1 Media and VFP feature register 1 RO 32 0x00000011 73 FZ VFP denormal airthmetic operations supported 0 4 DN VFP NaN value propagation supported 4 4 LS Advanded SIMD load/store instructions not supported 8 4 I Advanced SIMD integer operations not supported 12 4 SPFP Advanced SIMD single-precision operations not supported 16 4 HPFP Advanced SIMD half-precision operations not supported 20 4 VFP HPFP VFP half-precision operations supported 24 4 Core (All) All CPU Registers 32 RW unsigned int R0_USR General purpose register 0 (User Mode) 0 R1_USR General purpose register 1 (User Mode) 1 R2_USR General purpose register 2 (User Mode) 2 R3_USR General purpose register 3 (User Mode) 3 R4_USR General purpose register 4 (User Mode) 4 R5_USR General purpose register 5 (User Mode) 5 R6_USR General purpose register 6 (User Mode) 6 R7_USR General purpose register 7 (User Mode) 7 R8_USR General purpose register 8 (User Mode) 10 R9_USR General purpose register 9 (User Mode) 11 R10_USR General purpose register 10 (User Mode) 12 R11_USR General purpose register 11 (User Mode) 13 R12_USR General purpose register 12 (User Mode) 14 R13_USR Stack pointer (User Mode) 15 R14_USR Link register (User Mode) 16 R15_USR Program counter (User Mode) 9 SPSR_USR Current program status register (User Mode) 8 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R8_FIQ General purpose register 8 (Fast Interrupt Mode) 18 R9_FIQ General purpose register 9 (Fast Interrupt Mode) 19 R10_FIQ General purpose register 10 (Fast Interrupt Mode) 20 R11_FIQ General purpose register 11 (Fast Interrupt Mode) 21 R12_FIQ General purpose register 12 (Fast Interrupt Mode) 22 R13_FIQ Stack pointer (Fast Interrupt Mode) 23 R14_FIQ Link register (Fast Interrupt Mode) 24 SPSR_FIQ Current program status register (Fast Interrupt Mode) 17 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_SVC Stack pointer (Supervisor Mode) 26 R14_SVC Link register (Supervisor Mode) 27 SPSR_SVC Current program status register (Supervisor Mode) 25 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_ABT Stack pointer (Abort Mode) 29 R14_ABT Link register (Abort Mode) 30 SPSR_ABT Current program status register (Abort Mode) 28 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_IRQ Stack pointer (Interrupt Mode) 32 R14_IRQ Link register (Interrupt Mode) 33 SPSR_IRQ Current program status register (Interrupt Mode) 31 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 R13_UND Stack pointer (Undefined Mode) 35 R14_UND Link register (Undefined Mode) 36 SPSR_UND Current program status register (Undefined Mode) 34 M Mode bits 0 5 T Thumb state 5 1 F SVC disable 6 1 I IRQ disable 7 1 A Asynchroneous abort disable 8 1 E Data endianess 9 1 IC/IT Low Interruptible-continuable instruction low bits 10 6 IC/IT High Interruptible-continuable instruction high bits 25 2 GE Greater-than-or-equal bits 16 4 J Java state 24 1 Q Sticky overflow flag 27 1 V Overflow flag 28 1 C Carry flag 29 1 Z Zero flag 30 1 N Negative flag 31 1 CP15 Coprocessor 15 Registers 32 RW unsigned int MIDR Main ID Register ID Regs RO 0x411FC0E0 15,0,0,0,0 IMPLEMENTOR Implementor 24 8 REV_MAJOR Major revision number of the rnpn revision status 20 4 ARCHITECTURE Architecture Code. 0xF: ARMv7 16 4 PART_NBR Primary Part number. 0xC07: Cortex-A7 MPCore part number 4 12 REV_MINOR Minor revision number of the rnpn revision status 0 4 CTR Cache Type Register ID Regs RO 0x84448003 15,0,0,0,1 FORMAT CTR Format 29 3 CWG Cache Write-Back Granule 24 4 ERG Exclusive Reservation Granule 20 4 D_MIN_LINE Log2 of the number of words in the smalles cache line of all the data and unified caches under the core control 16 4 L1_POLICY L1 instruction cache policy 14 2 I_MIN_LINE Log2 of the number of words in the smallest cache line of all the instruction caches under the control of the processor 0 4 TCMTR Tightly Coupled Memory (TCM) Type Register RO ID Register 0x00000000 15,0,0,0,2 TLBTR Translation Lookaside Buffer (TLB) Type Register RO ID Regs 0x00000000 15,0,0,0,3 nU Unified TLB NOT present 0 1 MPIDR Multiprocessor Affinity Register ID Regs RO 15,0,0,0,5 U Uniprocessor System Present 30 1 MT Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach 24 1 CLUSTER_ID Value read in CLUSTERID configuration pins. 8 4 CPU_ID ID of the Processor 0 2 REVIDR Revision ID register ID Regs RO 0x00000000 15,0,0,0,0 ID_PFR0 Processor Feature Register 0 ID Regs RO 0x00001131 15,0,1,0,0 STATE_3 ThumbEE instruction set supported 12 4 STATE_2 Jazelle extension interface supported 8 4 STATE_1 Thumb-2 Instruction Set supported (0x3) 4 4 STATE_0 32-bit ARM instruction set supported 0 4 ID_PFR1 Processor Feature Register 1 ID Regs RO 0x00011011 15,0,1,0,1 GENERIC_TIMER Gerneric Timer supported 16 4 VIRTUAL_EXT Virtualization Extensions supported 12 4 M_PROFILE M profile programmers model supported 8 4 SECURITY_EXT Security extension architecture v1 supported 4 4 PROG_MODEL Standard ARMv4 programmers model supported 0 4 ID_DFR0 Debug Feature Register 0 ID Regs RO 0x02010555 15,0,1,0,2 PERF_MM Performance Monitor Model ID 24 4 M_PROFILE Memory-mapped debug model for M Profile processors supported 20 4 MM_TRACE_MODEL Memory-mapped trace debug model supported 16 4 CP_TRACE_MODEL Coprocessor Trace Model supported 12 4 MM_DEBUG_MODEL Memory-mapped Debug Model supported 8 4 CP_SEC_DBG_MODEL Coprocessor-based secure debug model supported 4 4 CP_DBG_MODEL Coprocessor based core debug model supported 0 4 ID_AFR0 Auxiliary Feature Register 0 ID Regs RO 0x00000000 15,0,1,0,3 ID_MMFR0 Memory Model Features Register 0 ID Regs RO 0x10101105 15,0,1,0,4 IN_SHARE Innermost shareability domain supported 28 4 FCSE Fast Context Switching Extension (FCSE) supported 24 4 AUX_CTRL_REG Auxiliary Control Registers supported 20 4 TCM Tight Coupled Memory (TCM) supported 16 4 SHRABILITY_LEVELS Number of Shareability Levels Implemented (0x1: two levels implemented) 12 4 OUTER_SHRABILITY Indicates the outermost Shareability Level Implemented (0x1: Processor supports hardware coherency) 8 4 PMSA Protected Memory System Architecture supported 4 4 VMSA Virtual Memory System Architecture supported 0 4 ID_MMFR1 Memory Model Features Register 1 ID Regs RO 0x40000000 15,0,1,0,5 BRANCH_PREDICT Branch Predictor Management Requirements 28 4 L1_CACHE_TNC L1 data cache test and clean operations supported 24 4 L1_UNIFIED_CACHE L1 unified cache clean/invalidate-all operations supported 20 4 L1_HARVARD_CACHE L1 data cache clean/invalidate-all operations supported 16 4 L1_UNIFIED_CACHE_SW L1 unfied cache maintencance operations by set/way supported 12 4 L1_HARVARD_CACHE_SW L1 Hardvard cache maintenance operations by set/way supported 8 4 L1_UNIFIED_CACHE_VA L1 unified cache maintenance operations by VA supported 4 4 L1_HARVARD_CACHE_VA L1 Harvard cache maintenance operations by VA supported 0 4 ID_MMFR2 Memory Model Features Register 2 ID Regs RO 0x01240000 15,0,1,0,6 HW_ACCESS Hardware access supported 28 4 WFI_STALL Wait For Interrupt (WFI) stalling supported 24 4 MEM_BARRIER Memory Barrier Operations supported 20 4 UNIFIED_TLB Unified TLB maintenance operations supported 16 4 HARVARD_TLB Harvard TLB maintenance operations supported 12 4 L1_HARVARD_RANGE L1 Hardvard range supported 8 4 L1_HBP L1 Harvard background prefetch operations supported 4 4 L1_HFP L1 Harvard foreground prefetch operations supported 0 4 ID_MMFR3 Memory Model Features Register 3 ID Regs RO 0x02102211 15,0,1,0,7 SS_SUPPORT 16 MB supersections supported 28 4 PHYS_MEM_SIZE Size of physical memory supported by processor caches 24 4 COHRERENT_WALK Coherent walk supported. 0x1: updates to translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks 20 4 MAINTENANCE_BC Cache, TLB and Branch prediction operations broadcast supported 12 4 BP_MAINTAIN Branch Predictor (BP) maintenance operations supported 8 4 CACHE MAINTENANCE_SW Set/Way cache maintenance supported 4 4 CACHE_MAINTENANCE_MVA MVA cache maintenance supported 0 4 ID_ISAR0 Instruction Set Attributes Register 0 ID Regs RO 0x02101110 15,0,2,0,0 DIVIDE_INSTR Integer hardware divide supported 24 4 DBG_INSTR BKPT instruction supported 20 4 CP_INSTRS CP14, CP15 and VFPv4 Coprocessor instructions supported 16 4 CAB_INSTRS Compare-and-branch instructions CBZ and CBNZ supported 12 4 BF_INSTRS Bit-Field instructions BFC, BFI, SBFX and UBFX supported 8 4 BC_INSTRS Bit count instruction CLZ supported 4 4 SWAP_INSTRS Swap instructions SWP and SWPB supported 0 4 ID_ISAR1 Instruction Set Attributes Register 1 ID Regs RO 0x13112111 15,0,2,0,1 JAZELLE_INSTRS Jazelle instructions supported 28 4 INTERW_INSTRS ARM/Thumb interworking instructions supported 24 4 IMM_INSTRS Special immediate-generating instructions supported 20 4 ITE_INSTRS Thumb IT blocks supported 16 4 EXTEND_INSTRS Extend instructions supported 12 4 EXCPT2_INSTRS Exception2-instructions SRS, RFE and CPS supported 8 4 EXCPT1_INSTRS Exception1-instructions LDM(2), LDM(3) and STM(2) supported 4 4 ENDIAN_INSTRS BE8 endian change supported with SETEND 0 4 ID_ISAR2 Instruction Set Attributes Register 2 ID Regs RO 0x21232041 15,0,2,0,2 REV_INSTRS Reversal instructions REV, REV16, REVSH and RBIT supported 28 4 PSR_INSTRS PSR instructions MRS and MSR and exception return data-processing instructions supported 24 4 MULT_U_INSTRS Long multiply instructions and UMAAL supported 20 4 MULT_S_INSTRS Signed-Multiply instructions and Q flag in PSRs supported 16 4 MULT_INSTRS Multiply instructions MUL, MLA and MLS supported 12 4 MAI_INSTRS Multi-access interruptible instructions (MAI) supported 8 4 MEM_HINT_INSTRS Memory hint instructions PLD, PLI and PLDW supported 4 4 LS_INSTRS Load and Store instructions LDRD and STRD supported 0 4 ID_ISAR3 Instruction Set Attributes Register 3 ID Regs RO 0x11112131 15,0,2,0,3 THUMB2_INSTRS Thumb-2 Executable Environment Extension instructions supported 28 4 TRUE_NOP_INSTR True no-operation instruction NOP32 supported 24 4 THUMB_CPY_INSTRS Thumb copy instructions MOV(3) and CPY alias supported 20 4 TBL_BRANCH_INSTRS Thumb table branch instruction TBB and TBH supported 16 4 SYNC_PRIM_INSTRS Synchronization Primitive Instructions Supported 12 4 SVC_INSTRS SVC instructions supported 8 4 SIMD_INSTRS All SIMD instructions supported 4 4 SAT_INSTRS Saturate instructions QADD, QDADD, QDSUB, QSUB and Q flag in PSRs supported 0 4 ID_ISAR4 Instruction Set Attributes Register 4 ID Regs RO 0x00011142 15,0,2,0,4 SWP_FRAC Memory System Locking the bus for SWP or SWPB instructions Supported 28 4 PSR_M_INSTRS Indicates together with ID_ISAR3 which Synchronization Primitive instructions are supported 25 4 SYNC_PRIMITIVE_INSTRS Synchronization primitive instructions supported 20 4 BARRIER_INSTRS Barrier instructions DMB, DSB and ISB supported 16 4 SMC_INSTRS Secure Monitor Call (SMC) instructions supported 12 4 WRITE_BACK_INSTRS All defined write-back addressing modes supported 8 4 WITH_SHIFT_INSTRS Immediate and register control shifted operations supported 4 4 UNPRIVILEGED_INSTRS Unpriviledges load/store instructions LDRT and STRT supported 0 4 ID_ISAR5 Instruction Set Attributes Register 5 ID Regs RO 0x00000000 15,0,2,0,5 CCSIDR Cache Size Identification Register ID Regs RO 15,0,0,1,0 WT Write-Through supported 31 1 WB Write-Back supported for (0x1) L1 data cache, (0x0) L1 instruction cache 30 1 RA Cache read allocation supported 29 1 WA Write allocation supported for: 1: L1 data cache, 0: L1 instruction cache 28 1 NUM_SETS Number of cache sets 13 15 ASSOCIATIVITY Cache associativity. 0x3: 4-way data cache, 0x1: 2-way instruction cache 3 10 LINE_SIZE Number of words per line. 0x1: eight words per line 0 3 CLIDR Cache Level ID Register ID Regs RO 0x0A200023 15,0,0,1,1 LoUU Level of Unification Uniprocessor 27 3 LoC Level of Coherency 24 3 LoUIS Level of Unification Inner Shared 21 3 CTYPE_7 Type of Cache implemented at Level 7 18 3 CTYPE_6 Type of Cache implemented at Level 6 15 3 CTYPE_5 Type of Cache implemented at Level 5 12 3 CTYPE_4 Type of Cache implemented at Level 4 9 3 CTYPE_3 Type of Cache implemented at Level 3 6 3 CTYPE_2 Type of Cache implemented at Level 2 3 3 CTYPE_1 Type of Cache implemented at Level 1 0 3 AIDR Auxiliary ID Register ID Regs RO 0x00000000 15,0,0,1,7 CSSELR Cache Size Selection Register ID Regs RW 15,0,0,2,0 LEVEL Cache level selected 1 3 InD Selected Cache. 0x1: instruction cache, 0x0: data cache 0 1 VPIDR Virtualization Processor ID Register Virtualization Extensions RW 15,0,0,4,0 VMPIDR Virtualization Multiprocessor ID Register Virtualization Extensions RW 15,0,0,4,5 SCTLR System Control Register Virtual Memory Control RW 0x00C50878 15,1,0,0,0 TE Thumb exception enable bit. 0: exceptions including reset are handled in ARM state, 1: exceptions including reset are handled in Thumb state 30 1 AFE Access Flag Enable bit. 0: full access permissions behaviour, 1: simplified access permissions behaviour 29 1 TRE TEX remap enable bit 28 1 EE Determines the value the CPSR E bit is set to on an exception. 0: set to 0, little-endian, 1: set to 1, big endian 25 1 UWXN Regions with unprivileged write permission are forced to be XN for accesses from software executing at PL1 20 1 WXN Regions with write permissions are forced to be XN 19 1 V Vectors bit. 0: normal exception vectors, 1: high exception vectors 13 1 I Instruction caching at any available cache level enabled 12 1 Z Branch Predictions enabled 11 1 C Data caching enabled 2 1 A Strict alignment fault checking enabled 1 1 M MMU enabled 0 1 ACTLR Auxiliary Control Register Other System Control RW 0x00000006 15,1,0,0,1 SMP Coherent Requests Enabled 6 1 ASSE ACE STREX Signaling Enable 3 1 L2PF L2 Prefetch Enabled 2 1 L1PF L1 Prefetch Enabled 1 1 CPACR Coprocessor Access Control Register Other System Control RW 0x00000000 15,1,0,0,2 ASEDIS Disable Advanced SIMD Extension functionality 31 1 CP11 Defines access permission for coprocessor 11 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 22 2 CP10 Defines access permissions for coprocessor 10 00: Access denied 01: Priviledged mode access only 11: Priviledged and User mode 20 2 SCR Secure Configuration Register Security Extensions RW 0x00000000 15,1,1,0,0 SIF Secure state insruction fetches from non-secure memory are not permitted 9 1 HCE HVC instruction enabled in non-secure PL1 mode 8 1 SCD Disable Secure Monitor Call (SMC) instructions in non-secure-state 7 1 nET Early Termination of Data Operations Disabled 6 1 AW Enable modifications to the A bit in the CPSR in the non-secure state 5 1 FW Enable modification of the F bit in the CPSR in the non-secure state 4 1 EA External abort behaviour for secure and non-secure states 0: branch to abort mode on an external abort exception 1: branch to monitor mode on an external abort exception 3 1 FIQ Determines FIQ behaviour for secure and non-secure states 0: branch to FIQ mode on an FIQ exception 1: branch to monitor mode on an FIQ exception 2 1 IRQ Determines the IRQ behaviour for secure and non-secure states 0: branch to FIQ mode on an FIQ excpetion 1: branch to monitor mode on an FIQ exception 1 1 NS For modes other than Monitor mode, indicates weather the processor is in secure or non-secure state 0: secure state 1: non-secure state 0 1 SDER Secure Debug Enable Register Security Extensions RW 0x00000000 15,1,1,0,1 SUNIDEN Secure user non-invasive debug enable 1 1 SUIDEN Secure user invasive debug enable 0 1 NSACR Non-secure Access Control Register Security Extensions RW 0x00000000 15,1,1,0,2 NS_SMP The SMP bit of the Auxilary Control Register ist writeable in non-secure state 18 1 NS_L2ERR L2 ACI asynchroneous error bits of L2ECR are writable in non-secure state 17 1 NS_ACTLR_PF_WRITE A write to ACTLR.PF_ENABLE in Non-secure state is accepted 16 1 NSASEDIS Disable non-secure advanced SIMD extension functionality 15 1 NSD32DIS Disable non-secure use of D16-D31 of the VFP register file 14 1 CP11 Determines permissions to access coprocessor 11 in the non-secure state. 0: secure access only, 1: secure or non-secure access 11 1 CP10 Determines permissions to access coprocessor 10 in the non-secure state. 0: secure access only, 1: secure or non-secure access 10 1 HSCTLR Hyp System Control Register Virtualization Extensions RW 15,1,0,4,0 TE Thumb Exception Enable. 0: exceptions taken in ARM state, 1: exceptions taken in thumb state 30 1 EE Exception Endianess. 0: little endian, 1: big endian 25 1 WXN Hyp translations that permit write are forced to be execute never (XN) 19 1 I Instruction caches enabled for memory accesses made in HYP mode 12 1 C Data and unified caches enabled for memory access made in HYP mode 2 1 A Alignment fault checking enabled for memory access made in HYP mode 1 1 M MMU stage 1 address translations enabled for memory access in HYP mode 0 1 HACTLR Hyp Auxiliary Configuration Register Virtualization Extensions RW 15,1,0,4,1 HCR Hyp Configuration Register Virtualization Extensions RW 0x00000000 15,1,1,4,0 TRVM Trap Read of Virtual Memory Controls 30 1 TGE Trap General Exceptions 27 1 TVM Trap Virtual Memory Controls 26 1 TTLB Trap TLB maintenance instructions 25 1 TPU Trap Cache maintenance instructions to point of unification 24 1 TPC Trap Data/Unified cache maintenance operations to point of cohrerency 23 1 TSW Trap Data/Unified Cache maintenance operations by Set/Way 22 1 TAC Trap ACTLR accesses 21 1 TIDCP Trap Implementation Dependent Functionality 20 1 TSC Trap SMC instruction 19 1 TID3 Trap ID Group 3 18 1 TID2 Trap ID Group 2 17 1 TID1 Trap ID Group 1 16 1 TID0 Trap ID Group 0 15 1 TWE WFE instruction executed in non-secure EL1 or EL0 is trapped to EL2 14 1 TWI WFI instruction executed in non-secure EL1 or EL0 is trapped to EL2 13 1 DC Default Cacheable 12 1 BSU Barrier Shareability Upgrade 11 2 FB Force Broadcast 9 1 VA Virtual Asynchroneous Abort exception 8 1 VI Virtual IRQ exception 7 1 VF Virtual FIQ exception 6 1 AMO Asynchroneous abort mask override 5 1 IMO IRQ Mask Override 4 1 FMO FIQ Mask Override 3 1 PTW Protected Table Walk 2 1 SWIO Set/Way Invalidation Override 1 1 VM Second stage of Translation enabled 0 1 HDCR Hyp Debug Control Register Virtualization Extensions RW 0x00000006 15,1,1,4,1 TDRA Trap Debug ROM Accesses 11 1 TDOSA Trap Debug OS-releated Register Accesses 10 1 TDA Trap Debug Accesses 9 1 TDE Trap Debug Exceptions 8 1 HPME Hypervisor Performance Monitor Enable 7 1 TPM Trap Performance Monitor Accesses 6 1 TPMCR Trap Performance Monitor Control Register Accesses 5 1 HPMN Hyp Performance Monitor Count 0 5 HCPTR Hyp Coprocessor Trap Register Virtualization Extensions RW 0x000033FF 15,1,1,4,2 TCPAC Trap Coprocessor Access Control Register Accesses 21 1 TTA Trap Trace Access 20 1 TASE Trap Advanced SIMD Extension 15 1 TCP11 Trap valid Non-secure accesses to CP11 to Hyp mode 11 1 TCP10 Trap valid Non-secure accesses to CP10 to Hyp mode 10 1 HSTR Hyp System Trap Register Virtualization Extensions RW 0x00000000 15,1,1,4,3 TTEE Trap T32EE 16 1 T15 Trap valid Non-secure accesses to coprocessor primary register CRn=15 to Hyp mode 15 1 T13 Trap valid Non-secure accesses to coprocessor primary register CRn=13 to Hyp mode 13 1 T12 Trap valid Non-secure accesses to coprocessor primary register CRn=12 to Hyp mode 12 1 T11 Trap valid Non-secure accesses to coprocessor primary register CRn=11 to Hyp mode 11 1 T10 Trap valid Non-secure accesses to coprocessor primary register CRn=10 to Hyp mode 10 1 T9 Trap valid Non-secure accesses to coprocessor primary register CRn=9 to Hyp mode 9 1 T8 Trap valid Non-secure accesses to coprocessor primary register CRn=8 to Hyp mode 8 1 T7 Trap valid Non-secure accesses to coprocessor primary register CRn=7 to Hyp mode 7 1 T6 Trap valid Non-secure accesses to coprocessor primary register CRn=6 to Hyp mode 6 1 T5 Trap valid Non-secure accesses to coprocessor primary register CRn=5 to Hyp mode 5 1 T3 Trap valid Non-secure accesses to coprocessor primary register CRn=3 to Hyp mode 3 1 T2 Trap valid Non-secure accesses to coprocessor primary register CRn=2 to Hyp mode 2 1 T1 Trap valid Non-secure accesses to coprocessor primary register CRn=1 to Hyp mode 1 1 T0 Trap valid Non-secure accesses to coprocessor primary register CRn=0 to Hyp mode 0 1 HACR Hyp Auxiliary Configuration Register Virtualization Extensions RW 15,1,1,4,7 TTBR0 Translation Table Base Register 0 Virtual Memory Control RW 15,2,0,0,0 TTB_0 Pointer to the level one translation table 31 18 IRGN[0] Used with bit 0, IRGN[1], to describe inner cacheability 6 1 RGN Outer Cacheable attributes for translation table walking 4 2 S Translation table walk to 0: non-shared memory, 1: shared memory 1 1 IRGN[1] Indicates inner cacheability for the translation table walk 0 1 TTBR1 Translation Table Base Register 1 Virtual Memory Control RW 15,2,0,0,1 TTB_1 Pointer to the level one translation table 7 18 IRGN[0] Used with bit 0, IRGN[1], to describe inner cacheability 6 1 RGN Outer Cacheable attributes for translation table walking 4 2 S Translation table walk to 0: non-shared memory, 1: shared memory 1 1 IRGN[1] Indicates inner cacheability for the translation table walk 0 1 TTBCR Translation Table Base Control Register Virtual Memory Control RW 0x00000000 15,2,0,0,2 PD1 Translation table walk on TLB miss disable when using TTBR1 5 1 PD0 Translation table walk on TLB miss disable when using TTBR0 4 1 N Boundary Size of TTBR0 2 3 HTCR Hyp Translation Control Register Virtualization Extensions RW 15,2,0,4,2 VTCR Virtualization Translation Control Register Virtualization Extensions RW 15,2,1,4,2 PS Physical Address Size 15 3 TG0 Granule Size for the corresponding TTBR0_ELx 14 1 SHO Shareability attribute for memory associated with translation table walks using TTBR0 12 2 ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0 10 2 IRGN0 Inner cacheability attribute for memory associated with translation table walks using TTBR0 8 2 SL0 Starting level of the VTCR_EL2 addressed region 6 2 T0SZ Size offset of the memory region addressed by TTBR0 0 6 DACR Domain Access Control Register Virtual Memory Control RW 15,3,0,0,0 D0 Domain 0 access permissions. 00: no access, 01: client access, 11: manager access 0 2 D1 Domain 1 access permissions. 00: no access, 01: client access, 11: manager access 2 2 D2 Domain 2 access permissions. 00: no access, 01: client access, 11: manager access 4 2 D3 Domain 3 access permissions. 00: no access, 01: client access, 11: manager access 6 2 D4 Domain 4 access permissions. 00: no access, 01: client access, 11: manager access 8 2 D5 Domain 5 access permissions. 00: no access, 01: client access, 11: manager access 10 2 D6 Domain 6 access permissions. 00: no access, 01: client access, 11: manager access 12 2 D7 Domain 7 access permissions. 00: no access, 01: client access, 11: manager access 14 2 D8 Domain 8 access permissions. 00: no access, 01: client access, 11: manager access 16 2 D9 Domain 9 access permissions. 00: no access, 01: client access, 11: manager access 18 2 D10 Domain 10 access permissions. 00: no access, 01: client access, 11: manager access 20 2 D11 Domain 11 access permissions. 00: no access, 01: client access, 11: manager access 22 2 D12 Domain 12 access permissions. 00: no access, 01: client access, 11: manager access 24 2 D13 Domain 13 access permissions. 00: no access, 01: client access, 11: manager access 26 2 D14 Domain 14 access permissions. 00: no access, 01: client access, 11: manager access 28 2 D15 Domain 15 access permissions. 00: no access, 01: client access, 11: manager access 30 2 DFSR Data Fault Status Register Fault Handling RW 15,5,0,0,0 CM Abort caused by a cache maintenance operation 13 1 ExT External Abort Qualifier 12 1 WnR IType of access that caused the abort. 0: read, 1: write 11 1 FS[4] Bit 4 of the Fault Status field 10 1 DOMAIN The domain (D15-D0) of the fault address 4 4 FAULT_STATUS Type of Fault generated 0 4 IFSR Instruction Fault Status Register Fault Handling RW 15,5,0,0,1 ExT External abort qualifier 0: external abort marked as DECERR 1: external abort marked as SLVERR 12 1 FS[4] Bit 4 of the Fault Status field 10 1 LPAE On taking a Data Abort exception, this bit is set to 0 to indicate use of the Short-descriptor translation table formats 9 1 > FAULT_STATUS Type of Fault generated 0 4 ADFSR Auxilary Data Fault Status Register Fault Handling 0x00000000 RW 15,5,1,0,0 AIFSR Auxilary Instruction Fault Status Register Fault Handling 0x00000000 RW 15,5,1,0,1 HADFSR Hyp Auxiliary Data Fault Status Syndrome Register Virtualization Extensions RW 15,5,1,4,0 HAIFSR Hyp Auxiliary Instruction Fault Status Syndrome Register Virtualization Extensions RW 15,5,1,4,1 HSR Hyp Syndrome Register Virtualization Extensions RW 15,5,2,4,0 EC Exception Class 26 6 IL Size of instruction that has been trapped to Hyp mode 25 1 ISS Instruction-specific Syndrome 0 25 DFAR Data Fault Address Register Fault Handling RW 15,6,0,0,0 IFAR Instruction Fault Address Register Fault Handling RW 15,6,0,0,2 HDFAR Hyp Data Fault Address Register Virtualization Extensions RW 15,6,0,4,0 HIFAR Hyp Instruction Fault Address Register Virtualization Extensions RW 15,6,0,4,2 HPFAR Hyp IPA Fault Address Register Virtualization Extensions RW 15,6,0,4,4 FIPA Bits [39:12] of the faulting intermediate physical address 0 12 NOP None Misc WO 15,7,0,0,4 ICIALLUIS Cache Operations Register: Invalidate entire instruction cache inner shareable Cache WO 15,7,1,0,0 BPIALLIS Cache Operations Register: Invalidate entire branch predictor array inner sharable Cache WO 15,7,1,0,6 PAR Physical Address Register Address Translation RW 15,7,4,0,0 ICIALLU Cache Operations Register: invalidate all instruction caches to PoU. Also flushes branch target cache Cache WO 15,7,5,0,0 ICIMVAU Cache Operations Register: invalidate instruction cache by VA to PoU Cache WO 15,7,5,0,1 CP15ISB None Misc WO 15,7,5,0,4 BPIALL Cache Operations Register: invalidate entire branch predictor array Cache WO 15,7,5,0,6 BPIMVA Cache Operations Register: invalidate VA from branch predictor array Cache WO 15,7,5,0,7 DCIMVAC Cache Operations Register: invalidate data cache line by VA to PoC Cache WO 15,7,6,0,1 DCISW Cache Operations Register: invalidate data cache line by Set/Way Cache WO 15,7,6,0,2 ATS1CPR Address Translation Operations: Stage 1 current state EL1 read Address Translation WO 15,7,8,0,0 ATS1CPW Address Translation Operations: State 1 current state EL1 write Address Translation WO 15,7,8,0,1 ATS1CUR Address Translation Operations: Stage 1 current state unpriviledged read Address Translation WO 15,7,8,0,2 ATS1CUW Address Translation Operations: Stage 1 current state unpriviledged write Address Translation WO 15,7,8,0,3 ATS12NSOPR Address Translation Operations: Stages 1 and 2 Non-secure EL1 read Address Translation WO 15,7,8,0,4 ATS12NSOPW Address Translation Operations: Stages 1 and 2 non-secure EL1 write Address Translation WO 15,7,8,0,5 ATS12NSOUR Address Translation Operations: Stages 1 and 2 non-secure unpriviledged read Address Translation WO 15,7,8,0,6 ATS12NSOUW Address Translation Operations: Stages 1 and 2 non-secure unpriviledged write Address Translation WO 15,7,8,0,7 DCCMVAC Cache Operations Register: clean data cache line to PoC by VA Cache WO 15,7,10,0,1 DCCSW Cache Operations Register: clean data cache line by Set/Way Cache WO 15,7,10,0,2 CP15DSB Data Synchronization Barrier Misc WO 15,7,10,0,4 CP15DMB Data Memory Barrier Misc WO 15,7,10,0,5 DCCMVAU Cache Operations Register: clean data or unified cache line by VA to PoU Cache WO 15,7,11,0,1 NOP No Operations Register Misc RO 15,7,13,0,1 DCCIMVAC Cache Operations Register: clean data or unified cache line by VA to PoU Cache RO 15,7,14,0,1 DCCISW Cache Operations Register: clean and invalidate data cache line by Set/Way Cache RO 15,7,14,0,2 ATS1HR Address Translation Operations: Stage 1 Hyp Mode Read Address Translation RO 15,7,8,4,0 ATS1HW Address Translation Operations: Stage 1 Hyp Mode Write Address Translation RO 15,7,8,4,1 TLBIALLIS Invalidate entire unified TLB Inner Shareable TLB WO 15,8,3,0,0 TLBIMVAIS Invalidate Unified TLB entry by VA Inner Shareable TLB WO 15,8,3,0,1 TLBIASIDIS Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,3,0,2 TLBIMVAAIS Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,3,0,3 ITLBIALL Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,5,0,0 ITLBIMVA Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,5,0,1 ITLBIASID Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,5,0,2 DTLBIALL Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,6,0,0 DTLBIMVA Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,6,0,1 DTLBIASID Invalidate Unified TLB entry by VA all ASID Inner Shareable TLB WO 15,8,6,0,2 TLBIALL Table Maintenance Operations: Invalifate entire unified TLB TLB WO 15,8,7,0,0 TLBIMVA Table Maintenance Operations: Invalidate Unified TLB by VA TLB WO 15,8,7,0,1 TLBIASID Table Maintenance Operations: Invalidate TLB entries by ASID match TLB WO 15,8,7,0,2 TLBIMVAA Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,7,0,3 TLBIALLHIS Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,3,4,0 TLBIMVAHIS Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,3,4,1 TLBIALLNSNHIS Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,3,4,4 TLBIALLH Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,7,4,0 TLBIMVAH Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,7,4,1 TLBIALLNSNH Table Maintenance Operations: Invalidate TLB entries by VA All ASID TLB WO 15,8,7,4,4 PMCR Performance Monitor Control Register Performance Monitor RW 0x41D30000 15,9,12,0,0 IMP Implementor Code. 0x41: arm 24 8 ID_CODE Identification Code 16 8 N Number of Counters Implemented 11 4 DP Disable Cycle Counter PMCCNTR in prohibited regions 5 1 X Export of the events from the event bus to an external monitoring block enabled 4 1 D Cycle Count Divider. 0: count every clock cycle when enabled. 1: count every 64th clock cycle when enabled. 3 1 C Cycle Counter Reset 2 1 P Reset all Performance Counters, including PMCCNTR 1 1 E Enable All Counters including PMCCNTR 0 1 PMNCNTENSET Count Enable Set Register Performance Monitor RW 15,9,12,0,1 C Cycle Counter Enabled 31 1 P1 Counter 1 Enabled 1 1 P2 Counter 0 Enabled 0 1 PMNCNTENCLR Count Enable Clear Register Performance Monitor RW 15,9,12,0,2 C PMCCNTR overflow interrupt clear bit 31 1 P1 Clear interrupt request on PMC1 overflow 1 1 P2 Clear interrupt request on PMC0 overflow 0 1 PMOVSR Overflow Flag Status Register Performance Monitor RW 15,9,12,0,3 C Cycle Counter Overflow Flag 31 1 P1 Counter 1 Overflow Flag 1 1 P2 Counter 0 Overflow Flag 0 1 PMSWINC Software Increment Register Performance Monitor WO 15,9,12,0,4 P1 Increment Counter 1 1 1 P0 Increment Counter 0 0 1 PMSELR Performance Counter Selection Register Performance Monitor RW 0x00000000 15,9,12,0,5 SEL Counter select. 0: select counter 0, 1: select counter 1, b11111: access the Cycle Count Filter Control Register. 31 1 PMCEID0 Common Event Identification Register 0 Performance Monitor RO 0x3BFFF0F3F 15,9,12,0,6 Event 0x1D Bus Cycle 29 1 Event 0x1C Write to translation table base 28 1 Event 0x1B Instruction speculatively executed 27 1 Event 0x1A Local Memory Error 26 1 Event 0x19 Bus Access 25 1 Event 0x18 Level 2 data cache write-back 24 1 Event 0x17 Level 2 data cache refill 23 1 Event 0x16 Level 1 data cache write-back 22 1 Event 0x15 Level 1 instruction cache access 21 1 Event 0x14 Data memory access 20 1 Event 0x13 Predictable branch speculatively executed 19 1 Event 0x12 Cycle 18 1 Event 0x11 Mispredicted or not predicted branch speculatively executed 17 1 Event 0x10 Unaligned Load or Store 16 1 Event 0x0F Precedure Return 15 1 Event 0x0E Bus Cycle 14 1 Event 0x0D Immediate Branch 13 1 Event 0x0C Software change of the PC 12 1 Event 0x0B Write to CONTEXTIDR 11 1 Event 0x0A Exception return 10 1 Event 0x09 Exception taken 9 1 Event 0x08 Instruction architecturally executed 8 1 Event 0x07 Store 7 1 Event 0x06 Load 6 1 Event 0x05 Level 1 data TLB refill 5 1 Event 0x04 Level 1 data cache access 4 1 Event 0x03 Level 1 data cache refill 3 1 Event 0x02 Level 1 Instruction TLB refill 2 1 Event 0x01 Level 1 Instruction Cache refill 1 1 Event 0x00 Software Increment 0 1 PMCEID1 Common Event Identification Register 1 Performance Monitor RO 0x00000000 15,9,12,0,7 PMCCNTR Cycle Count Register Performance Monitor RW 15,9,13,0,0 PMXEVTYPER Performance Monitor Event Type Select Register RW 15,9,13,0,1 SEL Selected Event Specificator 0 8 PMXEVCNTR Event Count Register. Counts instances of an event selected by PMXEVTYPER Performance Monitor RW 15,9,13,0,2 PMUSERENR User Enable Register Performance Monitor RW 0x00000000 15,9,14,0,0 EN User mode enable bit. 0 1 PMINTENSET Interrupt Enable Set Register Performance Monitor RW 15,9,14,0,1 C PMCCNTR overflow interrupt request enable. 31 1 P1 PMC1 overflow interrupt request enable. 1 1 P0 PMC0 overflow interrupt request enable. 0 1 PMINTENCLR Interrupt Enable Clear Register Performance Monitor RW 15,9,14,0,2 C PMCCNTR overflow interrupt clear bit. 31 1 P1 Clear interrupt request on PMC1 overflow. 1 1 P0 Clear interrupt request on PMC0 overflow. 0 1 PMOVSSET Performance Monitor Overflow Flag Status Set Register Performance Monitor RW 15,9,14,0,3 P Mode/State Configuration P Bit 31 1 U Mode/State Configuration U Bit 30 1 NSK Mode/State Configuration NSK Bit 29 1 NSU Mode/State Configuration NSU Bit 28 1 L2CTLR L2 Cache Control Register Impl. Defined RW 0x00000000 15,9,0,1,2 L2RSTDISABLE L2 valid RAM contents are not reset by hardware 31 1 IWINC Controls how the index increments 30 4 NUM_PROCS Number of Processors 25 2 SFEN Snoop Filter Enable 20 1 L2_ECC_DISABLE L2 ECC is disabled 19 1 L2_CACHE_DISABLE L2 cache is disabled 18 1 TRAM_SETUP_LATENCY L2 Tag-RAM setup Latency (1-8 cycles) 15 3 TRAM_READ_LATENCY L2 Tag-RAM read Latency (1-8 cycles) 12 3 TRAM_WRITE_LATENCY L2 Tag-RAM write Latency (1-8 cycles) 9 3 DRAM_SETUP_LATENCY L2 Data RAM Setup Latency (1-8 cycles) 6 3 DRAM_READ_LATENCY L2 Data RAM Read Latency (1-8 cycles) 3 3 DRAM_WRITE_LATENCY L2 Data RAM Write Latency (1-8 cycles) 0 3 L2ECTLR L2 Extended Control Register Impl. Defined RW 0x00000000 15,9,0,1,3 ECC_UNCOR_ERR An uncorrectable ECC error has occurred 30 1 AXI_ASYNC_ERR AXI asynchroneous error has occurred 29 1 L2DRAMRMD L2 dynamic RAM retention disabled 0 3 SCUCTLR SCU Control Register Impl. Defined RW 0x00000000 15,9,0,1,3 P3_RETENTION_DISABLE Processor 3 Retention Disabled 30 1 P3_POWER_STATUS Processor 3 Power Status 28 2 P2_RETENTION_DISABLE Processor 2 Retention Disabled 26 1 P2_POWER_STATUS Processor 2 Power Status 24 2 P1_RETENTION_DISABLE Processor 1 Retention Disabled 22 1 P1_POWER_STATUS Processor 1 Power Status 20 2 P0_RETENTION_DISABLE Processor 0 Retention Disabled 18 1 P0_POWER_STATUS Processor 0 Power Status 16 2 ACTLR.SMP Copy of ACTLR's SMP field 4 4 NUM_PROCESSORS Number of Processors present 0 2 L2MRERRSR L2 Memory Error Syndrome Register Impl. Defined RW 0x00000000 15,9,0,1,3 FATAL The Fatal bit is set to 1 on the first memory error that caused a Data Abort 31 1 OTHER_ERR_CNT This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID, way, or index information in this register while the sticky Valid bit is set 25 6 REPEAT_ERR_CNT This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID, way or index information in this register while the sticky Valid bit is set 19 6 ERR_LOCATION Location at which the first memory error is detected. [18:6]: Index, [5:2]: Way 2 17 RAMID RAM where the first memory error occurred. 0: Tag RAM, 1: Data RAM 1 1 VALID The VALID bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written 0 1 PRRR Primary Region Remap Register Virtual Memory Control RW 0x00098AA4 15,10,2,0,0 NOS7 Tex[0]=7 memory region is (0) outer or (1) inner shareable 31 1 NOS6 Tex[0]=7 memory region is (0) outer or (1) inner shareable 30 1 NOS5 Tex[0]=7 memory region is (0) outer or (1) inner shareable 29 1 NOS4 Tex[0]=7 memory region is (0) outer or (1) inner shareable 28 1 NOS3 Tex[0]=7 memory region is (0) outer or (1) inner shareable 27 1 NOS2 Tex[0]=7 memory region is (0) outer or (1) inner shareable 26 1 NOS1 Tex[0]=7 memory region is (0) outer or (1) inner shareable 25 1 NOS0 Tex[0]=7 memory region is (0) outer or (1) inner shareable 24 1 NS1 Mapping of S=1 attribute for normal memory 19 1 NS0 Mapping of S=1 attribute for normal memory 18 1 DS1 Mapping of S=1 attribute for device memory 17 1 DS0 Mapping of S=0 attribute for device memory 16 1 TR7 Primary TEX mapping for memory attributes 7 14 2 TR6 Primary TEX mapping for memory attributes 6 12 2 TR5 Primary TEX mapping for memory attributes 5 10 2 TR4 Primary TEX mapping for memory attributes 4 8 2 TR3 Primary TEX mapping for memory attributes 3 6 2 TR2 Primary TEX mapping for memory attributes 2 4 2 TR1 Primary TEX mapping for memory attributes 1 2 2 TR0 Primary TEX mapping for memory attributes 0 0 2 MAIR0 Memory Attribute Indirection Register 0 Virtual Memory Control RW 0x00098AA4 15,10,2,0,0 ATTR_3 Memory Attribute Encoding Field 3 24 8 ATTR_2 Memory Attribute Encoding Field 2 16 8 ATTR_1 Memory Attribute Encoding Field 1 8 8 ATTR_0 Memory Attribute Encoding Field 0 0 8 NMRR Normal Memory Remap Register Virtual Memory Control RW 0x44E048E0 15,10,2,0,1 OR7 Outer Cacheable property mapping for memory attributes 7 30 2 OR6 Outer Cacheable property mapping for memory attributes 7 28 2 OR5 Outer Cacheable property mapping for memory attributes 7 26 2 OR4 Outer Cacheable property mapping for memory attributes 7 24 2 OR3 Outer Cacheable property mapping for memory attributes 7 22 2 OR2 Outer Cacheable property mapping for memory attributes 2 20 2 OR1 Outer Cacheable property mapping for memory attributes 1 18 2 OR0 Outer Cacheable property mapping for memory attributes 0 16 2 IR7 Inner Cacheable property mapping for memory attributes 7 14 2 IR6 Inner Cacheable property mapping for memory attributes 6 12 2 IR5 Inner Cacheable property mapping for memory attributes 5 10 2 IR4 Inner Cacheable property mapping for memory attributes 4 8 2 IR3 Inner Cacheable property mapping for memory attributes 3 6 2 IR2 Inner Cacheable property mapping for memory attributes 2 4 2 IR1 Inner Cacheable property mapping for memory attributes 1 2 2 IR0 Inner Cacheable property mapping for memory attributes 0 0 2 MAIR1 Memory Attribute Indirection Register 1 Virtual Memory Control RW 0x44E048E0 15,10,2,0,1 ATTR_7 Memory Attribute Encoding Field 7 24 8 ATTR_6 Memory Attribute Encoding Field 6 16 8 ATTR_5 Memory Attribute Encoding Field 5 8 8 ATTR_4 Memory Attribute Encoding Field 4 0 8 AMAIR0 Auxiliary Memory Attribute Indirection Register 0 Virtualization Extensions RW 15,10,3,0,0 AMAIR1 Auxiliary Memory Attribute Indirection Register 1 Virtualization Extensions RW 15,10,3,0,1 HMAIR0 Hyp Memory Attribute Indirection Register 0 Virtualization Extensions RW 15,10,2,4,0 HMAIR1 Hyp Memory Attribute Indirection Register 1 Virtualization Extensions RW 15,10,2,4,1 HAMAIR0 Hyp Auxiliary Memory Attribute Indirection Register 0 Virtualization Extensions RW 15,10,3,4,0 HAMAIR1 Hyp Auxiliary Memory Attribute Indirection Register 1 Virtualization Extensions RW 15,10,3,4,1 VBAR Vector Base Address Register Security Extensions RW 0x00000000 15,12,0,0,0 VECT_BASE_ADDR The base address of normal exception vectors 5 27 MVBAR Monitor Vector Base Address Register Security Extensions RW 15,12,0,0,1 MONITOR_VBA The base address of the exception vectors for exceptions that are handled in monitor mode 5 27 ISR Interrupt Status Register Security Extensions RO 15,12,1,0,0 A External abort pending 8 1 I Interrupt pending 7 1 F Fast interrupt pending 6 1 HVBAR Hyp Vector Base Address Register Virtualization Extensions RW 15,12,0,4,0 VECT_BASE_ADDR Vector Base Address 0 32 FCSEIDR Fast Context Switch Extension Not Implemented Other System Control RO 0x00000000 15,13,0,0,0 CONTEXTIDR Context ID Register Virtual Memory Control RW 15,13,0,0,1 PROCID Processor Identifier 8 24 ASID Address Space Identifier 0 8 TPIDRURW Software Thread ID Register 1 Misc RW 15,13,0,0,2 TPIDRURO Software Thread ID Register 2 Misc RO 15,13,0,0,3 TPIDRPRW Software Thread ID Register 3 Misc RW 15,13,0,0,4 HTPIDR Hyp Software Thread ID Register Misc RO 15,13,0,4,2 CNTFRQ Generic Timer Frequency Register Generic Timer RW 15,14,0,0,0 CNTKCTL Generic Timer non-secure PL1 Control Register Generic Timer RO 15,14,1,0,0 CNTP_TVAL Generic Timer PL1 Physical Timer Value Register Generic Timer RO 15,14,2,0,0 CNTP_CTL Generic Timer PL1 Physical Timer Control Register Generic Timer RO 0x00000000 15,14,2,0,1 CNTV_TVAL Generic Timer PL1 Virtual Timer Value Register Generic Timer RO 15,14,3,0,0 CNTV_CTL Generic Timer PL1 Virtual Timer Control Register Generic Timer RO 15,14,3,0,1 CNTHCTL Generic Timer PL1 non-secure PL2 Control Register Generic Timer RO 15,14,1,4,0 CNTHP_TVAL Generic Timer non-secure PL2 Physical Timer Value Register Generic Timer RO 15,14,2,4,0 CNTHP_CTL Generic Timer non-secure PL2 Physical Timer Control Register Generic Timer RO 15,14,2,4,1 DGNCTLR0 Diagnostic Control Register 0 Impl. Defined RW 15,15,0,0,0 DGNCTLR1 Diagnostic Control Register 1 Impl. Defined RW 15,15,0,0,1 DGNCTLR2 Diagnostic Control Register 2 Impl. Defined RW 15,15,0,0,2 DGNCCTLR Diagnostic Common Control Register Impl. Defined RW 15,15,0,0,4 DCCIALL Data Cache Clean And Invalidate All Register Impl. Defined WO 15,15,14,1,0 LEVEL Cache Level 1 2 CDBGDR0 Direct access to internal memory, Data Register 0 Impl. Defined RO 15,15,0,3,0 PMSD Partial MOESI state, Dirty 31 1 POMA Partial Outer Memory Attribute 30 1 PMSV Partial MOESI State, Exlusive 29 1 PMSV Partial MOESI State, Valid 28 1 NS Non-Secure State, NS 27 1 TA Tag Address 0 27 CDBGDR1 Direct access to internal memory, Data Register 1 Impl. Defined RO 15,15,0,3,1 PMSGS Partial MOESI state, Globally Shared 0 1 CDBGDR2 Direct access to internal memory, Data Register 2 Impl. Defined RO 15,15,0,3,2 CDBGDCT Data Cache Tag Read Operation Register Impl. Defined WO 15,15,2,3,0 CACHE_WAY Cache Way 30 2 SET_INDEX Set Index 6 7 DATA_OFF Cache DWord Data Offset 3 3 CDBGICT Instruction Cache Tag Read Operation Register Impl. Defined WO 15,15,2,3,1 CACHE_WAY Cache Way 30 2 SET_INDEX Set Index 6 7 DATA_OFF Cache DWord Data Offset 3 3 CDBGDCD Data Cache Data Read Operation Register Impl. Defined WO 15,15,4,3,0 CACHE_WAY Cache Way 30 2 SET_INDEX Set Index 6 7 DATA_OFF Cache DWord Data Offset 3 3 CDBGICD Instruction Cache Data Read Operation Register Impl. Defined WO 15,15,4,3,1 CACHE_WAY Cache Way 30 2 SET_INDEX Set Index 6 7 DATA_OFF Cache DWord Data Offset 3 3 CDBGTD TLB Data Read Operation Register Impl. Defined WO 15,15,4,3,2 TLB_WAY TLB Way 30 2 TYPE Type 6 1 TLB_INDEX TLB Index 3 8 FILASTARTR Peripheral port start address register Impl. Defined RW 15,15,0,4,1 FLT_START_ADDR Start address of the peripheral port physical memory region 12 20 FILT_EN Indicates that FLT_START_ADDR and FLT_END_ADDR are valid 0 1 FILAENDR Peripheral port end address register Impl. Defined RW 15,15,0,4,2 FLT_END_ADDR End address of the peripheral port physical memory region 12 20