%define V7_TARGET 1 %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_default.grd" %if ((_TARGET_OS != OS_THREADX) && (_TARGET_OS != OS_INTEGRITY) && \ (_TARGET_OS != OS_UNIX)) %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_banked.grd" %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_hyp.grd" %endif %if (_TARGET_COPROCESSOR >= 2 && _TARGET_OS != OS_THREADX) %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_vfp.grd" %endif # Don't include any of the coprocessor registers in run-mode or TimeMachine. %if ((_TIMEMACHINE != 1) && !defined(VXWORKS_OSE_CHORUS_INTEGRITY_UNIX) && \ !(_IS_RUN_MODE)) %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_system_coprocessor.grd" %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_v7_types.grd" %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_v7_cpuid.grd" general { version = 3 bcr_info1 { # MIDR address=691; width=32; } bcr_mask1 = 0xffffffff; bcr_info2 { # DBGDSCR address=409; width=32; } bcr_mask2 = 0xffffffff; } %if ((_TARGET_OS != OS_THREADX) && (_TARGET_OS != OS_INTEGRITY) && \ (_TARGET_OS != OS_UNIX)) %if ((bcr_value2 & 0x00010000) == 0) %include "${__TOOLS_DEFAULTS_DIR__}/registers/arm_monitor.grd" %endif %endif enum { merrsr_ramid { "L1-I tag RAM" { value = 0x00 } "L1-I data RAM" { value = 0x01 } "L1-I BTB RAM" { value = 0x02 } "L1-D tag RAM" { value = 0x08 } "L1-D data RAM" { value = 0x09 } "L2 tag RAM" { value = 0x10 } "L2 data RAM" { value = 0x11 } "L2 snoop tag RAM" { value = 0x12 } "L2 dirty RAM" { value = 0x14 } "L2 TLB RAM" { value = 0x18 } } } bitfield { actlr_bitfield { Snoop_delayed_exclusive_handling { loc="31" } Force_main_clock_enable_active { loc="30" } Force_NEON_VFP_clock_enable_active { loc="29" } Write_streaming_no_allocate_threshold { loc="27..28" } Write_streaming_no_L1_allocate_threshold { loc="25..26" } Non_cacheable_streaming_enhancement { loc="24" } Force_in_order_requests_to_the_same_set_and_way { loc="23" } Force_in_order_load_issue { loc="22" } Disable_L2_TLB_prefetching { loc="21" } Disable_L2_translation_table_walk_IPA_PA_cache { loc="20" } Disable_L2_stage_1_translation_table_walk_cache { loc="19" } Disable_L2_stage_1_translation_table_walk_L2_PA_cache { loc="18" } Disable_L2_TLB_performance_optimization { loc="17" } Enable_full_Strongly_Ordered_and_Device_load_replay { loc="16" } Force_in_order_issue_in_branch_execution_unit { loc="15" } Force_limit_of_one_group_commit_deallocate_per_cycle { loc="14" } Flush_after_CP14_CP15_writes { loc="13" } Force_push_of_CP14_CP15_registers { loc="12" } Limit_to_one_instruction_per_instruction_group { loc="11" } Force_serialization_after_each_group { loc="10" } Disable_flag_renaming_optimization { loc="9" } Execute_WFI_instruction_as_a_NOP { loc="8" } Execute_WFE_instruction_as_a_NOP { loc="7" } SMP { loc="6" } Execute_PLD_instructions_as_a_NOP { loc="5" } Disable_indirect_predictor { loc="4" } Disable_micro_BTB { loc="3" } Limit_to_one_loop_buffer { loc="2" } Disable_loop_buffer { loc="1" } Enable_invalidates_of_BTB { loc="0" } } nsacr_cortexa15_bitfield { NSTRCDIS { loc="20" } RFR { loc="19" } NS_SMP { loc="18" } NS_L2ERR { loc="17" } NSASEDIS { loc="15" } NSD32DIS { loc="14" } cp13 { loc="13" } cp12 { loc="12" } cp11 { loc="11" } cp10 { loc="10" } cp9 { loc="9" } cp8 { loc="8" } cp7 { loc="7" } cp6 { loc="6" } cp5 { loc="5" } cp4 { loc="4" } cp3 { loc="3" } cp2 { loc="2" } cp1 { loc="1" } cp0 { loc="0" } } adfsr_bitfield { Valid { loc="31" } RAM_ID { loc="24..30" } L2_Error { loc="23" } Bank_Way { loc="18..22" } Index { loc="0..17" } } l2ctlr_bitfield { L2RSTDISABLE_monitor { loc="31" } Number_of_processors { loc="24..25" } Interrupt_Controller { loc="23" } ECC_and_parity_enable { loc="21" } Tag_RAM_slice { loc="12" } Data_RAM_slice { loc="10..11" } Tag_RAM_setup { loc="9" } Tag_RAM_latency { loc="6..8" } Data_RAM_setup { loc="5" } Data_RAM_latency { loc="0..2" } } l2ectlr_bitfield { L2_internal_asynchronous_error { loc="30" } AXI_asynchronous_error { loc="29" } } l2actlr_bitfield { Force_L2_tag_bank_clock_enable_active { loc="28" } Force_L2_logic_clock_enable_active { loc="27" } Enable_L2_GIC_and_Timer_regional_clock_gates { loc="26" } Enable_replay_threshold_single_issue { loc="16" } Enable_CPU_WFI_retention_mode { loc="15" } Enable_UniqueClean_evictions_with_data { loc="14" } Disable_SharedClean_data_transfers { loc="13" } Disable_multiple_outstanding_WriteClean_WriteBack_Evicts_using_the_same_AWID { loc="12" } Disable_DSB_with_no_DVM_synchronization { loc="11" } Disable_non_secure_debug_array_read { loc="10" } Enable_use_of_PF_bit_in_L2_cache_replacement_algorithm { loc="9" } Disable_DVM_CMO_message_broadcast { loc="8" } Enable_hazard_detect_timeout { loc="7" } Disable_shareable_transactions_from_master { loc="6" } Disable_WriteUnique_and_WriteLineUnique_transactions_from_master { loc="4" } Disable_clean_evict_push_to_external { loc="3" } Limit_to_one_request_per_tag_bank { loc="2" } Enable_arbitration_replay_threshold_timeout { loc="1" } Disable_prefetch_forwarding { loc="0" } } l2pfr_bitfield { Disable_dynamic_throttling_of_load_store_prefetch_requests { loc="12" } Enable_prefetch_requests_from_ReadUnique_transactions { loc="11" } Disable_table_walk_descriptor_access_prefetch { loc="10" } L2_instruction_fetch_prefetch_distance { loc="7..8" } L2_load_store_data_prefetch_distance { loc="4..5" } } actlr2_bitfield { Enable_CPU_regional_clock_gates { loc="31" } Execute_data_cache_clean_as_clean_invalidate { loc="0" } } cpumerrsr_bitfield { Fatal { loc="63" } Other_error_count { loc="40..47" } Repeat_error_count { loc="32..39" } Valid { loc="31" } RAMID { loc="24..30"; type="merrsr_ramid" } Bank_Way { loc="18..22" } Index { loc="0..17" } } l2merrsr_bitfield { Fatal { loc="63" } Other_error_count { loc="40..47" } Repeat_error_count { loc="32..39" } Valid { loc="31" } RAMID { loc="24..30"; type="merrsr_ramid" } CPUID_Way { loc="18..21" } Index { loc="0..17" } } cbar_bitfield { "PERIPHBASE[39:32]" { loc="0..7" } "PERIPHBASE[31:15]" { loc="15..31" } } } register { TEECR { address=17130; type="teecr_bitfield" } TEEHBR { address=17131 } JIDR { address=17126; type="jidr_bitfield" } JOSCR { address=17125; type="joscr_bitfield" } JMCR { address=17127; type="jmcr_bitfield" } MIDR { address=691; width=32; permission="write/none"; type="midr_bitfield" } CTR { address=692; width=32; permission="write/none"; type="ctr_bitfield" } TCMTR { address=693; width=32; permission="write/none" } TLBTR { address=694; width=32; permission="write/none"; type="tlbtr_bitfield" } MPIDR { address=696; width=32; permission="write/none"; type="mpidr_bitfield" } REVIDR { address=697; width=32; permission="write/none" } CCSIDR { address=2739; width=32; permission="write/none"; type="ccsidr_bitfield" } CLIDR { address=2740; width=32; permission="write/none"; type="clidr_bitfield" } AIDR { address=2746; width=32; permission="write/none" } CSSELR { address=4787; width=32; type="csselr_bitfield" } VPIDR { address=8883; width=32; type="mpidr_bitfield" } VMPIDR { address=8888; width=32; type="mpidr_bitfield" } SCTLR { address=819; width=32; type="sctlr_vmsa_bitfield" } ACTLR { address=820; width=32; type="actlr_bitfield" } CPACR { address=821; width=32; type="cpacr_bitfield" } %if ((bcr_value2 & 0x00010000) == 0) SCR { address=827; width=32; type="scr_bitfield" } SDER { address=828; width=32; type="sder_bitfield" } NSACR { address=829; width=32; type="nsacr_cortexa15_bitfield" } %else NSACR { address=829; width=32; permission="write/none"; type="nsacr_cortexa15_bitfield" } %endif HSCTLR { address=9011; width=32; type="hsctlr_bitfield" } HACTLR { address=9012; width=32 } HCR { address=9019; width=32; type="hcr_bitfield" } HDCR { address=9020; width=32; type="hdcr_bitfield" } HCPTR { address=9021; width=32; type="hcptr_bitfield" } HSTR { address=9022; width=32; type="hstr_bitfield" } HACR { address=9026; width=32 } TTBR0 { address=17138; width=64; type="ttbr0_64_bitfield" } TTBR1 { address=17170; width=64; type="ttbr1_64_bitfield" } TTBCR { address=949; width=32; type="ttbcr_long_bitfield" } HTCR { address=9141; width=32; type="htcr_bitfield" } VTCR { address=9149; width=32; type="vtcr_bitfield" } HTTBR { address=17266; width=64 } VTTBR { address=17330; width=64; type="vttbr_bitfield" } DACR { address=1075; width=32; type="dacr_bitfield" } DFSR { address=1331; width=32; type="dfsr_pmsa_bitfield" } IFSR { address=1332; width=32; type="ifsr_pmsa_bitfield" } ADFSR { address=1339; width=32; type="adfsr_bitfield" } AIFSR { address=1340; width=32 } HADFSR { address=9531; width=32; type="adfsr_bitfield" } HAIFSR { address=9532; width=32 } HSR { address=9539; width=32; type="hsr_bitfield" } DFAR { address=1459; width=32 } IFAR { address=1461; width=32 } HDFAR { address=9651; width=32 } HIFAR { address=9653; width=32 } HPFAR { address=9655; width=32; type="hpfar_bitfield" } ICIALLUIS { address=1595; width=32; permission="read/none"; hide=true } BPIALLIS { address=1601; width=32; permission="read/none"; hide=true } # The 32- and 64-bit formats of PAR are different enough that it seems best # to expose it as two seperate registers. PAR32 { address=1619; width=32; type="par32_bitfield" } PAR64 { address=17148; width=64; type="par64_bitfield" } ICIALLU { address=1627; width=32; permission="read/none"; hide=true } ICIMVAU { address=1628; width=32; permission="read/none"; hide=true } CP15ISB { address=1631; width=32; permission="read/none"; hide=true } BPIALL { address=1633; width=32; permission="read/none"; hide=true } BPIMVA { address=1634; width=32; permission="read/none"; hide=true } DCIMVAC { address=1636; width=32; permission="read/none"; hide=true } DCISW { address=1637; width=32; permission="read/none"; hide=true } ATS1CPR { address=1651; width=32; permission="read/none"; hide=true } ATS1CPW { address=1652; width=32; permission="read/none"; hide=true } ATS1CUR { address=1653; width=32; permission="read/none"; hide=true } ATS1CUW { address=1654; width=32; permission="read/none"; hide=true } ATS12NSOPR { address=1655; width=32; permission="read/none"; hide=true } ATS12NSOPW { address=1656; width=32; permission="read/none"; hide=true } ATS12NSOUR { address=1657; width=32; permission="read/none"; hide=true } ATS12NSOUW { address=1658; width=32; permission="read/none"; hide=true } DCCMVAC { address=1668; width=32; permission="read/none"; hide=true } DCCSW { address=1669; width=32; permission="read/none"; hide=true } CP15DSB { address=1671; width=32; permission="read/none"; hide=true } CP15DMB { address=1672; width=32; permission="read/none"; hide=true } DCCMVAU { address=1676; width=32; permission="read/none"; hide=true } DCCIMVAC { address=1700; width=32; permission="read/none"; hide=true } DCCISW { address=1701; width=32; permission="read/none"; hide=true } ATS1HR { address=9843; width=32; permission="read/none"; hide=true } ATS1HW { address=9844; width=32; permission="read/none"; hide=true } TLBIALLIS { address=1739; width=32; permission="read/none"; hide=true } TLBIMVAIS { address=1740; width=32; permission="read/none"; hide=true } TLBIASIDIS { address=1741; width=32; permission="read/none"; hide=true } TLBIMVAAIS { address=1742; width=32; permission="read/none"; hide=true } TLBIALL { address=1771; width=32; permission="read/none"; hide=true } TLBIMVA { address=1772; width=32; permission="read/none"; hide=true } TLBIASID { address=1773; width=32; permission="read/none"; hide=true } TLBIMVAA { address=1774; width=32; permission="read/none"; hide=true } TLBIALLHIS { address=9931; width=32; permission="read/none"; hide=true } TLBIMVAHIS { address=9932; width=32; permission="read/none"; hide=true } TLBIALLNSNHIS { address=9935; width=32; permission="read/none"; hide=true } TLBIALLH { address=9963; width=32; permission="read/none"; hide=true } TLBIMVAH { address=9964; width=32; permission="read/none"; hide=true } TLBIALLNSNH { address=9967; width=32; permission="read/none"; hide=true } PMCR { address=1939; width=32; type="pmcr_bitfield" } PMCNTENSET { address=1940; width=32; type="pm_event_c_bitfield" } PMCNTENCLR { address=1941; width=32; type="pm_event_c_bitfield" } PMOVSR { address=1942; width=32; type="pm_event_c_bitfield" } PMSWINC { address=1943; width=32; type="pm_event_bitfield"; permission="read/none"; hide=true } PMSELR { address=1944; width=32 } PMCCNTR { address=1947; width=32 } PMXEVTYPER { address=1948; width=32 } PMXEVCNTR { address=1949; width=32 } PMUSERENR { address=1955; width=32; type="pmuserenr_bitfield" } PMINTENSET { address=1956; width=32; type="pm_event_c_bitfield" } PMINTENCLR { address=1957; width=32; type="pm_event_c_bitfield" } PMOVSSET { address=1958; width=32; type="pm_event_c_bitfield" } L2CTLR { address=3893; width=32; type="l2ctlr_bitfield" } L2ECTLR { address=3894; width=32; type="l2ectlr_bitfield" } PRRR { address=1987; width=32; type="prrr_bitfield" } NMRR { address=1988; width=32; type="nmrr_bitfield" } MAIR0 { address=1987; width=32; type="mair0_bitfield" } MAIR1 { address=1988; width=32; type="mair1_bitfield" } AMAIR0 { address=1995; width=32 } AMAIR1 { address=1996; width=32 } HMAIR0 { address=10179; width=32; type="mair0_bitfield" } HMAIR1 { address=10180; width=32; type="mair1_bitfield" } HAMAIR0 { address=10187; width=32 } HAMAIR1 { address=10188; width=32 } VBAR { address=2227; width=32 } %if ((bcr_value2 & 0x00010000) == 0) MVBAR { address=2228; width=32 } %endif ISR { address=2235; width=32; type="isr_bitfield"; permission="write/none" } HVBAR { address=10419; width=32 } FCSEIDR { address=2355; width=32; type="fcseidr_bitfield" } CONTEXTIDR { address=2356; width=32; type="contextidr_bitfield" } TPIDRURW { address=2357; width=32 } TPIDRURO { address=2358; width=32 } TPIDRPRW { address=2359; width=32 } HTPIDR { address=10549; width=32 } %if ((bcr_value2 & 0x00010000) == 0) CNTFRQ { address=2483; width=32 } %else CNTFRQ { address=2483; width=32; permission="write/none" } %endif CNTPCT { address=17162; width=64; permission="write/none" } CNTKCTL { address=2491; width=32; type="cntkctl_bitfield" } CNTP_TVAL { address=2499; width=32 } CNTP_CTL { address=2500; width=32; type="cnt_ctl_bitfield" } CNTV_TVAL { address=2507; width=32 } CNTV_CTL { address=2508; width=32; type="cnt_ctl_bitfield" } CNTVCT { address=17194; width=64; permission="write/none" } CNTP_CVAL { address=17226; width=64 } CNTV_CVAL { address=17258; width=64 } CNTVOFF { address=17290; width=64 } CNTHCTL { address=10683; width=32; type="cnthctl_bitfield" } CNTHP_TVAL { address=10691; width=32 } CNTHP_CTL { address=10692; width=32; type="cnt_ctl_bitfield" } CNTHP_CVAL { address=17354; width=64 } IL1DATA0 { address=2611; width=32 } IL1DATA1 { address=2612; width=32 } IL1DATA2 { address=2613; width=32 } DL1DATA0 { address=2619; width=32 } DL1DATA1 { address=2620; width=32 } DL1DATA2 { address=2621; width=32 } DL1DATA3 { address=2622; width=32 } RAMINDEX { address=2643; width=32; permission="read/none"; hide=true } L2ACTLR { address=4659; width=32; type="l2actlr_bitfield" } L2PFR { address=4662; width=32; type="l2pfr_bitfield" } %if ((bcr_value1 & 0x00f0000f) >= 0x00300000) ACTLR2 { address=4663; width=32; type="actlr2_bitfield" } %endif CPUMERRSR { address=17164; width=64; type="cpumerrsr_bitfield" } L2MERRSR { address=17196; width=64; type="l2merrsr_bitfield" } CBAR { address=10803; width=32; type="cbar_bitfield"; permission="write/none" } # The INTEGRITY ARMv7 setup script uses the legacy names, so provide them # here for compatability. control { access="synonym"; address="SCTLR"; hide=true } ttbase0 { access="synonym"; address="TTBR0"; hide=true } ttbase1 { access="synonym"; address="TTBR1"; hide=true } ttbase_ctrl { access="synonym"; address="TTBCR"; hide=true } } group { cp15 { sn = "CP15" register += { "MIDR", "CTR", "TCMTR", "TLBTR", "MPIDR", "REVIDR" } register += { "ID_PFR0", "ID_PFR1", "ID_DFR0", "ID_AFR0", "ID_MMFR0" } register += { "ID_MMFR1", "ID_MMFR2", "ID_MMFR3", "ID_ISAR0" } register += { "ID_ISAR1", "ID_ISAR2", "ID_ISAR3", "ID_ISAR4" } register += { "ID_ISAR5", "CCSIDR", "CLIDR", "AIDR", "CSSELR" } register += { "VPIDR", "VMPIDR", "SCTLR", "ACTLR", "CPACR", "SCR" } register += { "SDER", "NSACR", "HSCTLR", "HACTLR", "HCR", "HDCR" } register += { "HCPTR", "HSTR", "HACR", "TTBR0", "TTBR1", "TTBCR" } register += { "HTCR", "VTCR", "HTTBR", "VTTBR", "DACR", "DFSR" } register += { "IFSR", "ADFSR", "AIFSR", "HADFSR", "HAIFSR", "HSR" } register += { "DFAR", "IFAR", "HDFAR", "HIFAR", "HPFAR", "ICIALLUIS" } register += { "BPIALLIS", "PAR32", "PAR64", "ICIALLU", "ICIMVAU", "CP15ISB" } register += { "BPIALL", "BPIMVA", "DCIMVAC", "DCISW", "ATS1CPR" } register += { "ATS1CPW", "ATS1CUR", "ATS1CUW", "ATS12NSOPR" } register += { "ATS12NSOPW", "ATS12NSOUR", "ATS12NSOUW", "DCCMVAC" } register += { "DCCSW", "CP15DSB", "CP15DMB", "DCCMVAU", "DCCIMVAC" } register += { "DCCISW", "ATS1HR", "ATS1HW", "TLBIALLIS", "TLBIMVAIS" } register += { "TLBIASIDIS", "TLBIMVAAIS", "TLBIALL", "TLBIMVA" } register += { "TLBIASID", "TLBIMVAA", "TLBIALLHIS", "TLBIMVAHIS" } register += { "TLBIALLNSNHIS", "TLBIALLH", "TLBIMVAH", "TLBIALLNSNH" } register += { "PMCR", "PMCNTENSET", "PMCNTENCLR", "PMOVSR", "PMSWINC" } register += { "PMSELR", "PMCCNTR", "PMXEVTYPER", "PMXEVCNTR" } register += { "PMUSERENR", "PMINTENSET", "PMINTENCLR", "PMOVSSET" } register += { "L2CTLR", "L2ECTLR", "PRRR", "NMRR", "MAIR0", "MAIR1", "AMAIR0", "AMAIR1" } register += { "HMAIR0", "HMAIR1", "HAMAIR0", "HAMAIR1", "VBAR" } register += { "MVBAR", "ISR", "HVBAR", "FCSEIDR", "CONTEXTIDR" } register += { "TPIDRURW", "TPIDRURO", "TPIDRPRW", "HTPIDR", "CNTFRQ" } register += { "CNTPCT", "CNTKCTL", "CNTP_TVAL", "CNTP_CTL" } register += { "CNTV_TVAL", "CNTV_CTL", "CNTVCT", "CNTP_CVAL" } register += { "CNTV_CVAL", "CNTVOFF", "CNTHCTL", "CNTHP_TVAL" } register += { "CNTHP_CTL", "CNTHP_CVAL" } } cp15_c15 { sn = "CP15 C15" register += { "IL1DATA0", "IL1DATA1", "IL1DATA2", "DL1DATA0" } register += { "DL1DATA1", "DL1DATA2", "DL1DATA3", "RAMINDEX" } register += { "L2ACTLR", "L2PFR", "ACTLR2", "CPUMERRSR", "L2MERRSR" } register += { "CBAR" } } Thumb2EE { sn = "Thumb2EE" register += { "TEECR", "TEEHBR" } } Jazelle { sn = "Jazelle" register += { "JIDR", "JOSCR", "JMCR" } } } %endif # (_TIMEMACHINE != 1) && !defined(VXWORKS_OSE_CHORUS_INTEGRITY_UNIX)