# ARM v7M NVIC memory mapped registers

# General information
general {
    version = 3
}

enum {
    "WRITEONLY_enum" {
        "*** Write only ***" {value=0}
    }
     "CANTREAD_enum" {
        "*** Cannot Read ***" {value=0}
    }
}

#Bitfield definitions

bitfield{

"ictr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..5" 
 	type = "binary" }
"INTLINESNUM"{
	desc = "Total number of interrupt lines in groups of 32";
	loc = "4..0" 
	type = "binary" }
}



"stcsr_bitfield" {
"COUNTFLAG"{
	desc = "Returns 1 if timer counted to 0 since last time this was read. Clears on read by application.";
	loc = "16" 
	type = "binary" }
"CLKSOURCE"{
	desc = "0 = external reference clock.";
	loc = "2" 
	type = "binary" }
"TICKINT"{
	desc = "1 = counting down to 0 pends the SysTick handler.";
	loc = "1" 
	type = "binary" }
"ENABLE"{
	desc = "1 = counter operates in a multi-shot way.";
	loc = "0" 
	type = "binary" }
}



"strvr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "24..31" 
 	type = "binary" }
"RELOAD"{
	desc = "Value to load into the SysTick Current Value Register when the counter reaches 0.";
	loc = "23..0" 
	type = "binary" }
}



"stcurvr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..24" 
 	type = "binary" }
"CURRENT"{
	desc = "Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care.";
	loc = "23..0" 
	type = "binary" }
}



"stcalvr_bitfield" {
"NOREF"{
	desc = "1 = the reference clock is not provided.";
	loc = "31" 
	type = "binary" }
"SKEW"{
	desc = "1 = the calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.";
	loc = "30" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "29..24" 
 	type = "binary" }
"TENMS"{
	desc = "This value is the Reload value to use for 10ms timing. Depending on the value of SKEW, this might be exactly 10ms or might be the closest value.";
	loc = "23..0" 
	type = "binary" }
}



"intseten_bitfield" {
"SETENA"{
	desc = "Interrupt set enable bits. ";
	loc = "31..0" 
	type = "binary" }
}



"intclren_bitfield" {
"CLRENA"{
	desc = "Interrupt clear-enable bits.";
	loc = "31..0" 
	type = "binary" }
}



"intsetp_bitfield" {
"SETPEND"{
	desc = "Interrupt set-pending bits";
	loc = "31..0" 
	type = "binary" }
}



"intclrp_bitfield" {
"CLRPEND"{
	desc = "Interrupt clear-pending bits";
	loc = "31..0" 
	type = "binary" }
}



"activebit_bitfield" {
"ACTIVE"{
	desc = "Interrupt active flags";
	loc = "31..0" 
	type = "binary" }
}



"intpriority_bitfield" {
"PRI_n"{
	desc = "Priority of interrupt n";
	loc = "7..0" 
	type = "binary" }
}



"cpuid_bitfield" {
"IMPLEMENTER"{
	desc = "Implementer code. ARM is 0x41";
	loc = "31..24" 
	type = "binary" }
"VARIANT"{
	desc = "Implementation defined variant number.";
	loc = "23..20" 
	type = "binary" }
"Constant"{
	desc = "Reads as 0xF";
	loc = "19..16" 
	type = "binary" }
"PARTNO"{
	desc = "Number of processor within family";
	loc = "15..4" 
	type = "binary" }
"REVISION"{
	desc = "Implementation defined revision number.";
	loc = "3..0" 
	type = "binary" }
}



"icsr_bitfield" {
"NMIPENDSET"{
	desc = "Set pending NMI bit";
	loc = "31" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "30..29" 
 	type = "binary" }
"PENDSVSET"{
	desc = "Set pending pendSV bit";
	loc = "28" 
	type = "binary" }
"PENDSVCLR"{
	desc = "Clear pending pendSV bit";
	loc = "27" 
	type = "binary" }
"PENDSTSET"{
	desc = "Set a pending SysTick bit";
	loc = "26" 
	type = "binary" }
"PENDSTCLR"{
	desc = "Clear pending SysTick bit";
	loc = "25" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "24" 
	type = "binary" }
"ISRPREEMPT"{
	desc = "You must only use this at debug time. ";
	loc = "23" 
	type = "binary" }
"ISRPENDING"{
	desc = "Interrupt pending flag. ";
	loc = "22" 
	type = "binary" }
"VECTPENDING"{
	desc = "Pending ISR number field. ";
	loc = "21..12" 
	type = "binary" }
"RETTOBASE"{
	desc = "This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set";
	loc = "11" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "10" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "9" 
	type = "binary" }
"VECTACTIVE"{
	desc = "Active ISR number field.";
	loc = "8..0" 
	type = "binary" }
}



"vtor_bitfield" {
"TBLBASE"{
	desc = "Table base is in Code (0) or RAM (1)";
	loc = "29" 
	type = "binary" }
"TBLOFF"{
	desc = "Vector table base offset field. ";
	loc = "31..7" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "6..0" 
 	type = "binary" }
}



"aircr_bitfield" {
"VECTKEY"{
	desc = "Register key. Writing to this register requires 0x5FA in the VECTKEY field. ";
	loc = "31..16" 
	type = "binary" }
"VECTKEYSTAT"{
	desc = "Reads as 0xFA05.";
	loc = "31..16" 
	type = "binary" }
"ENDIANESS"{
	desc = "Data endianness bit";
	loc = "15" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "14..11" 
 	type = "binary" }
"PRIGROUP"{
	desc = "Interrupt priority grouping field";
	loc = "10..8" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "7..3" 
 	type = "binary" }
"SYSRESETREQ"{
	desc = "Causes a signal to be asserted to the outer system that indicates a reset is requested.";
	loc = "2" 
	type = "binary" }
"VECTCLRACTIVE"{
	desc = "Clear active vector bit:";
	loc = "1" 
	type = "binary" }
"VECTRESET"{
	desc = "System Reset bit. Resets the system, with the exception of debug components.";
	loc = "0" 
	type = "binary" }
}



"scr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..5" 
 	type = "binary" }
"SEVONPEND"{
	desc = "When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. ";
	loc = "4" 
	type = "binary" }
"SLEEPDEEP"{
	desc = "Sleep deep bit:";
	loc = "2" 
	type = "binary" }
"SLEEPONEXIT"{
	desc = "Sleep on exit when returning from Handler mode to Thread mode";
	loc = "1" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "0" 
	type = "binary" }
}



"ccr_bitfield" {
"BP" { 
    loc="18" 
    type="binary"
    desc="Setting this bit to 1 enables branch prediction, also called program flow prediction."
}
"IC" {
    loc="17"
    type="binary"
    desc="This is a global enable bit for instruction caches. If the system does not implement any instruction caches that can be accessed by the processor at any level of the memory hierarchy, this bit is RAZ/WI."
}
"DC" {
    loc="16"
    type="binary"
    desc="This is a global enable bit for data and unified caches. If the system does not implement any data or unified caches that can be accessed by the processor at any level of the memory hierarchy, this bit is RAZ/WI."
}
"STKALIGN"{
	desc = "1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. ";
	loc = "9" 
	type = "binary" }
"BFHFNMIGN"{
	desc = "When enabled, this causes handlers running at priority -1 and -2 ";
	loc = "8" 
	type = "binary" }
"DIV_0_TRP"{
	desc = "Trap on Divide by 0. ";
	loc = "4" 
	type = "binary" }
"UNALIGN_TRP"{
	desc = "Trap for unaligned access. ";
	loc = "3" 
	type = "binary" }
"USERSETMPEND"{
	desc = "If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.";
	loc = "1" 
	type = "binary" }
"NONEBASETHRDENA"{
	desc = "When 0, default, It is only possible to enter Thread mode when returning from the last exception. ";
	loc = "0" 
	type = "binary" }
}



"shpr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..24" 
 	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "23..16" 
 	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "15..8" 
 	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "7..0" 
 	type = "binary" }
}



"shcsr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..19" 
 	type = "binary" }
"USGFAULTENA"{
	desc = "Set to 0 to disable, else 1 for enabled.";
	loc = "18" 
	type = "binary" }
"BUSFAULTENA"{
	desc = "Set to 0 to disable, else 1 for enabled.";
	loc = "17" 
	type = "binary" }
"MEMFAULTENA"{
	desc = "Set to 0 to disable, else 1 for enabled.";
	loc = "16" 
	type = "binary" }
"SVCALLPENDED"{
	desc = "Reads as 1 if SVCall is pended.";
	loc = "15" 
	type = "binary" }
"BUSFAULTPENDED"{
	desc = "Reads as 1 if BusFault is pended.";
	loc = "14" 
	type = "binary" }
"MEMFAULTPENDED"{
	desc = "Reads as 1 if MemManage is pended.";
	loc = "13" 
	type = "binary" }
"USGFAULTPENDED"{
	desc = "Read as 1 if usage fault is pended";
	loc = "12" 
	type = "binary" }
"SYSTICKACT"{
	desc = "Reads as 1 if SysTick is active.";
	loc = "11" 
	type = "binary" }
"PENDSVACT"{
	desc = "Reads as 1 if PendSV is active.";
	loc = "10" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "9" 
	type = "binary" }
"MONITORACT"{
	desc = "Reads as 1 if the Monitor is active.";
	loc = "8" 
	type = "binary" }
"SVCALLACT"{
	desc = "Reads as 1 if SVCall is active.";
	loc = "7" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "6..4" 
 	type = "binary" }
"USGFAULTACT"{
	desc = "Reads as 1 if UsageFault is active.";
	loc = "3" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "2" 
	type = "binary" }
"BUSFAULTACT"{
	desc = "Reads as 1 if BusFault is active.";
	loc = "1" 
	type = "binary" }
"MEMFAULTACT"{
	desc = "Reads as 1 if MemManage is active.";
	loc = "0" 
	type = "binary" }
}



"cfsr_bitfield" {
"DIVBYZERO"{
	desc = "When DIV_0_TRP is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs ";
	loc = "25" 
	type = "binary" }
"UNALIGNED"{
	desc = "When UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs.";
	loc = "24" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "23..20" 
 	type = "binary" }
"NOCP"{
	desc = "Attempt to use a coprocessor instruction. ";
	loc = "19" 
	type = "binary" }
"INVPC"{
	desc = "Attempt to load EXC_RETURN into PC illegally.";
	loc = "18" 
	type = "binary" }
"INVSTATE"{
	desc = "Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. ";
	loc = "17" 
	type = "binary" }
"UNDEFINSTR"{
	desc = "The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction.";
	loc = "16" 
	type = "binary" }
"BFARVALID"{
	desc = "This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. ";
	loc = "15" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "14..13" 
 	type = "binary" }
"STKERR"{
	desc = "Stacking from exception has caused one or more bus faults. ";
	loc = "12" 
	type = "binary" }
"UNSTKERR"{
	desc = "Unstack from exception return has caused one or more bus faults. ";
	loc = "11" 
	type = "binary" }
"IMPRECISERR"{
	desc = "Imprecise data bus error. ";
	loc = "10" 
	type = "binary" }
"PRECISERR"{
	desc = "Precise data bus error return.";
	loc = "9" 
	type = "binary" }
"IBUSERR"{
	desc = "Instruction bus error flag";
	loc = "8" 
	type = "binary" }
"MMARVALID"{
	desc = "Memory Manage Address Register (MMAR) address valid flag:";
	loc = "7" 
	type = "binary" }
"MSTKERR"{
	desc = "Stacking from exception has caused one or more access violations. ";
	loc = "4" 
	type = "binary" }
"MUNSTKERR"{
	desc = "Unstack from exception return has caused one or more access violations. ";
	loc = "3" 
	type = "binary" }
"DACCVIOL"{
	desc = "Data access violation flag. ";
	loc = "1" 
	type = "binary" }
"IACCVIOL"{
	desc = "Instruction access violation flag.";
	loc = "0" 
	type = "binary" }
}



"mmfsr_bitfield" {
"MMARVALID"{
	desc = "Memory Manage Address Register (MMAR) address valid flag:";
	loc = "7" 
	type = "binary" }
"MSTKERR"{
	desc = "Stacking from exception has caused one or more access violations. ";
	loc = "4" 
	type = "binary" }
"MUNSTKERR"{
	desc = "Unstack from exception return has caused one or more access violations. ";
	loc = "3" 
	type = "binary" }
"DACCVIOL"{
	desc = "Data access violation flag. ";
	loc = "1" 
	type = "binary" }
"IACCVIOL"{
	desc = "Instruction access violation flag.";
	loc = "0" 
	type = "binary" }
}



"bfsr_bitfield" {
"BFARVALID"{
	desc = "This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. ";
	loc = "7" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "6..5" 
 	type = "binary" }
"STKERR"{
	desc = "Stacking from exception has caused one or more bus faults. ";
	loc = "4" 
	type = "binary" }
"UNSTKERR"{
	desc = "Unstack from exception return has caused one or more bus faults. ";
	loc = "3" 
	type = "binary" }
"IMPRECISERR"{
	desc = "Imprecise data bus error. ";
	loc = "2" 
	type = "binary" }
"PRECISERR"{
	desc = "Precise data bus error return.";
	loc = "1" 
	type = "binary" }
"IBUSERR"{
	desc = "Instruction bus error flag";
	loc = "0" 
	type = "binary" }
}



"ufsr_bitfield" {
"DIVBYZERO"{
	desc = "When DIV_0_TRP is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs ";
	loc = "9" 
	type = "binary" }
"UNALIGNED"{
	desc = "When UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs.";
	loc = "8" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "7..4" 
 	type = "binary" }
"NOCP"{
	desc = "Attempt to use a coprocessor instruction. ";
	loc = "3" 
	type = "binary" }
"INVPC"{
	desc = "Attempt to load EXC_RETURN into PC illegally.";
	loc = "2" 
	type = "binary" }
"INVSTATE"{
	desc = "Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. ";
	loc = "1" 
	type = "binary" }
"UNDEFINSTR"{
	desc = "The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction.";
	loc = "0" 
	type = "binary" }
}



"hfsr_bitfield" {
"DEBUGEVT"{
	desc = "This bit is set if there is a fault related to debug.";
	loc = "31" 
	type = "binary" }
"FORCED"{
	desc = "Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled.";
	loc = "30" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "29..2" 
 	type = "binary" }
"VECTTBL"{
	desc = "This bit is set if there is a fault because of vector table read on exception processing ";
	loc = "1" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "0" 
	type = "binary" }
}



"dfsr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..5" 
 	type = "binary" }
"EXTERNAL"{
	desc = "External debug request flag:";
	loc = "4" 
	type = "binary" }
"VCATCH"{
	desc = "Vector catch flag:";
	loc = "3" 
	type = "binary" }
"DWTTRAP"{
	desc = "Data Watchpoint and Trace (DWT) flag:";
	loc = "2" 
	type = "binary" }
"BKPT"{
	desc = "BKPT flag:";
	loc = "1" 
	type = "binary" }
"HALTED"{
	desc = "Halt request flag:";
	loc = "0" 
	type = "binary" }
}



"mmar_bitfield" {
"ADDRESS"{
	desc = "Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt.";
	loc = "31..0" 
	type = "binary" }
}



"bfar_bitfield" {
"ADDRESS"{
	desc = "Bus fault address field. ADDRESS is the data address of a faulted load or store attempt.";
	loc = "31..0" 
	type = "binary" }
}



"afsr_bitfield" {
"IMPDEF"{
	desc = "Implementation defined. ";
	loc = "31..0" 
	type = "binary" }
}



"stir_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..9" 
 	type = "binary" }
"INTID"{
	desc = "Interrupt ID field.";
	loc = "8..0" 
	type = "binary" }
}

}


# Register definitions
register {
 ictr{
	type ="ictr_bitfield"; 
     	sn="ICTR";
	gui_tab="Processor";
	ln="Interrupt Control Type Register";
	permission="write/none";
	access="memorymapped";
	address="0xE000E004"
    }
 stcsr{
	type ="stcsr_bitfield"; 
     	sn="STCSR";
	gui_tab="Processor";
	ln="SysTick Control and Status Register";
	access="memorymapped";
	address="0xE000E010"
    }
 strvr{
	type ="strvr_bitfield"; 
     	sn="STRVR";
	gui_tab="Processor";
	ln="SysTick Reload Value Register";
	access="memorymapped";
	address="0xE000E014"
    }
 stcurvr{
	type ="stcurvr_bitfield"; 
     	sn="STCurVR";
	gui_tab="Processor";
	ln="SysTick Current Value Register";
	access="memorymapped";
	address="0xE000E018"
    }
 stcalvr{
	type ="stcalvr_bitfield"; 
     	sn="STCalVR";
	gui_tab="Processor";
	ln="SysTick Calibration Value Register";
	permission="write/none";
	access="memorymapped";
	address="0xE000E01C"
    }
 cpuid{
	type ="cpuid_bitfield"; 
     	sn="CPUID";
	gui_tab="Processor";
	ln="CPUID Base Register";
	permission="write/none";
	access="memorymapped";
	address="0xE000ED00"
    }
 icsr{
	type ="icsr_bitfield"; 
     	sn="ICSR";
	gui_tab="Processor";
	ln="Interrupt Control State Register";
	access="memorymapped";
	address="0xE000ED04"
    }
 vtor{
	type ="vtor_bitfield"; 
     	sn="VTOR";
	gui_tab="Processor";
	ln="Vector Table Offset Register";
	access="memorymapped";
	address="0xE000ED08"
    }
 aircr{
	type ="aircr_bitfield"; 
     	sn="AIRCR";
	gui_tab="Processor";
	ln="Application Interrupt/Reset Control Register";
	access="memorymapped";
	address="0xE000ED0C"
    }
 scr{
	type ="scr_bitfield"; 
     	sn="SCR";
	gui_tab="Processor";
	ln="System Control Register";
	access="memorymapped";
	address="0xE000ED10"
    }
 ccr{
	type ="ccr_bitfield"; 
     	sn="CCR";
	gui_tab="Processor";
	ln="Configuration Control Register";
	access="memorymapped";
	address="0xE000ED14"
    }
 shcsr{
	type ="shcsr_bitfield"; 
     	sn="SHCSR";
	gui_tab="Processor";
	ln="System Handler Control and State Register";
	access="memorymapped";
	address="0xE000ED24"
    }
 cfsr{
	type ="cfsr_bitfield"; 
     	sn="CFSR";
	gui_tab="Processor";
	ln="Configurable Fault Status Registers";
	access="memorymapped";
	address="0xE000ED28"
    }
 hfsr{
	type ="hfsr_bitfield"; 
     	sn="HFSR";
	gui_tab="Processor";
	ln="Hard Fault Status Register";
	access="memorymapped";
	address="0xE000ED2C"
    }
 dfsr{
	type ="dfsr_bitfield"; 
     	sn="DFSR";
	gui_tab="Processor";
	ln="Debug Fault Status Register";
	access="memorymapped";
	address="0xE000ED30"
    }
 mmar{
	type ="mmar_bitfield"; 
     	sn="MMAR";
	gui_tab="Processor";
	ln="Mem Manage Address Register";
	access="memorymapped";
	address="0xE000ED34"
    }
 bfar{
	type ="bfar_bitfield"; 
     	sn="BFAR";
	gui_tab="Processor";
	ln="Bus Fault Address Register";
	access="memorymapped";
	address="0xE000ED38"
    }
 stir{
	type ="stir_bitfield"; 
     	sn="STIR";
	gui_tab="Processor";
	ln="Software Trigger Interrupt Register";
	type="WRITEONLY_enum";
	permission="read/none";
	access="memorymapped";
	address="0xE000EF00"
    }
 irq0to31ser {
	type ="intseten_bitfield"; 
     	sn="IRQ0to31SER";
	gui_tab="Processor";
	ln="IRQ 0 to 31 Set Enable Register";
	access="memorymapped";
	address="0xE000E100"
    }
 irq32to63ser {
	type ="intseten_bitfield"; 
     	sn="IRQ32to63SER";
	gui_tab="Processor";
	ln="IRQ 32 to 63 Set Enable Register";
	access="memorymapped";
	address="0xE000E104"
    }
 irq64to95ser {
	type ="intseten_bitfield"; 
     	sn="IRQ64to95SER";
	gui_tab="Processor";
	ln="IRQ 64 to 95 Set Enable Register";
	access="memorymapped";
	address="0xE000E108"
    }
 irq96to127ser {
	type ="intseten_bitfield"; 
     	sn="IRQ96to127SER";
	gui_tab="Processor";
	ln="IRQ 96 to 127 Set Enable Register";
	access="memorymapped";
	address="0xE000E10C"
    }
 irq128to159ser {
	type ="intseten_bitfield"; 
     	sn="IRQ128to159SER";
	gui_tab="Processor";
	ln="IRQ 128 to 159 Set Enable Register";
	access="memorymapped";
	address="0xE000E110"
    }
 irq160to191ser {
	type ="intseten_bitfield"; 
     	sn="IRQ160to191SER";
	gui_tab="Processor";
	ln="IRQ 160 to 191 Set Enable Register";
	access="memorymapped";
	address="0xE000E114"
    }
 irq192to223ser {
	type ="intseten_bitfield"; 
     	sn="IRQ192to223SER";
	gui_tab="Processor";
	ln="IRQ 192 to 223 Set Enable Register";
	access="memorymapped";
	address="0xE000E118"
    }
 irq224to239ser {
	type ="intseten_bitfield"; 
     	sn="IRQ224to239SER";
	gui_tab="Processor";
	ln="IRQ 224 to 239 Set Enable Register";
	access="memorymapped";
	address="0xE000E11C"
    }
 irq0to31cer {
	type ="intclren_bitfield"; 
     	sn="IRQ0to31CER";
	gui_tab="Processor";
	ln="IRQ 0 to 31 Clear Enable Register";
	access="memorymapped";
	address="0xE000E180"
    }
 irq32to63cer {
	type ="intclren_bitfield"; 
     	sn="IRQ32to63CER";
	gui_tab="Processor";
	ln="IRQ 32 to 63 Clear Enable Register";
	access="memorymapped";
	address="0xE000E184"
    }
 irq64to95cer {
	type ="intclren_bitfield"; 
     	sn="IRQ64to95CER";
	gui_tab="Processor";
	ln="IRQ 64 to 95 Clear Enable Register";
	access="memorymapped";
	address="0xE000E188"
    }
 irq96to127cer {
	type ="intclren_bitfield"; 
     	sn="IRQ96to127CER";
	gui_tab="Processor";
	ln="IRQ 96 to 127 Clear Enable Register";
	access="memorymapped";
	address="0xE000E18C"
    }
 irq128to159cer {
	type ="intclren_bitfield"; 
     	sn="IRQ128to159CER";
	gui_tab="Processor";
	ln="IRQ 128 to 159 Clear Enable Register";
	access="memorymapped";
	address="0xE000E190"
    }
 irq160to191cer {
	type ="intclren_bitfield"; 
     	sn="IRQ160to191CER";
	gui_tab="Processor";
	ln="IRQ 160 to 191 Clear Enable Register";
	access="memorymapped";
	address="0xE000E194"
    }
 irq192to223cer {
	type ="intclren_bitfield"; 
     	sn="IRQ192to223CER";
	gui_tab="Processor";
	ln="IRQ 192 to 223 Clear Enable Register";
	access="memorymapped";
	address="0xE000E198"
    }
 irq224to239cer {
	type ="intclren_bitfield"; 
     	sn="IRQ224to239SER";
	gui_tab="Processor";
	ln="IRQ 224 to 239 Clear Enable Register";
	access="memorymapped";
	address="0xE000E19C"
    }
 irq0to31spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ0to31SPR";
	gui_tab="Processor";
	ln="IRQ 0 to 31 Set Pending Register";
	access="memorymapped";
	address="0xE000E200"
    }
 irq32to63spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ32to63SPR";
	gui_tab="Processor";
	ln="IRQ 32 to 63 Set Pending Register";
	access="memorymapped";
	address="0xE000E204"
    }
 irq64to95spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ64to95SPR";
	gui_tab="Processor";
	ln="IRQ 64 to 95 Set Pending Register";
	access="memorymapped";
	address="0xE000E208"
    }
 irq96to127spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ96to127SPR";
	gui_tab="Processor";
	ln="IRQ 96 to 127 Set Pending Register";
	access="memorymapped";
	address="0xE000E20C"
    }
 irq128to159spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ128to159SPR";
	gui_tab="Processor";
	ln="IRQ 128 to 159 Set Pending Register";
	access="memorymapped";
	address="0xE000E210"
    }
 irq160to191spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ160to191SPR";
	gui_tab="Processor";
	ln="IRQ 160 to 191 Set Pending Register";
	access="memorymapped";
	address="0xE000E214"
    }
 irq192to223spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ192to223SPR";
	gui_tab="Processor";
	ln="IRQ 192 to 223 Set Pending Register";
	access="memorymapped";
	address="0xE000E218"
    }
 irq224to239spr {
	type ="intsetp_bitfield"; 
     	sn="IRQ224to239SPR";
	gui_tab="Processor";
	ln="IRQ 224 to 239 Set Pending Register";
	access="memorymapped";
	address="0xE000E21C"
    }
 irq0to31cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ0to31CPR";
	gui_tab="Processor";
	ln="IRQ 0 to 31 Clear Pending Register";
	access="memorymapped";
	address="0xE000E280"
    }
 irq32to63cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ32to63CPR";
	gui_tab="Processor";
	ln="IRQ 32 to 63 Clear Pending Register";
	access="memorymapped";
	address="0xE000E284"
    }
 irq64to95cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ64to95CPR";
	gui_tab="Processor";
	ln="IRQ 64 to 95 Clear Pending Register";
	access="memorymapped";
	address="0xE000E288"
    }
 irq96to127cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ96to127CPR";
	gui_tab="Processor";
	ln="IRQ 96 to 127 Clear Pending Register";
	access="memorymapped";
	address="0xE000E28C"
    }
 irq128to159cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ128to159CPR";
	gui_tab="Processor";
	ln="IRQ 128 to 159 Clear Pending Register";
	access="memorymapped";
	address="0xE000E290"
    }
 irq160to191cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ160to191CPR";
	gui_tab="Processor";
	ln="IRQ 160 to 191 Clear Pending Register";
	access="memorymapped";
	address="0xE000E294"
    }
 irq192to223cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ192to223CPR";
	gui_tab="Processor";
	ln="IRQ 192 to 223 Clear Pending Register";
	access="memorymapped";
	address="0xE000E298"
    }
 irq224to239cpr {
	type ="intclrp_bitfield"; 
     	sn="IRQ224to239CPR";
	gui_tab="Processor";
	ln="IRQ 224 to 239 Clear Pending Register";
	access="memorymapped";
	address="0xE000E29C"
    }
 irq0to31abr {
	type ="activebit_bitfield"; 
     	sn="IRQ0to31ABR";
	gui_tab="Processor";
	ln="IRQ 0 to 31 Active Bit Register";
	access="memorymapped";
	address="0xE000E300"
    }
 irq32to63abr {
	type ="activebit_bitfield"; 
     	sn="IRQ32to63ABR";
	gui_tab="Processor";
	ln="IRQ 32 to 63 Active Bit Register";
	access="memorymapped";
	address="0xE000E304"
    }
 irq64to95abr {
	type ="activebit_bitfield"; 
     	sn="IRQ64to95ABR";
	gui_tab="Processor";
	ln="IRQ 64 to 95 Active Bit Register";
	access="memorymapped";
	address="0xE000E308"
    }
 irq96to127abr {
	type ="activebit_bitfield"; 
     	sn="IRQ96to127ABR";
	gui_tab="Processor";
	ln="IRQ 96 to 127 Active Bit Register";
	access="memorymapped";
	address="0xE000E30C"
    }
 irq128to159abr {
	type ="activebit_bitfield"; 
     	sn="IRQ128to159ABR";
	gui_tab="Processor";
	ln="IRQ 128 to 159 Active Bit Register";
	access="memorymapped";
	address="0xE000E310"
    }
 irq160to191abr {
	type ="activebit_bitfield"; 
     	sn="IRQ160to191ABR";
	gui_tab="Processor";
	ln="IRQ 160 to 191 Active Bit Register";
	access="memorymapped";
	address="0xE000E314"
    }
 irq192to223abr {
	type ="activebit_bitfield"; 
     	sn="IRQ192to223ABR";
	gui_tab="Processor";
	ln="IRQ 192 to 223 Active Bit Register";
	access="memorymapped";
	address="0xE000E318"
    }
 irq224to239abr {
	type ="activebit_bitfield"; 
     	sn="IRQ224to239ABR";
	gui_tab="Processor";
	ln="IRQ 224 to 239 Active Bit Register";
	access="memorymapped";
	address="0xE000E31C"
    }

 irq0to3pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ0to3PR";
	gui_tab="Processor";
	ln="IRQ 0 to 3 Priority Register";
	access="memorymapped";
	address="0xE000E400"
    }
 irq4to7pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ4to7PR";
	gui_tab="Processor";
	ln="IRQ 4 to 7 Priority Register";
	access="memorymapped";
	address="0xE000E404"
    }
 irq8to11pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ8to11PR";
	gui_tab="Processor";
	ln="IRQ 8 to 11 Priority Register";
	access="memorymapped";
	address="0xE000E408"
    }
 irq12to15pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ12to15PR";
	gui_tab="Processor";
	ln="IRQ 12 to 15 Priority Register";
	access="memorymapped";
	address="0xE000E40C"
    }
 irq16to19pr {
	type ="intpriority_bitfield"; 
     	sn="IR16to19PR";
	gui_tab="Processor";
	ln="IRQ 16 to 19 Priority Register";
	access="memorymapped";
	address="0xE000E410"
    }
 irq20to23pr {
	type ="intpriority_bitfield"; 
     	sn="IR2Q0to23PR";
	gui_tab="Processor";
	ln="IRQ 20 to 23 Priority Register";
	access="memorymapped";
	address="0xE000E414"
    }
 irq24to27pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ24to27PR";
	gui_tab="Processor";
	ln="IRQ 24 to 27 Priority Register";
	access="memorymapped";
	address="0xE000E418"
    }
 irq28to31pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ28to31PR";
	gui_tab="Processor";
	ln="IRQ 28 to 31 Priority Register";
	access="memorymapped";
	address="0xE000E41C"
    }
 irq32to35pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ32to35PR";
	gui_tab="Processor";
	ln="IRQ 32 to 35 Priority Register";
	access="memorymapped";
	address="0xE000E420"
    }
 irq36to39pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ36to39PR";
	gui_tab="Processor";
	ln="IRQ 36 to 39 Priority Register";
	access="memorymapped";
	address="0xE000E424"
    }
 irq40to43pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ40to43PR";
	gui_tab="Processor";
	ln="IRQ 40 to 43 Priority Register";
	access="memorymapped";
	address="0xE000E428"
    }
 irq44to47pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ44to47PR";
	gui_tab="Processor";
	ln="IRQ 44 to 47 Priority Register";
	access="memorymapped";
	address="0xE000E42C"
    }
 irq48to51pr {
	type ="intpriority_bitfield"; 
     	sn="IR480to51PR";
	gui_tab="Processor";
	ln="IRQ 48 to 51 Priority Register";
	access="memorymapped";
	address="0xE000E430"
    }
 irq52to55pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ52to55PR";
	gui_tab="Processor";
	ln="IRQ 52 to 55 Priority Register";
	access="memorymapped";
	address="0xE000E434"
    }
 irq56to59pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ56to59PR";
	gui_tab="Processor";
	ln="IRQ 56 to 59 Priority Register";
	access="memorymapped";
	address="0xE000E438"
    }
 irq60to63pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ60to63PR";
	gui_tab="Processor";
	ln="IRQ 60 to 63 Priority Register";
	access="memorymapped";
	address="0xE000E43C"
    }
 irq64to67pr {
	type ="intpriority_bitfield"; 
     	sn="IR64to67PR";
	gui_tab="Processor";
	ln="IRQ 64 to 67 Priority Register";
	access="memorymapped";
	address="0xE000E440"
    }
 irq68to71pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ68to71PR";
	gui_tab="Processor";
	ln="IRQ 68 to 71 Priority Register";
	access="memorymapped";
	address="0xE000E444"
    }
 irq72to75pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ72to75PR";
	gui_tab="Processor";
	ln="IRQ 72 to 75 Priority Register";
	access="memorymapped";
	address="0xE000E448"
    }
 irq76to79pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ76to79PR";
	gui_tab="Processor";
	ln="IRQ 76 to 79 Priority Register";
	access="memorymapped";
	address="0xE000E44C"
    }
 irq80to83pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ80to83PR";
	gui_tab="Processor";
	ln="IRQ 80 to 83 Priority Register";
	access="memorymapped";
	address="0xE000E450"
    }
 irq84to87pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ84to87PR";
	gui_tab="Processor";
	ln="IRQ 84 to 87 Priority Register";
	access="memorymapped";
	address="0xE000E454"
    }
 irq88to91pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ88to91PR";
	gui_tab="Processor";
	ln="IRQ 88 to 91 Priority Register";
	access="memorymapped";
	address="0xE000E458"
    }
 irq92to95pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ92to95PR";
	gui_tab="Processor";
	ln="IRQ 92 to 95 Priority Register";
	access="memorymapped";
	address="0xE000E45C"
    }
 irq96to99pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ96to99PR";
	gui_tab="Processor";
	ln="IRQ 96 to 99 Priority Register";
	access="memorymapped";
	address="0xE000E460"
    }
 irq100to103pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ100to103PR";
	gui_tab="Processor";
	ln="IRQ 100 to 103 Priority Register";
	access="memorymapped";
	address="0xE000E464"
    }
 irq104to107pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ104to107PR";
	gui_tab="Processor";
	ln="IRQ 104 to 107 Priority Register";
	access="memorymapped";
	address="0xE000E468"
    }
 irq108to111pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ108to111PR";
	gui_tab="Processor";
	ln="IRQ 108 to 111 Priority Register";
	access="memorymapped";
	address="0xE000E46C"
    }
 irq112to115pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ112to115PR";
	gui_tab="Processor";
	ln="IRQ 112 to 115 Priority Register";
	access="memorymapped";
	address="0xE000E470"
    }
 irq116to119pr {
	type ="intpriority_bitfield"; 
     	sn="IR116to119PR";
	gui_tab="Processor";
	ln="IRQ 116 to 119 Priority Register";
	access="memorymapped";
	address="0xE000E474"
    }
 irq120to123pr {
	type ="intpriority_bitfield"; 
     	sn="IR12Q0to123PR";
	gui_tab="Processor";
	ln="IRQ 120 to 123 Priority Register";
	access="memorymapped";
	address="0xE000E478"
    }
 irq124to127pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ124to127PR";
	gui_tab="Processor";
	ln="IRQ 124 to 127 Priority Register";
	access="memorymapped";
	address="0xE000E47C"
    }
 irq128to131pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ128to131PR";
	gui_tab="Processor";
	ln="IRQ 128 to 131 Priority Register";
	access="memorymapped";
	address="0xE000E480"
    }
 irq132to135pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ132to135PR";
	gui_tab="Processor";
	ln="IRQ 132 to 135 Priority Register";
	access="memorymapped";
	address="0xE000E484"
    }
 irq136to139pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ136to139PR";
	gui_tab="Processor";
	ln="IRQ 136 to 139 Priority Register";
	access="memorymapped";
	address="0xE000E488"
    }
 irq140to143pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ140to143PR";
	gui_tab="Processor";
	ln="IRQ 140 to 143 Priority Register";
	access="memorymapped";
	address="0xE000E48C"
    }
 irq144to147pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ144to147PR";
	gui_tab="Processor";
	ln="IRQ 144 to 147 Priority Register";
	access="memorymapped";
	address="0xE000E490"
    }
 irq148to151pr {
	type ="intpriority_bitfield"; 
     	sn="IR1480to151PR";
	gui_tab="Processor";
	ln="IRQ 148 to 151 Priority Register";
	access="memorymapped";
	address="0xE000E494"
    }
 irq152to155pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ152to155PR";
	gui_tab="Processor";
	ln="IRQ 152 to 155 Priority Register";
	access="memorymapped";
	address="0xE000E498"
    }
 irq156to159pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ156to159PR";
	gui_tab="Processor";
	ln="IRQ 156 to 159 Priority Register";
	access="memorymapped";
	address="0xE000E49C"
    }
 irq160to163pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ160to163PR";
	gui_tab="Processor";
	ln="IRQ 160 to 163 Priority Register";
	access="memorymapped";
	address="0xE000E4A0"
    }
 irq164to167pr {
	type ="intpriority_bitfield"; 
     	sn="IR164to167PR";
	gui_tab="Processor";
	ln="IRQ 164 to 167 Priority Register";
	access="memorymapped";
	address="0xE000E4A4"
    }
 irq168to171pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ168to171PR";
	gui_tab="Processor";
	ln="IRQ 168 to 171 Priority Register";
	access="memorymapped";
	address="0xE000E4A8"
    }
 irq172to175pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ172to175PR";
	gui_tab="Processor";
	ln="IRQ 172 to 175 Priority Register";
	access="memorymapped";
	address="0xE000E4AC"
    }
 irq176to179pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ176to179PR";
	gui_tab="Processor";
	ln="IRQ 176 to 179 Priority Register";
	access="memorymapped";
	address="0xE000E4B0"
    }
 irq180to183pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ180to183PR";
	gui_tab="Processor";
	ln="IRQ 180 to 183 Priority Register";
	access="memorymapped";
	address="0xE000E4B4"
    }
 irq184to187pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ184to187PR";
	gui_tab="Processor";
	ln="IRQ 184 to 187 Priority Register";
	access="memorymapped";
	address="0xE000E4B8"
    }
 irq188to191pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ188to191PR";
	gui_tab="Processor";
	ln="IRQ 188 to 191 Priority Register";
	access="memorymapped";
	address="0xE000E4BC"
    }
 irq192to195pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ192to195PR";
	gui_tab="Processor";
	ln="IRQ 192 to 195 Priority Register";
	access="memorymapped";
	address="0xE000E4C0"
    }
 irq196to199pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ196to199PR";
	gui_tab="Processor";
	ln="IRQ 196 to 199 Priority Register";
	access="memorymapped";
	address="0xE000E4C4"
    }
 irq200to203pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ200to203PR";
	gui_tab="Processor";
	ln="IRQ 200 to 203 Priority Register";
	access="memorymapped";
	address="0xE000E4C8"
    }
 irq204to207pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ204to207PR";
	gui_tab="Processor";
	ln="IRQ 204 to 207 Priority Register";
	access="memorymapped";
	address="0xE000E4CC"
    }
 irq208to211pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ208to211PR";
	gui_tab="Processor";
	ln="IRQ 208 to 211 Priority Register";
	access="memorymapped";
	address="0xE000E4D0"
    }
 irq212to215pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ212to215PR";
	gui_tab="Processor";
	ln="IRQ 212 to 215 Priority Register";
	access="memorymapped";
	address="0xE000E4D4"
    }
 irq216to219pr {
	type ="intpriority_bitfield"; 
     	sn="IR216to219PR";
	gui_tab="Processor";
	ln="IRQ 216 to 219 Priority Register";
	access="memorymapped";
	address="0xE000E4D8"
    }
 irq220to223pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ220to223PR";
	gui_tab="Processor";
	ln="IRQ 220 to 223 Priority Register";
	access="memorymapped";
	address="0xE000E4DC"
    }
 irq224to227pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ224to227PR";
	gui_tab="Processor";
	ln="IRQ 224 to 227 Priority Register";
	access="memorymapped";
	address="0xE000E4E0"
    }
 irq228to231pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ228to231PR";
	gui_tab="Processor";
	ln="IRQ 228 to 231 Priority Register";
	access="memorymapped";
	address="0xE000E4E4"
    }
 irq232to235pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ232to235PR";
	gui_tab="Processor";
	ln="IRQ 232 to 235 Priority Register";
	access="memorymapped";
	address="0xE000E4E8"
    }
 irq236to239pr {
	type ="intpriority_bitfield"; 
     	sn="IRQ236to239PR";
	gui_tab="Processor";
	ln="IRQ 236 to 239 Priority Register";
	access="memorymapped";
	address="0xE000E4EC"
    }

 sh4to7pr {
	type ="shpr_bitfield"; 
    	sn="SH4TO7PR";
	gui_tab="Processor";
	ln="System Handlers 4-7 Priority Register";
	access="memorymapped";
	address="0xE000ED18";
    }
 sh8to11pr {
	type ="shpr_bitfield"; 
    	sn="SH8TO11PR";
	gui_tab="Processor";
	ln="System Handlers 8 to 11 Priority Register";
	access="memorymapped";
	address="0xE000ED1C";
    }
 sh12to15pr {
	type ="shpr_bitfield"; 
    	sn="SH12TO15PR";
	gui_tab="Processor";
	ln="System Handlers 12 to 15 Priority Register";
	access="memorymapped";
	address="0xE000ED20";
    }
 afsr {
	type ="afsr_bitfield"; 
    	sn="AFSR";
	gui_tab="Processor";
	ln="Auxiliary Fault Status Register";
	access="memorymapped";
	address="0xE000ED3C";
    }
 pfr0 {
    	sn="PFR0";
	gui_tab="Processor";
	ln="Processor Feature Register 0";
	access="memorymapped";
	address="0xE000ED40";
    }
 pfr1 {
    	sn="PFR1";
	gui_tab="Processor";
	ln="Processor Feature Register 1";
	access="memorymapped";
	address="0xE000ED44";
    }
 dfr0 {
    	sn="DFR0";
	gui_tab="Processor";
	ln="Debug Feature Register 0";
	access="memorymapped";
	address="0xE000ED48";
    }
 afr0 {
    	sn="AFR0";
	gui_tab="Processor";
	ln="Auxiliary Feature Register 0";
	access="memorymapped";
	address="0xE000ED4C";
    }
 mmfr0 {
    	sn="MMFR0";
	gui_tab="Processor";
	ln="Memory Model Feature Register 0";
	access="memorymapped";
	address="0xE000ED50";
    }
 mmfr1 {
    	sn="MMFR1";
	gui_tab="Processor";
	ln="Memory Model Feature Register 1";
	access="memorymapped";
	address="0xE000ED54";
    }
 mmfr2 {
    	sn="MMFR2";
	gui_tab="Processor";
	ln="Memory Model Feature Register 2";
	access="memorymapped";
	address="0xE000ED58";
    }
 mmfr3 {
    	sn="MMFR3";
	gui_tab="Processor";
	ln="Memory Model Feature Register 3";
	access="memorymapped";
	address="0xE000ED5C";
    }
 isar0 {
    	sn="ISAR0";
	gui_tab="Processor";
	ln="ISA Feature Register 0";
	access="memorymapped";
	address="0xE000ED60";
    }
 isar1 {
    	sn="ISAR1";
	gui_tab="Processor";
	ln="ISA Feature Register 1";
	access="memorymapped";
	address="0xE000ED64";
    }
 isar2 {
    	sn="ISAR2";
	gui_tab="Processor";
	ln="ISA Feature Register 2";
	access="memorymapped";
	address="0xE000ED68";
    }
 isar3 {
    	sn="ISAR3";
	gui_tab="Processor";
	ln="ISA Feature Register 3";
	access="memorymapped";
	address="0xE000ED6C";
    }
 isar4 {
    	sn="ISAR4";
	gui_tab="Processor";
	ln="ISA Feature Register 4";
	access="memorymapped";
	address="0xE000ED70";
    }
 pid4 {
    	sn="PID4";
	gui_tab="Processor";
	ln="Peripheral Identification Register 4";
	access="memorymapped";
	address="0xE000EFD0";
    }
 pid5 {
    	sn="PID5";
	gui_tab="Processor";
	ln="Peripheral Identification Register 5";
	access="memorymapped";
	address="0xE000EFD4";
    }
 pid6 {
    	sn="PID6";
	gui_tab="Processor";
	ln="Peripheral Identification Register 6";
	access="memorymapped";
	address="0xE000EFD8";
    }
 pid7 {
    	sn="PID7";
	gui_tab="Processor";
	ln="Peripheral Identification Register 7";
	access="memorymapped";
	address="0xE000EFDC";
    }
 pid0 {
    	sn="PID0";
	gui_tab="Processor";
	ln="Peripheral Identification Register 0";
	access="memorymapped";
	address="0xE000EFE0";
    }
 pid1 {
    	sn="PID1";
	gui_tab="Processor";
	ln="Peripheral Identification Register 1";
	access="memorymapped";
	address="0xE000EFE4";
    }
 pid2 {
    	sn="PID2";
	gui_tab="Processor";
	ln="Peripheral Identification Register 2";
	access="memorymapped";
	address="0xE000EFE8";
    }
 pid3 {
    	sn="PID3";
	gui_tab="Processor";
	ln="Peripheral Identification Register 3";
	access="memorymapped";
	address="0xE000EFEC";
    }
 cid0 {
    	sn="CID0";
	gui_tab="Processor";
	ln="Component Identification Register 0";
	access="memorymapped";
	address="0xE000EFF0";
    }
 cid1 {
    	sn="CID1";
	gui_tab="Processor";
	ln="Component Identification Register 1";
	access="memorymapped";
	address="0xE000EFF4";
    }
 cid2 {
    	sn="CID2";
	gui_tab="Processor";
	ln="Component Identification Register 2";
	access="memorymapped";
	address="0xE000EFF8";
    }
 cid3 {
    	sn="CID3";
	gui_tab="Processor";
	ln="Component Identification Register 3";
	access="memorymapped";
	address="0xE000EFFC";
    }
    
}

# Group definitions
group {
    nvic {
        sn = "NVIC"
        ln = "NVIC Control Registers"
	register += { "ictr","cpuid","icsr","vtor","aircr","scr","ccr" }
	register += { "shcsr","cfsr","hfsr","dfsr","mmar","bfar","stir" }
	register += {"irq0to31ser","irq32to63ser","irq64to95ser","irq96to127ser","irq128to159ser","irq160to191ser","irq192to223ser","irq224to239ser"}
    	register += {"irq0to31cer","irq32to63cer","irq64to95cer","irq96to127cer","irq128to159cer","irq160to191cer","irq192to223cer","irq224to239cer"}
    	register += {"irq0to31spr","irq32to63spr","irq64to95spr","irq96to127spr","irq128to159spr","irq160to191spr","irq192to223spr","irq224to239spr"}
    	register += {"irq0to31cpr","irq32to63cpr","irq64to95cpr","irq96to127cpr","irq128to159cpr","irq160to191cpr","irq192to223cpr","irq224to239cpr"}
    	register += {"irq0to31abr","irq32to63abr","irq64to95abr","irq96to127abr","irq128to159abr","irq160to191abr","irq192to223abr","irq224to239abr"}
	register += {"irq0to3pr","irq4to7pr","irq8to11pr","irq12to15pr","irq16to19pr","irq20to23pr","irq24to27pr","irq28to31pr"}
	register += {"irq32to35pr","irq36to39pr","irq40to43pr","irq44to47pr","irq48to51pr","irq52to55pr","irq56to59pr","irq60to63pr"}
	register += {"irq64to67pr","irq68to71pr","irq72to75pr","irq76to79pr","irq80to83pr","irq84to87pr","irq88to91pr","irq92to95pr"}
	register += {"irq96to99pr","irq100to103pr","irq104to107pr","irq108to111pr","irq112to115pr","irq116to119pr","irq120to123pr","irq124to127pr"}
	register += {"irq128to131pr","irq132to135pr","irq136to139pr","irq140to143pr","irq144to147pr","irq148to151pr","irq152to155pr","irq156to159pr"}
	register += {"irq160to163pr","irq164to167pr","irq168to171pr","irq172to175pr","irq176to179pr","irq180to183pr","irq184to187pr","irq188to191pr"}
	register += {"irq192to195pr","irq196to199pr","irq200to203pr","irq204to207pr","irq208to211pr","irq212to215pr","irq216to219pr","irq220to223pr"}
	register += {"irq224to227pr","irq228to231pr","irq232to235pr","irq236to239pr"}
	register += {"sh4to7pr","sh8to11pr","sh12to15pr"}
	register += {"afsr","pfr0","pfr1","dfr0","afr0"}   
 	register += {"mmfr0","mmfr1","mmfr2","mmfr3","isar0","isar1","isar2","isar3","isar4"}
	register += {"pid4","pid5","pid6","pid7","pid0","pid1","pid2","pid3","cid0","cid1","cid2","cid3"}
    }
    systick {
        sn = "SysTick"
        ln = "SysTick Registers"
	register += { "stcsr","strvr","stcurvr","stcalvr" }
    }
}