# Register definitions

bitfield{

"MPUtype_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..24" 
 	type = "binary" }
"IREGION"{
	desc = "Because the processor core uses only a unified MPU, IREGION always contains 0x00.";
	loc = "23..16" 
	type = "binary" }
"DREGION"{
	desc = "Number of supported MPU regions field. ";
	loc = "15..8" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "7..0" 
 	type = "binary" }
"SEPARATE"{
	desc = "Because the processor core uses only a unified MPU, SEPARATE is always 0.";
	loc = "0" 
	type = "binary" }
}



"MPUcontrol_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..2" 
 	type = "binary" }
"PRIVDEFENA"{
	desc = "This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. ";
	loc = "2" 
	type = "binary" }
"HFNMIENA"{
	desc = "This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers.";
	loc = "1" 
	type = "binary" }
"ENABLE"{
	desc = "MPU enable bit";
	loc = "0" 
	type = "binary" }
}



"MPURegionNum_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..8" 
 	type = "binary" }
"REGION"{
	desc = "Region select field.";
	loc = "7..0" 
	type = "binary" }
}



"MPURegionBaseAdd_bitfield" {
"ADDR"{
	desc = "Region base address field. ";
	loc = "31..5" 
	type = "binary" }
"VALID"{
	desc = "MPU Region Number valid bit";
	loc = "4" 
	type = "binary" }
"REGION"{
	desc = "MPU region override field.";
	loc = "3..0" 
	type = "binary" }
}



"MPURegionAttr_bitfield" {
"RESERVED"{
 	desc = "RESERVED";
 	loc = "31..29" 
 	type = "binary" }
"XN"{
	desc = "Instruction access disable bit";
	loc = "28" 
	type = "binary" }
"RESERVED"{
	desc = "RESERVED";
	loc = "27" 
	type = "binary" }
"AP"{
	desc = "Data access permission field";
	loc = "26..24" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "23..22" 
 	type = "binary" }
"TEX"{
	desc = "Type extension field.";
	loc = "21..19" 
	type = "binary" }
"S"{
	desc = "Shareable bit:";
	loc = "18" 
	type = "binary" }
"C"{
	desc = "Cacheable bit:";
	loc = "17" 
	type = "binary" }
"B"{
	desc = "Bufferable bit:";
	loc = "16" 
	type = "binary" }
"SRD"{
	desc = "Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region.";
	loc = "15..8" 
	type = "binary" }
"RESERVED"{
 	desc = "RESERVED";
 	loc = "7..6" 
 	type = "binary" }
"SIZE"{
	desc = "MPU Protection Region Size Field. See Table 9-7.";
	loc = "5..1" 
	type = "binary" }
"ENABLE"{
	desc = "Region enable bit.";
	loc = "0" 
	type = "binary" }
}

}

register {
 MPU_TYPE { gui_tab = "Processor"; access = "memorymapped"; address = "0xe000ed90" ; type = "MPUtype_bitfield"          }

%if (pvr_value0 & 0xff00) == 0x0000
 # There is no MPU, but provide these registers as hidden for compatability
 # with older GRDs that always included them.
 MPU_CTRL { gui_tab = "Processor"; hide=true; access = "memorymapped"; address = "0xe000ed94" ; type = "MPUcontrol_bitfield"       }
 MPU_RNR  { gui_tab = "Processor"; hide=true; access = "memorymapped"; address = "0xe000ed98" ; type = "MPURegionNum_bitfield"     }
 MPU_RBAR { gui_tab = "Processor"; hide=true; access = "memorymapped"; address = "0xe000ed9c" ; type = "MPURegionBaseAdd_bitfield" }
 MPU_RASR { gui_tab = "Processor"; hide=true; access = "memorymapped"; address = "0xe000eda0" ; type = "MPURegionAttr_bitfield"    }
%else
 MPU_CTRL { gui_tab = "Processor"; access = "memorymapped"; address = "0xe000ed94" ; type = "MPUcontrol_bitfield"       }
 MPU_RNR  { gui_tab = "Processor"; access = "memorymapped"; address = "0xe000ed98" ; type = "MPURegionNum_bitfield"     }
 MPU_RBAR { gui_tab = "Processor"; access = "memorymapped"; address = "0xe000ed9c" ; type = "MPURegionBaseAdd_bitfield" }
 MPU_RASR { gui_tab = "Processor"; access = "memorymapped"; address = "0xe000eda0" ; type = "MPURegionAttr_bitfield"    }
%endif

%if (pvr_value0 & 0xff00) >= 0x0100
 MPU_RBAR_0 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "0"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_0 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "0"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0200
 MPU_RBAR_1 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "1"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_1 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "1"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0300
 MPU_RBAR_2 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "2"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_2 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "2"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0400
 MPU_RBAR_3 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "3"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_3 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "3"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0500
 MPU_RBAR_4 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "4"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_4 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "4"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0600
 MPU_RBAR_5 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "5"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_5 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "5"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0700
 MPU_RBAR_6 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "6"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_6 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "6"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0800
 MPU_RBAR_7 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "7"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_7 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "7"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0900
 MPU_RBAR_8 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "8"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_8 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "8"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0a00
 MPU_RBAR_9 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "9"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_9 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "9"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0b00
 MPU_RBAR_10 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "10"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_10 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "10"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0c00
 MPU_RBAR_11 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "11"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_11 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "11"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0d00
 MPU_RBAR_12 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "12"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_12 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "12"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0e00
 MPU_RBAR_13 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "13"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_13 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "13"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x0f00
 MPU_RBAR_14 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "14"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_14 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "14"; type="MPURegionAttr_bitfield"    }
%endif
%if (pvr_value0 & 0xff00) >= 0x1000
 MPU_RBAR_15 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RBAR"; address = "15"; type="MPURegionBaseAdd_bitfield" }
 MPU_RASR_15 { gui_tab="Processor"; access="indirect"; address_port="MPU_RNR"; data_port="MPU_RASR"; address = "15"; type="MPURegionAttr_bitfield"    }
%endif

 # Legacy names, for compatability
 MPUtype          { access="synonym"; hide=true; address="MPU_TYPE" }
 MPUcontrol       { access="synonym"; hide=true; address="MPU_CTRL" }
 MPURegionNum     { access="synonym"; hide=true; address="MPU_RNR"  }
 MPURegionBaseAdd { access="synonym"; hide=true; address="MPU_RBAR" }
 MPURegionAttr    { access="synonym"; hide=true; address="MPU_RASR" }

 # Leave the aliases for compatability, but no need to actually display them
 MPUa1RegionBaseAddtype {sn = "MPUa1RegionBaseAddtype"; hide=true; access = "memorymapped"; address = "0xe000eda4" ; type = "MPURegionBaseAdd_bitfield"}
 MPUta1RegionAttr       {sn = "MPUta1RegionAttr";       hide=true; access = "memorymapped"; address = "0xe000eda8" ; type = "MPURegionAttr_bitfield"}
 MPUa2RegionBaseAddtype {sn = "MPUa2RegionBaseAddtype"; hide=true; access = "memorymapped"; address = "0xe000edac" ; type = "MPURegionBaseAdd_bitfield"}
 MPUta2RegionAttr       {sn = "MPUta2RegionAttr";       hide=true; access = "memorymapped"; address = "0xe000edb0" ; type = "MPURegionAttr_bitfield"}
 MPUa3RegionBaseAddtype {sn = "MPUa3RegionBaseAddtype"; hide=true; access = "memorymapped"; address = "0xe000edb4" ; type = "MPURegionBaseAdd_bitfield"}
 MPUta3RegionAttr       {sn = "MPUta3RegionAttr";       hide=true; access = "memorymapped"; address = "0xe000edb8" ; type = "MPURegionAttr_bitfield"}
}

# Group definitions
group {
    v7m_mpu {
        sn = "MPU"
	register += { "MPU_TYPE" }
%if (pvr_value0 & 0xff00) != 0x0000
	register += { "MPU_CTRL", "MPU_RNR", "MPU_RBAR", "MPU_RASR" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0100
	register += { "MPU_RBAR_0", "MPU_RASR_0" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0200
	register += { "MPU_RBAR_1", "MPU_RASR_1" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0300
	register += { "MPU_RBAR_2", "MPU_RASR_2" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0400
	register += { "MPU_RBAR_3", "MPU_RASR_3" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0500
	register += { "MPU_RBAR_4", "MPU_RASR_4" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0600
	register += { "MPU_RBAR_5", "MPU_RASR_5" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0700
	register += { "MPU_RBAR_6", "MPU_RASR_6" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0800
	register += { "MPU_RBAR_7", "MPU_RASR_7" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0900
	register += { "MPU_RBAR_8", "MPU_RASR_8" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0a00
	register += { "MPU_RBAR_9", "MPU_RASR_9" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0b00
	register += { "MPU_RBAR_10", "MPU_RASR_10" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0c00
	register += { "MPU_RBAR_11", "MPU_RASR_11" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0d00
	register += { "MPU_RBAR_12", "MPU_RASR_12" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0e00
	register += { "MPU_RBAR_13", "MPU_RASR_13" }
%endif
%if (pvr_value0 & 0xff00) >= 0x0f00
	register += { "MPU_RBAR_14", "MPU_RASR_14" }
%endif
%if (pvr_value0 & 0xff00) >= 0x1000
	register += { "MPU_RBAR_15", "MPU_RASR_15" }
%endif
  }
}