# Converted with command: rdf2grd.pl -c -srs -sa arm_default.rdf

# ARM/Thumb Register Description File

##############################################################################
#
# This file contains the fundamental description of ARM registers.
#
# Take care when modifying this file, especially if you are not familiar with
# the register description file format.
#
##############################################################################

# General information
general {
    version = 3
}

# Enum definitions
enum {
    "statusMode" {
        "User" {value=16}
        "FIQ" {value=17}
        "IRQ" {value=18}
        "SVC" {value=19}
	"Monitor" {value=22}
        "Abort" {value=23}
	"Hyp" {value=26}
        "Undef" {value=27}
        "System" {value=31}
    }
    "thumbMode" {
        "ARM" {value=0}
        "Thumb" {value=1}
    }
    "FIQdisable" {
        "enabled" {value=0}
        "disabled" {value=1}
    }
    "IRQdisable" {
        "enabled" {value=0}
        "disabled" {value=1}
    }
    "abortDisable" {
        "enabled" {value=0}
        "disabled" {value=1}
    }
    "eBit" {
         "little" {value=0}
         "big" {value=1}
    }
    "itCond" {
	 "eq" {value=0}
	 "ne" {value=1}
	 "cs" {value=2}
	 "cc" {value=3}
	 "mi" {value=4}
	 "pl" {value=5}
	 "vs" {value=6}
	 "vc" {value=7}
	 "hi" {value=8}
	 "ls" {value=9}
	 "ge" {value=10}
	 "lt" {value=11}
	 "gt" {value=12}
	 "le" {value=13}
	 "al" {value=14}
	 "nv" {value=15}
    }
    "jBit" {
         "ARM/Thumb" {value=0}
         "Java" {value=1}
    }
    "qBit" {
         "none" {value=0}
         "saturated" {value=1}
    }
    "overflowBit" {
        "none" {value=0}
        "overflow" {value=1}
    }
    "carryBit" {
        "none" {value=0}
        "carry" {value=1}
    }
    "zeroBit" {
        "none" {value=0}
        "zero" {value=1}
    }
    "negativeBit" {
        "none" {value=0}
        "negative" {value=1}
    }
}

# Bitfield definitions
bitfield {
    cpsr_struct_bitfield {
        "M" {
	    loc="0..4";
	    type="statusMode"
	    desc = "Mode bits\n";
	    desc += "\n";
	    desc += "These five control bits enumerate the processor modes:\n";
	    desc += "User -       Registers PC, R14-R0, and CPSR are accessible\n";
	    desc += "FIQ -        Registers PC, R14_fiq-R8_fiq, R7-R0, CPSR, and SPSR_fiq are\n";
	    desc += "             accessible\n";
	    desc += "IRQ -        Registers PC, R14_irq-R13_irq, R12-R0, CPSR, and SPSR_irq are\n";
	    desc += "             accessible\n";
	    desc += "Supervisor - Registers PC, R14_svc-R13_svc, R12-R0, CPSR, and SPSR_svc are\n";
	    desc += "             accessible\n";
	    desc += "Abort -      Registers PC, R14_abt-R13_abt, R12-R0, CPSR, and SPSR_abt are\n";
	    desc += "             accessible\n";
	    desc += "Undefined -  Registers PC, R14_und-R13_und, R12-R0, CPSR, and SPSR_und are\n";
	    desc += "             accessible\n";
	    desc += "System -     Registers PC, R14-R0, and CPSR are accessible\n";
	}
        "T" {
	    loc="5..5";
	    type="thumbMode"
	    desc = "Thumb mode\n";
	    desc += "\n";
	    desc += "The value of this bit should be zero on ARM 3 and non-Thumb ARM 4. This bit\n";
	    desc += "controls the Thumb mode of the processor. If this bit is set on a non-Thumb\n";
	    desc += "ARM 5 processor, the next instruction will generate an Undefined Instruction\n";
	    desc += "exception.\n";
	}
        "F" {
	    loc="6..6";
	    type="FIQdisable"
	    desc = "FIQ disable\n";
	    desc += "\n";
	    desc += "This bit disables FIQ interrupts.\n";
	}
        "I" {
	    loc="7..7";
	    type="IRQdisable"
	    desc = "IRQ disable\n";
	    desc += "\n";
	    desc += "This bit disables IRQ interrupts.\n";
	}
%if (defined(V6_TARGET) || defined(V7_TARGET))
        "A" {
	    loc="8";
	    type = "abortDisable";
	    desc = "Imprecise abort bit\n";
	    desc += "\n";
	    desc += "This bit disables imprecise Data Aborts.\n";
	}
        "E" {
	    loc="9";
	    type = "eBit";
	    desc = "Data endianess bit\n";
	    desc += "\n";
	    desc += "This bit controls load/store endianness.\n";
	}
%if (_TARGET == ARM_11MP)	
	"DNM_RAZ10" { sn="DNM(RAZ)";
		      loc = "10..15"; desc = "Do Not Modify (Read As Zero)" }
%else
	"IT2" {
	    loc="10"
	    desc = "IT-Mask[2]\n";
	    desc += "\n";
	    desc += "IT[3:0] encodes the number of instructions that are\n";
	    desc += "due to be conditionally executed, and whether the condition\n";
	    desc += "for each is the base condition code or its inverse.\n";
	    desc += "All four bits are zero when no IT block is active.\n";
	}
	"IT3" {
	    loc="11"
	    desc = "IT-Mask[3]\n";
	    desc += "\n";
	    desc += "IT[3:0] encodes the number of instructions that are\n";
	    desc += "due to be conditionally executed, and whether the condition\n";
	    desc += "for each is the base condition code or its inverse.\n";
	    desc += "All four bits are zero when no IT block is active.\n";	    
	}
	"IT COND" {
	    loc="12..15";
	    type = "itCond";
	    desc = "IT-Condition\n";
	    desc += "\n";
	    desc += "Condition on which this instruction is executed,\n";
	    desc += "based on its location in the current IT-block.\n";
	}
%endif
        "GE0" {
	    loc="16";
	    desc = "Greater than or equal to\n";
	    desc += "\n";
	    desc += "Set by some of the SIMD instructions.\n";
	}
        "GE1" {
	    loc="17";
	    desc = "Greater than or equal to\n";
	    desc += "\n";
	    desc += "Set by some of the SIMD instructions.\n";
	}
        "GE2" {
	    loc="18";
	    desc = "Greater than or equal to\n";
	    desc += "\n";
	    desc += "Set by some of the SIMD instructions.\n";
	}
        "GE3" {
	    loc="19";
	    desc = "Greater than or equal to\n";
	    desc += "\n";
	    desc += "Set by some of the SIMD instructions.\n";
	}
%if (_TARGET == ARM_11MP)
	"020" { sn="0"; loc = "20" }
	"DNM_RAZ21" { sn="DNM(RAZ)";
		      loc = "21..23"; desc = "Do Not Modify (Read As Zero)" }
%endif
        "J" {
	    loc="24";
	    type = "jBit";
	    desc = "Java bit\n";
	    desc += "\n";
	    desc += "This bit set when the processor is in Java state.\n";
	}
%if (_TARGET == ARM_11MP)	
	"DNM_RAZ25" { sn="DNM(RAZ)";
		      loc = "25..26"; desc = "Do Not Modify (Read As Zero)" }
%else
	"IT0" {
	    loc="25"
	    desc = "IT-Mask[0]\n";
	    desc += "\n";
	    desc += "IT[3:0] encodes the number of instructions that are\n";
	    desc += "due to be conditionally executed, and whether the condition\n";
	    desc += "for each is the base condition code or its inverse.\n";
	    desc += "All four bits are zero when no IT block is active.\n";	    
	}
	"IT1" {
	    loc="26"
	    desc = "IT-Mask[1]\n";
	    desc += "\n";
	    desc += "IT[3:0] encodes the number of instructions that are\n";
	    desc += "due to be conditionally executed, and whether the condition\n";
	    desc += "for each is the base condition code or its inverse.\n";
	    desc += "All four bits are zero when no IT block is active.\n";	    
	}
%endif
%else
	"unused" {
	    loc="8..26"
	}
%endif
	"Q" {
	    loc="27..27";
	    type = "qBit";
	    desc = "Q flag\n";
	    desc += "\n";
	    desc += "Indicates saturation and/or overflow on enhanced DSP instructions\n";
	}
        "V" {
	    loc="28..28";
	    type="overflowBit"
	    desc = "Overflow flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an overflow occurred.\n";
	}
        "C" {
	    loc="29..29";
	    type="carryBit"
	    desc = "Carry flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation produced a carry.\n";
	}
        "Z" {
	    loc="30..30";
	    type="zeroBit"
	    desc = "Zero flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation resulted in a zero.\n";
	}
        "N" {
	    loc="31..31";
	    type="negativeBit"
	    desc = "Negative flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation produced a negative result.\n";
	}
    }
}

# Register definitions
register {
    # General Integer Registers    
    r0 {sn="R0"; address=0}
    r1 {sn="R1"; address=1}
    r2 {sn="R2"; address=2}
    r3 {sn="R3"; address=3}
    r4 {sn="R4"; address=4}
    r5 {sn="R5"; address=5}
    r6 {sn="R6"; address=6}
    r7 {sn="R7"; address=7}
    r8 {sn="R8"; address=8}
    r9 {sn="R9"; address=9}
    r10 {sn="R10"; address=10}
    fp {
	sn="FP";
	ln = "Frame Pointer";
	address=11;
	desc = "FP is a synonym for R11.";
    }
    ip {
	sn="IP";
	ln = "Intra-Procedure call scratch register";
	address=12;
	desc = "IP is a synonym for R12.";
    }
    sp {
	sn="SP";
	ln = "Stack Pointer";
	address=13;
	desc = "SP is a synonym for R13. SP holds a pointer to the stack, by convention.";
    }
    lr {
	sn="LR";
	ln = "Link Register";
	address=14;
	desc = "LR is a synonym for R14. LR stores the return address for a subroutine. On\n";
	desc = "return from a subroutine, the value in LR is copied to the program counter.\n";
	desc = "LR is also set to the exception return address when the processor hits an\n";
	desc = "exception.\n";
    }
    pc {sn="PC"; ln = "Program Counter"; address=15; type="code *"}
    sb {sn="SB"; access="synonym"; address="r9"; hide=true}
    sl {sn="SL"; access="synonym"; address="r10"; hide=true}
    r11 {sn="R11"; access="synonym"; address="fp"; hide=true}
    r12 {sn="R12"; access="synonym"; address="ip"; hide=true}
    r13 {sn="R13"; access="synonym"; address="sp"; hide=true}
    r14 {sn="R14"; access="synonym"; address="lr"; hide=true}
    r15 {sn="R15"; access="synonym"; address="pc"; hide=true}
    a1 {sn="A1"; access="synonym"; address="r0"; hide=true}
    a2 {sn="A2"; access="synonym"; address="r1"; hide=true}
    a3 {sn="A3"; access="synonym"; address="r2"; hide=true}
    a4 {sn="A4"; access="synonym"; address="r3"; hide=true}
    v1 {sn="V1"; access="synonym"; address="r4"; hide=true}
    v2 {sn="V2"; access="synonym"; address="r5"; hide=true}
    v3 {sn="V3"; access="synonym"; address="r6"; hide=true}
    v4 {sn="V4"; access="synonym"; address="r7"; hide=true}
    v5 {sn="V5"; access="synonym"; address="r8"; hide=true}
    v6 {sn="V6"; access="synonym"; address="r9"; hide=true}
    v7 {sn="V7"; access="synonym"; address="r10"; hide=true}
    result {sn="RESULT"; access="synonym"; address="r0"; hide=true}
    #cpsr_struct register
    cpsr {
	sn="CPSR";
	ln = "Current Program Status Register";
	address=40;
	type="cpsr_struct_bitfield"
    }
}

# Group definitions
group {
    general {
        sn = "General"
        ln = "General Registers"
	collapse = false
        top_level_index = 10
        register += {"r0", "r1", "r2", "r3", "r4", "r5"}
        register += {"r6", "r7", "r8", "r9", "r10", "fp"}
        register += {"ip", "sp", "lr", "pc"}
%if (!defined(V7M_TARGET) || _TARGET_OS == OS_THREADX)
        register += {"cpsr"}
%endif
    }
}