# Type definitions
enum {
    mpu_sbit {
	"Unified" { value = 0 }
	"Seperate" { value = 1 }
    }
    ana { 
	"Avilable" { value = 0 }
	"Not Avilable" { value = 1 }
    }
    cr4_ind_bit {
	"Data or Unified" { value = 0 }
	"Instruction" { value = 0 }
    }
    cr4_sd_bit {
	"AXI Decode" {value = 0}
	"AXI Encode" {value = 1}
    }
    cr4_rw_bit {
	"Read" { value = 0 }
	"Write" { value = 1 }
    }
}

bitfield {
    cr4_mpuir {
	Reserved1 { loc = "16..31" }
	MPURegions { loc="8..15"; ln = "MPU regions"; desc = "Specifies the number of MPU regions" }
	Reserved2 { loc = "1..7" }
	S { loc = "0"; type="mpu_sbit"; desc = "Specifies the type of MPU regions" }
    }
    cr4_ccsidr {
	WT { loc = "31"; type = "ana"; desc="Indicates support availability for write-through"}
	WB { loc = "30"; type = "ana"; desc="Indicates support availability for write-back"}
	RA { loc = "29"; type = "ana"; desc="Indicates support availability for read allocation"}
	WA { loc = "28"; type = "ana"; desc="Indicates support availability for write allocation"}
	NumSets { loc = "13..27"; desc="See the Cortex R4 Technical Reference Manual for the encoding of this field"}
	Associativity { loc = "3..12"; desc="See the Cortex R4 Technical Reference Manual for the encoding of this field"}
	LineSize {ln = "Line Size"; loc = "0..2"; desc="See the Cortex R4 Technical Reference Manual for the encoding of this field"}
    }
    cr4_clidr {
	SBZ { loc = "30..31" }
	LoU { loc = "27..29"; ln = "Level of Unification" }
	LoC { loc = "24..26"; ln = "Level of Coherency" }
	CL8 { loc = "21..23" }
	CL7 { loc = "18..20" }
	CL6 { loc = "15..17" }
	CL5 { loc = "12..14" }
	CL4 { loc = "9..11" }
	CL3 { loc = "6..8" }
	CL2 { loc = "3..5" }
	CL1 { loc = "0..2" }
    }
    cr4_csselr {
	Reserved { loc="4..31" }
	Level { loc="1..3" ; desc="Identifies which cache level to select"}
	InD { loc="0"; type="cr4_ind_bit"; desc="Identifies whether to select the instruction or the data/unified cache"}
    }
    cr4_dfsr {
	Reserved { loc="13..31" }
	SD { loc="12"; type="cr4_sd_bit"; desc="Determines whether the abort was caused by an AXI Slave error or AXI Decode error"}
	RW { loc="11"; type="cr4_rw_bit"; desc="Determines whether the abort was caused by a Read or a Write"}
	S { loc="10" }
	SBZ { loc="8..9"; desc="Should be Zero"}
	Domain { loc="4..7" }
	Status { loc="0..3" }
    }
    cr4_ifsr {
	Reserved1 { loc="13..31" }
	SD { loc="12"; type="cr4_sd_bit"; desc="Determines whether the abort was caused by an AXI Slave error or AXI Decode error"}
	Reserved2 { loc="11" }
	S { loc="10" }
	Reserved3 { loc="8..9" }
	Domain { loc="4..7" }
	Status { loc="0..3" }
    }
}

# Register definitions
register {
    midr {
	sn="midr"
	ln="Main ID c0"
	address=654
	type="id_bitfield"
	permission = "write/none"
    }
    ctr {
	sn="ctr"
	ln="Cache Type Register c0"
	address=683
	type="cachetype_bitfield"
	permission = "write/none"
    }
    tcmtr {
	sn="tcmtr"
	ln="TCM Status Register c0"
	address=668
	type="tcmstatus_bitfield"
	permission = "write/none"
    }
    mpuir {
	sn="mpuir"
	ln="MPU Type Register c0"
	address=663
	type="cr4_mpuir"
	permission = "write/none"
    }
    ccsidr {
	sn="ccsidr"
	ln="Current Cache Size Identification"
	address=684
	type="cr4_ccsidr"
	permission = "write/none"
    }
    clidr {
	sn="clidr"
	ln="Current Cache Level ID"
	address=685
	type="cr4_clidr"
	permission = "write/none"
    }
    csselr {
	sn="csselr"
	ln="Cache Size Selection"
	type="cr4_csselr"
	address=686
    }
    sctlr {
	sn="sctlr"
	ln="Control Register c1"
	address=652
	type="cr4_control_bitfield"
    }
    actlr {
	sn="actlr"
	ln="Auxiliary Control Register c1"
	address=653
    }
    dfsr {
	sn="dfsr"
	ln="Data Fault Status Register c5"
	address=657
	type="cr4_dfsr"
    }
    ifsr {
	sn="ifsr"
	ln="Instruction Fault Status Register c5"
	address=658
	type="cr4_ifsr"
    }
    adfsr {
	sn="adfsr"
	ln="Auxiliary Data Fault Status Register c5"
	address=659
	type="cr4_dfsr"
    }
    aifsr {
	sn="aifsr"
	ln="Auxiliary Instruction Fault Status Register c5"
	address=660
	type="cr4_ifsr"
    }
    dfar {
	sn="dfar"
	ln="Data Fault Address Register c6"
	desc="Contains the address of the data access being attempted when a Data Abort occurred."
	address=662
    }
    ifar {
	sn="ifar"
	ln="Instruction Fault Address Register c6"
	desc="Contains the address of the instruction that caused a Prefetch Abort."
	address=661
    }
    atcmrr {
	ln="ATCM Region"
	desc="Holds the base address and size of the ATCM/ITCM"
	address=670
    }
    btcmrr {
	ln="BTCM Region"
	desc="Holds the base address and size of the BTCM/DTCM"
	address=669
    }
    drbar {
	sn="drbar"
	ln="MPU Region Base Address"
	desc="Describes the base address of a region in the data or instruction memory"
	address=664
    }
    drsr {
	sn="drsr"
	ln="MPU Region Size and Enable"
	desc="Holds the size and address ranges used by a particular region, and whether that reagion is enabled."
	address=665
    }

    dracr {
	sn="dracr"
	ln="MPU Region Access Control"
	desc="Hold the region attributes and access permissions for a given memory region"
	address=666
    }

    rgnr {
	sn="rgnr"
	ln="MPU Memory Region Number"
	desc="Determines which memory region the other MPU memory region registers refer to."
	address=667
    }

    cpacr{sn = "cpacr"; address = 821} 
    contextidr   {sn = "contextidr";  address=656 }
    pmcr   { address=671 }
    pmcntenset { address=672 }
    pmcntenclr { address=673 }
    pmovsr   { address=674 }
    pmswinc { address=675 ; permission="read/none"; hide=true}
    pmselr{ address=676 }
    pmccntr   { address=677 }
    pmxevtyper{ address=678 }
    pmxevcntr   { address=679 }
    pmuserenr { address=680 }
    pmintenset { address=681 }
    pmintenclr { address=682 }

    # Compatability for old names
    id             { access="synonym"; address="midr";       hide=true; permission="write/none"; }
    cache_type     { access="synonym"; address="ctr";        hide=true; permission="write/none"; }
    tcm_status     { access="synonym"; address="tcmtr";      hide=true; permission="write/none"; }
    mpu_type       { access="synonym"; address="mpuir";      hide=true; permission="write/none"; }
    cache_size_id  { access="synonym"; address="ccsidr";     hide=true; permission="write/none"; }
    cache_level_id { access="synonym"; address="clidr";      hide=true; permission="write/none"; }
    cache_size_sel { access="synonym"; address="csselr";     hide=true; }
    control        { access="synonym"; address="sctlr";      hide=true; }
    aux_control    { access="synonym"; address="actlr";      hide=true; }
    region_base    { access="synonym"; address="drbar";      hide=true; }
    region_size    { access="synonym"; address="drsr";       hide=true; }
    region_access  { access="synonym"; address="dracr";      hide=true; }
    region_number  { access="synonym"; address="rgnr";       hide=true; }
    cp_access      { access="synonym"; address="cpacr";      hide=true; }
    processid      { access="synonym"; address="contextidr"; hide=true; }
    contextid      { access="synonym"; address="contextidr"; hide=true; }
    pmnc           { access="synonym"; address="pmcr";       hide=true; }
    cntens         { access="synonym"; address="pmcntenset"; hide=true; }
    cntenc         { access="synonym"; address="pmcntenclr"; hide=true; }
    flag           { access="synonym"; address="pmovsr";     hide=true; }
    swincr         { access="synonym"; address="pmswinc";    hide=true; permission="read/none" }
    pmnxsel        { access="synonym"; address="pmselr";     hide=true; }
    ccnt           { access="synonym"; address="pmccntr";    hide=true; }
    evtselx        { access="synonym"; address="pmxevtyper"; hide=true; }
    pmnx           { access="synonym"; address="pmxevcntr";  hide=true; }
    useren         { access="synonym"; address="pmuserenr";  hide=true; }
    intens         { access="synonym"; address="pmintenset"; hide=true; }
    intenc         { access="synonym"; address="pmintenclr"; hide=true; }
    
    # The TCM Region Registers go by many names.  The R4 and R5 Technical
    # Reference Manual use ATCM and BTCM.  The ARM Architecture Reference
    # Manual uses ITCMRR and DTCMRR.  Before ARM gave their registers short
    # names, GHS used the names itcm_region and dtcm_region.  A previous
    # version of this register file also included itcmregion and dtcmregion.
    # The TRM names are provided above, all the other names are provided as
    # aliases here.
    itcmrr      { access="synonym"; address="atcmrr"; hide=true }
    itcmregion  { access="synonym"; address="atcmrr"; hide=true }
    itcm_region { access="synonym"; address="atcmrr"; hide=true }
    dtcmrr      { access="synonym"; address="btcmrr"; hide=true }
    dtcmregion  { access="synonym"; address="btcmrr"; hide=true }
    dtcm_region { access="synonym"; address="btcmrr"; hide=true }
}


# Group definitions
group {
    cp15 {
	sn = "CP15"
	register += { "sctlr", "actlr", "midr", "contextidr" }
	register += { "dfsr", "ifsr", "adfsr", "aifsr", "ifar" }
	register += { "dfar", "mpuir", "drbar", "drsr" }
	register += { "dracr", "rgnr", "tcmtr" }
	register += { "atcmrr", "btcmrr", "cpacr", "pmcr", "pmcntenset" }
	register += { "pmcntenclr", "pmovsr", "pmswinc", "pmselr", "pmccntr" }
	register += { "pmxevtyper", "pmxevcntr", "pmuserenr", "pmintenset", "pmintenclr" }
	register += { "ctr", "ccsidr", "clidr" }
	register += { "csselr" }
    }
}