"general" {
    version = 3
}
"enum" {
    "CLKSEL_GFX_FCLK_CLKDIV_SEL_GFX_FCLK__enum" {
        "DIV1" {
            value = "0"
        }
        "DIV2" {
            value = "1"
        }
    }
    "CLKSEL_GPIO0_DBCLK_CLKSEL__enum" {
        "SEL1" {
            value = "0"
        }
        "SEL2" {
            value = "1"
        }
        "SEL3" {
            value = "2"
        }
    }
    "CLKSEL_IE_CLK_CLKSEL__enum" {
        "SEL1" {
            value = "0"
        }
        "SEL2" {
            value = "1"
        }
        "SEL3" {
            value = "2"
        }
        "SEL4" {
            value = "3"
        }
    }
    "CLKSEL_TIMER1MS_CLK_CLKSEL__enum" {
        "SEL1" {
            value = "0"
        }
        "SEL2" {
            value = "1"
        }
        "SEL3" {
            value = "2"
        }
        "SEL4" {
            value = "3"
        }
        "SEL5" {
            value = "4"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_DRIFTGUARD_EN__enum" {
        "Diasbled" {
            value = "0"
        }
        "Enabled" {
            value = "1"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_EN__enum" {
        "Reserved" {
            value = "0"
        }
        "Reserved1" {
            value = "1"
        }
        "Reserved2" {
            value = "2"
        }
        "Reserved3" {
            value = "3"
        }
        "DPLL_MN_BYP_MODE" {
            value = "4"
        }
        "DPLL_LP_BYP_MODE" {
            value = "5"
        }
        "DPLL_FR_BYP_MODE" {
            value = "6"
        }
        "DPLL_LOCK_MODE" {
            value = "7"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_LPMODE_EN__enum" {
        "DISABLED" {
            value = "0"
        }
        "ENABLED" {
            value = "1"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_RAMP_LEVEL__enum" {
        "RAMP_DISABLE" {
            value = "0"
        }
        "RAMP_ALGO1" {
            value = "1"
        }
        "RAMP_ALGO2" {
            value = "2"
        }
        "Reserved" {
            value = "3"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_RAMP_RATE__enum" {
        "REFCLKx2" {
            value = "0"
        }
        "REFCLKx4" {
            value = "1"
        }
        "REFCLKx8" {
            value = "2"
        }
        "REFCLKx16" {
            value = "3"
        }
        "REFCLKx32" {
            value = "4"
        }
        "REFCLKx64" {
            value = "5"
        }
        "REFCLKx128" {
            value = "6"
        }
        "REFCLKx512" {
            value = "7"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_REGM4XEN__enum" {
        "DISABLED" {
            value = "0"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_SSC_DOWNSPREAD__enum" {
        "FULL_SPREAD" {
            value = "0"
        }
        "LOW_SPREAD" {
            value = "1"
        }
    }
    "CM_CLKMODE_DPLL_DPLL_SSC_TYPE__enum" {
        "Triangular" {
            value = "0"
        }
        "Square" {
            value = "1"
        }
    }
    "CM_CLKMODE_DPLL_PER_DPLL_EN__enum" {
        "Reserved" {
            value = "0"
        }
        "DPLL_LP_STP_MODE" {
            value = "1"
        }
        "Reserved2" {
            value = "2"
        }
        "Reserved3" {
            value = "3"
        }
        "DPLL_MN_BYP_MODE" {
            value = "4"
        }
        "DPLL_LP_BYP_MODE" {
            value = "5"
        }
        "Reserved6" {
            value = "6"
        }
        "DPLL_LOCK_MODE" {
            value = "7"
        }
    }
    "CM_CLKOUT_CTRL_CLKOUT2DIV__enum" {
        "DIV1" {
            value = "0"
        }
        "DIV2" {
            value = "1"
        }
        "DIV3" {
            value = "2"
        }
        "DIV4" {
            value = "3"
        }
        "DIV5" {
            value = "4"
        }
        "DIV6" {
            value = "5"
        }
        "DIV7" {
            value = "6"
        }
        "DIV8" {
            value = "7"
        }
    }
    "CM_CLKOUT_CTRL_CLKOUT2SOURCE__enum" {
        "SEL0" {
            value = "0"
        }
        "SEL1" {
            value = "1"
        }
        "SEL2" {
            value = "2"
        }
        "SEL4" {
            value = "3"
        }
        "SEL5" {
            value = "4"
        }
    }
    "CM_CLKSEL_DPLL_CORE_DPLL_MULT__enum" {
        "Reserved_0" {
            value = "0"
        }
        "Reserved_1" {
            value = "1"
        }
    }
    "CM_CLKSEL_DPLL_PERIPH_DPLL_SD_DIV__enum" {
        "Reserved" {
            value = "0"
        }
        "Reserved1" {
            value = "1"
        }
    }
    "CM_CLKSEL_DPLL__DPLL_BYP_CLKSEL__enum" {
        "Sel0" {
            value = "0"
        }
        "Sel1" {
            value = "1"
        }
    }
    "CM_CLKSEL_DPLL__DPLL_MULT__enum" {
        "0" {
            value = "0"
        }
        "1" {
            value = "1"
        }
    }
    "CM_DIV_M2_DPLL_ST_DPLL_CLKOUT__enum" {
        "CLK_GATED" {
            value = "0"
        }
        "CLK_ENABLED" {
            value = "1"
        }
    }
    "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum" {
        "Reserved" {
            value = "0"
        }
    }
    "CM_D_DPLL_D_CLKO_GATE_CTRL__enum" {
        "CLK_AUTOGATE" {
            value = "0"
        }
        "CLK_ENABLE" {
            value = "1"
        }
    }
    "CM_D_DPLL_E_D_CLKO_PWDN__enum" {
        "ALWAYS_ACTIVE" {
            value = "0"
        }
        "AUTO_PWDN" {
            value = "1"
        }
    }
    "CM_D_DPLL_E_ST_D_CLKO__enum" {
        "CLK_ENABLED" {
            value = "0"
        }
        "CLK_GATED" {
            value = "1"
        }
    }
    "CM_IDLEST_DPLL_ST_DPLL_CLK__enum" {
        "DPLL_UNLOCKED" {
            value = "0"
        }
        "DPLL_LOCKED" {
            value = "1"
        }
    }
    "CM_IDLEST_DPLL_ST_MN_BYPASS__enum" {
        "NO_MNBYPASS" {
            value = "0"
        }
        "MN_BYPASS" {
            value = "1"
        }
    }
    "CM_IDLEST__enum" {
        "Func" {
            value = "0"
        }
        "Trans" {
            value = "1"
        }
        "Idle" {
            value = "2"
        }
        "Disable" {
            value = "3"
        }
    }
    "CM_MODULEMODE__enum" {
        "DISABLED" {
            value = "0"
        }
        "RESERVED_1" {
            value = "1"
        }
        "ENABLE" {
            value = "2"
        }
        "RESERVED" {
            value = "3"
        }
    }
    "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum" {
        "FCLK_DIS" {
            value = "0"
        }
        "FCLK_EN" {
            value = "1"
        }
    }
    "CM_STBYST__enum" {
        "Func" {
            value = "0"
        }
        "Standby" {
            value = "1"
        }
    }
    "CM_WKUP_CLKSTCTRL_CLKTRCTRL__enum" {
        "NO_SLEEP" {
            value = "0"
        }
        "SW_SLEEP" {
            value = "1"
        }
        "SW_WKUP" {
            value = "2"
        }
        "HW_AUTO" {
            value = "3"
        }
    }
    "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum" {
        "Inact" {
            value = "0"
        }
        "Act" {
            value = "1"
        }
    }
    "CM__CLKSTCTRL_CLKTRCTRL__enum" {
        "NO_SLEEP" {
            value = "0"
        }
        "SW_SLEEP" {
            value = "1"
        }
        "SW_WKUP" {
            value = "2"
        }
        "Reserved" {
            value = "3"
        }
    }
    "CPSW_WR_CONTROL_MMR_IDLEMODE__enum" {
        "Force-idle mode" {
            value = "0"
        }
        "No-idle mode" {
            value = "1"
        }
        "Reserved" {
            value = "2"
        }
        "Reserved" {
            value = "3"
        }
    }
    "CPSW_WR_CONTROL_MMR_STDBYMODE__enum" {
        "Force-standby mode" {
            value = "0"
        }
        "No-standby mode" {
            value = "1"
        }
        "Reserved" {
            value = "2"
        }
        "Reserved" {
            value = "3"
        }
    }
    "CS__CLK_CLKSEL__enum" {
        "SEL1" {
            value = "0"
        }
        "SEL2" {
            value = "1"
        }
    }
    "C_C_CLKSEL__CLK__enum" {
        "SEL0" {
            value = "0"
        }
        "SEL1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_AR__enum" {
        "one_shot" {
            value = "0"
        }
        "auto_rel" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_CAPT_MODE__enum" {
        "First_capt" {
            value = "0"
        }
        "Sec_capt" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_CE__enum" {
        "dsb_cmp" {
            value = "0"
        }
        "enb_cmp" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_GPO_CFG__enum" {
        "GPO_CFG_0" {
            value = "0"
        }
        "GPO_CFG_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_PRE__enum" {
        "no_prescal" {
            value = "0"
        }
        "prescal_on" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_PTV__enum" {
        "ptv" {
            value = "0"
        }
    }
    "DMTIMER1_1MS_TCLR_PT__enum" {
        "pulse" {
            value = "0"
        }
        "toggle" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_SCPWM__enum" {
        "def_low" {
            value = "0"
        }
        "def_high" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_ST__enum" {
        "cnt_stop" {
            value = "0"
        }
        "cnt_start" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TCLR_TCM__enum" {
        "no_edge" {
            value = "0"
        }
        "rise_edge" {
            value = "1"
        }
        "fall_edge" {
            value = "2"
        }
        "booth_edges" {
            value = "3"
        }
    }
    "DMTIMER1_1MS_TCLR_TRG__enum" {
        "no_trg" {
            value = "0"
        }
        "ovf_trg" {
            value = "1"
        }
        "ovf_mat_trg" {
            value = "2"
        }
        "reserved" {
            value = "3"
        }
    }
    "DMTIMER1_1MS_TIER_MAT_IT_ENA__enum" {
        "Dsb_match" {
            value = "0"
        }
        "Enb_match" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIER_OVF_IT_ENA__enum" {
        "Dsb_ovf" {
            value = "0"
        }
        "Enb_ovf" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIER_TCAR_IT_ENA__enum" {
        "Dsb_capt" {
            value = "0"
        }
        "Enb_capt" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_AutoIdle__enum" {
        "clkfree" {
            value = "0"
        }
        "clkgate" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_ClockActivity__enum" {
        "CA0" {
            value = "0"
        }
        "CA1" {
            value = "1"
        }
        "CA2" {
            value = "2"
        }
        "CA3" {
            value = "3"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_EmuFree__enum" {
        "timer_frozen" {
            value = "0"
        }
        "timer_free" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_EnaWakeup__enum" {
        "nowake" {
            value = "0"
        }
        "enbwake" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_IdleMode__enum" {
        "fidle" {
            value = "0"
        }
        "nidle" {
            value = "1"
        }
        "sidle" {
            value = "2"
        }
        "res" {
            value = "3"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG_SoftReset__enum" {
        "nmode" {
            value = "0"
        }
        "rstmode" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TISR_MAT_IT_FLAG__enum" {
        "MAT_IT_FLAG_0" {
            value = "0"
        }
        "MAT_IT_FLAG_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TISR_OVF_IT_FLAG__enum" {
        "OVF_IT_FLAG_0" {
            value = "0"
        }
        "OVF_IT_FLAG_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TISR_TCAR_IT_FLAG__enum" {
        "TCAR_IT_FLAG_0" {
            value = "0"
        }
        "TACR_IT_FLAG_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TISTAT_ResetDone__enum" {
        "rstongoing" {
            value = "0"
        }
        "rstcomp" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TSICR_POSTED__enum" {
        "POSTED_0" {
            value = "0"
        }
        "POSTED_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TSICR_SFT__enum" {
        "SFT_0" {
            value = "0"
        }
        "SFT_1" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWER_MAT_WUP_ENA__enum" {
        "DsbWupMat" {
            value = "0"
        }
        "EnbWupMat" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWER_OVF_WUP_ENA__enum" {
        "DsbWupOvf" {
            value = "0"
        }
        "EnbWupOvf" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWER_TCAR_WUP_ENA__enum" {
        "DsbWupCap" {
            value = "0"
        }
        "EnbWupCapt" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TCLR__enum" {
        "CLR_nPend" {
            value = "0"
        }
        "CLR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TCRR__enum" {
        "CRR_nPend" {
            value = "0"
        }
        "CRR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TCVR__enum" {
        "CVR_nPend" {
            value = "0"
        }
        "CVR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TLDR__enum" {
        "LDR_nPend" {
            value = "0"
        }
        "LDR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TMAR__enum" {
        "MAR_nPend" {
            value = "0"
        }
        "MAR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TNIR__enum" {
        "NIR_nPend" {
            value = "0"
        }
        "NIR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TOCR__enum" {
        "OCR_nPend" {
            value = "0"
        }
        "OCR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TOWR__enum" {
        "OWR_nPend" {
            value = "0"
        }
        "OWR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TPIR__enum" {
        "PIR_nPend" {
            value = "0"
        }
        "PIR_Pend" {
            value = "1"
        }
    }
    "DMTIMER1_1MS_TWPS_W_PEND_TTGR__enum" {
        "TGR_nPend" {
            value = "0"
        }
        "TGR_Pend" {
            value = "1"
        }
    }
    "INTC_CONTROL_NewFIQAgr__enum" {
        "nofun_w" {
            value = "0"
        }
        "NewFiq_w" {
            value = "1"
        }
    }
    "INTC_CONTROL_NewIRQAgr__enum" {
        "nofun_w" {
            value = "0"
        }
        "NewIrq_w" {
            value = "1"
        }
    }
    "INTC_IDLE_FuncIdle__enum" {
        "FuncAuto" {
            value = "0"
        }
        "FuncFree" {
            value = "1"
        }
    }
    "INTC_IDLE_Turbo__enum" {
        "SyncFree" {
            value = "0"
        }
        "SyncAuto" {
            value = "1"
        }
    }
    "INTC_ILR_FIQnIRQ__enum" {
        "IntIRQ" {
            value = "0"
        }
        "IntFIQ" {
            value = "1"
        }
    }
    "INTC_PROTECTION_Protection__enum" {
        "ProtMDis" {
            value = "0"
        }
        "ProtMEnb" {
            value = "1"
        }
    }
    "INTC_SYSCONFIG_Autoidle__enum" {
        "clkfree" {
            value = "0"
        }
        "autoClkGate" {
            value = "1"
        }
    }
    "INTC_SYSCONFIG_SoftReset__enum" {
        "always_r" {
            value = "0"
        }
        "nofun_w" {
            value = "0"
        }
        "never_r" {
            value = "1"
        }
        "rstMode_w" {
            value = "1"
        }
    }
    "INTC_SYSSTATUS_ResetDone__enum" {
        "rstOngoing" {
            value = "0"
        }
        "rstComp" {
            value = "1"
        }
    }
    "MAILBOX0_FIFOSTATUS_FIFOFULLMBM__enum" {
        "NotFull" {
            value = "0"
        }
        "Full" {
            value = "1"
        }
    }
    "MAILBOX0_IRQ_NStatusUuMB__enum" {
        "NoAction" {
            value = "0"
        }
        "NoEvent" {
            value = "0"
        }
        "SetEvent" {
            value = "1"
        }
        "EventPending" {
            value = "1"
        }
    }
    "MAILBOX0_SYSCONFIG_SIdleMode__enum" {
        "ForceIdle" {
            value = "0"
        }
        "NoIdle" {
            value = "1"
        }
        "SmartIdle" {
            value = "2"
        }
        "Reserved" {
            value = "3"
        }
    }
    "MAILBOX0_SYSCONFIG_SoftReset__enum" {
        "Normal" {
            value = "0"
        }
        "Reset" {
            value = "1"
        }
    }
    "M_LMODE_L__enum" {
        "Disabled" {
            value = "0"
        }
        "Enabled" {
            value = "1"
        }
    }
    "M_____enum" {
        "DIS" {
            value = "0"
        }
        "EN" {
            value = "1"
        }
    }
    "PM_CEFUSE_PWRSTCTRL_PowerState__enum" {
        "OFF" {
            value = "0"
        }
        "Reserved" {
            value = "1"
        }
        "INACT" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_CEFUSE_PWRSTST_PowerStateSt__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "INACTIVE" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_GFX_PWRSTCTRL_PowerState__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "reserved_1" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_PER_PWRSTCTRL__mem_ONState__enum" {
        "Reserved2" {
            value = "0"
        }
        "Reserved1" {
            value = "1"
        }
        "Reserved" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_PER_PWRSTCTRL_ram_mem_ONState__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "RESERVED" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_PER_PWRSTST_PowerStateSt__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "Reserved1" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM_P_PWRSTCTRL_PowerState__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "Reserved" {
            value = "2"
        }
        "ON" {
            value = "3"
        }
    }
    "PM__PWRSTCTRL_LogicRETState__enum" {
        "logic_off" {
            value = "0"
        }
        "logic_ret" {
            value = "1"
        }
    }
    "PM__PWRSTCTRL_M_ONState__enum" {
        "Mem_on" {
            value = "3"
        }
    }
    "PM__PWRSTCTRL___RETState__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
    }
    "PM__PWRSTST_InTransition__enum" {
        "No" {
            value = "0"
        }
        "Ongoing" {
            value = "1"
        }
    }
    "PM__PWRSTST_LoStatet__enum" {
        "OFF" {
            value = "0"
        }
        "ON" {
            value = "1"
        }
    }
    "PM__PWRSTST_PowerStateSt__enum" {
        "OFF" {
            value = "0"
        }
        "RET" {
            value = "1"
        }
        "ON" {
            value = "3"
        }
    }
    "PM__PWRSTT___tate__enum" {
        "Mem_off" {
            value = "0"
        }
        "Reserved" {
            value = "2"
        }
        "Mem_on" {
            value = "3"
        }
    }
    "PRM_IRQENABLE_M_o_en__enum" {
        "irq_msk" {
            value = "0"
        }
        "irq_en" {
            value = "1"
        }
    }
    "PRM_IRQSTATUS_M_o_st__enum" {
        "IRQ_fal" {
            value = "0"
        }
        "IRQ_tru" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ABBOFF_ACT_EXPORT__enum" {
        "SRAMNW_ACT_VDDS" {
            value = "0"
        }
        "SRAMNW_ACT_VDDAR" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ABBOFF_SLEEP_EXPORT__enum" {
        "SRAMNW_SLP_VDDS" {
            value = "0"
        }
        "SRAMNW_SLP_VDDAR" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_AIPOFF__enum" {
        "No_Override" {
            value = "0"
        }
        "Override" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_DISABLE_RTA_EXPORT__enum" {
        "RTA_ENABLED" {
            value = "0"
        }
        "RTA_DISABLED" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ENFUNC1_EXPORT__enum" {
        "Short_prot_disabled" {
            value = "0"
        }
        "Short_prot_enabled" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ENFUNC2_EXPORT__enum" {
        "Ext_cap" {
            value = "0"
        }
        "No_ext_cap" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ENFUNC3_EXPORT__enum" {
        "Sub_regul_disabled" {
            value = "0"
        }
        "Sub_regul_enabled" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ENFUNC4__enum" {
        "Ext_clock" {
            value = "0"
        }
        "No_ext_clock" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_ENFUNC5__enum" {
        "One_step" {
            value = "0"
        }
        "Two_step" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_SRAMLDO_STATUS__enum" {
        "ACTIVE" {
            value = "0"
        }
        "RETENTION" {
            value = "1"
        }
    }
    "PRM_LDO_SRAM_SRAM_IN_TRANSITION__enum" {
        "IDLE" {
            value = "0"
        }
        "IN_TRANSITION" {
            value = "1"
        }
    }
    "PRM_RST_RST__enum" {
        "0x0" {
            value = "0"
        }
        "0x1" {
            value = "1"
        }
    }
    "RM__RSTCTRL__RST__enum" {
        "CLEAR" {
            value = "0"
        }
        "ASSERT" {
            value = "1"
        }
    }
    "RM__RSTST__RST__enum" {
        "RESET_NO" {
            value = "0"
        }
        "RESET_YES" {
            value = "1"
        }
    }
    "Spinlock_LOCK_REG_TAKEN__enum" {
        "FREE" {
            value = "0"
        }
        "BUSY" {
            value = "1"
        }
    }
    "Spinlock_SYSCONFIG_AUTOGATING__enum" {
        "FREERUNNING" {
            value = "0"
        }
        "GATED" {
            value = "1"
        }
    }
    "Spinlock_SYSCONFIG_CLOCKACTIVITY__enum" {
        "NOTREQUIRED" {
            value = "0"
        }
        "REQUIRED" {
            value = "1"
        }
    }
    "Spinlock_SYSCONFIG_ENWAKEUP__enum" {
        "NOWAKEUPGEN" {
            value = "0"
        }
        "WAKEUPGEN1" {
            value = "1"
        }
    }
    "Spinlock_SYSCONFIG_SIDLEMODE__enum" {
        "FORCEIDLE" {
            value = "0"
        }
        "NOIDLE" {
            value = "1"
        }
        "SMARTIDLE" {
            value = "2"
        }
        "unused3" {
            value = "3"
        }
    }
    "Spinlock_SYSCONFIG_SOFTRESET__enum" {
        "NOOP" {
            value = "0"
        }
        "DORESET" {
            value = "1"
        }
    }
    "Spinlock_SYSTATUS_NUMLOCKS__enum" {
        "32LOCKS" {
            value = "1"
        }
        "64LOCKS" {
            value = "2"
        }
        "128LOCKS" {
            value = "4"
        }
        "256LOCKS" {
            value = "8"
        }
    }
}
"bitfield" {
    "ADC_TSC_ADCRANGE__bitfield" {
        "Reserved__1" {
            loc = "31..28"
            type = "binary"
        }
        "High_Range_Data" {
            loc = "27..16"
            type = "binary"
            desc = "Sampled ADC data is compared to this value.   If the sampled data is greater than the value, then an interrupt is generated."
        }
        "Reserved__2" {
            loc = "15..12"
            type = "binary"
        }
        "Low_Range_Data" {
            loc = "11..0"
            type = "binary"
            desc = "Sampled ADC data is compared to this value.   If the sampled data is less than the value, then an interrupt is generated."
        }
    }
    "ADC_TSC_ADCSTAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "PEN_IRQ1" {
            loc = "7..7"
            type = "binary"
            desc = "PEN_IRQ[1] status"
        }
        "PEN_IRQ0" {
            loc = "6..6"
            type = "binary"
            desc = "PEN_IRQ[0] status"
        }
        "FSM_BUSY" {
            loc = "5..5"
            type = "binary"
            desc = "Status of OCP FSM and ADC FSM. 0 = Idle. 1 = Busy."
        }
        "STEP_ID" {
            loc = "4..0"
            type = "binary"
            desc = "Encoded values:. 10000 = Idle. 10001 = Charge. 00000 = Step 1. 00001 = Step 2. 00010 = Step 3. 00011 = Step 4. 00100 = Step 5. 00101 = Step 6. 00110 = Step 7. 00111 = Step 8. 01000 = Step 9. 01001 = Step 10. 01010 = Step 11. 01011 = Step 12. 01100 = Step 13. 01101 = Step 14. 01110 = Step 15. 01111 = Step 16."
        }
    }
    "ADC_TSC_ADC_CLKDIV__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "ADC_ClkDiv" {
            loc = "15..0"
            type = "binary"
            desc = "The input ADC clock will be divided by this value and sent to the AFE.   Program to the value minus 1"
        }
    }
    "ADC_TSC_ADC_MISC__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "AFE_Spare_Output" {
            loc = "7..4"
            type = "binary"
            desc = "Connected to AFE Spare Output pins"
        }
        "AFE_Spare_Input" {
            loc = "3..0"
            type = "binary"
            desc = "Connected to AFE Spare Input pins"
        }
    }
    "ADC_TSC_CTRL__bitfield" {
        "Reserved" {
            loc = "31..10"
            type = "binary"
        }
        "HW_preempt" {
            loc = "9..9"
            type = "binary"
            desc = "0 = SW steps are not pre-empted by HW events. 1 = SW steps are pre-empted by HW events"
        }
        "HW_event_mapping" {
            loc = "8..8"
            type = "binary"
            desc = "0 = Map HW event to Pen touch irq (from AFE). 1 = Map HW event to HW event input."
        }
        "Touch_Screen_Enable" {
            loc = "7..7"
            type = "binary"
            desc = "0 = Touchscreen transistors disabled. 1 = Touchscreen transistors enabled"
        }
        "AFE_Pen_Ctrl" {
            loc = "6..5"
            type = "binary"
            desc = "These two bits are sent directly to the AFE Pen Ctrl inputs.   Bit 6 controls the Wiper touch (5 wire modes)Bit 5 controls the X+ touch (4 wire modes)User also needs to make sure the ground path is connected properly for pen interrupt to occur (using the StepConfig registers)Refer to section 4 interrupts for more information"
        }
        "Power_Down" {
            loc = "4..4"
            type = "binary"
            desc = "ADC Power Down control. 0 = AFE is powered up (default). 1 = Write 1 to power down AFE (the tsc_adc_ss enable (bit 0) should also be set to off)"
        }
        "ADC_Bias_Select" {
            loc = "3..3"
            type = "binary"
            desc = "Select Internal or External Bias to AFE. 0 = Internal. 1 = External."
        }
        "StepConfig_WriteProtect_n_active_low" {
            loc = "2..2"
            type = "binary"
            desc = "0 = Step configuration registers are protected (not writable). 1 = Step configuration registers are not protected (writable)."
        }
        "Step_ID_tag" {
            loc = "1..1"
            type = "binary"
            desc = "Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO. 0 = Write zeroes. 1 = Store the channel ID tag."
        }
        "Enable" {
            loc = "0..0"
            type = "binary"
            desc = "TSC_ADC_SS module enable bit. After programming all the steps and configuration registers, write a 1to this bit to turn on TSC_ADC_SS. Writing a 0 will disable the module (after the current conversion)."
        }
    }
    "ADC_TSC_DMAENABLE_CLR__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "Enable_1" {
            loc = "1..1"
            type = "binary"
            desc = "Disable DMA request FIFO 1. Write 0 = No action. Read 0 = DMA line disabled. Read 1 = DMA line enabled. Write 1 = Disable DMA line."
        }
        "Enable_0" {
            loc = "0..0"
            type = "binary"
            desc = "Disable DMA request FIFO 0. Write 0 = No action. Read 0 = DMA line disabled. Read 1 = DMA line enabled. Write 1 = Disable DMA line."
        }
    }
    "ADC_TSC_DMAENABLE_SET__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "Enable_1" {
            loc = "1..1"
            type = "binary"
            desc = "Enable DMA request FIFO 1. Write 0 = No action. Read 0 = DMA line disabled. Read 1 = DMA line enabled. Write 1 = Enable DMA line."
        }
        "Enable_0" {
            loc = "0..0"
            type = "binary"
            desc = "Enable DMA request FIFO 0. Write 0 = No action. Read 0 = DMA line disabled. Read 1 = DMA line enabled. Write 1 = Enable DMA line."
        }
    }
    "ADC_TSC_DMAREQ__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "DMA_Request_Level" {
            loc = "5..0"
            type = "binary"
            desc = "Number of words in FIFO0 before generating a DMA request (program to value minus 1)"
        }
    }
    "ADC_TSC_FIFOCOUNT__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "Words_in_FIFO0" {
            loc = "6..0"
            type = "binary"
            desc = "Number of words currently in the FIFO0"
        }
    }
    "ADC_TSC_FIFODATA__bitfield" {
        "Reserved__1" {
            loc = "31..20"
            type = "binary"
        }
        "ADCCHNLID" {
            loc = "19..16"
            type = "binary"
            desc = "Optional ID tag of channel that captured the data.   If tag option is disabled, these bits will be 0."
        }
        "Reserved__2" {
            loc = "15..12"
            type = "binary"
        }
        "ADCDATA" {
            loc = "11..0"
            type = "binary"
            desc = "12 bit sampled ADC converted data value stored in FIFO 0"
        }
    }
    "ADC_TSC_FIFOTHRESHOLD__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "FIFO0_threshold_Level" {
            loc = "5..0"
            type = "binary"
            desc = "Program the desired FIFO0 data sample level to  reach before generating interrupt to CPU (program to value minus 1)"
        }
    }
    "ADC_TSC_IDLECONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin. 0 = Single Ended. 1 = Differential Pair Enable."
        }
        "SEL_RFM__SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration. 00 = VSSA. 01 = XNUR. 10 = YNLR. 11 = VREFN."
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration. 0000 = Channel 1. 0111 = Channel 8. 1xxx = VREFN."
        }
        "SEL_INM_SWM3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for neg differential. 0000 = Channel 1. 0111 = Channel 8. 1xxx = VREFN."
        }
        "SEL_RFP__SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration. 000 = VDDA. 001 = XPUL. 010 = YPLL. 011 = VREFP. 1xx = INTREF."
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW  configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW__SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW__SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Reserved__2" {
            loc = "4..0"
            type = "binary"
        }
    }
    "ADC_TSC_IRQENABLE_CLR__bitfield" {
        "Reserved" {
            loc = "31..11"
            type = "binary"
        }
        "HW_Pen_Event_synchronous" {
            loc = "10..10"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "Pen_Up_Event" {
            loc = "9..9"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "Out_of_Range" {
            loc = "8..8"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO1_Underflow" {
            loc = "7..7"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO1_Overrun" {
            loc = "6..6"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO1_Threshold" {
            loc = "5..5"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO0_Underflow" {
            loc = "4..4"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO0_Overrun" {
            loc = "3..3"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "FIFO0_Threshold" {
            loc = "2..2"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "End_of_Sequence" {
            loc = "1..1"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
        "HW_Pen_Event_asynchronous" {
            loc = "0..0"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Disable interrupt."
        }
    }
    "ADC_TSC_IRQENABLE_SET__bitfield" {
        "Reserved" {
            loc = "31..11"
            type = "binary"
        }
        "HW_Pen_Event_synchronous" {
            loc = "10..10"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "Pen_Up_event" {
            loc = "9..9"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "Out_of_Range" {
            loc = "8..8"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "FIFO1_Underflow" {
            loc = "7..7"
            type = "binary"
            desc = "Write 0 = No action. Read 0 =  Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "FIFO1_Overrun" {
            loc = "6..6"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  Interrupt disabled (masked). Read 1 =  Interrupt enabled. Write 1 =  Enable interrupt."
        }
        "FIFO1_Threshold" {
            loc = "5..5"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "FIFO0_Underflow" {
            loc = "4..4"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  Interrupt disabled (masked). Read 1 =  Interrupt enabled. Write 1 =  Enable interrupt."
        }
        "FIFO0_Overrun" {
            loc = "3..3"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  Interrupt disabled (masked). Read 1 =  Interrupt enabled. Write 1 =  Enable interrupt."
        }
        "FIFO0_Threshold" {
            loc = "2..2"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "End_of_Sequence" {
            loc = "1..1"
            type = "binary"
            desc = "Write 0 = No action. Read 0 = Interrupt disabled (masked). Read 1 = Interrupt enabled. Write 1 = Enable interrupt."
        }
        "HW_Pen_Event_asynchronous" {
            loc = "0..0"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  Interrupt disabled (masked). Read 1 =  Interrupt enabled. Write 1 =  Enable interrupt."
        }
    }
    "ADC_TSC_IRQSTATUS_RAW__bitfield" {
        "Reserved" {
            loc = "31..11"
            type = "binary"
        }
        "PEN_IRQ_synchronized" {
            loc = "10..10"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "Pen_Up_Event" {
            loc = "9..9"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "Out_of_Range" {
            loc = "8..8"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO1_Underflow" {
            loc = "7..7"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO1_Overrun" {
            loc = "6..6"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO1_Threshold" {
            loc = "5..5"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO0_Underflow" {
            loc = "4..4"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO0_Overrun" {
            loc = "3..3"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "FIFO0_Threshold" {
            loc = "2..2"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "End_of_Sequence" {
            loc = "1..1"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
        "HW_Pen_Event_asynchronous" {
            loc = "0..0"
            type = "binary"
            desc = "Write 0 =  No action. Write 1 =  Set event (debug). Read 0 =  No event pending. Read 1 =  Event pending."
        }
    }
    "ADC_TSC_IRQSTATUS__bitfield" {
        "Reserved" {
            loc = "31..11"
            type = "binary"
        }
        "HW_Pen_Event_synchronous" {
            loc = "10..10"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "Pen_Up_event" {
            loc = "9..9"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "Out_of_Range" {
            loc = "8..8"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO1_Underflow" {
            loc = "7..7"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO1_Overrun" {
            loc = "6..6"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO1_Threshold" {
            loc = "5..5"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO0_Underflow" {
            loc = "4..4"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO0_Overrun" {
            loc = "3..3"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "FIFO0_Threshold" {
            loc = "2..2"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "End_of_Sequence" {
            loc = "1..1"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
        "HW_Pen_Event_asynchronous" {
            loc = "0..0"
            type = "binary"
            desc = "Write 0 =  No action. Read 0 =  No (enabled) event pending. Read 1 =  Event pending. Write 1 =  Clear (raw) event."
        }
    }
    "ADC_TSC_IRQWAKEUP__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "WAKEEN0" {
            loc = "0..0"
            type = "binary"
            desc = "Wakeup generation for HW Pen event. 0 = Wakeup disabled. 1 = Wakeup enabled."
        }
    }
    "ADC_TSC_REVISION__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "HL 0.8 scheme"
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Functional Number"
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision. Will vary depending on release."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision."
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Custom revision."
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision"
        }
    }
    "ADC_TSC_STEPCONFIG1__bitfield" {
        "Reserved" {
            loc = "31..28"
            type = "binary"
        }
        "Range_check" {
            loc = "27..27"
            type = "binary"
            desc = "0 = Disable out-of-range check. 1 = Compare ADC data with range check register."
        }
        "FIFO_select" {
            loc = "26..26"
            type = "binary"
            desc = "Sampled data will be stored in FIFO. 0 = FIFO. 1 = FIFO 1."
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin"
        }
        "SEL_RFM_SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration"
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration"
        }
        "SEL_INM_SWC_3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for negative differential"
        }
        "SEL_RFP_SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration"
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW  configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW  configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW  configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW_SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW_SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Averaging" {
            loc = "4..2"
            type = "binary"
            desc = "Number of samplings to average: 000 = No average. 001 = 2 samples average. 010 = 4 samples average. 011 = 8 samples average. 100 = 16 samples average."
        }
        "Mode" {
            loc = "1..0"
            type = "binary"
            desc = "00 = SW enabled, one-shot. 01 = SW enabled, continuous. 10 = HW synchronized, one-shot. 11 = HW synchronized, continuous."
        }
    }
    "ADC_TSC_STEPCONFIG2__bitfield" {
        "Reserved" {
            loc = "31..28"
            type = "binary"
        }
        "Range_check" {
            loc = "27..27"
            type = "binary"
            desc = "0 = Disable out-of-range check. 1 = Compare ADC data with range check register."
        }
        "FIFO_select" {
            loc = "26..26"
            type = "binary"
            desc = "Sampled data will be stored in FIFO. 0 = FIFO. 1 = FIFO1."
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin"
        }
        "SEL_RFM_SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration"
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration"
        }
        "SEL_INM_SWC_3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for negative differential"
        }
        "SEL_RFP_SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration"
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW  configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW_SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW_SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Averaging" {
            loc = "4..2"
            type = "binary"
            desc = "Number of samples to average: 000 = No average. 001 = 2 samples average. 010 = 4 samples average. 011 = 8 samples average. 100 = 16 samples average."
        }
        "Mode" {
            loc = "1..0"
            type = "binary"
            desc = "00 = SW enabled, one-shot. 01 = SW enabled, continuous. 10 = HW synchronized, one-shot. 11 = HW synchronized, continuous."
        }
    }
    "ADC_TSC_STEPCONFIG9__bitfield" {
        "Reserved" {
            loc = "31..28"
            type = "binary"
        }
        "Range_check" {
            loc = "27..27"
            type = "binary"
            desc = "0 = Disable out-of-range check. 1 = Compare ADC data with range check register."
        }
        "FIFO_select" {
            loc = "26..26"
            type = "binary"
            desc = "Sampled data will be stored in FIFO. 0 = FIFO 1. = FIFO1."
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin"
        }
        "SEL_RFM_SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration"
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration"
        }
        "SEL_INM_SWC_3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for negative differential"
        }
        "SEL_RFP_SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration"
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW_SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW_SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Averaging" {
            loc = "4..2"
            type = "binary"
            desc = "Number of samples to average: 000 = No average. 001 = 2 samples average. 010 = 4 samples average. 011 = 8 samples average. 100 = 16 samples average."
        }
        "Mode" {
            loc = "1..0"
            type = "binary"
            desc = "00 = SW enabled, one-shot. 01 = SW enabled, continuous. 10 = HW synchronized, one-shot. 11 = HW synchronized, continuous."
        }
    }
    "ADC_TSC_STEPCONFIG__bitfield" {
        "Reserved" {
            loc = "31..28"
            type = "binary"
        }
        "Range_check" {
            loc = "27..27"
            type = "binary"
            desc = "0 = Disable out-of-range check. 1 = Compare ADC data with range check register."
        }
        "FIFO_select" {
            loc = "26..26"
            type = "binary"
            desc = "Sampled data will be stored in FIFO. 0 = FIFO. 1 = FIFO1."
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin"
        }
        "SEL_RFM_SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration"
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration"
        }
        "SEL_INM_SWC_3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for negative differential"
        }
        "SEL_RFP_SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration"
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW_SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW_SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Averaging" {
            loc = "4..2"
            type = "binary"
            desc = "Number of samples to average: 000 = No average. 001 = 2 samples average. 010 = 4 samples average. 011 = 8 samples average. 100 = 16 samples average."
        }
        "Mode" {
            loc = "1..0"
            type = "binary"
            desc = "00 = SW enabled, one-shot. 01 = SW enabled, continuous. 10 = HW synchronized, one-shot. 11 = HW synchronized, continuous."
        }
    }
    "ADC_TSC_STEPDELAY__bitfield" {
        "SampleDelay" {
            loc = "31..24"
            type = "binary"
            desc = "This register will control the number of ADC clock cycles to sample (hold SOC high).    Any value programmed here will be added to the minimum requirement of 1 clock cycle."
        }
        "Reserved" {
            loc = "23..18"
            type = "binary"
        }
        "OpenDelay" {
            loc = "17..0"
            type = "binary"
            desc = "Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
        }
    }
    "ADC_TSC_STEPENABLE__bitfield" {
        "Reserved" {
            loc = "31..17"
            type = "binary"
        }
        "STEP16" {
            loc = "16..16"
            type = "binary"
            desc = "Enable step 16"
        }
        "STEP15" {
            loc = "15..15"
            type = "binary"
            desc = "Enable step 15"
        }
        "STEP14" {
            loc = "14..14"
            type = "binary"
            desc = "Enable step 14"
        }
        "STEP13" {
            loc = "13..13"
            type = "binary"
            desc = "Enable step 13"
        }
        "STEP12" {
            loc = "12..12"
            type = "binary"
            desc = "Enable step 12"
        }
        "STEP11" {
            loc = "11..11"
            type = "binary"
            desc = "Enable step 11"
        }
        "STEP10" {
            loc = "10..10"
            type = "binary"
            desc = "Enable step 10"
        }
        "STEP9" {
            loc = "9..9"
            type = "binary"
            desc = "Enable step 9"
        }
        "STEP8" {
            loc = "8..8"
            type = "binary"
            desc = "Enable step 8"
        }
        "STEP7" {
            loc = "7..7"
            type = "binary"
            desc = "Enable step 7"
        }
        "STEP6" {
            loc = "6..6"
            type = "binary"
            desc = "Enable step 6"
        }
        "STEP5" {
            loc = "5..5"
            type = "binary"
            desc = "Enable step 5"
        }
        "STEP4" {
            loc = "4..4"
            type = "binary"
            desc = "Enable step 4"
        }
        "STEP3" {
            loc = "3..3"
            type = "binary"
            desc = "Enable step 3"
        }
        "STEP2" {
            loc = "2..2"
            type = "binary"
            desc = "Enable step  2"
        }
        "STEP1" {
            loc = "1..1"
            type = "binary"
            desc = "Enable step  1"
        }
        "TS_Charge" {
            loc = "0..0"
            type = "binary"
            desc = "Enable TS Charge step"
        }
    }
    "ADC_TSC_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..4"
            type = "binary"
        }
        "IdleMode" {
            loc = "3..2"
            type = "binary"
            desc = "00 =  Force Idle (always acknowledges). 01 =  No Idle Mode (never acknowledges). 10 =  Smart-Idle Mode. 11 =  Smart Idle with Wakeup."
        }
        "Reserved__2" {
            loc = "1..0"
            type = "binary"
        }
    }
    "ADC_TSC_TS_CHARGE_DELAY__bitfield" {
        "Reserved" {
            loc = "31..18"
            type = "binary"
        }
        "OpenDelay" {
            loc = "17..0"
            type = "binary"
            desc = "Program the # of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state. (Value must be greater than 0.)"
        }
    }
    "ADC_TSC_TS_CHARGE_STEPCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Diff_CNTRL" {
            loc = "25..25"
            type = "binary"
            desc = "Differential Control Pin. 0 = Single Ended. 1 = Differential Pair Enable."
        }
        "SEL_RFM__SWC_1_0" {
            loc = "24..23"
            type = "binary"
            desc = "SEL_RFM pins SW configuration. 00 = VSSA. 01 = XNUR. 10 = YNLR. 11 = VREFN."
        }
        "SEL_INP_SWC_3_0" {
            loc = "22..19"
            type = "binary"
            desc = "SEL_INP pins SW configuration. 0000 = Channel 1. 0111 = Channel 8.  1xxx = VREFN."
        }
        "SEL_INM_SWM3_0" {
            loc = "18..15"
            type = "binary"
            desc = "SEL_INM pins for neg differential. 0000 = Channel 1. 0111 = Channel 8. 1xxx = VREFN."
        }
        "SEL_RFP__SWC_2_0" {
            loc = "14..12"
            type = "binary"
            desc = "SEL_RFP pins SW configuration. 000 = VDDA. 001 = XPUL. 010 = YPLL. 011 = VREFP.  1xx = INTREF."
        }
        "WPNSW_SWC" {
            loc = "11..11"
            type = "binary"
            desc = "WPNSW pin SW configuration"
        }
        "YPNSW_SWC" {
            loc = "10..10"
            type = "binary"
            desc = "YPNSW pin SW configuration"
        }
        "XNPSW_SWC" {
            loc = "9..9"
            type = "binary"
            desc = "XNPSW pin SW configuration"
        }
        "YNNSW_SWC" {
            loc = "8..8"
            type = "binary"
            desc = "YNNSW pin SW configuration"
        }
        "YPPSW__SWC" {
            loc = "7..7"
            type = "binary"
            desc = "YPPSW pin SW configuration"
        }
        "XNNSW__SWC" {
            loc = "6..6"
            type = "binary"
            desc = "XNNSW pin SW configuration"
        }
        "XPPSW_SWC" {
            loc = "5..5"
            type = "binary"
            desc = "XPPSW pin SW configuration"
        }
        "Reserved__2" {
            loc = "4..0"
            type = "binary"
        }
    }
    "ALARM2_DAYS_REG__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "ALARM2_DAY1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit for days, Range from 0 to 3"
        }
        "ALARM2_DAY0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit for days, Range from 0 to 9"
        }
    }
    "ALARM2_HOURS_REG__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "ALARM2_PM_nAM" {
            loc = "7..7"
            type = "binary"
            desc = "Only used in PM_AM mode (otherwise 0)"
        }
        "Reserved__2" {
            loc = "6..6"
            type = "binary"
        }
        "ALARM2_HOUR1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit of hours, Range is 0 to 2"
        }
        "ALARM2_HOUR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of hours, Range is 0 to 9"
        }
    }
    "ALARM2_MINUTES_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "ALARM2_MIN1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of minutes, Range is 0 to 5"
        }
        "ALARM2_MIN0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of minutes, Range is 0 to 9"
        }
    }
    "ALARM2_MONTHS_REG__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "ALARM2_MONTH1" {
            loc = "4..4"
            type = "binary"
            desc = "2nd digit of months, Range from 0 to 1"
        }
        "ALARM2_MONTH0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of months, Range from 0 to 9"
        }
    }
    "ALARM2_SECONDS_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "ALARM2_SEC1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of seconds, Range is 0 to 5"
        }
        "ALARM2_SEC0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of seconds, Range is 0 to 9"
        }
    }
    "ALARM2_YEARS_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "ALARM2_YEAR1" {
            loc = "7..4"
            type = "binary"
            desc = "2nd digit of years, Range from 0 to 9"
        }
        "ALARM2_YEAR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of years, Range from 0 to 9"
        }
    }
    "ALARM_DAYS_REG__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "ALARM_DAY1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit for days, Range from 0 to 3"
        }
        "ALARM_DAY0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit for days, Range from 0 to 9"
        }
    }
    "ALARM_HOURS_REG__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "ALARM_PM_nAM" {
            loc = "7..7"
            type = "binary"
            desc = "Only used in PM_AM mode (otherwise 0)"
        }
        "Reserved__2" {
            loc = "6..6"
            type = "binary"
        }
        "ALARM_HOUR1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit of hours, Range is 0 to 2"
        }
        "ALARM_HOUR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of hours, Range is 0 to 9"
        }
    }
    "ALARM_MINUTES_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "ALARM_MIN1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of minutes, Range is 0 to 5"
        }
        "ALARM_MIN0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of minutes, Range is 0 to 9"
        }
    }
    "ALARM_MONTHS_REG__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "ALARM_MONTH1" {
            loc = "4..4"
            type = "binary"
            desc = "2nd digit of months, Range from 0 to 1"
        }
        "ALARM_MONTH0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of months, Range from 0 to 9"
        }
    }
    "ALARM_SECONDS_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "ALARMSEC1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of seconds, Range is 0 to 5"
        }
        "ALARMSEC0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of seconds, Range is 0 to 9"
        }
    }
    "ALARM_YEARS_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "ALARM_YEAR1" {
            loc = "7..4"
            type = "binary"
            desc = "2nd digit of years, Range from 0 to 9"
        }
        "ALARM_YEAR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of years, Range from 0 to 9"
        }
    }
    "CLKSEL_GFX_FCLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL_GFX_FCLK" {
            loc = "1..1"
            type = "C_C_CLKSEL__CLK__enum"
            desc = "Selects  the clock on gfx fclk [warm reset insensitive]"
        }
        "CLKDIV_SEL_GFX_FCLK" {
            loc = "0..0"
            type = "CLKSEL_GFX_FCLK_CLKDIV_SEL_GFX_FCLK__enum"
            desc = "Selects  the divider value on gfx fclk [warm reset insensitive]"
        }
    }
    "CLKSEL_GPIO0_DBCLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_GPIO0_DBCLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for GPIO0 debounce  clock [warm reset insensitive]"
        }
    }
    "CLKSEL_LCDC_PIXEL_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Controls the Mux Select of LCDC PIXEL clock"
        }
    }
    "CLKSEL_PRU_ICSS_OCP_CLK__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "CLKSEL" {
            loc = "0..0"
            type = "CS__CLK_CLKSEL__enum"
            desc = "Controls Mux Select of PRU-ICSS OCP clock mux"
        }
    }
    "CLKSEL_TIMER1MS_CLK__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "CLKSEL" {
            loc = "2..0"
            type = "CLKSEL_TIMER1MS_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for DMTIMER_1MS clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER2_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER2 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER3_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER3 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER4_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER4 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER5_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER5 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER6_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER6 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_TIMER7_CLK__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "CLKSEL" {
            loc = "1..0"
            type = "CLKSEL_IE_CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for TIMER7 clock [warm reset insensitive]"
        }
    }
    "CLKSEL_WDT1_CLK__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "CLKSEL" {
            loc = "0..0"
            type = "CS__CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for WDT1 clock [warm reset insensitive]"
        }
    }
    "CM_AUTOIDLE_DPLL___bitfield__1" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "AUTO_DPLL_MODE" {
            loc = "2..0"
            type = "binary"
            desc = "AUTO_DPLL_MODE is not supported."
        }
    }
    "CM_AUTOIDLE_DPLL___bitfield__2" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "AUTO_DPLL_MODE" {
            loc = "2..0"
            type = "binary"
            desc = "This feature is not supported."
        }
    }
    "CM_CEFUSE_CEFUSE_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..18"
            type = "binary"
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status. [warm reset insensitive]"
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_CEFUSE_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "CLKACTIVITY_CUST_EFUSE_SYS_CLK" {
            loc = "9..9"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the Cust_Efuse_SYSCLK clock input of the domain. [warm reset insensitive]"
        }
        "CLKACTIVITY_L4_CEFUSE_GICLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L4_CEFUSE_GCLK clock input of the domain. [warm reset insensitive]"
        }
        "Reserved__2" {
            loc = "7..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the clock domain in customer efuse power domain."
        }
    }
    "CM_CLKDCOLDO_DPLL_PER__bitfield" {
        "Reserved__1" {
            loc = "31..13"
            type = "binary"
        }
        "DPLL_CLKDCOLDO_PWDN" {
            loc = "12..12"
            type = "CM_D_DPLL_E_D_CLKO_PWDN__enum"
            desc = "Automatic power down for CLKDCOLDO o/p when it is gated"
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "ST_DPLL_CLKDCOLDO" {
            loc = "9..9"
            type = "CM_D_DPLL_E_ST_D_CLKO__enum"
            desc = "DPLL CLKDCOLDO status"
        }
        "DPLL_CLKDCOLDO_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of DPLL CLKDCOLDO"
        }
        "Reserved__3" {
            loc = "7..0"
            type = "binary"
        }
    }
    "CM_CLKMODE_DPLL_PER__bitfield" {
        "Reserved__1" {
            loc = "31..16"
            type = "binary"
        }
        "DPLL_SSC_TYPE" {
            loc = "15..15"
            type = "CM_CLKMODE_DPLL_DPLL_SSC_TYPE__enum"
            desc = "Select between Triangular and SquareWave Spread Spectrum Clocking"
        }
        "DPLL_SSC_DOWNSPREAD" {
            loc = "14..14"
            type = "CM_CLKMODE_DPLL_DPLL_SSC_DOWNSPREAD__enum"
            desc = "Control if only low frequency spread is required"
        }
        "DPLL_SSC_ACK" {
            loc = "13..13"
            type = "M_LMODE_L__enum"
            desc = "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature"
        }
        "DPLL_SSC_EN" {
            loc = "12..12"
            type = "M_LMODE_L__enum"
            desc = "Enable or disable Spread Spectrum Clocking"
        }
        "Reserved__2" {
            loc = "11..3"
            type = "binary"
        }
        "DPLL_EN" {
            loc = "2..0"
            type = "CM_CLKMODE_DPLL_PER_DPLL_EN__enum"
            desc = "DPLL control.  Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect DPLL Low Power Stop mode."
        }
    }
    "CM_CLKMODE_DPLL___bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "DPLL_SSC_TYPE" {
            loc = "15..15"
            type = "CM_CLKMODE_DPLL_DPLL_SSC_TYPE__enum"
            desc = "Select between Triangular and SquareWave Spread Spectrum Clocking"
        }
        "DPLL_SSC_DOWNSPREAD" {
            loc = "14..14"
            type = "CM_CLKMODE_DPLL_DPLL_SSC_DOWNSPREAD__enum"
            desc = "Control if only low frequency spread is required"
        }
        "DPLL_SSC_ACK" {
            loc = "13..13"
            type = "M_LMODE_L__enum"
            desc = "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature"
        }
        "DPLL_SSC_EN" {
            loc = "12..12"
            type = "M_LMODE_L__enum"
            desc = "Enable or disable Spread Spectrum Clocking"
        }
        "DPLL_REGM4XEN" {
            loc = "11..11"
            type = "CM_CLKMODE_DPLL_DPLL_REGM4XEN__enum"
            desc = "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled."
        }
        "DPLL_LPMODE_EN" {
            loc = "10..10"
            type = "CM_CLKMODE_DPLL_DPLL_LPMODE_EN__enum"
            desc = "Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled."
        }
        "DPLL_RELOCK_RAMP_EN" {
            loc = "9..9"
            type = "binary"
            desc = "If enabled, the clock ramping feature is used applied during the lock process, as well as the relock process.  If disabled, the clock ramping feature is used only during the first lock."
        }
        "DPLL_DRIFTGUARD_EN" {
            loc = "8..8"
            type = "CM_CLKMODE_DPLL_DPLL_DRIFTGUARD_EN__enum"
            desc = "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set."
        }
        "DPLL_RAMP_RATE" {
            loc = "7..5"
            type = "CM_CLKMODE_DPLL_DPLL_RAMP_RATE__enum"
            desc = "Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process"
        }
        "DPLL_RAMP_LEVEL" {
            loc = "4..3"
            type = "CM_CLKMODE_DPLL_DPLL_RAMP_LEVEL__enum"
            desc = "The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock. The frequency ramping will happen in a maximum of 4 steps in frequency before the DPLL's frequency lock indicator is asserted.  This register is used to enable/disable the DPLL ramping feature. If enabled, it is also used to select the algorithm used for clock ramping"
        }
        "DPLL_EN" {
            loc = "2..0"
            type = "CM_CLKMODE_DPLL_DPLL_EN__enum"
            desc = "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN Bypass mode."
        }
    }
    "CM_CLKOUT_CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "CLKOUT2EN" {
            loc = "7..7"
            type = "M_____enum"
            desc = "This bit controls the external clock activity"
        }
        "Reserved__2" {
            loc = "6..6"
            type = "binary"
        }
        "CLKOUT2DIV" {
            loc = "5..3"
            type = "CM_CLKOUT_CTRL_CLKOUT2DIV__enum"
            desc = "THis  field controls the external clock divison factor"
        }
        "CLKOUT2SOURCE" {
            loc = "2..0"
            type = "CM_CLKOUT_CTRL_CLKOUT2SOURCE__enum"
            desc = "This field selects the external output clock source"
        }
    }
    "CM_CLKSEL_DPLL_CORE__bitfield" {
        "Reserved__1" {
            loc = "31..23"
            type = "binary"
        }
        "Reserved__2" {
            loc = "22..19"
            type = "binary"
        }
        "DPLL_MULT" {
            loc = "18..8"
            type = "CM_CLKSEL_DPLL_CORE_DPLL_MULT__enum"
            desc = "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN Bypass mode. (equal to input M of DPLL; M=2 to 2047 => DPLL multiplies by M)"
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "DPLL_DIV" {
            loc = "6..0"
            type = "binary"
            desc = "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."
        }
    }
    "CM_CLKSEL_DPLL_DDR__bitfield" {
        "Reserved__1" {
            loc = "31..24"
            type = "binary"
        }
        "DPLL_BYP_CLKSEL" {
            loc = "23..23"
            type = "CM_CLKSEL_DPLL__DPLL_BYP_CLKSEL__enum"
            desc = "Select CLKINP orr CLKINPULOW as bypass clock"
        }
        "Reserved__2" {
            loc = "22..19"
            type = "binary"
        }
        "DPLL_MULT" {
            loc = "18..8"
            type = "CM_CLKSEL_DPLL__DPLL_MULT__enum"
            desc = "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN Bypass mode. (equal to input M of DPLL; M=2 to 2047 => DPLL multiplies by M)."
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "DPLL_DIV" {
            loc = "6..0"
            type = "binary"
            desc = "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."
        }
    }
    "CM_CLKSEL_DPLL_DISP__bitfield" {
        "Reserved__1" {
            loc = "31..24"
            type = "binary"
        }
        "DPLL_BYP_CLKSEL" {
            loc = "23..23"
            type = "CM_CLKSEL_DPLL__DPLL_BYP_CLKSEL__enum"
            desc = "Select CLKINP or CLKINPULOW as bypass clock"
        }
        "Reserved__2" {
            loc = "22..19"
            type = "binary"
        }
        "DPLL_MULT" {
            loc = "18..8"
            type = "CM_CLKSEL_DPLL__DPLL_MULT__enum"
            desc = "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN Bypass mode. (equal to input M of DPLL; M=2 to 2047 => DPLL multiplies by M)."
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "DPLL_DIV" {
            loc = "6..0"
            type = "binary"
            desc = "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."
        }
    }
    "CM_CLKSEL_DPLL_MPU__bitfield" {
        "Reserved__1" {
            loc = "31..24"
            type = "binary"
        }
        "DPLL_BYP_CLKSEL" {
            loc = "23..23"
            type = "CM_CLKSEL_DPLL__DPLL_BYP_CLKSEL__enum"
            desc = "Selects CLKINP or CLKINPULOW as Bypass Clock"
        }
        "Reserved__2" {
            loc = "22..19"
            type = "binary"
        }
        "DPLL_MULT" {
            loc = "18..8"
            type = "CM_CLKSEL_DPLL__DPLL_MULT__enum"
            desc = "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN Bypass mode. (equal to input M of DPLL; M=2 to 2047 => DPLL multiplies by M)."
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "DPLL_DIV" {
            loc = "6..0"
            type = "binary"
            desc = "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."
        }
    }
    "CM_CLKSEL_DPLL_PERIPH__bitfield" {
        "DPLL_SD_DIV" {
            loc = "31..24"
            type = "CM_CLKSEL_DPLL_PERIPH_DPLL_SD_DIV__enum"
            desc = "Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). Must be set with M and N factors, and must not be changed once DPLL is locked."
        }
        "Reserved__1" {
            loc = "23..23"
            type = "binary"
        }
        "Reserved__2" {
            loc = "22..20"
            type = "binary"
        }
        "DPLL_MULT" {
            loc = "19..8"
            type = "CM_CLKSEL_DPLL__DPLL_MULT__enum"
            desc = "DPLL multiplier factor (2 to 4095). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN Bypass mode. (equal to input M of DPLL; M=2 to 4095 => DPLL multiplies by M)."
        }
        "DPLL_DIV" {
            loc = "7..0"
            type = "binary"
            desc = "DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)."
        }
    }
    "CM_CPTS_RFT_CLKSEL__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "Reserved__3" {
            loc = "1..1"
            type = "binary"
        }
        "CLKSEL" {
            loc = "0..0"
            type = "CS__CLK_CLKSEL__enum"
            desc = "Selects  the Mux select line for cpgmac rft clock [warm reset insensitive]"
        }
    }
    "CM_DIV_M2_DPLL_PER__bitfield" {
        "Reserved" {
            loc = "31..10"
            type = "binary"
        }
        "ST_DPLL_CLKOUT" {
            loc = "9..9"
            type = "CM_DIV_M2_DPLL_ST_DPLL_CLKOUT__enum"
            desc = "DPLL CLKOUT status"
        }
        "DPLL_CLKOUT_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of DPLL CLKOUT"
        }
        "DPLL_CLKOUT_DIVCHACK" {
            loc = "7..7"
            type = "binary"
            desc = "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect"
        }
        "DPLL_CLKOUT_DIV" {
            loc = "6..0"
            type = "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum"
            desc = "DPLL M2 post-divider factor (1 to 31)."
        }
    }
    "CM_DIV_M2_DPLL___bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "ST_DPLL_CLKOUT" {
            loc = "9..9"
            type = "CM_DIV_M2_DPLL_ST_DPLL_CLKOUT__enum"
            desc = "DPLL CLKOUT status"
        }
        "DPLL_CLKOUT_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of DPLL CLKOUT"
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "DPLL_CLKOUT_DIVCHACK" {
            loc = "5..5"
            type = "binary"
            desc = "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect"
        }
        "DPLL_CLKOUT_DIV" {
            loc = "4..0"
            type = "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum"
            desc = "DPLL M2 post-divider factor (1 to 31)."
        }
    }
    "CM_DIV_M4_DPLL_CORE__bitfield" {
        "Reserved__1" {
            loc = "31..13"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT1_PWDN" {
            loc = "12..12"
            type = "CM_D_DPLL_E_D_CLKO_PWDN__enum"
            desc = "Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "ST_HSDIVIDER_CLKOUT1" {
            loc = "9..9"
            type = "CM_D_DPLL_E_ST_D_CLKO__enum"
            desc = "HSDIVIDER CLKOUT1 status"
        }
        "HSDIVIDER_CLKOUT1_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of HSDIVIDER CLKOUT1"
        }
        "Reserved__3" {
            loc = "7..6"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT1_DIVCHACK" {
            loc = "5..5"
            type = "binary"
            desc = "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect"
        }
        "HSDIVIDER_CLKOUT1_DIV" {
            loc = "4..0"
            type = "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum"
            desc = "DPLL post-divider factor, M4, for internal clock generation. Divide values from 1 to 31."
        }
    }
    "CM_DIV_M5_DPLL_CORE__bitfield" {
        "Reserved__1" {
            loc = "31..13"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT2_PWDN" {
            loc = "12..12"
            type = "CM_D_DPLL_E_D_CLKO_PWDN__enum"
            desc = "Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "ST_HSDIVIDER_CLKOUT2" {
            loc = "9..9"
            type = "CM_D_DPLL_E_ST_D_CLKO__enum"
            desc = "HSDIVIDER CLKOUT2 status"
        }
        "HSDIVIDER_CLKOUT2_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of HSDIVIDER CLKOUT2"
        }
        "Reserved__3" {
            loc = "7..6"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT2_DIVCHACK" {
            loc = "5..5"
            type = "binary"
            desc = "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect"
        }
        "HSDIVIDER_CLKOUT2_DIV" {
            loc = "4..0"
            type = "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum"
            desc = "DPLL post-divider factor, M5, for internal clock generation. Divide values from 1 to 31."
        }
    }
    "CM_DIV_M6_DPLL_CORE__bitfield" {
        "Reserved__1" {
            loc = "31..13"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT3_PWDN" {
            loc = "12..12"
            type = "CM_D_DPLL_E_D_CLKO_PWDN__enum"
            desc = "Automatic power down for HSDIVIDER M6 divider and hence CLKOUT3 output when the o/p clock is gated."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "ST_HSDIVIDER_CLKOUT3" {
            loc = "9..9"
            type = "CM_D_DPLL_E_ST_D_CLKO__enum"
            desc = "HSDIVIDER CLKOUT3 status"
        }
        "HSDIVIDER_CLKOUT3_GATE_CTRL" {
            loc = "8..8"
            type = "CM_D_DPLL_D_CLKO_GATE_CTRL__enum"
            desc = "Control gating of HSDIVIDER CLKOUT3"
        }
        "Reserved__3" {
            loc = "7..6"
            type = "binary"
        }
        "HSDIVIDER_CLKOUT3_DIVCHACK" {
            loc = "5..5"
            type = "binary"
            desc = "Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect"
        }
        "HSDIVIDER_CLKOUT3_DIV" {
            loc = "4..0"
            type = "CM_DIV_M_DPLL_D_CLKOUT_DIV__enum"
            desc = "DPLL post-divider factor, M6, for internal clock generation. Divide values from 1 to 31."
        }
    }
    "CM_GFX_L3_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..10"
            type = "binary"
        }
        "CLKACTIVITY_GFX_FCLK" {
            loc = "9..9"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GFX_GCLK  clock in the domain."
        }
        "CLKACTIVITY_GFX_L3_GCLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GFX_L3_GCLK  clock in the domain."
        }
        "Reserved__3" {
            loc = "7..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the GFX clock domain in GFX power domain."
        }
    }
    "CM_GFX_L4LS_GFX_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..9"
            type = "binary"
        }
        "CLKACTIVITY_L4LS_GFX_GCLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  L4_LS clock in the domain."
        }
        "Reserved__2" {
            loc = "7..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L4LS clock domain in GFX power domain."
        }
    }
    "CM_IDLEST_DPLL___bitfield" {
        "Reserved__1" {
            loc = "31..9"
            type = "binary"
        }
        "ST_MN_BYPASS" {
            loc = "8..8"
            type = "CM_IDLEST_DPLL_ST_MN_BYPASS__enum"
            desc = "DPLL MN_BYPASS status"
        }
        "Reserved__2" {
            loc = "7..1"
            type = "binary"
        }
        "ST_DPLL_CLK" {
            loc = "0..0"
            type = "CM_IDLEST_DPLL_ST_DPLL_CLK__enum"
            desc = "DPLL clock activity"
        }
    }
    "CM_L3_AON_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..11"
            type = "binary"
        }
        "Reserved__3" {
            loc = "10..8"
            type = "binary"
        }
        "Reserved__4" {
            loc = "7..5"
            type = "binary"
        }
        "CLKACTIVITY_DEBUG_CLKA" {
            loc = "4..4"
            type = "binary"
            desc = "This field indicates the state of the Debugss CLKA clock in the domain."
        }
        "CLKACTIVITY_L3_AON_GCLK" {
            loc = "3..3"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L3_AON  clock in the domain."
        }
        "CLKACTIVITY_DBGSYSCLK" {
            loc = "2..2"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the Debugss sysclk  clock in the domain."
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L3 AON clock domain."
        }
    }
    "CM_L4_WKUP_AON_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..14"
            type = "binary"
        }
        "Reserved__3" {
            loc = "13..8"
            type = "binary"
        }
        "Reserved__4" {
            loc = "7..4"
            type = "binary"
        }
        "Reserved__5" {
            loc = "3..3"
            type = "binary"
        }
        "CLKACTIVITY_L4_WKUP_AON_GCLK" {
            loc = "2..2"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L4_WKUP  clock in the domain."
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "binary"
            desc = "Controls the clock state transition of the always on L4 clock domain."
        }
    }
    "CM_MAC_CLKSEL__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "MII_CLK_SEL" {
            loc = "2..2"
            type = "C_C_CLKSEL__CLK__enum"
            desc = "MII Clock Divider Selection. This bit is warm reset insensitive when CPSW RESET_ISO is enabled"
        }
        "Reserved__2" {
            loc = "1..0"
            type = "binary"
        }
    }
    "CM_MPU_CLKSTCTRL__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "CLKACTIVITY_MPU_CLK" {
            loc = "2..2"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the MPU Clock"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the MPU clock domains."
        }
    }
    "CM_PER_CLK_24MHZ_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..5"
            type = "binary"
        }
        "CLKACTIVITY_CLK_24MHZ_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  24MHz clock in the domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the 24MHz clock domain."
        }
    }
    "CM_PER_CPGMAC0_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "STBYST" {
            loc = "18..18"
            type = "CM_STBYST__enum"
            desc = "Module standby status. This bit is warm reset insensitive when CPSW RESET_ISO is enabled"
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status. This bit is warm reset insensitive when CPSW RESET_ISO is enabled"
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed. This bit is warm reset insensitive when CPSW RESET_ISO is enabled"
        }
    }
    "CM_PER_CPSW_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..5"
            type = "binary"
        }
        "CLKACTIVITY_CPSW_125MHz_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  CPSW 125 MHz OCP clock in the domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the CPSW OCP clock domain."
        }
    }
    "CM_PER_GPIO1_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "OPTFCLKEN_GPIO_1_GDBCLK" {
            loc = "18..18"
            type = "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum"
            desc = "Optional functional clock control."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_PER_GPIO2_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "OPTFCLKEN_GPIO_2_GDBCLK" {
            loc = "18..18"
            type = "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum"
            desc = "Optional functional clock control."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_PER_GPIO3_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "OPTFCLKEN_GPIO_3_GDBCLK" {
            loc = "18..18"
            type = "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum"
            desc = "Optional functional clock control."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_PER_L3S_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..11"
            type = "binary"
        }
        "Reserved__3" {
            loc = "10..10"
            type = "binary"
        }
        "Reserved__4" {
            loc = "9..9"
            type = "binary"
        }
        "Reserved__5" {
            loc = "8..8"
            type = "binary"
        }
        "Reserved__6" {
            loc = "7..5"
            type = "binary"
        }
        "Reserved__7" {
            loc = "4..4"
            type = "binary"
        }
        "CLKACTIVITY_L3S_GCLK" {
            loc = "3..3"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  L3S_GCLK clock in the domain."
        }
        "Reserved__8" {
            loc = "2..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L3 Slow clock domain."
        }
    }
    "CM_PER_L3_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "CLKACTIVITY_MCASP_GCLK" {
            loc = "7..7"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  MCASP_GCLK clock in the domain."
        }
        "CLKACTIVITY_CPTS_RFT_GCLK" {
            loc = "6..6"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  CLKACTIVITY_CPTS_RFT_GCLK clock in the domain."
        }
        "Reserved__2" {
            loc = "5..5"
            type = "binary"
        }
        "CLKACTIVITY_L3_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  L3_GCLK clock in the domain."
        }
        "CLKACTIVITY_MMC_FCLK" {
            loc = "3..3"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  MMC_GCLK clock in the domain."
        }
        "CLKACTIVITY_EMIF_GCLK" {
            loc = "2..2"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  EMIF_GCLK clock in the domain."
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L3 clock domain."
        }
    }
    "CM_PER_L4HS_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..7"
            type = "binary"
        }
        "CLKACTIVITY_CPSW_5MHZ_GCLK" {
            loc = "6..6"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  CPSW_5MHZ_GCLK clock in the domain."
        }
        "CLKACTIVITY_CPSW_50MHZ_GCLK" {
            loc = "5..5"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  CPSW_50MHZ_GCLK clock in the domain."
        }
        "CLKACTIVITY_CPSW_250MHZ_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  CPSW_250MHZ_GCLK clock in the domain."
        }
        "CLKACTIVITY_L4HS_GCLK" {
            loc = "3..3"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  L4HS_GCLK clock in the domain."
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L4 Fast clock domain."
        }
    }
    "CM_PER_L4LS_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..29"
            type = "binary"
        }
        "CLKACTIVITY_TIMER6_GCLK" {
            loc = "28..28"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER6 CLKTIMER  clock in the domain."
        }
        "CLKACTIVITY_TIMER5_GCLK" {
            loc = "27..27"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER5 CLKTIMER  clock in the domain."
        }
        "CLKACTIVITY_GPIO_5_GDBCLK" {
            loc = "26..26"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO5_GDBCLK  clock in the domain."
        }
        "CLKACTIVITY_SPI_GCLK" {
            loc = "25..25"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the SPI_GCLK  clock in the domain."
        }
        "CLKACTIVITY_I2C_FCLK" {
            loc = "24..24"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the I2C _FCLK  clock in the domain."
        }
        "Reserved__2" {
            loc = "23..23"
            type = "binary"
        }
        "CLKACTIVITY_GPIO_4_GDBCLK" {
            loc = "22..22"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO4_GDBCLK  clock in the domain."
        }
        "CLKACTIVITY_GPIO_3_GDBCLK" {
            loc = "21..21"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO3_GDBCLK  clock in the domain."
        }
        "CLKACTIVITY_GPIO_2_GDBCLK" {
            loc = "20..20"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO2_ GDBCLK clock in the domain."
        }
        "CLKACTIVITY_GPIO_1_GDBCLK" {
            loc = "19..19"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO1_GDBCLK  clock in the domain."
        }
        "CLKACTIVITY_GPIO_6_GDBCLK" {
            loc = "18..18"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the GPIO6_GDBCLK  clock in the domain."
        }
        "CLKACTIVITY_LCDC_GCLK" {
            loc = "17..17"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the LCD clock in the domain."
        }
        "CLKACTIVITY_TIMER4_GCLK" {
            loc = "16..16"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER4 CLKTIMER  clock in the domain."
        }
        "CLKACTIVITY_TIMER3_GCLK" {
            loc = "15..15"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER3 CLKTIMER  clock in the domain."
        }
        "CLKACTIVITY_TIMER2_GCLK" {
            loc = "14..14"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER2 CLKTIMER  clock in the domain."
        }
        "CLKACTIVITY_TIMER7_GCLK" {
            loc = "13..13"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER7 CLKTIMER  clock in the domain."
        }
        "Reserved__3" {
            loc = "12..12"
            type = "binary"
        }
        "CLKACTIVITY_CAN_CLK" {
            loc = "11..11"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the CAN_CLK clock in the domain."
        }
        "CLKACTIVITY_UART_GFCLK" {
            loc = "10..10"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the UART_GFCLK  clock in the domain."
        }
        "Reserved__4" {
            loc = "9..9"
            type = "binary"
        }
        "CLKACTIVITY_L4LS_GCLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L4LS_GCLK  clock in the domain."
        }
        "Reserved__5" {
            loc = "7..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the L4 SLOW clock domain in PER power domain."
        }
    }
    "CM_PER_LCDC_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "CLKACTIVITY_LCDC_L4_OCP_GCLK" {
            loc = "5..5"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  LCDC L4 OCP clock in the domain."
        }
        "CLKACTIVITY_LCDC_L3_OCP_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  LCDC L3 OCP clock in the domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the LCDC OCP clock domain."
        }
    }
    "CM_PER_OCPWP_L3_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "CLKACTIVITY_OCPWP_L4_GCLK" {
            loc = "5..5"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  OCPWP L4 clock in the domain."
        }
        "CLKACTIVITY_OCPWP_L3_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  OCPWP L3 clock in the domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the OCPWP clock domain."
        }
    }
    "CM_PER_PRU_ICSS_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..7"
            type = "binary"
        }
        "CLKACTIVITY_PRU_ICSS_UART_GCLK" {
            loc = "6..6"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  PRU-ICSS UART clock in the domain."
        }
        "CLKACTIVITY_PRU_ICSS_IEP_GCLK" {
            loc = "5..5"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  PRU-ICSS IEP clock in the domain."
        }
        "CLKACTIVITY_PRU_ICSS_OCP_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the  PRU-ICSS OCP clock in the domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the PRU-ICSS OCP clock domain."
        }
    }
    "CM_RTC_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..11"
            type = "binary"
        }
        "Reserved__3" {
            loc = "10..10"
            type = "binary"
        }
        "CLKACTIVITY_RTC_32KCLK" {
            loc = "9..9"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the 32K RTC clock in the domain."
        }
        "CLKACTIVITY_L4_RTC_GCLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L4 RTC clock in the domain."
        }
        "Reserved__4" {
            loc = "7..2"
            type = "binary"
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM__CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the RTC clock domains."
        }
    }
    "CM_SSC_DELTAMSTEP_DPLL___bitfield" {
        "Reserved" {
            loc = "31..20"
            type = "binary"
        }
        "DELTAMSTEP" {
            loc = "19..0"
            type = "binary"
            desc = "Fractional setting for DeltaMStep parameter"
        }
    }
    "CM_SSC_MODFREQDIV_DPLL___bitfield" {
        "Reserved__1" {
            loc = "31..11"
            type = "binary"
        }
        "MODFREQDIV_EXPONENT" {
            loc = "10..8"
            type = "binary"
            desc = "Set the Exponent component of MODFREQDIV factor"
        }
        "Reserved__2" {
            loc = "7..7"
            type = "binary"
        }
        "MODFREQDIV_MANTISSA" {
            loc = "6..0"
            type = "binary"
            desc = "Set the Mantissa component of MODFREQDIV factor"
        }
    }
    "CM_WKUP_CLKSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..15"
            type = "binary"
        }
        "CLKACTIVITY_ADC_FCLK" {
            loc = "14..14"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the ADC  clock in the domain."
        }
        "CLKACTIVITY_TIMER1_GCLK" {
            loc = "13..13"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the TIMER1 clock in the domain."
        }
        "CLKACTIVITY_UART0_GFCLK" {
            loc = "12..12"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the UART0 clock in the domain."
        }
        "CLKACTIVITY_I2C0_GFCLK" {
            loc = "11..11"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the I2C0  clock in the domain."
        }
        "CLKACTIVITY_TIMER0_GCLK" {
            loc = "10..10"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the WKUPTIMER_GCLK  clock in the domain."
        }
        "Reserved__2" {
            loc = "9..9"
            type = "binary"
        }
        "CLKACTIVITY_GPIO0_GDBCLK" {
            loc = "8..8"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the WKUPGPIO_DBGICLK  clock in the domain."
        }
        "Reserved__3" {
            loc = "7..5"
            type = "binary"
        }
        "CLKACTIVITY_WDT1_GCLK" {
            loc = "4..4"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the WDT1_GCLK  clock in the domain."
        }
        "CLKACTIVITY_SR_SYSCLK" {
            loc = "3..3"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the SMARTREFGLEX SYSCLK  clock in the domain."
        }
        "CLKACTIVITY_L4_WKUP_GCLK" {
            loc = "2..2"
            type = "CM__CLKSTCTRL_CLKACTIVITY_CLK__enum"
            desc = "This field indicates the state of the L4_WKUP  clock in the domain."
        }
        "CLKTRCTRL" {
            loc = "1..0"
            type = "CM_WKUP_CLKSTCTRL_CLKTRCTRL__enum"
            desc = "Controls the clock state transition of the always on clock domain."
        }
    }
    "CM_WKUP_DEBUGSS_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..31"
            type = "binary"
        }
        "OPTCLK_DEBUG_CLKA" {
            loc = "30..30"
            type = "binary"
        }
        "stm_pmd_clkdivsel" {
            loc = "29..27"
            type = "binary"
        }
        "trc_pmd_clkdivsel" {
            loc = "26..24"
            type = "binary"
        }
        "stm_pmd_clksel" {
            loc = "23..22"
            type = "binary"
        }
        "trc_pmd_clksel" {
            loc = "21..20"
            type = "binary"
        }
        "OPTFCLKEN_DBGSYSCLK" {
            loc = "19..19"
            type = "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum"
            desc = "Optional functional clock control."
        }
        "STBYST" {
            loc = "18..18"
            type = "CM_STBYST__enum"
            desc = "Module standby status."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_WKUP_GPIO0_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "OPTFCLKEN_GPIO0_GDBCLK" {
            loc = "18..18"
            type = "CM_P_G_CLKCTRL_OPTFCLKEN_DBCLK__enum"
            desc = "Optional functional clock control."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_WKUP_L4WKUP_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "Reserved__2" {
            loc = "18..18"
            type = "binary"
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__3" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "binary"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM_WKUP_WKUP_M3_CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "STBYST" {
            loc = "18..18"
            type = "CM_STBYST__enum"
            desc = "Module standby status."
        }
        "Reserved__2" {
            loc = "17..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "binary"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM__CLKCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..18"
            type = "binary"
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM___CLKCTRL__bitfield__1" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "Reserved__2" {
            loc = "18..18"
            type = "binary"
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__3" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CM___CLKCTRL__bitfield__2" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "STBYST" {
            loc = "18..18"
            type = "CM_STBYST__enum"
            desc = "Module standby status."
        }
        "IDLEST" {
            loc = "17..16"
            type = "CM_IDLEST__enum"
            desc = "Module idle status."
        }
        "Reserved__2" {
            loc = "15..2"
            type = "binary"
        }
        "MODULEMODE" {
            loc = "1..0"
            type = "CM_MODULEMODE__enum"
            desc = "Control the way mandatory clocks are managed."
        }
    }
    "CONNID_COS_1_MAP__bitfield" {
        "REG_CONNID_COS_1_MAP_EN" {
            loc = "31..31"
            type = "binary"
            desc = "Set 1 to enable connection ID to class of service 1 mapping. Set 0 to disable mapping."
        }
        "REG_CONNID_1_COS_1" {
            loc = "30..23"
            type = "binary"
            desc = "Connection ID value 1 for class of service 1."
        }
        "REG_MSK_1_COS_1" {
            loc = "22..20"
            type = "binary"
            desc = "Mask for connection ID value 1 for class of service 1.  0 = disable masking.  1 = mask connection ID bit 0.  2 = mask connection ID bits 1:0.  3 = mask connection ID bits 2:0.  4 = mask connection ID bits 3:0.  5 = mask connection ID bits 4:0.  6 = mask connection ID bits 5:0.  7 = mask connection ID bits 6:0."
        }
        "REG_CONNID_2_COS_1" {
            loc = "19..12"
            type = "binary"
            desc = "Connection ID value 2 for class of service 1."
        }
        "REG_MSK_2_COS_1" {
            loc = "11..10"
            type = "binary"
            desc = "Mask for connection ID value 2 for class of service 1.  0 = disable masking.  1 = mask connection ID bit 0.  2 = mask connection ID bits 1:0.  3 = mask connection ID bits 2:0."
        }
        "REG_CONNID_3_COS_1" {
            loc = "9..2"
            type = "binary"
            desc = "Connection ID value 3 for class of service 1."
        }
        "REG_MSK_3_COS_1" {
            loc = "1..0"
            type = "binary"
            desc = "Mask for connection ID. Value 3 for class of service 1. 0 = disable masking.  1 = mask connection ID bit 0. 2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0."
        }
    }
    "CONNID_COS_2_MAP__bitfield" {
        "REG_CONNID_COS_2_MAP_EN" {
            loc = "31..31"
            type = "binary"
            desc = "Set 1 to enable connection ID to class of service 2 mapping. Set 0 to disable mapping."
        }
        "REG_CONNID_1_COS_2" {
            loc = "30..23"
            type = "binary"
            desc = "Connection ID value 1 for class of service 2."
        }
        "REG_MSK_1_COS_2" {
            loc = "22..20"
            type = "binary"
            desc = "Mask for connection ID. Value 1 for class of service 2. 0 = disable masking. 1 = mask connection ID bit 0. 2= mask connection ID bits 1:0. 3= mask connection ID bits 2:0. 4 = mask connection ID bits 3:0. 5 = mask connection ID bits 4:0. 6 = mask connection ID bits 5:0. 7 = mask connection ID bits 6:0."
        }
        "REG_CONNID_2_COS_2" {
            loc = "19..12"
            type = "binary"
            desc = "Connection ID value 2 for class of service 2."
        }
        "REG_MSK_2_COS_2" {
            loc = "11..10"
            type = "binary"
            desc = "Mask for connection ID. Value 2 for class of service 2. 0 = disable masking. 1 = mask connection ID bit 0. 2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0."
        }
        "REG_CONNID_3_COS_2" {
            loc = "9..2"
            type = "binary"
            desc = "Connection ID value 3 for class of service 2."
        }
        "REG_MSK_3_COS_2" {
            loc = "1..0"
            type = "binary"
            desc = "Mask for connection ID. Value 3 for class of service 2. 0 = disable masking. 1 = mask connection ID bit 0. 2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0."
        }
    }
    "CPSW_ALE_CONTROL__bitfield" {
        "ENABLE_ALE" {
            loc = "31..31"
            type = "binary"
            desc = "Enable ALE -    0 - Drop all packets   1 - Enable ALE packet processing"
        }
        "CLEAR_TABLE" {
            loc = "30..30"
            type = "binary"
            desc = "Clear ALE address table - Setting this bit causes the ALE hardware to  write all table bit values to zero.  Software must perform a clear table  operation as part of the ALE setup/configuration process.  Setting this  bit causes all ALE accesses to be held up for 64 clocks while the clear is  performed.  Access to all ALE registers will be blocked (wait states) until  the 64 clocks have completed.  This bit cannot be read as one because  the read is blocked until the clear table is completed at which time this bit  is cleared to zero."
        }
        "AGE_OUT_NOW" {
            loc = "29..29"
            type = "binary"
            desc = "Age Out Address Table Now - Setting this bit causes the ALE hardware  to remove (free up) any ageable table entry that does not have a set  touch bit.   This bit is cleared when the age out process has completed.   This bit may be read.  The age out process takes 4096 clocks best case  (no ale packet processing during ageout) and 66550 clocks absolute  worst case."
        }
        "EN_P0_UNI_FLOOD" {
            loc = "8..8"
            type = "binary"
            desc = "Enable Port 0 (Host Port) unicast flood   0 - do not flood unknown unicast packets to host port (p0)   1 - flood unknown unicast packets to host port (p0)"
        }
        "LEARN_NO_VID" {
            loc = "7..7"
            type = "binary"
            desc = "Learn No VID -    0 - VID is learned with the source address   1 - VID is not learned with the source address (source address is not         tied to VID)."
        }
        "EN_VID0_MODE" {
            loc = "6..6"
            type = "binary"
            desc = "Enable VLAN ID = 0 Mode   0 - Process the packet with VID = PORT_VLAN[11:0].   1 - Process the packet with VID = 0."
        }
        "ENABLE_OUI_DENY" {
            loc = "5..5"
            type = "binary"
            desc = "Enable OUI Deny Mode - When set this bit indicates that a packet with a  non OUI table entry matching source address will be dropped to the host  unless the destination address matches a multicast table entry with the  super bit set."
        }
        "BYPASS" {
            loc = "4..4"
            type = "binary"
            desc = "ALE Bypass - When set, all packets received on ports 0 and 1 are sent  to the host (only to the host)."
        }
        "RATE_LIMIT_TX" {
            loc = "3..3"
            type = "binary"
            desc = "Rate Limit Transmit mode -   0 - Broadcast and multicast rate limit counters are received port based   1 - Broadcast and multicast rate limit counters are transmit port based."
        }
        "VLAN_AWARE" {
            loc = "2..2"
            type = "binary"
            desc = "ALE VLAN Aware - Determines what is done if VLAN not found.   0 - Flood if VLAN not found   1 - Drop packet if VLAN not found"
        }
        "ENABLE_AUTH_MODE" {
            loc = "1..1"
            type = "binary"
            desc = "Enable MAC Authorization Mode - Mac authorization mode requires that  all table entries be made by the host software.  There are no learned  address in authorization mode and the packet will be dropped if the  source address is not found (and the destination address is not a  multicast address with the super table entry bit set).     0 - The ALE is not in MAC authorization mode   1 - The ALE is in MAC authorization mode"
        }
        "ENABLE_RATE_LIMIT" {
            loc = "0..0"
            type = "binary"
            desc = "Enable Broadcast and Multicast Rate Limit   0 - Broadcast/Multicast rates not limited   1 - Broadcast/Multicast packet reception limited to the port control  register rate limit fields."
        }
    }
    "CPSW_ALE_IDVER__bitfield" {
        "IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "ALE Identification Value"
        }
        "MAJ_VER" {
            loc = "15..8"
            type = "binary"
            desc = "ALE Major Version Value"
        }
        "MINOR_VER" {
            loc = "7..0"
            type = "binary"
            desc = "ALE Minor Version Value"
        }
    }
    "CPSW_ALE_PORTCTL5__bitfield" {
        "BCAST_LIMIT" {
            loc = "31..24"
            type = "binary"
            desc = "Broadcast Packet Rate Limit -   Each prescale pulse loads this field into the port broadcast rate limit  counter.   The port counters are decremented with each packet received  or transmitted depending on whether the mode is transmit or receive.  If  the counters decrement to zero, then further packets are rate limited until  the next prescale pulse.  Broadcast rate limiting is enabled by a non-zero  value in this field"
        }
        "MCAST_LIMIT" {
            loc = "23..16"
            type = "binary"
            desc = "Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit  counter.   The port counters are decremented with each packet received  or transmitted depending on whether the mode is transmit or receive.  If  the counters decrement to zero, then further packets are rate limited until  the next prescale pulse.  Multicast rate limiting is enabled by a non-zero  value in this field."
        }
        "NO_SA_UPDATE" {
            loc = "5..5"
            type = "binary"
            desc = "No Souce Address Update - When set the port is disabled from  updating the source port number in an ALE table entry."
        }
        "NO_LEARN" {
            loc = "4..4"
            type = "binary"
            desc = "No Learn Mode - When set the port is disabled from learning an  address."
        }
        "VID_INGRESS_CHECK" {
            loc = "3..3"
            type = "binary"
            desc = "VLAN ID Ingress Check - If VLAN not found then drop the packet.   Packets with an unknown (default) VLAN will be dropped."
        }
        "DROP_UNTAGGED" {
            loc = "2..2"
            type = "binary"
            desc = "Drop Untagged Packets - Drop non-VLAN tagged ingress packets."
        }
        "PORT_STATE" {
            loc = "1..0"
            type = "binary"
            desc = "Port State   0 - Disabled   1 - Blocked   2 - Learn"
        }
    }
    "CPSW_ALE_PORTCTL__bitfield" {
        "BCAST_LIMIT" {
            loc = "31..24"
            type = "binary"
            desc = "Broadcast Packet Rate Limit -   Each prescale pulse loads this field into the port broadcast rate limit  counter.   The port counters are decremented with each packet received  or transmitted depending on whether the mode is transmit or receive.  If  the counters decrement to zero, then further packets are rate limited until  the next prescale pulse.  Broadcast rate limiting is enabled by a non-zero  value in this field"
        }
        "MCAST_LIMIT" {
            loc = "23..16"
            type = "binary"
            desc = "Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit  counter.   The port counters are decremented with each packet received  or transmitted depending on whether the mode is transmit or receive.  If  the counters decrement to zero, then further packets are rate limited until  the next prescale pulse.  Multicast rate limiting is enabled by a non-zero  value in this field."
        }
        "NO_SA_UPDATE" {
            loc = "5..5"
            type = "binary"
            desc = "No Souce Address Update - When set the port is disabled from  updating the source port number in an ALE table entry."
        }
        "NO_LEARN" {
            loc = "4..4"
            type = "binary"
            desc = "No Learn Mode - When set the port is disabled from learning an  address."
        }
        "VID_INGRESS_CHECK" {
            loc = "3..3"
            type = "binary"
            desc = "VLAN ID Ingress Check - If VLAN not found then drop the packet.   Packets with an unknown (default) VLAN will be dropped."
        }
        "DROP_UNTAGGED" {
            loc = "2..2"
            type = "binary"
            desc = "Drop Untagged Packets - Drop non-VLAN tagged ingress packets."
        }
        "PORT_STATE" {
            loc = "1..0"
            type = "binary"
            desc = "Port State   0 - Disabled   1 - Blocked   2 - Learn   3 - Forward"
        }
    }
    "CPSW_ALE_PRESCALE__bitfield" {
        "PRESCALE" {
            loc = "19..0"
            type = "binary"
            desc = "ALE Prescale Register - The input clock is divided by this value for use  in the multicast/broadcast rate limiters.  The minimum operating value is  0x10.  The prescaler is off when the value is zero."
        }
    }
    "CPSW_ALE_TBLCTL__bitfield" {
        "WRITE_RDZ" {
            loc = "31..31"
            type = "binary"
            desc = "Write Bit - This bit is always read as zero. Writing a 1 to this bit causes the three table word register values to be  written to the entry_pointer  location in the address table.   Writing a 0 to this bit causes the three table word register values to be  loaded from the entry_pointer location in the address table so that they  may be subsequently read.   A read of any ALE address location will be stalled until the read or write  has completed."
        }
        "ENTRY_POINTER" {
            loc = "9..0"
            type = "binary"
            desc = "Table Entry Pointer -  The entry_pointer contains the table entry value  that will be read/written with accesses to the table word registers."
        }
    }
    "CPSW_ALE_TBLW0__bitfield" {
        "ENTRY31_0" {
            loc = "31..0"
            type = "binary"
            desc = "Table entry bits 31:0"
        }
    }
    "CPSW_ALE_TBLW1__bitfield" {
        "ENTRY63_32" {
            loc = "31..0"
            type = "binary"
            desc = "Table entry bits 63:32"
        }
    }
    "CPSW_ALE_TBLW2__bitfield" {
        "ENTRY71-64" {
            loc = "7..0"
            type = "binary"
            desc = "Table entry bits 71:64"
        }
    }
    "CPSW_ALE_UNKNOWN_VLAN__bitfield" {
        "UNKNOWN_FORCE_UNTAGGED_EGRESS" {
            loc = "29..24"
            type = "binary"
            desc = "Unknown VLAN Force Untagged Egress."
        }
        "UNKNOWN_REG_MCAST_FLOOD_MASK" {
            loc = "21..16"
            type = "binary"
            desc = "Unknown VLAN Registered Multicast Flood Mask"
        }
        "UNKNOWN_MCAST_FLOOD_MASK" {
            loc = "13..8"
            type = "binary"
            desc = "Unknown VLAN Multicast Flood Mask"
        }
        "UNKNOWN_VLAN_MEMBER_LIST" {
            loc = "5..0"
            type = "binary"
            desc = "Unknown VLAN Member List"
        }
    }
    "CPSW_CPDMA_CPDMA_EOI_VECTOR__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "DMA_EOI_VECTOR" {
            loc = "4..0"
            type = "binary"
            desc = "DMA End of Interrupt Vector - The EOI_VECTOR(4:0) pins reflect the value  written to this location one CLK cycle after a write to this location.  The  EOI_WR signal is asserted for a single clock cycle after a latency of two  CLK cycles when a write is performed to this location."
        }
    }
    "CPSW_CPDMA_CPDMA_IN_VECTOR__bitfield" {
        "DMA_IN_VECTOR" {
            loc = "31..0"
            type = "binary"
            desc = "DMA Input Vector - The value of DMA_In_Vector is reset to zero, but will  change to the IN_VECTOR bus value one clock after reset is deasserted.   Thereafter, this value will change to a new IN_VECTOR value one clock after  the IN_VECTOR value changes."
        }
    }
    "CPSW_CPDMA_CPDMA_SOFT_RESET__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset - Writing a one to this bit causes the CPDMA logic to be  reset.  Software reset occurs when the RX and TX DMA Controllers are in  an idle state to avoid locking up the VBUSP bus.  After writing a one to  this bit, it may be polled to determine if the reset has occurred.  If a one is  read, the reset has not yet occurred.  If a zero is read then reset has  occurred."
        }
    }
    "CPSW_CPDMA_DMACONTROL__bitfield" {
        "Reserved__1" {
            loc = "31..16"
            type = "binary"
        }
        "TX_RLIM" {
            loc = "15..8"
            type = "binary"
            desc = "Transmit Rate Limit Channel Bus   00000000 - no rate-limited channels   10000000 - channel 7 is rate-limited   11000000 - channels 7 downto 6 are rate-limited   11100000 - channels 7 downto 5 are rate-limited   11110000 - channels 7 downto 4 are rate-limited   11111000 - channels 7 downto 3 are rate-limited   11111100 - channels 7 downto 2 are rate-limited   11111110 - channels 7 downto 1 are rate-limited   11111111 - channels 7 downto 0 are rate-limited   all others invalid - this bus must be set msb towards lsb. tx_ptype must be set if any tx_rlim bit is set for fixed priority."
        }
        "Reserved__2" {
            loc = "7..5"
            type = "binary"
        }
        "RX_CEF" {
            loc = "4..4"
            type = "binary"
            desc = "RX Copy Error Frames Enable - Enables DMA overrun frames to be  transferred to memory (up to the point of overrun).  The overrun error bit will  be set in the frame EOP buffer descriptor.   Overrun frame data will be  filtered when rx_cef is not set.  Frames coming from the receive FIFO with  other error bits set are not effected by this bit.   0 - Frames containing overrun errors are filtered.   1 - Frames containing overrun errors are transferred to memory."
        }
        "CMD_IDLE" {
            loc = "3..3"
            type = "binary"
            desc = "Command Idle   0 - Idle not commanded   1 - Idle Commanded (read idle in DMAStatus)"
        }
        "RX_OFFLEN_BLOCK" {
            loc = "2..2"
            type = "binary"
            desc = "Receive Offset/Length word write block.   0 - Do not block the DMA writes to the receive buffer descriptor  offset/buffer length word.  The offset/buffer length word is written as  specified in CPPI 3.0.   1 - Block all CPDMA DMA controller writes to the receive buffer descriptor  offset/buffer length words during CPPI packet processing.  when this bit is  set, the CPDMA will never write the third word to any receive buffer  descriptor."
        }
        "RX_OWNERSHIP" {
            loc = "1..1"
            type = "binary"
            desc = "Receive Ownership Write Bit Value.  0 - The CPDMA writes the receive ownership bit to zero at the end of  packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the receive ownership bit to one at the end of packet  processing.  Users who do not use the ownership mechanism can use this  mode to preclude the necessity of software having to set this bit each time  the buffer descriptor is used."
        }
        "TX_PTYPE" {
            loc = "0..0"
            type = "binary"
            desc = "Transmit Queue Priority Type   0 - The queue uses a round robin scheme to select the next          channel for transmission.   1 - The queue uses a fixed (channel 7 highest priority) priority         scheme to select the next channel for transmission"
        }
    }
    "CPSW_CPDMA_DMASTATUS__bitfield" {
        "IDLE" {
            loc = "31..31"
            type = "binary"
            desc = "Idle Status Bit - Indicates when set that the CPDMA is not transferring a  packet on transmit or receive."
        }
        "Reserved__1" {
            loc = "30..24"
            type = "binary"
        }
        "TX_HOST_ERR_CODE" {
            loc = "23..20"
            type = "binary"
            desc = "TX Host Error Code - This field is set to indicate CPDMA detected TX DMA  related host errors.  The host should read this field after a HOST_ERR_INT to  determine the error.  Host error Interrupts require hardware reset in order to  recover.  A zero packet length is an error, but it is not detected. 0000 - No error 0001 - SOP error. 0010 - Ownership bit not set in SOP buffer. 0011 - Zero Next Buffer Descriptor Pointer Without EOP 0100 - Zero Buffer Pointer. 0101 - Zero Buffer Length 0110 - Packet Length Error (sum of buffers is less than packet length) 0111 - reserved ... 1111 - reserved"
        }
        "Reserved__2" {
            loc = "19..19"
            type = "binary"
        }
        "TX_ERR_CH" {
            loc = "18..16"
            type = "binary"
            desc = "TX Host Error Channel - This field indicates which TX channel (if applicable)  the host error occurred on.  This field is cleared to zero on a host read.   000 - The host error occurred on TX channel 0   ...    111 - The host error occurred on TX channel 7"
        }
        "RX_HOST_ERR_CODE" {
            loc = "15..12"
            type = "binary"
            desc = "RX Host Error Code - This field is set to indicate CPDMA detected RX DMA  related host errors.  The host should read this field after a HOST_ERR_INT to  determine the error.  Host error Interrupts require hardware reset in order to  recover. 0000 - No error 0001 - reserved 0010 - Ownership bit not set in input buffer. 0011 - reserved 0100 - Zero Buffer Pointer. 0101 - Zero buffer length on non-SOP descriptor 0110 - SOP buffer length not greater than offset ... 1111 - reserved"
        }
        "Reserved__3" {
            loc = "11..11"
            type = "binary"
        }
        "RX_ERR_CH" {
            loc = "10..8"
            type = "binary"
            desc = "RX Host Error Channel - This field indicates which RX channel the host error  occurred on.  This field is cleared to zero on a host read.   000 - The host error occurred on RX channel 0   ...    111 - The host error occurred on RX channel 7"
        }
        "Reserved__4" {
            loc = "7..0"
            type = "binary"
        }
    }
    "CPSW_CPDMA_DMA_INTMASK_CLEAR__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "HOST_ERR_INT_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "Host Error Interrupt Mask - Write one to disable interrupt."
        }
        "STAT_INT_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "Statistics Interrupt Mask -   Write one to disable interrupt."
        }
    }
    "CPSW_CPDMA_DMA_INTMASK_SET__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "HOST_ERR_INT_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "Host Error Interrupt Mask - Write one to enable interrupt."
        }
        "STAT_INT_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "Statistics Interrupt Mask -   Write one to enable interrupt."
        }
    }
    "CPSW_CPDMA_DMA_INTSTAT_MASKED__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "HOST_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "Host Pending Interrupt - masked interrupt read."
        }
        "STAT_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "Statistics Pending Interrupt - masked interrupt read."
        }
    }
    "CPSW_CPDMA_DMA_INTSTAT_RAW__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "HOST_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "Host Pending Interrupt - raw int read (before mask)."
        }
        "STAT_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "Statistics Pending Interrupt - raw int read (before mask)."
        }
    }
    "CPSW_CPDMA_RX_BUFFER_OFFSET__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX_BUFFER_OFFSET" {
            loc = "15..0"
            type = "binary"
            desc = "Receive Buffer Offset Value - The rx_buffer_offset will be written by the port  into each frame SOP buffer descriptor buffer_offset field.  The frame data  will begin after the rx_buffer_offset value of bytes.  A value of 0x0000  indicates that there are no unused bytes at the beginning of the data and that  valid data begins on the first byte of the buffer.  A value of 0x000F (decimal  15) indicates that the first 15 bytes of the buffer are to be ignored by the port  and that valid buffer data starts on byte 16 of the buffer.  This value is used  for all channels."
        }
    }
    "CPSW_CPDMA_RX_CONTROL__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "RX_EN" {
            loc = "0..0"
            type = "binary"
            desc = "RX DMA Enable   0 - Disabled   1 - Enabled"
        }
    }
    "CPSW_CPDMA_RX_FREEBUFFER__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX_FREEBUFFER" {
            loc = "15..0"
            type = "binary"
            desc = "Rx Free Buffer Count - This field contains the count of free buffers  available.  The rx_pendthresh value is compared with this field to  determine if the receive threshold pending interrupt should be asseted (if  enabled).  This is a write to increment field.  This field rolls over to zero on  overflow. If receive threshold pending interrupts are used, the host must initialize this  field to the number of available buffers (one register per channel).  The port  decrements (by the number of buffers in the received frame) the  associated channel register for each received frame.  This is a write to  increment field.  The host must write this field with the number of buffers  that have been freed due to host processing."
        }
    }
    "CPSW_CPDMA_RX_IDVER__bitfield" {
        "RX_IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "RX Identification Value"
        }
        "RX_MAJOR_VER" {
            loc = "15..8"
            type = "binary"
            desc = "RX Major Version Value"
        }
        "RX_MINOR_VER" {
            loc = "7..0"
            type = "binary"
            desc = "RX Minor Version Value"
        }
    }
    "CPSW_CPDMA_RX_INTMASK_CLEAR__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX7_THRESH_PEND_MASK" {
            loc = "15..15"
            type = "binary"
            desc = "RX Channel 7 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX6_THRESH_PEND_MASK" {
            loc = "14..14"
            type = "binary"
            desc = "RX Channel 6 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX5_THRESH_PEND_MASK" {
            loc = "13..13"
            type = "binary"
            desc = "RX Channel 5 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX4_THRESH_PEND_MASK" {
            loc = "12..12"
            type = "binary"
            desc = "RX Channel 4 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX3_THRESH_PEND_MASK" {
            loc = "11..11"
            type = "binary"
            desc = "RX Channel 3 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX2_THRESH_PEND_MASK" {
            loc = "10..10"
            type = "binary"
            desc = "RX Channel 2 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX1_THRESH_PEND_MASK" {
            loc = "9..9"
            type = "binary"
            desc = "RX Channel 1 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX0_THRESH_PEND_MASK" {
            loc = "8..8"
            type = "binary"
            desc = "RX Channel 0 Threshold Pending Int. Mask - Write one to disable Int."
        }
        "RX7_PEND_MASK" {
            loc = "7..7"
            type = "binary"
            desc = "RX Channel 7 Pending Int. Mask - Write one to disable Int."
        }
        "RX6_PEND_MASK" {
            loc = "6..6"
            type = "binary"
            desc = "RX Channel 6 Pending Int. Mask - Write one to disable Int."
        }
        "RX5_PEND_MASK" {
            loc = "5..5"
            type = "binary"
            desc = "RX Channel 5 Pending Int. Mask - Write one to disable Int."
        }
        "RX4_PEND_MASK" {
            loc = "4..4"
            type = "binary"
            desc = "RX Channel 4 Pending Int. Mask - Write one to disable Int."
        }
        "RX3_PEND_MASK" {
            loc = "3..3"
            type = "binary"
            desc = "RX Channel 3 Pending Int. Mask - Write one to disable Int."
        }
        "RX2_PEND_MASK" {
            loc = "2..2"
            type = "binary"
            desc = "RX Channel 2 Pending Int. Mask - Write one to disable Int."
        }
        "RX1_PEND_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "RX Channel 1 Pending Int. Mask - Write one to disable Int."
        }
        "RX0_PEND_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "RX Channel 0 Pending Int. Mask - Write one to disable Int."
        }
    }
    "CPSW_CPDMA_RX_INTMASK_SET__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX7_THRESH_PEND_MASK" {
            loc = "15..15"
            type = "binary"
            desc = "RX Channel 7 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX6_THRESH_PEND_MASK" {
            loc = "14..14"
            type = "binary"
            desc = "RX Channel 6 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX5_THRESH_PEND_MASK" {
            loc = "13..13"
            type = "binary"
            desc = "RX Channel 5 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX4_THRESH_PEND_MASK" {
            loc = "12..12"
            type = "binary"
            desc = "RX Channel 4 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX3_THRESH_PEND_MASK" {
            loc = "11..11"
            type = "binary"
            desc = "RX Channel 3 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX2_THRESH_PEND_MASK" {
            loc = "10..10"
            type = "binary"
            desc = "RX Channel 2 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX1_THRESH_PEND_MASK" {
            loc = "9..9"
            type = "binary"
            desc = "RX Channel 1 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX0_THRESH_PEND_MASK" {
            loc = "8..8"
            type = "binary"
            desc = "RX Channel 0 Threshold Pending Int. Mask - Write one to enable Int."
        }
        "RX7_PEND_MASK" {
            loc = "7..7"
            type = "binary"
            desc = "RX Channel 7 Pending Int. Mask - Write one to enable Int."
        }
        "RX6_PEND_MASK" {
            loc = "6..6"
            type = "binary"
            desc = "RX Channel 6 Pending Int. Mask - Write one to enable Int."
        }
        "RX5_PEND_MASK" {
            loc = "5..5"
            type = "binary"
            desc = "RX Channel 5 Pending Int. Mask - Write one to enable Int."
        }
        "RX4_PEND_MASK" {
            loc = "4..4"
            type = "binary"
            desc = "RX Channel 4 Pending Int. Mask - Write one to enable Int."
        }
        "RX3_PEND_MASK" {
            loc = "3..3"
            type = "binary"
            desc = "RX Channel 3 Pending Int. Mask - Write one to enable Int."
        }
        "RX2_PEND_MASK" {
            loc = "2..2"
            type = "binary"
            desc = "RX Channel 2 Pending Int. Mask - Write one to enable Int."
        }
        "RX1_PEND_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "RX Channel 1 Pending Int. Mask - Write one to enable Int."
        }
        "RX0_PEND_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "RX Channel 0 Pending Int. Mask - Write one to enable Int."
        }
    }
    "CPSW_CPDMA_RX_INTSTAT_MASKED__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX7_THRESH_PEND" {
            loc = "15..15"
            type = "binary"
            desc = "RX7_THRESH_PEND masked int read."
        }
        "RX6_THRESH_PEND" {
            loc = "14..14"
            type = "binary"
            desc = "RX6_THRESH_PEND masked int read."
        }
        "RX5_THRESH_PEND" {
            loc = "13..13"
            type = "binary"
            desc = "RX5_THRESH_PEND masked int read."
        }
        "RX4_THRESH_PEND" {
            loc = "12..12"
            type = "binary"
            desc = "RX4_THRESH_PEND masked int read."
        }
        "RX3_THRESH_PEND" {
            loc = "11..11"
            type = "binary"
            desc = "RX3_THRESH_PEND masked int read."
        }
        "RX2_THRESH_PEND" {
            loc = "10..10"
            type = "binary"
            desc = "RX2_THRESH_PEND masked int read."
        }
        "RX1_THRESH_PEND" {
            loc = "9..9"
            type = "binary"
            desc = "RX1_THRESH_PEND masked int read."
        }
        "RX0_THRESH_PEND" {
            loc = "8..8"
            type = "binary"
            desc = "RX0_THRESH_PEND masked int read."
        }
        "RX7_PEND" {
            loc = "7..7"
            type = "binary"
            desc = "RX7_PEND masked int read."
        }
        "RX6_PEND" {
            loc = "6..6"
            type = "binary"
            desc = "RX6_PEND masked int read."
        }
        "RX5_PEND" {
            loc = "5..5"
            type = "binary"
            desc = "RX5_PEND masked int read."
        }
        "RX4_PEND" {
            loc = "4..4"
            type = "binary"
            desc = "RX4_PEND masked int read."
        }
        "RX3_PEND" {
            loc = "3..3"
            type = "binary"
            desc = "RX3_PEND masked int read."
        }
        "RX2_PEND" {
            loc = "2..2"
            type = "binary"
            desc = "RX2_PEND masked int read."
        }
        "RX1_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "RX1_PEND masked int read."
        }
        "RX0_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "RX0_PEND masked int read."
        }
    }
    "CPSW_CPDMA_RX_INTSTAT_RAW__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "RX7_THRESH_PEND" {
            loc = "15..15"
            type = "binary"
            desc = "RX7_THRESH_PEND raw int read (before mask)."
        }
        "RX6_THRESH_PEND" {
            loc = "14..14"
            type = "binary"
            desc = "RX6_THRESH_PEND raw int read (before mask)."
        }
        "RX5_THRESH_PEND" {
            loc = "13..13"
            type = "binary"
            desc = "RX5_THRESH_PEND raw int read (before mask)."
        }
        "RX4_THRESH_PEND" {
            loc = "12..12"
            type = "binary"
            desc = "RX4_THRESH_PEND raw int read (before mask)."
        }
        "RX3_THRESH_PEND" {
            loc = "11..11"
            type = "binary"
            desc = "RX3_THRESH_PEND raw int read (before mask)."
        }
        "RX2_THRESH_PEND" {
            loc = "10..10"
            type = "binary"
            desc = "RX2_THRESH_PEND raw int read (before mask)."
        }
        "RX1_THRESH_PEND" {
            loc = "9..9"
            type = "binary"
            desc = "RX1_THRESH_PEND raw int read (before mask)."
        }
        "RX0_THRESH_PEND" {
            loc = "8..8"
            type = "binary"
            desc = "RX0_THRESH_PEND raw int read (before mask)."
        }
        "RX7_PEND" {
            loc = "7..7"
            type = "binary"
            desc = "RX7_PEND raw int read (before mask)."
        }
        "RX6_PEND" {
            loc = "6..6"
            type = "binary"
            desc = "RX6_PEND raw int read (before mask)."
        }
        "RX5_PEND" {
            loc = "5..5"
            type = "binary"
            desc = "RX5_PEND raw int read (before mask)."
        }
        "RX4_PEND" {
            loc = "4..4"
            type = "binary"
            desc = "RX4_PEND raw int read (before mask)."
        }
        "RX3_PEND" {
            loc = "3..3"
            type = "binary"
            desc = "RX3_PEND raw int read (before mask)."
        }
        "RX2_PEND" {
            loc = "2..2"
            type = "binary"
            desc = "RX2_PEND raw int read (before mask)."
        }
        "RX1_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "RX1_PEND raw int read (before mask)."
        }
        "RX0_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "RX0_PEND raw int read (before mask)."
        }
    }
    "CPSW_CPDMA_RX_PENDTHRESH__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "RX_PENDTHRESH" {
            loc = "7..0"
            type = "binary"
            desc = "Rx Flow Threshold - This field contains the threshold value for issuing  receive threshold pending interrupts (when enabled)."
        }
    }
    "CPSW_CPDMA_RX_TEARDOWN__bitfield" {
        "RX_TDN_RDY" {
            loc = "31..31"
            type = "binary"
            desc = "Teardown Ready - read as zero, but is always assumed to be one (unused)."
        }
        "Reserved" {
            loc = "30..3"
            type = "binary"
        }
        "RX_TDN_CH" {
            loc = "2..0"
            type = "binary"
            desc = "Rx Teardown Channel -Receive channel teardown is commanded by writing  the encoded value of the receive channel to be torn down.  The teardown  register is read as zero.   000 - teardown receive channel 0    ...   111 - teardown receive channel 7"
        }
    }
    "CPSW_CPDMA_TX_CONTROL__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TX_EN" {
            loc = "0..0"
            type = "binary"
            desc = "TX Enable   0 - Disabled   1 - Enabled"
        }
    }
    "CPSW_CPDMA_TX_IDVER__bitfield" {
        "TX_IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "TX Identification Value"
        }
        "TX_MAJOR_VER" {
            loc = "15..8"
            type = "binary"
            desc = "TX Major Version Value - The value read is the major version number"
        }
        "TX_MINOR_VER" {
            loc = "7..0"
            type = "binary"
            desc = "TX Minor Version Value - The value read is the minor version number"
        }
    }
    "CPSW_CPDMA_TX_INTMASK_CLEAR__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "TX7_MASK" {
            loc = "7..7"
            type = "binary"
            desc = "TX Channel 7 Mask - Write one to disable interrupt."
        }
        "TX6_MASK" {
            loc = "6..6"
            type = "binary"
            desc = "TX Channel 6 Mask - Write one to disable interrupt."
        }
        "TX5_MASK" {
            loc = "5..5"
            type = "binary"
            desc = "TX Channel 5 Mask - Write one to disable interrupt."
        }
        "TX4_MASK" {
            loc = "4..4"
            type = "binary"
            desc = "TX Channel 4 Mask - Write one to disable interrupt."
        }
        "TX3_MASK" {
            loc = "3..3"
            type = "binary"
            desc = "TX Channel 3 Mask - Write one to disable interrupt."
        }
        "TX2_MASK" {
            loc = "2..2"
            type = "binary"
            desc = "TX Channel 2 Mask - Write one to disable interrupt."
        }
        "TX1_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "TX Channel 1 Mask - Write one to disable interrupt."
        }
        "TX0_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "TX Channel 0 Mask - Write one to disable interrupt."
        }
    }
    "CPSW_CPDMA_TX_INTMASK_SET__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "TX7_MASK" {
            loc = "7..7"
            type = "binary"
            desc = "TX Channel 7 Mask - Write one to enable interrupt."
        }
        "TX6_MASK" {
            loc = "6..6"
            type = "binary"
            desc = "TX Channel 6 Mask - Write one to enable interrupt."
        }
        "TX5_MASK" {
            loc = "5..5"
            type = "binary"
            desc = "TX Channel 5 Mask - Write one to enable interrupt."
        }
        "TX4_MASK" {
            loc = "4..4"
            type = "binary"
            desc = "TX Channel 4 Mask - Write one to enable interrupt."
        }
        "TX3_MASK" {
            loc = "3..3"
            type = "binary"
            desc = "TX Channel 3 Mask - Write one to enable interrupt."
        }
        "TX2_MASK" {
            loc = "2..2"
            type = "binary"
            desc = "TX Channel 2 Mask - Write one to enable interrupt."
        }
        "TX1_MASK" {
            loc = "1..1"
            type = "binary"
            desc = "TX Channel 1 Mask - Write one to enable interrupt."
        }
        "TX0_MASK" {
            loc = "0..0"
            type = "binary"
            desc = "TX Channel 0 Mask - Write one to enable interrupt."
        }
    }
    "CPSW_CPDMA_TX_INTSTAT_MASKED__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "TX7_PEND" {
            loc = "7..7"
            type = "binary"
            desc = "TX7_PEND masked interrupt read."
        }
        "TX6_PEND" {
            loc = "6..6"
            type = "binary"
            desc = "TX6_PEND masked interrupt read."
        }
        "TX5_PEND" {
            loc = "5..5"
            type = "binary"
            desc = "TX5_PEND masked interrupt read."
        }
        "TX4_PEND" {
            loc = "4..4"
            type = "binary"
            desc = "TX4_PEND masked interrupt read."
        }
        "TX3_PEND" {
            loc = "3..3"
            type = "binary"
            desc = "TX3_PEND masked interrupt read."
        }
        "TX2_PEND" {
            loc = "2..2"
            type = "binary"
            desc = "TX2_PEND masked interrupt read."
        }
        "TX1_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "TX1_PEND masked interrupt read."
        }
        "TX0_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "TX0_PEND masked interrupt read."
        }
    }
    "CPSW_CPDMA_TX_INTSTAT_RAW__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "TX7_PEND" {
            loc = "7..7"
            type = "binary"
            desc = "TX7_PEND raw int read (before mask)."
        }
        "TX6_PEND" {
            loc = "6..6"
            type = "binary"
            desc = "TX6_PEND raw int read (before mask)."
        }
        "TX5_PEND" {
            loc = "5..5"
            type = "binary"
            desc = "TX5_PEND raw int read (before mask)."
        }
        "TX4_PEND" {
            loc = "4..4"
            type = "binary"
            desc = "TX4_PEND raw int read (before mask)."
        }
        "TX3_PEND" {
            loc = "3..3"
            type = "binary"
            desc = "TX3_PEND raw int read (before mask)."
        }
        "TX2_PEND" {
            loc = "2..2"
            type = "binary"
            desc = "TX2_PEND raw int read (before mask)."
        }
        "TX1_PEND" {
            loc = "1..1"
            type = "binary"
            desc = "TX1_PEND raw int read (before mask)."
        }
        "TX0_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "TX0_PEND raw int read (before mask)."
        }
    }
    "CPSW_CPDMA_TX_PRI_RATE__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "PRIN_IDLE_CNT" {
            loc = "29..16"
            type = "binary"
            desc = "Priority (7:0) idle count"
        }
        "Reserved__2" {
            loc = "15..14"
            type = "binary"
        }
        "PRIN_SEND_CNT" {
            loc = "13..0"
            type = "binary"
            desc = "Priority (7:0) send count"
        }
    }
    "CPSW_CPDMA_TX_TEARDOWN__bitfield" {
        "TX_TDN_RDY" {
            loc = "31..31"
            type = "binary"
            desc = "Tx Teardown Ready - read as zero, but is always assumed to be one  (unused)."
        }
        "Reserved" {
            loc = "30..3"
            type = "binary"
        }
        "TX_TDN_CH" {
            loc = "2..0"
            type = "binary"
            desc = "Tx Teardown Channel - Transmit channel teardown is commanded by writing  the encoded value of the transmit channel to be torn down.  The teardown  register is read as zero.   000 - teardown transmit channel 0    ...   111 - teardown transmit channel 7"
        }
    }
    "CPSW_PORT_P0_BLK_CNT__bitfield" {
        "P0_TX_BLK_CNT" {
            loc = "8..4"
            type = "binary"
            desc = "Port 0 Transmit Block Count Usage - This value is the number of blocks  allocated to the FIFO logical transmit queues."
        }
        "P0_RX_BLK_CNT" {
            loc = "3..0"
            type = "binary"
            desc = "Port 0 Receive Block Count Usage - This value is the number of blocks  allocated to the FIFO logical receive queues."
        }
    }
    "CPSW_PORT_P0_CONTROL__bitfield" {
        "P0_DLR_CPDMA_CH" {
            loc = "30..28"
            type = "binary"
            desc = "Port 0 DLR CPDMA Channel   This field indicates the CPDMA channel that DLR packets will be   received on."
        }
        "P0_PASS_PRI_TAGGED" {
            loc = "24..24"
            type = "binary"
            desc = "Port 0 Pass Priority Tagged   0 - Priority tagged packets have the zero VID replaced with the         input port P0_PORT_VLAN[11:0]   1 - Priority tagged packets are processed unchanged."
        }
        "P0_VLAN_LTYPE2_EN" {
            loc = "21..21"
            type = "binary"
            desc = "Port 0 VLAN LTYPE 2 enable 0 - disabled   1 - enabled"
        }
        "P0_VLAN_LTYPE1_EN" {
            loc = "20..20"
            type = "binary"
            desc = "Port 0 VLAN LTYPE 1 enable 0 - disabled   1 - enabled"
        }
        "P0_DSCP_PRI_EN" {
            loc = "16..16"
            type = "binary"
            desc = "Port 0 DSCP Priority Enable   0 - DSCP priority disabled   1 - DSCP priority enabled.  All non-tagged IPV4 packets have         their received packet priority determined by mapping the          6 TOS bits through the port DSCP priority mapping registers."
        }
    }
    "CPSW_PORT_P0_CPDMA_RX_CH_MAP__bitfield" {
        "P2_PRI3" {
            loc = "30..28"
            type = "binary"
            desc = "Port 2 Priority 3 packets go to this CPDMA Rx Channel"
        }
        "P2_PRI2" {
            loc = "26..24"
            type = "binary"
            desc = "Port 2 Priority 2 packets go to this CPDMA Rx Channel"
        }
        "P2_PRI1" {
            loc = "22..20"
            type = "binary"
            desc = "Port 2 Priority 1 packets go to this CPDMA Rx Channel"
        }
        "P2_PRI0" {
            loc = "18..16"
            type = "binary"
            desc = "Port 2 Priority 0 packets go to this CPDMA Rx Channel"
        }
        "P1_PRI3" {
            loc = "14..12"
            type = "binary"
            desc = "Port 1 Priority 3 packets go to this CPDMA Rx Channel"
        }
        "P1_PRI2" {
            loc = "10..8"
            type = "binary"
            desc = "Port 1 Priority 2 packets go to this CPDMA Rx Channel"
        }
        "P1_PRI1" {
            loc = "6..4"
            type = "binary"
            desc = "Port 1 Priority 1 packets go to this CPDMA Rx Channel"
        }
        "P1_PRI0" {
            loc = "2..0"
            type = "binary"
            desc = "Port 1 Priority 0 packets go to this CPDMA Rx Channel"
        }
    }
    "CPSW_PORT_P0_CPDMA_TX_PRI_MAP__bitfield" {
        "PRI7" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 7 - A packet pri of 0x7 is mapped (changed) to this header packet pri."
        }
        "PRI6" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 6 - A packet pri of 0x6 is mapped (changed) to this header packet pri."
        }
        "PRI5" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 5 - A packet pri of 0x5 is mapped (changed) to this header packet pri."
        }
        "PRI4" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 4 - A packet pri of 0x4 is mapped (changed) to this header packet pri."
        }
        "PRI3" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 3 - A packet pri of 0x3 is mapped (changed) to this header packet pri."
        }
        "PRI2" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 2 - A packet pri of 0x2 is mapped (changed) to this header packet pri."
        }
        "PRI1" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 1 - A packet pri of 0x1 is mapped (changed) to this header packet pri."
        }
        "PRI0" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 0 - A packet pri of 0x0 is mapped (changed) to this header packet pri."
        }
    }
    "CPSW_PORT_P0_MAX_BLKS__bitfield" {
        "P0_TX_MAX_BLKS" {
            loc = "8..4"
            type = "binary"
            desc = "Transmit FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical transmit priority  queues.  0x10 is the recommended value of p0_tx_max_blks.  Port 0  should remain in flow control mode. 0xe is the minimum value tx max blks."
        }
        "P0_RX_MAX_BLKS" {
            loc = "3..0"
            type = "binary"
            desc = "Receive FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical receive queue. 0x4 is the recommended value.  0x3 is the minimum value rx max blks and  0x6 is the maximum value."
        }
    }
    "CPSW_PORT_P0_TX_IN_CTL__bitfield" {
        "TX_RATE_EN" {
            loc = "23..20"
            type = "binary"
            desc = "Transmit FIFO Input Rate Enable"
        }
        "TX_IN_SEL" {
            loc = "17..16"
            type = "binary"
            desc = "Transmit FIFO Input Queue Type Select   00 - Normal priority mode   01 - Dual MAC mode   10 - Rate Limit mode   11 - reserved Note that Dual MAC mode is not compatible with escalation or shaping  because dual mac mode forces round robin priority on FIFO egress."
        }
        "TX_BLKS_REM" {
            loc = "15..12"
            type = "binary"
            desc = "Transmit FIFO Input Blocks to subtract in dual mac mode"
        }
        "TX_PRI_WDS" {
            loc = "9..0"
            type = "binary"
            desc = "Transmit FIFO Words in queue"
        }
    }
    "CPSW_PORT_P1_BLK_CNT__bitfield" {
        "P1_TX_BLK_CNT" {
            loc = "8..4"
            type = "binary"
            desc = "Port 1 Transmit Block Count Usage - This value is the number of blocks  allocated to the FIFO logical transmit queues."
        }
        "P1_RX_BLK_CNT" {
            loc = "3..0"
            type = "binary"
            desc = "Port 1 Receive Block Count Usage - This value is the number of blocks  allocated to the FIFO logical receive queues."
        }
    }
    "CPSW_PORT_P1_CONTROL__bitfield" {
        "P1_PASS_PRI_TAGGED" {
            loc = "24..24"
            type = "binary"
            desc = "Port 1 Pass Priority Tagged   0 - Priority tagged packets have the zero VID replaced with the         input port P1_PORT_VLAN[11:0]   1 - Priority tagged packets are processed unchanged."
        }
        "P1_VLAN_LTYPE2_EN" {
            loc = "21..21"
            type = "binary"
            desc = "Port 1 VLAN LTYPE 2 enable 0 - disabled   1 - VLAN LTYPE2 enabled on transmit and receive"
        }
        "P1_VLAN_LTYPE1_EN" {
            loc = "20..20"
            type = "binary"
            desc = "Port 1 VLAN LTYPE 1 enable 0 - disabled   1 - VLAN LTYPE1 enabled on transmit and receive"
        }
        "P1_DSCP_PRI_EN" {
            loc = "16..16"
            type = "binary"
            desc = "Port 1 DSCP Priority Enable   0 - DSCP priority disabled   1 - DSCP priority enabled.  All non-tagged IPV4 packets have         their received packet priority determined by mapping the          6 TOS bits through the port DSCP priority mapping registers."
        }
        "P1_TS_320" {
            loc = "14..14"
            type = "binary"
            desc = "Port 1 Time Sync Destination Port Number 320 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port             number 320 (decimal) is enabled."
        }
        "P1_TS_319" {
            loc = "13..13"
            type = "binary"
            desc = "Port 1 Time Sync Destination Port Number 319 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port             number 319 (decimal) is enabled."
        }
        "P1_TS_132" {
            loc = "12..12"
            type = "binary"
            desc = "Port 1 Time Sync Destination IP Address 132 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 132 (decimal) is enabled."
        }
        "P1_TS_131" {
            loc = "11..11"
            type = "binary"
            desc = "Port 1 Time Sync Destination IP Address 131 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 131 (decimal) is enabled."
        }
        "P1_TS_130" {
            loc = "10..10"
            type = "binary"
            desc = "Port 1 Time Sync Destination IP Address 130 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 130 (decimal) is enabled."
        }
        "P1_TS_129" {
            loc = "9..9"
            type = "binary"
            desc = "Port 1 Time Sync Destination IP Address 129 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 129 (decimal) is enabled."
        }
        "P1_TS_ANNEX_D_EN" {
            loc = "4..4"
            type = "binary"
            desc = "Port 1 Time Sync Annex D enable   0 - Annex D disabled   1 - Annex D enabled"
        }
        "P1_TS_LTYPE2_EN" {
            loc = "3..3"
            type = "binary"
            desc = "Port 1 Time Sync LTYPE 2 enable 0 - disabled   1 - enabled"
        }
        "P1_TS_LTYPE1_EN" {
            loc = "2..2"
            type = "binary"
            desc = "Port 1 Time Sync LTYPE 1 enable 0 - disabled   1 - enabled"
        }
        "P1_TS_TX_EN" {
            loc = "1..1"
            type = "binary"
            desc = "Port 1 Time Sync Transmit Enable 0 - disabled   1 - enabled"
        }
        "P1_TS_RX_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Port 1 Time Sync Receive Enable   0 - Port 1 Receive Time Sync disabled   1 - Port 1 Receive Time Sync enabled"
        }
    }
    "CPSW_PORT_P1_MAX_BLKS__bitfield" {
        "P1_TX_MAX_BLKS" {
            loc = "8..4"
            type = "binary"
            desc = "Transmit FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical transmit priority  queues.  0x11 is the recommended value of p1_tx_max_blks unless the  port is in fullduplex  flow control mode.  In flow control mode, the  p1_rx_max_blks will need to increase in order to accept the required run  out in fullduplex mode.  This value will need to decrease by the amount of  increase in p1_rx_max_blks.  0xe is the minimum value tx max blks."
        }
        "P1_RX_MAX_BLKS" {
            loc = "3..0"
            type = "binary"
            desc = "Receive FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical receive queue. This value must be greater than or equal to 0x3.  It should be increased In   fullduplex flow control mode to 0x5 or 0x6 depending on the required  runout space.  The p1_tx_max_blks value must be decreased by the  amount of increase in p1_rx_max_blks.  0x3 is the minimum value rx max  blks and 0x6 is the maximum value."
        }
    }
    "CPSW_PORT_P1_SA_HI__bitfield" {
        "MACSRCADDR_23_16" {
            loc = "31..24"
            type = "binary"
            desc = "Source Address bits 23:16 (byte 2)"
        }
        "MACSRCADDR_31_24" {
            loc = "23..16"
            type = "binary"
            desc = "Source Address bits 31:24 (byte 3)"
        }
        "MACSRCADDR_39_32" {
            loc = "15..8"
            type = "binary"
            desc = "Source Address bits 39:32 (byte 4)"
        }
        "MACSRCADDR_47_40" {
            loc = "7..0"
            type = "binary"
            desc = "Source Address bits 47:40 (byte 5)"
        }
    }
    "CPSW_PORT_P1_TS_SEQ_MTYPE__bitfield" {
        "P1_TS_SEQ_ID_OFFSET" {
            loc = "21..16"
            type = "binary"
            desc = "Port 1 Time Sync Sequence ID Offset   This is the number of octets that the sequence ID is offset in the tx    and rx time sync message header.  The minimum value is 6."
        }
        "P1_TS_MSG_TYPE_EN" {
            loc = "15..0"
            type = "binary"
            desc = "Port 1 Time Sync Message Type Enable -   Each bit in this field enables the corresponding message type in    receive and transmit time sync messages (Bit 0 enables message    type 0 etc.)."
        }
    }
    "CPSW_PORT_P2_BLK_CNT__bitfield" {
        "P2_TX_BLK_CNT" {
            loc = "8..4"
            type = "binary"
            desc = "Port 2 Transmit Block Count Usage - This value is the number of blocks  allocated to the FIFO logical transmit queues."
        }
        "P2_RX_BLK_CNT" {
            loc = "3..0"
            type = "binary"
            desc = "Port 2 Receive Block Count Usage - This value is the number of blocks  allocated to the FIFO logical receive queues."
        }
    }
    "CPSW_PORT_P2_CONTROL__bitfield" {
        "P2_PASS_PRI_TAGGED" {
            loc = "24..24"
            type = "binary"
            desc = "Port 2 Pass Priority Tagged   0 - Priority tagged packets have the zero VID replaced with the         input port P2_PORT_VLAN[11:0]   1 - Priority tagged packets are processed unchanged."
        }
        "P2_VLAN_LTYPE2_EN" {
            loc = "21..21"
            type = "binary"
            desc = "Port 2 VLAN LTYPE 2 enable 0 - disabled   1 - VLAN LTYPE2 enabled on transmit and receive"
        }
        "P2_VLAN_LTYPE1_EN" {
            loc = "20..20"
            type = "binary"
            desc = "Port 2 VLAN LTYPE 1 enable 0 - disabled   1 - VLAN LTYPE1 enabled on transmit and receive"
        }
        "P2_TS_129" {
            loc = "19..19"
            type = "binary"
            desc = "Port 2 Time Sync Destination IP Address 129 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 129 (decimal) is enabled."
        }
        "P2_DSCP_PRI_EN" {
            loc = "16..16"
            type = "binary"
            desc = "Port 0 DSCP Priority Enable   0 - DSCP priority disabled   1 - DSCP priority enabled.  All non-tagged IPV4 packets have         their received packet priority determined by mapping the          6 TOS bits through the port DSCP priority mapping registers."
        }
        "P2_TS_320" {
            loc = "14..14"
            type = "binary"
            desc = "Port 2 Time Sync Destination Port Number 320 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port             number 320 (decimal) is enabled."
        }
        "P2_TS_319" {
            loc = "13..13"
            type = "binary"
            desc = "Port 2 Time Sync Destination Port Number 319 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port             number 319 (decimal) is enabled."
        }
        "P2_TS_132" {
            loc = "12..12"
            type = "binary"
            desc = "Port 2 Time Sync Destination IP Address 132 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 132 (decimal) is enabled."
        }
        "P2_TS_131" {
            loc = "11..11"
            type = "binary"
            desc = "Port 2 Time Sync Destination IP Address 131 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 131 (decimal) is enabled."
        }
        "P2_TS_130" {
            loc = "10..10"
            type = "binary"
            desc = "Port 2 Time Sync Destination IP Address 130 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address            number 130 (decimal) is enabled."
        }
        "P2_TS_ANNEX_D_EN" {
            loc = "4..4"
            type = "binary"
            desc = "Port 2 Time Sync Annex D enable   0 - Annex D disabled   1 - Annex D enabled"
        }
        "P2_TS_LTYPE2_EN" {
            loc = "3..3"
            type = "binary"
            desc = "Port 2 Time Sync LTYPE 2 enable 0 - disabled   1 - enabled"
        }
        "P2_TS_LTYPE1_EN" {
            loc = "2..2"
            type = "binary"
            desc = "Port 2 Time Sync LTYPE 1 enable 0 - disabled   1 - enabled"
        }
        "P2_TS_TX_EN" {
            loc = "1..1"
            type = "binary"
            desc = "Port 2 Time Sync Transmit Enable 0 - disabled   1 - enabled"
        }
        "P2_TS_RX_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Port 2 Time Sync Receive Enable   0 - Port 1 Receive Time Sync disabled   1 - Port 1 Receive Time Sync enabled"
        }
    }
    "CPSW_PORT_P2_MAX_BLKS__bitfield" {
        "P2_TX_MAX_BLKS" {
            loc = "8..4"
            type = "binary"
            desc = "Transmit FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical transmit priority  queues.  0x11 is the recommended value of p2_tx_max_blks unless the  port is in fullduplex  flow control mode.  In flow control mode, the  p2_rx_max_blks will need to increase in order to accept the required run  out in fullduplex mode.  This value will need to decrease by the amount of  increase in p2_rx_max_blks.  0xe is the minimum value tx max blks."
        }
        "P2_RX_MAX_BLKS" {
            loc = "3..0"
            type = "binary"
            desc = "Receive FIFO Maximum Blocks - This value is the maximum number of 1k  memory blocks that may be allocated to the FIFO's logical receive queue. This value must be greater than or equal to 0x3.  It should be increased In   fullduplex flow control mode to 0x5 or 0x6 depending on the required  runout space.  The p2_tx_max_blks value must be decreased by the  amount of increase in p2_rx_max_blks.  0x3 is the minimum value rx max  blks and 0x6 is the maximum value."
        }
    }
    "CPSW_PORT_P2_SA_HI__bitfield" {
        "MACSRCADDR_23_16" {
            loc = "31..24"
            type = "binary"
            desc = "Source Address bits 23:16 (byte 2)"
        }
        "MACSRCADDR_31_23" {
            loc = "23..16"
            type = "binary"
            desc = "Source Address bits 31:23 (byte 3)"
        }
        "MACSRCADDR_39_32" {
            loc = "15..8"
            type = "binary"
            desc = "Source Address bits 39:32 (byte 4)"
        }
        "MACSRCADDR_47_40" {
            loc = "7..0"
            type = "binary"
            desc = "Source Address bits 47:40 (byte 5)"
        }
    }
    "CPSW_PORT_P2_TS_SEQ_MTYPE__bitfield" {
        "P2_TS_SEQ_ID_OFFSET" {
            loc = "21..16"
            type = "binary"
            desc = "Port 2 Time Sync Sequence ID Offset   This is the number of octets that the sequence ID is offset in the tx    and rx time sync message header.  The minimum value is 6."
        }
        "P2_TS_MSG_TYPE_EN" {
            loc = "15..0"
            type = "binary"
            desc = "Port 2 Time Sync Message Type Enable -   Each bit in this field enables the corresponding message type in    receive and transmit time sync messages (Bit 0 enables message    type 0 etc.)."
        }
    }
    "CPSW_PORT_P_PORT_VLAN__bitfield" {
        "PORT_PRI" {
            loc = "15..13"
            type = "binary"
            desc = "Port VLAN Priority (7 is highest priority)"
        }
        "PORT_CFI" {
            loc = "12..12"
            type = "binary"
            desc = "Port CFI bit"
        }
        "PORT_VID" {
            loc = "11..0"
            type = "binary"
            desc = "Port VLAN ID"
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP0__bitfield" {
        "PRI7" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority."
        }
        "PRI6" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority."
        }
        "PRI5" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority."
        }
        "PRI4" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority."
        }
        "PRI3" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority."
        }
        "PRI2" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority."
        }
        "PRI1" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority."
        }
        "PRI0" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP1__bitfield" {
        "PRI15" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority."
        }
        "PRI14" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority."
        }
        "PRI13" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority."
        }
        "PRI12" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority."
        }
        "PRI11" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority."
        }
        "PRI10" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority."
        }
        "PRI9" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 9  - A packet TOS of 0d9 is mapped to this received packet priority."
        }
        "PRI8" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 8  - A packet TOS of 0d8 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP2__bitfield" {
        "PRI23" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority."
        }
        "PRI22" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority."
        }
        "PRI21" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority."
        }
        "PRI20" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority."
        }
        "PRI19" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority."
        }
        "PRI18" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority."
        }
        "PRI17" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority."
        }
        "PRI16" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP3__bitfield" {
        "PRI31" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority."
        }
        "PRI30" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority."
        }
        "PRI29" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority."
        }
        "PRI28" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority."
        }
        "PRI27" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority."
        }
        "PRI26" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority."
        }
        "PRI25" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority."
        }
        "PRI24" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP4__bitfield" {
        "PRI39" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority."
        }
        "PRI38" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority."
        }
        "PRI37" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority."
        }
        "PRI36" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority."
        }
        "PRI35" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority."
        }
        "PRI34" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority."
        }
        "PRI33" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority."
        }
        "PRI32" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP5__bitfield" {
        "PRI47" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority."
        }
        "PRI46" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority."
        }
        "PRI45" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority."
        }
        "PRI44" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority."
        }
        "PRI43" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority."
        }
        "PRI42" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority."
        }
        "PRI41" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority."
        }
        "PRI40" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP6__bitfield" {
        "PRI55" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority."
        }
        "PRI54" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority."
        }
        "PRI53" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority."
        }
        "PRI52" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority."
        }
        "PRI51" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority."
        }
        "PRI50" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority."
        }
        "PRI49" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority."
        }
        "PRI48" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_RX_DSCP_PRI_MAP7__bitfield" {
        "PRI63" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority."
        }
        "PRI62" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority."
        }
        "PRI61" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority."
        }
        "PRI60" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority."
        }
        "PRI59" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority."
        }
        "PRI58" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority."
        }
        "PRI57" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority."
        }
        "PRI56" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority."
        }
    }
    "CPSW_PORT_P_SA_LO__bitfield" {
        "MACSRCADDR_7_0" {
            loc = "15..8"
            type = "binary"
            desc = "Source Address Lower 8 bits (byte 0)"
        }
        "MACSRCADDR_15_8" {
            loc = "7..0"
            type = "binary"
            desc = "Source Address bits 15:8      (byte 1)"
        }
    }
    "CPSW_PORT_P_SEND_PERCENT__bitfield" {
        "PRI3_SEND_PERCENT" {
            loc = "22..16"
            type = "binary"
            desc = "Priority 3 Transmit Percentage - This percentage value is sent from FIFO  priority 3 (maximum) when the p1_pri3_shape_en is set (queue shaping  enabled).  This is the percentage of the wire that packets from priority 3  receive (which includes interpacket gap and preamble bytes).   If shaping is  enabled on this queue then this value must be between zero and 0d100 (not  inclusive)."
        }
        "PRI2_SEND_PERCENT" {
            loc = "14..8"
            type = "binary"
            desc = "Priority 2 Transmit Percentage - This percentage value is sent from FIFO  priority 2 (maximum) when the p1_pri2_shape_en is set (queue shaping  enabled).  This is the percentage of the wire that packets from priority 2  receive (which includes interpacket gap and preamble bytes).   If shaping is  enabled on this queue then this value must be between zero and 0d100 (not  inclusive)."
        }
        "PRI1_SEND_PERCENT" {
            loc = "6..0"
            type = "binary"
            desc = "Priority 1 Transmit Percentage - This percentage value is sent from FIFO  priority 1 (maximum) when the p1_pri1_shape_en is set (queue shaping  enabled).  This is the percentage of the wire that packets from priority 1  receive (which includes interpacket gap and preamble bytes).   If shaping is  enabled on this queue then this value must be between zero and 0d100 (not  inclusive)."
        }
    }
    "CPSW_PORT_P_TX_IN_CTL__bitfield" {
        "HOST_BLKS_REM" {
            loc = "27..24"
            type = "binary"
            desc = "Transmit FIFO Blocks that must be free before a non rate-limited CPDMA  channel can begin sending a packet to the FIFO."
        }
        "TX_RATE_EN" {
            loc = "23..20"
            type = "binary"
            desc = "Transmit FIFO Input Rate Enable"
        }
        "TX_IN_SEL" {
            loc = "17..16"
            type = "binary"
            desc = "Transmit FIFO Input Queue Type Select   00 - Normal priority mode   01 - reserved   10 - Rate Limit mode   11 - reserved"
        }
        "TX_BLKS_REM" {
            loc = "15..12"
            type = "binary"
            desc = "Transmit FIFO Input Blocks to subtract in dual mac mode and blocks to  subtract on non rate-limited traffic in rate-limit mode."
        }
        "TX_PRI_WDS" {
            loc = "9..0"
            type = "binary"
            desc = "Transmit FIFO Words in queue"
        }
    }
    "CPSW_PORT_P_TX_PRI_MAP__bitfield" {
        "PRI7" {
            loc = "29..28"
            type = "binary"
            desc = "Priority 7 - A packet header priority of 0x7 is given this switch queue pri."
        }
        "PRI6" {
            loc = "25..24"
            type = "binary"
            desc = "Priority 6 - A packet header priority of 0x6 is given this switch queue pri."
        }
        "PRI5" {
            loc = "21..20"
            type = "binary"
            desc = "Priority 5 - A packet header priority of 0x5 is given this switch queue pri."
        }
        "PRI4" {
            loc = "17..16"
            type = "binary"
            desc = "Priority 4 - A packet header priority of 0x4 is given this switch queue pri."
        }
        "PRI3" {
            loc = "13..12"
            type = "binary"
            desc = "Priority 3 - A packet header priority of 0x3 is given this switch queue pri."
        }
        "PRI2" {
            loc = "9..8"
            type = "binary"
            desc = "Priority 2 - A packet header priority of 0x2 is given this switch queue pri."
        }
        "PRI1" {
            loc = "5..4"
            type = "binary"
            desc = "Priority 1 - A packet header priority of 0x1 is given this switch queue pri."
        }
        "PRI0" {
            loc = "1..0"
            type = "binary"
            desc = "Priority 0 - A packet header priority of 0x0 is given this switch queue pri."
        }
    }
    "CPSW_SL_BOFFTEST__bitfield" {
        "Reserved__1" {
            loc = "31..31"
            type = "binary"
        }
        "PACEVAL" {
            loc = "30..26"
            type = "binary"
            desc = "Pacing Register Current Value. A non-zero value in this field indicates that  transmit pacing is active. A transmit frame collision or deferral causes paceval  to loaded with decimal 31, good frame transmissions (with no collisions or  deferrals) cause paceval to be decremented down to zero.  When paceval is  nonzero, the transmitter delays 4 IPGs between new frame transmissions after  each successfully transmitted frame that had no deferrals or collisions.   Transmit pacing helps reduce \"capture\" effects improving overall network  bandwidth."
        }
        "RNDNUM" {
            loc = "25..16"
            type = "binary"
            desc = "Backoff Random Number Generator - This field allows the Backoff Random  Number Generator to be read (or written in test mode only). This field can be  written only when mtest has previously been set. Reading this field returns the  generator's current value.  The value is reset to zero and begins counting on the  clock after the deassertion of reset."
        }
        "COLL_COUNT" {
            loc = "15..12"
            type = "binary"
            desc = "Collision Count - The number of collisions the current frame has experienced."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "TX_BACKOFF" {
            loc = "9..0"
            type = "binary"
            desc = "Backoff Count - This field allows the current value of the backoff counter to be  observed for test purposes.  This field is loaded automatically according to the  backoff algorithm, and is decremented by one for each slot time after the  collision."
        }
    }
    "CPSW_SL_IDVER__bitfield" {
        "IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "Rx Identification Value"
        }
        "Z" {
            loc = "15..11"
            type = "binary"
            desc = "Rx Z value (X.Y.Z)"
        }
        "X" {
            loc = "10..8"
            type = "binary"
            desc = "Rx X value (major)"
        }
        "Y" {
            loc = "7..0"
            type = "binary"
            desc = "Rx Y value (minor)"
        }
    }
    "CPSW_SL_MACCONTROL__bitfield" {
        "Reserved__1" {
            loc = "31..25"
            type = "binary"
        }
        "RX_CMF_EN" {
            loc = "24..24"
            type = "binary"
            desc = "RX Copy MAC Control Frames Enable - Enables MAC control frames to be  transferred to memory.  MAC control frames are normally acted upon (if  enabled), but not copied to memory.  MAC control frames that are pause  frames will be acted upon if enabled in the MacControl register, regardless  of the value of rx_cmf_en.  Frames transferred to memory due to  rx_cmf_en will have the control bit set in their EOP buffer descriptor.    0 - MAC control frames are filtered (but acted upon if enabled).   1 - MAC control frames are transferred to memory."
        }
        "RX_CSF_EN" {
            loc = "23..23"
            type = "binary"
            desc = "RX Copy Short Frames Enable - Enables frames or fragments shorter than  64 bytes to be copied to memory.  Frames transferred to memory due to  rx_csf_en will have the fragment or undersized bit set in their receive  footer.  Fragments are short frames that contain CRC/align/code errors and  undersized are short frames without errors.   0 - Short frames are filtered   1 - Short frames are transferred to memory."
        }
        "RX_CEF_EN" {
            loc = "22..22"
            type = "binary"
            desc = "RX Copy Error Frames Enable - Enables frames containing errors to be  transferred to memory.  The appropriate error bit will be set in the frame  receive footer.   Frames containing errors will be filtered when rx_cef _en is  not set.   0 - Frames containing errors are filtered.   1 - Frames containing errors are transferred to memory."
        }
        "TX_SHORT_GAP_LIM_EN" {
            loc = "21..21"
            type = "binary"
            desc = "Transmit Short Gap Limit Enable  When set this bit limits the number of short gap packets transmitted to  100ppm.  Each time a short gap packet is sent, a counter is loaded with  10,000 and decremented on each wireside clock.  Another short gap packet  will not be sent out until the counter decrements to zero.  This mode is  included to preclude the host from filling up the FIFO and sending every  packet out with short gap which would violate the maximum number of  packets per second allowed."
        }
        "Reserved__2" {
            loc = "20..19"
            type = "binary"
        }
        "EXT_EN" {
            loc = "18..18"
            type = "binary"
            desc = "Control Enable - Enables the fullduplex and gigabit mode to be selected  from the FULLDUPLEX_IN and GIG_IN input signals and not from the  fullduplex and gig bits in this register.  The FULLDUPLEX_MODE bit  reflects the actual fullduplex mode selected."
        }
        "GIG_FORCE" {
            loc = "17..17"
            type = "binary"
            desc = "Gigabit Mode Force - This bit is used to force the CPGMAC_SL into  gigabit mode if the input GMII_MTCLK has been stopped by the PHY."
        }
        "IFCTL_B" {
            loc = "16..16"
            type = "binary"
            desc = "Connects to the speed_in input of the respective RMII gasket. When using RMII mode:   0 - 10Mbps operation   1 - 100Mbps operation"
        }
        "IFCTL_A" {
            loc = "15..15"
            type = "binary"
            desc = "Connects to the speed_in input of the respective RMII gasket. When using RMII mode:   0 - 10Mbps operation   1 - 100Mbps operation"
        }
        "Reserved__3" {
            loc = "14..12"
            type = "binary"
        }
        "CMD_IDLE" {
            loc = "11..11"
            type = "binary"
            desc = "Command Idle   0 - Idle not commanded   1 - Idle Commanded (read idle in MacStatus)"
        }
        "TX_SHORT_GAP_EN" {
            loc = "10..10"
            type = "binary"
            desc = "Transmit Short Gap Enable   0 - Transmit with a short IPG is disabled   1 - Transmit with a short IPG (when TX_SHORT_GAP input is asserted) is              enabled."
        }
        "Reserved__4" {
            loc = "9..8"
            type = "binary"
        }
        "GIG" {
            loc = "7..7"
            type = "binary"
            desc = "Gigabit Mode -    0 - 10/100 mode   1 - Gigabit mode (full duplex only) The GIG_OUT output is the value of this bit."
        }
        "TX_PACE" {
            loc = "6..6"
            type = "binary"
            desc = "Transmit Pacing Enable   0 - Transmit Pacing Disabled   1 - Transmit Pacing Enabled"
        }
        "GMII_EN" {
            loc = "5..5"
            type = "binary"
            desc = "GMII Enable -    0 - GMII RX and TX held in reset.   1 - GMII RX and TX released from reset."
        }
        "TX_FLOW_EN" {
            loc = "4..4"
            type = "binary"
            desc = "Transmit Flow Control Enable -  Determines if incoming pause frames are  acted upon in full-duplex mode.  Incoming pause frames are not acted  upon in half-duplex mode regardless of this bit setting.  The  RX_MBP_Enable bits determine whether or not received pause frames are  transferred to memory.   0 - Transmit Flow Control Disabled.           Full-duplex mode - Incoming pause frames are not acted upon.   1 - Transmit Flow Control Enabled .           Full-duplex mode - Incoming pause frames are acted upon."
        }
        "RX_FLOW_EN" {
            loc = "3..3"
            type = "binary"
            desc = "Receive Flow Control Enable -    0 - Receive Flow Control Disabled         Half-duplex mode - No flow control generated collisions are sent.         Full-duplex mode - No outgoing pause frames are sent.   1 - Receive Flow Control Enabled         Half-duplex mode -  Collisions are initiated when receive                                          flow control is triggered.           Full-duplex mode -   Outgoing pause frames are sent when                                           receive flow control is triggered."
        }
        "MTEST" {
            loc = "2..2"
            type = "binary"
            desc = "Manufacturing Test mode - This bit must be set to allow writes to the   Backoff_Test and PauseTimer registers."
        }
        "LOOPBACK" {
            loc = "1..1"
            type = "binary"
            desc = "Loop Back Mode - Loopback mode forces internal fullduplex mode  regardless of whether the fullduplex bit is set or not.  The loopback bit  should be changed only when GMII_en is deasserted.   0 - Not looped back   1 - Loop Back Mode enabled"
        }
        "FULLDUPLEX" {
            loc = "0..0"
            type = "binary"
            desc = "Full Duplex mode - Gigabit mode forces fullduplex mode regardless of  whether the fullduplex bit is set or not.  The FULLDUPLEX_OUT output is  the value of this register bit   0 - half duplex mode   1 - full duplex mode"
        }
    }
    "CPSW_SL_MACSTATUS__bitfield" {
        "IDLE" {
            loc = "31..31"
            type = "binary"
            desc = "CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle  command)   0 - The CPGMAC_SL is not in the idle state.   1 -  The CPGMAC_SL is in the idle state."
        }
        "Reserved__1" {
            loc = "30..5"
            type = "binary"
        }
        "EXT_GIG" {
            loc = "4..4"
            type = "binary"
            desc = "External GIG - This is the value of the EXT_GIG input bit."
        }
        "EXT_FULLDUPLEX" {
            loc = "3..3"
            type = "binary"
            desc = "External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit."
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "RX_FLOW_ACT" {
            loc = "1..1"
            type = "binary"
            desc = "Receive Flow Control Active - When asserted, indicates that receive flow  control is enabled and triggered."
        }
        "TX_FLOW_ACT" {
            loc = "0..0"
            type = "binary"
            desc = "Transmit Flow Control Active - When asserted, this bit indicates that the pause  time period is being observed for a received pause frame.  No new  transmissions will begin while this bit is asserted except for the transmission  of pause frames.  Any transmission in progress when this bit is asserted will  complete."
        }
    }
    "CPSW_SL_RX_MAXLEN__bitfield" {
        "Reserved" {
            loc = "31..14"
            type = "binary"
        }
        "RX_MAXLEN" {
            loc = "13..0"
            type = "binary"
            desc = "RX Maximum Frame Length - This field determines the maximum length  of a received frame.  The reset value is 1518 (dec).  Frames with byte  counts greater than rx_maxlen are long frames.  Long frames with no  errors are oversized frames.  Long frames with CRC, code, or alignment  error are jabber frames.  The maximum value is 16,383."
        }
    }
    "CPSW_SL_RX_PAUSE__bitfield" {
        "rx_pausetimer" {
            loc = "31..16"
            type = "binary"
            desc = "RX Pause Timer Value - This field allows the contents of the receive pause  timer to be observed (and written in test mode).  The receive pause timer is  loaded with 0xFF00 when the CPGMAC_SL sends an outgoing pause frame  (with pause time of 0xFFFF).  The receive pause timer is decremented at slot  time intervals.  If the receive pause timer decrements to zero, then another  outgoing pause frame will be sent and the load/decrement process will be  repeated."
        }
        "Reserved" {
            loc = "15..0"
            type = "binary"
        }
    }
    "CPSW_SL_RX_PRI_MAP__bitfield" {
        "Reserved__1" {
            loc = "31..31"
            type = "binary"
        }
        "PRI7" {
            loc = "30..28"
            type = "binary"
            desc = "Priority 7 - A packet priority of 0x7 is mapped (changed) to this value."
        }
        "Reserved__2" {
            loc = "27..27"
            type = "binary"
        }
        "PRI6" {
            loc = "26..24"
            type = "binary"
            desc = "Priority 6 - A packet priority of 0x6 is mapped (changed) to this value."
        }
        "Reserved__3" {
            loc = "23..23"
            type = "binary"
        }
        "PRI5" {
            loc = "22..20"
            type = "binary"
            desc = "Priority 5 - A packet priority of 0x5 is mapped (changed) to this value."
        }
        "Reserved__4" {
            loc = "19..19"
            type = "binary"
        }
        "PRI4" {
            loc = "18..16"
            type = "binary"
            desc = "Priority 4 - A packet priority of 0x4 is mapped (changed) to this value."
        }
        "Reserved__5" {
            loc = "15..15"
            type = "binary"
        }
        "PRI3" {
            loc = "14..12"
            type = "binary"
            desc = "Priority 3 - A packet priority of 0x3 is mapped (changed) to this value."
        }
        "Reserved__6" {
            loc = "11..11"
            type = "binary"
        }
        "PRI2" {
            loc = "10..8"
            type = "binary"
            desc = "Priority 2 - A packet priority of 0x2 is mapped (changed) to this value."
        }
        "Reserved__7" {
            loc = "7..7"
            type = "binary"
        }
        "PRI1" {
            loc = "6..4"
            type = "binary"
            desc = "Priority 1 - A packet priority of 0x1 is mapped (changed) to this value."
        }
        "Reserved__8" {
            loc = "3..3"
            type = "binary"
        }
        "PRI0" {
            loc = "2..0"
            type = "binary"
            desc = "Priority 0 - A packet priority of 0x0 is mapped (changed) to this value."
        }
    }
    "CPSW_SL_SOFT_RESET__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset - Writing a one to this bit causes the CPGMAC_SL logic to  be reset.  After writing a one to this bit, it may be polled to determine if the  reset has occurred.  If a one is read, the reset has not yet occurred.  If a  zero is read then reset has occurred."
        }
    }
    "CPSW_SL_TX_GAP__bitfield" {
        "Reserved" {
            loc = "31..9"
            type = "binary"
        }
        "TX_GAP" {
            loc = "8..0"
            type = "binary"
            desc = "Transmit Inter-Packet Gap"
        }
    }
    "CPSW_SL_TX_PAUSE__bitfield" {
        "tx_pausetimer" {
            loc = "31..16"
            type = "binary"
            desc = "TX Pause Timer Value - This field allows the contents of the transmit pause  timer to be observed (and written in test mode).   The transmit pause timer is  loaded by a received (incoming) pause frame, and then decremented, at  slottime intervals, down to zero at which time CPGMAC_SL transmit frames  are again enabled."
        }
        "Reserved" {
            loc = "15..0"
            type = "binary"
        }
    }
    "CPSW_SS_CONTROL__bitfield" {
        "DLR_EN" {
            loc = "3..3"
            type = "binary"
            desc = "DLR enable   0 - DLR is disabled.  DLR packets will not be moved to queue priority 3         and will not be separated out onto dlr_cpdma_ch.   1 - DLR is disabled.  DLR packets be moved to destination port  transmit         queue priority 3 and will be separated out onto dlr_cpdma_ch when          packet is to egress on port 0."
        }
        "RX_VLAN_ENCAP" {
            loc = "2..2"
            type = "binary"
            desc = "Port 0  VLAN Encapsulation (egress):   0 - Port 2 receive packets (from 3G) are not VLAN          encapsulated.   1 - Port 2 receive packets (from 3G) are VLAN         encapsulated."
        }
        "VLAN_AWARE" {
            loc = "1..1"
            type = "binary"
            desc = "VLAN Aware Mode:   0 - 3G is in the VLAN unaware mode.   1 - 3G is in the VLAN aware mode."
        }
        "FIFO_LOOPBACK" {
            loc = "0..0"
            type = "binary"
            desc = "FIFO Loopback Mode    0 - Loopback is disabled   1 - FIFO Loopback mode enabled.  Each packet received           is turned around and sent out on the same port's transmit path.         Port 2 receive is fixed on channel zero.  The RXSOFOVERRUN         statistic will increment for every packet sent in FIFO loopback  mode."
        }
    }
    "CPSW_SS_DLR_LTYPE__bitfield" {
        "DLR_LTYPE" {
            loc = "15..0"
            type = "binary"
            desc = "DLR LTYPE"
        }
    }
    "CPSW_SS_FLOW_CONTROL__bitfield" {
        "P2_FLOW_EN" {
            loc = "2..2"
            type = "binary"
            desc = "Port 2 Receive flow control enable"
        }
        "P1_FLOW_EN" {
            loc = "1..1"
            type = "binary"
            desc = "Port 1 Receive flow control enable"
        }
        "P0_FLOW_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Port 0 Receive flow control enable"
        }
    }
    "CPSW_SS_GAP_THRESH__bitfield" {
        "GAP_THRESH" {
            loc = "4..0"
            type = "binary"
            desc = "CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for  triggering TX_SHORT_GAP."
        }
    }
    "CPSW_SS_ID_VER__bitfield" {
        "CPSW_3G_IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "3G Identification Value"
        }
        "CPSW_3G_RTL_VER" {
            loc = "15..11"
            type = "binary"
            desc = "3G RTL Version Value"
        }
        "CPSW_3G_MAJ_VER" {
            loc = "10..8"
            type = "binary"
            desc = "3G Major Version Value"
        }
        "CPSW_3G_MINOR_VER" {
            loc = "7..0"
            type = "binary"
            desc = "3G Minor Version Value"
        }
    }
    "CPSW_SS_PTYPE__bitfield" {
        "P2_PRI3_SHAPE_EN" {
            loc = "21..21"
            type = "binary"
            desc = "Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one  shaping queue then it must be priority 3."
        }
        "P2_PRI2_SHAPE_EN" {
            loc = "20..20"
            type = "binary"
            desc = "Port 2 Queue Priority 2 Transmit Shape Enable - If there are two  shaping queues then they must be priorities 3 and 2."
        }
        "P2_PRI1_SHAPE_EN" {
            loc = "19..19"
            type = "binary"
            desc = "Port 2 Queue Priority 1 Transmit Shape Enable - If there are three  shaping queues all three bits should be set."
        }
        "P1_PRI3_SHAPE_EN" {
            loc = "18..18"
            type = "binary"
            desc = "Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one  shaping queue then it must be priority 3."
        }
        "P1_PRI2_SHAPE_EN" {
            loc = "17..17"
            type = "binary"
            desc = "Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping  queues then they must be priorities 3 and 2."
        }
        "P1_PRI1_SHAPE_EN" {
            loc = "16..16"
            type = "binary"
            desc = "Port 1 Queue Priority 1 Transmit Shape Enable- If there are three  shaping queues all three bits should be set."
        }
        "P2_PTYPE_ESC" {
            loc = "10..10"
            type = "binary"
            desc = "Port 2 Priority Type Escalate -    0 - Port 2 priority type fixed   1 - Port 2 priority type escalate Escalate should not be used with queue shaping."
        }
        "P1_PTYPE_ESC" {
            loc = "9..9"
            type = "binary"
            desc = "Port 1 Priority Type Escalate -    0 - Port 1 priority type fixed   1 - Port 1 priority type escalate Escalate should not be used with queue shaping."
        }
        "P0_PTYPE_ESC" {
            loc = "8..8"
            type = "binary"
            desc = "Port 0 Priority Type Escalate -    0 - Port 0 priority type fixed   1 - Port 0 priority type escalate Escalate should not be used with queue shaping."
        }
        "ESC_PRI_LD_VAL" {
            loc = "4..0"
            type = "binary"
            desc = "Escalate Priority Load Value   When a port is in escalate priority, this is the number of higher priority   packets sent before the next lower priority is allowed to send a packet.     Escalate priority allows lower priority packets to be sent at a fixed rate   relative to the next higher priority."
        }
    }
    "CPSW_SS_SOFT_IDLE__bitfield" {
        "SOFT_IDLE" {
            loc = "0..0"
            type = "binary"
            desc = "Software Idle - Setting this bit causes the switch fabric to stop forwarding  packets at the next start of packet."
        }
    }
    "CPSW_SS_SOFT_RESET__bitfield" {
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset - Writing a one to this bit causes the 3G logic to be  reset.  After writing a one to this bit, it may be polled to determine if the  reset has occurred.  If a one is read, the reset has not yet occurred.  If a  zero is read then reset has occurred."
        }
    }
    "CPSW_SS_STAT_PORT_EN__bitfield" {
        "P2_STAT_EN" {
            loc = "2..2"
            type = "binary"
            desc = "Port 2 (GMII2 and Port 2 FIFO) Statistics Enable   0 - Port 2 statistics are not enabled.   1 - Port 2 statistics are enabled."
        }
        "P1_STAT_EN" {
            loc = "1..1"
            type = "binary"
            desc = "Port 1 (GMII1 and Port 1 FIFO) Statistics Enable   0 - Port 1 statistics are not enabled.   1 - Port 1 statistics are enabled."
        }
        "P0_STAT_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Port 0 Statistics Enable   0 - Port 0 statistics are not enabled   1 - Port 0 statistics are enabled. FIFO overruns (SOFOVERRUNS) are the only port 0 statistics that are  enabled to be kept."
        }
    }
    "CPSW_SS_THRU_RATE__bitfield" {
        "SL_RX_THRU_RATE" {
            loc = "15..12"
            type = "binary"
            desc = "CPGMAC_SL Switch FIFO receive through rate. This register value is the maximum throughput of the ethernet ports to the  crossbar SCR.  The default is one 8-byte word for every 3 CLK periods  maximum."
        }
        "CPDMA_THRU_RATE" {
            loc = "3..0"
            type = "binary"
            desc = "CPDMA Switch FIFO receive through rate. This register value is the maximum throughput of the CPDMA host port to  the crossbar SCR.  The default is one 8-byte word for every 3 CLK periods  maximum."
        }
    }
    "CPSW_SS_TS_LTYPE__bitfield" {
        "TS_LTYPE2" {
            loc = "21..16"
            type = "binary"
            desc = "Time Sync LTYPE2   This is an Ethertype value to match for tx and rx time sync packets."
        }
        "TS_LTYPE1" {
            loc = "15..0"
            type = "binary"
            desc = "Time Sync LTYPE1   This is an ethertype value to match for tx and rx time sync packets."
        }
    }
    "CPSW_SS_TX_START_WDS__bitfield" {
        "TX_START_WDS" {
            loc = "10..0"
            type = "binary"
            desc = "FIFO Packet Transmit (egress) Start Words. This value is the number of required packet words in the transmit FIFO  before the packet egress will begin.  This value is non-zero to preclude  underrun.  Decimal 32 is the recommended value.  It should not be  increased unnecessairly to prevent adding to the switch latency."
        }
    }
    "CPSW_SS_VLAN_LTYPE__bitfield" {
        "VLAN_LTYPE2" {
            loc = "31..16"
            type = "binary"
            desc = "Time Sync VLAN LTYPE2   This VLAN LTYPE value is used for tx and rx.  This is the inner   VLAN if both are present."
        }
        "VLAN_LTYPE1" {
            loc = "15..0"
            type = "binary"
            desc = "Time Sync VLAN LTYPE1   This VLAN LTYPE value is used for tx and rx.  This is the outer   VLAN if both are present."
        }
    }
    "CPSW_WR_C0_MISC_EN__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C0_MISC_EN" {
            loc = "4..0"
            type = "binary"
            desc = "Core 0 Misc Enable -  Each bit in this register corresponds to the  miscellaneous interrupt (evnt_pend, stat_pend, host_pend, mdio_linkint,  mdio_userint) that is enabled to generate an interrupt on C0_Misc_PULSE."
        }
    }
    "CPSW_WR_C0_MISC_STAT__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C0_MISC_STAT" {
            loc = "4..0"
            type = "binary"
            desc = "Core 0 Misc Masked Interrupt Status -  Each bit in this register corresponds  to the miscellaneous interrupt (evnt_pend, stat_pend, host_pend,  mdio_linkint, mdio_userint) that is enabled and generating an interrupt on  C0_MISC_PULSE ."
        }
    }
    "CPSW_WR_C0_RX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_RX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Receive Enable -  Each bit in this register corresponds to the bit in  the rx interrupt that is enabled to generate an interrupt on C0_RX_PULSE."
        }
    }
    "CPSW_WR_C0_RX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C0_RX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 0 Receive Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C0_RX_PULSE if pacing is  enabled for this interrupt."
        }
    }
    "CPSW_WR_C0_RX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_RX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Receive Masked Interrupt Status -  Each bit in this read only register  corresponds to the bit in the Rx interrupt that is enabled and generating an  interrupt on C0_RX_PULSE."
        }
    }
    "CPSW_WR_C0_RX_THRESH_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_RX_THRESH_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Receive Threshold Enable -  Each bit in this register corresponds to  the bit in the receive threshold interrupt that is enabled to generate an  interrupt on C0_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C0_RX_THRESH_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_RX_THRESH_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Receive Threshold Masked Interrupt Status -  Each bit in this read  only register corresponds to the bit in the receive threshold interrupt that is  enabled and generating an interrupt on C0_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C0_TX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_TX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Transmit Enable -  Each bit in this register corresponds to the bit in  the tx interrupt that is enabled to generate an interrupt on C0_TX_PULSE."
        }
    }
    "CPSW_WR_C0_TX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C0_TX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 0 Transmit Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C0_TX_PULSE if pacing is enabled  for this interrupt."
        }
    }
    "CPSW_WR_C0_TX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C0_TX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 0 Transmit Masked Interrupt Status -  Each bit in this read only  register corresponds to the bit in the Tx interrupt that is enabled and  generating an interrupt on C0_TX_PULSE ."
        }
    }
    "CPSW_WR_C1_MISC_EN__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C1_MISC_EN" {
            loc = "4..0"
            type = "binary"
            desc = "Core 1 Misc Enable -  Each bit in this register corresponds to the  miscellaneous interrupt (evnt_pend, stat_pend, host_pend, mdio_linkint,  mdio_userint) that is enabled to generate an interrupt on C1_Misc_PULSE."
        }
    }
    "CPSW_WR_C1_MISC_STAT__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C1_MISC_STAT" {
            loc = "4..0"
            type = "binary"
            desc = "Core 1 Misc Masked Interrupt Status -  Each bit in this register corresponds  to the miscellaneous interrupt (evnt_pend, stat_pend, host_pend,  mdio_linkint, mdio_userint) that is enabled and generating an interrupt on  C1_MISC_PULSE ."
        }
    }
    "CPSW_WR_C1_RX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_RX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Receive Enable -  Each bit in this register corresponds to the bit in  the rx interrupt that is enabled to generate an interrupt on C1_RX_PULSE."
        }
    }
    "CPSW_WR_C1_RX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C1_RX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 1 Receive Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C1_RX_PULSE if pacing is  enabled for this interrupt."
        }
    }
    "CPSW_WR_C1_RX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_RX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Receive Masked Interrupt Status -  Each bit in this register  corresponds to the bit in the Rx interrupt that is enabled and generating an  interrupt on C1_RX_PULSE."
        }
    }
    "CPSW_WR_C1_RX_THRESH_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_RX_THRESH_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Receive Threshold Enable -  Each bit in this register corresponds to  the bit in the receive threshold interrupt that is enabled to generate an  interrupt on C1_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C1_RX_THRESH_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_RX_THRESH_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Receive Threshold Masked Interrupt Status -  Each bit in this  register corresponds to the bit in the receive threshold interrupt that is  enabled and generating an interrupt on C1_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C1_TX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_TX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Transmit Enable -  Each bit in this register corresponds to the bit in  the tx interrupt that is enabled to generate an interrupt on C1_TX_PULSE."
        }
    }
    "CPSW_WR_C1_TX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C1_TX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 1 Transmit Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C1_TX_PULSE if pacing is enabled  for this interrupt."
        }
    }
    "CPSW_WR_C1_TX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C1_TX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 1 Transmit Masked Interrupt Status -  Each bit in this register  corresponds to the bit in the Tx interrupt that is enabled and generating an  interrupt on C1_TX_PULSE."
        }
    }
    "CPSW_WR_C2_MISC_EN__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C2_MISC_EN" {
            loc = "4..0"
            type = "binary"
            desc = "Core 2 Misc Enable -  Each bit in this register corresponds to the  miscellaneous interrupt (evnt_pend, stat_pend, host_pend, mdio_linkint,  mdio_userint) that is enabled to generate an interrupt on C2_Misc_PULSE."
        }
    }
    "CPSW_WR_C2_MISC_STAT__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "C2_MISC_STAT" {
            loc = "4..0"
            type = "binary"
            desc = "Core 2 Misc Masked Interrupt Status -  Each bit in this register corresponds  to the miscellaneous interrupt (evnt_pend, stat_pend, host_pend,  mdio_linkint, mdio_userint) that is enabled and generating an interrupt on  C2_MISC_PULSE ."
        }
    }
    "CPSW_WR_C2_RX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_RX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Receive Enable -  Each bit in this register corresponds to the bit in  the rx interrupt that is enabled to generate an interrupt on C2_RX_PULSE."
        }
    }
    "CPSW_WR_C2_RX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C2_RX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 2 Receive Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C2_RX_PULSE if pacing is  enabled for this interrupt."
        }
    }
    "CPSW_WR_C2_RX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_RX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Receive Masked Interrupt Status -  Each bit in this register  corresponds to the bit in the Rx interrupt that is enabled and generating an  interrupt on C2_RX_PULSE."
        }
    }
    "CPSW_WR_C2_RX_THRESH_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_RX_THRESH_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Receive Threshold Enable -  Each bit in this register corresponds to  the bit in the receive threshold interrupt that is enabled to generate an  interrupt on C2_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C2_RX_THRESH_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_RX_THRESH_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Receive Threshold Masked Interrupt Status -  Each bit in this  register corresponds to the bit in the receive threshold interrupt that is  enabled and generating an interrupt on C2_RX_THRESH_PULSE."
        }
    }
    "CPSW_WR_C2_TX_EN__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_TX_EN" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Transmit Enable -  Each bit in this register corresponds to the bit in  the tx interrupt that is enabled to generate an interrupt on C2_TX_PULSE."
        }
    }
    "CPSW_WR_C2_TX_IMAX__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "C2_TX_IMAX" {
            loc = "5..0"
            type = "binary"
            desc = "Core 2 Transmit Interrupts per Millisecond -  The maximum number of  interrupts per millisecond generated on C2_TX_PULSE if pacing is enabled  for this interrupt."
        }
    }
    "CPSW_WR_C2_TX_STAT__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "C2_TX_STAT" {
            loc = "7..0"
            type = "binary"
            desc = "Core 2 Transmit Masked Interrupt Status -  Each bit in this register  corresponds to the bit in the Tx interrupt that is enabled and generating an  interrupt on C2_TX_PULSE."
        }
    }
    "CPSW_WR_CONTROL__bitfield" {
        "Reserved" {
            loc = "31..4"
            type = "binary"
        }
        "MMR_STDBYMODE" {
            loc = "3..2"
            type = "CPSW_WR_CONTROL_MMR_STDBYMODE__enum"
            desc = "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."
        }
        "MMR_IDLEMODE" {
            loc = "1..0"
            type = "CPSW_WR_CONTROL_MMR_IDLEMODE__enum"
            desc = "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of IDLE state."
        }
    }
    "CPSW_WR_IDVER__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Scheme value"
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNCTION" {
            loc = "27..16"
            type = "binary"
            desc = "function value"
        }
        "RTL" {
            loc = "15..11"
            type = "binary"
            desc = "rtl version"
        }
        "MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "major version"
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "custom version"
        }
        "MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "minor version"
        }
    }
    "CPSW_WR_INT_CONTROL__bitfield" {
        "INT_TEST" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt Test - Test bit to the interrupt pacing blocks"
        }
        "Reserved__1" {
            loc = "30..22"
            type = "binary"
        }
        "INT_PACE_EN" {
            loc = "21..16"
            type = "binary"
            desc = "Interrupt Pacing Enable Bus    int_pace_en[0] - Enables C0_Rx_Pulse Pacing (0 is pacing bypass)    int_pace_en[1] - Enables C0_Tx_Pulse Pacing (0 is pacing bypass)    int_pace_en[2] - Enables C1_Rx_Pulse Pacing (0 is pacing bypass)    int_pace_en[3] - Enables C1_Tx_Pulse Pacing (0 is pacing bypass)    int_pace_en[4] - Enables C2_Rx_Pulse Pacing (0 is pacing bypass)    int_pace_en[5] - Enables C2_Tx_Pulse Pacing (0 is pacing bypass)"
        }
        "Reserved__2" {
            loc = "15..12"
            type = "binary"
        }
        "INT_PRESCALE" {
            loc = "11..0"
            type = "binary"
            desc = "Interrupt Counter Prescaler -  The number of  MAIN_CLK periods in 4us."
        }
    }
    "CPSW_WR_RGMII_CTL__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "RGMII2_FULLDUPLEX" {
            loc = "7..7"
            type = "binary"
            desc = "RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal.   0 - Half-duplex mode   1 - Fullduplex mode"
        }
        "RGMII2_SPEED" {
            loc = "6..5"
            type = "binary"
            desc = "RGMII2 Speed - This is the CPRGMI speed output signal  00 - 10Mbps mode  01 - 100Mbps mode  10 - 1000Mbps (gig) mode  11 - reserved"
        }
        "RGMII2_LINK" {
            loc = "4..4"
            type = "binary"
            desc = "RGMII2 Link Indicator - This is the CPRGMII link output signal  0 - RGMII2 link is down  1 - RGMII2 link is up"
        }
        "RGMII1_FULLDUPLEX" {
            loc = "3..3"
            type = "binary"
            desc = "RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal.   0 - Half-duplex mode   1 - Fullduplex mode"
        }
        "RGMII1_SPEED" {
            loc = "2..1"
            type = "binary"
            desc = "RGMII1 Speed - This is the CPRGMII speed output signal  00 - 10Mbps mode  01 - 100Mbps mode  10 - 1000Mbps (gig) mode  11 - reserved"
        }
        "RGMII1_LINK" {
            loc = "0..0"
            type = "binary"
            desc = "RGMII1 Link Indicator - This is the CPRGMII link output signal  0 - RGMII1 link is down"
        }
    }
    "CPSW_WR_SOFT_RESET__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset - Writing a one to this bit causes the CPGMACSS_R logic  to be reset (INT, REGS, CPPI).  Software reset occurs on the clock  following the register bit write."
        }
    }
    "CPSW__EMCONTROL__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "SOFT" {
            loc = "1..1"
            type = "binary"
            desc = "Emulation Soft Bit"
        }
        "FREE" {
            loc = "0..0"
            type = "binary"
            desc = "Emulation Free Bit"
        }
    }
    "CPTS_CONTROL__bitfield" {
        "Reserved__1" {
            loc = "31..12"
            type = "binary"
        }
        "HW4_TS_PUSH_EN" {
            loc = "11..11"
            type = "binary"
            desc = "Hardware push 4 enable"
        }
        "HW3_TS_PUSH_EN" {
            loc = "10..10"
            type = "binary"
            desc = "Hardware push 3 enable"
        }
        "HW2_TS_PUSH_EN" {
            loc = "9..9"
            type = "binary"
            desc = "Hardware push 2 enable"
        }
        "HW1_TS_PUSH_EN" {
            loc = "8..8"
            type = "binary"
            desc = "Hardware push 1 enable"
        }
        "Reserved__2" {
            loc = "7..2"
            type = "binary"
        }
        "INT_TEST" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt Test - When set, this bit allows the raw interrupt to be written to  facilitate interrupt test."
        }
        "CPTS_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Time Sync Enable - When disabled (cleared to zero), the RCLK domain is  held in reset.   0 - Time Sync Disabled   1 - Time Sync Enabled"
        }
    }
    "CPTS_EVENT_HIGH__bitfield" {
        "Reserved" {
            loc = "31..29"
            type = "binary"
        }
        "PORT_NUMBER" {
            loc = "28..24"
            type = "binary"
            desc = "Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)."
        }
        "EVENT_TYPE" {
            loc = "23..20"
            type = "binary"
            desc = "Time Sync Event Type   0000 - Time Stamp Push Event   0001 - Time Stamp Rollover Event   0010 - Time Stamp Half Rollover Event   0011 - Hardware Time Stamp Push Event   0100 - Ethernet Receive Event   0101 - Ethernet Transmit Event"
        }
        "MESSAGE_TYPE" {
            loc = "19..16"
            type = "binary"
            desc = "Message type - The message type value that was contained in an  ethernet transmit or receive time sync packet.  This field is valid only for  ethernet transmit or receive events."
        }
        "SEQUENCE_ID" {
            loc = "15..0"
            type = "binary"
            desc = "Sequence ID - The 16-bit sequence id is the value that was contained in  an ethernet transmit or receivetime sync packet.  This field is valid only for ethernet transmit or receive events."
        }
    }
    "CPTS_EVENT_LOW__bitfield" {
        "TIME_STAMP" {
            loc = "31..0"
            type = "binary"
            desc = "Time Stamp - The timestamp is valid for transmit, receive, and time  stamp push event types.  The timestamp value is not valid for counter  roll event types."
        }
    }
    "CPTS_EVENT_POP__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "EVENT_POP" {
            loc = "0..0"
            type = "binary"
            desc = "Event Pop - When a logic high is written to this bit an event is popped  off the event FIFO.  The event FIFO pop occurs as part of the interrupt  process after the event has been read in the Event_Low and  Event_High registers.  Popping an event discards the event and causes  the next event, if any, to be moved to the top of the FIFO ready to be  read by software on interrupt."
        }
    }
    "CPTS_IDVER__bitfield" {
        "TX_IDENT" {
            loc = "31..16"
            type = "binary"
            desc = "TX Identification Value"
        }
        "RTL_VER" {
            loc = "15..11"
            type = "binary"
            desc = "RTL Version Value"
        }
        "MAJOR_VER" {
            loc = "10..8"
            type = "binary"
            desc = "Major Version Value"
        }
        "MINOR_VER" {
            loc = "7..0"
            type = "binary"
            desc = "Minor Version Value"
        }
    }
    "CPTS_INTSTAT_MASKED__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TS_PEND" {
            loc = "0..0"
            type = "binary"
            desc = "TS_PEND masked interrupt read (after enable)."
        }
    }
    "CPTS_INTSTAT_RAW__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TS_PEND_RAW" {
            loc = "0..0"
            type = "binary"
            desc = "TS_PEND_RAW int read (before enable).  Writable when int_test = 1 A one in this bit indicates that there is one or more events in the event FIFO."
        }
    }
    "CPTS_INT_ENABLE__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TS_PEND_EN" {
            loc = "0..0"
            type = "binary"
            desc = "TS_PEND masked interrupt enable."
        }
    }
    "CPTS_TS_LOAD_EN__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TS_LOAD_EN" {
            loc = "0..0"
            type = "binary"
            desc = "Time Stamp Load - Writing a one to this bit enables the time stamp  value to be written via the ts_load_val[31:0] register.  This feature is  included for test purposes.  This bit is write only."
        }
    }
    "CPTS_TS_LOAD_VAL__bitfield" {
        "TS_LOAD_VAL" {
            loc = "31..0"
            type = "binary"
            desc = "Time Stamp Load Value - Writing the ts_load_en bit causes the value  contained in this register to be written into the time stamp.  The time  stamp value is read by initiating a time stamp push event, not by  reading this register.  When reading this register, the value read is not  the time stamp, but is the value that was last written to this register."
        }
    }
    "CPTS_TS_PUSH__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TS_PUSH" {
            loc = "0..0"
            type = "binary"
            desc = "Time stamp event push - When a logic high is written to this bit a time  stamp event is pushed onto the event FIFO.  The time stamp value is  the time of the write of this register, not the time of the event read.  The  time stamp value can then be read on interrupt via the event registers.   Software should not push a second time stamp event onto the event  FIFO until the first time stamp value has been read from the event FIFO  (there should be only one time stamp event in the event FIFO at any  given time).  This bit is write only and always reads zero."
        }
    }
    "DAYS_REG__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "DAY1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit of days, Range is 0 to 3"
        }
        "DAY0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of days, Range is 0 to 9"
        }
    }
    "DDR_PHY_CTRL_1__bitfield" {
        "Reserved__1" {
            loc = "31..21"
            type = "binary"
        }
        "reg_phy_enable_dynamic_pwrdn" {
            loc = "20..20"
            type = "binary"
            desc = "0 = Power down PHY data macros. 1 = Enable power to PHY data macros."
        }
        "Reserved__2" {
            loc = "19..16"
            type = "binary"
        }
        "reg_phy_rst_n" {
            loc = "15..15"
            type = "binary"
            desc = "Writing a 1 to this bit will hold the PHY macros in reset. Writing a 0 will bring PHY macros out of reset."
        }
        "Reserved__3" {
            loc = "14..14"
            type = "binary"
        }
        "reg_phy_idle_local_odt" {
            loc = "13..12"
            type = "binary"
            desc = "Value to drive on the 2-bit local_odt PHY outputs when reg_phy_dynamic_pwrdn_enable is asserted and a read is not in progress and reg_phy_dynamic_pwrdn_enable. Typically this is the value required to disable termination  (00) to save power when idle."
        }
        "reg_phy_wr_local_odt" {
            loc = "11..10"
            type = "binary"
            desc = "This bit controls the value assigned to the reg_phy_wr_local_odt input on the data macros. Always set to 00."
        }
        "reg_phy_rd_local_odt" {
            loc = "9..8"
            type = "binary"
            desc = "Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. 00 = ODT off. 01 = Full thevenin load. 10 = ODT off. 11 = Half thevenin load."
        }
        "Reserved__4" {
            loc = "7..5"
            type = "binary"
        }
        "reg_read_latency" {
            loc = "4..0"
            type = "binary"
            desc = "This field defines the latency for read data from DDR SDRAM in number of DDR clock cycles. The value applied should be equal to the required value minus one. The maximum read latency supported by the DDR PHY is equal to CAS latency plus 7 clock cycles. The minimum read latency must be equal to CAS latency plus 2 clock cycle."
        }
    }
    "DMAEMU__bitfield" {
        "SOFT" {
            loc = "1..1"
            type = "binary"
            desc = "Control for emulation pause request 1 = Does not force emu_pause_req low 0 = Forces emu_pause_req low"
        }
        "FREE" {
            loc = "0..0"
            type = "binary"
            desc = "Enable for emulation suspend CPPI DMA Emulation Control Register"
        }
    }
    "DMAREVID__bitfield" {
        "MODID" {
            loc = "29..16"
            type = "binary"
            desc = "Module ID field"
        }
        "REVRTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision. Will vary depending on release."
        }
        "REVMAJ" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision."
        }
        "REVMIN" {
            loc = "7..0"
            type = "binary"
            desc = "Minor revision. CPPI DMA Revision Register"
        }
    }
    "DMA_SCHED_CTRL__bitfield" {
        "ENABLE" {
            loc = "31..31"
            type = "binary"
            desc = "This is the enable bit for the scheduler and is encoded as  follows: 0 = scheduler is disabled and will no longer fetch entries  from the scheduler table or pass credits to the DMA  controller 1 = scheduler is enabled This bit should only be set after the table has been  initialized."
        }
        "LAST_ENTRY" {
            loc = "7..0"
            type = "binary"
            desc = "This field indicates the last valid entry in the scheduler  table.  There are 64 words in the table and there are 4  entries in each word.  The table can be programmed with  any integer number of entries from 1 to 256.  The  corresponding encoding for this field is as follows: 0 = 1 entry 1 = 2 entries ... 254 = 255 entries 255 = 256 entries CPPI DMA Scheduler Control Registers"
        }
    }
    "DMTIMER1_1MS_TCAR1__bitfield" {
        "CAPTURE_VALUE1" {
            loc = "31..0"
            type = "binary"
            desc = "The value of first captured counter register"
        }
    }
    "DMTIMER1_1MS_TCAR2__bitfield" {
        "CAPTURE_VALUE2" {
            loc = "31..0"
            type = "binary"
            desc = "The value of second captured counter register"
        }
    }
    "DMTIMER1_1MS_TCLR__bitfield" {
        "Reserved" {
            loc = "31..15"
            type = "binary"
        }
        "GPO_CFG" {
            loc = "14..14"
            type = "DMTIMER1_1MS_TCLR_GPO_CFG__enum"
        }
        "CAPT_MODE" {
            loc = "13..13"
            type = "DMTIMER1_1MS_TCLR_CAPT_MODE__enum"
            desc = "Capture mode select bit (first/second)"
        }
        "PT" {
            loc = "12..12"
            type = "DMTIMER1_1MS_TCLR_PT__enum"
            desc = "Pulse or Toggle select bit"
        }
        "TRG" {
            loc = "11..10"
            type = "DMTIMER1_1MS_TCLR_TRG__enum"
            desc = "Trigger Output Mode"
        }
        "TCM" {
            loc = "9..8"
            type = "DMTIMER1_1MS_TCLR_TCM__enum"
            desc = "Transition Capture Mode"
        }
        "SCPWM" {
            loc = "7..7"
            type = "DMTIMER1_1MS_TCLR_SCPWM__enum"
            desc = "Pulse Width Modulation output pin default value"
        }
        "CE" {
            loc = "6..6"
            type = "DMTIMER1_1MS_TCLR_CE__enum"
            desc = "Compare enable"
        }
        "PRE" {
            loc = "5..5"
            type = "DMTIMER1_1MS_TCLR_PRE__enum"
            desc = "Prescaler enable"
        }
        "PTV" {
            loc = "4..2"
            type = "DMTIMER1_1MS_TCLR_PTV__enum"
            desc = "Trigger Output Mode"
        }
        "AR" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TCLR_AR__enum"
            desc = "Auto-reload mode"
        }
        "ST" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TCLR_ST__enum"
            desc = "Start/Stop timer control"
        }
    }
    "DMTIMER1_1MS_TCRR__bitfield" {
        "TIMER_COUNTER" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the timer counter register"
        }
    }
    "DMTIMER1_1MS_TCVR__bitfield" {
        "COUNTER_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of CVR counter."
        }
    }
    "DMTIMER1_1MS_TIDR__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "TID_REV" {
            loc = "7..0"
            type = "binary"
            desc = "IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1"
        }
    }
    "DMTIMER1_1MS_TIER__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_IT_ENA" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TIER_TCAR_IT_ENA__enum"
            desc = "Enable capture interrupt"
        }
        "OVF_IT_ENA" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TIER_OVF_IT_ENA__enum"
            desc = "Enable overflow interrupt"
        }
        "MAT_IT_ENA" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TIER_MAT_IT_ENA__enum"
            desc = "Enable match interrupt"
        }
    }
    "DMTIMER1_1MS_TIOCP_CFG__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "ClockActivity" {
            loc = "9..8"
            type = "DMTIMER1_1MS_TIOCP_CFG_ClockActivity__enum"
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "EmuFree" {
            loc = "5..5"
            type = "DMTIMER1_1MS_TIOCP_CFG_EmuFree__enum"
            desc = "Emulation mode"
        }
        "IdleMode" {
            loc = "4..3"
            type = "DMTIMER1_1MS_TIOCP_CFG_IdleMode__enum"
            desc = "Power Management, req/ack control"
        }
        "EnaWakeup" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TIOCP_CFG_EnaWakeup__enum"
            desc = "Wake-up feature global control"
        }
        "SoftReset" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TIOCP_CFG_SoftReset__enum"
            desc = "Software reset. This bit is automatically reset by the hardware. During reads, it always return 0"
        }
        "AutoIdle" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TIOCP_CFG_AutoIdle__enum"
            desc = "Internal OCP clock gating strategy"
        }
    }
    "DMTIMER1_1MS_TISR__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_IT_FLAG" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TISR_TCAR_IT_FLAG__enum"
            desc = "indicates when an external pulse transition of the correct polarity is detected on the external pin PIEVENTCAPT"
        }
        "OVF_IT_FLAG" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TISR_OVF_IT_FLAG__enum"
            desc = "TCRR overflow"
        }
        "MAT_IT_FLAG" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TISR_MAT_IT_FLAG__enum"
            desc = "the compare result of TCRR and TMAR"
        }
    }
    "DMTIMER1_1MS_TISTAT__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "ResetDone" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TISTAT_ResetDone__enum"
            desc = "Internal reset monitoring"
        }
    }
    "DMTIMER1_1MS_TLDR__bitfield" {
        "LOAD_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the timer load register"
        }
    }
    "DMTIMER1_1MS_TMAR__bitfield" {
        "COMPARE_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the match register"
        }
    }
    "DMTIMER1_1MS_TNIR__bitfield" {
        "NEGATIVE_INV_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the negative increment."
        }
    }
    "DMTIMER1_1MS_TOCR__bitfield" {
        "Reserved" {
            loc = "31..24"
            type = "binary"
        }
        "OVF_COUNTER_VALUE" {
            loc = "23..0"
            type = "binary"
            desc = "The number of overflow events."
        }
    }
    "DMTIMER1_1MS_TOWR__bitfield" {
        "Reserved" {
            loc = "31..24"
            type = "binary"
        }
        "OVF_WRAPPING_VALUE" {
            loc = "23..0"
            type = "binary"
            desc = "The number of masked interrupts."
        }
    }
    "DMTIMER1_1MS_TPIR__bitfield" {
        "POSITIVE_INC_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the positive increment."
        }
    }
    "DMTIMER1_1MS_TSICR__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "POSTED" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TSICR_POSTED__enum"
            desc = "posted mode active/inactive"
        }
        "SFT" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TSICR_SFT__enum"
            desc = "This bit reset all the functional part of the module"
        }
        "Reserved__2" {
            loc = "0..0"
            type = "binary"
        }
    }
    "DMTIMER1_1MS_TTGR__bitfield" {
        "TTGR_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "The value of the trigger register                                       During reads, it always returns \"0xFFFFFFFF\""
        }
    }
    "DMTIMER1_1MS_TWER__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_WUP_ENA" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TWER_TCAR_WUP_ENA__enum"
            desc = "Enable capture wake-up"
        }
        "OVF_WUP_ENA" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TWER_OVF_WUP_ENA__enum"
            desc = "Enable overflow wake-up"
        }
        "MAT_WUP_ENA" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TWER_MAT_WUP_ENA__enum"
            desc = "Enable match wake-up"
        }
    }
    "DMTIMER1_1MS_TWPS__bitfield" {
        "Reserved" {
            loc = "31..10"
            type = "binary"
        }
        "W_PEND_TOWR" {
            loc = "9..9"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TOWR__enum"
            desc = "Write pending for register TOWR"
        }
        "W_PEND_TOCR" {
            loc = "8..8"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TOCR__enum"
            desc = "Write pending for register TOCR"
        }
        "W_PEND_TCVR" {
            loc = "7..7"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TCVR__enum"
            desc = "Write pending for register TCVR"
        }
        "W_PEND_TNIR" {
            loc = "6..6"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TNIR__enum"
            desc = "Write pending for register TNIR"
        }
        "W_PEND_TPIR" {
            loc = "5..5"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TPIR__enum"
            desc = "Write pending for register TPIR"
        }
        "W_PEND_TMAR" {
            loc = "4..4"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TMAR__enum"
            desc = "Write pending for register TMAR"
        }
        "W_PEND_TTGR" {
            loc = "3..3"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TTGR__enum"
            desc = "Write pending for register TTGR"
        }
        "W_PEND_TLDR" {
            loc = "2..2"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TLDR__enum"
            desc = "Write pending for register TLDR"
        }
        "W_PEND_TCRR" {
            loc = "1..1"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TCRR__enum"
            desc = "Write pending for register TCRR"
        }
        "W_PEND_TCLR" {
            loc = "0..0"
            type = "DMTIMER1_1MS_TWPS_W_PEND_TCLR__enum"
            desc = "Write pending for register TCLR"
        }
    }
    "DMTIMER_IRQENABLE___bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_EN_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "IRQ enable for Compare"
        }
        "OVF_EN_FLAG" {
            loc = "1..1"
            type = "binary"
            desc = "IRQ enable for Overflow"
        }
        "MAT_EN_FLAG" {
            loc = "0..0"
            type = "binary"
            desc = "IRQ enable for Match"
        }
    }
    "DMTIMER_IRQSTATUS__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_IT_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "IRQ status for Capture"
        }
        "OVF_IT_FLAG" {
            loc = "1..1"
            type = "binary"
            desc = "IRQ status for Overflow"
        }
        "MAT_IT_FLAG" {
            loc = "0..0"
            type = "binary"
            desc = "IRQ status for Match"
        }
    }
    "DMTIMER_IRQWAKEEN__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "TCAR_WUP_ENA" {
            loc = "2..2"
            type = "binary"
            desc = "Wakeup generation for Compare"
        }
        "OVF_WUP_ENA" {
            loc = "1..1"
            type = "binary"
            desc = "Wakeup generation for Overflow"
        }
        "MAT_WUP_ENA" {
            loc = "0..0"
            type = "binary"
            desc = "Wakeup generation for Match"
        }
    }
    "DMTIMER_TCAR__bitfield" {
        "CAPTURED_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Timer counter value captured on an external event trigger"
        }
    }
    "DMTIMER_TCLR__bitfield" {
        "Reserved" {
            loc = "31..15"
            type = "binary"
        }
        "GPO_CFG" {
            loc = "14..14"
            type = "binary"
            desc = "General purpose output this register drives directly the PORGPOCFG output pin"
        }
        "CAPT_MODE" {
            loc = "13..13"
            type = "binary"
            desc = "Capture mode."
        }
        "PT" {
            loc = "12..12"
            type = "binary"
            desc = "Pulse or toggle mode on PORTIMERPWM output pin"
        }
        "TRG" {
            loc = "11..10"
            type = "binary"
            desc = "Trigger output mode on PORTIMERPWM output pin"
        }
        "TCM" {
            loc = "9..8"
            type = "binary"
            desc = "Transition Capture Mode on PIEVENTCAPT input pin"
        }
        "SCPWM" {
            loc = "7..7"
            type = "binary"
            desc = "This bit should be set or clear while the timer is stopped or the trigger is off"
        }
        "CE" {
            loc = "6..6"
            type = "binary"
        }
        "PRE" {
            loc = "5..5"
            type = "binary"
            desc = "Prescaler enable"
        }
        "PTV" {
            loc = "4..2"
            type = "binary"
            desc = "Pre-scale clock Timer value"
        }
        "AR" {
            loc = "1..1"
            type = "binary"
        }
        "ST" {
            loc = "0..0"
            type = "binary"
            desc = "In the case of one-shot mode selected (AR = 0), this bit is automatically reset by internal logic when the counter is overflowed."
        }
    }
    "DMTIMER_TCRR__bitfield" {
        "TIMER_COUNTER" {
            loc = "31..0"
            type = "binary"
            desc = "Value of TIMER counter"
        }
    }
    "DMTIMER_TIDR__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between old scheme and current."
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Function indicates a software compatible module family."
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL Version (R)."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major Revision (X)."
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Indicates a special version for a particular device."
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor Revision (Y)."
        }
    }
    "DMTIMER_TIOCP_CFG__bitfield" {
        "Reserved" {
            loc = "31..4"
            type = "binary"
        }
        "IDLEMODE" {
            loc = "3..2"
            type = "binary"
            desc = "Power management, req/ack control"
        }
        "EMUFREE" {
            loc = "1..1"
            type = "binary"
            desc = "Emulation mode"
        }
        "SOFTRESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset."
        }
    }
    "DMTIMER_TLDR__bitfield" {
        "LOAD_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Timer counter value loaded on overflow in auto-reload mode or on TTGR write access"
        }
    }
    "DMTIMER_TMAR__bitfield" {
        "COMPARE_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Value to be compared to the timer counter"
        }
    }
    "DMTIMER_TSICR__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "POSTED" {
            loc = "2..2"
            type = "binary"
            desc = "PIFREQRATIO"
        }
        "SFT" {
            loc = "1..1"
            type = "binary"
            desc = "This bit resets all the function parts of the module. During reads it always returns 0."
        }
        "Reserved__2" {
            loc = "0..0"
            type = "binary"
        }
    }
    "DMTIMER_TTGR__bitfield" {
        "TTGR_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Writing in the TTGR register, TCRR will be loaded from TLDR and prescaler counter will be cleared. Reload will be done regardless of the AR field value of TCLR register."
        }
    }
    "DMTIMER_TWPS__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "W_PEND_TMAR" {
            loc = "4..4"
            type = "binary"
            desc = "When equal to 1, a write is pending to the TMAR register"
        }
        "W_PEND_TTGR" {
            loc = "3..3"
            type = "binary"
            desc = "When equal to 1, a write is pending to the TTGR register"
        }
        "W_PEND_TLDR" {
            loc = "2..2"
            type = "binary"
            desc = "When equal to 1, a write is pending to the TLDR register"
        }
        "W_PEND_TCRR" {
            loc = "1..1"
            type = "binary"
            desc = "When equal to 1, a write is pending to the TCRR register"
        }
        "W_PEND_TCLR" {
            loc = "0..0"
            type = "binary"
            desc = "When equal to 1, a write is pending to the TCLR register"
        }
    }
    "EMIF_MOD_ID_REV__bitfield" {
        "reg_scheme" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between old and current schemes."
        }
        "Reserved__1" {
            loc = "29..28"
            type = "binary"
        }
        "reg_module_id" {
            loc = "27..16"
            type = "binary"
            desc = "EMIF module ID."
        }
        "reg_rtl_version" {
            loc = "15..11"
            type = "binary"
            desc = "RTL Version."
        }
        "reg_major_revision" {
            loc = "10..8"
            type = "binary"
            desc = "Major Revision."
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "reg_minor_revision" {
            loc = "5..0"
            type = "binary"
            desc = "Minor Revision."
        }
    }
    "FDBSC0__bitfield" {
        "FDBQ3_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 3 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ2_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 2 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ1_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 1 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ0_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 0 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 0"
        }
    }
    "FDBSC1__bitfield" {
        "FDBQ7_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 7 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ6_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 6 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ5_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 5 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ4_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 4 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 1"
        }
    }
    "FDBSC2__bitfield" {
        "FDBQ11_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 11 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ10_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 10 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ9_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 9 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ8_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 8 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 2"
        }
    }
    "FDBSC3__bitfield" {
        "FDBQ15_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 15 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ14_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 14 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ13_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 13 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ12_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 12 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu.  Table 109 - QMGR_Free_Descriptor_Buffer_Starvation_Count Register 3"
        }
    }
    "FDBSC4__bitfield" {
        "FDBQ19_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 19 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ18_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 18 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ17_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 17 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ16_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 16 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 4"
        }
    }
    "FDBSC5__bitfield" {
        "FDBQ23_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 23 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ22_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 22 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ21_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 21 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ20_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 20 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 5"
        }
    }
    "FDBSC6__bitfield" {
        "FDBQ27_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 27 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ26_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 26 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ25_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 25 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ24_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 24 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 6"
        }
    }
    "FDBSC7__bitfield" {
        "FDBQ31_STARVE_CNT" {
            loc = "31..24"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 31 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ30_STARVE_CNT" {
            loc = "23..16"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 30 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ29_STARVE_CNT" {
            loc = "15..8"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 29 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu."
        }
        "FDBQ28_STARVE_CNT" {
            loc = "7..0"
            type = "binary"
            desc = "This field increments each time the Free  Descriptor/Buffer Queue 28 is read while it is empty via  the CPPI DMA. This field is cleared when read via the  cpu. Queue_Manager_Free_Descriptor_Buffer_Starvation_Count Register 7"
        }
    }
    "GPIO_CLEARDATAOUT__bitfield" {
        "INTLINE[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Clear Data Output Register"
        }
    }
    "GPIO_CTRL__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "GATINGRATIO" {
            loc = "2..1"
            type = "binary"
            desc = "Gating Ratio. Controls the clock gating for the event detection logic."
        }
        "DISABLEMODULE" {
            loc = "0..0"
            type = "binary"
            desc = "Module Disable"
        }
    }
    "GPIO_DATAIN__bitfield" {
        "DATAIN" {
            loc = "31..0"
            type = "binary"
            desc = "Sampled Input Data"
        }
    }
    "GPIO_DATAOUT__bitfield" {
        "DATAOUT" {
            loc = "31..0"
            type = "binary"
            desc = "Data to set on output pins"
        }
    }
    "GPIO_DEBOUNCENABLE__bitfield" {
        "DEBOUNCEENABLE[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Input Debounce Enable"
        }
    }
    "GPIO_DEBOUNCINGTIME__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "DEBOUNCETIME" {
            loc = "7..0"
            type = "binary"
            desc = "Input Debouncing Value in 31 microsecond steps. Debouncing time = (DEBOUNCETIME + 1) - 31 microseconds"
        }
    }
    "GPIO_FALLINGDETECT__bitfield" {
        "FALLINGDETECT[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Falling Edge Interrupt Enable"
        }
    }
    "GPIO_IRQSTATUS____bitfield" {
        "INTLINE[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Interrupt n enable"
        }
    }
    "GPIO_IRQSTATUS___bitfield" {
        "INTLINE[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Interrupt n status."
        }
    }
    "GPIO_IRQWAKEN___bitfield" {
        "INTLINE" {
            loc = "31..0"
            type = "binary"
            desc = "Wakeup Enable for Interrupt Line"
        }
    }
    "GPIO_LEVELDETECT0__bitfield" {
        "LEVELDETECT0[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Low Level Interrupt Enable"
        }
    }
    "GPIO_LEVELDETECT1__bitfield" {
        "LEVELDETECT1[n]" {
            loc = "31..0"
            type = "binary"
            desc = "High Level Interrupt Enable"
        }
    }
    "GPIO_OE__bitfield" {
        "OUTPUTEN[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Output Data Enable"
        }
    }
    "GPIO_REVISION__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between old Scheme and current."
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Indicates a software compatible module family."
        }
        "RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL version"
        }
        "MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major Revision"
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Indicates a special version for a particular device."
        }
        "MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor Revision"
        }
    }
    "GPIO_RISINGDETECT__bitfield" {
        "RISINGDETECT[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Rising Edge Interrupt Enable"
        }
    }
    "GPIO_SETDATAOUT__bitfield" {
        "INTLINE[n]" {
            loc = "31..0"
            type = "binary"
            desc = "Set Data Output Register"
        }
    }
    "GPIO_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..5"
            type = "binary"
        }
        "IDLEMODE" {
            loc = "4..3"
            type = "binary"
            desc = "Power Management, Req/Ack control 3 = Smart-idle."
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "SOFTRESET" {
            loc = "1..1"
            type = "binary"
            desc = "Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0."
        }
        "AUTOIDLE" {
            loc = "0..0"
            type = "binary"
            desc = "Internal interface clock gating strategy"
        }
    }
    "GPIO_SYSSTATUS__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "RESETDONE" {
            loc = "0..0"
            type = "binary"
            desc = "Reset status information."
        }
    }
    "HOURS_REG__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "PM_nAM" {
            loc = "7..7"
            type = "binary"
            desc = "Only used in PM_AM mode (otherwise 0)"
        }
        "Reserved__2" {
            loc = "6..6"
            type = "binary"
        }
        "HOUR1" {
            loc = "5..4"
            type = "binary"
            desc = "2nd digit of hours, Range is 0 to 2"
        }
        "HOUR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of hours, Range is 0 to 9"
        }
    }
    "INTC_CONTROL__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "NewFIQAgr" {
            loc = "1..1"
            type = "INTC_CONTROL_NewFIQAgr__enum"
            desc = "Reset FIQ output and enable new FIQ generation"
        }
        "NewIRQAgr" {
            loc = "0..0"
            type = "INTC_CONTROL_NewIRQAgr__enum"
            desc = "New IRQ generation"
        }
    }
    "INTC_FIQ_PRIORITY__bitfield" {
        "SpuriousFIQflag" {
            loc = "31..7"
            type = "binary"
            desc = "Spurious FIQ flag"
        }
        "FIQPriority" {
            loc = "6..0"
            type = "binary"
            desc = "Current FIQ priority"
        }
    }
    "INTC_IDLE__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "Turbo" {
            loc = "1..1"
            type = "INTC_IDLE_Turbo__enum"
            desc = "Input synchroniser clock auto-gating"
        }
        "FuncIdle" {
            loc = "0..0"
            type = "INTC_IDLE_FuncIdle__enum"
            desc = "Functional clock auto-idle mode"
        }
    }
    "INTC_ILR__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "Priority" {
            loc = "7..2"
            type = "binary"
            desc = "Interrupt priority"
        }
        "FIQnIRQ" {
            loc = "0..0"
            type = "INTC_ILR_FIQnIRQ__enum"
            desc = "Interrupt IRQ FiQ mapping"
        }
    }
    "INTC_IRQ_PRIORITY__bitfield" {
        "SpuriousIRQflag" {
            loc = "31..7"
            type = "binary"
            desc = "Spurious IRQ flag"
        }
        "IRQPriority" {
            loc = "6..0"
            type = "binary"
            desc = "Current IRQ priority"
        }
    }
    "INTC_ISR_CLEAR__bitfield" {
        "IsrClear" {
            loc = "31..0"
            type = "binary"
            desc = "Write 1 clears the sofware interrupt bits to 0, reads return 0"
        }
    }
    "INTC_ISR_SET__bitfield" {
        "IsrSet" {
            loc = "31..0"
            type = "binary"
            desc = "Reads returns the currently active software interrupts, Write 1 sets the software interrupt bits to 1"
        }
    }
    "INTC_ITR__bitfield" {
        "Itr" {
            loc = "31..0"
            type = "binary"
            desc = "Interrupt status before masking"
        }
    }
    "INTC_MIR_CLEAR__bitfield" {
        "MirClear" {
            loc = "31..0"
            type = "binary"
            desc = "Write 1 clears the mask bit to 0, reads return 0"
        }
    }
    "INTC_MIR_SET__bitfield" {
        "MirSet" {
            loc = "31..0"
            type = "binary"
            desc = "Write 1 sets the mask bit to 1, reads return 0"
        }
    }
    "INTC_MIR__bitfield" {
        "Mir" {
            loc = "31..0"
            type = "binary"
            desc = "Interrupt mask"
        }
    }
    "INTC_PENDING_FIQ__bitfield" {
        "PendingFIQ" {
            loc = "31..0"
            type = "binary"
            desc = "FIQ status after masking"
        }
    }
    "INTC_PENDING_IRQ__bitfield" {
        "PendingIRQ" {
            loc = "31..0"
            type = "binary"
            desc = "IRQ status after masking"
        }
    }
    "INTC_PROTECTION__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "Protection" {
            loc = "0..0"
            type = "INTC_PROTECTION_Protection__enum"
            desc = "Protection mode"
        }
    }
    "INTC_SIR_FIQ__bitfield" {
        "SpuriousFIQ" {
            loc = "31..7"
            type = "binary"
            desc = "Spurious FIQ flag"
        }
        "ActiveFIQ" {
            loc = "6..0"
            type = "binary"
            desc = "Active FIQ number"
        }
    }
    "INTC_SIR_IRQ__bitfield" {
        "SpuriousIRQ" {
            loc = "31..7"
            type = "binary"
            desc = "Spurious IRQ flag"
        }
        "ActiveIRQ" {
            loc = "6..0"
            type = "binary"
            desc = "Active IRQ number"
        }
    }
    "INTC_SYSCONFIG__bitfield" {
        "Reserved" {
            loc = "4..3"
            type = "binary"
        }
        "SoftReset" {
            loc = "1..1"
            type = "INTC_SYSCONFIG_SoftReset__enum"
            desc = "Software reset.  Set this bit to trigger a module reset. The bit is automatically reset by the hardware.  During reads, it always returns 0."
        }
        "Autoidle" {
            loc = "0..0"
            type = "INTC_SYSCONFIG_Autoidle__enum"
            desc = "Internal OCP clock gating strategy"
        }
    }
    "INTC_SYSSTATUS__bitfield" {
        "Reserved" {
            loc = "7..1"
            type = "binary"
        }
        "ResetDone" {
            loc = "0..0"
            type = "INTC_SYSSTATUS_ResetDone__enum"
            desc = "Internal reset monitoring"
        }
    }
    "INTC_THRESHOLD__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "PriorityThreshold" {
            loc = "7..0"
            type = "binary"
            desc = "Priority threshold (used values 0x00-0x1f or 0x00-0x3f, 0xff disables the threshold)."
        }
    }
    "IRQENABLE_CLR_SYS__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "reg_en_ta_sys" {
            loc = "1..1"
            type = "binary"
            desc = "Enable clear for system OCP interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect."
        }
        "reg_en_err_sys" {
            loc = "0..0"
            type = "binary"
            desc = "Enable clear for system OCP interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect."
        }
    }
    "IRQENABLE_SET_SYS__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "reg_en_ta_sys" {
            loc = "1..1"
            type = "binary"
            desc = "Enable set for system OCP interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect."
        }
        "reg_en_err_sys" {
            loc = "0..0"
            type = "binary"
            desc = "Enable set for system OCP interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect."
        }
    }
    "IRQSTATUS_RAW_SYS__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "reg_ta_sys" {
            loc = "1..1"
            type = "binary"
            desc = "Raw status of system OCP interrupt. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect."
        }
        "reg_err_sys" {
            loc = "0..0"
            type = "binary"
            desc = "Raw status of system OCP interrupt. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect."
        }
    }
    "IRQSTATUS_SYS__bitfield" {
        "Reserved__1" {
            loc = "31..3"
            type = "binary"
        }
        "Reserved__2" {
            loc = "2..2"
            type = "binary"
        }
        "reg_ta_sys" {
            loc = "1..1"
            type = "binary"
            desc = "Enabled status of system OCP interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect."
        }
        "reg_err_sys" {
            loc = "0..0"
            type = "binary"
            desc = "Enabled status of system OCP interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect."
        }
    }
    "KICK0R__bitfield" {
        "KICK0_" {
            loc = "31..0"
            type = "binary"
            desc = "Kick0 data"
        }
    }
    "KICK1R__bitfield" {
        "KICK1" {
            loc = "31..0"
            type = "binary"
            desc = "Kick1 data"
        }
    }
    "LCD_Controller_CLKC_ENABLE__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "dma_clk_en" {
            loc = "2..2"
            type = "binary"
            desc = "Software Clock Enable for the DMA submodule. The DMA submodule runs on the L3 Clock domain."
        }
        "lidd_clk_en" {
            loc = "1..1"
            type = "binary"
            desc = "Software Clock Enable for the LIDD submodule (character displays). The LIDD submodule runs on the System Clock (lcd_clk) domain"
        }
        "core_clk_en" {
            loc = "0..0"
            type = "binary"
            desc = "Software Clock Enable for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic. The Core runs on the System Clock (lcd_clk) domain."
        }
    }
    "LCD_Controller_CLKC_RESET__bitfield" {
        "Reserved" {
            loc = "31..4"
            type = "binary"
        }
        "main_rst" {
            loc = "3..3"
            type = "binary"
            desc = "Software Reset for the entire LCD module. 1 = Reset Enable 0 = Reset Disable"
        }
        "dma_rst" {
            loc = "2..2"
            type = "binary"
            desc = "Software Reset for the DMA submodule. 1 = Reset Enable 0 = Reset Disable"
        }
        "lidd_rst" {
            loc = "1..1"
            type = "binary"
            desc = "Software Reset for the LIDD submodule (character displays). 1 = Reset Enable 0 = Reset Disable"
        }
        "core_rst" {
            loc = "0..0"
            type = "binary"
            desc = "Software Reset for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic. 1 = Reset Enable 0 = Reset Disable"
        }
    }
    "LCD_Controller_CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..16"
            type = "binary"
        }
        "clkdiv" {
            loc = "15..8"
            type = "binary"
            desc = "Clock divisor. Value (from 0-255) used to specify the frequency of the pixel clock (in Raster Mode) or MCLK in (LIDD mode) based on the lcd_clk frequency. Pixel clock frequency can range from lcd_clk/2 to lcd_clk/255 (clkdiv=0 or clkdiv=1 are N/A). MCLK can vary from lcd_clk to lcd_clk/255 (clkdiv=0 or clkdiv=1 sets MCLK=lcd_clk)."
        }
        "Reserved__2" {
            loc = "7..2"
            type = "binary"
        }
        "auto_uflow_restart" {
            loc = "1..1"
            type = "binary"
            desc = "0 = On an underflow, the software has to restart the module 1 = On an underflow, the hardware will restart on the next frame"
        }
        "modesel" {
            loc = "0..0"
            type = "binary"
            desc = "LCD Mode select. 0 = LCD Controller in LIDD Mode 1 = LCD Controller in Raster Mode"
        }
    }
    "LCD_Controller_IRQENABLE_CLEAR__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "eof1_en_clr" {
            loc = "9..9"
            type = "binary"
            desc = "DMA End-of-Frame 1 Interrupt Enable Clear Read indicates enabled status. 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "eof0_en_clr" {
            loc = "8..8"
            type = "binary"
            desc = "DMA End-of-Frame 0 Interrupt Enable Clear Read indicates enabled status 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__2" {
            loc = "7..7"
            type = "binary"
        }
        "pl_en_clr" {
            loc = "6..6"
            type = "binary"
            desc = "DMA Palette Loaded Interrupt Enable Clear Read indicates enabled status. 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "fuf_en_clr" {
            loc = "5..5"
            type = "binary"
            desc = "DMA FIFO Underflow Interrupt Enable Clear LCD dithering logic not supplying data to FIFO at a sufficient rate, FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO. Read indicates enabled status. 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__3" {
            loc = "4..4"
            type = "binary"
        }
        "acb_en_clr" {
            loc = "3..3"
            type = "binary"
            desc = "For Passive Matrix Panels Only AC Bias Count Interrupt Enable Clear AC bias transition counter has decremented to zero, indicating that the lcd_ac_o line has transitioned the number of times which is specified by the acbi control bit-field. The counter is reloaded with the value in acbi but it is disabled until the user clears ABC. Read indicates enabled status. 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "sync_en_clr" {
            loc = "2..2"
            type = "binary"
            desc = "Frame Synchronization Lost Interrupt Enable Clear Read indicates enabled status 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__4" {
            loc = "1..1"
            type = "binary"
        }
        "done_en_clr" {
            loc = "0..0"
            type = "binary"
            desc = "Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Interrupt Enable Clear. Read indicates enabled status. 0 = disabled 1 = enabled Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
    }
    "LCD_Controller_IRQENABLE_SET__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "eof1_en_set" {
            loc = "9..9"
            type = "binary"
            desc = "DMA End-of-Frame 1 Interrupt Enable Set Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "eof0_en_set" {
            loc = "8..8"
            type = "binary"
            desc = "DMA End-of-Frame 0 Interrupt Enable Set Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "Reserved__2" {
            loc = "7..7"
            type = "binary"
        }
        "pl_en_set" {
            loc = "6..6"
            type = "binary"
            desc = "DMA Palette Loaded Interrupt Enable Set Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "fuf_en_set" {
            loc = "5..5"
            type = "binary"
            desc = "DMA FIFO Underflow Interrupt Enable Set LCD dithering logic not supplying data to FIFO at a sufficient rate, FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO. Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "Reserved__3" {
            loc = "4..4"
            type = "binary"
        }
        "acb_en_set" {
            loc = "3..3"
            type = "binary"
            desc = "For Passive Matrix Panels Only AC Bias Count Interrupt Enable Set AC bias transition counter has decremented to zero, indicating that the lcd_ac_o line has transitioned the number of times which is specified by the acbi control bit-field. The counter is reloaded with the value in acbi but it is disabled until the user clears ABC. Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "sync_en_set" {
            loc = "2..2"
            type = "binary"
            desc = "Frame Synchronization Lost Interrupt Enable Set Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable. Writing 0 has no effect."
        }
        "Reserved__4" {
            loc = "1..1"
            type = "binary"
        }
        "done_en_set" {
            loc = "0..0"
            type = "binary"
            desc = "Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Interrupt Enable Set Read indicates enabled (mask) status 0 = disabled 1 = enabled Writing 1 will set interrupt enable."
        }
    }
    "LCD_Controller_IRQSTATUS_RAW__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "eof1_raw_set" {
            loc = "9..9"
            type = "binary"
            desc = "DMA End-of-Frame 1 Raw Interrupt Status and Set Read indicates raw status 0 = Inactive 1 = Active Writing 1 will set status. Writing 0 has no effect."
        }
        "eof0_raw_set" {
            loc = "8..8"
            type = "binary"
            desc = "DMA End-of-Frame 0 Raw Interrupt Status and Set Read indicates raw status 0 = inactive 1 = active Writing 1 will set status. Writing 0 has no effect."
        }
        "Reserved__2" {
            loc = "7..7"
            type = "binary"
        }
        "pl_raw_set" {
            loc = "6..6"
            type = "binary"
            desc = "DMA Palette Loaded Raw Interrupt Status and Set Read indicates raw status 0 = inactive 1 = active Writing 1 will set status. Writing 0 has no effect."
        }
        "fuf_raw_set" {
            loc = "5..5"
            type = "binary"
            desc = "DMA FIFO Underflow Raw Interrupt Status and Set LCD dithering logic not supplying data to FIFO at a sufficient rate, FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO. Read indicates raw status 0 = Inactive 1 = Active Writing 1 will set status. Writing 0 has no effect."
        }
        "Reserved__3" {
            loc = "4..4"
            type = "binary"
        }
        "acb_raw_set" {
            loc = "3..3"
            type = "binary"
            desc = "For Passive Matrix Panels Only AC Bias Count Raw Interrupt Status and Set AC bias transition counter has decremented to zero, indicating that the lcd_ac_o line has transitioned the number of times which is specified by the acbi control bit-field. The counter is reloaded with the value in acbi but it is disabled until the user clears ABC. Read indicates raw status 0 = inactive 1 = active Writing 1 will set status. Writing 0 has no effect."
        }
        "sync_raw_set" {
            loc = "2..2"
            type = "binary"
            desc = "Frame Synchronization Lost Raw Interrupt Status and Set Read indicates raw status 0 = inactive 1 = active Writing 1 will set status. Writing 0 has no effect."
        }
        "Reserved__4" {
            loc = "1..1"
            type = "binary"
        }
        "done_raw_set" {
            loc = "0..0"
            type = "binary"
            desc = "Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Raw Interrupt Status and Set Read indicates raw status 0 = inactive 1 = active Writing 1 will set status. Writing 0 has no effect."
        }
    }
    "LCD_Controller_IRQSTATUS__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "eof1_en_clr" {
            loc = "9..9"
            type = "binary"
            desc = "DMA End-of-Frame 1 Enabled Interrupt and Clear Read indicates enabled (masked) status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "eof0_en_clr" {
            loc = "8..8"
            type = "binary"
            desc = "DMA End-of-Frame 0 Enabled Interrupt and Clear Read indicates enabled (masked) status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__2" {
            loc = "7..7"
            type = "binary"
        }
        "pl_en_clr" {
            loc = "6..6"
            type = "binary"
            desc = "DMA Palette Loaded Enabled Interrupt and Clear Read indicates enabled (masked) status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "fuf_en_clr" {
            loc = "5..5"
            type = "binary"
            desc = "DMA FIFO Underflow Enabled Interrupt and Clear LCD dithering logic not supplying data to FIFO at a sufficient rate, FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO. Read indicates enabled (masked) status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__3" {
            loc = "4..4"
            type = "binary"
        }
        "acb_en_clr" {
            loc = "3..3"
            type = "binary"
            desc = "For Passive Matrix Panels Only AC Bias Count Enabled Interrupt and Clear AC bias transition counter has decremented to zero, indicating that the lcd_ac_o line has transitioned the number of times which is specified by the acbi control bit-field. The counter is reloaded with the value in acbi but it is disabled until the user clears ABC. Read indicates enabled (masked) status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "sync_en_clr" {
            loc = "2..2"
            type = "binary"
            desc = "Frame Synchronization Lost Enabled Interrupt and Clear Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
        "Reserved__4" {
            loc = "1..1"
            type = "binary"
        }
        "done_en_clr" {
            loc = "0..0"
            type = "binary"
            desc = "Raster or LIDD Frame Done (shared, depends on whether Raster or LIDD mode enabled) Enabled Interrupt and Clear Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt enable. Writing 0 has no effect."
        }
    }
    "LCD_Controller_LCDDMA_CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "dma_master_prio" {
            loc = "18..16"
            type = "binary"
            desc = "Priority for the L3 OCP Master Bus"
        }
        "Reserved__2" {
            loc = "15..11"
            type = "binary"
        }
        "th_fifo_ready" {
            loc = "10..8"
            type = "binary"
            desc = "DMA FIFO threshold. The DMA FIFO becomes ready when the number of words specified by this register from the frame buffer have been loaded. 000 = 8 001 = 16 010 = 32 011 = 64 100 = 128 101 = 256 110 = 512 111 = reserved"
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "burst_size" {
            loc = "6..4"
            type = "binary"
            desc = "Burst Size setting for DMA transfers (all DMA transfers are 32 bits wide): 000 = burst size of 1 001 = burst size of 2 010 = burst size of 4 011 = burst size of 8 100 = burst size of 16 101 = N/A 110 = N/A 111 = N/A burst_size cannot be changed once the DMA is enabled in LIDD or Raster modes. In this case, the DMA must be disabled and the Done Interrupt must occur before the value in this register can be changed."
        }
        "byte_swap" {
            loc = "3..3"
            type = "binary"
            desc = "This bit controls the bytelane ordering of the data on the output of the DMA module. It works in conjunction with the big-endian bit. See the big-endian description for configuration guidelines."
        }
        "Reserved__4" {
            loc = "2..2"
            type = "binary"
        }
        "bigendian" {
            loc = "1..1"
            type = "binary"
            desc = "Big Endian Enable. Use this bit when the processor is operating in Big Endian mode AND writes to the frame buffer(s) are less than 32 bits wide. Only in this scenario do we need to change the byte alignment for data coming into the FIFO from the frame buffer(s). 0 = Big Endian data reordering disabled 1 = Big Endian data reordering enabled"
        }
        "frame_mode" {
            loc = "0..0"
            type = "binary"
            desc = "Frame Mode 0 = one frame buffer (FB0 only) used 1 = two frame buffers used DMA ping-pongs between FB0 and FB1 in this mode"
        }
    }
    "LCD_Controller_LCDDMA_FB0_BASE__bitfield" {
        "fb0_base" {
            loc = "31..2"
            type = "binary"
            desc = "Frame Buffer 0 Base Address pointer"
        }
        "Reserved" {
            loc = "1..0"
            type = "binary"
        }
    }
    "LCD_Controller_LCDDMA_FB0_CEILING__bitfield" {
        "fb0_ceil" {
            loc = "31..2"
            type = "binary"
            desc = "Frame Buffer 0 Ceiling Address pointer"
        }
        "Reserved" {
            loc = "1..0"
            type = "binary"
        }
    }
    "LCD_Controller_LCDDMA_FB1_BASE__bitfield" {
        "fb1_base" {
            loc = "31..2"
            type = "binary"
            desc = "Frame Buffer 1 Base Address pointer"
        }
        "Reserved" {
            loc = "1..0"
            type = "binary"
        }
    }
    "LCD_Controller_LCDDMA_FB1_CEILING__bitfield" {
        "fb1_ceil" {
            loc = "31..2"
            type = "binary"
            desc = "Frame Buffer 1 Ceiling Address pointer"
        }
        "Reserved" {
            loc = "1..0"
            type = "binary"
        }
    }
    "LCD_Controller_LIDD_CS0_CONF__bitfield" {
        "w_su" {
            loc = "31..27"
            type = "binary"
            desc = "Write Strobe Set-Up cycles. When performing a write access, this field defines the number of memclk cycles that Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 0 have to be ready before the Write Strobe is asserted. The minimum value is 0x0."
        }
        "w_strobe" {
            loc = "26..21"
            type = "binary"
            desc = "Write Strobe Duration cycles. Field value defines the number of memclk cycles for which the Write Strobe is held active when performing a write access. The minimum value is 0x1."
        }
        "w_hold" {
            loc = "20..17"
            type = "binary"
            desc = "Write Strobe Hold cycles. Field value defines the number of memclk cycles for which Data Bus/Pas Output Enable, ALE, the Direction bit, and Chip Select 0 are held after the Write Strobe is de-asserted when performing write access. The minimum value is 0x1."
        }
        "r_su" {
            loc = "16..12"
            type = "binary"
            desc = "Read Strobe Set-Up cycles. When performing a read access, this field defines the number of memclk cycles that Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 0 have to be ready before the Read Strobe is asserted."
        }
        "r_strobe" {
            loc = "11..6"
            type = "binary"
            desc = "Read Strobe Duration cycles. Field value defines the number of memclk cycles for which the Read Strobe is held active when performing a read access. The minimum value is 0x1."
        }
        "r_hold" {
            loc = "5..2"
            type = "binary"
            desc = "Read Strobe Hold cycles. Field value defines the number of memclk cycles for which Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 0 are held after the Read Strobe is deasserted when performing a read access. The minimum value is 0x1."
        }
        "ta" {
            loc = "1..0"
            type = "binary"
            desc = "Field value defines the number of memclk (ta+1) cycles between the end of one CS0 device access and the start of another CS0 device access unless the two accesses are both Reads. In this case, this delay is not incurred. The minimum value is 0x0."
        }
    }
    "LCD_Controller_LIDD_CS1_CONF__bitfield" {
        "w_su" {
            loc = "31..27"
            type = "binary"
            desc = "Write Strobe Set-Up cycles. When performing a write access, this field defines the number of memclk cycles that Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 1 have to be ready before the Write Strobe is asserted. The minimum value is 0x0."
        }
        "w_strobe" {
            loc = "26..21"
            type = "binary"
            desc = "Write Strobe Duration cycles. Field value defines the number of memclk cycles for which the Write Strobe is held active when performing a write access. The minimum value is 0x1."
        }
        "w_hold" {
            loc = "20..17"
            type = "binary"
            desc = "Write Strobe Hold cycles. Field value defines the number of memclk cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip Select 1 are held after the Write Strobe is deasserted when performing a write access. The minimum value is 0x1."
        }
        "r_su" {
            loc = "16..12"
            type = "binary"
            desc = "Read Strobe Set-Up cycles. When performing a read access, this field defines the number of memclk cycles that Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 1 have to be ready before the Read Strobe is asserted. The minimum value is 0x0."
        }
        "r_strobe" {
            loc = "11..6"
            type = "binary"
            desc = "Read Strobe Duration cycles. Field value defines the number of memclk cycles for which the Read Strobe is held active when performing a read access. The minimum value is 0x1."
        }
        "r_hold" {
            loc = "5..2"
            type = "binary"
            desc = "Read Strobe Hold cycles. Field value defines the number of memclk cycles for which Data Bus/Pad Output Enable, , the Direction bit, and Chip Select 1 are held after the Read Strobe is deasserted when performing a read access. The minimum value is 0x1."
        }
        "ta" {
            loc = "1..0"
            type = "binary"
            desc = "Field value defines the number of memclk (ta+1) cycles between the end of one CS1 device access and the start of another CS1 device access unless the two accesses are both Reads. In this case, this delay is not incurred. The minimum value is 0x0."
        }
    }
    "LCD_Controller_LIDD_CS_ADDR__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "adr_indx" {
            loc = "15..0"
            type = "binary"
            desc = "The LCD Controller supports a shared Address/Data output bus. A write to this register would initiate a bus write transaction. A read from this register would initiate a bus read transaction. CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode (cfg_lidd_dma_en = 1). If the LIDD is being used as a generic bus interface, writing to this register can store adr_indx to an external transparent latch holding a 16-bit address. If the LIDD is being used to interface with a character based LCD panel in configuration mode, reading and writing to this register can be used to access the command instruction area of the panel."
        }
    }
    "LCD_Controller_LIDD_CS_DATA__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "data" {
            loc = "15..0"
            type = "binary"
            desc = "The LCD Controller supports a shared Address/Data output bus. A write to this register would initiate a bus write transaction. A read from this register would initiate a bus read transaction. CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode (cfg_lidd_dma_en = 1). If the LIDD is being used as a generic bus interface, writing to this register can store adr_indx to an external transparent latch holding a 16-bit address. If the LIDD is being used to interface with a character based LCD panel in configuration mode, reading and writing to this register can be used to access the command instruction area of the panel."
        }
    }
    "LCD_Controller_LIDD_CTRL__bitfield" {
        "Reserved" {
            loc = "31..10"
            type = "binary"
        }
        "dma_cs0_cs1" {
            loc = "9..9"
            type = "binary"
            desc = "CS0/CS1 Select for LIDD DMA writes. 0 = DMA writes to LIDD CS0 1 = DMA writes for LIDD CS1"
        }
        "lidd_dma_en" {
            loc = "8..8"
            type = "binary"
            desc = "LIDD DMA Enable 0 = Deactivate DMA control of LIDD interface. DMA control is released upon completion of transfer of the current frame of data (LIDD Frame Done) after this bit is cleared. The MPU has direct read/write access to the panel in this mode. 1 = Activate DMA to drive LIDD interface to support streaming data to smart panels. The MPU cannot access the panel directly in this mode."
        }
        "cs1_e1_pol" {
            loc = "7..7"
            type = "binary"
            desc = "Chip Select 1/Enable 1 (Secondary) Polarity Control 0 = Do Not Invert Chip Select 1/Enable 1. Chip Select 1 is active low by default. Enable 1 is active high by default. 1 = Invert Chip Select 1/Enable 1."
        }
        "cs0_e0_pol" {
            loc = "6..6"
            type = "binary"
            desc = "Chip Select 0/Enable 0 (Secondary) Polarity Control. 0 = Do Not Invert Chip Select 0/Enable 0. Chip Select 0 is active low by default. Enable 0 is active high by default. 1 = Invert Chip Select 0/Enable 0."
        }
        "ws_dir_pol" {
            loc = "5..5"
            type = "binary"
            desc = "Write Strobe/Direction Polarity Control 0 = Do Not Invert Write Strobe/Direction. Write Strobe/Direction is active low/write low by default. 1 = Invert Write Strobe/Direction"
        }
        "rs_en_pol" {
            loc = "4..4"
            type = "binary"
            desc = "Read Strobe/Direction Polarity Control. 0 = Do Not Invert Read Strobe/Direction. Read Strobe/Direction is active low/write low by default. 1 = Invert Read Strobe/Direction"
        }
        "alepol" {
            loc = "3..3"
            type = "binary"
            desc = "Address Latch Enable (ALE) Polarity Control 0 = Do Not Invert ALE. ALE is active low by default. 1 = Invert"
        }
        "lidd_mode_sel" {
            loc = "2..0"
            type = "binary"
            desc = "LIDD Mode Select. Selects type of LCD display interface for the LIDD to drive: 000b = Sync MPU68 001b = Async MPU68 010b = Sync MPU80 011b = Async MPU80 100b = Hitachi (Async) 101b = N/A 110b = N/A 111b = N/A"
        }
    }
    "LCD_Controller_PID__bitfield" {
        "scheme" {
            loc = "31..30"
            type = "binary"
            desc = "The scheme of the register used. This field indicates the 3.5 Method."
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "func" {
            loc = "27..16"
            type = "binary"
            desc = "The function of the module being used."
        }
        "rtl" {
            loc = "15..11"
            type = "binary"
            desc = "The Release number for this IP."
        }
        "major" {
            loc = "10..8"
            type = "binary"
            desc = "Major Release Number"
        }
        "custom" {
            loc = "7..6"
            type = "binary"
            desc = "Custom IP"
        }
        "minor" {
            loc = "5..0"
            type = "binary"
            desc = "Minor Release Number"
        }
    }
    "LCD_Controller_RASTER_CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..27"
            type = "binary"
        }
        "tft24unpacked" {
            loc = "26..26"
            type = "binary"
            desc = "24 bit Mode Packing Only used when cfg_tft24=1 and cfg_lcdtft=1 0: 24-bit pixels are packed into 32 bit boundaries, which means 4 pixels are saved in every three words Word0: pix1[7:0], pix0[23:0] Word1: pix2[15:0], pix1[23:8] Word2: pix3[23:0], pix2[23:16] 1: 24-bit pixels are stored unpacked in with the uppermost byte unused Word0: Unused[7:0], pix0[23:0] Word1: Unused[7:0], pix1[23:0] Word2: Unused[7:0], pix2[23:0] Word3: Unused[7:0], pix3[23:0]"
        }
        "tft24" {
            loc = "25..25"
            type = "binary"
            desc = "24 bit mode 0 = off 1 = on (24-bit data in active mode) The format of the framebuffer data depends on cfg_tft24unpacked."
        }
        "stn565" {
            loc = "24..24"
            type = "binary"
            desc = "Passive Matrix Mode only (cfg_lcdtft='0') and 16 bpp raw data framebuffers (bpp = ?00?. If the bpp field in the framebuffer palette header is ?00?(12/16/24 bpp source), then the DDR contains raw data and the palette lookup is bypassed. Only for this case, this bit selects whether the framebuffer format is 16 bpp 565 or 12 bpp. The Grayscaler can only take 12 bits per pixel. The framebuffer data is 16 bits per pixel 565 when stn565 is set to `1' and only the 4 most significant bits of each color component are sent to the Grayscaler input. 0: Framebuffer is 12 bpp packed in bits [11:0] 1: Framebuffer is 16 bpp 565"
        }
        "tftmap" {
            loc = "23..23"
            type = "binary"
            desc = "TFT Mode Alternate Signal Mapping for Palettized framebuffer. Must be `0' for all 12/16/24 bpp raw data formats. Can only be `1' for 1/2/4/8 bpp Palette Lookup data. Valid only in Active Matrix mode when cfg_lcdtft='1'. 0 = 4 bits per component output data for 1, 2, 4, and 8 bpp modes will be right aligned on lcd_pins (11:0) 1 = 4 bits per component output data for 1, 2, 4, and 8 bpp will be converted to 5,6,5, format and use pins (15:0) R3 R2 R1 R0 R3 G3 G2 G1 G0 G3 G2 B3 B2 B1 B0 B3"
        }
        "nibmode" {
            loc = "22..22"
            type = "binary"
            desc = "Nibble Mode This bit is used to determine palette indexing and is used in conjunction with cfg_rdorder. 0: Nibble mode is disabled 1: Nibble mode is enabled"
        }
        "palmode" {
            loc = "21..20"
            type = "binary"
            desc = "Palette Loading Mode 00: Palette and data loading, reset value 01: Palette loading only 10: Data loading only For Raw Data (12/16/24 bpp) framebuffers, no palette lookup is employed. Thus, these framebuffers should use the data-only loading mode."
        }
        "reqdly" {
            loc = "19..12"
            type = "binary"
            desc = "Palette Loading Delay When loading the Palette from DDR, palette data is burst into the internal Palette SRAM from the Async FIFO. 1-, 2-, and 4-bit per pixel framebuffer encodings use a fixed 16-word entry palette residing above the video data. The 8 bit per pixel framebuffer encoding uses a 256-word entry palette residing above the video data. Likewise, 12, 16, and 24 bit per pixel framebuffer encodings also define a 256-word entry palette even though these encodings will not do a full bit-depth palette lookup. However, the 256-word palette entry must still be read from DDR as a framebuffer is fetched. Bursting in 256 words in sequential lcd_clk cycles may cause the Async FIFO to underflow depending on the SOC DDR burst bandwidth. This 8-bit reqdly parameter pauses reading of the Palette data from the Async FIFO between each burst of 16 words. The delay is in terms of lcd_clk (system clock) cycles. Value (0-255) used to specify the number of system clock cycles that should be paused between bursts of 16 word reads from the Async FIFO while loading the Palette SRAM. Programming reqdly=00h disables this pause when loading the palette table."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "nono8b" {
            loc = "9..9"
            type = "binary"
            desc = "Mono 8 bit 0: lcd_pixel_o\\[3:0\\] is used to output four pixel values to the panel each pixel clock transition 1: lcd_pixel_o\\[7:0\\] is used to output eight pixel values to the panel each pixel clock transition. This bit is ignored in all other modes."
        }
        "rdorder" {
            loc = "8..8"
            type = "binary"
            desc = "Raster Data Order Select 0: The frame buffer parsing for Palette Data lookup is from Bit 0 to bit 31 of the input word from the DMA output. 1: The fame buffer parsing for Palette Data lookup is from Bit 31 to Bit 0 of the input word from the DMA output. This bit has no effect on raw data framebuffers (12/16/24 bpp). This bit is used to determine palette indexing and is used in conjunction with cfg_nibmode."
        }
        "lcdtft" {
            loc = "7..7"
            type = "binary"
            desc = "LCD 0: Passive or display operation enabled, dither logic is enabled 1: Active or display operation enabled, external palette and DAC required, dither logic bypassed, pin timing changes to support continuous pixel clock, output enable, vsync, and hsync."
        }
        "Reserved__3" {
            loc = "6..2"
            type = "binary"
        }
        "lcdbw" {
            loc = "1..1"
            type = "binary"
            desc = "Only Applies for Passive Matrix Panels LCD Monochrome 0: Color operation enabled 1: Monochrome operation enabled"
        }
        "lcden" {
            loc = "0..0"
            type = "binary"
            desc = "LCD Controller Enable 0: LCD controller disabled 1: LCD controller enabled"
        }
    }
    "LCD_Controller_RASTER_SUBPANEL2__bitfield" {
        "Reserved" {
            loc = "31..9"
            type = "binary"
        }
        "lppt_b10" {
            loc = "8..8"
            type = "binary"
            desc = "Lines Per Panel Threshold Bit 10 This register is Bit 10 of the lppt field in RASTER_SUBPANEL."
        }
        "dpdmsb" {
            loc = "7..0"
            type = "binary"
            desc = "Default Pixel Data MSB [23:16] DPD defines the default value of the pixel data sent to the panel for the lines until LPPT is reached or after passing the LPPT"
        }
    }
    "LCD_Controller_RASTER_SUBPANEL__bitfield" {
        "spen" {
            loc = "31..31"
            type = "binary"
            desc = "Sub Panel Enable 0 = function disabled 1 = sub-panel function mode enabled"
        }
        "Reserved__1" {
            loc = "30..30"
            type = "binary"
        }
        "hols" {
            loc = "29..29"
            type = "binary"
            desc = "High or Low Signal This field indicates the position of the sub-panel based on the LPPT value. 0 = Default Pixel Data lines are at the top of the screen and the active video lines are at the bottom of the screen. 1 = Active video lines are at the top of the screen and Default Pixel Data lines are at the bottom of the screen."
        }
        "Reserved__2" {
            loc = "28..26"
            type = "binary"
        }
        "lppt" {
            loc = "25..16"
            type = "binary"
            desc = "Line Per Panel Threshold Encoded value (programmed value range of {0:2047} represents an actual range of {1:2048}) used to specify the number of lines on the bottom part of the panel. Bit10 of this field is in RASTER_SUBPANEL2. Hols determines whether Default Pixel Data is on the top (hols=''0') or on the bottom (hols='1'). Lppt defines the number of lines on the bottom part of the output."
        }
        "dpdlsb" {
            loc = "15..0"
            type = "binary"
            desc = "Default Pixel Data LSB[15:0] DPD defines the default value of the pixel data sent to the panel for the lines until LPPT is reach or after passing LPPT"
        }
    }
    "LCD_Controller_RASTER_TIMING_0__bitfield" {
        "hbp" {
            loc = "31..24"
            type = "binary"
            desc = "Horizontal Back Porch Lowbits Bits 7:0 of the horizontal back porch field. Encoded value (from 1-1024) used to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (programmed value plus 1). Note that pixel clock is held in its inactive state during the beginning of the line wait period in passive display mode, and is permitted to transition in active display mode."
        }
        "hfp" {
            loc = "23..16"
            type = "binary"
            desc = "Horizontal Front Porch Lowbits Encoded value (from 1-1024) used to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (programmed value plus 1). Note that pixel clock is held in its inactive state during the end of line wait period in passive display mode, and is permitted to transition in active display mode."
        }
        "hsw" {
            loc = "15..10"
            type = "binary"
            desc = "Horizontal Sync Pulse Width Lowbits Bits 5:0 of the horizontal sync pulse width field. Encoded value (from 1-1024) used to specify the number of pixel clock periods to pulse the line clock at the end of each line (programmed value plus 1). Note that pixel clock is held in its inactive state during the generation of line clock in passive display mode, and is permitted to transition in active display mode"
        }
        "ppllsb" {
            loc = "9..4"
            type = "binary"
            desc = "Pixels-per-line LSB[9:4] Encoded LSB value (from 1-1024) used to specify the number of pixels contained within each line on the LCD display (programmed to value minus one). PPL = 11'b{pplmsb, ppllsb, 4'b1111} + 1 ex: pplmsb=1'b1, pppllsb=6'0001000 PPL = 11'b{1, 000100, 1111}+ 1 = 1104d (decimal) pixels per line. In other words, PPL = 16*({pplmsb, ppllsb}+1)."
        }
        "pplmsb" {
            loc = "3..3"
            type = "binary"
            desc = "Pixels-per-line MSB[10] Needed in order to support up to 2048 ppl"
        }
        "Reserved" {
            loc = "2..0"
            type = "binary"
        }
    }
    "LCD_Controller_RASTER_TIMING_1__bitfield" {
        "vbp" {
            loc = "31..24"
            type = "binary"
            desc = "Vertical Back Porch Value (from 0-255) use to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display. Note that line clock transitions during the insertion of the extra line clock periods."
        }
        "vfp" {
            loc = "23..16"
            type = "binary"
            desc = "Vertical Front Porch Value (from 0-255) used to specify the number of line clock periods to add to the end of each frame. Note that the line clock transitions during the insertion of the extra line clock periods."
        }
        "vsw" {
            loc = "15..10"
            type = "binary"
            desc = "Vertical Sync Width Pulse In active mode (lcdtft=1), encoded value (from 1-64) used to specify the number of line clock periods to set the lcd_fp pin active at the end of each frame after the (vfp) period elapses. The number of clock cycles is programmed value plus one. The frame clock is used as the VSYNC signal in active mode. In passive mode (lcdtft=0), encoded value (from 1-64) used to specify the number of extra line clock periods to insert after the vertical front porch (vfp) period has elapsed. Note that the width of lcd_fp is not affected by vsw in passive mode and line clock transitions during the insertion of the extra line clock periods (programmed value plus one)."
        }
        "lpp" {
            loc = "9..0"
            type = "binary"
            desc = "Lines Per Panel Encoded value (programmed value range of {0:2047} represents an actual range of {1:2048}) used to specify the number of lines per panel. It represents the total number of lines on the LCD (programmed value plus one). Bit 10 of this field is in RASTER_TIMING_2."
        }
    }
    "LCD_Controller_RASTER_TIMING_2__bitfield" {
        "Reserved__1" {
            loc = "31..31"
            type = "binary"
        }
        "hsw_highbits" {
            loc = "30..27"
            type = "binary"
            desc = "Bits 9:6 of the horizontal sync width field"
        }
        "lpp_b10" {
            loc = "26..26"
            type = "binary"
            desc = "Lines Per Panel Bit 10 Bit 10 of the lpp field in RASTER_TIMING_1"
        }
        "phsvs_on_off" {
            loc = "25..25"
            type = "binary"
            desc = "Hsync/Vsync Pixel Clock Control On/Off 0 = lcd_lp and lcd_fp are driven on opposite edges of pixel clock than the lcd_pixel_o 1 = lcd_lp and lcd_fp are driven according to bit 24 Note that this bit MUST be set to `0' for Passive Matrix displays. The edge timing is fixed."
        }
        "phsvs_rf" {
            loc = "24..24"
            type = "binary"
            desc = "Program HSYNC/VSYNC Rise or Fall 0: lcd_lp and lcd_fp are driven on the rising edge of pixel clock (bit 25 must be set to 1). 1: lcd_lp and lcd_fp are driven on the falling edge of pixel clock (bit 25 must be set to 1)."
        }
        "ieo" {
            loc = "23..23"
            type = "binary"
            desc = "Invert Output Enable 0 = lcd_ac pin is active high in active display mode 1 = lcd_ac pin is active low in active display mode Active display mode: data driven out of the LCD's data lines on programmed pixel clock edge where AC-bias is active. Note that ieo is ignored in passive display mode."
        }
        "ipc" {
            loc = "22..22"
            type = "binary"
            desc = "Invert Pixel Clock 0 = Data is driven on the LCD's data lines on the rising edge of lcd_cp 1 = Data is driven on the LCD's data lines in the falling edge of lcd_cp For Active Matrix output (cfg_lcdtft='1'), the Output Pixel Clock is a free running clock in that it transitions in horizontal blanking (including horizontal front porch, horizontal back porch) areas and all vertical blanking times. For Passive Matrix output (cfg_lcdtft='0'), the Output Pixel Clock on occurs when an output data value is written. It is in a return-to-zero state when cfg_ipc='0' and a return-to-one state when cfg_ipc='1.'"
        }
        "ihs" {
            loc = "21..21"
            type = "binary"
            desc = "Invert Hsync 0: lcd_lp pin is active high and inactive low 1: lcd_lp pin is active low and inactive high Active and passive mode: horizontal sync pulse/line clock active between lines, after the end of line wait period"
        }
        "ivs" {
            loc = "20..20"
            type = "binary"
            desc = "Invert Vsync 0 = lcd_fp pin is active high and inactive low 1 = lcd_fp pin is active low and inactive high Active mode: vertical sync pulse active between frames, after end of frame wait period Passive mode: frame clock active during first line of each frame"
        }
        "acbi" {
            loc = "19..16"
            type = "binary"
            desc = "AC Bias Pins Transitions per Interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions to count before setting the line count status (lcs) bit, signaling an interrupt request. Counter frozen when lcd is set, and is restarted when lcs is cleared by software. This function is disabled when acbi = b'0000'"
        }
        "acb" {
            loc = "15..8"
            type = "binary"
            desc = "AC Bias Pin Frequency Value (from 0-255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display. acb = Number of line clocks/toggle of the lcd_ac pin."
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "hbp_highbits" {
            loc = "5..4"
            type = "binary"
            desc = "Bits 9:8 of the horizontal back porch field"
        }
        "Reserved__3" {
            loc = "3..2"
            type = "binary"
        }
        "hfp_highbits" {
            loc = "1..0"
            type = "binary"
            desc = "Bits 9:8 of the horizontal front porch field"
        }
    }
    "LCD_Controller_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "standbymode" {
            loc = "5..4"
            type = "binary"
            desc = "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state 0x0: Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x1: No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x2: Smart-standby mode: local initiator standby status depends on local conditions, i.e. the module's functional requirement from the initiator. IP module shall not generate (initiator-related) wakeup events 0x3: Smart-Standby wakeup-capable mode: local initiator standby status depends on local conditions, i.e. the module's functional requirement from the initiator. IP module may generate (master-related) wakeup events when in standby state. Mode is only relevant if the appropriate IP module \"mwakeup\" output is implemented"
        }
        "idlemode" {
            loc = "3..2"
            type = "binary"
            desc = "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0: Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1: No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2: Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module \"swakeup\" output(s) is (are) implemented"
        }
        "Reserved__2" {
            loc = "1..0"
            type = "binary"
        }
    }
    "LRAM0BASE__bitfield" {
        "REGION0_BASE" {
            loc = "31..2"
            type = "binary"
            desc = "This field stores the base address for the first region of  the linking RAM. This may be anywhere in 32-bit  address space but would be typically located in on-chip  memory."
        }
    }
    "LRAM0SIZE__bitfield" {
        "REGION0_SIZE" {
            loc = "13..0"
            type = "binary"
            desc = "This field indicates the number of entries that are  contained in the linking RAM region 0. A descriptor with  index less than region0_size value has its linking  location in region 0. A descriptor with index greater than  region0_size has its linking location in region 1. The  queue manager will add the index (left shifted by 2 bits)  to the appropriate regionX_base_addr to get the  absolute 32-bit address to the linking location for a  descriptor. Queue Manager Linking Ram Region 0 Size Register"
        }
    }
    "LRAM1BASE__bitfield" {
        "REGION1_BASE" {
            loc = "31..2"
            type = "binary"
            desc = "This field stores the base address for the second  region of the linking RAM. This may be anywhere in 32- bit address space but would be typically located in off- chip memory."
        }
    }
    "MAILBOX0_FIFOSTATUS___bitfield" {
        "MESSAGEVALUEMBM" {
            loc = "31..1"
            type = "binary"
            desc = "Message in Mailbox. The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue."
        }
        "FIFOFULLMBM" {
            loc = "0..0"
            type = "MAILBOX0_FIFOSTATUS_FIFOFULLMBM__enum"
            desc = "Full flag for Mailbox"
        }
    }
    "MAILBOX0_IRQ___bitfield" {
        "NotFullStatusUuMB7" {
            loc = "15..15"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 7"
        }
        "NewMSGStatusUuMB7" {
            loc = "14..14"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 7"
        }
        "NotFullStatusUuMB6" {
            loc = "13..13"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 6"
        }
        "NewMSGStatusUuMB6" {
            loc = "12..12"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 6"
        }
        "NotFullStatusUuMB5" {
            loc = "11..11"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 5"
        }
        "NewMSGStatusUuMB5" {
            loc = "10..10"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 5"
        }
        "NotFullStatusUuMB4" {
            loc = "9..9"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 4"
        }
        "NewMSGStatusUuMB4" {
            loc = "8..8"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 4"
        }
        "NotFullStatusUuMB3" {
            loc = "7..7"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 3"
        }
        "NewMSGStatusUuMB3" {
            loc = "6..6"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 3"
        }
        "NotFullStatusUuMB2" {
            loc = "5..5"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 2"
        }
        "NewMSGStatusUuMB2" {
            loc = "4..4"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 2"
        }
        "NotFullStatusUuMB1" {
            loc = "3..3"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 1"
        }
        "NewMSGStatusUuMB1" {
            loc = "2..2"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 1"
        }
        "NotFullStatusUuMB0" {
            loc = "1..1"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "Not Full Status bit for User u, Mailbox 0"
        }
        "NewMSGStatusUuMB0" {
            loc = "0..0"
            type = "MAILBOX0_IRQ_NStatusUuMB__enum"
            desc = "New Message Status bit for User u, Mailbox 0"
        }
    }
    "MAILBOX0_MESSAGE___bitfield" {
        "MESSAGEVALUEMBM" {
            loc = "31..0"
            type = "binary"
            desc = "Message in Mailbox. The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue."
        }
    }
    "MAILBOX0_MSGSTATUS___bitfield" {
        "NBOFMSGMBM" {
            loc = "2..0"
            type = "binary"
            desc = "Number of unread messages in Mailbox. Limited to four messages per mailbox."
        }
    }
    "MAILBOX0_REVISION__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Not defined yet"
        }
        "RES" {
            loc = "29..28"
            type = "binary"
            desc = "Reserved"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Not defined yet"
        }
        "RTL" {
            loc = "15..11"
            type = "binary"
            desc = "Not defined yet"
        }
        "MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "IP-Major Revision"
        }
        "Custom" {
            loc = "7..6"
            type = "binary"
            desc = "Not Defined Yet"
        }
        "MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "IP-Minor Revision"
        }
    }
    "MAILBOX0_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..4"
            type = "binary"
        }
        "SIdleMode" {
            loc = "3..2"
            type = "MAILBOX0_SYSCONFIG_SIdleMode__enum"
        }
        "Reserved__2" {
            loc = "1..1"
            type = "binary"
        }
        "SoftReset" {
            loc = "0..0"
            type = "MAILBOX0_SYSCONFIG_SoftReset__enum"
            desc = "Software reset. This bit is automatically reset by the hardware. During reads, it always return 0"
        }
    }
    "MINUTES_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "MIN1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of minutes, Range is 0 to 5"
        }
        "MIN0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of minutes, Range is 0 to 9"
        }
    }
    "MMC_SD_AC12__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "CNI" {
            loc = "7..7"
            type = "binary"
            desc = "Command not issue by auto CMD12 error. If this bit is set to 1, it means that pending command is not executed due to auto CMD12 error ACEB, ACCE, ACTO, or ACNE."
        }
        "Reserved__2" {
            loc = "6..5"
            type = "binary"
        }
        "ACIE" {
            loc = "4..4"
            type = "binary"
            desc = "Auto CMD12 index error. This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (SD_CMD[20] CICE bit)."
        }
        "ACEB" {
            loc = "3..3"
            type = "binary"
            desc = "Auto CMD12 end bit error. This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response."
        }
        "ACCE" {
            loc = "2..2"
            type = "binary"
            desc = "Auto CMD12 CRC error. This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in the SD_CMD[19] CCCE bit."
        }
        "ACTO" {
            loc = "1..1"
            type = "binary"
            desc = "Auto CMD12 timeout error. This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command."
        }
        "ACNE" {
            loc = "0..0"
            type = "binary"
            desc = "Auto CMD12 not executed. This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before auto CMD12 starts."
        }
    }
    "MMC_SD_ADMAES__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "LME" {
            loc = "2..2"
            type = "binary"
            desc = "ADMA Length Mismatch Error: While Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length cannot be divided by the block length."
        }
        "AES" {
            loc = "1..0"
            type = "binary"
            desc = "ADMA Error State. This field indicates the state of ADMA when an error occurred during an ADMA data transfer. This field never indicates \"10\" because ADMA never stops in this state."
        }
    }
    "MMC_SD_ADMASAH__bitfield" {
        "ADMA_A32B" {
            loc = "31..0"
            type = "binary"
            desc = "ADMA_A32B."
        }
    }
    "MMC_SD_ADMASAL__bitfield" {
        "ADMA_A32B_" {
            loc = "31..0"
            type = "binary"
            desc = "The ADMA increments this register address, which points to the next line, whenever fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register holds the valid Descriptor address depending on the ADMA state. The Host Driver shall program the Descriptor Table on a 32-bit boundary and set the 32-bit boundary address to this register. ADMA2 ignores the lower 2 bits of this register and assumes it to be 00b."
        }
    }
    "MMC_SD_ARG__bitfield" {
        "ARG" {
            loc = "31..0"
            type = "binary"
            desc = "Command argument bits [31:0] ."
        }
    }
    "MMC_SD_BLK__bitfield" {
        "NBLK" {
            loc = "31..16"
            type = "binary"
            desc = "Blocks count for current transfer. This register is enabled when Block count Enable (SD_CMD[1] BCE bit) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count."
        }
        "Reserved" {
            loc = "15..12"
            type = "binary"
        }
        "BLEN" {
            loc = "11..0"
            type = "binary"
            desc = "Transfer block size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (SD_STAT[1] TC bit set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched."
        }
    }
    "MMC_SD_CAPA__bitfield" {
        "Reserved__1" {
            loc = "31..29"
            type = "binary"
        }
        "64BIT" {
            loc = "28..28"
            type = "binary"
            desc = "64 Bit System Bus Support. Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus."
        }
        "Reserved__2" {
            loc = "27..27"
            type = "binary"
        }
        "VS18" {
            loc = "26..26"
            type = "binary"
            desc = "Voltage support 1.8 V. Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        }
        "VS30" {
            loc = "25..25"
            type = "binary"
            desc = "Voltage support 3.0V. Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        }
        "VS33" {
            loc = "24..24"
            type = "binary"
            desc = "Voltage support 3.3V. Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        }
        "SRS" {
            loc = "23..23"
            type = "binary"
            desc = "Suspend/resume support (SDIO cards only). This bit indicates whether the host controller supports Suspend/Resume functionality."
        }
        "DS" {
            loc = "22..22"
            type = "binary"
            desc = "DMA support. This bit indicates that the Host controller is able to use DMA to transfer data between system memory and the Host controller directly."
        }
        "HSS" {
            loc = "21..21"
            type = "binary"
            desc = "High-speed support. This bit indicates that the host controller supports high speed operations and can supply an up-to-52 MHz clock to the card."
        }
        "Reserved__3" {
            loc = "20..20"
            type = "binary"
        }
        "AD2S_" {
            loc = "19..19"
            type = "binary"
            desc = "This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN."
        }
        "Reserved__4" {
            loc = "18..18"
            type = "binary"
        }
        "MBL" {
            loc = "17..16"
            type = "binary"
            desc = "Maximum block length. This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. The host controller supports 512 bytes and 1024 bytes block transfers."
        }
        "Reserved__5" {
            loc = "15..14"
            type = "binary"
        }
        "BCF" {
            loc = "13..8"
            type = "binary"
            desc = "Base clock frequency for clock provided to the card. ARRAY(0x1bfe1b0)"
        }
        "TCU" {
            loc = "7..7"
            type = "binary"
            desc = "Timeout clock unit. This bit shows the unit of base clock frequency used to detect Data Timeout Error (SD_STAT[20] DTO bit)."
        }
        "Reserved__6" {
            loc = "6..6"
            type = "binary"
        }
        "TCF" {
            loc = "5..0"
            type = "binary"
            desc = "Timeout clock frequency. The timeout clock frequency is used to detect Data Timeout Error (SD_STAT[20] DTO bit)."
        }
    }
    "MMC_SD_CMD__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "INDX" {
            loc = "29..24"
            type = "binary"
            desc = "Command index binary encoded value from 0 to 63 specifying the command number send to card."
        }
        "CMD_TYPE" {
            loc = "23..22"
            type = "binary"
            desc = "Command type. This register specifies three types of special commands: Suspend, Resume and Abort. These bits shall be cleared to 0b00 for all other commands."
        }
        "DP" {
            loc = "21..21"
            type = "binary"
            desc = "Data present select. This register indicates that data is present and mmc_dat line shall be used. It must be cleared to 0 in the following conditions: Command using only mmc_cmd line. Command with no data transfer but using busy signal on mmc_dat0. Resume command."
        }
        "CICE" {
            loc = "20..20"
            type = "binary"
            desc = "Command Index check enable. This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it is reported as a command index error (SD_STAT[19] CIE bit set to1) NoteThe CICE bit cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued."
        }
        "CCCE" {
            loc = "19..19"
            type = "binary"
            desc = "Command CRC check enable. This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC error (SD_STAT[17] CCRC bit set to 1). NoteThe CCCE bit cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued."
        }
        "Reserved__2" {
            loc = "18..18"
            type = "binary"
        }
        "RSP_TYPE" {
            loc = "17..16"
            type = "binary"
            desc = "Response type. This bits defines the response type of the command."
        }
        "Reserved__3" {
            loc = "15..6"
            type = "binary"
        }
        "MSBS" {
            loc = "5..5"
            type = "binary"
            desc = "Multi/Single block select. This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be cleared to 0."
        }
        "DDIR" {
            loc = "4..4"
            type = "binary"
            desc = "Data transfer Direction. Select This bit defines either data transfer will be a read or a write."
        }
        "Reserved__4" {
            loc = "3..3"
            type = "binary"
        }
        "ACEN" {
            loc = "2..2"
            type = "binary"
            desc = "Auto CMD12 Enable (SD cards only). When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set this bit to issue commands that do not require CMD12 to stop data transfer. In particular, secure commands do not require CMD12. For CE-ATA commands (SD_CON[12] CEATA bit set to 1), auto CMD12 is useless; therefore when this bit is set the mechanism to detect command completion signal, named CCS, interrupt is activated."
        }
        "BCE" {
            loc = "1..1"
            type = "binary"
            desc = "Block Count Enable (Multiple block transfers only). This bit is used to enable the block count register (SD_BLK[31:16] NBLK bits). When Block Count is disabled (SD_CMD[1] BCE bit is cleared to 0) in Multiple block transfers (SD_CMD[5] MSBS bits is set to 1), the module can perform infinite transfer."
        }
        "DE" {
            loc = "0..0"
            type = "binary"
            desc = "DMA Enable. This bit is used to enable DMA mode for host data access."
        }
    }
    "MMC_SD_CON__bitfield" {
        "Reserved__1" {
            loc = "31..22"
            type = "binary"
        }
        "SDMA_LnE_" {
            loc = "21..21"
            type = "binary"
            desc = "Slave DMA Level/Edge Request. The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to SD_DATA register or late de-assertion, request remains active until last allowed data written into SD_DATA."
        }
        "DMA_MnS_" {
            loc = "20..20"
            type = "binary"
            desc = "DMA Master or Slave selection. When this bit is set and the controller is configured to use the DMA, Ocp master interface is used to get datas from system using ADMA2 procedure (direct access to the memory). This option is only available if generic parameter MADMA_EN is asserted to 1."
        }
        "DDR" {
            loc = "19..19"
            type = "binary"
            desc = "Dual Data Rate mode. When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of SD_SYSCTL[CLKD], it is insensitive to SD_HCTL[HSPE] setting."
        }
        "BOOT_CF0_" {
            loc = "18..18"
            type = "binary"
            desc = "Boot Status Supported. This register is set when the CMD line needs to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in SD_CMD. The line is released when this bit field is de-asserted and aborts data transfer in case of a pending transaction."
        }
        "BOOT_ACK" {
            loc = "17..17"
            type = "binary"
            desc = "Book acknowledge received. When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated."
        }
        "CLKEXTFREE" {
            loc = "16..16"
            type = "binary"
            desc = "External clock free running. This register is used to maintain card clock out of transfer transaction to enable slave module (for example to generate a synchronous interrupt on mmc_dat[1] ). The Clock will be maintain only if SD_SYSCTL[2] CEN bit is set."
        }
        "PADEN" {
            loc = "15..15"
            type = "binary"
            desc = "Control power for MMC lines. This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for mmc_dat[1] , the signal is also combine outside the module with the dedicated power control SD_CON[11] CTPL bit."
        }
        "Reserved__2" {
            loc = "14..13"
            type = "binary"
        }
        "CEATA" {
            loc = "12..12"
            type = "binary"
            desc = "CE-ATA control mode (MMC cards compliant with CE-ATA). This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is not supported."
        }
        "CTPL" {
            loc = "11..11"
            type = "binary"
            desc = "Control Power for mmc_dat[1] line (SD cards). By default, this bit is cleared to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards. When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of mmc_dat[1] outside of a transaction in order to detect asynchronous card interrupt on mmc_dat[1] line and minimize the leakage current of the buffers."
        }
        "DVAL" {
            loc = "10..9"
            type = "binary"
            desc = "Debounce filter value (all cards). This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card."
        }
        "WPP" {
            loc = "8..8"
            type = "binary"
            desc = "Write protect polarity (SD and SDIO cards only). This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the type of the connector housing that accommodates the card."
        }
        "CDP" {
            loc = "7..7"
            type = "binary"
            desc = "Card detect polarity (all cards). This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the type of the connector housing that accommodates the card."
        }
        "MIT" {
            loc = "6..6"
            type = "binary"
            desc = "MMC interrupt command (MMC cards only). This bit must be set to 1, when the next write access to the command register (SD_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response."
        }
        "DW8" {
            loc = "5..5"
            type = "binary"
            desc = "8-bit mode MMC select (MMC cards only). For SD/SDIO cards, this bit must be cleared to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification."
        }
        "MODE" {
            loc = "4..4"
            type = "binary"
            desc = "Mode select (all cards). This bit selects the functional mode."
        }
        "STR" {
            loc = "3..3"
            type = "binary"
            desc = "Stream command (MMC cards only). This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20WRITE_DAT_UNTIL_STOP)."
        }
        "HR" {
            loc = "2..2"
            type = "binary"
            desc = "Broadcast host response (MMC cards only). This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core. In order to have the host response to be generated in open drain mode, the register SD_CON[OD] must be set to 1. When SD_CON[12] CEATA bit is set to 1 and SD_ARG cleared to 0, when writing 0000 0000h into SD_CMD register, the host controller performs a 'command completion signal disable' token (i.e., mmc_cmd line held to 0 during 47 cycles followed by a 1)."
        }
        "INIT" {
            loc = "1..1"
            type = "binary"
            desc = "Send initialization stream (all cards). When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the mmc_cmd line to 1 during 80 clock cycles. The initialization sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (SD_SYSCTL[15:6] CLKD bits) should be set to ensure that 80 clock periods are greater than 1ms. Note: In this mode, there is no command sent to the card and no response is expected. A command complete interrupt will be generated once the initialization sequence is completed. SD_STAT[0] CC bit can be polled."
        }
        "OD" {
            loc = "0..0"
            type = "binary"
            desc = "Card open drain mode (MMC cards only). This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register SD_CON[2] HR bit)."
        }
    }
    "MMC_SD_CSRE__bitfield" {
        "CSRE" {
            loc = "31..0"
            type = "binary"
            desc = "Card status response error"
        }
    }
    "MMC_SD_CUR_CAPA__bitfield" {
        "Reserved" {
            loc = "31..24"
            type = "binary"
        }
        "CUR_1V8" {
            loc = "23..16"
            type = "binary"
            desc = "Maximum current for 1.8 V"
        }
        "CUR_3V0" {
            loc = "15..8"
            type = "binary"
            desc = "Maximum current for 3.0 V"
        }
        "CUR_3V3" {
            loc = "7..0"
            type = "binary"
            desc = "Maximum current for 3.3 V"
        }
    }
    "MMC_SD_DATA__bitfield" {
        "DATA" {
            loc = "31..0"
            type = "binary"
            desc = "Data register [31:0]. In functional mode (SD_CON[4] MODE bit set to the default value 0): A read access to this register is allowed only when the buffer read enable status is set to 1 (SD_PSTATE[11] BRE bit), otherwise a bad access (SD_STAT[29] BADA bit) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1 (SD_PSTATE[10] BWE bit), otherwise a bad access (SD_STAT[29] BADA bit) is signaled and the data is not written."
        }
    }
    "MMC_SD_FE__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "FE_BADA" {
            loc = "29..29"
            type = "binary"
            desc = "Force Event Bad access to data space."
        }
        "FE_CERR" {
            loc = "28..28"
            type = "binary"
            desc = "Force Event Card error"
        }
        "Reserved__2" {
            loc = "27..26"
            type = "binary"
        }
        "FE_ADMAE" {
            loc = "25..25"
            type = "binary"
            desc = "Force Event ADMA error"
        }
        "FE_ACE" {
            loc = "24..24"
            type = "binary"
            desc = "Force Event Auto CMD12 error."
        }
        "Reserved__3" {
            loc = "23..23"
            type = "binary"
        }
        "FE_DEB" {
            loc = "22..22"
            type = "binary"
            desc = "Force Event Data End Bit error."
        }
        "FE_DCRC" {
            loc = "21..21"
            type = "binary"
            desc = "Force Event Data CRC error"
        }
        "FE_DTO" {
            loc = "20..20"
            type = "binary"
            desc = "Force Event Data timeout error"
        }
        "FE_CIE" {
            loc = "19..19"
            type = "binary"
            desc = "Force Event Command index error"
        }
        "FE_CEB" {
            loc = "18..18"
            type = "binary"
            desc = "Force Event Command end bit error"
        }
        "FE_CCRC" {
            loc = "17..17"
            type = "binary"
            desc = "Force Event Comemand CRC error"
        }
        "FE_CTO" {
            loc = "16..16"
            type = "binary"
            desc = "Force Event Command Timeout error"
        }
        "Reserved__4" {
            loc = "15..8"
            type = "binary"
        }
        "FE_CNI" {
            loc = "7..7"
            type = "binary"
            desc = "Force Event Command not issue by Auto CMD12 error"
        }
        "Reserved__5" {
            loc = "6..5"
            type = "binary"
        }
        "FE_ACIE" {
            loc = "4..4"
            type = "binary"
            desc = "Force Event Auto CMD12 index error"
        }
        "FE_ACEB" {
            loc = "3..3"
            type = "binary"
            desc = "Force Event Auto CMD12 end bit error"
        }
        "FE_ACCE" {
            loc = "2..2"
            type = "binary"
            desc = "Force Event Auto CMD12 CRC error"
        }
        "FE_ACTO" {
            loc = "1..1"
            type = "binary"
            desc = "Force Event Auto CMD12 timeout error"
        }
        "FE_ACNE" {
            loc = "0..0"
            type = "binary"
            desc = "Force Event Auto CMD12 not executed."
        }
    }
    "MMC_SD_HCTL__bitfield" {
        "Reserved__1" {
            loc = "31..28"
            type = "binary"
        }
        "OBWE" {
            loc = "27..27"
            type = "binary"
            desc = "Wake-up event enable for 'out-of-band' Interrupt. This bit enables wake-up events for 'out-of-band' assertion. Wake-up is generated if the wake-up feature is enabled (SD_SYSCONFIG[2] ENAWAKEUP bit). The write to this register is ignored when SD_CON[14] OBIE bit is not set."
        }
        "REM" {
            loc = "26..26"
            type = "binary"
            desc = "Wake-up event enable on SD card removal. This bit enables wake-up events for card removal assertion. Wake-up is generated if the wake-up feature is enabled (SD_SYSCONFIG[2] ENAWAKEUP bit)."
        }
        "INS" {
            loc = "25..25"
            type = "binary"
            desc = "Wake-up event enable on SD card insertion This bit enables wake-up events for card insertion assertion. Wake-up is generated if the wake-up feature is enabled (SD_SYSCONFIG[2] ENAWAKEUP bit)."
        }
        "IWE" {
            loc = "24..24"
            type = "binary"
            desc = "Wake-up event enable on SD card interrupt. This bit enables wake-up events for card interrupt assertion. Wake-up is generated if the wake-up feature is enabled (SD_SYSCONFIG[2] ENAWAKEUP bit) and enable status bit is set (SD_IE[8] CIRQ_ENABLE bit)."
        }
        "Reserved__2" {
            loc = "23..20"
            type = "binary"
        }
        "IBG" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt block at gap. This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be cleared to 0."
        }
        "RWC" {
            loc = "18..18"
            type = "binary"
            desc = "Read wait control. The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (SD_HCTL[16] SBGR bit) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on mmc_dat line."
        }
        "CR" {
            loc = "17..17"
            type = "binary"
            desc = "Continue request. This bit is used to restart a transaction that was stopped by requesting a stop at block gap (SD_HCTL[16] SBGR bit). Set this bit to 1 restarts the transfer. The bit is automatically cleared to 0 by the host controller when transfer has restarted, that is, mmc_dat line is active (SD_PSTATE[2] DLA bit) or transferring data (SD_PSTATE[8] WTA bit). The Stop at block gap request must be disabled (SD_HCTL[16] SBGR bit =0) before setting this bit."
        }
        "SBGR" {
            loc = "16..16"
            type = "binary"
            desc = "Stop at block gap request. This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (SD_HCTL[17] CR bit) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (SD_STAT[1] TC bit set to 1), the host driver shall leave this bit set to 1.If this bit is set, the local host shall not write to the data register (SD_DATA)."
        }
        "Reserved__3" {
            loc = "15..12"
            type = "binary"
        }
        "SDVS" {
            loc = "11..9"
            type = "binary"
            desc = "SD bus voltage select (All cards). The host driver should set these bits to select the voltage level for the card according to the voltage supported by the system (SD_CAPA[26] VS18 bit, SD_CAPA[25] VS30 bit, SD_CAPA[24] VS33 bit) before starting a transfer. If MMCHS2: This field must be set to 5h. If MMCHS3: This field must be set to 5h."
        }
        "SDBP" {
            loc = "8..8"
            type = "binary"
            desc = "SD bus power. Before setting this bit, the host driver shall select the SD bus voltage (SD_HCTL[11:9] SDVS bits). If the host controller detects the No card state, this bit is automatically cleared to 0. If the module is power off, a write in the command register (SD_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage is not supported according to capability register (SD_CAPA[VS*])."
        }
        "CDSS" {
            loc = "7..7"
            type = "binary"
            desc = "Card Detect Signal Selection. This bit selects source for the card detection. When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupt being caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing."
        }
        "CDTL" {
            loc = "6..6"
            type = "binary"
            desc = "Card Detect Test Level. This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. 0 = No card 1 = Card inserted."
        }
        "Reserved__4" {
            loc = "5..5"
            type = "binary"
        }
        "DMAS" {
            loc = "4..3"
            type = "binary"
            desc = "DMA Select. One of the supported DMA modes can be selected. The host driver shall check support of DMA modes by referencing the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is cleared to 0 the bit field is read only and returned value is 0."
        }
        "HSPE" {
            loc = "2..2"
            type = "binary"
            desc = "High Speed Enable. Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is cleared to 0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock. This bit shall not be set when dual data rate mode is activated in SD_CON[DDR]."
        }
        "DTW" {
            loc = "1..1"
            type = "binary"
            desc = "Data transfer width. This bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card."
        }
        "Reserved__5" {
            loc = "0..0"
            type = "binary"
        }
    }
    "MMC_SD_IE__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "BADA_ENABLE" {
            loc = "29..29"
            type = "binary"
            desc = "Bad access to data space interrupt enable"
        }
        "CERR_ENABLE" {
            loc = "28..28"
            type = "binary"
            desc = "Card error interrupt enable"
        }
        "Reserved__2" {
            loc = "27..26"
            type = "binary"
        }
        "ADMA_ENABLE_" {
            loc = "25..25"
            type = "binary"
            desc = "ADMA error Interrupt Enable"
        }
        "ACE_ENABLE" {
            loc = "24..24"
            type = "binary"
            desc = "Auto CMD12 error interrupt enable"
        }
        "Reserved__3" {
            loc = "23..23"
            type = "binary"
        }
        "DEB_ENABLE" {
            loc = "22..22"
            type = "binary"
            desc = "Data end bit error interrupt enable"
        }
        "DCRC_ENABLE" {
            loc = "21..21"
            type = "binary"
            desc = "Data CRC error interrupt enable"
        }
        "DTO_ENABLE" {
            loc = "20..20"
            type = "binary"
            desc = "Data timeout error interrupt enable"
        }
        "CIE_ENABLE" {
            loc = "19..19"
            type = "binary"
            desc = "Command index error interrupt enable"
        }
        "CEB_ENABLE" {
            loc = "18..18"
            type = "binary"
            desc = "Command end bit error interrupt enable"
        }
        "CCRC_ENABLE" {
            loc = "17..17"
            type = "binary"
            desc = "Command CRC error interrupt enable"
        }
        "CTO_ENABLE" {
            loc = "16..16"
            type = "binary"
            desc = "Command timeout error interrupt enable"
        }
        "NULL" {
            loc = "15..15"
            type = "binary"
            desc = "Fixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored."
        }
        "Reserved__4" {
            loc = "14..11"
            type = "binary"
        }
        "BSR_ENABLE_" {
            loc = "10..10"
            type = "binary"
            desc = "Boot Status Interrupt Enable A write to this register when SD_CON[BOOT] is cleared to 0 is ignored."
        }
        "OBI_ENABLE" {
            loc = "9..9"
            type = "binary"
            desc = "Out-of-band interrupt enable A write to this register when SD_CON[14] OBIE is cleared to 0 is ignored."
        }
        "CIRQ_ENABLE" {
            loc = "8..8"
            type = "binary"
            desc = "Card interrupt enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1. This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "CREM_ENABLE_" {
            loc = "7..7"
            type = "binary"
            desc = "Card Removal interrupt Enable This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "CINS_ENABLE_" {
            loc = "6..6"
            type = "binary"
            desc = "Card Insertion interrupt Enable This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "BRR_ENABLE" {
            loc = "5..5"
            type = "binary"
            desc = "Buffer read ready interrupt enable"
        }
        "BWR_ENABLE" {
            loc = "4..4"
            type = "binary"
            desc = "Buffer write ready interrupt enable"
        }
        "DMA_ENABLE_" {
            loc = "3..3"
            type = "binary"
            desc = "DMA interrupt enable"
        }
        "BGE_ENABLE" {
            loc = "2..2"
            type = "binary"
            desc = "Block gap event interrupt enable"
        }
        "TC_ENABLE" {
            loc = "1..1"
            type = "binary"
            desc = "Transfer completed interrupt enable"
        }
        "CC_ENABLE" {
            loc = "0..0"
            type = "binary"
            desc = "Command completed interrupt enable"
        }
    }
    "MMC_SD_ISE__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "BADA_SIGEN" {
            loc = "29..29"
            type = "binary"
            desc = "Bad access to data space interrupt enable"
        }
        "CERR_SIGEN" {
            loc = "28..28"
            type = "binary"
            desc = "Card error interrupt signal status enable"
        }
        "Reserved__2" {
            loc = "27..26"
            type = "binary"
        }
        "ADMA_SIGEN_" {
            loc = "25..25"
            type = "binary"
            desc = "ADMA error signal status enable"
        }
        "ACE_SIGEN" {
            loc = "24..24"
            type = "binary"
            desc = "Auto CMD12 error signal status enable"
        }
        "Reserved__3" {
            loc = "23..23"
            type = "binary"
        }
        "DEB_SIGEN" {
            loc = "22..22"
            type = "binary"
            desc = "Data end bit error signal status enable"
        }
        "DCRC_SIGEN" {
            loc = "21..21"
            type = "binary"
            desc = "Data CRC error signal status enable"
        }
        "DTO_SIGEN" {
            loc = "20..20"
            type = "binary"
            desc = "Data timeout error signal status enable"
        }
        "CIE_SIGEN" {
            loc = "19..19"
            type = "binary"
            desc = "Command index error signal status enable"
        }
        "CEB_SIGEN" {
            loc = "18..18"
            type = "binary"
            desc = "Command end bit error signal status enable"
        }
        "CCRC_SIGEN" {
            loc = "17..17"
            type = "binary"
            desc = "Command CRC error signal status enable"
        }
        "CTO_SIGEN" {
            loc = "16..16"
            type = "binary"
            desc = "Command timeout error signal status enable"
        }
        "NULL" {
            loc = "15..15"
            type = "binary"
            desc = "Fixed to 0. The host driver shall control error interrupts using the error interrupt signal enable register. Writes to this bit are ignored."
        }
        "Reserved__4" {
            loc = "14..11"
            type = "binary"
        }
        "BSR_SIGEN_" {
            loc = "10..10"
            type = "binary"
            desc = "Boot Status signal status enable. A write to this register when SD_CON[BOOT] is cleared to 0 is ignored"
        }
        "OBI_SIGEN" {
            loc = "9..9"
            type = "binary"
            desc = "Out-of-band interrupt signal status enable. A write to this register when SD_CON[14] OBIE is cleared to 0 is ignored."
        }
        "CIRQ_SIGEN" {
            loc = "8..8"
            type = "binary"
            desc = "Card interrupt signal status enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1. This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "CREM_SIGEN_" {
            loc = "7..7"
            type = "binary"
            desc = "Card Removal signal status enable This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "CINS_SIGEN" {
            loc = "6..6"
            type = "binary"
            desc = "Card Insertion signal status enable. This bit must be set to 1 when entering in smart idle mode to enable system to identity wake-up event and to allow controller to clear internal wake-up source."
        }
        "BRR_SIGEN" {
            loc = "5..5"
            type = "binary"
            desc = "Buffer read ready signal status enable"
        }
        "BWR_SIGEN" {
            loc = "4..4"
            type = "binary"
            desc = "Buffer write ready signal status enable"
        }
        "DMA_SIGEN_" {
            loc = "3..3"
            type = "binary"
            desc = "DMA signal status enable"
        }
        "BGE_SIGEN" {
            loc = "2..2"
            type = "binary"
            desc = "Block gap event signal status enable"
        }
        "TC_SIGEN" {
            loc = "1..1"
            type = "binary"
            desc = "Transfer completed signal status enable"
        }
        "CC_SIGEN" {
            loc = "0..0"
            type = "binary"
            desc = "Command completed signal status enable"
        }
    }
    "MMC_SD_PSTATE__bitfield" {
        "Reserved__1" {
            loc = "31..25"
            type = "binary"
        }
        "CLEV" {
            loc = "24..24"
            type = "binary"
            desc = "mmc_cmd line signal level. This status is used to check the mmc_cmd line level to recover from errors, and for debugging. The value of this register after reset depends on the mmc_cmd line level at that time."
        }
        "DLEV" {
            loc = "23..20"
            type = "binary"
            desc = "mmc_dat[3:0] line signal level mmc_dat3 equal to or greater than bit 23. mmc_dat2 equal to or greater than bit 22. mmc_dat1 equal to or greater than bit 21. mmc_dat0 equal to or greater than bit 20. This status is used to check mmc_dat line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from mmc_dat0 . The value of these registers after reset depends on the mmc_dat lines level at that time."
        }
        "WP" {
            loc = "19..19"
            type = "binary"
            desc = "Write Protect. MMC/SD/SDIO1 only. SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends one the protect input pin (SDWP) level at that time."
        }
        "CDPL" {
            loc = "18..18"
            type = "binary"
            desc = "Card Detect Pin Level. MMC/SD/SDIO1 only. SDIO cards only. This bit reflects the inverse value of the card detect input pin (SDCD). Debouncing is not performed on this bit and is valid only when Card State is stable. (SD_PSTATE[17] is set to 1). This bit must be debounced by software. The value of this register after reset depends on the card detect input pin (SDCD) level at that time."
        }
        "CSS" {
            loc = "17..17"
            type = "binary"
            desc = "Card State Stable. This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (SD_PSTATE[18] CPDL). Debouncing is performed on the card detect input pin (SDCD) to detect card stability. This bit is not affected by software reset."
        }
        "CINS" {
            loc = "16..16"
            type = "binary"
            desc = "Card inserted. This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (SD_STAT[CINS]). A active to inactive transition of the card detect input pin (SDCD) will generate a card removal interrupt (SD_STAT[REM]). This bit is not affected by a software reset."
        }
        "Reserved__2" {
            loc = "15..12"
            type = "binary"
        }
        "BRE" {
            loc = "11..11"
            type = "binary"
            desc = "Buffer read enable. This bit is used for non-DMA read transfers. It indicates that a complete block specified by SD_BLK[10:0] BLEN bits has been written in the buffer and is ready to be read. It is cleared to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (SD_STAT[5] BRR bit)."
        }
        "BWE" {
            loc = "10..10"
            type = "binary"
            desc = "Buffer Write enable. This status is used for non-DMA write transfers. It indicates if space is available for write data."
        }
        "RTA" {
            loc = "9..9"
            type = "binary"
            desc = "Read transfer active. This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (SD_HCTL[17] CR bit) following a stop at block gap request. This bit is cleared to 0 when all data have been read by the local host after last block or after a stop at block gap request."
        }
        "WTA" {
            loc = "8..8"
            type = "binary"
            desc = "Write transfer active. This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (SD_HCTL[17] CR bit) following a stop at block gap request. This bit is cleared to 0 when CRC status has been received after last block or after a stop at block gap request."
        }
        "Reserved__3" {
            loc = "7..3"
            type = "binary"
        }
        "DLA" {
            loc = "2..2"
            type = "binary"
            desc = "mmc_dat line active. This status bit indicates whether one of the mmc_dat lines is in use. In the case of read transactions (card to host)This bit is set to 1 after the end bit of read command or by activating continue request SD_HCTL[17] CR bit. This bit is cleared to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card)This bit is set to 1 after the end bit of write command or by activating continue request SD_HCTL[17] CR bit. This bit is cleared to 0 on the end of busy event for the last block. The host controller must wait 8 clock cycles with line not busy to really consider not \"busy state\" or after the busy block as a result of a stop at gap request."
        }
        "DATI" {
            loc = "1..1"
            type = "binary"
            desc = "Command inhibit (mmc_dat). This status bit is generated if either mmc_dat line is active (SD_PSTATE[2] DLA bit) or Read transfer is active (SD_PSTATE[9] RTA bit) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (SD_STAT[1] TC bit)."
        }
        "CMDI" {
            loc = "0..0"
            type = "binary"
            desc = "Command inhibit(mmc_cmd). This status bit indicates that the mmc_cmd line is in use. This bit is cleared to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is cleared to 0 in either the following cases: After the end bit of the command response, excepted if there is a command conflict error (SD_STAT[17] CCRC bit or SD_STAT[18] CEB bit set to 1) or a Auto CMD12 is not executed (SD_AC12[0] ACNE bit). After the end bit of the command without response (SD_CMD[17:16] RSP_TYPE bits set to \"00\"). In case of a command data error is detected (SD_STAT[19] CTO bit set to 10, this register is not automatically cleared."
        }
    }
    "MMC_SD_PWCNT__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "PWRCNT" {
            loc = "15..0"
            type = "binary"
            desc = "Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued."
        }
    }
    "MMC_SD_REV__bitfield" {
        "VREV" {
            loc = "31..24"
            type = "binary"
            desc = "Vendor Version Number. Bits [7:4] is the major revision, bits [3:0] is the minor revision. Examples: 10h for 1.0 21h for 2.1"
        }
        "SREV" {
            loc = "23..16"
            type = "binary"
            desc = "Specification Version Number. This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version."
        }
        "Reserved" {
            loc = "15..1"
            type = "binary"
        }
        "SIS" {
            loc = "0..0"
            type = "binary"
            desc = "Slot Interrupt Status. This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (SD_SYSCTL[24] SRA), the interrupt signal shall be deasserted and this status shall read 0."
        }
    }
    "MMC_SD_RSP10__bitfield" {
        "RSP1" {
            loc = "31..16"
            type = "binary"
            desc = "Command Response [31:16]"
        }
        "RSP0" {
            loc = "15..0"
            type = "binary"
            desc = "Command Response [15:0]"
        }
    }
    "MMC_SD_RSP32__bitfield" {
        "RSP3" {
            loc = "31..16"
            type = "binary"
            desc = "Command Response [63:48]"
        }
        "RSP2" {
            loc = "15..0"
            type = "binary"
            desc = "Command Response [47:32]"
        }
    }
    "MMC_SD_RSP54__bitfield" {
        "RSP5" {
            loc = "31..16"
            type = "binary"
            desc = "Command Response [95:80]"
        }
        "RSP4" {
            loc = "15..0"
            type = "binary"
            desc = "Command Response [79:64]"
        }
    }
    "MMC_SD_RSP76__bitfield" {
        "RSP7" {
            loc = "31..16"
            type = "binary"
            desc = "Command Response [127:112]"
        }
        "RSP6" {
            loc = "15..0"
            type = "binary"
            desc = "Command Response [111:96]"
        }
    }
    "MMC_SD_SDMASA__bitfield" {
        "SDMA_SYSADDR_" {
            loc = "31..0"
            type = "binary"
            desc = "This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register."
        }
    }
    "MMC_SD_STAT__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "BADA" {
            loc = "29..29"
            type = "binary"
            desc = "Bad access to data space. This bit is set automatically to indicate a bad access to buffer when not allowed: During a read access to the data register (SD_DATA) while buffer reads are not allowed (SD_PSTATE[11] BRE bit =0). During a write access to the data register (SD_DATA) while buffer writes are not allowed (SD_PSTATE[10] BWE bit=0)."
        }
        "CERR" {
            loc = "28..28"
            type = "binary"
            desc = "Card error. This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E (error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error SD_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read SD_RSP76 register to detect error bits in the command response."
        }
        "Reserved__2" {
            loc = "27..26"
            type = "binary"
        }
        "ADMAE_" {
            loc = "25..25"
            type = "binary"
            desc = "ADMA Error. This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register. In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor."
        }
        "ACE" {
            loc = "24..24"
            type = "binary"
            desc = "Auto CMD12 error. This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1."
        }
        "Reserved__3" {
            loc = "23..23"
            type = "binary"
        }
        "DEB" {
            loc = "22..22"
            type = "binary"
            desc = "Data End Bit error. This bit is set automatically when detecting a 0 at the end bit position of read data on mmc_dat line or at the end position of the CRC status in write mode."
        }
        "DCRC" {
            loc = "21..21"
            type = "binary"
            desc = "Data CRC Error. This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position \"010\" token during a block write command."
        }
        "DTO" {
            loc = "20..20"
            type = "binary"
            desc = "Data timeout error. This bit is set automatically according to the following conditions: Busy timeout for R1b, R5b response type. Busy timeout after write CRC status. Write CRC status timeout. Read data timeout."
        }
        "CIE" {
            loc = "19..19"
            type = "binary"
            desc = "Command index error. This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable bit (SD_CMD[20] CICE)."
        }
        "CEB" {
            loc = "18..18"
            type = "binary"
            desc = "Command end bit error. This bit is set automatically when detecting a 0 at the end bit position of a command response."
        }
        "CCRC" {
            loc = "17..17"
            type = "binary"
            desc = "Command CRC error. This bit is set automatically when there is a CRC7 error in the command response depending on the enable bit (SD_CMD[19] CCCE)."
        }
        "CTO" {
            loc = "16..16"
            type = "binary"
            desc = "Command timeout error. This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles."
        }
        "ERRI" {
            loc = "15..15"
            type = "binary"
            desc = "Error interrupt. If any of the bits in the Error Interrupt Status register (SD_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored."
        }
        "Reserved__4" {
            loc = "14..11"
            type = "binary"
        }
        "BSR" {
            loc = "10..10"
            type = "binary"
            desc = "Boot Status Received Interrupt. This bit is set automatically when SD_CON[BOOT] is set 1 or 2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card."
        }
        "OBI" {
            loc = "9..9"
            type = "binary"
            desc = "Out-of-band interrupt (This interrupt is only useful for MMC card). This bit is set automatically when SD_CON[14] OBIE bit is set and an out-of-band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by SD_CON[13] OBIP bit. The out-of-band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation."
        }
        "CIRQ" {
            loc = "8..8"
            type = "binary"
            desc = "Card interrupt. This bit is only used for SD and SDIO cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wake-up). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives mmc_cmd line to zero during one cycle after data transmission end. All modes above are fully exclusive. The controller interrupt must be clear by setting SD_IE[8] CIRQ_ENABLE to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as SD_IE[8] CIRQ_ENABLE is set to 1. Writes to this bit are ignored."
        }
        "CREM" {
            loc = "7..7"
            type = "binary"
            desc = "Card Removal. This bit is set automatically when SD_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS])."
        }
        "CINS" {
            loc = "6..6"
            type = "binary"
            desc = "Card Insertion. This bit is set automatically when SD_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS])."
        }
        "BRR" {
            loc = "5..5"
            type = "binary"
            desc = "Buffer read ready. This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by the SD_BLK[10:0] BLEN bit field is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated."
        }
        "BWR" {
            loc = "4..4"
            type = "binary"
            desc = "Buffer write ready. This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by SD_BLK[10:0] BLEN. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated."
        }
        "DMA" {
            loc = "3..3"
            type = "binary"
            desc = "DMA Interrupt. This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion."
        }
        "BGE" {
            loc = "2..2"
            type = "binary"
            desc = "Block gap event. When a stop at block gap is requested (SD_HCTL[16] SBGR bit), this bit is automatically set when transaction is stopped at the block gap during a read or write operation."
        }
        "TC" {
            loc = "1..1"
            type = "binary"
            desc = "Transfer completed. This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (SD_HCTL[16] SBGR bit)."
        }
        "CC" {
            loc = "0..0"
            type = "binary"
            desc = "Command complete. This bit is set when a 1-to-0 transition occurs in the register command inhibit (SD_PSTATE[0] CMDI bit)"
        }
    }
    "MMC_SD_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..14"
            type = "binary"
        }
        "STANDBYMODE" {
            loc = "13..12"
            type = "binary"
            desc = "Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0."
        }
        "Reserved__2" {
            loc = "11..10"
            type = "binary"
        }
        "CLOCKACTIVITY" {
            loc = "9..8"
            type = "binary"
            desc = "Clocks activity during wake up mode period. Bit 8 is the Interface clock. Bit 9 is the Functional clock."
        }
        "Reserved__3" {
            loc = "7..5"
            type = "binary"
        }
        "SIDLEMODE" {
            loc = "4..3"
            type = "binary"
            desc = "Power management"
        }
        "ENAWAKEUP" {
            loc = "2..2"
            type = "binary"
            desc = "Wake-up feature control"
        }
        "SOFTRESET" {
            loc = "1..1"
            type = "binary"
            desc = "Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0."
        }
        "AUTOIDLE" {
            loc = "0..0"
            type = "binary"
            desc = "Internal Clock gating strategy"
        }
    }
    "MMC_SD_SYSCTL__bitfield" {
        "Reserved__1" {
            loc = "31..27"
            type = "binary"
        }
        "SRD" {
            loc = "26..26"
            type = "binary"
            desc = "Software reset for mmc_dat line. This bit is set to 1 for reset and released to 0 when completed. mmc_dat finite state machine in both clock domain are also reset. These registers are cleared by the SD_SYSCTL[26] SRD bit: SD_DATA. SD_PSTATEBRE, BWE, RTA, WTA, DLA and DATI. SD_HCTLSBGR and CR. SD_STATBRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized. Note: If a soft reset is issued when an interrupt is asserted, data may be lost."
        }
        "SRC" {
            loc = "25..25"
            type = "binary"
            desc = "Software reset for mmc_cmd line. This bit is set to 1 for reset and released to 0 when completed. mmc_cmd finite state machine in both clock domain are also reset. These registers are cleared by the SD_SYSCTL[25] SRC bit: SD_PSTATECMDI. SD_STATCC Interconnect and MMC command status management is reinitialized. Note: If a soft reset is issued when an interrupt is asserted, data may be lost."
        }
        "SRA" {
            loc = "24..24"
            type = "binary"
            desc = "Software reset for all. This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers."
        }
        "Reserved__2" {
            loc = "23..20"
            type = "binary"
        }
        "DTO" {
            loc = "19..16"
            type = "binary"
            desc = "Data timeout counter value and busy timeout. This value determines the interval by which mmc_dat lines timeouts are detected. The host driver needs to set this bit field based on: The maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer). The data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card. The timeout clock base frequency (SD_CAPA[5:0] TCF bits). If the card does not respond within the specified number of cycles, a data timeout error occurs (SD_STAT[20] DTO bit). The SD_SYSCTL[19,16] DTO bit field is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write."
        }
        "CLKD" {
            loc = "15..6"
            type = "binary"
            desc = "Clock frequency select. These bits define the ratio between a reference clock frequency (system dependant) and the output clock frequency on the mmc_clk pin of either the memory card (MMC, SD, or SDIO)."
        }
        "Reserved__3" {
            loc = "5..3"
            type = "binary"
        }
        "CEN" {
            loc = "2..2"
            type = "binary"
            desc = "Clock enable. This bit controls if the clock is provided to the card or not."
        }
        "ICS" {
            loc = "1..1"
            type = "binary"
            desc = "Internal clock stable (status)This bit indicates either the internal clock is stable or not."
        }
        "ICE" {
            loc = "0..0"
            type = "binary"
            desc = "Internal clock enable. This register controls the internal clock activity. In very low power state, the internal clock is stopped. NoteThe activity of the debounce clock (used for wake-up events) and the interface clock (used for reads and writes to the module register map) are not affected by this register."
        }
    }
    "MMC_SD_SYSSTATUS__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "RESETDONE" {
            loc = "0..0"
            type = "binary"
            desc = "Internal Reset Monitoring. Notethe debounce clock , the interface clock and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring."
        }
    }
    "MMC_SD_SYSTEST__bitfield" {
        "Reserved" {
            loc = "31..17"
            type = "binary"
        }
        "OBI" {
            loc = "16..16"
            type = "binary"
            desc = "Out-of-band interrupt (OBI) data value."
        }
        "SDCD" {
            loc = "15..15"
            type = "binary"
            desc = "Card detect input signal (SDCD) data value"
        }
        "SDWP" {
            loc = "14..14"
            type = "binary"
            desc = "Write protect input signal (SDWP) data value"
        }
        "WAKD" {
            loc = "13..13"
            type = "binary"
            desc = "Wake request output signal data value."
        }
        "SSB" {
            loc = "12..12"
            type = "binary"
            desc = "Set status bit. This bit must be cleared prior attempting to clear a status bit of the interrupt status register (SD_STAT)."
        }
        "D7D" {
            loc = "11..11"
            type = "binary"
            desc = "DAT7 input/output signal data value."
        }
        "D6D" {
            loc = "10..10"
            type = "binary"
            desc = "DAT6 input/output signal data value."
        }
        "D5D" {
            loc = "9..9"
            type = "binary"
            desc = "DAT5 input/output signal data value."
        }
        "D4D" {
            loc = "8..8"
            type = "binary"
            desc = "DAT4 input/output signal data value."
        }
        "D3D" {
            loc = "7..7"
            type = "binary"
            desc = "DAT3 input/output signal data value."
        }
        "D2D" {
            loc = "6..6"
            type = "binary"
            desc = "DAT2 input/output signal data value."
        }
        "D1D" {
            loc = "5..5"
            type = "binary"
            desc = "DAT1 input/output signal data value."
        }
        "D0D" {
            loc = "4..4"
            type = "binary"
            desc = "DAT0 input/output signal data value."
        }
        "DDIR" {
            loc = "3..3"
            type = "binary"
            desc = "Control of the DAT[7:0] pins direction."
        }
        "CDAT" {
            loc = "2..2"
            type = "binary"
            desc = "CMD input/output signal data value"
        }
        "CDIR" {
            loc = "1..1"
            type = "binary"
            desc = "Control of the CMD pin direction"
        }
        "MCKD" {
            loc = "0..0"
            type = "binary"
            desc = "MMC clock output signal data value"
        }
    }
    "MONTHS_REG__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "MONTH1" {
            loc = "4..4"
            type = "binary"
            desc = "2nd digit of months, Range is 0 to 1"
        }
        "MONTH0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of months, Range is 0 to 9"
        }
    }
    "PEND0__bitfield" {
        "QPEND0" {
            loc = "31..0"
            type = "binary"
            desc = "This field indicates the queue pending status for  queues[31:0]."
        }
    }
    "PEND1__bitfield" {
        "QPEND1" {
            loc = "31..0"
            type = "binary"
            desc = "This field indicates the queue pending status for  queues[63:32].  Table 118 - QMGR_Queue_Pending_1 Register 1"
        }
    }
    "PEND2__bitfield" {
        "QPEND2" {
            loc = "31..0"
            type = "binary"
            desc = "This field indicates the queue pending status for  queues[95:64]. Queue_Manager_Queue_Pending_2 Register 2"
        }
    }
    "PEND3__bitfield" {
        "QPEND3" {
            loc = "31..0"
            type = "binary"
            desc = "This field indicates the queue pending status for  queues[127:96]. Queue_Manager_Queue_Pending_3 Register 3"
        }
    }
    "PEND4__bitfield" {
        "QPEND4" {
            loc = "31..0"
            type = "binary"
            desc = "This field indicates the queue pending status for  queues[159:128]. Queue_Manager_Queue_Pending_4 Register 4"
        }
    }
    "PERF_CNT_1__bitfield" {
        "reg_counter1" {
            loc = "31..0"
            type = "binary"
            desc = "32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register."
        }
    }
    "PERF_CNT_2__bitfield" {
        "reg_counter2" {
            loc = "31..0"
            type = "binary"
            desc = "32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register."
        }
    }
    "PERF_CNT_CFG__bitfield" {
        "reg_cntr2_mconnid_en" {
            loc = "31..31"
            type = "binary"
            desc = "MConnID filter enable for Performance Counter 2 register."
        }
        "reg_cntr2_region_en" {
            loc = "30..30"
            type = "binary"
            desc = "Chip Select filter enable for Performance Counter 2 register."
        }
        "Reserved__1" {
            loc = "29..20"
            type = "binary"
        }
        "reg_cntr2_cfg" {
            loc = "19..16"
            type = "binary"
            desc = "Filter configuration for Performance Counter 2. Refer to table for details."
        }
        "reg_cntr1_mconnid_en" {
            loc = "15..15"
            type = "binary"
            desc = "MConnID filter enable for Performance Counter 1 register."
        }
        "reg_cntr1_region_en" {
            loc = "14..14"
            type = "binary"
            desc = "Chip Select filter enable for Performance Counter 1 register."
        }
        "Reserved__2" {
            loc = "13..4"
            type = "binary"
        }
        "reg_cntr1_cfg" {
            loc = "3..0"
            type = "binary"
            desc = "Filter configuration for Performance Counter 1. Refer to table for details."
        }
    }
    "PERF_CNT_SEL__bitfield" {
        "reg_mconnid2" {
            loc = "31..24"
            type = "binary"
            desc = "MConnID for Performance Counter 2 register."
        }
        "Reserved__1" {
            loc = "23..18"
            type = "binary"
        }
        "reg_region_sel2" {
            loc = "17..16"
            type = "binary"
            desc = "MAddrSpace for Performance Counter 2 register."
        }
        "reg_mconnid1" {
            loc = "15..8"
            type = "binary"
            desc = "MConnID for Performance Counter 1 register."
        }
        "Reserved__2" {
            loc = "7..2"
            type = "binary"
        }
        "reg_region_sel1" {
            loc = "1..0"
            type = "binary"
            desc = "MAddrSpace for Performance Counter 1 register."
        }
    }
    "PERF_CNT_TIM__bitfield" {
        "reg_total_time" {
            loc = "31..0"
            type = "binary"
            desc = "32-bit counter that continuously counts number for m_clk cycles elapsed after EMIF is brought out of reset."
        }
    }
    "PM_CEFUSE_PWRSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..5"
            type = "binary"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "PowerState" {
            loc = "1..0"
            type = "PM_CEFUSE_PWRSTCTRL_PowerState__enum"
            desc = "Power state control"
        }
    }
    "PM_CEFUSE_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "LastPowerStateEntered" {
            loc = "25..24"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."
        }
        "Reserved__2" {
            loc = "23..21"
            type = "binary"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__3" {
            loc = "19..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "PowerStateSt" {
            loc = "1..0"
            type = "PM_CEFUSE_PWRSTST_PowerStateSt__enum"
            desc = "Current power state status"
        }
    }
    "PM_GFX_PWRSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..19"
            type = "binary"
        }
        "GFX_MEM_ONState" {
            loc = "18..17"
            type = "PM__PWRSTCTRL_M_ONState__enum"
            desc = "GFX memory state when domain is ON."
        }
        "Reserved__2" {
            loc = "16..7"
            type = "binary"
        }
        "GFX_MEM_RETState" {
            loc = "6..6"
            type = "PM__PWRSTCTRL___RETState__enum"
        }
        "Reserved__3" {
            loc = "5..5"
            type = "binary"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "Reserved__4" {
            loc = "3..3"
            type = "binary"
        }
        "LogicRETState" {
            loc = "2..2"
            type = "PM__PWRSTCTRL_LogicRETState__enum"
            desc = "Logic state when power domain is RETENTION"
        }
        "PowerState" {
            loc = "1..0"
            type = "PM_GFX_PWRSTCTRL_PowerState__enum"
            desc = "Power state control"
        }
    }
    "PM_GFX_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..21"
            type = "binary"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__2" {
            loc = "19..6"
            type = "binary"
        }
        "GFX_MEM_StateSt" {
            loc = "5..4"
            type = "PM__PWRSTT___tate__enum"
            desc = "GFX memory state status"
        }
        "Reserved__3" {
            loc = "3..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "PowerStateSt" {
            loc = "1..0"
            type = "PM__PWRSTST_PowerStateSt__enum"
            desc = "Current Power State Status"
        }
    }
    "PM_MPU_PWRSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..25"
            type = "binary"
        }
        "mpu_ram_RETState" {
            loc = "24..24"
            type = "binary"
            desc = "Default power domain memory(ram) retention state when power domain is in retention"
        }
        "mpu_l2_RETState" {
            loc = "23..23"
            type = "binary"
            desc = "Default power domain memory(L2) retention state when power domain is in retention"
        }
        "mpu_l1_RETState" {
            loc = "22..22"
            type = "binary"
            desc = "Default power domain memory(L1) retention state when power domain is in retention"
        }
        "MPU_L2_ONState" {
            loc = "21..20"
            type = "PM__PWRSTCTRL_M_ONState__enum"
            desc = "Default power domain memory state when domain is ON."
        }
        "MPU_L1_ONState" {
            loc = "19..18"
            type = "PM__PWRSTCTRL_M_ONState__enum"
            desc = "Default power domain memory state when domain is ON."
        }
        "MPU_RAM_ONState" {
            loc = "17..16"
            type = "PM__PWRSTT___tate__enum"
            desc = "Default power domain memory state when domain is ON."
        }
        "Reserved__3" {
            loc = "15..5"
            type = "binary"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "Reserved__4" {
            loc = "3..3"
            type = "binary"
        }
        "LogicRETState" {
            loc = "2..2"
            type = "PM__PWRSTCTRL_LogicRETState__enum"
            desc = "Logic state when power domain is RETENTION"
        }
        "PowerState" {
            loc = "1..0"
            type = "PM_P_PWRSTCTRL_PowerState__enum"
            desc = "Power state control"
        }
    }
    "PM_MPU_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..21"
            type = "binary"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__2" {
            loc = "19..10"
            type = "binary"
        }
        "MPU_L2_StateSt" {
            loc = "9..8"
            type = "PM__PWRSTT___tate__enum"
            desc = "MPU L2 memory state status"
        }
        "MPU_L1_StateSt" {
            loc = "7..6"
            type = "PM__PWRSTT___tate__enum"
            desc = "MPU L1 memory state status"
        }
        "MPU_RAM_StateSt" {
            loc = "5..4"
            type = "PM__PWRSTT___tate__enum"
            desc = "MPU_RAM memory state status"
        }
        "Reserved__3" {
            loc = "3..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "PowerStateSt" {
            loc = "1..0"
            type = "PM__PWRSTST_PowerStateSt__enum"
            desc = "Current Power State Status"
        }
    }
    "PM_PER_PWRSTCTRL__bitfield" {
        "ram_mem_ONState" {
            loc = "31..30"
            type = "PM_PER_PWRSTCTRL_ram_mem_ONState__enum"
            desc = "OCMC RAM memory on state"
        }
        "PER_mem_RETState" {
            loc = "29..29"
            type = "PM__PWRSTCTRL___RETState__enum"
            desc = "Other memories in PER Domain RET state"
        }
        "Reserved__1" {
            loc = "28..28"
            type = "binary"
        }
        "ram_mem_RETState" {
            loc = "27..27"
            type = "PM__PWRSTCTRL___RETState__enum"
            desc = "OCMC RAM memory RET state"
        }
        "PER_mem_ONState" {
            loc = "26..25"
            type = "PM_PER_PWRSTCTRL__mem_ONState__enum"
            desc = "Other memories in PER Domain ON state"
        }
        "Reserved__2" {
            loc = "24..8"
            type = "binary"
        }
        "pru_icss_mem_RETState" {
            loc = "7..7"
            type = "PM__PWRSTCTRL___RETState__enum"
            desc = "PRU-ICSS memory RET state"
        }
        "pru_icss_mem_ONState" {
            loc = "6..5"
            type = "PM_PER_PWRSTCTRL__mem_ONState__enum"
            desc = "PRU-ICSS memory ON state"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "LogicRETState" {
            loc = "3..3"
            type = "PM__PWRSTCTRL_LogicRETState__enum"
            desc = "Logic state when power domain is RETENTION"
        }
        "Reserved__3" {
            loc = "2..2"
            type = "binary"
        }
        "PowerState" {
            loc = "1..0"
            type = "PM_P_PWRSTCTRL_PowerState__enum"
            desc = "PER domain power state control"
        }
    }
    "PM_PER_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..25"
            type = "binary"
        }
        "pru_icss_mem_statest" {
            loc = "24..23"
            type = "PM__PWRSTT___tate__enum"
            desc = "PRU-ICSS memory state status"
        }
        "ram_mem_statest" {
            loc = "22..21"
            type = "PM__PWRSTT___tate__enum"
            desc = "OCMC RAM memory state status"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__2" {
            loc = "19..19"
            type = "binary"
        }
        "PER_mem_statest" {
            loc = "18..17"
            type = "PM__PWRSTT___tate__enum"
            desc = "PER domain memory state status"
        }
        "Reserved__3" {
            loc = "16..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "PowerStateSt" {
            loc = "1..0"
            type = "PM_PER_PWRSTST_PowerStateSt__enum"
            desc = "Current Power State Status"
        }
    }
    "PM_RTC_PWRSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..26"
            type = "binary"
        }
        "Reserved__2" {
            loc = "25..16"
            type = "binary"
        }
        "Reserved__3" {
            loc = "15..5"
            type = "binary"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "Reserved__4" {
            loc = "3..3"
            type = "binary"
        }
        "LogicRETState" {
            loc = "2..2"
            type = "PM__PWRSTCTRL_LogicRETState__enum"
            desc = "Logic state when power domain is RETENTION"
        }
        "Reserved__5" {
            loc = "1..0"
            type = "binary"
        }
    }
    "PM_RTC_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..21"
            type = "binary"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__2" {
            loc = "19..10"
            type = "binary"
        }
        "Reserved__3" {
            loc = "9..4"
            type = "binary"
        }
        "Reserved__4" {
            loc = "3..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "Reserved__5" {
            loc = "1..0"
            type = "binary"
        }
    }
    "PM_WKUP_PWRSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "Reserved__2" {
            loc = "29..29"
            type = "binary"
        }
        "Reserved__3" {
            loc = "28..28"
            type = "binary"
        }
        "Reserved__4" {
            loc = "27..27"
            type = "binary"
        }
        "Reserved__5" {
            loc = "26..25"
            type = "binary"
        }
        "Reserved__6" {
            loc = "24..5"
            type = "binary"
        }
        "LowPowerStateChange" {
            loc = "4..4"
            type = "M_____enum"
            desc = "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."
        }
        "LogicRETState" {
            loc = "3..3"
            type = "PM__PWRSTCTRL_LogicRETState__enum"
            desc = "Logic state when power domain is RETENTION"
        }
        "Reserved__7" {
            loc = "2..2"
            type = "binary"
        }
        "Reserved__8" {
            loc = "1..0"
            type = "binary"
        }
    }
    "PM_WKUP_PWRSTST__bitfield" {
        "Reserved__1" {
            loc = "31..23"
            type = "binary"
        }
        "Reserved__2" {
            loc = "22..21"
            type = "binary"
        }
        "InTransition" {
            loc = "20..20"
            type = "PM__PWRSTST_InTransition__enum"
            desc = "Domain transition status"
        }
        "Reserved__3" {
            loc = "19..19"
            type = "binary"
        }
        "Debugss_mem_statest" {
            loc = "18..17"
            type = "PM__PWRSTT___tate__enum"
            desc = "WKUP domain memory state status"
        }
        "Reserved__4" {
            loc = "16..3"
            type = "binary"
        }
        "LogicStateSt" {
            loc = "2..2"
            type = "PM__PWRSTST_LoStatet__enum"
            desc = "Logic state status"
        }
        "Reserved__5" {
            loc = "1..0"
            type = "binary"
        }
    }
    "PRI_COS_MAP__bitfield" {
        "REG_PRI_COS_MAP_EN" {
            loc = "31..31"
            type = "binary"
            desc = "Set 1 to enable priority to class of service mapping. Set 0 to disable mapping."
        }
        "Reserved" {
            loc = "30..16"
            type = "binary"
        }
        "REG_PRI_7_COS" {
            loc = "15..14"
            type = "binary"
            desc = "Class of service for commands with priority of 7. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_6_COS" {
            loc = "13..12"
            type = "binary"
            desc = "Class of service for commands with priority of 6. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_5_COS" {
            loc = "11..10"
            type = "binary"
            desc = "Class of service for commands with priority of 5. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_4_COS" {
            loc = "9..8"
            type = "binary"
            desc = "Class of service for commands with priority of 4. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_3_COS" {
            loc = "7..6"
            type = "binary"
            desc = "Class of service for commands with priority of 3. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_2_COS" {
            loc = "5..4"
            type = "binary"
            desc = "Class of service for commands with priority of 2. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_1_COS" {
            loc = "3..2"
            type = "binary"
            desc = "Class of service for commands with priority of 1. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
        "REG_PRI_0_COS" {
            loc = "1..0"
            type = "binary"
            desc = "Class of service for commands with priority of 0. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service."
        }
    }
    "PRM_IRQENABLE_M__bitfield" {
        "Reserved__1" {
            loc = "31..16"
            type = "binary"
        }
        "dpll_disp_recal_en" {
            loc = "15..15"
            type = "M_____enum"
            desc = "Interrupt enable for disp dpll recaliberation"
        }
        "dpll_ddr_recal_en" {
            loc = "14..14"
            type = "M_____enum"
            desc = "Interrupt enable for ddr dpll recaliberation"
        }
        "dpll_per_recal_en" {
            loc = "13..13"
            type = "M_____enum"
            desc = "Interrupt enable for usb dpll recaliberation"
        }
        "dpll_core_recal_en" {
            loc = "12..12"
            type = "M_____enum"
            desc = "Interrupt enable for core dpll recaliberation"
        }
        "dpll_mpu_recal_en" {
            loc = "11..11"
            type = "M_____enum"
            desc = "Interrupt enable for mpu dpll recaliberation"
        }
        "ForceWkup_en" {
            loc = "10..10"
            type = "PRM_IRQENABLE_M_o_en__enum"
            desc = "Software supervised Froce Wakeup completed event interrupt enable"
        }
        "Reserved__2" {
            loc = "9..9"
            type = "binary"
        }
        "Transition_en" {
            loc = "8..8"
            type = "PRM_IRQENABLE_M_o_en__enum"
            desc = "Software supervised transition completed event interrupt enable (any domain)"
        }
        "Reserved__3" {
            loc = "7..6"
            type = "binary"
        }
        "Reserved__4" {
            loc = "5..1"
            type = "binary"
        }
        "Reserved__5" {
            loc = "0..0"
            type = "binary"
        }
    }
    "PRM_IRQSTATUS_M__bitfield" {
        "Reserved__1" {
            loc = "31..16"
            type = "binary"
        }
        "dpll_per_recal_st" {
            loc = "15..15"
            type = "M_____enum"
            desc = "interrupt status for usb dpll recaliberation"
        }
        "dpll_ddr_recal_st" {
            loc = "14..14"
            type = "M_____enum"
            desc = "interrupt status for ddr dpll recaliberation"
        }
        "dpll_disp_recal_st" {
            loc = "13..13"
            type = "M_____enum"
            desc = "interrupt status for disp dpll recaliberation"
        }
        "dpll_core_recal_st" {
            loc = "12..12"
            type = "M_____enum"
            desc = "interrupt status for core dpll recaliberation"
        }
        "dpll_mpu_recal_st" {
            loc = "11..11"
            type = "M_____enum"
            desc = "interrupt status for mpu dpll recaliberation"
        }
        "ForceWkup_st" {
            loc = "10..10"
            type = "PRM_IRQSTATUS_M_o_st__enum"
            desc = "Software supervised wakeup completed event interrupt status"
        }
        "Reserved__2" {
            loc = "9..9"
            type = "binary"
        }
        "Transition_st" {
            loc = "8..8"
            type = "PRM_IRQSTATUS_M_o_st__enum"
            desc = "Software supervised transition completed event interrupt status (any domain)"
        }
        "Reserved__3" {
            loc = "7..0"
            type = "binary"
        }
    }
    "PRM_LDO_SRAM__CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "SRAM_IN_TRANSITION" {
            loc = "9..9"
            type = "PRM_LDO_SRAM_SRAM_IN_TRANSITION__enum"
            desc = "Status indicating SRAM LDO state machine state."
        }
        "SRAMLDO_STATUS" {
            loc = "8..8"
            type = "PRM_LDO_SRAM_SRAMLDO_STATUS__enum"
            desc = "SRAMLDO status"
        }
        "Reserved__2" {
            loc = "7..1"
            type = "binary"
        }
        "RETMODE_ENABLE" {
            loc = "0..0"
            type = "M_LMODE_L__enum"
            desc = "Control if the SRAM LDO retention mode is used or not."
        }
    }
    "PRM_LDO_SRAM__SETUP__bitfield" {
        "Reserved" {
            loc = "31..9"
            type = "binary"
        }
        "AIPOFF" {
            loc = "8..8"
            type = "PRM_LDO_SRAM_AIPOFF__enum"
            desc = "Override on AIPOFF input of SRAM LDO."
        }
        "ENFUNC5" {
            loc = "7..7"
            type = "PRM_LDO_SRAM_ENFUNC5__enum"
            desc = "ENFUNC5 input of SRAM LDO."
        }
        "ENFUNC4" {
            loc = "6..6"
            type = "PRM_LDO_SRAM_ENFUNC4__enum"
            desc = "ENFUNC4 input of SRAM LDO."
        }
        "ENFUNC3_EXPORT" {
            loc = "5..5"
            type = "PRM_LDO_SRAM_ENFUNC3_EXPORT__enum"
            desc = "ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
        "ENFUNC2_EXPORT" {
            loc = "4..4"
            type = "PRM_LDO_SRAM_ENFUNC2_EXPORT__enum"
            desc = "ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
        "ENFUNC1_EXPORT" {
            loc = "3..3"
            type = "PRM_LDO_SRAM_ENFUNC1_EXPORT__enum"
            desc = "ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
        "ABBOFF_SLEEP_EXPORT" {
            loc = "2..2"
            type = "PRM_LDO_SRAM_ABBOFF_SLEEP_EXPORT__enum"
            desc = "Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
        "ABBOFF_ACT_EXPORT" {
            loc = "1..1"
            type = "PRM_LDO_SRAM_ABBOFF_ACT_EXPORT__enum"
            desc = "Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
        "DISABLE_RTA_EXPORT" {
            loc = "0..0"
            type = "PRM_LDO_SRAM_DISABLE_RTA_EXPORT__enum"
            desc = "Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this."
        }
    }
    "PRM_RSTCTRL__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "RST_GLOBAL_COLD_SW" {
            loc = "1..1"
            type = "PRM_RST_RST__enum"
            desc = "Global COLD software reset control.  This bit is reset only upon a global cold source of reset. Read returns 0."
        }
        "RST_GLOBAL_WARM_SW" {
            loc = "0..0"
            type = "PRM_RST_RST__enum"
            desc = "Global WARM software reset control.  This bit is reset upon any global source of reset (warm and cold).  Read returns 0."
        }
    }
    "PRM_RSTST__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "ICEPICK_RST" {
            loc = "9..9"
            type = "PRM_RST_RST__enum"
            desc = "IcePick reset event.  This is a source of global warm reset initiated by the emulation. [warm reset insensitive]"
        }
        "Reserved__2" {
            loc = "8..6"
            type = "binary"
        }
        "EXTERNAL_WARM_RST" {
            loc = "5..5"
            type = "PRM_RST_RST__enum"
            desc = "External warm reset event [warm reset insensitive]"
        }
        "WDT1_RST" {
            loc = "4..4"
            type = "PRM_RST_RST__enum"
            desc = "Watchdog1 timer reset event. This is a source of global WARM reset. [warm reset insensitive]"
        }
        "Reserved__3" {
            loc = "3..3"
            type = "binary"
        }
        "Reserved__4" {
            loc = "2..2"
            type = "binary"
        }
        "GLOBAL_WARM_SW_RST" {
            loc = "1..1"
            type = "PRM_RST_RST__enum"
            desc = "Global warm software reset event [warm reset insensitive]"
        }
        "GLOBAL_COLD_RST" {
            loc = "0..0"
            type = "PRM_RST_RST__enum"
            desc = "Power-on (cold) reset event [warm reset insensitive]"
        }
    }
    "PRM_RSTTIME__bitfield" {
        "Reserved" {
            loc = "31..13"
            type = "binary"
        }
        "RSTTIME2" {
            loc = "12..8"
            type = "binary"
            desc = "(Power domain) reset duration 2 (number of RM.SYSCLK clock cycles)"
        }
        "RSTTIME1" {
            loc = "7..0"
            type = "binary"
            desc = "(Global) reset duration 1 (number of SYS_CLK clock cycles)"
        }
    }
    "PRM_SRAM_COUNT__bitfield" {
        "StartUp_Count" {
            loc = "31..24"
            type = "binary"
            desc = "Determines the start-up duration of SRAM and ABB LDO. The duration is computed as 16 x NbCycles of system clock cycles. Target is 50us."
        }
        "SLPCNT_VALUE" {
            loc = "23..16"
            type = "binary"
            desc = "Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high. Counting on system clock. Target is 2us."
        }
        "VSETUPCNT_VALUE" {
            loc = "15..8"
            type = "binary"
            desc = "SRAM LDO rampup time from retention to active mode. The duration is computed as 8 x NbCycles of system clock cycles. Target is 30us."
        }
        "Reserved" {
            loc = "7..6"
            type = "binary"
        }
        "PCHARGECNT_VALUE" {
            loc = "5..0"
            type = "binary"
            desc = "Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns."
        }
    }
    "PWMSS_CLKCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "ePWMCLKSTOP_REQ" {
            loc = "9..9"
            type = "binary"
            desc = "This bit controls the clkstop_req input to the ePWM module."
        }
        "ePWMCLK_EN" {
            loc = "8..8"
            type = "binary"
            desc = "This bit controls the clk_en input to the ePWM module."
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "eQEPCLKSTOP_REQ" {
            loc = "5..5"
            type = "binary"
            desc = "This bit controls the clkstop_req input to the eQEP module"
        }
        "eQEPCLK_EN" {
            loc = "4..4"
            type = "binary"
            desc = "This bit controls the clk_en input to the eQEP module."
        }
        "Reserved__3" {
            loc = "3..2"
            type = "binary"
        }
        "eCAPCLKSTOP_REQ" {
            loc = "1..1"
            type = "binary"
            desc = "This bit controls the clkstop_req input to the eCAP module."
        }
        "eCAPCLK_EN" {
            loc = "0..0"
            type = "binary"
            desc = "This bit controls the clk_en input to the eCAP module."
        }
    }
    "PWMSS_CLKSTATUS__bitfield" {
        "Reserved__1" {
            loc = "31..10"
            type = "binary"
        }
        "ePWM_CLKSTOP_ACK" {
            loc = "9..9"
            type = "binary"
            desc = "This bit is the clkstop_req_ack status output of the ePWM module."
        }
        "ePWM_CLK_EN_ACK" {
            loc = "8..8"
            type = "binary"
            desc = "This bit is the clk_en status output of the ePWM module."
        }
        "Reserved__2" {
            loc = "7..6"
            type = "binary"
        }
        "eQEP_CLKSTOP_ACK" {
            loc = "5..5"
            type = "binary"
            desc = "This bit is the clkstop_req_ack status output of the eQEP module."
        }
        "eQEP_CLK_EN_ACK" {
            loc = "4..4"
            type = "binary"
            desc = "This bit is the clk_en status output of the eQEP module."
        }
        "Reserved__3" {
            loc = "3..2"
            type = "binary"
        }
        "eCAP_CLKSTOP_ACK" {
            loc = "1..1"
            type = "binary"
            desc = "This bit is the clkstop_req_ack status output of the eCAP module."
        }
        "eCAP_CLK_EN_ACK" {
            loc = "0..0"
            type = "binary"
            desc = "This bit is the clk_en status output of the eCAP module."
        }
    }
    "PWMSS_IDVER__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between the old scheme and current."
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "FUNC"
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL version (R), maintained by IP design owner."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision (X)"
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "CUSTOM"
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision (Y)"
        }
    }
    "PWMSS_SYSCONFIG__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "STANDBYMODE" {
            loc = "5..4"
            type = "binary"
            desc = "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."
        }
        "IDLEMODE" {
            loc = "3..2"
            type = "binary"
            desc = "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."
        }
        "FREEEMU" {
            loc = "1..1"
            type = "binary"
            desc = "Sensitivity to emulation (debug) suspend input signal."
        }
        "SOFTRESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset (optional)"
        }
    }
    "PWR_MGMT_CTRL_SHDW__bitfield" {
        "Reserved" {
            loc = "31..12"
            type = "binary"
        }
        "reg_pd_tim_shdw" {
            loc = "11..8"
            type = "binary"
            desc = "Shadow field for reg_pd_tim. This field is loaded into reg_pd_tim field in Power Management Control register when SIdleAck is asserted."
        }
        "reg_sr_tim_shdw" {
            loc = "7..4"
            type = "binary"
            desc = "Shadow field for reg_sr_tim. This field is loaded into reg_sr_tim field in Power Management Control register when SIdleAck is asserted."
        }
        "reg_cs_tim_shdw" {
            loc = "3..0"
            type = "binary"
            desc = "Shadow field for reg_cs_tim. This field is loaded into reg_cs_tim field in Power Management Control register when SIdleAck is asserted."
        }
    }
    "PWR_MGMT_CTRL__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "reg_pd_tim" {
            loc = "15..12"
            type = "binary"
            desc = "Power Mangement timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of m_clk cycles and if reg_lp_mode field is set to 4. Set to 0 to immediately enter Power-Down mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks."
        }
        "reg_dpd_en" {
            loc = "11..11"
            type = "binary"
            desc = "Deep Power Down enable. Set to 0 for normal operation. Set to 1 to enter deep power down mode. This mode will override the reg_lp_mode field setting."
        }
        "reg_lp_mode" {
            loc = "10..8"
            type = "binary"
            desc = "Automatic Power Management enable. Set to 1 for Clock Stop, set to 2 for Self Refresh, and set to 4 for Power-Down. All other values will disable automatic power management."
        }
        "reg_sr_tim" {
            loc = "7..4"
            type = "binary"
            desc = "Power Mangement timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of m_clk cycles and if reg_lp_mode field is set to 2. Set to 0 to immediately enter Self Refresh mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks."
        }
        "reg_cs_tim" {
            loc = "3..0"
            type = "binary"
            desc = "Power Mangement timer for Clock Stop. The EMIF will put the external SDRAM in Clock Stop mode after the EMIF is idle for these number of m_clk cycles and if reg_lp_mode field is set to 1. Set to 0 to immediately enter Clock Stop mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks."
        }
    }
    "QMEMCTRL__bitfield" {
        "START_INDEX" {
            loc = "29..16"
            type = "binary"
            desc = "This field indicates where in linking RAM does the  descriptor linking information corresponding to memory  region R starts."
        }
        "DESC_SIZE" {
            loc = "11..8"
            type = "binary"
            desc = "This field indicates the size of each descriptor in this  memory region. It is an encoded value that specifies  descriptor size as 2^(5+desc_size) number of bytes.  The settings of desc_size from 9-15 are reserved."
        }
        "REG_SIZE" {
            loc = "2..0"
            type = "binary"
            desc = "This field indicates the size of the memory region (in  terms of number of descriptors). It is an encoded value  that specifies region size as 2^(5+reg_size) number of  descriptors. Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each  queue in the queues region. For reasons of implementation and area efficiency, these registers  are not actually implemented as a huge array of flip flops but are instead implemented as a  single set of mailbox registers which use the LSBs of the provided address as a queue index.  Due to this implementation all accesses to these registers need to be performed as a single  burst write for each packet push operation or a single burst read for each packet pop operation.  The length of a burst to push or pop a packet will vary depending on the optional features that  the queue supports which may be 4, 8, 12 or 16 bytes. Queue N Register D must always be  written / read in the burst but the preceding words are optional depending on the required queue  functionality."
        }
    }
    "QMEMRBASE__bitfield" {
        "REG" {
            loc = "31..5"
            type = "binary"
            desc = "This field contains the base address of the memory  region R."
        }
    }
    "QMGRREVID__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Scheme that this register is compliant with"
        }
        "FUNCTION" {
            loc = "27..16"
            type = "binary"
            desc = "Function"
        }
        "REVRTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision"
        }
        "REVMAJ" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision"
        }
        "REVCUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Custom revision"
        }
        "REVMIN" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision Queue Manager Revision Register"
        }
    }
    "QMGRRST__bitfield" {
        "HEAD_TAIL" {
            loc = "31..31"
            type = "binary"
            desc = "Indicates whether queue contents should be merged on  to head or tail of destination queue. Clear this field for  head and set for tail."
        }
        "DEST_QNUM" {
            loc = "29..16"
            type = "binary"
            desc = "Destination Queue Number"
        }
        "SOURCE_QNUM" {
            loc = "13..0"
            type = "binary"
            desc = "Source Queue Number Queue Manager Queue Diversion Register Note : CBA write transactions to this register cause the QMGR to start processing an internal  state machine. This disables CBA read transactions.while it is busy processing the state  machine.  Once the state machine is back in the idle state ; CBA read transactions are available  again."
        }
    }
    "QUEUE__A__bitfield" {
        "QUEUE_ENTRY_COUNT" {
            loc = "13..0"
            type = "binary"
            desc = "This field indicates how many packets are currently  queued on the queue. This count is incremented by 1  whenever a packet is added to the queue. This count is  decremented by 1 whenever a packet is popped from  the queue."
        }
    }
    "QUEUE__B__bitfield" {
        "QUEUE_BYTE_COUNT" {
            loc = "27..0"
            type = "binary"
            desc = "This field indicates how many bytes total are contained  in all of the packets which are currently queued on this  queue."
        }
    }
    "QUEUE__C__bitfield" {
        "HEAD_TAIL" {
            loc = "31..31"
            type = "binary"
            desc = "Head/Tail Push Control. Set to zero in order to push  packet onto tail of queue and set to one in order to  push packet onto head of queue."
        }
        "PACKET_SIZE" {
            loc = "13..0"
            type = "binary"
            desc = "packet_size This field indicates packet size and is assumed to be  zero on each packet add unless the value is explicitly  overwritten. This field indicates packet size for packet  pop operation."
        }
    }
    "QUEUE__D__bitfield" {
        "DESC_PTR" {
            loc = "31..5"
            type = "binary"
            desc = "Descriptor pointer. It will be read as zero if the queue is  empty. It will indicate a 32-bit aligned address that  points to a descriptor when the queue is not empty."
        }
        "DESC_SIZE" {
            loc = "4..0"
            type = "binary"
            desc = "Descriptor Size. It is encoded in 4-byte increments with  values 0 to 31 representing 24 and so on to 148 bytes.  This field will return a 0x0 when an empty queue is read. Queue Manager Queue N Registers D To save hardware resources, the queue manager internally stores descriptor size (desc_size)  information in four bits. However, register D has five LSBs that specify descriptor size. As a  consequence, the value of desc_size that is pushed may not be same as that is read during a  pop. The value that is read back is equal to always rounded to an odd number. So, for even  values, the value read back is one more than what was written. For odd values, the value read  back is same as the value that was written. Note that this 5-bit field (desc_size) is unrelated to the  code for size of descriptors in a descriptor region. It is just a place holder for a 5-bit value that is  maintained across the push and pop operations for every descriptor managed by the queue  manager."
        }
    }
    "QUEUE__STATUS_A__bitfield" {
        "QUEUE_ENTRY_COUNT" {
            loc = "13..0"
            type = "binary"
            desc = "This field indicates how many packets are currently  queued on the queue. Queue Manager Queue N Status Registers A"
        }
    }
    "QUEUE__STATUS_B__bitfield" {
        "QUEUE_BYTE_COUNT" {
            loc = "27..0"
            type = "binary"
            desc = "This field indicates how many bytes total are contained  in all of the packets which are currently queued on this  queue. Queue_Manager_Queue_n_Status_B Registers B"
        }
    }
    "QUEUE__STATUS_C__bitfield" {
        "PACKET_SIZE" {
            loc = "13..0"
            type = "binary"
            desc = "This field indicates packet size of the head element of a  queue. Queue_Manager_Queue_N_Status_C Registers C"
        }
    }
    "RDWR_LVL_CTRL__bitfield" {
        "REG_RDWRLVLFULL_START" {
            loc = "31..31"
            type = "binary"
            desc = "Full leveling trigger. Writing a 1 to this field triggers full read and write leveling. This bit will self-clear to 0."
        }
        "REG_RDWRLVLINC_PRE" {
            loc = "30..24"
            type = "binary"
            desc = "Incremental leveling pre-scalar in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register."
        }
        "REG_RDLVLINC_INT" {
            loc = "23..16"
            type = "binary"
            desc = "Incremental read data eye training interval. Number of reg_rdwrlvlinc_pre intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training."
        }
        "REG_RDLVLGATEINC_INT" {
            loc = "15..8"
            type = "binary"
            desc = "Incremental read DQS gate training interval. Number of reg_rdwrlvlinc_pre intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training."
        }
        "REG_WRLVLINC_INT" {
            loc = "7..0"
            type = "binary"
            desc = "Incremental write leveling interval. Number of reg_rdwrlvlinc_pre intervals between incremental write leveling. A value of 0 will disable incremental write leveling."
        }
    }
    "RDWR_LVL_RMP_CTRL__bitfield" {
        "REG_RDWRLVL_EN" {
            loc = "31..31"
            type = "binary"
            desc = "Read-Write Leveling enable.  Set 1 to enable leveling. Set 0 to disable leveling."
        }
        "REG_RDWRLVLINC_RMP_PRE" {
            loc = "30..24"
            type = "binary"
            desc = "Incremental leveling pre-scalar in number of refresh periods during ramp window. The value programmed is minus one the required value. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register."
        }
        "REG_RDLVLINC_RMP_INT" {
            loc = "23..16"
            type = "binary"
            desc = "Incremental read data eye training interval during ramp window. Number of reg_rdwrlvlinc_rmp_pre intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training during ramp window."
        }
        "REG_RDLVLGATEINC_RMP_INT" {
            loc = "15..8"
            type = "binary"
            desc = "Incremental read DQS gate training interval during ramp window. Number of reg_rdwrlvlinc_rmp_pre intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training during ramp window."
        }
        "REG_WRLVLINC_RMP_INT" {
            loc = "7..0"
            type = "binary"
            desc = "Incremental write leveling interval during ramp window. Number of reg_rdwrlvlinc_rmp_pre intervals between incremental write leveling. A value of 0 will disable incremental write leveling during ramp window."
        }
    }
    "RDWR_LVL_RMP_WIN__bitfield" {
        "Reserved" {
            loc = "31..13"
            type = "binary"
        }
        "REG_RDWRLVLINC_RMP_WIN" {
            loc = "12..0"
            type = "binary"
            desc = "Incremental leveling ramp window in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register."
        }
    }
    "RD_WR_EXEC_THRSH__bitfield" {
        "Reserved__1" {
            loc = "31..13"
            type = "binary"
        }
        "REG_WR_THRSH" {
            loc = "12..8"
            type = "binary"
            desc = "Write Threshold. Number of SDRAM write bursts after which the EMIF arbitration will switch to executing read commands. The value programmed is always minus one the required number."
        }
        "Reserved__2" {
            loc = "7..5"
            type = "binary"
        }
        "REG_RD_THRSH" {
            loc = "4..0"
            type = "binary"
            desc = "Read Threshold. Number of SDRAM read bursts after which the EMIF arbitration will switch to executing write commands. The value programmed is always minus one the required number."
        }
    }
    "READ_IDLE_CTRL_SHDW__bitfield" {
        "Reserved__1" {
            loc = "31..20"
            type = "binary"
        }
        "reg_read_idle_len_shdw" {
            loc = "19..16"
            type = "binary"
            desc = "Shadow field for reg_read_idle_len. This field is loaded into reg_read_idle_len field in Read Idle Control register when SIdleAck is asserted"
        }
        "Reserved__2" {
            loc = "15..9"
            type = "binary"
        }
        "reg_read_idle_interval_shdw" {
            loc = "8..0"
            type = "binary"
            desc = "Shadow field for reg_read_idle_interval. This field is loaded into reg_read_idle_interval field in Read Idle Control register when SIdleAck is asserted."
        }
    }
    "READ_IDLE_CTRL__bitfield" {
        "Reserved__1" {
            loc = "31..20"
            type = "binary"
        }
        "reg_read_idle_len" {
            loc = "19..16"
            type = "binary"
            desc = "The Read Idle Length field determines the minimum size (reg_read_idle_len-1 clock cycles) of Read Idle window for the read idle detection as well as the force read idle time."
        }
        "Reserved__2" {
            loc = "15..9"
            type = "binary"
        }
        "reg_read_idle_interval" {
            loc = "8..0"
            type = "binary"
            desc = "The Read Idle Interval field determines the maximum interval ((reg_read_idle_interval-1)*64 clock cycles) between read idle detections or force. A value of zero disables the read idle function."
        }
    }
    "REVISION__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "Rev" {
            loc = "7..0"
            type = "binary"
            desc = "IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1"
        }
    }
    "RM_GFX_RSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..4"
            type = "binary"
        }
        "Reserved__2" {
            loc = "3..2"
            type = "binary"
        }
        "Reserved__3" {
            loc = "1..1"
            type = "binary"
        }
        "GFX_RST" {
            loc = "0..0"
            type = "RM__RSTCTRL__RST__enum"
            desc = "GFX domain local reset control"
        }
    }
    "RM_GFX_RSTST__bitfield" {
        "Reserved__1" {
            loc = "31..12"
            type = "binary"
        }
        "Reserved__2" {
            loc = "11..2"
            type = "binary"
        }
        "Reserved__3" {
            loc = "1..1"
            type = "binary"
        }
        "GFX_RST" {
            loc = "0..0"
            type = "RM__RSTST__RST__enum"
            desc = "GFX Domain Logic Reset"
        }
    }
    "RM_MPU_RSTST__bitfield" {
        "Reserved__1" {
            loc = "31..15"
            type = "binary"
        }
        "Reserved__2" {
            loc = "14..8"
            type = "binary"
        }
        "Reserved__3" {
            loc = "7..7"
            type = "binary"
        }
        "ICECRUSHER_MPU_RST" {
            loc = "6..6"
            type = "RM__RSTST__RST__enum"
            desc = "MPU Processor  has been reset due to MPU ICECRUSHER1 reset event"
        }
        "EMULATION_MPU_RST" {
            loc = "5..5"
            type = "RM__RSTST__RST__enum"
            desc = "MPU Processor  has been reset due to emulation reset source  e.g. assert reset command initiated by the icepick module"
        }
        "Reserved__4" {
            loc = "4..4"
            type = "binary"
        }
        "Reserved__5" {
            loc = "3..3"
            type = "binary"
        }
        "Reserved__6" {
            loc = "2..2"
            type = "binary"
        }
        "Reserved__7" {
            loc = "1..0"
            type = "binary"
        }
    }
    "RM_PER_RSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "Reserved__2" {
            loc = "5..3"
            type = "binary"
        }
        "Reserved__3" {
            loc = "2..2"
            type = "binary"
        }
        "PRU_ICSS_LRST" {
            loc = "1..1"
            type = "RM__RSTCTRL__RST__enum"
            desc = "PER domain PRU-ICSS local reset control"
        }
        "Reserved__4" {
            loc = "0..0"
            type = "binary"
        }
    }
    "RM_WKUP_RSTCTRL__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "Reserved__2" {
            loc = "5..4"
            type = "binary"
        }
        "WKUP_M3_LRST" {
            loc = "3..3"
            type = "RM__RSTCTRL__RST__enum"
            desc = "Assert Reset to WKUP_M3"
        }
        "Reserved__3" {
            loc = "2..0"
            type = "binary"
        }
    }
    "RM_WKUP_RSTST__bitfield" {
        "Reserved__1" {
            loc = "31..8"
            type = "binary"
        }
        "ICECRUSHER_M3_RST" {
            loc = "7..7"
            type = "RM__RSTST__RST__enum"
            desc = "M3 Processor  has been reset due to M3 ICECRUSHER1 reset event"
        }
        "EMULATION_M3_RST" {
            loc = "6..6"
            type = "RM__RSTST__RST__enum"
            desc = "M3 Processor  has been reset due to emulation reset source  e.g. assert reset command initiated by the icepick module"
        }
        "WKUP_M3_LRST" {
            loc = "5..5"
            type = "RM__RSTST__RST__enum"
            desc = "M3 Processor  has been reset"
        }
        "Reserved__2" {
            loc = "4..0"
            type = "binary"
        }
    }
    "RTC_COMP_LSB_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "RTC_COMP_LSB" {
            loc = "7..0"
            type = "binary"
            desc = "Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour"
        }
    }
    "RTC_COMP_MSB_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "RTC_COMP_MSB" {
            loc = "7..0"
            type = "binary"
            desc = "Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour"
        }
    }
    "RTC_CTRL_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "RTC_DISABLE" {
            loc = "6..6"
            type = "binary"
            desc = "Disable RTC module and gate 32-kHz reference clock."
        }
        "SET_32_COUNTER" {
            loc = "5..5"
            type = "binary"
            desc = "Set the 32-kHz counter with the value stored in the compensation registers when the SET_32_COUNTER bit is set."
        }
        "TEST_MODE" {
            loc = "4..4"
            type = "binary"
            desc = "Test mode."
        }
        "MODE_12_24" {
            loc = "3..3"
            type = "binary"
            desc = "Enable 12-hour mode for HOURS and ALARMHOURS registers."
        }
        "AUTO_COMP" {
            loc = "2..2"
            type = "binary"
            desc = "Enable oscillator compensation mode."
        }
        "ROUND_30S" {
            loc = "1..1"
            type = "binary"
            desc = "Enable one-time rounding to nearest minute on next time register read."
        }
        "STOP_RTC" {
            loc = "0..0"
            type = "binary"
            desc = "Stop the RTC 32-kHz counter."
        }
    }
    "RTC_DEBOUNCE__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "DEBOUNCE_REG" {
            loc = "7..0"
            type = "binary"
            desc = "Debounce time. A value, n, other than 0 results in a debounce time of 30.52 s*(n+1)."
        }
    }
    "RTC_INTERRUPTS_REG__bitfield" {
        "Reserved" {
            loc = "31..5"
            type = "binary"
        }
        "IT_ALARM2" {
            loc = "4..4"
            type = "binary"
            desc = "Enable one interrupt when the alarm value is reached (TC ALARM2 registers) by the TC registers"
        }
        "IT_ALARM" {
            loc = "3..3"
            type = "binary"
            desc = "Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers"
        }
        "IT_TIMER" {
            loc = "2..2"
            type = "binary"
            desc = "Enable periodic interrupt."
        }
        "EVERY" {
            loc = "1..0"
            type = "binary"
            desc = "Interrupt period."
        }
    }
    "RTC_IRQWAKEEN__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "ALARM_WAKEEN" {
            loc = "1..1"
            type = "binary"
            desc = "Wakeup generation for event Alarm."
        }
        "TIMER_WAKEEN" {
            loc = "0..0"
            type = "binary"
            desc = "Wakeup generation for event Timer."
        }
    }
    "RTC_OSC_REG__bitfield" {
        "Reserved__1" {
            loc = "31..7"
            type = "binary"
        }
        "32KCLK_EN" {
            loc = "6..6"
            type = "binary"
            desc = "32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk"
        }
        "Reserved__2" {
            loc = "5..5"
            type = "binary"
        }
        "OSC32K_GZ" {
            loc = "4..4"
            type = "binary"
            desc = "Disable the oscillator and apply high impedance to the output"
        }
        "32KCLK_SEL" {
            loc = "3..3"
            type = "binary"
            desc = "32-kHz clock source select"
        }
        "RES_SELECT" {
            loc = "2..2"
            type = "binary"
            desc = "External feedback resistor"
        }
        "SW2" {
            loc = "1..1"
            type = "binary"
            desc = "Inverter size adjustment"
        }
        "SW1" {
            loc = "0..0"
            type = "binary"
            desc = "Inverter size adjustment"
        }
    }
    "RTC_PMIC__bitfield" {
        "Reserved" {
            loc = "31..19"
            type = "binary"
        }
        "PWR_ENABLE_SM" {
            loc = "18..17"
            type = "binary"
            desc = "Power state machine state."
        }
        "PWR_ENABLE_EN" {
            loc = "16..16"
            type = "binary"
            desc = "Enable for PMIC_POWER_EN signal"
        }
        "EXT_WAKEUP_STATUS" {
            loc = "15..12"
            type = "binary"
            desc = "External wakeup status. Write 1 to clear EXT_WAKEUP_STATUS[n] status of ext_wakeup[n]."
        }
        "EXT_WAKEUP_DB_EN" {
            loc = "11..8"
            type = "binary"
            desc = "External wakeup debounce enabled. EXT_WAKEUP_DB_EN[n] controls ext_wakeup[n]"
        }
        "EXT_WAKEUP_POL" {
            loc = "7..4"
            type = "binary"
            desc = "External wakeup inputs polarity. EXT_WAKEUP_POL[n] controls ext_wakeup[n]."
        }
        "EXT_WAKEUP_EN" {
            loc = "3..0"
            type = "binary"
            desc = "Enable external wakeup inputs. EXT_WAKEUP_EN[n] controls ext_wakeup[n]."
        }
    }
    "RTC_REVISION__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between old scheme and current"
        }
        "Reserved" {
            loc = "29..28"
            type = "binary"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Function indicates a software compatible module family"
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL Version (R)"
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major Revision"
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Indicates a special version for a particular device"
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor Revision (Y)"
        }
    }
    "RTC_SCRATCH0_REG__bitfield" {
        "RTCSCRATCH0" {
            loc = "31..0"
            type = "binary"
            desc = "Scratch registers, available to program"
        }
    }
    "RTC_SCRATCH1_REG__bitfield" {
        "RTCSCRATCH1" {
            loc = "31..0"
            type = "binary"
            desc = "Scratch registers, available to program"
        }
    }
    "RTC_SCRATCH2_REG__bitfield" {
        "RTCSCRATCH2" {
            loc = "31..0"
            type = "binary"
            desc = "Scratch registers, available to program"
        }
    }
    "RTC_STATUS_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "ALARM2" {
            loc = "7..7"
            type = "binary"
            desc = "Indicates that an alarm2 interrupt has been generated. Software needs to wait 31 s before it clears this status to allow pmic_pwr_enable 1 ' 0 transmission."
        }
        "ALARM" {
            loc = "6..6"
            type = "binary"
            desc = "Indicates that an alarm interrupt has been generated"
        }
        "1D_EVENT" {
            loc = "5..5"
            type = "binary"
            desc = "One day has occurred"
        }
        "1H_EVENT" {
            loc = "4..4"
            type = "binary"
            desc = "One hour has occurred"
        }
        "1M_EVENT" {
            loc = "3..3"
            type = "binary"
            desc = "One minute has occurred"
        }
        "1S_EVENT" {
            loc = "2..2"
            type = "binary"
            desc = "One second has occurred"
        }
        "RUN" {
            loc = "1..1"
            type = "binary"
            desc = "RTC is frozen or is running."
        }
        "BUSY" {
            loc = "0..0"
            type = "binary"
            desc = "Status of RTC module."
        }
    }
    "RTC_SYSCONFIG__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "IDLEMODE" {
            loc = "1..0"
            type = "binary"
            desc = "Configuration of the local target state management mode, By definition target can handle read/write transaction as long as it is out of IDLE state."
        }
    }
    "RXGCR__bitfield" {
        "RX_ENABLE" {
            loc = "31..31"
            type = "binary"
            desc = "This field enables or disables the channel 0 = channel is disabled 1 = channel is enabled This field will be cleared after a channel teardown is  complete."
        }
        "RX_TEARDOWN" {
            loc = "30..30"
            type = "binary"
            desc = "This field indicates whether or not an Rx teardown operation  is complete.  This field should be cleared when a channel is  initialized.  This field will be set after a channel teardown is  complete."
        }
        "RX_PAUSE" {
            loc = "29..29"
            type = "binary"
            desc = "Setting this bit causes the CPPI DMA to be suspended for rx  channels.  If a pause is being requested and the channel is  not in a packet then drop the credit."
        }
        "RX_ERROR_HANDLING" {
            loc = "24..24"
            type = "binary"
            desc = "This bit controls the error handling mode for the channel and  is only used when channel errors (i.e. descriptor or buffer  starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming  any used descriptor or buffer resources back to the original  queues/pools they were allocated to 1 = Starvation errors result in subsequent re-try of the  descriptor allocation operation.  In this mode, the DMA will  return to the IDLE state without saving it's internal operational  state back to the internal state RAM and without issuing an  advance operation on the FIFO interface.  This results in the  DMA re-initiating the FIFO block transfer at a later time with  the intention that additional free buffers and/or descriptors  will have been added. Regardless of the value of this bit, the DMA will assert the  cdma_rx_sof_overrun (for SOP) or cdma_rx_mof_overrun  (for non-SOP) when"
        }
        "RX_SOP_OFFSET" {
            loc = "23..16"
            type = "binary"
            desc = "This field specifies the number of bytes that are to be  skipped in the SOP buffer before beginning to write the  payload.  This value must be less than the minimum size of a  buffer in the system.  Valid values are 0 - 255 bytes."
        }
        "RX_DEFAULT_DESC_TYPE" {
            loc = "15..14"
            type = "binary"
            desc = "This field indicates the default descriptor type to use: 0 = Reserved 1 = Host 2 = Reserved 3 = Reserved The actual descriptor type that will be used for reception can be overridden by information provided in the CPPI FIFO data block."
        }
        "RX_DEFAULT_RQ_QMGR" {
            loc = "13..12"
            type = "binary"
            desc = "This field indicates the default receive queue manager that  this channel should use.  The actual receive queue manager  index can be overridden by information provided in the CPPI  FIFO data block."
        }
        "RX_DEFAULT_RQ_QNUM" {
            loc = "11..0"
            type = "binary"
            desc = "This field indicates the default receive queue that this channel  should use.  The actual receive queue that will be used for  reception can be overridden by information provided in the  CPPI FIFO data block. Table 99 -Rx Channel N Global Configuration Registers"
        }
    }
    "RXHPCRA__bitfield" {
        "RX_HOST_FDQ1_QMGR" {
            loc = "29..28"
            type = "binary"
            desc = "This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet."
        }
        "RX_HOST_FDQ1_QNUM" {
            loc = "27..16"
            type = "binary"
            desc = "This field specifies which Free Descriptor / Buffer Pool should  be used for the 2nd Rx buffer in a host type packet"
        }
        "RX_HOST_FDQ0_QMGR" {
            loc = "13..12"
            type = "binary"
            desc = "This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet."
        }
        "RX_HOST_FDQ0_QNUM" {
            loc = "11..0"
            type = "binary"
            desc = "This field specifies which Free Descriptor / Buffer Pool should  be used for the 1st Rx buffer in a host type packet Table 100 -Rx Channel N Host Packet Configuration Registers A"
        }
    }
    "RXHPCRB__bitfield" {
        "RX_HOST_FDQ3_QMGR" {
            loc = "29..28"
            type = "binary"
            desc = "This field specifies which  Manager should be used for the 4th or  later Rx buffers in a host type packet"
        }
        "RX_HOST_FDQ3_QNUM" {
            loc = "27..16"
            type = "binary"
            desc = "This field specifies which Free Descriptor Queue should be  used for the 4th or later Rx  buffers in a host type packet"
        }
        "RX_HOST_FDQ2_QMGR" {
            loc = "13..12"
            type = "binary"
            desc = "This field specifies which Buffer Manager should be used for  the 3rd Rx buffer in a host type packet"
        }
        "RX_HOST_FDQ2_QNUM" {
            loc = "11..0"
            type = "binary"
            desc = "This field specifies which Free Descriptor / Buffer Pool should  be used for the 3rd Rx buffer in a host type packet Table 101 -Rx Channel N Host Packet Configuration Registers B"
        }
    }
    "RX_CP__bitfield" {
        "RX_CP" {
            loc = "31..0"
            type = "binary"
            desc = "Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal."
        }
    }
    "RX_HDP__bitfield" {
        "RX_HDP" {
            loc = "31..0"
            type = "binary"
            desc = "RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset."
        }
    }
    "SDRAM_CONFIG_2__bitfield" {
        "Reserved__1" {
            loc = "31..31"
            type = "binary"
        }
        "Reserved__2" {
            loc = "30..30"
            type = "binary"
        }
        "Reserved__3" {
            loc = "29..28"
            type = "binary"
        }
        "reg_ebank_pos" {
            loc = "27..27"
            type = "binary"
            desc = "External bank position. Set to 0 to assign external bank address bits from lower OCP address, as shown in the tables for  OCP Address to DDR2/3/mDDR Address Mapping. Set to 1 to assign external bank address bits from higher OCP address bits, as shown in the tables for  OCP Address to DDR2/3/mDDR Address Mapping."
        }
        "Reserved__4" {
            loc = "26..6"
            type = "binary"
        }
        "Reserved__5" {
            loc = "5..4"
            type = "binary"
        }
        "Reserved__6" {
            loc = "3..3"
            type = "binary"
        }
        "Reserved__7" {
            loc = "2..0"
            type = "binary"
        }
    }
    "SDRAM_CONFIG__bitfield" {
        "reg_sdram_type" {
            loc = "31..29"
            type = "binary"
            desc = "SDRAM Type selection. Set to 0 for DDR1, set to 1 for LPDDR1, set to 2 for DDR2, set to 3 for DDR3. All other values are reserved."
        }
        "reg_ibank_pos" {
            loc = "28..27"
            type = "binary"
            desc = "Internal bank position. Set to 0 to assign internal bank address bits from lower OCP address bits, as shown in the tables for  OCP Address to DDR2/3/mDDR Address Mapping. Set to 1, 2, or 3 to assign internal bank address bits from higher OCP address, as shown in the tables for  OCP Address to DDR2/3/mDDR Address Mapping."
        }
        "reg_ddr_term" {
            loc = "26..24"
            type = "binary"
            desc = "DDR2 and DDR3 termination resistor value. Set to 0 to disable termination. For DDR2, set to 1 for 75 ohm, set to 2 for 150 ohm, and set to 3 for 50 ohm. For DDR3, set to 1 for RZQ/4, set to 2 for RZQ/2, set to 3 for RZQ/6, set to 4 for RZQ/12, and set to 5 for RZQ/8. All other values are reserved."
        }
        "reg_ddr2_ddqs" {
            loc = "23..23"
            type = "binary"
            desc = "DDR2 differential DQS enable. Set to 0 for single ended DQS. Set to 1 for differential DQS."
        }
        "reg_dyn_odt" {
            loc = "22..21"
            type = "binary"
            desc = "DDR3 Dynamic ODT. Set to 0 to turn off dynamic ODT. Set to 1 for RZQ/4 and set to 2 for RZQ/2. All other values are reserved."
        }
        "reg_ddr_disable_dll" {
            loc = "20..20"
            type = "binary"
            desc = "Disable DLL select. Set to 1 to disable DLL inside SDRAM."
        }
        "reg_sdram_drive" {
            loc = "19..18"
            type = "binary"
            desc = "SDRAM drive strength. For DDR1/DDR2, set to 0 for normal, and set to 1 for weak drive strength. For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. For LPDDR1, set to 0 for full, set to 1 for 1/2, set to 2 for 1/4, and set to 3 for 1/8 drive strength. All other values are reserved."
        }
        "reg_cwl" {
            loc = "17..16"
            type = "binary"
            desc = "DDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved."
        }
        "reg_narrow_mode" {
            loc = "15..14"
            type = "binary"
            desc = "SDRAM data bus width. Set to 0 for 32-bit and set to 1 for 16-bit. All other values are reserved."
        }
        "reg_cl" {
            loc = "13..10"
            type = "binary"
            desc = "CAS Latency. The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Value of 2, 3, 5, and 6 (CAS latency of 2, 3, 1.5, and 2.5) are supported for DDR1. Value of 2, 3, 4, and 5 (CAS latency of 2, 3, 4, and 5) are supported for DDR2. Value of 2, 4, 6, 8, 10, 12, and 14 (CAS latency of 5, 6, 7, 8, 9, 10, and 11) are supported for DDR3. Value of 2 and 3 (CAS latency of 2 and 3) are supported for LPDDR1. All other values are reserved."
        }
        "reg_rowsize" {
            loc = "9..7"
            type = "binary"
            desc = "Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, set to 1 for 10 row bits, set to 2 for 11 row bits, set to 3 for 12 row bits, set to 4 for 13 row bits, set to 5 for 14 row bits, set to 6 for 15 row bits, and set to 7 for 16 row bits. This field is only used when reg_ibank_pos field in SDRAM Config register is set to 1, 2, or 3, or reg_ebank_pos field in SDRAM Config_2 register is set to 1."
        }
        "reg_ibank" {
            loc = "6..4"
            type = "binary"
            desc = "Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, set to 1 for 2 banks, set to 2 for 4 banks, and set to 3 for 8 banks. All other values are reserved."
        }
        "reg_ebank" {
            loc = "3..3"
            type = "binary"
            desc = "External chip select setup. Defines whether SDRAM accesses will use 1 or 2 chip select lines. Set to 0 to use pad_cs_o_n[0] only. All other values reserved."
        }
        "reg_pagesize" {
            loc = "2..0"
            type = "binary"
            desc = "Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), set to 1 for 512-word page (9 column bits), set to 2 for 1024-word page (10 column bits), and set to 3 for 2048-word page (11 column bits). All other values are reserved."
        }
    }
    "SDRAM_REF_CTRL_SHDW__bitfield" {
        "Reserved" {
            loc = "31..16"
            type = "binary"
        }
        "reg_refresh_rate_shdw" {
            loc = "15..0"
            type = "binary"
            desc = "Shadow field for reg_refresh_rate. This field is loaded into reg_refresh_rate field in SDRAM Refresh Control register when SIdleAck is asserted. This register is not auto corrected when the value is invalid."
        }
    }
    "SDRAM_REF_CTRL__bitfield" {
        "reg_initref_dis" {
            loc = "31..31"
            type = "binary"
            desc = "Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions."
        }
        "Reserved__1" {
            loc = "30..30"
            type = "binary"
        }
        "reg_srt" {
            loc = "29..29"
            type = "binary"
            desc = "DDR3 Self Refresh temperature range. Set to 0 for normal operating temperature range and set to 1 for extended operating temperature range when the reg_asr field is set to 0. This bit must be set to 0 if the reg_asr field is set to 1. A write to this field will cause the EMIF to start the SDRAM initialization sequence."
        }
        "reg_asr" {
            loc = "28..28"
            type = "binary"
            desc = "DDR3 Auto Self Refresh enable. Set to 1 for auto Self Refresh enable. Set to 0 for manual Self Refresh reference indicated by the reg_srt field. A write to this field will cause the EMIF to start the SDRAM initialization sequence."
        }
        "Reserved__2" {
            loc = "27..27"
            type = "binary"
        }
        "reg_pasr" {
            loc = "26..24"
            type = "binary"
            desc = "Partial Array Self Refresh. These bits get loaded into the Extended Mode Register of an LPDDR1 or DDR3 during initialization. For LPDDR1, set to 0 for full array, set to 1 for 1/2 array, set to 2 for 1/4 array, set to 5 for 1/8 array, and set to 6 for 1/16 array to be refreshed. For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2 or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4 array to be refreshed. All other values are reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence."
        }
        "Reserved__3" {
            loc = "23..16"
            type = "binary"
        }
        "reg_refresh_rate" {
            loc = "15..0"
            type = "binary"
            desc = "Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = EMIF rate / reg_refresh_rate where EMIF rate is equal to m_clk rate. If reg_refresh_rate andlt (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20 then it will be loaded with (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20. This is done to avoid lock-up situations when illegal values are programmed."
        }
    }
    "SDRAM_TIM_1_SHDW__bitfield" {
        "Reserved" {
            loc = "31..29"
            type = "binary"
        }
        "reg_t_rp_shdw" {
            loc = "28..25"
            type = "binary"
            desc = "Shadow field for reg_t_rp. This field is loaded into reg_t_rp field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
        "reg_t_rcd_shdw" {
            loc = "24..21"
            type = "binary"
            desc = "Shadow field for reg_t_rcd. This field is loaded into reg_t_rcd field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
        "reg_t_wr_shdw" {
            loc = "20..17"
            type = "binary"
            desc = "Shadow field for reg_t_wr. This field is loaded into reg_t_wr field in SDRAM Timing 1 register when SIdleAck is asserted. initialization sequence will be started when the value of this field is changed from the previous value and the EMIF is in DDR2 mode."
        }
        "reg_t_ras_shdw" {
            loc = "16..12"
            type = "binary"
            desc = "Shadow field for reg_t_ras. This field is loaded into reg_t_ras field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
        "reg_t_rc_shdw" {
            loc = "11..6"
            type = "binary"
            desc = "Shadow field for reg_t_rc. This field is loaded into reg_t_rc field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
        "reg_t_rrd_shdw" {
            loc = "5..3"
            type = "binary"
            desc = "Shadow field for reg_t_rrd. This field is loaded into reg_t_rrd field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
        "reg_t_wtr_shdw" {
            loc = "2..0"
            type = "binary"
            desc = "Shadow field for reg_t_wtr. This field is loaded into reg_t_wtr field in SDRAM Timing 1 register when SIdleAck is asserted."
        }
    }
    "SDRAM_TIM_1__bitfield" {
        "Reserved" {
            loc = "31..29"
            type = "binary"
        }
        "reg_t_rp" {
            loc = "28..25"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Precharge to Activate or Refresh, minus one."
        }
        "reg_t_rcd" {
            loc = "24..21"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Activate to Read or Write, minus one."
        }
        "reg_t_wr" {
            loc = "20..17"
            type = "binary"
            desc = "Minimum number of m_clk cycles from last Write transfer to Pre-charge, minus one. The SDRAM initialization sequence will be started when the value of this field is changed from the previous value and the EMIF is in DDR2 mode."
        }
        "reg_t_ras" {
            loc = "16..12"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Activate to Pre-charge, minus one. reg_t_ras >= reg_t_rcd."
        }
        "reg_t_rc" {
            loc = "11..6"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Activate to Activate, minus one."
        }
        "reg_t_rrd" {
            loc = "5..3"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Activate to Activate for a different bank, minus one. For an 8-bank DDR2, this field must be equal to ((((4*tRRD)+(2*tCK))/(4*tCK))-1)."
        }
        "reg_t_wtr" {
            loc = "2..0"
            type = "binary"
            desc = "Minimum number of m_clk cycles from last Write to Read, minus one."
        }
    }
    "SDRAM_TIM_2_SHDW__bitfield" {
        "Reserved" {
            loc = "31..31"
            type = "binary"
        }
        "reg_t_xp_shdw" {
            loc = "30..28"
            type = "binary"
            desc = "Shadow field for reg_t_xp. This field is loaded into reg_t_xp field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
        "reg_t_odt_shdw" {
            loc = "27..25"
            type = "binary"
            desc = "Shadow field for reg_t_odt. This field is loaded into reg_t_odt field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
        "reg_t_xsnr_shdw" {
            loc = "24..16"
            type = "binary"
            desc = "Shadow field for reg_t_xsnr. This field is loaded into reg_t_xsnr field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
        "reg_t_xsrd_shdw" {
            loc = "15..6"
            type = "binary"
            desc = "Shadow field for reg_t_xsrd. This field is loaded into reg_t_xsrd field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
        "reg_t_rtp_shdw" {
            loc = "5..3"
            type = "binary"
            desc = "Shadow field for reg_t_rtp. This field is loaded into reg_t_rtp field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
        "reg_t_cke_shdw" {
            loc = "2..0"
            type = "binary"
            desc = "Shadow field for reg_t_cke. This field is loaded into reg_t_cke field in SDRAM Timing 2 register when SIdleAck is asserted."
        }
    }
    "SDRAM_TIM_2__bitfield" {
        "Reserved" {
            loc = "31..31"
            type = "binary"
        }
        "reg_t_xp" {
            loc = "30..28"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Powerdown exit to any command other than a Read command, minus one. For DDR2 and LPDDR1, this field must satisfy greater of tXP or tCKE."
        }
        "reg_t_odt" {
            loc = "27..25"
            type = "binary"
            desc = "Minimum number of m_clk cycles from ODT enable to write data driven for DDR2 and DDR3. reg_t_odt must be equal to tAOND."
        }
        "reg_t_xsnr" {
            loc = "24..16"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Self-Refresh exit to any command other than a Read command, minus one."
        }
        "reg_t_xsrd" {
            loc = "15..6"
            type = "binary"
            desc = "Minimum number of m_clk cycles from Self-Refresh exit to a Read command, minus one."
        }
        "reg_t_rtp" {
            loc = "5..3"
            type = "binary"
            desc = "Minimum number of m_clk cycles from the last Read command to a Pre-charge command for DDR2, minus one."
        }
        "reg_t_cke" {
            loc = "2..0"
            type = "binary"
            desc = "Minimum number of m_clk cycles between pad_cke_o changes, minus one."
        }
    }
    "SDRAM_TIM_3__bitfield" {
        "reg_t_pdll_ul" {
            loc = "31..28"
            type = "binary"
            desc = "Minimum number of DDR clock cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks."
        }
        "Reserved__1" {
            loc = "27..24"
            type = "binary"
        }
        "Reserved__2" {
            loc = "23..21"
            type = "binary"
        }
        "reg_zq_zqcs" {
            loc = "20..15"
            type = "binary"
            desc = "Number of DDR clock clock cycles for a ZQCS command, minus one."
        }
        "Reserved__3" {
            loc = "14..13"
            type = "binary"
        }
        "reg_t_rfc" {
            loc = "12..4"
            type = "binary"
            desc = "Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one."
        }
        "reg_t_ras_max" {
            loc = "3..0"
            type = "binary"
            desc = "Maximum number of reg_refresh_rate intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. This field is only applicable for mDDR. This field must be programmed to 0xF for other SDRAM types."
        }
    }
    "SECONDS_REG__bitfield" {
        "Reserved" {
            loc = "31..7"
            type = "binary"
        }
        "SEC1" {
            loc = "6..4"
            type = "binary"
            desc = "2nd digit of seconds, Range is 0 to 5"
        }
        "SEC0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of seconds, Range is 0 to 9"
        }
    }
    "STATUS__bitfield" {
        "reg_be" {
            loc = "31..31"
            type = "binary"
            desc = "Big Endian. Reflects the value on the config_big_endian port that defines whether the EMIF is in big or little endian mode.  0 = Little endian. 1 = Big endian."
        }
        "reg_dual_clk_mode" {
            loc = "30..30"
            type = "binary"
            desc = "Dual Clock mode. Reflects the value on the config_dual_clk_mode port that defines whether the ocp_clk and m_clk are asynchronous. 0 = ocp_clk = m_clk. 1 = Asynchronous ocp_clk and m_clk."
        }
        "reg_fast_init" {
            loc = "29..29"
            type = "binary"
            desc = "Fast Init. Reflects the value on the config_fast_init port that defines whether the EMIF fast initialization mode has been enabled. 0 = Fast init disabled. 1 = Fast init enabled."
        }
        "Reserved__1" {
            loc = "28..3"
            type = "binary"
        }
        "reg_phy_dll_ready" {
            loc = "2..2"
            type = "binary"
            desc = "DDR PHY Ready. Reflects the value on the phy_ready port (active high) that defines whether the DDR PHY is ready for normal operation."
        }
        "Reserved__2" {
            loc = "1..0"
            type = "binary"
        }
    }
    "Spinlock_LOCK_REG___bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "TAKEN" {
            loc = "0..0"
            type = "Spinlock_LOCK_REG_TAKEN__enum"
        }
    }
    "Spinlock_REV__bitfield" {
        "REV" {
            loc = "31..0"
            type = "binary"
            desc = "IP Revision Code."
        }
    }
    "Spinlock_SYSCONFIG__bitfield" {
        "Reserved__1" {
            loc = "31..9"
            type = "binary"
        }
        "CLOCKACTIVITY" {
            loc = "8..8"
            type = "Spinlock_SYSCONFIG_CLOCKACTIVITY__enum"
            desc = "Indicates whether the module requires the OCP when in IDLE mode."
        }
        "Reserved__2" {
            loc = "7..5"
            type = "binary"
        }
        "SIDLEMODE" {
            loc = "4..3"
            type = "Spinlock_SYSCONFIG_SIDLEMODE__enum"
            desc = "Control of the slave interface power management IDLE request acknowledgement."
        }
        "ENWAKEUP" {
            loc = "2..2"
            type = "Spinlock_SYSCONFIG_ENWAKEUP__enum"
            desc = "Asynchronous wakeup gereration."
        }
        "SOFTRESET" {
            loc = "1..1"
            type = "Spinlock_SYSCONFIG_SOFTRESET__enum"
            desc = "Module software reset."
        }
        "AUTOGATING" {
            loc = "0..0"
            type = "Spinlock_SYSCONFIG_AUTOGATING__enum"
            desc = "Internal OCP clock gating strategy."
        }
    }
    "Spinlock_SYSTATUS__bitfield" {
        "NUMLOCKS" {
            loc = "31..24"
            type = "Spinlock_SYSTATUS_NUMLOCKS__enum"
        }
        "Reserved__1" {
            loc = "23..16"
            type = "binary"
        }
        "IU7" {
            loc = "15..15"
            type = "binary"
        }
        "IU6" {
            loc = "14..14"
            type = "binary"
        }
        "IU5" {
            loc = "13..13"
            type = "binary"
        }
        "IU4" {
            loc = "12..12"
            type = "binary"
        }
        "IU3" {
            loc = "11..11"
            type = "binary"
        }
        "IU2" {
            loc = "10..10"
            type = "binary"
        }
        "IU1" {
            loc = "9..9"
            type = "binary"
            desc = "In-Use flag 1, covering lock registers 32 - 63.  Reads as one only if one or more lock registers in this range are TAKEN. If no lock registers are implemented in this range, then this flag always reads as 0."
        }
        "IU0" {
            loc = "8..8"
            type = "binary"
            desc = "In-Use flag 0, covering lock registers 0 - 31.  Reads as one only if one or more lock registers in this range are TAKEN."
        }
        "Reserved__2" {
            loc = "7..1"
            type = "binary"
        }
        "RESETDONE" {
            loc = "0..0"
            type = "binary"
            desc = "0: Reset in progress. 1: Reset is completed."
        }
    }
    "TDFDQ__bitfield" {
        "TD_DESC_QMGR" {
            loc = "13..12"
            type = "binary"
            desc = "This field controls which of the 4 Queue  Managers the DMA will access in order to  allocate a channel teardown descriptor from  the teardown descriptor queue."
        }
        "TD_DESC_QNUM" {
            loc = "11..0"
            type = "binary"
            desc = "This field controls which of the 2K queues in  the indicated queue manager should be read in  order to allocate channel teardown descriptors. CPPI DMA Teardown Free Descriptor Queue Control Register"
        }
    }
    "TXGCR__bitfield" {
        "TX_ENABLE" {
            loc = "31..31"
            type = "binary"
            desc = "This field enables or disables the channel 0 = channel is disabled 1 = channel is enabled This field will be cleared after a channel teardown is complete."
        }
        "TX_TEARDOWN" {
            loc = "30..30"
            type = "binary"
            desc = "Setting this bit will request the channel to be torn down.  This field  will remain set after a channel teardown is complete."
        }
        "TX_DEFAULT_QMGR" {
            loc = "13..12"
            type = "binary"
            desc = "This field controls the default queue manager number that will be  used to queue teardown descriptors back to the host."
        }
        "TX_DEFAULT_QNUM" {
            loc = "11..0"
            type = "binary"
            desc = "This field controls the default queue number within the selected  queue manager onto which teardown descriptors will be queued  back to the host. Table 98 -Tx Channel N Global Configuration Registers"
        }
    }
    "TX_CP__bitfield" {
        "TX_CP" {
            loc = "31..0"
            type = "binary"
            desc = "Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted."
        }
    }
    "TX_HDP__bitfield" {
        "TX_HDP" {
            loc = "31..0"
            type = "binary"
            desc = "TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset."
        }
    }
    "USB0AUTOREQ__bitfield" {
        "RX15_AUTOREQ" {
            loc = "29..28"
            type = "binary"
            desc = "RX endpoint 14 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX14_AUTOREQ" {
            loc = "27..26"
            type = "binary"
            desc = "RX endpoint 13 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX13_AUTOREQ" {
            loc = "25..24"
            type = "binary"
            desc = "RX endpoint 12 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX12_AUTOREQ" {
            loc = "23..22"
            type = "binary"
            desc = "RX endpoint 11 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX11_AUTOREQ" {
            loc = "21..20"
            type = "binary"
            desc = "RX endpoint 10 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX10_AUTOREQ" {
            loc = "19..18"
            type = "binary"
            desc = "RX endpoint 9 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX9_AUTOREQ" {
            loc = "17..16"
            type = "binary"
            desc = "RX endpoint 8 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX8_AUTOREQ" {
            loc = "15..14"
            type = "binary"
            desc = "RX endpoint 7 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX7_AUTOREQ" {
            loc = "13..12"
            type = "binary"
            desc = "RX endpoint 6 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX6_AUTOREQ" {
            loc = "11..10"
            type = "binary"
            desc = "RX endpoint 5 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX5_AUTOREQ" {
            loc = "9..8"
            type = "binary"
            desc = "RX endpoint 4 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX4_AUTOREQ" {
            loc = "7..6"
            type = "binary"
            desc = "RX endpoint 3 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX3_AUTOREQ" {
            loc = "5..4"
            type = "binary"
            desc = "RX endpoint 2 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX2_AUTOREQ" {
            loc = "3..2"
            type = "binary"
            desc = "RX endpoint 1 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX1_AUTOREQ" {
            loc = "1..0"
            type = "binary"
            desc = "RX endpoint 0 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always USB0 Auto Req Registers"
        }
    }
    "USB0CTRL__bitfield" {
        "DIS_DEB" {
            loc = "31..31"
            type = "binary"
            desc = "Disable the VBUS debouncer circuit fix"
        }
        "DIS_SRP" {
            loc = "30..30"
            type = "binary"
            desc = "Disable the OTG Session Request Protocol (SRP) AVALID  circuit fix.  When enabled (=0) this allows additional time for  the VBUS signal to be measured against the VBUS  thresholds. The time is specified in the USB0 SRP Fix Time  Register."
        }
        "SOFT_RESET_ISOLATION" {
            loc = "5..5"
            type = "binary"
            desc = "Soft reset isolation.  When high this bit forces all USB0  signals that connect to the USBSS to known values during a  soft reset via bit 0 of this register.  This bit should be set  high prior to setting bit 0 and cleared after bit 0 is cleared."
        }
        "RNDIS" {
            loc = "4..4"
            type = "binary"
            desc = "Global RNDIS mode enable for all endpoints."
        }
        "UINT" {
            loc = "3..3"
            type = "binary"
            desc = "USB interrupt enable 1 = Legacy 0 = Current (recommended setting); If uint is set high, then the mentor controller generic interrupt for USB[9] will be generated (if enabled). This requires S/W to read the mentor controller's registers to determine which interrupt from USB[0] to USB[7] that occurred.; If uint is set low, then the usb20otg_f module will automatically read the mentor controller's registers and set the appropriate interrupt from USB[0] to USB[7] (if enabled). The generic interrupt for USB[9] will not be generated."
        }
        "CLKFACK" {
            loc = "1..1"
            type = "binary"
            desc = "Clock stop fast ack enable."
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset of USB0. Write 0 = no action Write 1 = Initiate software reset Read 0 = Reset done, no action Read 1 = Reset ongoing; Both the soft_reset and soft_reset_isolation bits should be asserted simultaneously. This will cause the following sequence of actions to occur over multiple cycles:;; - All USB0 output signals will go to a known constant value via multiplexers. This removes the possibility of timing errors due to the asynchronous resets.; - All USB0 registers will be reset.; - The USB0 resets will be de-asserted.; - The reset isolation multiplexer inputs will be de-selected.; - Both the soft_reset and soft_reset_isolation bits will be automatically cleared.;; Setting only the soft_reset_isolation bit will cause all USB0 output signals to go to a known constant value via multiplexers. This will prevent future access to USB0. To clear this condition the USBSS must be reset via a hard or soft reset."
        }
    }
    "USB0GENRNDISEP10__bitfield" {
        "EP10_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP11__bitfield" {
        "EP11_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP12__bitfield" {
        "EP12_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP13__bitfield" {
        "EP13_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP14__bitfield" {
        "EP14_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP15__bitfield" {
        "EP15_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP1__bitfield" {
        "EP1_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP2__bitfield" {
        "EP2_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP3__bitfield" {
        "EP3_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP4__bitfield" {
        "EP4_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP5__bitfield" {
        "EP5_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP6__bitfield" {
        "EP6_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP7__bitfield" {
        "EP7_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP8__bitfield" {
        "EP8_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0GENRNDISEP9__bitfield" {
        "EP9_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB0 Generic RNDIS EP N Size Register"
        }
    }
    "USB0IRQENABLECLR0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 0 USB0 IRQ_ENABLE_CLR_0 Register"
        }
    }
    "USB0IRQENABLECLR1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 1"
        }
        "TX_FIFO_0" {
            loc = "16..16"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 0"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for Suspend signaling detected USB0 IRQ_ENABLE_CLR_1 Register"
        }
    }
    "USB0IRQENABLESET0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 0 USB0 IRQ_ENABLE_SET_0 Register"
        }
    }
    "USB0IRQENABLESET1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 1"
        }
        "TX_FIFO_0" {
            loc = "16..16"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 0"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for Suspend signaling detected USB0 IRQ_ENABLE_SET_1 Register"
        }
    }
    "USB0IRQMSTAT__bitfield" {
        "BANK1" {
            loc = "1..1"
            type = "binary"
            desc = "0: No events pending from IRQ_STATUS_1 1: At least one event is pending from IRQ_STATUS_1"
        }
        "BANK0" {
            loc = "0..0"
            type = "binary"
            desc = "0: No events pending from IRQ_STATUS_0 1: At least one event is pending from IRQ_STATUS_0 USB0 IRQ_MERGED_STATUS Register"
        }
    }
    "USB0IRQSTAT0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt status for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt status for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt status for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt status for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for TX endpoint 0 USB0 IRQ_STATUS_0 Register"
        }
    }
    "USB0IRQSTAT1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 1"
        }
        "TX_FIFO_0" {
            loc = "16..16"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 0"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for Suspend signaling detected USB0 IRQ_STATUS_1 Register"
        }
    }
    "USB0IRQSTATRAW0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt status for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt status for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt status for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt status for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for TX endpoint 0 USB0 IRQ_STATUS_RAW_0 Register"
        }
    }
    "USB0IRQSTATRAW1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 1"
        }
        "TX_FIFO_0" {
            loc = "16..16"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 0"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for Suspend signaling detected USB0 IRQ_STATUS_RAW_1 Register"
        }
    }
    "USB0MODE__bitfield" {
        "IDDIG" {
            loc = "8..8"
            type = "binary"
            desc = "MGC input value for iddig 0=A type 1=B type"
        }
        "PHY_TEST" {
            loc = "1..1"
            type = "binary"
            desc = "PHY test 0 = Normal mode 1 = PHY test mode"
        }
        "LOOPBACK" {
            loc = "0..0"
            type = "binary"
            desc = "Loopback test mode 0 = Normal mode 1 = Loopback test mode USB0 Mode Register"
        }
    }
    "USB0REV__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between legacy interface scheme and current. 0 = Legacy 1 = Current"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Function indicates a software compatible module family."
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision. Will vary depending on release."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision."
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Custom revision"
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision. USB0 Revision Register"
        }
    }
    "USB0RXMODE__bitfield" {
        "RX15_MODE" {
            loc = "29..28"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 14 01: RNDIS Mode on RX endpoint 14 10: CDC Mode on RX endpoint 14 11: Generic RNDIS or Infinite Mode on RX endpoint 14"
        }
        "RX14_MODE" {
            loc = "27..26"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 13 01: RNDIS Mode on RX endpoint 13 10: CDC Mode on RX endpoint 13 11: Generic RNDIS or Infinite Mode on RX endpoint 13"
        }
        "RX13_MODE" {
            loc = "25..24"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 12 01: RNDIS Mode on RX endpoint 12 10: CDC Mode on RX endpoint 12 11: Generic RNDIS or Infinite Mode on RX endpoint 12"
        }
        "RX12_MODE" {
            loc = "23..22"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 11 01: RNDIS Mode on RX endpoint 11 10: CDC Mode on RX endpoint 11 11: Generic RNDIS or Infinite Mode on RX endpoint 11"
        }
        "RX11_MODE" {
            loc = "21..20"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 10 01: RNDIS Mode on RX endpoint 10 10: CDC Mode on RX endpoint 10 11: Generic RNDIS or Infinite Mode on RX endpoint 10"
        }
        "RX10_MODE" {
            loc = "19..18"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 9 01: RNDIS Mode on RX endpoint 9 10: CDC Mode on RX endpoint 9 11: Generic RNDIS or Infinite Mode on RX endpoint 9"
        }
        "RX9_MODE" {
            loc = "17..16"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 8 01: RNDIS Mode on RX endpoint 8 10: CDC Mode on RX endpoint 8 11: Generic RNDIS Mode on RX endpoint 8"
        }
        "RX8_MODE" {
            loc = "15..14"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 7 01: RNDIS Mode on RX endpoint 7 10: CDC Mode on RX endpoint 7 11: Generic RNDIS or Infinite Mode on RX endpoint 7"
        }
        "RX7_MODE" {
            loc = "13..12"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 6 01: RNDIS Mode on RX endpoint 6 10: CDC Mode on RX endpoint 6 11: Generic RNDIS or Infinite Mode on RX endpoint 6"
        }
        "RX6_MODE" {
            loc = "11..10"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 5 01: RNDIS Mode on RX endpoint 5 10: CDC Mode on RX endpoint 5 11: Generic RNDIS or Infinite Mode on RX endpoint 5"
        }
        "RX5_MODE" {
            loc = "9..8"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 4 01: RNDIS Mode on RX endpoint 4 10: CDC Mode on RX endpoint 4 11: Generic RNDIS or Infinite Mode on RX endpoint 4"
        }
        "RX4_MODE" {
            loc = "7..6"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 3 01: RNDIS Mode on RX endpoint 3 10: CDC Mode on RX endpoint 3 11: Generic RNDIS or Infinite Mode on RX endpoint 3"
        }
        "RX3_MODE" {
            loc = "5..4"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 2 01: RNDIS Mode on RX endpoint 2 10: CDC Mode on RX endpoint 2 11: Generic RNDIS or Infinite Mode on RX endpoint 2"
        }
        "RX2_MODE" {
            loc = "3..2"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 1 01: RNDIS Mode on RX endpoint 1 10: CDC Mode on RX endpoint 1 11: Generic RNDIS or Infinite Mode on RX endpoint 1"
        }
        "RX1_MODE" {
            loc = "1..0"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 0 01: RNDIS Mode on RX endpoint 0 10: CDC Mode on RX endpoint 0 11: Generic RNDIS or Infinite Mode on RX endpoint 0 Each RX endpoint can be configured into 1 of 5 packet termination modes. Transparent mode (b00) * Supports USB endpoint sizes of o FS :  8, 16, 32, 64, and 1023 o HS : 64, 128, 512, and 1024 * Mentor Controller's RXMAXP/TXMAXP must be a valid USB endpoint size. * With autoreq=3 XDMA will always generate a ReqPkt's at the end of the packet. * With autoreq=1 XDMA will never generatate a ReqPkt at the end of the packet. * Each USB packet is equivalent to a single CPPI DMA packet. * Each received CPPI packet will be no larger than the USB max packet size (1023 bytes  for FS, 1024 bytes for HS) and will be both a SOP and EOP. * Transmitted CPPI packets can be no larger than the USB max packet size. * Primarily used for interrupt or isochronous endpoints, as CPU will receive an interrupt for  every USB packet (if enabled). RNDIS mode (b01) * Supports USB endpoint sizes of o FS : 64 o HS : 64, 128, 512, and 1024 * Mentor controller's RXMAXP/TXMAXP must be an integer multiple of the USB endpoint  size. * With autoreq=3 XDMA will always generate a ReqPkt's at the end of the packet. * With autoreq=1 XDMA will continue the generation of ReqPkt's to the Mentor controller  until a short packet is received. * Supports transmission of CPPI packets larger than the USB max packet size. * The end of a CPPI packet is defined by a USB short packet (a USB packet less than the  USB max packet size). * In the case where the CPPI packet is an exact multiple of the USB max packet size, a  zero length terminating packet is used (XDMA recognizes this terminating packet on  reception, and generates it on transmission). * Designed for use in an RNDIS compliant networking type of USB device and bulk  endpoints Linux CDC mode (b10) * Same as RNDIS mode, except terminating packet has 1-byte of 0 data. * Designed for use with a Linux OS and USB driver stack and bulk endpoints. Generic RNDIS mode (b11 and Generic RNDIS EP N Size register is greater than 0) * Same as RNDIS mode, except the end of a CPPI packet is determined by a USB short  packet or when the value in the GENERIC RNDIS EPn SIZE Register is reached (Rx  mode only)(i.e. Tx mode does not use this register). The CPU configures this register  with a value that is a multiple of the corresponding endpoint size. * No terminating packet is used. * Designed for general bulk endpoint use where specific packet terminations are not  required. * Transmit mode transfers only support FS or HS EP sizes through the XDMA and Mentor  controller.  The CPPI DMA size can be of any legal size as defined by the CPPI 4.1  specification. Infinite mode (b11 and Generic RNDIS EP N Size register equal to 0) * Same as RNDIS mode, except the end of a CPPI packet is determined by a USB short  packet or when the CPPI DMA closes up the packet after a defined number of buffers  have been filled. This is defined in Rx Channel N Global Configuration Register bits  28:26 rx_max_buffer_cnt. * The CPPI DMA will ignore SOPs generated by the XDMA. * The XDMA packet is assumed to be infinite. * The XDMA starts the packet with a SOP (ignored by the CPPI DMA). * The XDMA ends the packet when a short packet occurs. * Short packets are defined when RXMAXP (0x14) is not equal to RXCOUNT (0x18).  RXMAXP and RXCOUNT are both registers within the Mentor controller. * The XDMA will continue to request RX packets from the Mentor controller until a short  packet is received. * When the CPPI is configured for chaining mode, the Buffer Descriptor sizes must be  integer multiples of the RXMAXP size. * Transmit mode is not supported. * USB0 or USB1 Auto Req register should be set to AUTO REQ ALWAYS."
        }
    }
    "USB0SRPFIXTIME__bitfield" {
        "SRPFIXTIME" {
            loc = "31..0"
            type = "binary"
            desc = "SRP Fix maximum time in 60 MHz cycles. Default is  700 ms. USB0 SRP Fix Time Register"
        }
    }
    "USB0STAT__bitfield" {
        "DRVVBUS" {
            loc = "0..0"
            type = "binary"
            desc = "Current DRVVBUS value USB0 Status Register"
        }
    }
    "USB0TXMODE__bitfield" {
        "TX15_MODE" {
            loc = "29..28"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 14 01: RNDIS Mode on TX endpoint 14 10: CDC Mode on TX endpoint 14 11: Generic RNDIS Mode on TX endpoint 14"
        }
        "TX14_MODE" {
            loc = "27..26"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 13 01: RNDIS Mode on TX endpoint 13 10: CDC Mode on TX endpoint 13 11: Generic RNDIS Mode on TX endpoint 13"
        }
        "TX13_MODE" {
            loc = "25..24"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 12 01: RNDIS Mode on TX endpoint 12 10: CDC Mode on TX endpoint 12 11: Generic RNDIS Mode on TX endpoint 12"
        }
        "TX12_MODE" {
            loc = "23..22"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 11 01: RNDIS Mode on TX endpoint 11 10: CDC Mode on TX endpoint 11 11: Generic RNDIS Mode on TX endpoint 11"
        }
        "TX11_MODE" {
            loc = "21..20"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 10 01: RNDIS Mode on TX endpoint 10 10: CDC Mode on TX endpoint 10 11: Generic RNDIS Mode on TX endpoint 10"
        }
        "TX10_MODE" {
            loc = "19..18"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 9 01: RNDIS Mode on TX endpoint 9 10: CDC Mode on TX endpoint 9 11: Generic RNDIS Mode on TX endpoint 9"
        }
        "TX9_MODE" {
            loc = "17..16"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 8 01: RNDIS Mode on TX endpoint 8 10: CDC Mode on TX endpoint 8 11: Generic RNDIS Mode on TX endpoint 8"
        }
        "TX8_MODE" {
            loc = "15..14"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 7 01: RNDIS Mode on TX endpoint 7 10: CDC Mode on TX endpoint 7 11: Generic RNDIS Mode on TX endpoint 7"
        }
        "TX7_MODE" {
            loc = "13..12"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 6 01: RNDIS Mode on TX endpoint 6 10: CDC Mode on TX endpoint 6 11: Generic RNDIS Mode on TX endpoint 6"
        }
        "TX6_MODE" {
            loc = "11..10"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 5 01: RNDIS Mode on TX endpoint 5 10: CDC Mode on TX endpoint 5 11: Generic RNDIS Mode on TX endpoint 5"
        }
        "TX5_MODE" {
            loc = "9..8"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 4 01: RNDIS Mode on TX endpoint 4 10: CDC Mode on TX endpoint 4 11: Generic RNDIS Mode on TX endpoint 4"
        }
        "TX4_MODE" {
            loc = "7..6"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 3 01: RNDIS Mode on TX endpoint 3 10: CDC Mode on TX endpoint 3 11: Generic RNDIS Mode on TX endpoint 3"
        }
        "TX3_MODE" {
            loc = "5..4"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 2 01: RNDIS Mode on TX endpoint 2 10: CDC Mode on TX endpoint 2 11: Generic RNDIS Mode on TX endpoint 2"
        }
        "TX2_MODE" {
            loc = "3..2"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 1 01: RNDIS Mode on TX endpoint 1 10: CDC Mode on TX endpoint 1 11: Generic RNDIS Mode on TX endpoint 1"
        }
        "TX1_MODE" {
            loc = "1..0"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 0 01: RNDIS Mode on TX endpoint 0 10: CDC Mode on TX endpoint 0 11: Generic RNDIS Mode on TX endpoint 0 USB0 Tx Mode Registers"
        }
    }
    "USB0UTMI__bitfield" {
        "TXBITSTUFFEN" {
            loc = "23..23"
            type = "binary"
            desc = "PHY UTMI input for signal txbitstuffen"
        }
        "TXBITSTUFFENH" {
            loc = "22..22"
            type = "binary"
            desc = "PHY UTMI input for signal txbitstuffenh"
        }
        "OTGDISABLE" {
            loc = "21..21"
            type = "binary"
            desc = "PHY UTMI input for signal otgdisable"
        }
        "VBUSVLDEXTSEL" {
            loc = "20..20"
            type = "binary"
            desc = "PHY UTMI input for signal vbusvldextsel"
        }
        "VBUSVLDEXT" {
            loc = "19..19"
            type = "binary"
            desc = "PHY UTMI input for signal vbusvldext"
        }
        "TXENABLEN" {
            loc = "18..18"
            type = "binary"
            desc = "PHY UTMI input for signal txenablen"
        }
        "FSXCVROWNER" {
            loc = "17..17"
            type = "binary"
            desc = "PHY UTMI input for signal fsxcvrowner"
        }
        "TXVALIDH" {
            loc = "16..16"
            type = "binary"
            desc = "PHY UTMI input for signal txvalidh"
        }
        "DATAINH" {
            loc = "15..8"
            type = "binary"
            desc = "PHY UTMI input for signal datainh"
        }
        "WORDINTERFACE" {
            loc = "2..2"
            type = "binary"
            desc = "PHY UTMI input for signal wordinterface"
        }
        "FSDATAEXT" {
            loc = "1..1"
            type = "binary"
            desc = "PHY UTMI input for signal fsdataext"
        }
        "FSSE0EXT" {
            loc = "0..0"
            type = "binary"
            desc = "PHY UTMI input for signal fsse0ext USB0 PHY UTMI Register"
        }
    }
    "USB1AUTOREQ__bitfield" {
        "RX15_AUTOREQ" {
            loc = "29..28"
            type = "binary"
            desc = "RX endpoint 14 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX14_AUTOREQ" {
            loc = "27..26"
            type = "binary"
            desc = "RX endpoint 13 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX13_AUTOREQ" {
            loc = "25..24"
            type = "binary"
            desc = "RX endpoint 12 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX12_AUTOREQ" {
            loc = "23..22"
            type = "binary"
            desc = "RX endpoint 11 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX11_AUTOREQ" {
            loc = "21..20"
            type = "binary"
            desc = "RX endpoint 10 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX10_AUTOREQ" {
            loc = "19..18"
            type = "binary"
            desc = "RX endpoint 9 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX9_AUTOREQ" {
            loc = "17..16"
            type = "binary"
            desc = "RX endpoint 8 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX8_AUTOREQ" {
            loc = "15..14"
            type = "binary"
            desc = "RX endpoint 7 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX7_AUTOREQ" {
            loc = "13..12"
            type = "binary"
            desc = "RX endpoint 6 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX6_AUTOREQ" {
            loc = "11..10"
            type = "binary"
            desc = "RX endpoint 5 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX5_AUTOREQ" {
            loc = "9..8"
            type = "binary"
            desc = "RX endpoint 4 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX4_AUTOREQ" {
            loc = "7..6"
            type = "binary"
            desc = "RX endpoint 3 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX3_AUTOREQ" {
            loc = "5..4"
            type = "binary"
            desc = "RX endpoint 2 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX2_AUTOREQ" {
            loc = "3..2"
            type = "binary"
            desc = "RX endpoint 1 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always"
        }
        "RX1_AUTOREQ" {
            loc = "1..0"
            type = "binary"
            desc = "RX endpoint 0 Auto Req enable 00 = no auto req 01 = auto req on all but EOP 10 = reserved 11 = auto req always USB1 Auto Req Registers"
        }
    }
    "USB1CTRL__bitfield" {
        "DIS_DEB" {
            loc = "31..31"
            type = "binary"
            desc = "Disable the VBUS debouncer circuit fix"
        }
        "DIS_SRP" {
            loc = "30..30"
            type = "binary"
            desc = "Disable the OTG Session Request Protocol (SRP) AVALID  circuit fix.  When enabled (=0) this allows additional time for  the VBUS signal to be measured against the VBUS  thresholds. The time is specified in the USB0 SRP Fix Time  Register."
        }
        "SOFT_RESET_ISOLATION" {
            loc = "5..5"
            type = "binary"
            desc = "Soft reset isolation.  When high this bit forces all USB1  signals that connect to the USBSS to known values during a  soft reset via bit 0 of this register.  This bit should be set  high prior to setting bit 0 and cleared after bit 0 is cleared."
        }
        "RNDIS" {
            loc = "4..4"
            type = "binary"
            desc = "Global RNDIS mode enable for all endpoints."
        }
        "UINT" {
            loc = "3..3"
            type = "binary"
            desc = "USB interrupt enable 1 = Legacy 0 = Current (recommended setting); If uint is set high, then the mentor controller generic interrupt for USB[9] will be generated (if enabled). This requires S/W to read the mentor controller's registers to determine which interrupt from USB[0] to USB[7] that occurred.; If uint is set low, then the usb20otg_f module will automatically read the mentor controller's registers and set the appropriate interrupt from USB[0] to USB[7] (if enabled). The generic interrupt for USB[9] will not be generated."
        }
        "CLKFACK" {
            loc = "1..1"
            type = "binary"
            desc = "Clock stop fast ack enable."
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset of USB1. Write 0 = no action Write 1 = Initiate software reset Read 0 = Reset done, no action Read 1 = Reset ongoing; Both the soft_reset and soft_reset_isolation bits should be asserted simultaneously. This will cause the following sequence of actions to occur over multiple cycles:;; - All USB0 output signals will go to a known constant value via multiplexers. This removes the possibility of timing errors due to the asynchronous resets.; - All USB0 registers will be reset.; - The USB0 resets will be de-asserted.; - The reset isolation multiplexer inputs will be de-selected.; - Both the soft_reset and soft_reset_isolation bits will be automatically cleared.;; Setting only the soft_reset_isolation bit will cause all USB0 output signals to go to a known constant value via multiplexers. This will prevent future access to USB0. To clear this condition the USBSS must be reset via a hard or soft reset."
        }
    }
    "USB1GENRNDISEP10__bitfield" {
        "EP10_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP11__bitfield" {
        "EP11_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP12__bitfield" {
        "EP12_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP13__bitfield" {
        "EP13_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP14__bitfield" {
        "EP14_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP15__bitfield" {
        "EP15_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP1__bitfield" {
        "EP1_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP2__bitfield" {
        "EP2_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP3__bitfield" {
        "EP3_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP4__bitfield" {
        "EP4_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP5__bitfield" {
        "EP5_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP6__bitfield" {
        "EP6_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP7__bitfield" {
        "EP7_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP8__bitfield" {
        "EP8_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1GENRNDISEP9__bitfield" {
        "EP9_SIZE" {
            loc = "16..0"
            type = "binary"
            desc = "Generic RNDIS packet size. USB1 Generic RNDIS EP N Size Register"
        }
    }
    "USB1IRQENABLECLR0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 0 USB1 IRQ_ENABLE_CLR_0 Register"
        }
    }
    "USB1IRQENABLECLR1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 1"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for Suspend signaling detected USB1 IRQ_ENABLE_CLR_1 Register"
        }
    }
    "USB1IRQENABLESET0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for TX endpoint 0 USB1 IRQ_ENABLE_SET_0 Register"
        }
    }
    "USB1IRQENABLESET1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt enable for TX FIFO endpoint 1"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt enable for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt enable for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt enable for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt enable for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt enable for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable for Suspend signaling detected USB1 IRQ_ENABLE_SET_1 Register"
        }
    }
    "USB1IRQMSTAT__bitfield" {
        "BANK1" {
            loc = "1..1"
            type = "binary"
            desc = "0: No events pending from IRQ_STATUS_1 1: At least one event is pending from IRQ_STATUS_1"
        }
        "BANK0" {
            loc = "0..0"
            type = "binary"
            desc = "0: No events pending from IRQ_STATUS_0 1: At least one event is pending from IRQ_STATUS_0 USB1 IRQ_MERGED_STATUS Register"
        }
    }
    "USB1IRQSTAT0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt status for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt status for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt status for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt status for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for TX endpoint 0 USB1 IRQ_STATUS_0 Register"
        }
    }
    "USB1IRQSTAT1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 1"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for Suspend signaling detected USB1 IRQ_STATUS_1 Register"
        }
    }
    "USB1IRQSTATRAW0__bitfield" {
        "RX_EP_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for RX endpoint 15"
        }
        "RX_EP_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for RX endpoint 14"
        }
        "RX_EP_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for RX endpoint 13"
        }
        "RX_EP_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for RX endpoint 12"
        }
        "RX_EP_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for RX endpoint 11"
        }
        "RX_EP_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for RX endpoint 10"
        }
        "RX_EP_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for RX endpoint 9"
        }
        "RX_EP_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for RX endpoint 8"
        }
        "RX_EP_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for RX endpoint 7"
        }
        "RX_EP_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for RX endpoint 6"
        }
        "RX_EP_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for RX endpoint 5"
        }
        "RX_EP_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for RX endpoint 4"
        }
        "RX_EP_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for RX endpoint 3"
        }
        "RX_EP_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for RX endpoint 2"
        }
        "RX_EP_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for RX endpoint 1"
        }
        "TX_EP_15" {
            loc = "15..15"
            type = "binary"
            desc = "Interrupt status for TX endpoint 15"
        }
        "TX_EP_14" {
            loc = "14..14"
            type = "binary"
            desc = "Interrupt status for TX endpoint 14"
        }
        "TX_EP_13" {
            loc = "13..13"
            type = "binary"
            desc = "Interrupt status for TX endpoint 13"
        }
        "TX_EP_12" {
            loc = "12..12"
            type = "binary"
            desc = "Interrupt status for TX endpoint 12"
        }
        "TX_EP_11" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for TX endpoint 11"
        }
        "TX_EP_10" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for TX endpoint 10"
        }
        "TX_EP_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for TX endpoint 9"
        }
        "TX_EP_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for TX endpoint 8"
        }
        "TX_EP_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for TX endpoint 7"
        }
        "TX_EP_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for TX endpoint 6"
        }
        "TX_EP_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for TX endpoint 5"
        }
        "TX_EP_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for TX endpoint 4"
        }
        "TX_EP_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for TX endpoint 3"
        }
        "TX_EP_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for TX endpoint 2"
        }
        "TX_EP_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for TX endpoint 1"
        }
        "TX_EP_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for TX endpoint 0 USB1 IRQ_STATUS_RAW_0 Register"
        }
    }
    "USB1IRQSTATRAW1__bitfield" {
        "TX_FIFO_15" {
            loc = "31..31"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 15"
        }
        "TX_FIFO_14" {
            loc = "30..30"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 14"
        }
        "TX_FIFO_13" {
            loc = "29..29"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 13"
        }
        "TX_FIFO_12" {
            loc = "28..28"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 12"
        }
        "TX_FIFO_11" {
            loc = "27..27"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 11"
        }
        "TX_FIFO_10" {
            loc = "26..26"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 10"
        }
        "TX_FIFO_9" {
            loc = "25..25"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 9"
        }
        "TX_FIFO_8" {
            loc = "24..24"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 8"
        }
        "TX_FIFO_7" {
            loc = "23..23"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 7"
        }
        "TX_FIFO_6" {
            loc = "22..22"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 6"
        }
        "TX_FIFO_5" {
            loc = "21..21"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 5"
        }
        "TX_FIFO_4" {
            loc = "20..20"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 4"
        }
        "TX_FIFO_3" {
            loc = "19..19"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 3"
        }
        "TX_FIFO_2" {
            loc = "18..18"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 2"
        }
        "TX_FIFO_1" {
            loc = "17..17"
            type = "binary"
            desc = "Interrupt status for TX FIFO endpoint 1"
        }
        "USB_9" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for Mentor controller USB_INT generic  interrupt"
        }
        "USB_8" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for DRVVBUS level change"
        }
        "USB_7" {
            loc = "7..7"
            type = "binary"
            desc = "Interrupt status for VBUS < VBUS valid threshold"
        }
        "USB_6" {
            loc = "6..6"
            type = "binary"
            desc = "Interrupt status for SRP detected"
        }
        "USB_5" {
            loc = "5..5"
            type = "binary"
            desc = "Interrupt status for device disconnected (host mode)"
        }
        "USB_4" {
            loc = "4..4"
            type = "binary"
            desc = "Interrupt status for device connected (host mode)"
        }
        "USB_3" {
            loc = "3..3"
            type = "binary"
            desc = "Interrupt status for SOF started"
        }
        "USB_2" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status for Reset signaling detected (peripheral  mode) Babble detected (host mode)"
        }
        "USB_1" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status for Resume signaling detected"
        }
        "USB_0" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status for Suspend signaling detected USB1 IRQ_STATUS_RAW_1 Register"
        }
    }
    "USB1MODE__bitfield" {
        "IDDIG" {
            loc = "8..8"
            type = "binary"
            desc = "MGC input value for iddig 0=A type 1=B type"
        }
        "PHY_TEST" {
            loc = "1..1"
            type = "binary"
            desc = "PHY test 0 = Normal mode 1 = PHY test mode"
        }
        "LOOPBACK" {
            loc = "0..0"
            type = "binary"
            desc = "Loopback test mode 0 = Normal mode 1 = Loopback test mode USB1 Mode Register"
        }
    }
    "USB1REV__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between legacy interface scheme and current. 0 = Legacy 1 = Current"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Function indicates a software compatible module family."
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision. Will vary depending on release."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision."
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Custom revision"
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision. USB1 Revision Register"
        }
    }
    "USB1RXMODE__bitfield" {
        "RX15_MODE" {
            loc = "29..28"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 14 01: RNDIS Mode on RX endpoint 14 10: CDC Mode on RX endpoint 14 11: Generic RNDIS or Infinite Mode on RX endpoint 14"
        }
        "RX14_MODE" {
            loc = "27..26"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 13 01: RNDIS Mode on RX endpoint 13 10: CDC Mode on RX endpoint 13 11: Generic RNDIS or Infinite Mode on RX endpoint 13"
        }
        "RX13_MODE" {
            loc = "25..24"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 12 01: RNDIS Mode on RX endpoint 12 10: CDC Mode on RX endpoint 12 11: Generic RNDIS or Infinite Mode on RX endpoint 12"
        }
        "RX12_MODE" {
            loc = "23..22"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 11 01: RNDIS Mode on RX endpoint 11 10: CDC Mode on RX endpoint 11 11: Generic RNDIS or Infinite Mode on RX endpoint 11"
        }
        "RX11_MODE" {
            loc = "21..20"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 10 01: RNDIS Mode on RX endpoint 10 10: CDC Mode on RX endpoint 10 11: Generic RNDIS or Infinite Mode on RX endpoint 10"
        }
        "RX10_MODE" {
            loc = "19..18"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 9 01: RNDIS Mode on RX endpoint 9 10: CDC Mode on RX endpoint 9 11: Generic RNDIS or Infinite Mode on RX endpoint 9"
        }
        "RX9_MODE" {
            loc = "17..16"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 8 01: RNDIS Mode on RX endpoint 8 10: CDC Mode on RX endpoint 8 11: Generic RNDIS or Infinite Mode on RX endpoint 8"
        }
        "RX8_MODE" {
            loc = "15..14"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 7 01: RNDIS Mode on RX endpoint 7 10: CDC Mode on RX endpoint 7 11: Generic RNDIS or Infinite Mode on RX endpoint 7"
        }
        "RX7_MODE" {
            loc = "13..12"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 6 01: RNDIS Mode on RX endpoint 6 10: CDC Mode on RX endpoint 6 11: Generic RNDIS or Infinite Mode on RX endpoint 6"
        }
        "RX6_MODE" {
            loc = "11..10"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 5 01: RNDIS Mode on RX endpoint 5 10: CDC Mode on RX endpoint 5 11: Generic RNDIS or Infinite Mode on RX endpoint 5"
        }
        "RX5_MODE" {
            loc = "9..8"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 4 01: RNDIS Mode on RX endpoint 4 10: CDC Mode on RX endpoint 4 11: Generic RNDIS or Infinite Mode on RX endpoint 4"
        }
        "RX4_MODE" {
            loc = "7..6"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 3 01: RNDIS Mode on RX endpoint 3 10: CDC Mode on RX endpoint 3 11: Generic RNDIS or Infinite Mode on RX endpoint 3"
        }
        "RX3_MODE" {
            loc = "5..4"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 2 01: RNDIS Mode on RX endpoint 2 10: CDC Mode on RX endpoint 2 11: Generic RNDIS or Infinite Mode on RX endpoint 2"
        }
        "RX2_MODE" {
            loc = "3..2"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 1 01: RNDIS Mode on RX endpoint 1 10: CDC Mode on RX endpoint 1 11: Generic RNDIS or Infinite Mode on RX endpoint 1"
        }
        "RX1_MODE" {
            loc = "1..0"
            type = "binary"
            desc = "00: Transparent Mode on RX endpoint 0 01: RNDIS Mode on RX endpoint 0 10: CDC Mode on RX endpoint 0 11: Generic RNDIS or Infinite Mode on RX endpoint 0 USB1 Rx Mode Registers"
        }
    }
    "USB1SRPFIXTIME__bitfield" {
        "SRPFIXTIME" {
            loc = "31..0"
            type = "binary"
            desc = "SRP Fix maximum time in 60 MHz cycles. Default is  700 ms. USB1 SRP Fix Time Register"
        }
    }
    "USB1STAT__bitfield" {
        "DRVVBUS" {
            loc = "0..0"
            type = "binary"
            desc = "Current DRVVBUS value USB1 Status Register"
        }
    }
    "USB1TXMODE__bitfield" {
        "TX15_MODE" {
            loc = "29..28"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 14 01: RNDIS Mode on TX endpoint 14 10: CDC Mode on TX endpoint 14 11: Generic RNDIS Mode on TX endpoint 14"
        }
        "TX14_MODE" {
            loc = "27..26"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 13 01: RNDIS Mode on TX endpoint 13 10: CDC Mode on TX endpoint 13 11: Generic RNDIS Mode on TX endpoint 13"
        }
        "TX13_MODE" {
            loc = "25..24"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 12 01: RNDIS Mode on TX endpoint 12 10: CDC Mode on TX endpoint 12 11: Generic RNDIS Mode on TX endpoint 12"
        }
        "TX12_MODE" {
            loc = "23..22"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 11 01: RNDIS Mode on TX endpoint 11 10: CDC Mode on TX endpoint 11 11: Generic RNDIS Mode on TX endpoint 11"
        }
        "TX11_MODE" {
            loc = "21..20"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 10 01: RNDIS Mode on TX endpoint 10 10: CDC Mode on TX endpoint 10 11: Generic RNDIS Mode on TX endpoint 10"
        }
        "TX10_MODE" {
            loc = "19..18"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 9 01: RNDIS Mode on TX endpoint 9 10: CDC Mode on TX endpoint 9 11: Generic RNDIS Mode on TX endpoint 9"
        }
        "TX9_MODE" {
            loc = "17..16"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 8 01: RNDIS Mode on TX endpoint 8 10: CDC Mode on TX endpoint 8 11: Generic RNDIS Mode on TX endpoint 8"
        }
        "TX8_MODE" {
            loc = "15..14"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 7 01: RNDIS Mode on TX endpoint 7 10: CDC Mode on TX endpoint 7 11: Generic RNDIS Mode on TX endpoint 7"
        }
        "TX7_MODE" {
            loc = "13..12"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 6 01: RNDIS Mode on TX endpoint 6 10: CDC Mode on TX endpoint 6 11: Generic RNDIS Mode on TX endpoint 6"
        }
        "TX6_MODE" {
            loc = "11..10"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 5 01: RNDIS Mode on TX endpoint 5 10: CDC Mode on TX endpoint 5 11: Generic RNDIS Mode on TX endpoint 5"
        }
        "TX5_MODE" {
            loc = "9..8"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 4 01: RNDIS Mode on TX endpoint 4 10: CDC Mode on TX endpoint 4 11: Generic RNDIS Mode on TX endpoint 4"
        }
        "TX4_MODE" {
            loc = "7..6"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 3 01: RNDIS Mode on TX endpoint 3 10: CDC Mode on TX endpoint 3 11: Generic RNDIS Mode on TX endpoint 3"
        }
        "TX3_MODE" {
            loc = "5..4"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 2 01: RNDIS Mode on TX endpoint 2 10: CDC Mode on TX endpoint 2 11: Generic RNDIS Mode on TX endpoint 2"
        }
        "TX2_MODE" {
            loc = "3..2"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 1 01: RNDIS Mode on TX endpoint 1 10: CDC Mode on TX endpoint 1 11: Generic RNDIS Mode on TX endpoint 1"
        }
        "TX1_MODE" {
            loc = "1..0"
            type = "binary"
            desc = "00: Transparent Mode on TX endpoint 0 01: RNDIS Mode on TX endpoint 0 10: CDC Mode on TX endpoint 0 11: Generic RNDIS Mode on TX endpoint 0 USB1 Tx Mode Registers"
        }
    }
    "USB1UTMI__bitfield" {
        "TXBITSTUFFEN" {
            loc = "23..23"
            type = "binary"
            desc = "PHY UTMI input for signal txbitstuffen"
        }
        "TXBITSTUFFENH" {
            loc = "22..22"
            type = "binary"
            desc = "PHY UTMI input for signal txbitstuffenh"
        }
        "OTGDISABLE" {
            loc = "21..21"
            type = "binary"
            desc = "PHY UTMI input for signal otgdisable"
        }
        "VBUSVLDEXTSEL" {
            loc = "20..20"
            type = "binary"
            desc = "PHY UTMI input for signal vbusvldextsel"
        }
        "VBUSVLDEXT" {
            loc = "19..19"
            type = "binary"
            desc = "PHY UTMI input for signal vbusvldext"
        }
        "TXENABLEN" {
            loc = "18..18"
            type = "binary"
            desc = "PHY UTMI input for signal txenablen"
        }
        "FSXCVROWNER" {
            loc = "17..17"
            type = "binary"
            desc = "PHY UTMI input for signal fsxcvrowner"
        }
        "TXVALIDH" {
            loc = "16..16"
            type = "binary"
            desc = "PHY UTMI input for signal txvalidh"
        }
        "DATAINH" {
            loc = "15..8"
            type = "binary"
            desc = "PHY UTMI input for signal datainh"
        }
        "WORDINTERFACE" {
            loc = "2..2"
            type = "binary"
            desc = "PHY UTMI input for signal wordinterface"
        }
        "FSDATAEXT" {
            loc = "1..1"
            type = "binary"
            desc = "PHY UTMI input for signal fsdataext"
        }
        "FSSE0EXT" {
            loc = "0..0"
            type = "binary"
            desc = "PHY UTMI input for signal fsse0ext USB1 PHY UTMI Register"
        }
    }
    "USBSS_IRQCLEARR__bitfield" {
        "RX_PKT_CMP_1" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for USB1 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_1" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for USB1 Tx CPPI DMA packet completion  status"
        }
        "RX_PKT_CMP_0" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for USB0 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_0" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for USB0 Tx CPPI DMA packet completion  status"
        }
        "PD_CMP_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable when the packet is completed, the differ bits  is set,  and the Packet Descriptor is pushed into the queue  manager"
        }
        "RX_MOP_STARVATION" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable when queue manager cannot allocate an Rx  buffer in the middle of a packet."
        }
        "RX_SOP_STARVATION" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable when queue manager cannot allocate an Rx  buffer at the start of a packet. USBSS IRQ_ENABLE_CLR Register"
        }
    }
    "USBSS_IRQDMAENABLE0__bitfield" {
        "DMA_EN_RX0_15" {
            loc = "31..31"
            type = "binary"
            desc = "DMA threshold enable value for rx_pkt_cmp_0 for USB0  Endpoint 15. ... ... ... ... ..."
        }
        "DMA_EN_RX0_1" {
            loc = "17..17"
            type = "binary"
            desc = "DMA threshold enable value for rx_pkt_cmp_0 for USB0  Endpoint 1."
        }
        "DMA_EN_TX0_15" {
            loc = "15..15"
            type = "binary"
            desc = "DMA threshold enable value for tx_pkt_cmp_0 for USB0  Endpoint 15. ... ... ... ... ..."
        }
        "DMA_EN_TX0_2" {
            loc = "2..2"
            type = "binary"
            desc = "DMA threshold enable value for tx_pkt_cmp_0 for USB0  Endpoint 2."
        }
        "DMA_EN_TX0_1" {
            loc = "0..0"
            type = "binary"
            desc = "DMA threshold enable value for tx_pkt_cmp_0 for USB0  Endpoint 1."
        }
    }
    "USBSS_IRQDMAENABLE1__bitfield" {
        "DMA_EN_RX1_15" {
            loc = "31..31"
            type = "binary"
            desc = "DMA threshold enable value for rx_pkt_cmp_1 for USB1  Endpoint 15. ... ... ... ... ..."
        }
        "DMA_EN_RX1_1" {
            loc = "17..17"
            type = "binary"
            desc = "DMA threshold enable value for rx_pkt_cmp_1 for USB1  Endpoint 1."
        }
        "DMA_EN_TX1_15" {
            loc = "15..15"
            type = "binary"
            desc = "DMA threshold enable value for tx_pkt_cmp_1 for USB1  Endpoint 15. ... ... ... ... ..."
        }
        "DMA_EN_TX1_1" {
            loc = "1..1"
            type = "binary"
            desc = "DMA threshold enable value for tx_pkt_cmp_1 for USB1  Endpoint 1."
        }
    }
    "USBSS_IRQDMATHOLDRX00__bitfield" {
        "DMA_THRES_RX0_3" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 3."
        }
        "DMA_THRES_RX0_2" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 2."
        }
        "DMA_THRES_RX0_1" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 1."
        }
    }
    "USBSS_IRQDMATHOLDRX01__bitfield" {
        "DMA_THRES_RX0_7" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 7."
        }
        "DMA_THRES_RX0_6" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 6."
        }
        "DMA_THRES_RX0_5" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 5."
        }
        "DMA_THRES_RX0_4" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 4. USBSS IRQ_DMA_THRSHOLD_RX0_1 Register"
        }
    }
    "USBSS_IRQDMATHOLDRX02__bitfield" {
        "DMA_THRES_RX0_11" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  11."
        }
        "DMA_THRES_RX0_10" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  10."
        }
        "DMA_THRES_RX0_9" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 9."
        }
        "DMA_THRES_RX0_8" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 8. USBSS IRQ_DMA_THRSHOLD_RX0_2 Register"
        }
    }
    "USBSS_IRQDMATHOLDRX03__bitfield" {
        "DMA_THRES_RX0_15" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  15."
        }
        "DMA_THRES_RX0_14" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  14."
        }
        "DMA_THRES_RX0_13" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  13."
        }
        "DMA_THRES_RX0_12" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint  12. USBSS IRQ_DMA_THRSHOLD_RX0_3 Register"
        }
    }
    "USBSS_IRQDMATHOLDRX10__bitfield" {
        "DMA_THRES_RX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 3."
        }
        "DMA_THRES_RX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 2."
        }
        "DMA_THRES_RX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 1."
        }
    }
    "USBSS_IRQDMATHOLDRX11__bitfield" {
        "DMA_THRES_RX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 7."
        }
        "DMA_THRES_RX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 6."
        }
        "DMA_THRES_RX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 5."
        }
        "DMA_THRES_RX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 4. USBSS IRQ_DMA_THRSHOLD_RX1_1 Register"
        }
    }
    "USBSS_IRQDMATHOLDRX12__bitfield" {
        "DMA_THRES_RX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  11."
        }
        "DMA_THRES_RX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  10."
        }
        "DMA_THRES_RX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 9."
        }
        "DMA_THRES_RX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 8. USBSS IRQ_DMA_THRSHOLD_RX1_2 Register"
        }
    }
    "USBSS_IRQDMATHOLDRX13__bitfield" {
        "DMA_THRES_RX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  15."
        }
        "DMA_THRES_RX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  14."
        }
        "DMA_THRES_RX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  13."
        }
        "DMA_THRES_RX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint  12. USBSS IRQ_DMA_THRSHOLD_RX1_3 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX00__bitfield" {
        "DMA_THRES_TX0_3" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 3."
        }
        "DMA_THRES_TX0_2" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 2."
        }
        "DMA_THRES_TX0_1" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 1."
        }
    }
    "USBSS_IRQDMATHOLDTX01__bitfield" {
        "DMA_THRES_TX0_7" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 7."
        }
        "DMA_THRES_TX0_6" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 6."
        }
        "DMA_THRES_TX0_5" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 5."
        }
        "DMA_THRES_TX0_4" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 4. USBSS IRQ_DMA_THRSHOLD_TX0_1 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX02__bitfield" {
        "DMA_THRES_TX0_11" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  11."
        }
        "DMA_THRES_TX0_10" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  10."
        }
        "DMA_THRES_TX0_9" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 9."
        }
        "DMA_THRES_TX0_8" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 8. USBSS IRQ_DMA_THRSHOLD_TX0_2 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX03__bitfield" {
        "DMA_THRES_TX0_15" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  15."
        }
        "DMA_THRES_TX0_14" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  14."
        }
        "DMA_THRES_TX0_13" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  13."
        }
        "DMA_THRES_TX0_12" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint  12. USBSS IRQ_DMA_THRSHOLD_TX0_3 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX10__bitfield" {
        "DMA_THRES_TX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 3."
        }
        "DMA_THRES_TX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 2."
        }
        "DMA_THRES_TX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 1."
        }
    }
    "USBSS_IRQDMATHOLDTX11__bitfield" {
        "DMA_THRES_TX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 7."
        }
        "DMA_THRES_TX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 6."
        }
        "DMA_THRES_TX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 5."
        }
        "DMA_THRES_TX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 4. USBSS IRQ_DMA_THRSHOLD_TX1_1 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX12__bitfield" {
        "DMA_THRES_TX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  11."
        }
        "DMA_THRES_TX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  10."
        }
        "DMA_THRES_TX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 9."
        }
        "DMA_THRES_TX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 8. USBSS IRQ_DMA_THRSHOLD_TX1_2 Register"
        }
    }
    "USBSS_IRQDMATHOLDTX13__bitfield" {
        "DMA_THRES_TX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  15."
        }
        "DMA_THRES_TX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  14."
        }
        "DMA_THRES_TX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  13."
        }
        "DMA_THRES_TX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint  12. USBSS IRQ_DMA_THRSHOLD_TX1_3 Register"
        }
    }
    "USBSS_IRQENABLER__bitfield" {
        "RX_PKT_CMP_1" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt enable for USB1 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_1" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt enable for USB1 Tx CPPI DMA packet completion  status"
        }
        "RX_PKT_CMP_0" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt enable for USB0 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_0" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt enable for USB0 Tx CPPI DMA packet completion  status"
        }
        "PD_CMP_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt enable when the packet is completed, the differ bits  is set,  and the Packet Descriptor is pushed into the queue  manager"
        }
        "RX_MOP_STARVATION" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt enable when queue manager cannot allocate an Rx  buffer in the middle of a packet."
        }
        "RX_SOP_STARVATION" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt enable when queue manager cannot allocate an Rx  buffer at the start of a packet. USBSS IRQ_ENABLE_SET Register"
        }
    }
    "USBSS_IRQFRAMEENABLE0__bitfield" {
        "FRAME_EN_RX0_15" {
            loc = "31..31"
            type = "binary"
            desc = "FRAME threshold enable value for rx_pkt_cmp_0 for USB0  Endpoint 15. ... ... ... ... ..."
        }
        "FRAME_EN_RX0_1" {
            loc = "17..17"
            type = "binary"
            desc = "FRAME threshold enable value for rx_pkt_cmp_0 for USB0  Endpoint 1."
        }
        "FRAME_EN_TX0_15" {
            loc = "15..15"
            type = "binary"
            desc = "FRAME threshold enable value for tx_pkt_cmp_0 for USB0  Endpoint 15. ... ... ... ... ..."
        }
        "FRAME_EN_TX0_1" {
            loc = "1..1"
            type = "binary"
            desc = "FRAME threshold enable value for tx_pkt_cmp_0 for USB0  Endpoint 1."
        }
    }
    "USBSS_IRQFRAMEENABLE1__bitfield" {
        "FRAME_EN_RX1_15" {
            loc = "31..31"
            type = "binary"
            desc = "FRAME threshold enable value for rx_pkt_cmp_1 for USB1  Endpoint 15. ... ... ... ... ..."
        }
        "FRAME_EN_RX1_1" {
            loc = "17..17"
            type = "binary"
            desc = "FRAME threshold enable value for rx_pkt_cmp_1 for USB1  Endpoint 1."
        }
        "FRAME_EN_TX1_15" {
            loc = "15..15"
            type = "binary"
            desc = "FRAME threshold enable value for tx_pkt_cmp_1 for USB1  Endpoint 15. ... ... ... ... ..."
        }
        "FRAME_EN_TX1_1" {
            loc = "1..1"
            type = "binary"
            desc = "FRAME threshold enable value for tx_pkt_cmp_1 for USB1  Endpoint 1."
        }
    }
    "USBSS_IRQFRAMETHOLDRX00__bitfield" {
        "FRAME_THRES_RX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  3."
        }
        "FRAME_THRES_RX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  2."
        }
        "FRAME_THRES_RX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  1."
        }
    }
    "USBSS_IRQFRAMETHOLDRX01__bitfield" {
        "FRAME_THRES_RX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  7."
        }
        "FRAME_THRES_RX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  6."
        }
        "FRAME_THRES_RX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  5."
        }
        "FRAME_THRES_RX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  4. USBSS IRQ_FRAME_THRSHOLD_RX0_1 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDRX02__bitfield" {
        "FRAME_THRES_RX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  11."
        }
        "FRAME_THRES_RX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  10."
        }
        "FRAME_THRES_RX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  9."
        }
        "FRAME_THRES_RX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  8. USBSS IRQ_FRAME_THRSHOLD_RX0_2 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDRX03__bitfield" {
        "FRAME_THRES_RX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  15."
        }
        "FRAME_THRES_RX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  14."
        }
        "FRAME_THRES_RX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  13."
        }
        "FRAME_THRES_RX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint  12. USBSS IRQ_FRAME_THRSHOLD_RX0_3 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDRX10__bitfield" {
        "FRAME_THRES_RX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  3."
        }
        "FRAME_THRES_RX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  2."
        }
        "FRAME_THRES_RX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  1."
        }
    }
    "USBSS_IRQFRAMETHOLDRX11__bitfield" {
        "FRAME_THRES_RX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  7."
        }
        "FRAME_THRES_RX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  6."
        }
        "FRAME_THRES_RX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  5."
        }
        "FRAME_THRES_RX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  4. USBSS IRQ_FRAME_THRSHOLD_RX1_1 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDRX12__bitfield" {
        "FRAME_THRES_RX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  11."
        }
        "FRAME_THRES_RX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  10."
        }
        "FRAME_THRES_RX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  9."
        }
        "FRAME_THRES_RX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  8. USBSS IRQ_FRAME_THRSHOLD_RX1_2 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDRX13__bitfield" {
        "FRAME_THRES_RX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  15."
        }
        "FRAME_THRES_RX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  14."
        }
        "FRAME_THRES_RX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  13."
        }
        "FRAME_THRES_RX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint  12. USBSS IRQ_FRAME_THRSHOLD_RX1_3 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX00__bitfield" {
        "FRAME_THRES_TX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  3."
        }
        "FRAME_THRES_TX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  2."
        }
        "FRAME_THRES_TX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  1."
        }
    }
    "USBSS_IRQFRAMETHOLDTX01__bitfield" {
        "FRAME_THRES_TX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  7."
        }
        "FRAME_THRES_TX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  6."
        }
        "FRAME_THRES_TX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  5."
        }
        "FRAME_THRES_TX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  4. USBSS IRQ_FRAME_THRSHOLD_TX0_1 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX02__bitfield" {
        "FRAME_THRES_TX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  11."
        }
        "FRAME_THRES_TX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  10."
        }
        "FRAME_THRES_TX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  9."
        }
        "FRAME_THRES_TX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  8. USBSS IRQ_FRAME_THRSHOLD_TX0_2 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX03__bitfield" {
        "FRAME_THRES_TX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  15."
        }
        "FRAME_THRES_TX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  14."
        }
        "FRAME_THRES_TX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  13."
        }
        "FRAME_THRES_TX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint  12. USBSS IRQ_FRAME_THRSHOLD_TX0_3 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX10__bitfield" {
        "FRAME_THRES_TX1_3" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  3."
        }
        "FRAME_THRES_TX1_2" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  2."
        }
        "FRAME_THRES_TX1_1" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  1."
        }
    }
    "USBSS_IRQFRAMETHOLDTX11__bitfield" {
        "FRAME_THRES_TX1_7" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  7."
        }
        "FRAME_THRES_TX1_6" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  6."
        }
        "FRAME_THRES_TX1_5" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  5."
        }
        "FRAME_THRES_TX1_4" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  4. USBSS IRQ_FRAME_THRSHOLD_TX1_1 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX12__bitfield" {
        "FRAME_THRES_TX1_11" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  11."
        }
        "FRAME_THRES_TX1_10" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  10."
        }
        "FRAME_THRES_TX1_9" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  9."
        }
        "FRAME_THRES_TX1_8" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  8. USBSS IRQ_FRAME_THRSHOLD_TX1_2 Register"
        }
    }
    "USBSS_IRQFRAMETHOLDTX13__bitfield" {
        "FRAME_THRES_TX1_15" {
            loc = "31..24"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  15."
        }
        "FRAME_THRES_TX1_14" {
            loc = "23..16"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  14."
        }
        "FRAME_THRES_TX1_13" {
            loc = "15..8"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  13."
        }
        "FRAME_THRES_TX1_12" {
            loc = "7..0"
            type = "binary"
            desc = "FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint  12. USBSS IRQ_FRAME_THRSHOLD_TX1_3 Register"
        }
    }
    "USBSS_IRQSTATRAW__bitfield" {
        "RX_PKT_CMP_1" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for USB1 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_1" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for USB1 Tx CPPI DMA packet completion  status"
        }
        "RX_PKT_CMP_0" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for USB0 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_0" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for USB0 Tx CPPI DMA packet completion  status"
        }
        "PD_CMP_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status when the packet is completed, the differ bits  is set, and the Packet Descriptor is pushed into the queue  manager"
        }
        "RX_MOP_STARVATION" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status when queue manager cannot allocate an Rx  buffer in the middle of a packet."
        }
        "RX_SOP_STARVATION" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status when queue manager cannot allocate an Rx  buffer at the start of a packet. USBSS IRQ_STATUS_RAW Register"
        }
    }
    "USBSS_IRQSTAT__bitfield" {
        "RX_PKT_CMP_1" {
            loc = "11..11"
            type = "binary"
            desc = "Interrupt status for USB1 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_1" {
            loc = "10..10"
            type = "binary"
            desc = "Interrupt status for USB1 Tx CPPI DMA packet completion  status"
        }
        "RX_PKT_CMP_0" {
            loc = "9..9"
            type = "binary"
            desc = "Interrupt status for USB0 Rx CPPI DMA packet completion  status"
        }
        "TX_PKT_CMP_0" {
            loc = "8..8"
            type = "binary"
            desc = "Interrupt status for USB0 Tx CPPI DMA packet completion  status"
        }
        "PD_CMP_FLAG" {
            loc = "2..2"
            type = "binary"
            desc = "Interrupt status when the packet is completed, the differ bits  is set,  and the Packet Descriptor is pushed into the queue  manager"
        }
        "RX_MOP_STARVATION" {
            loc = "1..1"
            type = "binary"
            desc = "Interrupt status when queue manager cannot allocate an Rx  buffer in the middle of a packet."
        }
        "RX_SOP_STARVATION" {
            loc = "0..0"
            type = "binary"
            desc = "Interrupt status when queue manager cannot allocate an Rx  buffer at the start of a packet. USBSS IRQ_STATUS Register"
        }
    }
    "USBSS_REVREG__bitfield" {
        "SCHEME" {
            loc = "31..30"
            type = "binary"
            desc = "Used to distinguish between legacy interface scheme and current. 0 = Legacy 1 = Current"
        }
        "FUNC" {
            loc = "27..16"
            type = "binary"
            desc = "Function indicates a software compatible module family."
        }
        "R_RTL" {
            loc = "15..11"
            type = "binary"
            desc = "RTL revision. Will vary depending on release."
        }
        "X_MAJOR" {
            loc = "10..8"
            type = "binary"
            desc = "Major revision."
        }
        "CUSTOM" {
            loc = "7..6"
            type = "binary"
            desc = "Custom revision"
        }
        "Y_MINOR" {
            loc = "5..0"
            type = "binary"
            desc = "Minor revision. USBSS Revision Register"
        }
    }
    "USBSS_SYSCONFIG__bitfield" {
        "USB0_OCP_EN_N" {
            loc = "11..11"
            type = "binary"
            desc = "Active low clock enable for usb0_ocp_clk 0 = enable 1 = disable"
        }
        "PHY0_UTMI_EN_N" {
            loc = "10..10"
            type = "binary"
            desc = "Active low clock enable for phy0_utmi_clk 0 = enable 1 = disable"
        }
        "USB1_OCP_EN_N" {
            loc = "9..9"
            type = "binary"
            desc = "Active low clock enable for usb1_ocp_clk 0 = enable 1 = disable"
        }
        "PHY1_UTMI_EN_N" {
            loc = "8..8"
            type = "binary"
            desc = "Active low clock enable for phy1_utmi_clk 0 = enable 1 = disable"
        }
        "STANDBY_MODE" {
            loc = "5..4"
            type = "binary"
            desc = "Configuration of the local initiator state management mode. 0 = force-standby mode 1 = no-standby mode 2 = smart-standby mode 3 = smart-standby wakeup capable mode"
        }
        "IDLEMODE" {
            loc = "3..2"
            type = "binary"
            desc = "Configuration of the local target state management mode. 0 = force-idle mode 1 = no-idle mode 2 = smart-idle mode 3 = smart-idle wakeup capable mode"
        }
        "FREEEMU" {
            loc = "1..1"
            type = "binary"
            desc = "Sensitivity to emulation (debug) suspend input signal. 0 = sensitive to emulation suspend 1 = NOT sensitive to emulation suspend"
        }
        "SOFT_RESET" {
            loc = "0..0"
            type = "binary"
            desc = "Software reset of USBSS, USB0, and USB1 modules Write 0 = no action Write 1 = Initiate software reset Read 0 = Reset done, no action Read 1 = Reset ongoing USBSS SIGCONFIG Register"
        }
    }
    "USBTDOWN__bitfield" {
        "TX_TDOWN" {
            loc = "31..17"
            type = "binary"
            desc = "Tx Endpoint Teardown.  Write '1' to corresponding bit  to set.  Read as '0'. Bit 31 = Endpoint 15 ... Bit 17 = Endpoint 1"
        }
        "RX_TDOWN" {
            loc = "15..1"
            type = "binary"
            desc = "RX Endpoint Teardown.  Write '1' to corresponding  bit to set.  Read as '0'. Bit 15 = Endpoint 15 ... Bit 1 = Endpoint 1"
        }
    }
    "USBUTMILB__bitfield" {
        "SUSPENDM" {
            loc = "28..28"
            type = "binary"
            desc = "loopback test observed value for suspendm"
        }
        "OPMODE" {
            loc = "27..26"
            type = "binary"
            desc = "loopback test observed value for opmode"
        }
        "TXVALID" {
            loc = "25..25"
            type = "binary"
            desc = "loopback test observed value for txvalid"
        }
        "XCVRSEL" {
            loc = "24..23"
            type = "binary"
            desc = "loopback test observed value for xcvrsel"
        }
        "TERMSEL" {
            loc = "22..22"
            type = "binary"
            desc = "loopback test observed value for termsel"
        }
        "DRVVBUS" {
            loc = "21..21"
            type = "binary"
            desc = "loopback test observed value for drvvbus"
        }
        "CHRGVBUS" {
            loc = "20..20"
            type = "binary"
            desc = "loopback test observed value for chrgvbus"
        }
        "DISCHRGVBUS" {
            loc = "19..19"
            type = "binary"
            desc = "loopback test observed value for dischrgvbus"
        }
        "DPPULLDOWN" {
            loc = "18..18"
            type = "binary"
            desc = "loopback test observed value for dppulldown"
        }
        "DMPULLDOWN" {
            loc = "17..17"
            type = "binary"
            desc = "loopback test observed value for dmpulldown"
        }
        "IDPULLUP" {
            loc = "16..16"
            type = "binary"
            desc = "loopback test observed value for idpullup"
        }
        "IDDIG" {
            loc = "11..11"
            type = "binary"
            desc = "loopback test value for iddig"
        }
        "HOSTDISCON" {
            loc = "10..10"
            type = "binary"
            desc = "loopback test value for hostdiscon"
        }
        "SESSEND" {
            loc = "9..9"
            type = "binary"
            desc = "loopback test value for sessend"
        }
        "AVALID" {
            loc = "8..8"
            type = "binary"
            desc = "loopback test value for avalid"
        }
        "VBUSVALID" {
            loc = "7..7"
            type = "binary"
            desc = "loopback test value for vbusvalid"
        }
        "RXERROR" {
            loc = "6..6"
            type = "binary"
            desc = "loopback test value for rxerror"
        }
        "LINESTATE" {
            loc = "3..2"
            type = "binary"
            desc = "loopback test value for linestate"
        }
    }
    "USB_PHY_AD_INTERFACE_REG1__bitfield" {
        "USE_AD_DATA_REG" {
            loc = "31..31"
            type = "binary"
            desc = "Override for bits 30-29"
        }
        "HS_TX_DATA" {
            loc = "30..30"
            type = "binary"
        }
        "FS_TX_DATA" {
            loc = "29..29"
            type = "binary"
        }
        "TEST_PRE_EN_CNTRL" {
            loc = "28..28"
            type = "binary"
            desc = "Override for bits 27-25"
        }
        "SQ_PRE_EN" {
            loc = "27..27"
            type = "binary"
        }
        "HS_TX_PRE_EN" {
            loc = "26..26"
            type = "binary"
        }
        "HS_RX_PRE_EN" {
            loc = "25..25"
            type = "binary"
        }
        "TEST_EN_CNTRL" {
            loc = "24..24"
            type = "binary"
            desc = "Override for bits 23-19"
        }
        "HS_TX_EN" {
            loc = "23..23"
            type = "binary"
        }
        "FS_RX_EN" {
            loc = "22..22"
            type = "binary"
        }
        "Reserved__1" {
            loc = "21..21"
            type = "binary"
        }
        "SQ_EN" {
            loc = "20..20"
            type = "binary"
        }
        "HS_RX_EN" {
            loc = "19..19"
            type = "binary"
        }
        "TEST_HS_MODE" {
            loc = "18..18"
            type = "binary"
            desc = "Override for bits 17-16"
        }
        "HS_HV_SW" {
            loc = "17..17"
            type = "binary"
        }
        "HS_CHIRP" {
            loc = "16..16"
            type = "binary"
        }
        "TEST_FS_MODE" {
            loc = "15..15"
            type = "binary"
            desc = "Override for bits 14 - 12"
        }
        "FSTX_GZ" {
            loc = "14..14"
            type = "binary"
        }
        "FSTX_PRE_EN" {
            loc = "13..13"
            type = "binary"
        }
        "Reserved__2" {
            loc = "12..12"
            type = "binary"
        }
        "TEST_SQ_CAL_CONTROL" {
            loc = "11..11"
            type = "binary"
            desc = "Override for bits 10 - 8"
        }
        "SQ_CAL_EN3" {
            loc = "10..10"
            type = "binary"
        }
        "SQ_CAL_EN1" {
            loc = "9..9"
            type = "binary"
        }
        "SQ_CAL_EN2" {
            loc = "8..8"
            type = "binary"
        }
        "TEST_RTERM_CAL_CONTROL" {
            loc = "7..7"
            type = "binary"
            desc = "Override for bits 6"
        }
        "RTERM_CAL_EN" {
            loc = "6..6"
            type = "binary"
        }
        "DLL_RX_DATA" {
            loc = "5..5"
            type = "binary"
        }
        "DISCON_DETECT" {
            loc = "4..4"
            type = "binary"
        }
        "USE_LSHOST_REG" {
            loc = "3..3"
            type = "binary"
            desc = "Use bit 2 for this reg"
        }
        "LSHOSTMODE" {
            loc = "2..2"
            type = "binary"
        }
        "LSFS_RX_DATA" {
            loc = "1..1"
            type = "binary"
        }
        "SQUELCH" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_AD_INTERFACE_REG2__bitfield" {
        "USE_SUSP_DRV_REG" {
            loc = "31..31"
            type = "binary"
            desc = "Use bits 27-30 from this register as overrides"
        }
        "SUS_DRV_DP_DATA" {
            loc = "30..30"
            type = "binary"
        }
        "SUS_DRV_DP_EN" {
            loc = "29..29"
            type = "binary"
        }
        "SUS_DRV_DM_DATA" {
            loc = "28..28"
            type = "binary"
        }
        "SUS_DRV_DM_EN" {
            loc = "27..27"
            type = "binary"
        }
        "USE_DISCON_REG" {
            loc = "26..26"
            type = "binary"
            desc = "Use bits 24-25 from this register as override"
        }
        "DISCON_EN" {
            loc = "25..25"
            type = "binary"
        }
        "DISCON_PRE_EN" {
            loc = "24..24"
            type = "binary"
        }
        "Reserved" {
            loc = "23..23"
            type = "binary"
        }
        "SPARE_OUT_CORE" {
            loc = "22..18"
            type = "binary"
        }
        "SERX_DP_CORE" {
            loc = "17..17"
            type = "binary"
        }
        "SERX_DM_CORE" {
            loc = "16..16"
            type = "binary"
        }
        "USE_HSRX_CAL_EN_REG" {
            loc = "15..15"
            type = "binary"
            desc = "Use bit 14 from this register as override"
        }
        "HSRX_CAL_EN" {
            loc = "14..14"
            type = "binary"
        }
        "USE_RPU_RPD_REG" {
            loc = "13..13"
            type = "binary"
            desc = "Use override from bits 7-12"
        }
        "RPU_DP_SW1_EN_CORE" {
            loc = "12..12"
            type = "binary"
        }
        "RPU_DP_SW2_EN_CORE" {
            loc = "11..11"
            type = "binary"
        }
        "RPU_DM_SW1_EN_CORE" {
            loc = "10..10"
            type = "binary"
        }
        "RPU_DM_SW2_EN_CORE" {
            loc = "9..9"
            type = "binary"
        }
        "DP_PULLDOWN_EN_CORE" {
            loc = "8..8"
            type = "binary"
        }
        "DM_PULLDOWN_EN_CORE" {
            loc = "7..7"
            type = "binary"
        }
        "DP_DM_5V_SHORT" {
            loc = "6..6"
            type = "binary"
        }
        "SPARE_IN_CORE" {
            loc = "5..1"
            type = "binary"
        }
        "PORZ" {
            loc = "0..0"
            type = "binary"
            desc = "Read only bit -> the PORZ generated from the digital registered on the A-D interface."
        }
    }
    "USB_PHY_AD_INTERFACE_REG3__bitfield" {
        "USE_HSOS_DATA_REG" {
            loc = "31..31"
            type = "binary"
            desc = "Use bits 30-23 in this register as bypass bits"
        }
        "HSOS_DATA" {
            loc = "30..23"
            type = "binary"
        }
        "USE_FS_REG3" {
            loc = "22..22"
            type = "binary"
            desc = "Use bits 20-21 as bypass bits"
        }
        "FSTX_MODE" {
            loc = "21..21"
            type = "binary"
        }
        "FSTX_SE0" {
            loc = "20..20"
            type = "binary"
        }
        "USE_HS_TERM_RES_REG" {
            loc = "19..19"
            type = "binary"
            desc = "Use bit 18 as override bit"
        }
        "HS_TERM_RES" {
            loc = "18..18"
            type = "binary"
        }
        "SPARE_IN_LDO" {
            loc = "17..10"
            type = "binary"
        }
        "SPARE_OUT_LDO" {
            loc = "9..2"
            type = "binary"
        }
        "USE_FARCORE_REG" {
            loc = "1..1"
            type = "binary"
            desc = "Use bit 0 from this register as bypass"
        }
        "FARCORE" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_ANA_CONFIG1__bitfield" {
        "SQ_CTRL_REG" {
            loc = "31..17"
            type = "binary"
        }
        "FS_SLEW" {
            loc = "16..14"
            type = "binary"
        }
        "HS_PRE_EMP_CNTRL" {
            loc = "13..12"
            type = "binary"
        }
        "HSFSTX_TEST" {
            loc = "11..5"
            type = "binary"
        }
        "PROTECT_TEST" {
            loc = "4..0"
            type = "binary"
        }
    }
    "USB_PHY_ANA_CONFIG2__bitfield" {
        "RTERM_CAL_TEST" {
            loc = "31..27"
            type = "binary"
        }
        "REF_GEN_TEST" {
            loc = "26..20"
            type = "binary"
            desc = "REF_GEN_TEST[26:24] = 000 is the default REF_GEN_TEST[26:24] = 110 for increasing the vertical eye opening by 15mV REF_GEN_TEST[26:24] = 101 for decreasing the vertical eye opening by 15mV"
        }
        "FSRX_TEST" {
            loc = "19..15"
            type = "binary"
        }
        "DISCON_TEST" {
            loc = "14..11"
            type = "binary"
        }
        "HSRX_TEST" {
            loc = "10..6"
            type = "binary"
        }
        "SERX_TEST" {
            loc = "5..3"
            type = "binary"
        }
        "SERX_HYST_CNTRL" {
            loc = "2..1"
            type = "binary"
        }
        "SQ_LPMODEZ" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_BIST_CRC__bitfield" {
        "BIST_CRC" {
            loc = "31..0"
            type = "binary"
            desc = "The CRC value from the BIST."
        }
    }
    "USB_PHY_BIST__bitfield" {
        "BIST_START" {
            loc = "31..31"
            type = "binary"
            desc = "When set to '1' the BIST mode is started."
        }
        "REDUCED_SWING" {
            loc = "30..30"
            type = "binary"
            desc = "When '1' the TX swing is reduced in BIST mode"
        }
        "BIST_CRC_CALC_EN" {
            loc = "29..29"
            type = "binary"
            desc = "Enables CRC calculation during BIST when set to '1'"
        }
        "BIST_PKT_LENGTH" {
            loc = "28..20"
            type = "binary"
            desc = "Address for which BIST to select"
        }
        "LOOPBACK_EN" {
            loc = "19..19"
            type = "binary"
            desc = "Enables the loopback mode"
        }
        "BIST_OP_PHASE_SEL" {
            loc = "18..16"
            type = "binary"
            desc = "Selects which phase to use for data transmission during BIST"
        }
        "SWEEP_EN" {
            loc = "15..15"
            type = "binary"
            desc = "Enables freq sweep on CDR"
        }
        "SWEEP_MODE" {
            loc = "14..12"
            type = "binary"
            desc = "Selects the freq sweep mode. Details in DFT spec."
        }
        "BIST_PASS" {
            loc = "11..11"
            type = "binary"
            desc = "Indicates that the BIST has passed. Read value is valid only if VDDLDO is on."
        }
        "BIST_BUSY" {
            loc = "10..10"
            type = "binary"
            desc = "Indicates that BIST is running. Read value is valid only if VDDLDO is on."
        }
        "Reserved__1" {
            loc = "9..7"
            type = "binary"
        }
        "OP_CODE" {
            loc = "6..5"
            type = "binary"
            desc = "Defined in DFT spec"
        }
        "RX_TEST_MODE" {
            loc = "4..4"
            type = "binary"
            desc = "Defined in DFT spec"
        }
        "Reserved__2" {
            loc = "3..3"
            type = "binary"
        }
        "INTER_PKT_DELAY_TEST" {
            loc = "2..2"
            type = "binary"
            desc = "Defined in DFT spec"
        }
        "HS_ALL_ONES_TEST" {
            loc = "1..1"
            type = "binary"
            desc = "Defined in DFT spec"
        }
        "USE_BIST_TX_PHASES" {
            loc = "0..0"
            type = "binary"
            desc = "When set to '1' bits 18-16 are activated for choosing the transmitting phase."
        }
    }
    "USB_PHY_CDR_BIST2__bitfield" {
        "CDR_EXE_EN" {
            loc = "31..31"
            type = "binary"
            desc = "CDR debug bits"
        }
        "CDR_EXE_MODE" {
            loc = "30..28"
            type = "binary"
            desc = "CDR debug bits"
        }
        "NUM_DECISIONS" {
            loc = "27..25"
            type = "binary"
            desc = "CDR debug bits"
        }
        "CDR_CHOSEN_PHASE" {
            loc = "24..22"
            type = "binary"
        }
        "FORCE_CDR_PHASE" {
            loc = "21..19"
            type = "binary"
        }
        "DISABLE_CDR_FREQ_TRACK" {
            loc = "18..18"
            type = "binary"
        }
        "CDR_CONFIGURE" {
            loc = "17..13"
            type = "binary"
        }
        "FORCE_CDR_PHASE_EN" {
            loc = "12..12"
            type = "binary"
            desc = "Use bits 21-19 as the phase to be forced on the CDR."
        }
        "Bist_start_addr" {
            loc = "11..6"
            type = "binary"
            desc = "See DFT spec for details"
        }
        "Bist_end_addr" {
            loc = "5..0"
            type = "binary"
            desc = "See DFT spec for details"
        }
    }
    "USB_PHY_CHRG_DET__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "USE_CHG_DET_REG" {
            loc = "29..29"
            type = "binary"
            desc = "Use bits 28-24 and 18-17 from this register"
        }
        "DIS_CHG_DET" {
            loc = "28..28"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "SRC_ON_DM" {
            loc = "27..27"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "SINK_ON_DP" {
            loc = "26..26"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "CHG_DET_EXT_CTL" {
            loc = "25..25"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "RESTART_CHG_DET" {
            loc = "24..24"
            type = "binary"
            desc = "Restart the charger detection protocol when this goes from 0 to 1"
        }
        "CHG_DET_DONE" {
            loc = "23..23"
            type = "binary"
            desc = "Charger detect protocol has completed"
        }
        "CHG_DETECTED" {
            loc = "22..22"
            type = "binary"
            desc = "Same signal as CE"
        }
        "DATA_DET" {
            loc = "21..21"
            type = "binary"
            desc = "Output of the data det comparator"
        }
        "Reserved__2" {
            loc = "20..19"
            type = "binary"
        }
        "CHG_ISINK_EN" {
            loc = "18..18"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "CHG_VSRC_EN" {
            loc = "17..17"
            type = "binary"
            desc = "When read, returns current value of charger detect input. When USE_CHG_DET_REG = '1', the value written to this field  overrides the corresponding charger detect input."
        }
        "COMP_DP" {
            loc = "16..16"
            type = "binary"
            desc = "Comparator on the DP line value"
        }
        "COMP_DM" {
            loc = "15..15"
            type = "binary"
            desc = "Comparator on the DM line value"
        }
        "CHG_DET_OSC_CNTRL" {
            loc = "14..13"
            type = "binary"
            desc = "Charger detect osc control"
        }
        "CHG_DET_TIMER" {
            loc = "12..7"
            type = "binary"
            desc = "Charger detect timer control. See charger detect section for details"
        }
        "Reserved__3" {
            loc = "6..5"
            type = "binary"
        }
        "CHG_DET_ICTRL" {
            loc = "4..3"
            type = "binary"
            desc = "Charger detect current control"
        }
        "CHG_DET_VCTRL" {
            loc = "2..1"
            type = "binary"
            desc = "Charger detect voltage buffer control"
        }
        "FOR_CE" {
            loc = "0..0"
            type = "binary"
            desc = "Force CE = '1' when this bit is set"
        }
    }
    "USB_PHY_DLLHS_2__bitfield" {
        "DLLHS_CNTRL_LDO" {
            loc = "31..24"
            type = "binary"
            desc = "See DFT spec for details"
        }
        "DLLHS_STATUS_LDO" {
            loc = "23..16"
            type = "binary"
            desc = "See DFT spec for details"
        }
        "Reserved" {
            loc = "15..5"
            type = "binary"
        }
        "LINESTATE_DEBOUNCE_EN" {
            loc = "4..4"
            type = "binary"
            desc = "Enables the linestate debounce filter"
        }
        "LINESTATE_DEBOUNCE_CNTL" {
            loc = "3..0"
            type = "binary"
            desc = "Used for control of the linestate debounce filter when going from syncronous to async linestate."
        }
    }
    "USB_PHY_DLLHS__bitfield" {
        "Reserved__1" {
            loc = "31..29"
            type = "binary"
        }
        "DLLHS_LOCK" {
            loc = "28..28"
            type = "binary"
            desc = "Read the AFE output by this name"
        }
        "DLLHS_GENERATED_CODE" {
            loc = "27..22"
            type = "binary"
            desc = "Read the AFE output by this name.Read value is valid only if VDDLDO is on."
        }
        "DLL_SEL_CODE_PHS" {
            loc = "21..21"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[0] on AFE interface. see DFT spec for details."
        }
        "DLL_LOCKCHK" {
            loc = "20..19"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[2:1] on AFE interface. see DFT spec for details."
        }
        "DLL_SEL_COD" {
            loc = "18..16"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[5:3] on AFE interface. see DFT spec for details."
        }
        "DLL_PHS0_8" {
            loc = "15..15"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[6] on AFE interface. see DFT spec for details."
        }
        "DLL_FORCED_CODE" {
            loc = "14..9"
            type = "binary"
            desc = "Connect to the pin of this name  on AFE interface. see DFT spec for details."
        }
        "FORCE_DLL_CODE" {
            loc = "8..8"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[11] on AFE interface. see DFT spec for details."
        }
        "DLL_RATE" {
            loc = "7..6"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[8:7] on AFE interface. see DFT spec for details."
        }
        "DLL_FILT" {
            loc = "5..4"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[10:9] on AFE interface. see DFT spec for details."
        }
        "DLL_CDR_MODE" {
            loc = "3..3"
            type = "binary"
            desc = "Connect to the pin of this name  on AFE interface. see DFT spec for details."
        }
        "DLL_IDLE" {
            loc = "2..2"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[12] on AFE interface. see DFT spec for details."
        }
        "DLL_FREEZE" {
            loc = "1..1"
            type = "binary"
            desc = "Connect to DLLHS_TEST_LDO[13] on AFE interface. see DFT spec for details."
        }
        "Reserved__2" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_GPIO__bitfield" {
        "USEGPIOMODEREG" {
            loc = "31..31"
            type = "binary"
            desc = "When set to '1' use bits 31 - 24 from this register instead of primary inputs"
        }
        "GPIOMODE" {
            loc = "30..30"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "DPGPIOGZ" {
            loc = "29..29"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "DMGPIOGZ" {
            loc = "28..28"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "DPGPIOA" {
            loc = "27..27"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "DMGPIOA" {
            loc = "26..26"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "DPGPIOY" {
            loc = "25..25"
            type = "binary"
            desc = "The GPIO Y output is stored here"
        }
        "DMGPIOY" {
            loc = "24..24"
            type = "binary"
            desc = "The GPIO Y output is stored here"
        }
        "GPIO1P8VCONFIG" {
            loc = "23..23"
            type = "binary"
            desc = "Overrides the corresponding primary input"
        }
        "GPIOCONFIG" {
            loc = "22..20"
            type = "binary"
            desc = "Used for configuring the GPIOs. Details to be updated."
        }
        "DMGPIOPIPD" {
            loc = "19..19"
            type = "binary"
            desc = "GPIO mode DM pull down enabled. Overrides the corresponding primary input"
        }
        "DPGPIOPIPD" {
            loc = "18..18"
            type = "binary"
            desc = "GPIO mode DP pull-down enabled. Overrides the corresponding primary input."
        }
        "Reserved" {
            loc = "17..0"
            type = "binary"
        }
    }
    "USB_PHY_PWR_CNTL__bitfield" {
        "RESETDONETCLK" {
            loc = "31..31"
            type = "binary"
            desc = "Goes high when the RESET is synchronized to TCLK"
        }
        "RESET_DONE_VMAIN" {
            loc = "30..30"
            type = "binary"
            desc = "Goes high when LDO domain is up and PLL LOCK is available and utmi_reset is de-asserted."
        }
        "VMAIN_GLOBAL_RESET_DONE" {
            loc = "29..29"
            type = "binary"
            desc = "Goes high when LDO domain is up and PLL LOCK is available."
        }
        "RESETDONEMCLK" {
            loc = "28..28"
            type = "binary"
            desc = "Goes high when the RESET is synchronized to MCLK"
        }
        "RESETDONE_CHGDET" {
            loc = "27..27"
            type = "binary"
            desc = "Goes high when the RESET is synchronized to charger detect oscillator clock domain"
        }
        "LDOPWRCOUNTER" {
            loc = "26..12"
            type = "binary"
            desc = "This is the value of the counter used for LDO power up. RESET to default."
        }
        "FORCEPLLSLOWCLK" {
            loc = "11..11"
            type = "binary"
            desc = "Forces the PLL to the slow clk mode"
        }
        "FORCELDOON" {
            loc = "10..10"
            type = "binary"
            desc = "Forces the LDO to be ON."
        }
        "FORCEPLLON" {
            loc = "9..9"
            type = "binary"
            desc = "Forces the PLL to be ON."
        }
        "Reserved__1" {
            loc = "8..7"
            type = "binary"
        }
        "PLLLOCK" {
            loc = "6..6"
            type = "binary"
            desc = "Lock signal from the PLL"
        }
        "USEPLLLOCK" {
            loc = "5..5"
            type = "binary"
            desc = "This signal is used to indicate to the Phy, not to do any clock related activity until PLLLOCK = '1'.This is not the default option.0 - do not use PLLLOCK. 1 - use PLLLOCK as a clock gate."
        }
        "USE_DATAPOLARITYN_REG" {
            loc = "4..4"
            type = "binary"
            desc = "1 -> use bit 3 as override for the DATAPOLARITYN signal."
        }
        "DATAPOLARITYN" {
            loc = "3..3"
            type = "binary"
            desc = "Override value of datapolarityn"
        }
        "USE_PD_REG" {
            loc = "2..2"
            type = "binary"
            desc = "Use bit 1 from this register as PD override when set to '1'"
        }
        "PD" {
            loc = "1..1"
            type = "binary"
            desc = "Override value for PD"
        }
        "Reserved__2" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_RX_CALIB__bitfield" {
        "RESTART_HSRX_CAL" {
            loc = "31..31"
            type = "binary"
            desc = "Restart the HSRX calibration state machine when this bit goes from 0 to 1."
        }
        "USE_HS_OFF_REG" {
            loc = "30..30"
            type = "binary"
            desc = "Override HS offset correction with HS_OFF_CODE when set to '1'"
        }
        "HS_OFF_CODE" {
            loc = "29..24"
            type = "binary"
            desc = "HS offset code, this code is forced when bit 30 is '1'. Code is updated from calibration logic when bit 30 = 0."
        }
        "HSRX_COMP_OUT" {
            loc = "23..23"
            type = "binary"
            desc = "The output of the HSRX comparator.Read value is valid only if VDDLDO is on."
        }
        "HSRX_CAL_DONE" {
            loc = "22..22"
            type = "binary"
            desc = "Signal that indicates that the HSRX calibration is done. This gets reset at every restart.Read value is valid only if VDDLDO is on."
        }
        "USE_SQ_OFF_DAC1" {
            loc = "21..21"
            type = "binary"
            desc = "Override Squelch offset DAC1 code when '1'"
        }
        "SQ_OFF_CODE_DAC1" {
            loc = "20..15"
            type = "binary"
            desc = "When read returns current Sq offset code for DAC1, if VDDLDO is on. When written this is used as Sq offset code for DAC1 when USE_SQ_OFF_DAC1 = '1'"
        }
        "USE_SQ_OFF_DAC2" {
            loc = "14..14"
            type = "binary"
            desc = "Override Squelch offset DAC2 code when '1'"
        }
        "SQ_OFF_CODE_DAC2" {
            loc = "13..9"
            type = "binary"
            desc = "When read returns current Sq offset code for DAC2, if VDDLDO is on. When written this is used as Sq offset code for DAC2 when USE_SQ_OFF_DAC2 = '1'"
        }
        "USE_SQ_OFF_DAC3" {
            loc = "8..8"
            type = "binary"
            desc = "Override Squelch offset DAC3 code when '1'"
        }
        "SQ_OFF_CODE_DAC3" {
            loc = "7..3"
            type = "binary"
            desc = "When read returns current Sq offset code for DAC3, if VDDLDO is on. When written this is used as Sq offset code for DAC3 when USE_SQ_OFF_DAC3 = '1'"
        }
        "SQ_COMP_OUT" {
            loc = "2..2"
            type = "binary"
            desc = "Sq comp output.Read value is valid only if VDDLDO is on."
        }
        "SQ_CAL_DONE" {
            loc = "1..1"
            type = "binary"
            desc = "Sq calibration is done when this bit = 1. see RESTART_SQ_CAL for more description.Read value is valid only if VDDLDO is on."
        }
        "RESTART_SQ_CAL" {
            loc = "0..0"
            type = "binary"
            desc = "the squelch calibration continuously goes through restart cycles when this bit is '1'. i.e. restarts waits for done - then restarts again etc."
        }
    }
    "USB_PHY_RX_DEBUG_REG__bitfield" {
        "SYNCERR" {
            loc = "31..31"
            type = "binary"
        }
        "BITSTUFFERR" {
            loc = "30..30"
            type = "binary"
        }
        "UTMIRXDATARCV" {
            loc = "29..14"
            type = "binary"
        }
        "EOPERR" {
            loc = "13..13"
            type = "binary"
        }
        "PKTCOUNT" {
            loc = "12..10"
            type = "binary"
        }
        "BYTECOUNT" {
            loc = "9..5"
            type = "binary"
        }
        "SYNCBITCOUNT" {
            loc = "4..1"
            type = "binary"
        }
        "Reserved" {
            loc = "0..0"
            type = "binary"
        }
    }
    "USB_PHY_RX_TEST_2__bitfield" {
        "HSOSREVERSAL" {
            loc = "31..31"
            type = "binary"
            desc = "Swaps the dataout from HSOS"
        }
        "HSOSBITINVERSION" {
            loc = "30..30"
            type = "binary"
            desc = "Inverts the HSOS bits"
        }
        "PHYCLKOUTINVERSION" {
            loc = "29..29"
            type = "binary"
            desc = "This inverts the phase for the PHYCLKOUT"
        }
        "RXPIDERR" {
            loc = "28..28"
            type = "binary"
            desc = "Flags if the RX data packet has PID error. NOT IMPLEMENTED YET"
        }
        "USEINTDATAOUT" {
            loc = "27..27"
            type = "binary"
            desc = "This will bypass the analog and will send data packet to controller incase of receiver (Faking the receive data). data used will be INTDATAOUTREG"
        }
        "INTDATAOUTREG" {
            loc = "26..11"
            type = "binary"
            desc = "This register will be loaded through OCP and this data will be given to the controller if USEINTDATAOUT is set to '1'"
        }
        "Reserved" {
            loc = "10..8"
            type = "binary"
        }
        "CDR_TESTOUT" {
            loc = "7..0"
            type = "binary"
            desc = "CDR debug bits. Read value is valid only if VDDLDO is on. see DFT spec for details"
        }
    }
    "USB_PHY_Termination_control__bitfield" {
        "Reserved__1" {
            loc = "31..30"
            type = "binary"
        }
        "ALWAYS_UPDATE" {
            loc = "29..29"
            type = "binary"
            desc = "When set to '1', the calibration code is updated immediately after a code computation without waiting for idle periods."
        }
        "RTERM_CAL_DONE" {
            loc = "28..28"
            type = "binary"
            desc = "Rterm calibration is done. 1st time cal is done this bit gets set and gets reset at a restart cal.Read value is valid only if VDDLDO is on."
        }
        "FS_CODE_SEL" {
            loc = "27..24"
            type = "binary"
            desc = "FS Code selection control"
        }
        "Reserved__2" {
            loc = "23..22"
            type = "binary"
        }
        "USE_RTERM_RMX_REG" {
            loc = "21..21"
            type = "binary"
            desc = "Override termination resistor trim code with RTERM_RMX from this register"
        }
        "RTERM_RMX" {
            loc = "20..14"
            type = "binary"
            desc = "When read,  this field returns the current Termination resistor trim code.Read value is valid only if VDDLDO is on. The value written to this field is used as Termination resistor trim code  if bit 21 is set to '1'"
        }
        "HS_CODE_SEL" {
            loc = "13..11"
            type = "binary"
            desc = "HS Code selection control"
        }
        "RTERM_COMP_OUT" {
            loc = "10..10"
            type = "binary"
            desc = "Master loop comparator output. Read value is valid only if VDDLDO is on."
        }
        "RESTART_RTERM_CAL" {
            loc = "9..9"
            type = "binary"
            desc = "Restart the rterm calibration. The calibration restarts on any toggle 0 to 1 or 1 to 0 on this bit."
        }
        "DISABLE_TEMP_TRACK" {
            loc = "8..8"
            type = "binary"
            desc = "Disables the temperature tracking function of the termination calibration"
        }
        "USE_RTERM_CAL_REG" {
            loc = "7..7"
            type = "binary"
            desc = "when '1' the rterm cal code is overridden by values in RTERM_CAL"
        }
        "RTERM_CAL" {
            loc = "6..0"
            type = "binary"
            desc = "When read this field returns the current rterm calibration code. Read value is valid only if VDDLDO is on. The value written to this field is used as rterm calibration code  if  the bit USE_RTERM_CAL_REG is 1."
        }
    }
    "USB_PHY_USB2PHYCM_CONFIG__bitfield" {
        "CONFIGURECM" {
            loc = "31..24"
            type = "binary"
            desc = "Connects to the CONFIGURECM pins. see DFT spec for details."
        }
        "CMSTATUS" {
            loc = "23..18"
            type = "binary"
            desc = "Reads the CMSTATUS bits. see DFT spec for details."
        }
        "LDOCONFIG" {
            loc = "17..2"
            type = "binary"
            desc = "The LDOCONFIG bit settings. See DFT spec for details."
        }
        "LDOSTATUS" {
            loc = "1..0"
            type = "binary"
            desc = "Reads the LDOSTATUS bits. see DFT spec for details."
        }
    }
    "USB_PHY_USB2PHYCM_TRIM__bitfield" {
        "USEBGTRIM" {
            loc = "31..31"
            type = "binary"
            desc = "When set to '1' bits 30 to 16 are used as the trim value for the USB2PHYCM bandgap"
        }
        "BGTRIM" {
            loc = "30..16"
            type = "binary"
            desc = "Override value for the BGTRIM value"
        }
        "USE_SW_TRIM" {
            loc = "15..15"
            type = "binary"
            desc = "Use bits 14-9 to override the switch cap trim value."
        }
        "SWTRIM" {
            loc = "14..8"
            type = "binary"
            desc = "Override value for the switch cap trim value."
        }
        "USE_NWELLTRIM_REG" {
            loc = "7..7"
            type = "binary"
            desc = "Override NWELL resistor trim using NWELLTRIM_CODE"
        }
        "NWELLTRIM_CODE" {
            loc = "6..4"
            type = "binary"
            desc = "NWELL resistor trim code.This code is used if bit 21 is set to '1'"
        }
        "Reserved" {
            loc = "3..0"
            type = "binary"
        }
    }
    "USB_PHY_USBOTG__bitfield" {
        "TESTOTGCONFIG" {
            loc = "31..16"
            type = "binary"
            desc = "Used to control the OTG module if used."
        }
        "TESTOTGSTATUS" {
            loc = "15..6"
            type = "binary"
            desc = "The OTG status bits (if OTG macro is used)"
        }
        "Reserved" {
            loc = "5..0"
            type = "binary"
        }
    }
    "USB_PHY_UTMI_INTERFACE_CNTL_1__bitfield" {
        "USEUTMIDATAREG" {
            loc = "31..31"
            type = "binary"
            desc = "Use datain from UTMI interface register"
        }
        "UTMIDATAIN" {
            loc = "30..15"
            type = "binary"
            desc = "Override value for the UTMIDATAIN"
        }
        "Reserved" {
            loc = "14..14"
            type = "binary"
        }
        "USEDATABUSREG" {
            loc = "13..13"
            type = "binary"
            desc = "When set to '1' use bit 12 from register instead of interface"
        }
        "DATABUS16OR8" {
            loc = "12..12"
            type = "binary"
            desc = "Override value for UTMI signal DATABUS16OR8"
        }
        "USEOPMODEREG" {
            loc = "11..11"
            type = "binary"
            desc = "When set to '1' use bit 10-9 from register instead of interface"
        }
        "OPMODE" {
            loc = "10..9"
            type = "binary"
            desc = "Override value for UTMI signal OPMODE[1:0]"
        }
        "OVERRIDESUSRESET" {
            loc = "8..8"
            type = "binary"
            desc = "Override the suspend and reset values. Use bits 6 and 7"
        }
        "SUSPENDM" {
            loc = "7..7"
            type = "binary"
            desc = "Override value for UTMI signal SUSPENDM"
        }
        "UTMIRESET" {
            loc = "6..6"
            type = "binary"
            desc = "Override value for UTMI signal UTMIRESET"
        }
        "OVERRIDEXCVRSEL" {
            loc = "5..5"
            type = "binary"
            desc = "When set to '1' use bit 4-3 from register instead of interface"
        }
        "XCVRSEL" {
            loc = "4..3"
            type = "binary"
            desc = "Override value for UTMI signal XCVRSEL[1:0]"
        }
        "USETXVALIDREG" {
            loc = "2..2"
            type = "binary"
            desc = "When set to '1' use bit 1-0 from register instead of interface"
        }
        "TXVALID" {
            loc = "1..1"
            type = "binary"
            desc = "Override value for UTMI signal TXVALID"
        }
        "TXVALIDH" {
            loc = "0..0"
            type = "binary"
            desc = "Override value for UTMI signal TXVALIDH"
        }
    }
    "USB_PHY_UTMI_INTERFACE_CNTL_2__bitfield" {
        "RXRCV" {
            loc = "31..31"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on.Read value is valid only if VDDLDO is on."
        }
        "RXDP" {
            loc = "30..30"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "RXDM" {
            loc = "29..29"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "HOSTDISCONNECT" {
            loc = "28..28"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "LINESTATE" {
            loc = "27..26"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "RXVALID" {
            loc = "25..25"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "RXVALIDH" {
            loc = "24..24"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "RXACTIVE" {
            loc = "23..23"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "RXERROR" {
            loc = "22..22"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "TXREADY" {
            loc = "21..21"
            type = "binary"
            desc = "Read for UTMI signal.Read value is valid only if VDDLDO is on."
        }
        "UTMIRESETDONE" {
            loc = "20..20"
            type = "binary"
            desc = "Read for UTMIRESETDONE signal"
        }
        "USEBITSTUFFREG" {
            loc = "19..19"
            type = "binary"
            desc = "When set to '1' use bits 18-17 from register instead of interface"
        }
        "TXBITSTUFFENABLE" {
            loc = "18..18"
            type = "binary"
            desc = "Override value for signal TXBITSTUFFENABLE"
        }
        "TXBITSTUFFENABLEH" {
            loc = "17..17"
            type = "binary"
            desc = "Override value for pin TXBITSTUFFENABLE"
        }
        "USETERMCONTROLREG" {
            loc = "16..16"
            type = "binary"
            desc = "-When set to '1' use bits 15-13 from register instead of interface"
        }
        "TERMSEL" {
            loc = "15..15"
            type = "binary"
            desc = "Override value for signal TERMSEL"
        }
        "DPPULLDOWN" {
            loc = "14..14"
            type = "binary"
            desc = "Override value for signal DPPULLDOWN"
        }
        "DMPULLDOWN" {
            loc = "13..13"
            type = "binary"
            desc = "Override value for signal DMPULLDOWN"
        }
        "Reserved__1" {
            loc = "12..10"
            type = "binary"
        }
        "USEREGSERIALMODE" {
            loc = "9..9"
            type = "binary"
            desc = "When set to '1' use bits 8-5 from register instead of interface"
        }
        "TXSE0" {
            loc = "8..8"
            type = "binary"
            desc = "Override value for signal TXSE0"
        }
        "TXDAT" {
            loc = "7..7"
            type = "binary"
            desc = "Override value for signal TXDAT"
        }
        "FSLSSERIALMODE" {
            loc = "6..6"
            type = "binary"
            desc = "Override value for signal FSLSSERIALMODE"
        }
        "TXENABLEN" {
            loc = "5..5"
            type = "binary"
            desc = "Override value for signal TXENABLEN"
        }
        "Reserved__2" {
            loc = "4..1"
            type = "binary"
        }
        "sig_bypass_suspendmpulse_incr" {
            loc = "0..0"
            type = "binary"
            desc = "If the suspend signal is asserted for very short-time, it is pulse extended so that all the sampling logic samples it reliably. This pulse extention can be bypassed by writin a '1' to this bit ( so that IP's behaviour is similar to previous versions)"
        }
    }
    "WDT_WCLR__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "PRE" {
            loc = "5..5"
            type = "binary"
            desc = "Prescaler enable/disable configuration"
        }
        "PTV" {
            loc = "4..2"
            type = "binary"
            desc = "Prescaler value The timer counter is prescaled with the value: 2**PTV. Example: PTV = 3 then counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port."
        }
        "Reserved__2" {
            loc = "1..0"
            type = "binary"
        }
    }
    "WDT_WCRR__bitfield" {
        "TIMER_COUNTER" {
            loc = "31..0"
            type = "binary"
            desc = "Value of the timer counter register"
        }
    }
    "WDT_WDLY__bitfield" {
        "WDLY_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Value of the delay register"
        }
    }
    "WDT_WDSC__bitfield" {
        "Reserved__1" {
            loc = "31..6"
            type = "binary"
        }
        "EMUFREE" {
            loc = "5..5"
            type = "binary"
            desc = "Emulation mode"
        }
        "Reserved__2" {
            loc = "4..2"
            type = "binary"
        }
        "SOFTRESET" {
            loc = "1..1"
            type = "binary"
            desc = "Software reset. (Optional)"
        }
        "Reserved__3" {
            loc = "0..0"
            type = "binary"
        }
    }
    "WDT_WDST__bitfield" {
        "Reserved" {
            loc = "31..1"
            type = "binary"
        }
        "RESETDONE" {
            loc = "0..0"
            type = "binary"
            desc = "Internal module reset monitoring"
        }
    }
    "WDT_WIDR__bitfield" {
        "REVISION" {
            loc = "31..0"
            type = "binary"
            desc = "IP Revision"
        }
    }
    "WDT_WIER__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "DLY_IT_ENA" {
            loc = "1..1"
            type = "binary"
            desc = "Delay interrupt enable/disable"
        }
        "OVF_IT_ENA" {
            loc = "0..0"
            type = "binary"
            desc = "Overflow interrupt enable/disable"
        }
    }
    "WDT_WIRQEN__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "ENABLE_DLY" {
            loc = "1..1"
            type = "binary"
            desc = "Enable for delay event"
        }
        "ENABLE_OVF" {
            loc = "0..0"
            type = "binary"
            desc = "Enable for overflow event"
        }
    }
    "WDT_WIRQSTATRAW__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "EVENT_DLY" {
            loc = "1..1"
            type = "binary"
            desc = "Settable raw status for delay event"
        }
        "EVENT_OVF" {
            loc = "0..0"
            type = "binary"
            desc = "Settable raw status for overflow event"
        }
    }
    "WDT_WIRQSTAT__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "EVENT_DLY" {
            loc = "1..1"
            type = "binary"
            desc = "Clearable, enabled status for delay event"
        }
        "EVENT_OVF" {
            loc = "0..0"
            type = "binary"
            desc = "Clearable, enabled status for overflow event"
        }
    }
    "WDT_WISR__bitfield" {
        "Reserved" {
            loc = "31..2"
            type = "binary"
        }
        "DLY_IT_FLAG" {
            loc = "1..1"
            type = "binary"
            desc = "Pending delay interrupt status."
        }
        "OVF_IT_FLAG" {
            loc = "0..0"
            type = "binary"
            desc = "Pending overflow interrupt status."
        }
    }
    "WDT_WLDR__bitfield" {
        "TIMER_LOAD" {
            loc = "31..0"
            type = "binary"
            desc = "Value of the timer load register"
        }
    }
    "WDT_WSPR__bitfield" {
        "WSPR_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Value of the start-stop register"
        }
    }
    "WDT_WTGR__bitfield" {
        "TTGR_VALUE" {
            loc = "31..0"
            type = "binary"
            desc = "Value of the trigger register"
        }
    }
    "WDT_WWPS__bitfield" {
        "Reserved" {
            loc = "31..6"
            type = "binary"
        }
        "W_PEND_WDLY" {
            loc = "5..5"
            type = "binary"
            desc = "Write pending for register WDLY"
        }
        "W_PEND_WSPR" {
            loc = "4..4"
            type = "binary"
            desc = "Write pending for register WSPR"
        }
        "W_PEND_WTGR" {
            loc = "3..3"
            type = "binary"
            desc = "Write pending for register WTGR"
        }
        "W_PEND_WLDR" {
            loc = "2..2"
            type = "binary"
            desc = "Write pending for register WLDR"
        }
        "W_PEND_WCRR" {
            loc = "1..1"
            type = "binary"
            desc = "Write pending for register WCRR"
        }
        "W_PEND_WCLR" {
            loc = "0..0"
            type = "binary"
            desc = "Write pending for register WCLR"
        }
    }
    "WEEKS_REG__bitfield" {
        "Reserved" {
            loc = "31..3"
            type = "binary"
        }
        "WEEK" {
            loc = "2..0"
            type = "binary"
            desc = "1st digit of days in a week, Range from 0 (Sunday) to 6 (Saturday)"
        }
    }
    "WORD__bitfield" {
        "ENTRY3_RXTX" {
            loc = "31..31"
            type = "binary"
            desc = "This bit indicates if this entry is for a Tx  or an Rx channel and is encoded as  follows: 0 = Tx Channel 1 = Rx Channel"
        }
        "ENTRY2_RXTX" {
            loc = "23..23"
            type = "binary"
            desc = "This bit indicates if this entry is for a Tx  or an Rx channel and is encoded as  follows: 0 = Tx Channel 1 = Rx Channel"
        }
        "ENTRY1_RXTX" {
            loc = "15..15"
            type = "binary"
            desc = "This bit indicates if this entry is for a Tx  or an Rx channel and is encoded as  follows: 0 = Tx Channel 1 = Rx Channel"
        }
        "ENTRY0_RXTX" {
            loc = "7..7"
            type = "binary"
            desc = "This bit indicates if this entry is for a Tx  or an Rx channel and is encoded as  follows: 0 = Tx Channel 1 = Rx Channel"
        }
    }
    "YEARS_REG__bitfield" {
        "Reserved" {
            loc = "31..8"
            type = "binary"
        }
        "YEAR1" {
            loc = "7..4"
            type = "binary"
            desc = "2nd digit of years, Range is 0 to 9"
        }
        "YEAR0" {
            loc = "3..0"
            type = "binary"
            desc = "1st digit of years, Range is 0 to 9"
        }
    }
    "ZQ_CONFIG__bitfield" {
        "reg_zq_cs1en" {
            loc = "31..31"
            type = "binary"
            desc = "Writing a 1 enables ZQ calibration for CS1."
        }
        "reg_zq_cs0en" {
            loc = "30..30"
            type = "binary"
            desc = "Writing a 1 enables ZQ calibration for CS0."
        }
        "reg_zq_dualcalen" {
            loc = "29..29"
            type = "binary"
            desc = "ZQ Dual Calibration enable. Allows both ranks to be ZQ calibrated simultaneously. Setting this bit requires both chip selects to have a seerate calibration resistor per device."
        }
        "reg_zq_sfexiten" {
            loc = "28..28"
            type = "binary"
            desc = "ZQCL on Self Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit."
        }
        "Reserved" {
            loc = "27..20"
            type = "binary"
        }
        "reg_zq_zqinit_mult" {
            loc = "19..18"
            type = "binary"
            desc = "Indicates the number of ZQCL intervals that make up a ZQINIT interval, minus one."
        }
        "reg_zq_zqcl_mult" {
            loc = "17..16"
            type = "binary"
            desc = "Indicates the number of ZQCS intervals that make up a ZQCL interval, minus one. ZQCS interval is defined by reg_zq_zqcs in SDRAM Timing 3 Register."
        }
        "reg_zq_refinterval" {
            loc = "15..0"
            type = "binary"
            desc = "Number of refresh periods between ZQCS commans. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register."
        }
    }
}
"register" {
    "ADC_TSC_ADCRANGE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d048"
        desc = "High and Low Range Threshold@TSC_ADC_SS_Range_Check Register"
        type = "ADC_TSC_ADCRANGE__bitfield"
    }
    "ADC_TSC_ADCSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d044"
        desc = "General Status bits @TSC_ADC_SS_Sequencer_Status Register"
        type = "ADC_TSC_ADCSTAT__bitfield"
    }
    "ADC_TSC_ADC_CLKDIV" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d04c"
        desc = "ADC clock divider register@TSC_ADC_SS_Clock_Divider Register"
        type = "ADC_TSC_ADC_CLKDIV__bitfield"
    }
    "ADC_TSC_ADC_MISC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d050"
        desc = "AFE misc debug@TSC_ADC_SS_MISC Register"
        type = "ADC_TSC_ADC_MISC__bitfield"
    }
    "ADC_TSC_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d040"
        desc = "@TSC_ADC_SS Control Register"
        type = "ADC_TSC_CTRL__bitfield"
    }
    "ADC_TSC_DMA0REQ" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0ec"
        desc = "FIFO0 DMA req0 trigger@TSC_ADC_SS_FIFO0 DMA REQUEST Register"
        type = "ADC_TSC_DMAREQ__bitfield"
    }
    "ADC_TSC_DMA1REQ" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0f8"
        desc = "FIFO1  DMA req1 trigger@TSC_ADC_SS_FIFO1 DMA Request Register"
        type = "ADC_TSC_DMAREQ__bitfield"
    }
    "ADC_TSC_DMAENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d03c"
        desc = "Per-Line DMA clr"
        type = "ADC_TSC_DMAENABLE_CLR__bitfield"
    }
    "ADC_TSC_DMAENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d038"
        desc = "Per-Line DMA set"
        type = "ADC_TSC_DMAENABLE_SET__bitfield"
    }
    "ADC_TSC_FIFO0COUNT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0e4"
        desc = "FIFO0 word count@TSC_ADC_SS_FIFO0 Word Count Register"
        type = "ADC_TSC_FIFOCOUNT__bitfield"
    }
    "ADC_TSC_FIFO0DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d100"
        desc = "ADC_ FIFO0 _READ Data @TSC_ADC_SS_FIFO0 READ Register"
        type = "ADC_TSC_FIFODATA__bitfield"
    }
    "ADC_TSC_FIFO0THRESHOLD" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0e8"
        desc = "FIFO0 Threshold trigger@TSC_ADC_SS_FIFO0 Threshold Level Register"
        type = "ADC_TSC_FIFOTHRESHOLD__bitfield"
    }
    "ADC_TSC_FIFO1COUNT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0f0"
        desc = "FIFO1 word count@TSC_ADC_SS_FIFO1 Word Count Register"
        type = "ADC_TSC_FIFOCOUNT__bitfield"
    }
    "ADC_TSC_FIFO1DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d200"
        desc = "ADC FIFO1_READ Data@TSC_ADC_SS_FIFO1 READ Register"
        type = "ADC_TSC_FIFODATA__bitfield"
    }
    "ADC_TSC_FIFO1THRESHOLD" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0f4"
        desc = "FIFO1 Threshold trigger@TSC_ADC_SS_FIFO1 Threshold Level Register"
        type = "ADC_TSC_FIFOTHRESHOLD__bitfield"
    }
    "ADC_TSC_IDLECONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d058"
        desc = "Idle Step configuration@TSC_ADC_SS_IDLE_StepConfig Register"
        type = "ADC_TSC_IDLECONFIG__bitfield"
    }
    "ADC_TSC_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d030"
        desc = "IRQ enable clear bits"
        type = "ADC_TSC_IRQENABLE_CLR__bitfield"
    }
    "ADC_TSC_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d02c"
        desc = "IRQ enable set bits"
        type = "ADC_TSC_IRQENABLE_SET__bitfield"
    }
    "ADC_TSC_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d028"
        desc = "IRQ status (masked)"
        type = "ADC_TSC_IRQSTATUS__bitfield"
    }
    "ADC_TSC_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d024"
        desc = "IRQ status (unmasked)"
        type = "ADC_TSC_IRQSTATUS_RAW__bitfield"
    }
    "ADC_TSC_IRQWAKEUP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d034"
        desc = "IRQ wakeup enable"
        type = "ADC_TSC_IRQWAKEUP__bitfield"
    }
    "ADC_TSC_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d000"
        desc = "Revision Register"
        type = "ADC_TSC_REVISION__bitfield"
    }
    "ADC_TSC_STEPCONFIG1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d064"
        desc = "Step Configuration  1"
        type = "ADC_TSC_STEPCONFIG1__bitfield"
    }
    "ADC_TSC_STEPCONFIG10" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0ac"
        desc = "Step Configuration  10"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG11" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0b4"
        desc = "Step Configuration  11"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG12" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0bc"
        desc = "Step Configuration  12"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG13" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0c4"
        desc = "Step Configuration  13"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG14" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0cc"
        desc = "Step Configuration  14"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG15" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0d4"
        desc = "Step Configuration  15"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG16" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0dc"
        desc = "Step Configuration  16"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d06c"
        desc = "Step Configuration 2"
        type = "ADC_TSC_STEPCONFIG2__bitfield"
    }
    "ADC_TSC_STEPCONFIG3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d074"
        desc = "Step Configuration  3"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG4" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d07c"
        desc = "Step Configuration  4"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG5" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d084"
        desc = "Step Configuration  5"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG6" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d08c"
        desc = "Step Configuration  6"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG7" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d094"
        desc = "Step Configuration  7"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG8" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d09c"
        desc = "Step Configuration  8"
        type = "ADC_TSC_STEPCONFIG__bitfield"
    }
    "ADC_TSC_STEPCONFIG9" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0a4"
        desc = "Step Configuration  9"
        type = "ADC_TSC_STEPCONFIG9__bitfield"
    }
    "ADC_TSC_STEPDELAY1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d068"
        desc = "Step Delay Register 1"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY10" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0b0"
        desc = "Step Delay Register 10"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY11" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0b8"
        desc = "Step Delay Register 11"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY12" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0c0"
        desc = "Step Delay Register 12"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY13" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0c8"
        desc = "Step Delay Register 13"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY14" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0d0"
        desc = "Step Delay Register 14"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY15" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0d8"
        desc = "Step Delay Register 15"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY16" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0e0"
        desc = "Step Delay Register 16"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d070"
        desc = "Step Delay Register 2"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d078"
        desc = "Step Delay Register 3"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY4" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d080"
        desc = "Step Delay Register 4"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY5" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d088"
        desc = "Step Delay Register 5"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY6" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d090"
        desc = "Step Delay Register 6"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY7" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d098"
        desc = "Step Delay Register 7"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY8" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0a0"
        desc = "Step Delay Register 8"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPDELAY9" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d0a8"
        desc = "Step Delay Register 9"
        type = "ADC_TSC_STEPDELAY__bitfield"
    }
    "ADC_TSC_STEPENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d054"
        desc = "Step Enable"
        type = "ADC_TSC_STEPENABLE__bitfield"
    }
    "ADC_TSC_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d010"
        desc = "SysConfig Register"
        type = "ADC_TSC_SYSCONFIG__bitfield"
    }
    "ADC_TSC_TS_CHARGE_DELAY" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d060"
        desc = "TS Charge Delay Register@TSC_ADC_SS_TS_Charge_StepDelay Register"
        type = "ADC_TSC_TS_CHARGE_DELAY__bitfield"
    }
    "ADC_TSC_TS_CHARGE_STEPCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0d05c"
        desc = "TS Charge StepConfiguration@TSC_ADC_SS_TS_Charge_StepConfig Register"
        type = "ADC_TSC_TS_CHARGE_STEPCONFIG__bitfield"
    }
    "ALARM2_DAYS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e08c"
        desc = "The ALARM2_DAYS_REG is used to program the day of the month value for the alarm2 date. Days are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_DAYS_REG__bitfield"
    }
    "ALARM2_HOURS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e088"
        desc = "The ALARM2_HOURS_REG is used to program the hour value for the alarm2 time. Hours are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_HOURS_REG__bitfield"
    }
    "ALARM2_MINUTES_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e084"
        desc = "The ALARM2_MINUTES_REG is used to program the minute value for the alarm2 time. Minutes are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_MINUTES_REG__bitfield"
    }
    "ALARM2_MONTHS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e090"
        desc = "The ALARM2_MONTHS_REG is used to program the month in the year value for the alarm2 date. The month is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_MONTHS_REG__bitfield"
    }
    "ALARM2_SECONDS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e080"
        desc = "The ALARM2_SECONDS_REG is used to program the second value for the alarm2 time. Seconds are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_SECONDS_REG__bitfield"
    }
    "ALARM2_YEARS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e094"
        desc = "The ALARM2_YEARS_REG is used to program the year for the alarm2 date. Only the last two digits are used to represent the year and stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM2_YEARS_REG__bitfield"
    }
    "ALARM_DAYS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e02c"
        desc = "The ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt. Days are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_DAYS_REG__bitfield"
    }
    "ALARM_HOURS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e028"
        desc = "The ALARM_HOURS_REG is used to program the hour value for the alarm interrupt. Hours are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_HOURS_REG__bitfield"
    }
    "ALARM_MINUTES_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e024"
        desc = "The ALARM_MINUTES_REG is used to program the minute value for the alarm interrupt. Minutes are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_MINUTES_REG__bitfield"
    }
    "ALARM_MONTHS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e030"
        desc = "The ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt. The month is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_MONTHS_REG__bitfield"
    }
    "ALARM_SECONDS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e020"
        desc = "The ALARM_SECONDS_REG is used to program the second value for the alarm interrupt. Seconds are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_SECONDS_REG__bitfield"
    }
    "ALARM_YEARS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e034"
        desc = "The ALARM_YEARS_REG is used to program the year for the alarm interrupt. Only the last two digits are used to represent the year and is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent."
        type = "ALARM_YEARS_REG__bitfield"
    }
    "Broadcast_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100904"
    }
    "Broadcast_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100938"
    }
    "CLKSEL_GFX_FCLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0052c"
        desc = "Selects  the divider value for GFX clock [warm reset insensitive]"
        type = "CLKSEL_GFX_FCLK__bitfield"
    }
    "CLKSEL_GPIO0_DBCLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0053c"
        desc = "Selects  the Mux select line for GPIO0 debounce clock [warm reset insensitive]"
        type = "CLKSEL_GPIO0_DBCLK__bitfield"
    }
    "CLKSEL_LCDC_PIXEL_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00534"
        desc = "Controls  the Mux select line for LCDC PIXEL clock [warm reset insensitive]"
        type = "CLKSEL_LCDC_PIXEL_CLK__bitfield"
    }
    "CLKSEL_PRU_ICSS_OCP_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00530"
        desc = "Controls  the Mux select line for PRU-ICSS OCP clock [warm reset insensitive]"
        type = "CLKSEL_PRU_ICSS_OCP_CLK__bitfield"
    }
    "CLKSEL_TIMER1MS_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00528"
        desc = "Selects  the Mux select line for TIMER1 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER1MS_CLK__bitfield"
    }
    "CLKSEL_TIMER2_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00508"
        desc = "Selects  the Mux select line for TIMER2 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER2_CLK__bitfield"
    }
    "CLKSEL_TIMER3_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0050c"
        desc = "Selects  the Mux select line for TIMER3 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER3_CLK__bitfield"
    }
    "CLKSEL_TIMER4_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00510"
        desc = "Selects  the Mux select line for TIMER4 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER4_CLK__bitfield"
    }
    "CLKSEL_TIMER5_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00518"
        desc = "Selects  the Mux select line for TIMER5 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER5_CLK__bitfield"
    }
    "CLKSEL_TIMER6_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0051c"
        desc = "Selects  the Mux select line for TIMER6 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER6_CLK__bitfield"
    }
    "CLKSEL_TIMER7_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00504"
        desc = "Selects  the Mux select line for TIMER7 clock [warm reset insensitive]"
        type = "CLKSEL_TIMER7_CLK__bitfield"
    }
    "CLKSEL_WDT1_CLK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00538"
        desc = "Selects  the Mux select line for Watchdog1 clock [warm reset insensitive]"
        type = "CLKSEL_WDT1_CLK__bitfield"
    }
    "CMD0_REG_PHY_CTRL_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1201c"
    }
    "CMD0_REG_PHY_DLL_LOCK_DIFF_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12028"
    }
    "CMD0_REG_PHY_INVERT_CLKOUT_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1202c"
    }
    "CMD1_REG_PHY_CTRL_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12050"
    }
    "CMD1_REG_PHY_DLL_LOCK_DIFF_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1205c"
    }
    "CMD1_REG_PHY_INVERT_CLKOUT_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12060"
    }
    "CMD2_REG_PHY_CTRL_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12084"
    }
    "CMD2_REG_PHY_DLL_LOCK_DIFF_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12090"
    }
    "CMD2_REG_PHY_INVERT_CLKOUT_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12094"
    }
    "CM_AUTOIDLE_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00458"
        desc = "This register provides automatic control over the DPLL activity."
        type = "CM_AUTOIDLE_DPLL___bitfield__2"
    }
    "CM_AUTOIDLE_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00430"
        desc = "This register provides automatic control over the DPLL activity."
        type = "CM_AUTOIDLE_DPLL___bitfield__1"
    }
    "CM_AUTOIDLE_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00444"
        desc = "This register provides automatic control over the DPLL activity."
        type = "CM_AUTOIDLE_DPLL___bitfield__1"
    }
    "CM_AUTOIDLE_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0041c"
        desc = "This register provides automatic control over the DPLL activity."
        type = "CM_AUTOIDLE_DPLL___bitfield__2"
    }
    "CM_AUTOIDLE_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0046c"
        desc = "This register provides automatic control over the DPLL activity."
        type = "CM_AUTOIDLE_DPLL___bitfield__1"
    }
    "CM_CEFUSE_CEFUSE_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00a20"
        desc = "This register manages the CEFUSE clocks."
        type = "CM_CEFUSE_CEFUSE_CLKCTRL__bitfield"
    }
    "CM_CEFUSE_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00a00"
        desc = "This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_CEFUSE_CLKSTCTRL__bitfield"
    }
    "CM_CLKDCOLDO_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0047c"
        desc = "This register provides controls over the digitally controlled oscillator output of the PER DPLL."
        type = "CM_CLKDCOLDO_DPLL_PER__bitfield"
    }
    "CM_CLKMODE_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00490"
        desc = "This register allows controlling the DPLL modes."
        type = "CM_CLKMODE_DPLL___bitfield"
    }
    "CM_CLKMODE_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00494"
        desc = "This register allows controlling the DPLL modes."
        type = "CM_CLKMODE_DPLL___bitfield"
    }
    "CM_CLKMODE_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00498"
        desc = "This register allows controlling the DPLL modes."
        type = "CM_CLKMODE_DPLL___bitfield"
    }
    "CM_CLKMODE_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00488"
        desc = "This register allows controlling the DPLL modes."
        type = "CM_CLKMODE_DPLL___bitfield"
    }
    "CM_CLKMODE_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0048c"
        desc = "This register allows controlling the DPLL modes."
        type = "CM_CLKMODE_DPLL_PER__bitfield"
    }
    "CM_CLKOUT_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00700"
        desc = "This register provides the control over CLKOUT2 output"
        type = "CM_CLKOUT_CTRL__bitfield"
    }
    "CM_CLKSEL_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00468"
        desc = "This register provides controls over the DPLL."
        type = "CM_CLKSEL_DPLL_CORE__bitfield"
    }
    "CM_CLKSEL_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00440"
        desc = "This register provides controls over the DPLL."
        type = "CM_CLKSEL_DPLL_DDR__bitfield"
    }
    "CM_CLKSEL_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00454"
        desc = "This register provides controls over the DPLL."
        type = "CM_CLKSEL_DPLL_DISP__bitfield"
    }
    "CM_CLKSEL_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0042c"
        desc = "This register provides controls over the DPLL."
        type = "CM_CLKSEL_DPLL_MPU__bitfield"
    }
    "CM_CLKSEL_DPLL_PERIPH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0049c"
        desc = "This register provides controls over the DPLL."
        type = "CM_CLKSEL_DPLL_PERIPH__bitfield"
    }
    "CM_CPTS_RFT_CLKSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00520"
        desc = "Selects  the Mux select line for CPTS RFT clock [warm reset insensitive]"
        type = "CM_CPTS_RFT_CLKSEL__bitfield"
    }
    "CM_DIV_M2_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004a0"
        desc = "This register provides controls over the M2 divider of the DPLL."
        type = "CM_DIV_M2_DPLL___bitfield"
    }
    "CM_DIV_M2_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004a4"
        desc = "This register provides controls over the M2 divider of the DPLL."
        type = "CM_DIV_M2_DPLL___bitfield"
    }
    "CM_DIV_M2_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004a8"
        desc = "This register provides controls over the M2 divider of the DPLL."
        type = "CM_DIV_M2_DPLL___bitfield"
    }
    "CM_DIV_M2_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004ac"
        desc = "This register provides controls over the M2 divider of the DPLL."
        type = "CM_DIV_M2_DPLL_PER__bitfield"
    }
    "CM_DIV_M4_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00480"
        desc = "This register provides controls over the CLKOUT1 o/p of the HSDIVIDER."
        type = "CM_DIV_M4_DPLL_CORE__bitfield"
    }
    "CM_DIV_M5_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00484"
        desc = "This register provides controls over the CLKOUT2 o/p of the HSDIVIDER."
        type = "CM_DIV_M5_DPLL_CORE__bitfield"
    }
    "CM_DIV_M6_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004d8"
        desc = "This register provides controls over the CLKOUT3 o/p of the HSDIVIDER. [warm reset insensitive]"
        type = "CM_DIV_M6_DPLL_CORE__bitfield"
    }
    "CM_GFX_GFX_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00904"
        desc = "This register manages the GFX clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_GFX_L3_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00900"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_GFX_L3_CLKSTCTRL__bitfield"
    }
    "CM_GFX_L4LS_GFX_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0090c"
        desc = "This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_GFX_L4LS_GFX_CLKSTCTRL__bitfield"
    }
    "CM_GFX_MMUCFG_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00910"
        desc = "This register manages the MMU CFG clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_GFX_MMUDATA_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00914"
        desc = "This register manages the MMU clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_IDLEST_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0045c"
        desc = "This register allows monitoring the master clock activity. This register is read only and automatically updated. [warm reset insensitive]"
        type = "CM_IDLEST_DPLL___bitfield"
    }
    "CM_IDLEST_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00434"
        desc = "This register allows monitoring the master clock activity. This register is read only and automatically updated. [warm reset insensitive]"
        type = "CM_IDLEST_DPLL___bitfield"
    }
    "CM_IDLEST_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00448"
        desc = "This register allows monitoring the master clock activity. This register is read only and automatically updated. [warm reset insensitive]"
        type = "CM_IDLEST_DPLL___bitfield"
    }
    "CM_IDLEST_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00420"
        desc = "This register allows monitoring the master clock activity. This register is read only and automatically updated.[warm reset insensitive]"
        type = "CM_IDLEST_DPLL___bitfield"
    }
    "CM_IDLEST_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00470"
        desc = "This register allows monitoring the master clock activity. This register is read only and automatically updated. [warm reset insensitive]"
        type = "CM_IDLEST_DPLL___bitfield"
    }
    "CM_L3_AON_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00418"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_L3_AON_CLKSTCTRL__bitfield"
    }
    "CM_L4_WKUP_AON_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004cc"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_L4_WKUP_AON_CLKSTCTRL__bitfield"
    }
    "CM_MAC_CLKSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00514"
        desc = "Selects  the clock divide ration for MII clock [warm reset insensitive]"
        type = "CM_MAC_CLKSEL__bitfield"
    }
    "CM_MPU_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00600"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_MPU_CLKSTCTRL__bitfield"
    }
    "CM_MPU_MPU_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00604"
        desc = "This register manages the MPU clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_CLKDIV32K_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0014c"
        desc = "This register manages the CLKDIV32K clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_CLK_24MHZ_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00150"
        desc = "This register  enables  the clock domain state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_CLK_24MHZ_CLKSTCTRL__bitfield"
    }
    "CM_PER_CPGMAC0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00014"
        desc = "This register manages the CPSW clocks."
        type = "CM_PER_CPGMAC0_CLKCTRL__bitfield"
    }
    "CM_PER_CPSW_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00144"
        desc = "This register  enables  the clock domain state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_CPSW_CLKSTCTRL__bitfield"
    }
    "CM_PER_DCAN0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000c0"
        desc = "This register manages the DCAN0 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_PER_DCAN1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000c4"
        desc = "This register manages the DCAN1 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_PER_ELM_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00040"
        desc = "This register manages the ELM clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_EMIF_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00028"
        desc = "This register manages the EMIF clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_EPWMSS0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000d4"
        desc = "This register manages the PWMSS0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_EPWMSS1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000cc"
        desc = "This register manages the PWMSS1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_EPWMSS2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000d8"
        desc = "This register manages the PWMSS2 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_GPIO1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000ac"
        desc = "This register manages the GPIO1 clocks."
        type = "CM_PER_GPIO1_CLKCTRL__bitfield"
    }
    "CM_PER_GPIO2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000b0"
        desc = "This register manages the GPIO2 clocks."
        type = "CM_PER_GPIO2_CLKCTRL__bitfield"
    }
    "CM_PER_GPIO3_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000b4"
        desc = "This register manages the GPIO3 clocks."
        type = "CM_PER_GPIO3_CLKCTRL__bitfield"
    }
    "CM_PER_GPMC_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00030"
        desc = "This register manages the GPMC clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_I2C1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00048"
        desc = "This register manages the I2C1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_I2C2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00044"
        desc = "This register manages the I2C2 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_IEEE5000_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000e4"
        desc = "This register manages the IEEE1500 clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_L3S_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00004"
        desc = "This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_L3S_CLKSTCTRL__bitfield"
    }
    "CM_PER_L3_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000e0"
        desc = "This register manages the L3 Interconnect clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_L3_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0000c"
        desc = "This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_L3_CLKSTCTRL__bitfield"
    }
    "CM_PER_L3_INSTR_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000dc"
        desc = "This register manages the L3 INSTR clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_L4FW_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00064"
        desc = "This register manages the L4FW clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_L4HS_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00120"
        desc = "This register manages the L4 Fast clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_L4HS_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0011c"
        desc = "This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_L4HS_CLKSTCTRL__bitfield"
    }
    "CM_PER_L4LS_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00060"
        desc = "This register manages the L4LS clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_L4LS_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00000"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-PER and ON-INPER states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_L4LS_CLKSTCTRL__bitfield"
    }
    "CM_PER_LCDC_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00018"
        desc = "This register manages the LCD clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_LCDC_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00148"
        desc = "This register  enables  the clock domain state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_LCDC_CLKSTCTRL__bitfield"
    }
    "CM_PER_MAILBOX0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00110"
        desc = "This register manages the MAILBOX0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_MCASP0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00034"
        desc = "This register manages the MCASP0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_MCASP1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00068"
        desc = "This register manages the MCASP1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_MMC0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0003c"
        desc = "This register manages the MMC0 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_PER_MMC1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000f4"
        desc = "This register manages the MMC1 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_PER_MMC2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000f8"
        desc = "This register manages the MMC2 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_PER_OCMCRAM_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0002c"
        desc = "This register manages the OCMC clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_OCPWP_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00130"
        desc = "This register manages the OCPWP clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_OCPWP_L3_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0012c"
        desc = "This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_OCPWP_L3_CLKSTCTRL__bitfield"
    }
    "CM_PER_PRU_ICSS_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000e8"
        desc = "This register manages the PRU-ICSS clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_PRU_ICSS_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00140"
        desc = "This register  enables  the clock domain state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_PER_PRU_ICSS_CLKSTCTRL__bitfield"
    }
    "CM_PER_SPI0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0004c"
        desc = "This register manages the SPI0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_SPI1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00050"
        desc = "This register manages the SPI1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_SPINLOCK_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0010c"
        desc = "This register manages the SPINLOCK clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00080"
        desc = "This register manages the TIMER2 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER3_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00084"
        desc = "This register manages the TIMER3 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER4_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00088"
        desc = "This register manages the TIMER4 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER5_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000ec"
        desc = "This register manages the TIMER5 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER6_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000f0"
        desc = "This register manages the TIMER6 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TIMER7_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0007c"
        desc = "This register manages the TIMER7 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TPCC_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000bc"
        desc = "This register manages the TPCC clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_TPTC0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00024"
        desc = "This register manages the TPTC clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_TPTC1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e000fc"
        desc = "This register manages the TPTC1 clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_TPTC2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00100"
        desc = "This register manages the TPTC2 clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_PER_UART1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0006c"
        desc = "This register manages the UART1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_UART2_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00070"
        desc = "This register manages the UART2 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_UART3_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00074"
        desc = "This register manages the UART3 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_UART4_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00078"
        desc = "This register manages the UART4 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_UART5_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00038"
        desc = "This register manages the UART5 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_PER_USB0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0001c"
        desc = "This register manages the USB clocks."
        type = "CM___CLKCTRL__bitfield__2"
    }
    "CM_RTC_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00804"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_RTC_CLKSTCTRL__bitfield"
    }
    "CM_RTC_RTC_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00800"
        desc = "This register manages the RTC clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_SSC_DELTAMSTEP_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00460"
        desc = "Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part. [warm reset insensitive]"
        type = "CM_SSC_DELTAMSTEP_DPLL___bitfield"
    }
    "CM_SSC_DELTAMSTEP_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00438"
        desc = "Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part. [warm reset insensitive]"
        type = "CM_SSC_DELTAMSTEP_DPLL___bitfield"
    }
    "CM_SSC_DELTAMSTEP_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0044c"
        desc = "Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part. [warm reset insensitive]"
        type = "CM_SSC_DELTAMSTEP_DPLL___bitfield"
    }
    "CM_SSC_DELTAMSTEP_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00424"
        desc = "Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part. [warm reset insensitive]"
        type = "CM_SSC_DELTAMSTEP_DPLL___bitfield"
    }
    "CM_SSC_DELTAMSTEP_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00474"
        desc = "Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part. [warm reset insensitive]"
        type = "CM_SSC_DELTAMSTEP_DPLL___bitfield"
    }
    "CM_SSC_MODFREQDIV_DPLL_CORE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00464"
        desc = "Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]"
        type = "CM_SSC_MODFREQDIV_DPLL___bitfield"
    }
    "CM_SSC_MODFREQDIV_DPLL_DDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0043c"
        desc = "Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]"
        type = "CM_SSC_MODFREQDIV_DPLL___bitfield"
    }
    "CM_SSC_MODFREQDIV_DPLL_DISP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00450"
        desc = "Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]"
        type = "CM_SSC_MODFREQDIV_DPLL___bitfield"
    }
    "CM_SSC_MODFREQDIV_DPLL_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00428"
        desc = "Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]"
        type = "CM_SSC_MODFREQDIV_DPLL___bitfield"
    }
    "CM_SSC_MODFREQDIV_DPLL_PER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00478"
        desc = "Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique by defining it as a ratio of DPLL_REFCLK/4 Fm = [DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV = MODFREQDIV_MANTISSA * 2^MODFREQDIV_EXPONENT [warm reset insensitive]"
        type = "CM_SSC_MODFREQDIV_DPLL___bitfield"
    }
    "CM_WKUP_ADC_TSC_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004bc"
        desc = "This register manages the ADC clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_WKUP_CLKSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00400"
        desc = "This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain."
        type = "CM_WKUP_CLKSTCTRL__bitfield"
    }
    "CM_WKUP_CONTROL_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00404"
        desc = "This register manages the Control Module clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_WKUP_DEBUGSS_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00414"
        desc = "This register manages the DEBUGSS clocks."
        type = "CM_WKUP_DEBUGSS_CLKCTRL__bitfield"
    }
    "CM_WKUP_GPIO0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00408"
        desc = "This register manages the GPIO0 clocks."
        type = "CM_WKUP_GPIO0_CLKCTRL__bitfield"
    }
    "CM_WKUP_I2C0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004b8"
        desc = "This register manages the I2C0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_WKUP_L4WKUP_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0040c"
        desc = "This register manages the L4WKUP clocks."
        type = "CM_WKUP_L4WKUP_CLKCTRL__bitfield"
    }
    "CM_WKUP_SMARTREFLEX0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004c0"
        desc = "This register manages the SmartReflex0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_WKUP_SMARTREFLEX1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004c8"
        desc = "This register manages the SmartReflex1 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_WKUP_TIMER0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00410"
        desc = "This register manages the TIMER0 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_WKUP_TIMER1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004c4"
        desc = "This register manages the TIMER1 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_WKUP_UART0_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004b4"
        desc = "This register manages the UART0 clocks."
        type = "CM__CLKCTRL__bitfield"
    }
    "CM_WKUP_WDT1_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004d4"
        desc = "This register manages the WDT1 clocks."
        type = "CM___CLKCTRL__bitfield__1"
    }
    "CM_WKUP_WKUP_M3_CLKCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e004b0"
        desc = "This register manages the WKUP M3 clocks."
        type = "CM_WKUP_WKUP_M3_CLKCTRL__bitfield"
    }
    "CONNID_COS_1_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000104"
        type = "CONNID_COS_1_MAP__bitfield"
    }
    "CONNID_COS_2_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000108"
        desc = " "
        type = "CONNID_COS_2_MAP__bitfield"
    }
    "CPSW_ALE_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d08"
        desc = "ADDRESS LOOKUP ENGINE CONTROL REGISTER"
        type = "CPSW_ALE_CONTROL__bitfield"
    }
    "CPSW_ALE_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d00"
        desc = "ADDRESS LOOKUP ENGINE ID/VERSION REGISTER"
        type = "CPSW_ALE_IDVER__bitfield"
    }
    "CPSW_ALE_PORTCTL0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d40"
        desc = "ADDRESS LOOKUP ENGINE PORT 0 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL__bitfield"
    }
    "CPSW_ALE_PORTCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d44"
        desc = "ADDRESS LOOKUP ENGINE PORT 1 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL__bitfield"
    }
    "CPSW_ALE_PORTCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d48"
        desc = "ADDRESS LOOKUP ENGINE PORT 2 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL__bitfield"
    }
    "CPSW_ALE_PORTCTL3" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d4c"
        desc = "ADDRESS LOOKUP ENGINE PORT 3 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL__bitfield"
    }
    "CPSW_ALE_PORTCTL4" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d50"
        desc = "ADDRESS LOOKUP ENGINE PORT 4 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL__bitfield"
    }
    "CPSW_ALE_PORTCTL5" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d54"
        desc = "ADDRESS LOOKUP ENGINE PORT 5 CONTROL REGISTER"
        type = "CPSW_ALE_PORTCTL5__bitfield"
    }
    "CPSW_ALE_PRESCALE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d10"
        desc = "ADDRESS LOOKUP ENGINE PRESCALE REGISTER"
        type = "CPSW_ALE_PRESCALE__bitfield"
    }
    "CPSW_ALE_TBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d20"
        desc = "ADDRESS LOOKUP ENGINE TABLE CONTROL"
        type = "CPSW_ALE_TBLCTL__bitfield"
    }
    "CPSW_ALE_TBLW0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d3c"
        desc = "ADDRESS LOOKUP ENGINE TABLE WORD 0 REGISTER"
        type = "CPSW_ALE_TBLW0__bitfield"
    }
    "CPSW_ALE_TBLW1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d38"
        desc = "ADDRESS LOOKUP ENGINE TABLE WORD 1 REGISTER"
        type = "CPSW_ALE_TBLW1__bitfield"
    }
    "CPSW_ALE_TBLW2" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d34"
        desc = "ADDRESS LOOKUP ENGINE TABLE WORD 2 REGISTER"
        type = "CPSW_ALE_TBLW2__bitfield"
    }
    "CPSW_ALE_UNKNOWN_VLAN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d18"
        desc = "ADDRESS LOOKUP ENGINE UNKNOWN VLAN REGISTER"
        type = "CPSW_ALE_UNKNOWN_VLAN__bitfield"
    }
    "CPSW_CPDMA_CPDMA_EOI_VECTOR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100894"
        desc = "CPDMA_INT END OF INTERRUPT VECTOR"
        type = "CPSW_CPDMA_CPDMA_EOI_VECTOR__bitfield"
    }
    "CPSW_CPDMA_CPDMA_IN_VECTOR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100890"
        desc = "CPDMA_INT INPUT VECTOR (READ ONLY)"
        type = "CPSW_CPDMA_CPDMA_IN_VECTOR__bitfield"
    }
    "CPSW_CPDMA_CPDMA_SOFT_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10081c"
        desc = "CPDMA_REGS SOFT RESET REGISTER"
        type = "CPSW_CPDMA_CPDMA_SOFT_RESET__bitfield"
    }
    "CPSW_CPDMA_DMACONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100820"
        desc = "CPDMA_REGS CPDMA CONTROL REGISTER"
        type = "CPSW_CPDMA_DMACONTROL__bitfield"
    }
    "CPSW_CPDMA_DMASTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100824"
        desc = "CPDMA_REGS CPDMA STATUS REGISTER"
        type = "CPSW_CPDMA_DMASTATUS__bitfield"
    }
    "CPSW_CPDMA_DMA_INTMASK_CLEAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008bc"
        desc = "CPDMA_INT DMA INTERRUPT MASK CLEAR REGISTER"
        type = "CPSW_CPDMA_DMA_INTMASK_CLEAR__bitfield"
    }
    "CPSW_CPDMA_DMA_INTMASK_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008b8"
        desc = "CPDMA_INT DMA INTERRUPT MASK SET REGISTER"
        type = "CPSW_CPDMA_DMA_INTMASK_SET__bitfield"
    }
    "CPSW_CPDMA_DMA_INTSTAT_MASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008b4"
        desc = "CPDMA_INT DMA INTERRUPT STATUS REGISTER (MASKED VALUE)"
        type = "CPSW_CPDMA_DMA_INTSTAT_MASKED__bitfield"
    }
    "CPSW_CPDMA_DMA_INTSTAT_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008b0"
        desc = "CPDMA_INT DMA INTERRUPT STATUS REGISTER (RAW VALUE)"
        type = "CPSW_CPDMA_DMA_INTSTAT_RAW__bitfield"
    }
    "CPSW_CPDMA_EMCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10082c"
        desc = "CPDMA_REGS EMULATION CONTROL"
        type = "CPSW__EMCONTROL__bitfield"
    }
    "CPSW_CPDMA_RX0_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008e0"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 0"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX0_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008c0"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 0"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX1_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008e4"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 1"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX1_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008c4"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 1"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX2_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008e8"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 2"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX2_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008c8"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 2"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX3_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008ec"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 3"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX3_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008cc"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 3"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX4_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008f0"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 4"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX4_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008d0"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 4"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX5_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008f4"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 5"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX5_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008d4"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 5"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX6_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008f8"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 6"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX6_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008d8"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 6"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX7_FREEBUFFER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008fc"
        desc = "CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 7"
        type = "CPSW_CPDMA_RX_FREEBUFFER__bitfield"
    }
    "CPSW_CPDMA_RX7_PENDTHRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008dc"
        desc = "CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 7"
        type = "CPSW_CPDMA_RX_PENDTHRESH__bitfield"
    }
    "CPSW_CPDMA_RX_BUFFER_OFFSET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100828"
        desc = "CPDMA_REGS RECEIVE BUFFER OFFSET"
        type = "CPSW_CPDMA_RX_BUFFER_OFFSET__bitfield"
    }
    "CPSW_CPDMA_RX_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100814"
        desc = "CPDMA_REGS RX CONTROL REGISTER"
        type = "CPSW_CPDMA_RX_CONTROL__bitfield"
    }
    "CPSW_CPDMA_RX_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100810"
        desc = "CPDMA_REGS RX IDENTIFICATION AND VERSION REGISTER"
        type = "CPSW_CPDMA_RX_IDVER__bitfield"
    }
    "CPSW_CPDMA_RX_INTMASK_CLEAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008ac"
        desc = "CPDMA_INT RX INTERRUPT MASK CLEAR REGISTER"
        type = "CPSW_CPDMA_RX_INTMASK_CLEAR__bitfield"
    }
    "CPSW_CPDMA_RX_INTMASK_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008a8"
        desc = "CPDMA_INT RX INTERRUPT MASK SET REGISTER"
        type = "CPSW_CPDMA_RX_INTMASK_SET__bitfield"
    }
    "CPSW_CPDMA_RX_INTSTAT_MASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008a4"
        desc = "CPDMA_INT RX INTERRUPT STATUS REGISTER (MASKED VALUE)"
        type = "CPSW_CPDMA_RX_INTSTAT_MASKED__bitfield"
    }
    "CPSW_CPDMA_RX_INTSTAT_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a1008a0"
        desc = "CPDMA_INT RX INTERRUPT STATUS REGISTER (RAW VALUE)"
        type = "CPSW_CPDMA_RX_INTSTAT_RAW__bitfield"
    }
    "CPSW_CPDMA_RX_TEARDOWN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100818"
        desc = "CPDMA_REGS RX TEARDOWN REGISTER"
        type = "CPSW_CPDMA_RX_TEARDOWN__bitfield"
    }
    "CPSW_CPDMA_TX_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100804"
        desc = "CPDMA_REGS TX CONTROL REGISTER"
        type = "CPSW_CPDMA_TX_CONTROL__bitfield"
    }
    "CPSW_CPDMA_TX_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100800"
        desc = "CPDMA_REGS TX IDENTIFICATION AND VERSION REGISTER"
        type = "CPSW_CPDMA_TX_IDVER__bitfield"
    }
    "CPSW_CPDMA_TX_INTMASK_CLEAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10088c"
        desc = "CPDMA_INT TX INTERRUPT MASK CLEAR REGISTER"
        type = "CPSW_CPDMA_TX_INTMASK_CLEAR__bitfield"
    }
    "CPSW_CPDMA_TX_INTMASK_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100888"
        desc = "CPDMA_INT TX INTERRUPT MASK SET REGISTER"
        type = "CPSW_CPDMA_TX_INTMASK_SET__bitfield"
    }
    "CPSW_CPDMA_TX_INTSTAT_MASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100884"
        desc = "CPDMA_INT TX INTERRUPT STATUS REGISTER  (MASKED VALUE)"
        type = "CPSW_CPDMA_TX_INTSTAT_MASKED__bitfield"
    }
    "CPSW_CPDMA_TX_INTSTAT_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100880"
        desc = "CPDMA_INT TX INTERRUPT STATUS REGISTER (RAW VALUE)"
        type = "CPSW_CPDMA_TX_INTSTAT_RAW__bitfield"
    }
    "CPSW_CPDMA_TX_PRI0_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100830"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 0 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI1_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100834"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 1 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI2_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100838"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 2 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI3_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10083c"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 3 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI4_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100840"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 4 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI5_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100844"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 5 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI6_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100848"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_PRI7_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10084c"
        desc = "CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 7 RATE"
        type = "CPSW_CPDMA_TX_PRI_RATE__bitfield"
    }
    "CPSW_CPDMA_TX_TEARDOWN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100808"
        desc = "CPDMA_REGS TX TEARDOWN REGISTER"
        type = "CPSW_CPDMA_TX_TEARDOWN__bitfield"
    }
    "CPSW_PORT_P0_BLK_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10010c"
        desc = "CPSW PORT 0 FIFO BLOCK USAGE COUNT (READ ONLY)"
        type = "CPSW_PORT_P0_BLK_CNT__bitfield"
    }
    "CPSW_PORT_P0_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100100"
        desc = "CPSW PORT 0 CONTROL REGISTER"
        type = "CPSW_PORT_P0_CONTROL__bitfield"
    }
    "CPSW_PORT_P0_CPDMA_RX_CH_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100120"
        desc = "CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL"
        type = "CPSW_PORT_P0_CPDMA_RX_CH_MAP__bitfield"
    }
    "CPSW_PORT_P0_CPDMA_TX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10011c"
        desc = "CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY"
        type = "CPSW_PORT_P0_CPDMA_TX_PRI_MAP__bitfield"
    }
    "CPSW_PORT_P0_MAX_BLKS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100108"
        desc = "CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER"
        type = "CPSW_PORT_P0_MAX_BLKS__bitfield"
    }
    "CPSW_PORT_P0_PORT_VLAN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100114"
        desc = "CPSW PORT 0 VLAN REGISTER"
        type = "CPSW_PORT_P_PORT_VLAN__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100130"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP0__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100134"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP1__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100138"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP2__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10013c"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP3__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100140"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP4__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP5" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100144"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP5__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP6" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100148"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP6__bitfield"
    }
    "CPSW_PORT_P0_RX_DSCP_PRI_MAP7" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10014c"
        desc = "CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP7__bitfield"
    }
    "CPSW_PORT_P0_TX_IN_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100110"
        desc = "CPSW PORT 0 TRANSMIT FIFO CONTROL"
        type = "CPSW_PORT_P0_TX_IN_CTL__bitfield"
    }
    "CPSW_PORT_P0_TX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100118"
        desc = "CPSW PORT 0 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER"
        type = "CPSW_PORT_P_TX_PRI_MAP__bitfield"
    }
    "CPSW_PORT_P1_BLK_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10020c"
        desc = "CPSW PORT 1 FIFO BLOCK USAGE COUNT (READ ONLY)"
        type = "CPSW_PORT_P1_BLK_CNT__bitfield"
    }
    "CPSW_PORT_P1_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100200"
        desc = "CPSW PORT 1 CONTROL REGISTER"
        type = "CPSW_PORT_P1_CONTROL__bitfield"
    }
    "CPSW_PORT_P1_MAX_BLKS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100208"
        desc = "CPSW PORT 1 MAXIMUM FIFO BLOCKS REGISTER"
        type = "CPSW_PORT_P1_MAX_BLKS__bitfield"
    }
    "CPSW_PORT_P1_PORT_VLAN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100214"
        desc = "CPSW PORT 1 VLAN REGISTER"
        type = "CPSW_PORT_P_PORT_VLAN__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100230"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP0__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100234"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP1__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100238"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP2__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10023c"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP3__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100240"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP4__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP5" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100244"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP5__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP6" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100248"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP6__bitfield"
    }
    "CPSW_PORT_P1_RX_DSCP_PRI_MAP7" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10024c"
        desc = "CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP7__bitfield"
    }
    "CPSW_PORT_P1_SA_HI" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100224"
        desc = "CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER"
        type = "CPSW_PORT_P1_SA_HI__bitfield"
    }
    "CPSW_PORT_P1_SA_LO" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100220"
        desc = "CPSW CPGMAC_SL1 SOURCE ADDRESS LOW REGISTER"
        type = "CPSW_PORT_P_SA_LO__bitfield"
    }
    "CPSW_PORT_P1_SEND_PERCENT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100228"
        desc = "CPSW PORT 1 TRANSMIT QUEUE SEND PERCENTAGES"
        type = "CPSW_PORT_P_SEND_PERCENT__bitfield"
    }
    "CPSW_PORT_P1_TS_SEQ_MTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10021c"
        desc = "CPSW PORT 1 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE."
        type = "CPSW_PORT_P1_TS_SEQ_MTYPE__bitfield"
    }
    "CPSW_PORT_P1_TX_IN_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100210"
        desc = "CPSW PORT 1 TRANSMIT FIFO CONTROL"
        type = "CPSW_PORT_P_TX_IN_CTL__bitfield"
    }
    "CPSW_PORT_P1_TX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100218"
        desc = "CPSW PORT 1 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER"
        type = "CPSW_PORT_P_TX_PRI_MAP__bitfield"
    }
    "CPSW_PORT_P2_BLK_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10030c"
        desc = "CPSW PORT 2 FIFO BLOCK USAGE COUNT (READ ONLY)"
        type = "CPSW_PORT_P2_BLK_CNT__bitfield"
    }
    "CPSW_PORT_P2_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100300"
        desc = "CPSW_3GF PORT 2 CONTROL REGISTER"
        type = "CPSW_PORT_P2_CONTROL__bitfield"
    }
    "CPSW_PORT_P2_MAX_BLKS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100308"
        desc = "CPSW PORT 2 MAXIMUM FIFO BLOCKS REGISTER"
        type = "CPSW_PORT_P2_MAX_BLKS__bitfield"
    }
    "CPSW_PORT_P2_PORT_VLAN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100314"
        desc = "CPSW PORT 2 VLAN REGISTER"
        type = "CPSW_PORT_P_PORT_VLAN__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100330"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP0__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100334"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP1__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100338"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP2__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10033c"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP3__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100340"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP4__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP5" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100344"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP5__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP6" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100348"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP6__bitfield"
    }
    "CPSW_PORT_P2_RX_DSCP_PRI_MAP7" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10034c"
        desc = "CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7"
        type = "CPSW_PORT_P_RX_DSCP_PRI_MAP7__bitfield"
    }
    "CPSW_PORT_P2_SA_HI" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100324"
        desc = "CPSW CPGMAC_SL2 SOURCE ADDRESS HIGH REGISTER"
        type = "CPSW_PORT_P2_SA_HI__bitfield"
    }
    "CPSW_PORT_P2_SA_LO" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100320"
        desc = "CPSW CPGMAC_SL2 SOURCE ADDRESS LOW REGISTER"
        type = "CPSW_PORT_P_SA_LO__bitfield"
    }
    "CPSW_PORT_P2_SEND_PERCENT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100328"
        desc = "CPSW PORT 2 TRANSMIT QUEUE SEND PERCENTAGES"
        type = "CPSW_PORT_P_SEND_PERCENT__bitfield"
    }
    "CPSW_PORT_P2_TS_SEQ_MTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10031c"
        desc = "CPSW_3GF PORT 2 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE."
        type = "CPSW_PORT_P2_TS_SEQ_MTYPE__bitfield"
    }
    "CPSW_PORT_P2_TX_IN_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100310"
        desc = "CPSW PORT 2 TRANSMIT FIFO CONTROL"
        type = "CPSW_PORT_P_TX_IN_CTL__bitfield"
    }
    "CPSW_PORT_P2_TX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100318"
        desc = "CPSW PORT 2 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER"
        type = "CPSW_PORT_P_TX_PRI_MAP__bitfield"
    }
    "CPSW_SL1_BOFFTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d94"
        desc = "CPGMAC_SL BACKOFF TEST REGISTER"
        type = "CPSW_SL_BOFFTEST__bitfield"
    }
    "CPSW_SL1_EMCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100da0"
        desc = "CPGMAC_SL EMULATION CONTROL REGISTER"
        type = "CPSW__EMCONTROL__bitfield"
    }
    "CPSW_SL1_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d80"
        desc = "CPGMAC_SL ID/VERSION REGISTER"
        type = "CPSW_SL_IDVER__bitfield"
    }
    "CPSW_SL1_MACCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d84"
        desc = "CPGMAC_SL MAC CONTROL REGISTER"
        type = "CPSW_SL_MACCONTROL__bitfield"
    }
    "CPSW_SL1_MACSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d88"
        desc = "CPGMAC_SL MAC STATUS REGISTER"
        type = "CPSW_SL_MACSTATUS__bitfield"
    }
    "CPSW_SL1_RX_MAXLEN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d90"
        desc = "CPGMAC_SL RX MAXIMUM LENGTH REGISTER"
        type = "CPSW_SL_RX_MAXLEN__bitfield"
    }
    "CPSW_SL1_RX_PAUSE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d98"
        desc = "CPGMAC_SL RECEIVE PAUSE TIMER REGISTER"
        type = "CPSW_SL_RX_PAUSE__bitfield"
    }
    "CPSW_SL1_RX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100da4"
        desc = "CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER"
        type = "CPSW_SL_RX_PRI_MAP__bitfield"
    }
    "CPSW_SL1_SOFT_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d8c"
        desc = "CPGMAC_SL SOFT RESET REGISTER"
        type = "CPSW_SL_SOFT_RESET__bitfield"
    }
    "CPSW_SL1_TX_GAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100da8"
        desc = "TRANSMIT INTER-PACKET GAP REGISTER"
        type = "CPSW_SL_TX_GAP__bitfield"
    }
    "CPSW_SL1_TX_PAUSE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100d9c"
        desc = "CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER"
        type = "CPSW_SL_TX_PAUSE__bitfield"
    }
    "CPSW_SL2_BOFFTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dd4"
        desc = "CPGMAC_SL BACKOFF TEST REGISTER"
        type = "CPSW_SL_BOFFTEST__bitfield"
    }
    "CPSW_SL2_EMCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100de0"
        desc = "CPGMAC_SL EMULATION CONTROL REGISTER"
        type = "CPSW__EMCONTROL__bitfield"
    }
    "CPSW_SL2_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dc0"
        desc = "CPGMAC_SL ID/VERSION REGISTER"
        type = "CPSW_SL_IDVER__bitfield"
    }
    "CPSW_SL2_MACCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dc4"
        desc = "CPGMAC_SL MAC CONTROL REGISTER"
        type = "CPSW_SL_MACCONTROL__bitfield"
    }
    "CPSW_SL2_MACSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dc8"
        desc = "CPGMAC_SL MAC STATUS REGISTER"
        type = "CPSW_SL_MACSTATUS__bitfield"
    }
    "CPSW_SL2_RX_MAXLEN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dd0"
        desc = "CPGMAC_SL RX MAXIMUM LENGTH REGISTER"
        type = "CPSW_SL_RX_MAXLEN__bitfield"
    }
    "CPSW_SL2_RX_PAUSE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dd8"
        desc = "CPGMAC_SL RECEIVE PAUSE TIMER REGISTER"
        type = "CPSW_SL_RX_PAUSE__bitfield"
    }
    "CPSW_SL2_RX_PRI_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100de4"
        desc = "CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER"
        type = "CPSW_SL_RX_PRI_MAP__bitfield"
    }
    "CPSW_SL2_SOFT_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100dcc"
        desc = "CPGMAC_SL SOFT RESET REGISTER"
        type = "CPSW_SL_SOFT_RESET__bitfield"
    }
    "CPSW_SL2_TX_GAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100de8"
        desc = "TRANSMIT INTER-PACKET GAP REGISTER"
        type = "CPSW_SL_TX_GAP__bitfield"
    }
    "CPSW_SL2_TX_PAUSE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100ddc"
        desc = "CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER"
        type = "CPSW_SL_TX_PAUSE__bitfield"
    }
    "CPSW_SS_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100004"
        desc = "SWITCH CONTROL REGISTER"
        type = "CPSW_SS_CONTROL__bitfield"
    }
    "CPSW_SS_DLR_LTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100030"
        desc = "DLR LTYPE REGISTER"
        type = "CPSW_SS_DLR_LTYPE__bitfield"
    }
    "CPSW_SS_FLOW_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100024"
        desc = "FLOW CONTROL"
        type = "CPSW_SS_FLOW_CONTROL__bitfield"
    }
    "CPSW_SS_GAP_THRESH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10001c"
        desc = "CPGMAC_SL SHORT GAP THRESHOLD"
        type = "CPSW_SS_GAP_THRESH__bitfield"
    }
    "CPSW_SS_ID_VER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100000"
        desc = "ID VERSION REGISTER"
        type = "CPSW_SS_ID_VER__bitfield"
    }
    "CPSW_SS_PTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100010"
        desc = "TRANSMIT PRIORITY TYPE REGISTER"
        type = "CPSW_SS_PTYPE__bitfield"
    }
    "CPSW_SS_SOFT_IDLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100014"
        desc = "SOFTWARE IDLE"
        type = "CPSW_SS_SOFT_IDLE__bitfield"
    }
    "CPSW_SS_SOFT_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100008"
        desc = "SOFT RESET REGISTER"
        type = "CPSW_SS_SOFT_RESET__bitfield"
    }
    "CPSW_SS_STAT_PORT_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10000c"
        desc = "STATISTICS PORT ENABLE REGISTER"
        type = "CPSW_SS_STAT_PORT_EN__bitfield"
    }
    "CPSW_SS_THRU_RATE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100018"
        desc = "THROUGHPUT RATE"
        type = "CPSW_SS_THRU_RATE__bitfield"
    }
    "CPSW_SS_TS_LTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10002c"
        desc = "VLAN_LTYPE1 AND VLAN_LTYPE2 REGISTER"
        type = "CPSW_SS_TS_LTYPE__bitfield"
    }
    "CPSW_SS_TX_START_WDS" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100020"
        desc = "TRANSMIT START WORDS"
        type = "CPSW_SS_TX_START_WDS__bitfield"
    }
    "CPSW_SS_VLAN_LTYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100028"
        desc = "LTYPE1 AND LTYPE 2 REGISTER"
        type = "CPSW_SS_VLAN_LTYPE__bitfield"
    }
    "CPSW_STATERAM_RX0_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101460"
    }
    "CPSW_STATERAM_RX0_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101420"
    }
    "CPSW_STATERAM_RX1_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101464"
    }
    "CPSW_STATERAM_RX1_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101424"
    }
    "CPSW_STATERAM_RX2_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101468"
    }
    "CPSW_STATERAM_RX2_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101428"
    }
    "CPSW_STATERAM_RX3_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10146c"
    }
    "CPSW_STATERAM_RX3_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10142c"
    }
    "CPSW_STATERAM_RX4_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101470"
    }
    "CPSW_STATERAM_RX4_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101430"
    }
    "CPSW_STATERAM_RX5_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101474"
    }
    "CPSW_STATERAM_RX5_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101434"
    }
    "CPSW_STATERAM_RX6_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101478"
    }
    "CPSW_STATERAM_RX6_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101438"
    }
    "CPSW_STATERAM_RX7_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10147c"
    }
    "CPSW_STATERAM_RX7_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10143c"
    }
    "CPSW_STATERAM_TX0_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101440"
    }
    "CPSW_STATERAM_TX0_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101400"
    }
    "CPSW_STATERAM_TX1_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101444"
    }
    "CPSW_STATERAM_TX1_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101404"
    }
    "CPSW_STATERAM_TX2_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101448"
    }
    "CPSW_STATERAM_TX2_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101408"
    }
    "CPSW_STATERAM_TX3_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10144c"
    }
    "CPSW_STATERAM_TX3_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10140c"
    }
    "CPSW_STATERAM_TX4_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101450"
    }
    "CPSW_STATERAM_TX4_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101410"
    }
    "CPSW_STATERAM_TX5_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101454"
    }
    "CPSW_STATERAM_TX5_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101414"
    }
    "CPSW_STATERAM_TX6_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101458"
    }
    "CPSW_STATERAM_TX6_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101418"
    }
    "CPSW_STATERAM_TX7_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10145c"
    }
    "CPSW_STATERAM_TX7_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10141c"
    }
    "CPSW_WR_C0_MISC_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10121c"
        desc = "SUBSYSTEM CORE 0 MISC INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C0_MISC_EN__bitfield"
    }
    "CPSW_WR_C0_MISC_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10124c"
        desc = "SUBSYSTEM CORE 0 MISC INTERRUPT MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C0_MISC_STAT__bitfield"
    }
    "CPSW_WR_C0_RX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101214"
        desc = "SUBSYSTEM CORE 0 RECEIVE INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C0_RX_EN__bitfield"
    }
    "CPSW_WR_C0_RX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101270"
        desc = "SUBSYSTEM CORE 0 RECEIVE INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C0_RX_IMAX__bitfield"
    }
    "CPSW_WR_C0_RX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101244"
        desc = "SUBSYSTEM CORE 0 RX INTERRUPT MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C0_RX_STAT__bitfield"
    }
    "CPSW_WR_C0_RX_THRESH_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101210"
        desc = "SUBSYSTEM CORE 0 RECEIVE THRESHOLD INT ENABLE REGISTER"
        type = "CPSW_WR_C0_RX_THRESH_EN__bitfield"
    }
    "CPSW_WR_C0_RX_THRESH_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101240"
        desc = "SUBSYSTEM CORE 0 RX THRESHOLD MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C0_RX_THRESH_STAT__bitfield"
    }
    "CPSW_WR_C0_TX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101218"
        desc = "SUBSYSTEM CORE 0 TRANSMIT INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C0_TX_EN__bitfield"
    }
    "CPSW_WR_C0_TX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101274"
        desc = "SUBSYSTEM CORE 0 TRANSMIT INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C0_TX_IMAX__bitfield"
    }
    "CPSW_WR_C0_TX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101248"
        desc = "SUBSYSTEM CORE 0 TX INTERRUPT MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C0_TX_STAT__bitfield"
    }
    "CPSW_WR_C1_MISC_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10122c"
        desc = "SUBSYSTEM CORE 1 MISC INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C1_MISC_EN__bitfield"
    }
    "CPSW_WR_C1_MISC_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10125c"
        desc = "SUBSYSTEM CORE 1 MISC MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C1_MISC_STAT__bitfield"
    }
    "CPSW_WR_C1_RX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101224"
        desc = "SUBSYSTEM CORE 1 RECEIVE INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C1_RX_EN__bitfield"
    }
    "CPSW_WR_C1_RX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101278"
        desc = "SUBSYSTEM CORE 1 RECEIVE INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C1_RX_IMAX__bitfield"
    }
    "CPSW_WR_C1_RX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101254"
        desc = "SUBSYSTEM CORE 1 RECEIVE MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C1_RX_STAT__bitfield"
    }
    "CPSW_WR_C1_RX_THRESH_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101220"
        desc = "SUBSYSTEM CORE 1 RECEIVE THRESHOLD INT ENABLE REGISTER"
        type = "CPSW_WR_C1_RX_THRESH_EN__bitfield"
    }
    "CPSW_WR_C1_RX_THRESH_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101250"
        desc = "SUBSYSTEM CORE 1 RX THRESHOLD  MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C1_RX_THRESH_STAT__bitfield"
    }
    "CPSW_WR_C1_TX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101228"
        desc = "SUBSYSTEM CORE 1 TRANSMIT INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C1_TX_EN__bitfield"
    }
    "CPSW_WR_C1_TX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10127c"
        desc = "SUBSYSTEM CORE 1 TRANSMIT INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C1_TX_IMAX__bitfield"
    }
    "CPSW_WR_C1_TX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101258"
        desc = "SUBSYSTEM CORE 1 TRANSMIT MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C1_TX_STAT__bitfield"
    }
    "CPSW_WR_C2_MISC_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10123c"
        desc = "SUBSYSTEM CORE 2 MISC INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C2_MISC_EN__bitfield"
    }
    "CPSW_WR_C2_MISC_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10126c"
        desc = "SUBSYSTEM CORE 2 MISC MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C2_MISC_STAT__bitfield"
    }
    "CPSW_WR_C2_RX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101234"
        desc = "SUBSYSTEM CORE 2 RECEIVE INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C2_RX_EN__bitfield"
    }
    "CPSW_WR_C2_RX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101280"
        desc = "SUBSYSTEM CORE 2 RECEIVE INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C2_RX_IMAX__bitfield"
    }
    "CPSW_WR_C2_RX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101264"
        desc = "SUBSYSTEM CORE 2 RECEIVE MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C2_RX_STAT__bitfield"
    }
    "CPSW_WR_C2_RX_THRESH_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101230"
        desc = "SUBSYSTEM CORE 2 RECEIVE THRESHOLD INT ENABLE REGISTER"
        type = "CPSW_WR_C2_RX_THRESH_EN__bitfield"
    }
    "CPSW_WR_C2_RX_THRESH_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101260"
        desc = "SUBSYSTEM CORE 2 RX THRESHOLD MASKED INT STATUS REGISTER"
        type = "CPSW_WR_C2_RX_THRESH_STAT__bitfield"
    }
    "CPSW_WR_C2_TX_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101238"
        desc = "SUBSYSTEM CORE 2 TRANSMIT INTERRUPT ENABLE REGISTER"
        type = "CPSW_WR_C2_TX_EN__bitfield"
    }
    "CPSW_WR_C2_TX_IMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101284"
        desc = "SUBSYSTEM CORE 2 TRANSMIT INTERRUPTS PER MILLISECOND"
        type = "CPSW_WR_C2_TX_IMAX__bitfield"
    }
    "CPSW_WR_C2_TX_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101268"
        desc = "SUBSYSTEM CORE 2 TRANSMIT MASKED INTERRUPT STATUS REGISTER"
        type = "CPSW_WR_C2_TX_STAT__bitfield"
    }
    "CPSW_WR_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101208"
        desc = "SUBSYSTEM CONTROL REGISTER"
        type = "CPSW_WR_CONTROL__bitfield"
    }
    "CPSW_WR_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101200"
        desc = "SUBSYSTEM ID VERSION REGISTER"
        type = "CPSW_WR_IDVER__bitfield"
    }
    "CPSW_WR_INT_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10120c"
        desc = "SUBSYSTEM INTERRUPT CONTROL"
        type = "CPSW_WR_INT_CONTROL__bitfield"
    }
    "CPSW_WR_RGMII_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101288"
        desc = "RGMII CONTROL SIGNAL REGISTER"
        type = "CPSW_WR_RGMII_CTL__bitfield"
    }
    "CPSW_WR_SOFT_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101204"
        desc = "SUBSYSTEM SOFT RESET REGISTER"
        type = "CPSW_WR_SOFT_RESET__bitfield"
    }
    "CPTS_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c04"
        desc = "TIME SYNC CONTROL REGISTER"
        type = "CPTS_CONTROL__bitfield"
    }
    "CPTS_EVENT_HIGH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c38"
        desc = "UPPER 32-BITS OF THE EVENT VALUE"
        type = "CPTS_EVENT_HIGH__bitfield"
    }
    "CPTS_EVENT_LOW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c34"
        desc = "LOWER 32-BITS OF THE EVENT VALUE"
        type = "CPTS_EVENT_LOW__bitfield"
    }
    "CPTS_EVENT_POP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c30"
        desc = "EVENT INTERRUPT POP REGISTER"
        type = "CPTS_EVENT_POP__bitfield"
    }
    "CPTS_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c00"
        desc = "IDENTIFICATION AND VERSION REGISTER"
        type = "CPTS_IDVER__bitfield"
    }
    "CPTS_INTSTAT_MASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c24"
        desc = "TIME SYNC INTERRUPT STATUS MASKED REGISTER"
        type = "CPTS_INTSTAT_MASKED__bitfield"
    }
    "CPTS_INTSTAT_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c20"
        desc = "TIME SYNC INTERRUPT STATUS RAW REGISTER"
        type = "CPTS_INTSTAT_RAW__bitfield"
    }
    "CPTS_INT_ENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c28"
        desc = "TIME SYNC INTERRUPT ENABLE REGISTER"
        type = "CPTS_INT_ENABLE__bitfield"
    }
    "CPTS_TS_LOAD_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c14"
        desc = "TIME STAMP LOAD ENABLE REGISTER"
        type = "CPTS_TS_LOAD_EN__bitfield"
    }
    "CPTS_TS_LOAD_VAL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c10"
        desc = "TIME STAMP LOAD VALUE REGISTER"
        type = "CPTS_TS_LOAD_VAL__bitfield"
    }
    "CPTS_TS_PUSH" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100c0c"
        desc = "TIME STAMP EVENT PUSH REGISTER"
        type = "CPTS_TS_PUSH__bitfield"
    }
    "Carrier_Sense_Errors" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100960"
    }
    "Collisions" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100948"
    }
    "DATA0_REG_PHY_DLL_LOCK_DIFF_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12138"
    }
    "DATA0_REG_PHY_DQ_OFFSET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1211c"
    }
    "DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12108"
    }
    "DATA0_REG_PHY_GATELVL_INIT_MODE_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12104"
    }
    "DATA0_REG_PHY_GATELVL_INIT_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e120fc"
    }
    "DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e120c8"
    }
    "DATA0_REG_PHY_USE_RANK0_DELAYS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12134"
    }
    "DATA0_REG_PHY_WRLVL_INIT_MODE_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e120f8"
    }
    "DATA0_REG_PHY_WRLVL_INIT_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e120f0"
    }
    "DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12120"
    }
    "DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e120dc"
    }
    "DATA1_REG_PHY_DLL_LOCK_DIFF_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121dc"
    }
    "DATA1_REG_PHY_DQ_OFFSET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121c0"
    }
    "DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121ac"
    }
    "DATA1_REG_PHY_GATELVL_INIT_MODE_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121a8"
    }
    "DATA1_REG_PHY_GATELVL_INIT_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121a0"
    }
    "DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1216c"
    }
    "DATA1_REG_PHY_USE_RANK0_DELAYS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121d8"
    }
    "DATA1_REG_PHY_WRLVL_INIT_MODE_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1219c"
    }
    "DATA1_REG_PHY_WRLVL_INIT_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12194"
    }
    "DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e121c4"
    }
    "DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e12180"
    }
    "DAYS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e00c"
        desc = "The DAYS_REG is used to program the day of the month value of the current date. Days are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. If the day value of the date is 28, DAY0 is set as 8 and DAY1 is set as 2."
        type = "DAYS_REG__bitfield"
    }
    "DCAN0_ABOTR" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc080"
    }
    "DCAN0_BTR" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc00c"
    }
    "DCAN0_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc000"
    }
    "DCAN0_ERRC" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc008"
    }
    "DCAN0_ES" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc004"
    }
    "DCAN0_IF1ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc108"
    }
    "DCAN0_IF1CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc100"
    }
    "DCAN0_IF1DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc110"
    }
    "DCAN0_IF1DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc114"
    }
    "DCAN0_IF1MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc10c"
    }
    "DCAN0_IF1MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc104"
    }
    "DCAN0_IF2ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc128"
    }
    "DCAN0_IF2CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc120"
    }
    "DCAN0_IF2DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc130"
    }
    "DCAN0_IF2DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc134"
    }
    "DCAN0_IF2MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc12c"
    }
    "DCAN0_IF2MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc124"
    }
    "DCAN0_IF3ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc148"
    }
    "DCAN0_IF3DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc150"
    }
    "DCAN0_IF3DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc154"
    }
    "DCAN0_IF3MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc14c"
    }
    "DCAN0_IF3MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc144"
    }
    "DCAN0_IF3OBS" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc140"
    }
    "DCAN0_IF3UPD12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc160"
    }
    "DCAN0_IF3UPD34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc164"
    }
    "DCAN0_IF3UPD56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc168"
    }
    "DCAN0_IF3UPD78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc16c"
    }
    "DCAN0_INT" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc010"
    }
    "DCAN0_INTMUX12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0d8"
    }
    "DCAN0_INTMUX34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0dc"
    }
    "DCAN0_INTMUX56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0e0"
    }
    "DCAN0_INTMUX78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0e4"
    }
    "DCAN0_INTPND12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0b0"
    }
    "DCAN0_INTPND34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0b4"
    }
    "DCAN0_INTPND56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0b8"
    }
    "DCAN0_INTPND78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0bc"
    }
    "DCAN0_INTPND_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0ac"
    }
    "DCAN0_MSGVAL12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0c4"
    }
    "DCAN0_MSGVAL34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0c8"
    }
    "DCAN0_MSGVAL56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0cc"
    }
    "DCAN0_MSGVAL78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0d0"
    }
    "DCAN0_MSGVAL_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0c0"
    }
    "DCAN0_NWDAT12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc09c"
    }
    "DCAN0_NWDAT34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0a0"
    }
    "DCAN0_NWDAT56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0a4"
    }
    "DCAN0_NWDAT78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc0a8"
    }
    "DCAN0_NWDAT_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc098"
    }
    "DCAN0_PARITYERR_EOI" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc004"
    }
    "DCAN0_PERR" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc01c"
    }
    "DCAN0_RIOC" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc1e4"
    }
    "DCAN0_TEST" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc014"
    }
    "DCAN0_TIOC" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc1e0"
    }
    "DCAN0_TXRQ12" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc088"
    }
    "DCAN0_TXRQ34" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc08c"
    }
    "DCAN0_TXRQ56" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc090"
    }
    "DCAN0_TXRQ78" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc094"
    }
    "DCAN0_TXRQ_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481cc084"
    }
    "DCAN1_ABOTR" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0080"
    }
    "DCAN1_BTR" {
        access = "memorymapped"
        width = "32"
        address = "0x481d000c"
    }
    "DCAN1_CTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0000"
    }
    "DCAN1_ERRC" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0008"
    }
    "DCAN1_ES" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0004"
    }
    "DCAN1_IF1ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0108"
    }
    "DCAN1_IF1CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0100"
    }
    "DCAN1_IF1DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0110"
    }
    "DCAN1_IF1DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0114"
    }
    "DCAN1_IF1MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d010c"
    }
    "DCAN1_IF1MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0104"
    }
    "DCAN1_IF2ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0128"
    }
    "DCAN1_IF2CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0120"
    }
    "DCAN1_IF2DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0130"
    }
    "DCAN1_IF2DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0134"
    }
    "DCAN1_IF2MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d012c"
    }
    "DCAN1_IF2MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0124"
    }
    "DCAN1_IF3ARB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0148"
    }
    "DCAN1_IF3DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0150"
    }
    "DCAN1_IF3DATB" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0154"
    }
    "DCAN1_IF3MCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d014c"
    }
    "DCAN1_IF3MSK" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0144"
    }
    "DCAN1_IF3OBS" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0140"
    }
    "DCAN1_IF3UPD12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0160"
    }
    "DCAN1_IF3UPD34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0164"
    }
    "DCAN1_IF3UPD56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0168"
    }
    "DCAN1_IF3UPD78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d016c"
    }
    "DCAN1_INT" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0010"
    }
    "DCAN1_INTMUX12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00d8"
    }
    "DCAN1_INTMUX34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00dc"
    }
    "DCAN1_INTMUX56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00e0"
    }
    "DCAN1_INTMUX78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00e4"
    }
    "DCAN1_INTPND12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00b0"
    }
    "DCAN1_INTPND34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00b4"
    }
    "DCAN1_INTPND56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00b8"
    }
    "DCAN1_INTPND78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00bc"
    }
    "DCAN1_INTPND_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00ac"
    }
    "DCAN1_MSGVAL12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00c4"
    }
    "DCAN1_MSGVAL34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00c8"
    }
    "DCAN1_MSGVAL56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00cc"
    }
    "DCAN1_MSGVAL78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00d0"
    }
    "DCAN1_MSGVAL_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00c0"
    }
    "DCAN1_NWDAT12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d009c"
    }
    "DCAN1_NWDAT34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00a0"
    }
    "DCAN1_NWDAT56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00a4"
    }
    "DCAN1_NWDAT78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d00a8"
    }
    "DCAN1_NWDAT_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0098"
    }
    "DCAN1_PARITYERR_EOI" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0004"
    }
    "DCAN1_PERR" {
        access = "memorymapped"
        width = "32"
        address = "0x481d001c"
    }
    "DCAN1_RIOC" {
        access = "memorymapped"
        width = "32"
        address = "0x481d01e4"
    }
    "DCAN1_TEST" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0014"
    }
    "DCAN1_TIOC" {
        access = "memorymapped"
        width = "32"
        address = "0x481d01e0"
    }
    "DCAN1_TXRQ12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0088"
    }
    "DCAN1_TXRQ34" {
        access = "memorymapped"
        width = "32"
        address = "0x481d008c"
    }
    "DCAN1_TXRQ56" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0090"
    }
    "DCAN1_TXRQ78" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0094"
    }
    "DCAN1_TXRQ_X" {
        access = "memorymapped"
        width = "32"
        address = "0x481d0084"
    }
    "DDR_PHY_CTRL_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000e4"
        desc = "A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11."
        type = "DDR_PHY_CTRL_1__bitfield"
    }
    "DDR_PHY_CTRL_1_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000e8"
        desc = "A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11."
        type = "DDR_PHY_CTRL_1__bitfield"
    }
    "DMAEMU" {
        access = "memorymapped"
        width = "32"
        address = "0x47402008"
        type = "DMAEMU__bitfield"
    }
    "DMAREVID" {
        access = "memorymapped"
        width = "32"
        address = "0x47402000"
        type = "DMAREVID__bitfield"
    }
    "DMA_SCHED_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x47403000"
        type = "DMA_SCHED_CTRL__bitfield"
    }
    "DMTIMER0_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER0_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0502c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER0_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER0_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER0_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER0_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER0_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER0_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER0_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0503c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER0_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER0_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER0_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER0_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0504c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER0_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER0_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER0_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e05048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER1_1MS_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3103c"
        desc = "This register holds the value of the first counter register capture   "
        type = "DMTIMER1_1MS_TCAR1__bitfield"
    }
    "DMTIMER1_1MS_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31044"
        desc = "This register holds the value of the second counter register capture   "
        type = "DMTIMER1_1MS_TCAR2__bitfield"
    }
    "DMTIMER1_1MS_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31024"
        desc = "This register controls optional features specific to the timer functionality   "
        type = "DMTIMER1_1MS_TCLR__bitfield"
    }
    "DMTIMER1_1MS_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31028"
        desc = "This register holds the value of the internal counter   "
        type = "DMTIMER1_1MS_TCRR__bitfield"
    }
    "DMTIMER1_1MS_TCVR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31050"
        desc = "This register is used for 1ms tick generation. The TCVR register defines whether next value loaded in TCRR will be the sub-period  value or the over-period value."
        type = "DMTIMER1_1MS_TCVR__bitfield"
    }
    "DMTIMER1_1MS_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31000"
        desc = "This register contains the IP revision code   "
        type = "DMTIMER1_1MS_TIDR__bitfield"
    }
    "DMTIMER1_1MS_TIER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3101c"
        desc = "This register controls (enable/disable) the interrupt events   "
        type = "DMTIMER1_1MS_TIER__bitfield"
    }
    "DMTIMER1_1MS_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31010"
        desc = "This register controls the various parameters of the OCP interface   "
        type = "DMTIMER1_1MS_TIOCP_CFG__bitfield"
    }
    "DMTIMER1_1MS_TISR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31018"
        desc = "The Timer Status Register is used to determine which of the timer events requested an interrupt.  "
        type = "DMTIMER1_1MS_TISR__bitfield"
    }
    "DMTIMER1_1MS_TISTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31014"
        desc = "This register provides status information about the module, excluding the interrupt status information   "
        type = "DMTIMER1_1MS_TISTAT__bitfield"
    }
    "DMTIMER1_1MS_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3102c"
        desc = "This register holds the timer's load value   "
        type = "DMTIMER1_1MS_TLDR__bitfield"
    }
    "DMTIMER1_1MS_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31038"
        desc = "This register holds the match value to be compared with the counter's value   "
        type = "DMTIMER1_1MS_TMAR__bitfield"
    }
    "DMTIMER1_1MS_TNIR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3104c"
        desc = "This register is used for 1ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added with the value of the TCVR to define whether next value loaded in TCRR will be the sub-period  value or the over-period value. "
        type = "DMTIMER1_1MS_TNIR__bitfield"
    }
    "DMTIMER1_1MS_TOCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31054"
        desc = "This register is used to mask the tick interrupt for a selected number of ticks."
        type = "DMTIMER1_1MS_TOCR__bitfield"
    }
    "DMTIMER1_1MS_TOWR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31058"
        desc = "This register holds the number of masked overflow interrupts. "
        type = "DMTIMER1_1MS_TOWR__bitfield"
    }
    "DMTIMER1_1MS_TPIR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31048"
        desc = "This register is used for 1ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added with the value of the TCVR to define whether next value loaded in TCRR will be the sub-period  value or the over-period value."
        type = "DMTIMER1_1MS_TPIR__bitfield"
    }
    "DMTIMER1_1MS_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31040"
        desc = "Timer Synchronous Interface Control Register    "
        type = "DMTIMER1_1MS_TSICR__bitfield"
    }
    "DMTIMER1_1MS_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31030"
        desc = "This register triggers a counter reload of timer by writing any value in it.   "
        type = "DMTIMER1_1MS_TTGR__bitfield"
    }
    "DMTIMER1_1MS_TWER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31020"
        desc = "This register controls (enable/disable) the wakeup feature on specific interrupt events   "
        type = "DMTIMER1_1MS_TWER__bitfield"
    }
    "DMTIMER1_1MS_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e31034"
        desc = "This register contains the write posting bits for all writ-able functional registers    "
        type = "DMTIMER1_1MS_TWPS__bitfield"
    }
    "DMTIMER2_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER2_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804002c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER2_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48040028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER2_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x48040024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER2_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x48040034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER2_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48040050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER2_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48040058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER2_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER2_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804003c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER2_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER2_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x48040010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER2_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER2_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804004c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER2_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER2_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x48040044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER2_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48040048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER3_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER3_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804202c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER3_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48042028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER3_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x48042024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER3_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x48042034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER3_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48042050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER3_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48042058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER3_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER3_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804203c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER3_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER3_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x48042010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER3_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER3_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804204c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER3_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER3_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x48042044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER3_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48042048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER4_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER4_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804402c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER4_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48044028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER4_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x48044024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER4_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x48044034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER4_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48044050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER4_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48044058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER4_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER4_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804403c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER4_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER4_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x48044010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER4_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER4_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804404c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER4_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER4_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x48044044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER4_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48044048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER5_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER5_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804602c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER5_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48046028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER5_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x48046024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER5_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x48046034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER5_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48046050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER5_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48046058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER5_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER5_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804603c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER5_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER5_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x48046010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER5_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER5_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804604c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER5_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER5_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x48046044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER5_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48046048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER6_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER6_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804802c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER6_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48048028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER6_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x48048024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER6_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x48048034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER6_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48048050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER6_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48048058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER6_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER6_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804803c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER6_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER6_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x48048010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER6_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER6_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804804c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER6_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER6_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x48048044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER6_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48048048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "DMTIMER7_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a030"
        desc = "Component interrupt request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER7_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a02c"
        desc = "Component interrupt request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "DMTIMER_IRQENABLE___bitfield"
    }
    "DMTIMER7_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a028"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER7_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a024"
        desc = "Component interrupt request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "DMTIMER_IRQSTATUS__bitfield"
    }
    "DMTIMER7_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a034"
        desc = "Wakeup-enabled events taking place when module is idle will generate an asynchronous wakeup."
        type = "DMTIMER_IRQWAKEEN__bitfield"
    }
    "DMTIMER7_TCAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a050"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic the current counter value is stored to the TCAR1 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR1 register properly:"
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER7_TCAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a058"
        desc = "When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the capture on second event is activated from the control register (TCLR), the current counter value is stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is being updated due to some capture event. In 16-bit mode the following sequence must be followed to read the TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register."
        type = "DMTIMER_TCAR__bitfield"
    }
    "DMTIMER7_TCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a038"
        desc = "When the TCM field passed from (00) to any other combination then the TCAR_IT_FLAG and the edge detection logic are cleared. The ST bit of TCLR register may be updated from the OCP interface or reset due to one-shot overflow. The OCP interface update has the priority."
        type = "DMTIMER_TCLR__bitfield"
    }
    "DMTIMER7_TCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a03c"
        desc = "The TCRR register is a 32-bit register, 16-bit addressable. The MCU can perform a 32-bit access or two 16-bit accesses to access the register . Note that since the OCP clock is completely asynchronous with the timer clock, some synchronization is done in order to make sure that the TCRR value is not read while it is being incremented. In 16-bit mode the following sequence must be followed to read the TCRR register properly: First, perform an OCP Read Transaction to Read the lower 16-bit of the TCRR register (offset = 28h). When the TCRR is read and synchronized, the lower 16-bit LSBs are driven onto the output OCP data bus and the upper 16-bit MSBs of the TCRR register are stored in a temporary register. Second, perform an OCP Read Transaction to read the upper 16-bit of the TCRR register (offset = 2Ah). During this Read, the value of the upper 16-bit MSBs that has been temporary register is forwarded onto the output OCP data bus. So, to read the value of TCRR correctly, the first OCP read access has to be to the lower 16-bit (offset = 28h), followed by OCP read access to the upper 16-bit (offset = 2Ah). As the TCRR is updated using more sources (shadow_in_tcrr, incremented value of tcrr, TLDR and 0 ), a priority order will be defined: The first priority is the OCP update. The second is the reload way (triggered through TTGR reg. or following an auto-reload overflow). The third is the one-shot overflow reset to 0. The last is the incremented value."
        type = "DMTIMER_TCRR__bitfield"
    }
    "DMTIMER7_TIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a000"
        desc = "This read only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
        type = "DMTIMER_TIDR__bitfield"
    }
    "DMTIMER7_TIOCP_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a010"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "DMTIMER_TIOCP_CFG__bitfield"
    }
    "DMTIMER7_TLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a040"
        desc = "LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh)."
        type = "DMTIMER_TLDR__bitfield"
    }
    "DMTIMER7_TMAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a04c"
        desc = "The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s current value with the value stored in the TMAR register."
        type = "DMTIMER_TMAR__bitfield"
    }
    "DMTIMER7_TSICR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a054"
        desc = "Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any wrong behavior, software can permanently reset the functional part of the module. Also in case of a wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock situation cannot happen. Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardware module configuration."
        type = "DMTIMER_TSICR__bitfield"
    }
    "DMTIMER7_TTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a044"
        desc = "The read value of this register is always FFFF FFFFh."
        type = "DMTIMER_TTGR__bitfield"
    }
    "DMTIMER7_TWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x4804a048"
        desc = "In posted mode the software must read the pending write status bits (Timer Write Posted Status register bits [4:0]) to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged."
        type = "DMTIMER_TWPS__bitfield"
    }
    "Deferred_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100944"
    }
    "ELM_ERROR_LOCATION_0_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080880"
    }
    "ELM_ERROR_LOCATION_0_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080980"
    }
    "ELM_ERROR_LOCATION_0_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a80"
    }
    "ELM_ERROR_LOCATION_0_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b80"
    }
    "ELM_ERROR_LOCATION_0_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c80"
    }
    "ELM_ERROR_LOCATION_0_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d80"
    }
    "ELM_ERROR_LOCATION_0_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e80"
    }
    "ELM_ERROR_LOCATION_0_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f80"
    }
    "ELM_ERROR_LOCATION_10_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808a8"
    }
    "ELM_ERROR_LOCATION_10_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809a8"
    }
    "ELM_ERROR_LOCATION_10_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080aa8"
    }
    "ELM_ERROR_LOCATION_10_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ba8"
    }
    "ELM_ERROR_LOCATION_10_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ca8"
    }
    "ELM_ERROR_LOCATION_10_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080da8"
    }
    "ELM_ERROR_LOCATION_10_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ea8"
    }
    "ELM_ERROR_LOCATION_10_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fa8"
    }
    "ELM_ERROR_LOCATION_11_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808ac"
    }
    "ELM_ERROR_LOCATION_11_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809ac"
    }
    "ELM_ERROR_LOCATION_11_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080aac"
    }
    "ELM_ERROR_LOCATION_11_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080bac"
    }
    "ELM_ERROR_LOCATION_11_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080cac"
    }
    "ELM_ERROR_LOCATION_11_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080dac"
    }
    "ELM_ERROR_LOCATION_11_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080eac"
    }
    "ELM_ERROR_LOCATION_11_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fac"
    }
    "ELM_ERROR_LOCATION_12_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808b0"
    }
    "ELM_ERROR_LOCATION_12_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809b0"
    }
    "ELM_ERROR_LOCATION_12_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ab0"
    }
    "ELM_ERROR_LOCATION_12_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080bb0"
    }
    "ELM_ERROR_LOCATION_12_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080cb0"
    }
    "ELM_ERROR_LOCATION_12_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080db0"
    }
    "ELM_ERROR_LOCATION_12_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080eb0"
    }
    "ELM_ERROR_LOCATION_12_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fb0"
    }
    "ELM_ERROR_LOCATION_13_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808b4"
    }
    "ELM_ERROR_LOCATION_13_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809b4"
    }
    "ELM_ERROR_LOCATION_13_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ab4"
    }
    "ELM_ERROR_LOCATION_13_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080bb4"
    }
    "ELM_ERROR_LOCATION_13_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080cb4"
    }
    "ELM_ERROR_LOCATION_13_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080db4"
    }
    "ELM_ERROR_LOCATION_13_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080eb4"
    }
    "ELM_ERROR_LOCATION_13_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fb4"
    }
    "ELM_ERROR_LOCATION_14_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808b8"
    }
    "ELM_ERROR_LOCATION_14_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809b8"
    }
    "ELM_ERROR_LOCATION_14_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ab8"
    }
    "ELM_ERROR_LOCATION_14_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080bb8"
    }
    "ELM_ERROR_LOCATION_14_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080cb8"
    }
    "ELM_ERROR_LOCATION_14_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080db8"
    }
    "ELM_ERROR_LOCATION_14_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080eb8"
    }
    "ELM_ERROR_LOCATION_14_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fb8"
    }
    "ELM_ERROR_LOCATION_15_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808bc"
    }
    "ELM_ERROR_LOCATION_15_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809bc"
    }
    "ELM_ERROR_LOCATION_15_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080abc"
    }
    "ELM_ERROR_LOCATION_15_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080bbc"
    }
    "ELM_ERROR_LOCATION_15_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080cbc"
    }
    "ELM_ERROR_LOCATION_15_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080dbc"
    }
    "ELM_ERROR_LOCATION_15_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ebc"
    }
    "ELM_ERROR_LOCATION_15_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fbc"
    }
    "ELM_ERROR_LOCATION_1_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080884"
    }
    "ELM_ERROR_LOCATION_1_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080984"
    }
    "ELM_ERROR_LOCATION_1_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a84"
    }
    "ELM_ERROR_LOCATION_1_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b84"
    }
    "ELM_ERROR_LOCATION_1_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c84"
    }
    "ELM_ERROR_LOCATION_1_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d84"
    }
    "ELM_ERROR_LOCATION_1_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e84"
    }
    "ELM_ERROR_LOCATION_1_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f84"
    }
    "ELM_ERROR_LOCATION_2_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080888"
    }
    "ELM_ERROR_LOCATION_2_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080988"
    }
    "ELM_ERROR_LOCATION_2_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a88"
    }
    "ELM_ERROR_LOCATION_2_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b88"
    }
    "ELM_ERROR_LOCATION_2_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c88"
    }
    "ELM_ERROR_LOCATION_2_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d88"
    }
    "ELM_ERROR_LOCATION_2_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e88"
    }
    "ELM_ERROR_LOCATION_2_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f88"
    }
    "ELM_ERROR_LOCATION_3_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4808088c"
    }
    "ELM_ERROR_LOCATION_3_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4808098c"
    }
    "ELM_ERROR_LOCATION_3_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a8c"
    }
    "ELM_ERROR_LOCATION_3_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b8c"
    }
    "ELM_ERROR_LOCATION_3_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c8c"
    }
    "ELM_ERROR_LOCATION_3_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d8c"
    }
    "ELM_ERROR_LOCATION_3_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e8c"
    }
    "ELM_ERROR_LOCATION_3_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f8c"
    }
    "ELM_ERROR_LOCATION_4_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080890"
    }
    "ELM_ERROR_LOCATION_4_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080990"
    }
    "ELM_ERROR_LOCATION_4_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a90"
    }
    "ELM_ERROR_LOCATION_4_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b90"
    }
    "ELM_ERROR_LOCATION_4_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c90"
    }
    "ELM_ERROR_LOCATION_4_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d90"
    }
    "ELM_ERROR_LOCATION_4_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e90"
    }
    "ELM_ERROR_LOCATION_4_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f90"
    }
    "ELM_ERROR_LOCATION_5_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080894"
    }
    "ELM_ERROR_LOCATION_5_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080994"
    }
    "ELM_ERROR_LOCATION_5_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a94"
    }
    "ELM_ERROR_LOCATION_5_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b94"
    }
    "ELM_ERROR_LOCATION_5_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c94"
    }
    "ELM_ERROR_LOCATION_5_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d94"
    }
    "ELM_ERROR_LOCATION_5_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e94"
    }
    "ELM_ERROR_LOCATION_5_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f94"
    }
    "ELM_ERROR_LOCATION_6_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080898"
    }
    "ELM_ERROR_LOCATION_6_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080998"
    }
    "ELM_ERROR_LOCATION_6_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a98"
    }
    "ELM_ERROR_LOCATION_6_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b98"
    }
    "ELM_ERROR_LOCATION_6_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c98"
    }
    "ELM_ERROR_LOCATION_6_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d98"
    }
    "ELM_ERROR_LOCATION_6_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e98"
    }
    "ELM_ERROR_LOCATION_6_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f98"
    }
    "ELM_ERROR_LOCATION_7_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4808089c"
    }
    "ELM_ERROR_LOCATION_7_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4808099c"
    }
    "ELM_ERROR_LOCATION_7_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a9c"
    }
    "ELM_ERROR_LOCATION_7_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b9c"
    }
    "ELM_ERROR_LOCATION_7_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c9c"
    }
    "ELM_ERROR_LOCATION_7_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d9c"
    }
    "ELM_ERROR_LOCATION_7_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e9c"
    }
    "ELM_ERROR_LOCATION_7_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f9c"
    }
    "ELM_ERROR_LOCATION_8_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808a0"
    }
    "ELM_ERROR_LOCATION_8_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809a0"
    }
    "ELM_ERROR_LOCATION_8_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080aa0"
    }
    "ELM_ERROR_LOCATION_8_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ba0"
    }
    "ELM_ERROR_LOCATION_8_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ca0"
    }
    "ELM_ERROR_LOCATION_8_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080da0"
    }
    "ELM_ERROR_LOCATION_8_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ea0"
    }
    "ELM_ERROR_LOCATION_8_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fa0"
    }
    "ELM_ERROR_LOCATION_9_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480808a4"
    }
    "ELM_ERROR_LOCATION_9_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480809a4"
    }
    "ELM_ERROR_LOCATION_9_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080aa4"
    }
    "ELM_ERROR_LOCATION_9_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ba4"
    }
    "ELM_ERROR_LOCATION_9_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ca4"
    }
    "ELM_ERROR_LOCATION_9_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080da4"
    }
    "ELM_ERROR_LOCATION_9_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080ea4"
    }
    "ELM_ERROR_LOCATION_9_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080fa4"
    }
    "ELM_IRQENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4808001c"
    }
    "ELM_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48080018"
    }
    "ELM_LOCATION_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48080020"
    }
    "ELM_LOCATION_STATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080800"
    }
    "ELM_LOCATION_STATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080900"
    }
    "ELM_LOCATION_STATUS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080a00"
    }
    "ELM_LOCATION_STATUS_3" {
        access = "memorymapped"
        width = "32"
        address = "0x48080b00"
    }
    "ELM_LOCATION_STATUS_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080c00"
    }
    "ELM_LOCATION_STATUS_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080d00"
    }
    "ELM_LOCATION_STATUS_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080e00"
    }
    "ELM_LOCATION_STATUS_7" {
        access = "memorymapped"
        width = "32"
        address = "0x48080f00"
    }
    "ELM_PAGE_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x48080080"
    }
    "ELM_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x48080000"
    }
    "ELM_SYNDROME_FRAGMENT_0_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080400"
    }
    "ELM_SYNDROME_FRAGMENT_0_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080440"
    }
    "ELM_SYNDROME_FRAGMENT_0_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080480"
    }
    "ELM_SYNDROME_FRAGMENT_0_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804c0"
    }
    "ELM_SYNDROME_FRAGMENT_0_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080500"
    }
    "ELM_SYNDROME_FRAGMENT_0_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080540"
    }
    "ELM_SYNDROME_FRAGMENT_0_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080580"
    }
    "ELM_SYNDROME_FRAGMENT_0_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805c0"
    }
    "ELM_SYNDROME_FRAGMENT_1_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080404"
    }
    "ELM_SYNDROME_FRAGMENT_1_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080444"
    }
    "ELM_SYNDROME_FRAGMENT_1_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080484"
    }
    "ELM_SYNDROME_FRAGMENT_1_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804c4"
    }
    "ELM_SYNDROME_FRAGMENT_1_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080504"
    }
    "ELM_SYNDROME_FRAGMENT_1_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080544"
    }
    "ELM_SYNDROME_FRAGMENT_1_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080584"
    }
    "ELM_SYNDROME_FRAGMENT_1_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805c4"
    }
    "ELM_SYNDROME_FRAGMENT_2_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080408"
    }
    "ELM_SYNDROME_FRAGMENT_2_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080448"
    }
    "ELM_SYNDROME_FRAGMENT_2_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080488"
    }
    "ELM_SYNDROME_FRAGMENT_2_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804c8"
    }
    "ELM_SYNDROME_FRAGMENT_2_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080508"
    }
    "ELM_SYNDROME_FRAGMENT_2_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080548"
    }
    "ELM_SYNDROME_FRAGMENT_2_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080588"
    }
    "ELM_SYNDROME_FRAGMENT_2_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805c8"
    }
    "ELM_SYNDROME_FRAGMENT_3_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4808040c"
    }
    "ELM_SYNDROME_FRAGMENT_3_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4808044c"
    }
    "ELM_SYNDROME_FRAGMENT_3_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4808048c"
    }
    "ELM_SYNDROME_FRAGMENT_3_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804cc"
    }
    "ELM_SYNDROME_FRAGMENT_3_4" {
        access = "memorymapped"
        width = "32"
        address = "0x4808050c"
    }
    "ELM_SYNDROME_FRAGMENT_3_5" {
        access = "memorymapped"
        width = "32"
        address = "0x4808054c"
    }
    "ELM_SYNDROME_FRAGMENT_3_6" {
        access = "memorymapped"
        width = "32"
        address = "0x4808058c"
    }
    "ELM_SYNDROME_FRAGMENT_3_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805cc"
    }
    "ELM_SYNDROME_FRAGMENT_4_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080410"
    }
    "ELM_SYNDROME_FRAGMENT_4_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080450"
    }
    "ELM_SYNDROME_FRAGMENT_4_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080490"
    }
    "ELM_SYNDROME_FRAGMENT_4_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804d0"
    }
    "ELM_SYNDROME_FRAGMENT_4_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080510"
    }
    "ELM_SYNDROME_FRAGMENT_4_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080550"
    }
    "ELM_SYNDROME_FRAGMENT_4_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080590"
    }
    "ELM_SYNDROME_FRAGMENT_4_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805d0"
    }
    "ELM_SYNDROME_FRAGMENT_5_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080414"
    }
    "ELM_SYNDROME_FRAGMENT_5_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080454"
    }
    "ELM_SYNDROME_FRAGMENT_5_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080494"
    }
    "ELM_SYNDROME_FRAGMENT_5_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804d4"
    }
    "ELM_SYNDROME_FRAGMENT_5_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080514"
    }
    "ELM_SYNDROME_FRAGMENT_5_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080554"
    }
    "ELM_SYNDROME_FRAGMENT_5_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080594"
    }
    "ELM_SYNDROME_FRAGMENT_5_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805d4"
    }
    "ELM_SYNDROME_FRAGMENT_6_0" {
        access = "memorymapped"
        width = "32"
        address = "0x48080418"
    }
    "ELM_SYNDROME_FRAGMENT_6_1" {
        access = "memorymapped"
        width = "32"
        address = "0x48080458"
    }
    "ELM_SYNDROME_FRAGMENT_6_2" {
        access = "memorymapped"
        width = "32"
        address = "0x48080498"
    }
    "ELM_SYNDROME_FRAGMENT_6_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480804d8"
    }
    "ELM_SYNDROME_FRAGMENT_6_4" {
        access = "memorymapped"
        width = "32"
        address = "0x48080518"
    }
    "ELM_SYNDROME_FRAGMENT_6_5" {
        access = "memorymapped"
        width = "32"
        address = "0x48080558"
    }
    "ELM_SYNDROME_FRAGMENT_6_6" {
        access = "memorymapped"
        width = "32"
        address = "0x48080598"
    }
    "ELM_SYNDROME_FRAGMENT_6_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480805d8"
    }
    "ELM_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48080010"
    }
    "ELM_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48080014"
    }
    "EMIF_MOD_ID_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000000"
        type = "EMIF_MOD_ID_REV__bitfield"
    }
    "Excessive_Collisions" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100954"
    }
    "FDBSC0" {
        access = "memorymapped"
        width = "32"
        address = "0x47404020"
        type = "FDBSC0__bitfield"
    }
    "FDBSC1" {
        access = "memorymapped"
        width = "32"
        address = "0x47404024"
        type = "FDBSC1__bitfield"
    }
    "FDBSC2" {
        access = "memorymapped"
        width = "32"
        address = "0x47404028"
        type = "FDBSC2__bitfield"
    }
    "FDBSC3" {
        access = "memorymapped"
        width = "32"
        address = "0x4740402c"
        type = "FDBSC3__bitfield"
    }
    "FDBSC4" {
        access = "memorymapped"
        width = "32"
        address = "0x47404030"
        type = "FDBSC4__bitfield"
    }
    "FDBSC5" {
        access = "memorymapped"
        width = "32"
        address = "0x47404034"
        type = "FDBSC5__bitfield"
    }
    "FDBSC6" {
        access = "memorymapped"
        width = "32"
        address = "0x47404038"
        type = "FDBSC6__bitfield"
    }
    "FDBSC7" {
        access = "memorymapped"
        width = "32"
        address = "0x4740403c"
        type = "FDBSC7__bitfield"
    }
    "GPIO0_CLEARDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07190"
        desc = "Writing a 1 to a bit in the GPIO_CLEARDATAOUT register clears to 0 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_CLEARDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_CLEARDATAOUT__bitfield"
    }
    "GPIO0_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07130"
        desc = "The GPIO_CTRL register controls the clock gating functionality. The DISABLEMODULE bit controls a clock gating feature at the module level. When set, this bit forces the clock gating for all internal clock paths. Module internal activity is suspended. System interface is not affected by this bit. System interface clock gating is controlled with the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG). This bit is to be used for power saving when the module is not used because of the multiplexing configuration selected at the chip level. This bit has precedence over all other internal configuration bits."
        type = "GPIO_CTRL__bitfield"
    }
    "GPIO0_DATAIN" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07138"
        desc = "The GPIO_DATAIN register is used to register the data that is read from the GPIO pins. The GPIO_DATAIN register is a read-only register. The input data is sampled synchronously with the interface clock and then captured in the GPIO_DATAIN register synchronously with the interface clock. So, after changing, GPIO pin levels are captured into this register after two interface clock cycles (the required cycles to synchronize and to write the data). When the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG) is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_DATAIN__bitfield"
    }
    "GPIO0_DATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0713c"
        desc = "The GPIO_DATAOUT register is used for setting the value of the GPIO output pins. Data is written to the GPIO_DATAOUT register synchronously with the interface clock. This register can be accessed with direct read/write operations or using the alternate Set/Clear feature. This feature enables to set or clear specific bits of this register with a single write access to the set data output register (GPIO_SETDATAOUT) or to the clear data output register (GPIO_CLEARDATAOUT) address. "
        type = "GPIO_DATAOUT__bitfield"
    }
    "GPIO0_DEBOUNCENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07150"
        desc = "The GPIO_DEBOUNCENABLE register is used to enable/disable the debouncing feature for each input line."
        type = "GPIO_DEBOUNCENABLE__bitfield"
    }
    "GPIO0_DEBOUNCINGTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07154"
        desc = "The GPIO_DEBOUNCINGTIME register controls debouncing time (the value is global for all ports). The debouncing cell is running with the debouncing clock (32 kHz), this register represents the number of the clock cycle(s) (31 s long) to be used."
        type = "GPIO_DEBOUNCINGTIME__bitfield"
    }
    "GPIO0_FALLINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0714c"
        desc = "The GPIO_FALLINGDETECT register is used to enable/disable for each input lines the falling-edge (transition 1 to 0) detection to be used for the interrupt request generation."
        type = "GPIO_FALLINGDETECT__bitfield"
    }
    "GPIO0_IRQSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0702c"
        desc = "The GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO0_IRQSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07030"
        desc = "The GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO0_IRQSTATUS_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0703c"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_0 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO0_IRQSTATUS_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07040"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_1 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO0_IRQSTATUS_RAW_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07024"
        desc = "The GPIO_IRQSTATUS_RAW_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO0_IRQSTATUS_RAW_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07028"
        desc = "The GPIO_IRQSTATUS_RAW_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO0_IRQSTATUS_SET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07034"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_0 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO0_IRQSTATUS_SET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07038"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_1 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO0_IRQWAKEN_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07044"
        desc = "Per-event wakeup enable vector (corresponding to first line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_0 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_0 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. Note: In Force-Idle mode, the module wake-up feature is totally inhibited. The wake-up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO0_IRQWAKEN_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07048"
        desc = "Per-event wakeup enable vector (corresponding to second line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_1 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_1 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO0_LEVELDETECT0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07140"
        desc = "The GPIO_LEVELDETECT0 register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT0__bitfield"
    }
    "GPIO0_LEVELDETECT1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07144"
        desc = "The GPIO_LEVELDETECT1 register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT1__bitfield"
    }
    "GPIO0_OE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07134"
        desc = "The GPIO_OE register is used to enable the pins output capabilities. At reset, all the GPIO related pins are configured as input and output capabilities are disabled. This register is not used within the module, its only function is to carry the pads configuration. When the application is using a pin as an output and does not want interrupt generation from this pin, the application can/has to properly configure the Interrupt Enable registers."
        type = "GPIO_OE__bitfield"
    }
    "GPIO0_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07000"
        desc = "The GPIO revision register is a read only register containing the revision number of the GPIO module. A write to this register has no effect, the same as the reset."
        type = "GPIO_REVISION__bitfield"
    }
    "GPIO0_RISINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07148"
        desc = "The GPIO_RISINGDETECT register is used to enable/disable for each input lines the rising-edge (transition 0 to 1) detection to be used for the interrupt request generation. "
        type = "GPIO_RISINGDETECT__bitfield"
    }
    "GPIO0_SETDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07194"
        desc = "Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_SETDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_SETDATAOUT__bitfield"
    }
    "GPIO0_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07010"
        desc = "The GPIO_SYSCONFIG register controls the various parameters of the L4 interconnect. When the AUTOIDLE bit is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_SYSCONFIG__bitfield"
    }
    "GPIO0_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e07114"
        desc = "The GPIO_SYSSTATUS register provides the reset status information about the GPIO module. It is a read-only register; a write to this register has no effect."
        type = "GPIO_SYSSTATUS__bitfield"
    }
    "GPIO1_CLEARDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c190"
        desc = "Writing a 1 to a bit in the GPIO_CLEARDATAOUT register clears to 0 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_CLEARDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_CLEARDATAOUT__bitfield"
    }
    "GPIO1_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c130"
        desc = "The GPIO_CTRL register controls the clock gating functionality. The DISABLEMODULE bit controls a clock gating feature at the module level. When set, this bit forces the clock gating for all internal clock paths. Module internal activity is suspended. System interface is not affected by this bit. System interface clock gating is controlled with the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG). This bit is to be used for power saving when the module is not used because of the multiplexing configuration selected at the chip level. This bit has precedence over all other internal configuration bits."
        type = "GPIO_CTRL__bitfield"
    }
    "GPIO1_DATAIN" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c138"
        desc = "The GPIO_DATAIN register is used to register the data that is read from the GPIO pins. The GPIO_DATAIN register is a read-only register. The input data is sampled synchronously with the interface clock and then captured in the GPIO_DATAIN register synchronously with the interface clock. So, after changing, GPIO pin levels are captured into this register after two interface clock cycles (the required cycles to synchronize and to write the data). When the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG) is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_DATAIN__bitfield"
    }
    "GPIO1_DATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c13c"
        desc = "The GPIO_DATAOUT register is used for setting the value of the GPIO output pins. Data is written to the GPIO_DATAOUT register synchronously with the interface clock. This register can be accessed with direct read/write operations or using the alternate Set/Clear feature. This feature enables to set or clear specific bits of this register with a single write access to the set data output register (GPIO_SETDATAOUT) or to the clear data output register (GPIO_CLEARDATAOUT) address. "
        type = "GPIO_DATAOUT__bitfield"
    }
    "GPIO1_DEBOUNCENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c150"
        desc = "The GPIO_DEBOUNCENABLE register is used to enable/disable the debouncing feature for each input line."
        type = "GPIO_DEBOUNCENABLE__bitfield"
    }
    "GPIO1_DEBOUNCINGTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c154"
        desc = "The GPIO_DEBOUNCINGTIME register controls debouncing time (the value is global for all ports). The debouncing cell is running with the debouncing clock (32 kHz), this register represents the number of the clock cycle(s) (31 s long) to be used."
        type = "GPIO_DEBOUNCINGTIME__bitfield"
    }
    "GPIO1_FALLINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c14c"
        desc = "The GPIO_FALLINGDETECT register is used to enable/disable for each input lines the falling-edge (transition 1 to 0) detection to be used for the interrupt request generation."
        type = "GPIO_FALLINGDETECT__bitfield"
    }
    "GPIO1_IRQSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c02c"
        desc = "The GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO1_IRQSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c030"
        desc = "The GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO1_IRQSTATUS_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c03c"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_0 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO1_IRQSTATUS_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c040"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_1 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO1_IRQSTATUS_RAW_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c024"
        desc = "The GPIO_IRQSTATUS_RAW_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO1_IRQSTATUS_RAW_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c028"
        desc = "The GPIO_IRQSTATUS_RAW_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO1_IRQSTATUS_SET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c034"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_0 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO1_IRQSTATUS_SET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c038"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_1 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO1_IRQWAKEN_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c044"
        desc = "Per-event wakeup enable vector (corresponding to first line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_0 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_0 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. Note: In Force-Idle mode, the module wake-up feature is totally inhibited. The wake-up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO1_IRQWAKEN_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c048"
        desc = "Per-event wakeup enable vector (corresponding to second line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_1 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_1 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO1_LEVELDETECT0" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c140"
        desc = "The GPIO_LEVELDETECT0 register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT0__bitfield"
    }
    "GPIO1_LEVELDETECT1" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c144"
        desc = "The GPIO_LEVELDETECT1 register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT1__bitfield"
    }
    "GPIO1_OE" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c134"
        desc = "The GPIO_OE register is used to enable the pins output capabilities. At reset, all the GPIO related pins are configured as input and output capabilities are disabled. This register is not used within the module, its only function is to carry the pads configuration. When the application is using a pin as an output and does not want interrupt generation from this pin, the application can/has to properly configure the Interrupt Enable registers."
        type = "GPIO_OE__bitfield"
    }
    "GPIO1_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c000"
        desc = "The GPIO revision register is a read only register containing the revision number of the GPIO module. A write to this register has no effect, the same as the reset."
        type = "GPIO_REVISION__bitfield"
    }
    "GPIO1_RISINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c148"
        desc = "The GPIO_RISINGDETECT register is used to enable/disable for each input lines the rising-edge (transition 0 to 1) detection to be used for the interrupt request generation. "
        type = "GPIO_RISINGDETECT__bitfield"
    }
    "GPIO1_SETDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c194"
        desc = "Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_SETDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_SETDATAOUT__bitfield"
    }
    "GPIO1_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c010"
        desc = "The GPIO_SYSCONFIG register controls the various parameters of the L4 interconnect. When the AUTOIDLE bit is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_SYSCONFIG__bitfield"
    }
    "GPIO1_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4804c114"
        desc = "The GPIO_SYSSTATUS register provides the reset status information about the GPIO module. It is a read-only register; a write to this register has no effect."
        type = "GPIO_SYSSTATUS__bitfield"
    }
    "GPIO2_CLEARDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac190"
        desc = "Writing a 1 to a bit in the GPIO_CLEARDATAOUT register clears to 0 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_CLEARDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_CLEARDATAOUT__bitfield"
    }
    "GPIO2_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac130"
        desc = "The GPIO_CTRL register controls the clock gating functionality. The DISABLEMODULE bit controls a clock gating feature at the module level. When set, this bit forces the clock gating for all internal clock paths. Module internal activity is suspended. System interface is not affected by this bit. System interface clock gating is controlled with the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG). This bit is to be used for power saving when the module is not used because of the multiplexing configuration selected at the chip level. This bit has precedence over all other internal configuration bits."
        type = "GPIO_CTRL__bitfield"
    }
    "GPIO2_DATAIN" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac138"
        desc = "The GPIO_DATAIN register is used to register the data that is read from the GPIO pins. The GPIO_DATAIN register is a read-only register. The input data is sampled synchronously with the interface clock and then captured in the GPIO_DATAIN register synchronously with the interface clock. So, after changing, GPIO pin levels are captured into this register after two interface clock cycles (the required cycles to synchronize and to write the data). When the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG) is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_DATAIN__bitfield"
    }
    "GPIO2_DATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac13c"
        desc = "The GPIO_DATAOUT register is used for setting the value of the GPIO output pins. Data is written to the GPIO_DATAOUT register synchronously with the interface clock. This register can be accessed with direct read/write operations or using the alternate Set/Clear feature. This feature enables to set or clear specific bits of this register with a single write access to the set data output register (GPIO_SETDATAOUT) or to the clear data output register (GPIO_CLEARDATAOUT) address. "
        type = "GPIO_DATAOUT__bitfield"
    }
    "GPIO2_DEBOUNCENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac150"
        desc = "The GPIO_DEBOUNCENABLE register is used to enable/disable the debouncing feature for each input line."
        type = "GPIO_DEBOUNCENABLE__bitfield"
    }
    "GPIO2_DEBOUNCINGTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac154"
        desc = "The GPIO_DEBOUNCINGTIME register controls debouncing time (the value is global for all ports). The debouncing cell is running with the debouncing clock (32 kHz), this register represents the number of the clock cycle(s) (31 s long) to be used."
        type = "GPIO_DEBOUNCINGTIME__bitfield"
    }
    "GPIO2_FALLINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac14c"
        desc = "The GPIO_FALLINGDETECT register is used to enable/disable for each input lines the falling-edge (transition 1 to 0) detection to be used for the interrupt request generation."
        type = "GPIO_FALLINGDETECT__bitfield"
    }
    "GPIO2_IRQSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac02c"
        desc = "The GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO2_IRQSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac030"
        desc = "The GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO2_IRQSTATUS_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac03c"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_0 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO2_IRQSTATUS_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac040"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_1 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO2_IRQSTATUS_RAW_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac024"
        desc = "The GPIO_IRQSTATUS_RAW_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO2_IRQSTATUS_RAW_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac028"
        desc = "The GPIO_IRQSTATUS_RAW_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO2_IRQSTATUS_SET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac034"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_0 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO2_IRQSTATUS_SET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac038"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_1 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO2_IRQWAKEN_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac044"
        desc = "Per-event wakeup enable vector (corresponding to first line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_0 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_0 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. Note: In Force-Idle mode, the module wake-up feature is totally inhibited. The wake-up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO2_IRQWAKEN_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac048"
        desc = "Per-event wakeup enable vector (corresponding to second line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_1 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_1 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO2_LEVELDETECT0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac140"
        desc = "The GPIO_LEVELDETECT0 register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT0__bitfield"
    }
    "GPIO2_LEVELDETECT1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac144"
        desc = "The GPIO_LEVELDETECT1 register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT1__bitfield"
    }
    "GPIO2_OE" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac134"
        desc = "The GPIO_OE register is used to enable the pins output capabilities. At reset, all the GPIO related pins are configured as input and output capabilities are disabled. This register is not used within the module, its only function is to carry the pads configuration. When the application is using a pin as an output and does not want interrupt generation from this pin, the application can/has to properly configure the Interrupt Enable registers."
        type = "GPIO_OE__bitfield"
    }
    "GPIO2_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac000"
        desc = "The GPIO revision register is a read only register containing the revision number of the GPIO module. A write to this register has no effect, the same as the reset."
        type = "GPIO_REVISION__bitfield"
    }
    "GPIO2_RISINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac148"
        desc = "The GPIO_RISINGDETECT register is used to enable/disable for each input lines the rising-edge (transition 0 to 1) detection to be used for the interrupt request generation. "
        type = "GPIO_RISINGDETECT__bitfield"
    }
    "GPIO2_SETDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac194"
        desc = "Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_SETDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_SETDATAOUT__bitfield"
    }
    "GPIO2_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac010"
        desc = "The GPIO_SYSCONFIG register controls the various parameters of the L4 interconnect. When the AUTOIDLE bit is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_SYSCONFIG__bitfield"
    }
    "GPIO2_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x481ac114"
        desc = "The GPIO_SYSSTATUS register provides the reset status information about the GPIO module. It is a read-only register; a write to this register has no effect."
        type = "GPIO_SYSSTATUS__bitfield"
    }
    "GPIO3_CLEARDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae190"
        desc = "Writing a 1 to a bit in the GPIO_CLEARDATAOUT register clears to 0 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_CLEARDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_CLEARDATAOUT__bitfield"
    }
    "GPIO3_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae130"
        desc = "The GPIO_CTRL register controls the clock gating functionality. The DISABLEMODULE bit controls a clock gating feature at the module level. When set, this bit forces the clock gating for all internal clock paths. Module internal activity is suspended. System interface is not affected by this bit. System interface clock gating is controlled with the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG). This bit is to be used for power saving when the module is not used because of the multiplexing configuration selected at the chip level. This bit has precedence over all other internal configuration bits."
        type = "GPIO_CTRL__bitfield"
    }
    "GPIO3_DATAIN" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae138"
        desc = "The GPIO_DATAIN register is used to register the data that is read from the GPIO pins. The GPIO_DATAIN register is a read-only register. The input data is sampled synchronously with the interface clock and then captured in the GPIO_DATAIN register synchronously with the interface clock. So, after changing, GPIO pin levels are captured into this register after two interface clock cycles (the required cycles to synchronize and to write the data). When the AUTOIDLE bit in the system configuration register (GPIO_SYSCONFIG) is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_DATAIN__bitfield"
    }
    "GPIO3_DATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae13c"
        desc = "The GPIO_DATAOUT register is used for setting the value of the GPIO output pins. Data is written to the GPIO_DATAOUT register synchronously with the interface clock. This register can be accessed with direct read/write operations or using the alternate Set/Clear feature. This feature enables to set or clear specific bits of this register with a single write access to the set data output register (GPIO_SETDATAOUT) or to the clear data output register (GPIO_CLEARDATAOUT) address. "
        type = "GPIO_DATAOUT__bitfield"
    }
    "GPIO3_DEBOUNCENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae150"
        desc = "The GPIO_DEBOUNCENABLE register is used to enable/disable the debouncing feature for each input line."
        type = "GPIO_DEBOUNCENABLE__bitfield"
    }
    "GPIO3_DEBOUNCINGTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae154"
        desc = "The GPIO_DEBOUNCINGTIME register controls debouncing time (the value is global for all ports). The debouncing cell is running with the debouncing clock (32 kHz), this register represents the number of the clock cycle(s) (31 s long) to be used."
        type = "GPIO_DEBOUNCINGTIME__bitfield"
    }
    "GPIO3_FALLINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae14c"
        desc = "The GPIO_FALLINGDETECT register is used to enable/disable for each input lines the falling-edge (transition 1 to 0) detection to be used for the interrupt request generation."
        type = "GPIO_FALLINGDETECT__bitfield"
    }
    "GPIO3_IRQSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae02c"
        desc = "The GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO3_IRQSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae030"
        desc = "The GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit clears the bit to 0, that is, clears the IRQ. Writing a 0 has no effect, that is, the register value is not modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO3_IRQSTATUS_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae03c"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_0 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO3_IRQSTATUS_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae040"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_CLR_1 register clear a specific interrupt event. Writing a 1 to a bit disables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO3_IRQSTATUS_RAW_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae024"
        desc = "The GPIO_IRQSTATUS_RAW_0 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO3_IRQSTATUS_RAW_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae028"
        desc = "The GPIO_IRQSTATUS_RAW_1 register provides core status information for the interrupt handling, showing all active events (enabled and not enabled). The fields are read-write. Writing a 1 to a bit sets it to 1, that is, triggers the IRQ (mostly for debug). Writing a 0 has no effect, that is, the register value is not be modified. Only enabled, active events trigger an actual interrupt request on the IRQ output line."
        type = "GPIO_IRQSTATUS___bitfield"
    }
    "GPIO3_IRQSTATUS_SET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae034"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_0 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO3_IRQSTATUS_SET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae038"
        desc = "All 1-bit fields in the GPIO_IRQSTATUS_SET_1 register enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the register value is not modified."
        type = "GPIO_IRQSTATUS____bitfield"
    }
    "GPIO3_IRQWAKEN_0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae044"
        desc = "Per-event wakeup enable vector (corresponding to first line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_0 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_0 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. Note: In Force-Idle mode, the module wake-up feature is totally inhibited. The wake-up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO3_IRQWAKEN_1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae048"
        desc = "Per-event wakeup enable vector (corresponding to second line of interrupt). Every 1-bit field in the GPIO_IRQWAKEN_1 register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line). This register allows the user to mask the expected transition on input GPIO from generating a wakeup request. The GPIO_IRQWAKEN_1 is programmed synchronously with the interface clock before any Idle mode request coming from the host processor. "
        type = "GPIO_IRQWAKEN___bitfield"
    }
    "GPIO3_LEVELDETECT0" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae140"
        desc = "The GPIO_LEVELDETECT0 register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT0__bitfield"
    }
    "GPIO3_LEVELDETECT1" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae144"
        desc = "The GPIO_LEVELDETECT1 register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation. Enabling at the same time high-level detection and low-level detection for one given pin makes a constant interrupt generator. "
        type = "GPIO_LEVELDETECT1__bitfield"
    }
    "GPIO3_OE" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae134"
        desc = "The GPIO_OE register is used to enable the pins output capabilities. At reset, all the GPIO related pins are configured as input and output capabilities are disabled. This register is not used within the module, its only function is to carry the pads configuration. When the application is using a pin as an output and does not want interrupt generation from this pin, the application can/has to properly configure the Interrupt Enable registers."
        type = "GPIO_OE__bitfield"
    }
    "GPIO3_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae000"
        desc = "The GPIO revision register is a read only register containing the revision number of the GPIO module. A write to this register has no effect, the same as the reset."
        type = "GPIO_REVISION__bitfield"
    }
    "GPIO3_RISINGDETECT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae148"
        desc = "The GPIO_RISINGDETECT register is used to enable/disable for each input lines the rising-edge (transition 0 to 1) detection to be used for the interrupt request generation. "
        type = "GPIO_RISINGDETECT__bitfield"
    }
    "GPIO3_SETDATAOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae194"
        desc = "Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_SETDATAOUT register returns the value of the data output register (GPIO_DATAOUT). "
        type = "GPIO_SETDATAOUT__bitfield"
    }
    "GPIO3_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae010"
        desc = "The GPIO_SYSCONFIG register controls the various parameters of the L4 interconnect. When the AUTOIDLE bit is set, the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism. When the AUTOIDLE bit is not set, the GPIO_DATAIN read command has a 2 OCP cycle latency."
        type = "GPIO_SYSCONFIG__bitfield"
    }
    "GPIO3_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x481ae114"
        desc = "The GPIO_SYSSTATUS register provides the reset status information about the GPIO module. It is a read-only register; a write to this register has no effect."
        type = "GPIO_SYSSTATUS__bitfield"
    }
    "GPMC_BCH_RESULT0_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000240"
    }
    "GPMC_BCH_RESULT0_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000250"
    }
    "GPMC_BCH_RESULT0_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000260"
    }
    "GPMC_BCH_RESULT0_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000270"
    }
    "GPMC_BCH_RESULT0_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000280"
    }
    "GPMC_BCH_RESULT0_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000290"
    }
    "GPMC_BCH_RESULT0_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500002a0"
    }
    "GPMC_BCH_RESULT1_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000244"
    }
    "GPMC_BCH_RESULT1_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000254"
    }
    "GPMC_BCH_RESULT1_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000264"
    }
    "GPMC_BCH_RESULT1_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000274"
    }
    "GPMC_BCH_RESULT1_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000284"
    }
    "GPMC_BCH_RESULT1_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000294"
    }
    "GPMC_BCH_RESULT1_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500002a4"
    }
    "GPMC_BCH_RESULT2_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000248"
    }
    "GPMC_BCH_RESULT2_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000258"
    }
    "GPMC_BCH_RESULT2_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000268"
    }
    "GPMC_BCH_RESULT2_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000278"
    }
    "GPMC_BCH_RESULT2_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000288"
    }
    "GPMC_BCH_RESULT2_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000298"
    }
    "GPMC_BCH_RESULT2_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500002a8"
    }
    "GPMC_BCH_RESULT3_0" {
        access = "memorymapped"
        width = "32"
        address = "0x5000024c"
    }
    "GPMC_BCH_RESULT3_1" {
        access = "memorymapped"
        width = "32"
        address = "0x5000025c"
    }
    "GPMC_BCH_RESULT3_2" {
        access = "memorymapped"
        width = "32"
        address = "0x5000026c"
    }
    "GPMC_BCH_RESULT3_3" {
        access = "memorymapped"
        width = "32"
        address = "0x5000027c"
    }
    "GPMC_BCH_RESULT3_4" {
        access = "memorymapped"
        width = "32"
        address = "0x5000028c"
    }
    "GPMC_BCH_RESULT3_5" {
        access = "memorymapped"
        width = "32"
        address = "0x5000029c"
    }
    "GPMC_BCH_RESULT3_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500002ac"
    }
    "GPMC_BCH_RESULT4_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000300"
    }
    "GPMC_BCH_RESULT4_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000310"
    }
    "GPMC_BCH_RESULT4_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000320"
    }
    "GPMC_BCH_RESULT4_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000330"
    }
    "GPMC_BCH_RESULT4_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000340"
    }
    "GPMC_BCH_RESULT4_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000350"
    }
    "GPMC_BCH_RESULT4_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000360"
    }
    "GPMC_BCH_RESULT5_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000304"
    }
    "GPMC_BCH_RESULT5_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000314"
    }
    "GPMC_BCH_RESULT5_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000324"
    }
    "GPMC_BCH_RESULT5_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000334"
    }
    "GPMC_BCH_RESULT5_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000344"
    }
    "GPMC_BCH_RESULT5_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000354"
    }
    "GPMC_BCH_RESULT5_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000364"
    }
    "GPMC_BCH_RESULT6_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000308"
    }
    "GPMC_BCH_RESULT6_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000318"
    }
    "GPMC_BCH_RESULT6_2" {
        access = "memorymapped"
        width = "32"
        address = "0x50000328"
    }
    "GPMC_BCH_RESULT6_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000338"
    }
    "GPMC_BCH_RESULT6_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000348"
    }
    "GPMC_BCH_RESULT6_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000358"
    }
    "GPMC_BCH_RESULT6_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000368"
    }
    "GPMC_BCH_SWDATA" {
        access = "memorymapped"
        width = "32"
        address = "0x500002d0"
    }
    "GPMC_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x50000050"
    }
    "GPMC_CONFIG1_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000060"
    }
    "GPMC_CONFIG1_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000090"
    }
    "GPMC_CONFIG1_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000c0"
    }
    "GPMC_CONFIG1_3" {
        access = "memorymapped"
        width = "32"
        address = "0x500000f0"
    }
    "GPMC_CONFIG1_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000120"
    }
    "GPMC_CONFIG1_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000150"
    }
    "GPMC_CONFIG1_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000180"
    }
    "GPMC_CONFIG2_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000064"
    }
    "GPMC_CONFIG2_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000094"
    }
    "GPMC_CONFIG2_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000c4"
    }
    "GPMC_CONFIG2_3" {
        access = "memorymapped"
        width = "32"
        address = "0x500000f4"
    }
    "GPMC_CONFIG2_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000124"
    }
    "GPMC_CONFIG2_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000154"
    }
    "GPMC_CONFIG2_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000184"
    }
    "GPMC_CONFIG3_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000068"
    }
    "GPMC_CONFIG3_1" {
        access = "memorymapped"
        width = "32"
        address = "0x50000098"
    }
    "GPMC_CONFIG3_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000c8"
    }
    "GPMC_CONFIG3_3" {
        access = "memorymapped"
        width = "32"
        address = "0x500000f8"
    }
    "GPMC_CONFIG3_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000128"
    }
    "GPMC_CONFIG3_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000158"
    }
    "GPMC_CONFIG3_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000188"
    }
    "GPMC_CONFIG4_0" {
        access = "memorymapped"
        width = "32"
        address = "0x5000006c"
    }
    "GPMC_CONFIG4_1" {
        access = "memorymapped"
        width = "32"
        address = "0x5000009c"
    }
    "GPMC_CONFIG4_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000cc"
    }
    "GPMC_CONFIG4_3" {
        access = "memorymapped"
        width = "32"
        address = "0x500000fc"
    }
    "GPMC_CONFIG4_4" {
        access = "memorymapped"
        width = "32"
        address = "0x5000012c"
    }
    "GPMC_CONFIG4_5" {
        access = "memorymapped"
        width = "32"
        address = "0x5000015c"
    }
    "GPMC_CONFIG4_6" {
        access = "memorymapped"
        width = "32"
        address = "0x5000018c"
    }
    "GPMC_CONFIG5_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000070"
    }
    "GPMC_CONFIG5_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000a0"
    }
    "GPMC_CONFIG5_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000d0"
    }
    "GPMC_CONFIG5_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000100"
    }
    "GPMC_CONFIG5_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000130"
    }
    "GPMC_CONFIG5_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000160"
    }
    "GPMC_CONFIG5_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000190"
    }
    "GPMC_CONFIG6_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000074"
    }
    "GPMC_CONFIG6_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000a4"
    }
    "GPMC_CONFIG6_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000d4"
    }
    "GPMC_CONFIG6_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000104"
    }
    "GPMC_CONFIG6_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000134"
    }
    "GPMC_CONFIG6_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000164"
    }
    "GPMC_CONFIG6_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000194"
    }
    "GPMC_CONFIG7_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000078"
    }
    "GPMC_CONFIG7_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000a8"
    }
    "GPMC_CONFIG7_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000d8"
    }
    "GPMC_CONFIG7_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000108"
    }
    "GPMC_CONFIG7_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000138"
    }
    "GPMC_CONFIG7_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000168"
    }
    "GPMC_CONFIG7_6" {
        access = "memorymapped"
        width = "32"
        address = "0x50000198"
    }
    "GPMC_ECC1_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000200"
    }
    "GPMC_ECC2_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000204"
    }
    "GPMC_ECC3_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000208"
    }
    "GPMC_ECC4_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x5000020c"
    }
    "GPMC_ECC5_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000210"
    }
    "GPMC_ECC6_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000214"
    }
    "GPMC_ECC7_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000218"
    }
    "GPMC_ECC8_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x5000021c"
    }
    "GPMC_ECC9_RESULT" {
        access = "memorymapped"
        width = "32"
        address = "0x50000220"
    }
    "GPMC_ECC_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x500001f4"
    }
    "GPMC_ECC_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x500001f8"
    }
    "GPMC_ECC_SIZE_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x500001fc"
    }
    "GPMC_ERR_ADDRESS" {
        access = "memorymapped"
        width = "32"
        address = "0x50000044"
    }
    "GPMC_ERR_TYPE" {
        access = "memorymapped"
        width = "32"
        address = "0x50000048"
    }
    "GPMC_IRQENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x5000001c"
    }
    "GPMC_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x50000018"
    }
    "GPMC_NAND_ADDRESS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000080"
    }
    "GPMC_NAND_ADDRESS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000b0"
    }
    "GPMC_NAND_ADDRESS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000e0"
    }
    "GPMC_NAND_ADDRESS_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000110"
    }
    "GPMC_NAND_ADDRESS_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000140"
    }
    "GPMC_NAND_ADDRESS_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000170"
    }
    "GPMC_NAND_ADDRESS_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500001a0"
    }
    "GPMC_NAND_COMMAND_0" {
        access = "memorymapped"
        width = "32"
        address = "0x5000007c"
    }
    "GPMC_NAND_COMMAND_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000ac"
    }
    "GPMC_NAND_COMMAND_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000dc"
    }
    "GPMC_NAND_COMMAND_3" {
        access = "memorymapped"
        width = "32"
        address = "0x5000010c"
    }
    "GPMC_NAND_COMMAND_4" {
        access = "memorymapped"
        width = "32"
        address = "0x5000013c"
    }
    "GPMC_NAND_COMMAND_5" {
        access = "memorymapped"
        width = "32"
        address = "0x5000016c"
    }
    "GPMC_NAND_COMMAND_6" {
        access = "memorymapped"
        width = "32"
        address = "0x5000019c"
    }
    "GPMC_NAND_DATA_0" {
        access = "memorymapped"
        width = "32"
        address = "0x50000084"
    }
    "GPMC_NAND_DATA_1" {
        access = "memorymapped"
        width = "32"
        address = "0x500000b4"
    }
    "GPMC_NAND_DATA_2" {
        access = "memorymapped"
        width = "32"
        address = "0x500000e4"
    }
    "GPMC_NAND_DATA_3" {
        access = "memorymapped"
        width = "32"
        address = "0x50000114"
    }
    "GPMC_NAND_DATA_4" {
        access = "memorymapped"
        width = "32"
        address = "0x50000144"
    }
    "GPMC_NAND_DATA_5" {
        access = "memorymapped"
        width = "32"
        address = "0x50000174"
    }
    "GPMC_NAND_DATA_6" {
        access = "memorymapped"
        width = "32"
        address = "0x500001a4"
    }
    "GPMC_PREFETCH_CONFIG1" {
        access = "memorymapped"
        width = "32"
        address = "0x500001e0"
    }
    "GPMC_PREFETCH_CONFIG2" {
        access = "memorymapped"
        width = "32"
        address = "0x500001e4"
    }
    "GPMC_PREFETCH_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x500001ec"
    }
    "GPMC_PREFETCH_STATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x500001f0"
    }
    "GPMC_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x50000000"
    }
    "GPMC_STATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x50000054"
    }
    "GPMC_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x50000010"
    }
    "GPMC_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x50000014"
    }
    "GPMC_TIMEOUT_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x50000040"
    }
    "Good_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100900"
    }
    "Good_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100934"
    }
    "HOURS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e008"
        desc = "The HOURS_REG is used to program the hours value of the current time. Hours are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. In 24Hr time mode if you want to set the hour as 18, then HOUR0 is set as 8 and HOUR1 is set as 1."
        type = "HOURS_REG__bitfield"
    }
    "I2C0_ACTOA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0d0"
    }
    "I2C0_BUF" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b094"
    }
    "I2C0_BUFSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0c0"
    }
    "I2C0_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b098"
    }
    "I2C0_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0a4"
    }
    "I2C0_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b09c"
    }
    "I2C0_DMARXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b040"
    }
    "I2C0_DMARXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b038"
    }
    "I2C0_DMARXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b048"
    }
    "I2C0_DMATXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b044"
    }
    "I2C0_DMATXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b03c"
    }
    "I2C0_DMATXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b04c"
    }
    "I2C0_EOI" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b020"
    }
    "I2C0_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b030"
    }
    "I2C0_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b02c"
    }
    "I2C0_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b028"
    }
    "I2C0_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b024"
    }
    "I2C0_OA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0a8"
    }
    "I2C0_OA1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0c4"
    }
    "I2C0_OA2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0c8"
    }
    "I2C0_OA3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0cc"
    }
    "I2C0_PSC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0b0"
    }
    "I2C0_REVNB_HI" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b004"
    }
    "I2C0_REVNB_LO" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b000"
    }
    "I2C0_SA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0ac"
    }
    "I2C0_SBLOCK" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0d4"
    }
    "I2C0_SCLH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0b8"
    }
    "I2C0_SCLL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0b4"
    }
    "I2C0_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b010"
    }
    "I2C0_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b090"
    }
    "I2C0_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b0bc"
    }
    "I2C0_WE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0b034"
    }
    "I2C1_ACTOA" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0d0"
    }
    "I2C1_BUF" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a094"
    }
    "I2C1_BUFSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0c0"
    }
    "I2C1_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a098"
    }
    "I2C1_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0a4"
    }
    "I2C1_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a09c"
    }
    "I2C1_DMARXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a040"
    }
    "I2C1_DMARXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a038"
    }
    "I2C1_DMARXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a048"
    }
    "I2C1_DMATXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a044"
    }
    "I2C1_DMATXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a03c"
    }
    "I2C1_DMATXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a04c"
    }
    "I2C1_EOI" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a020"
    }
    "I2C1_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a030"
    }
    "I2C1_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a02c"
    }
    "I2C1_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a028"
    }
    "I2C1_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a024"
    }
    "I2C1_OA" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0a8"
    }
    "I2C1_OA1" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0c4"
    }
    "I2C1_OA2" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0c8"
    }
    "I2C1_OA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0cc"
    }
    "I2C1_PSC" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0b0"
    }
    "I2C1_REVNB_HI" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a004"
    }
    "I2C1_REVNB_LO" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a000"
    }
    "I2C1_SA" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0ac"
    }
    "I2C1_SBLOCK" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0d4"
    }
    "I2C1_SCLH" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0b8"
    }
    "I2C1_SCLL" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0b4"
    }
    "I2C1_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a010"
    }
    "I2C1_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a090"
    }
    "I2C1_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a0bc"
    }
    "I2C1_WE" {
        access = "memorymapped"
        width = "32"
        address = "0x4802a034"
    }
    "I2C2_ACTOA" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0d0"
    }
    "I2C2_BUF" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c094"
    }
    "I2C2_BUFSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0c0"
    }
    "I2C2_CNT" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c098"
    }
    "I2C2_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0a4"
    }
    "I2C2_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c09c"
    }
    "I2C2_DMARXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c040"
    }
    "I2C2_DMARXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c038"
    }
    "I2C2_DMARXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c048"
    }
    "I2C2_DMATXENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c044"
    }
    "I2C2_DMATXENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c03c"
    }
    "I2C2_DMATXWAKE_EN" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c04c"
    }
    "I2C2_EOI" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c020"
    }
    "I2C2_IRQENABLE_CLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c030"
    }
    "I2C2_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c02c"
    }
    "I2C2_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c028"
    }
    "I2C2_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c024"
    }
    "I2C2_OA" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0a8"
    }
    "I2C2_OA1" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0c4"
    }
    "I2C2_OA2" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0c8"
    }
    "I2C2_OA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0cc"
    }
    "I2C2_PSC" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0b0"
    }
    "I2C2_REVNB_HI" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c004"
    }
    "I2C2_REVNB_LO" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c000"
    }
    "I2C2_SA" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0ac"
    }
    "I2C2_SBLOCK" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0d4"
    }
    "I2C2_SCLH" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0b8"
    }
    "I2C2_SCLL" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0b4"
    }
    "I2C2_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c010"
    }
    "I2C2_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c090"
    }
    "I2C2_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c0bc"
    }
    "I2C2_WE" {
        access = "memorymapped"
        width = "32"
        address = "0x4819c034"
    }
    "INTC_CONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x48200048"
        desc = "This register contains the new interrupt agreement bits  "
        type = "INTC_CONTROL__bitfield"
    }
    "INTC_FIQ_PRIORITY" {
        access = "memorymapped"
        width = "32"
        address = "0x48200064"
        desc = "This register supplies the currently active FIQ priority level"
        type = "INTC_FIQ_PRIORITY__bitfield"
    }
    "INTC_IDLE" {
        access = "memorymapped"
        width = "32"
        address = "0x48200050"
        desc = "This register controls the clock auto-idle for the functional clock and the input synchronisers  "
        type = "INTC_IDLE__bitfield"
    }
    "INTC_ILR0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200100"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48200104"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR10" {
        access = "memorymapped"
        width = "32"
        address = "0x48200128"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR100" {
        access = "memorymapped"
        width = "32"
        address = "0x48200290"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR101" {
        access = "memorymapped"
        width = "32"
        address = "0x48200294"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR102" {
        access = "memorymapped"
        width = "32"
        address = "0x48200298"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR103" {
        access = "memorymapped"
        width = "32"
        address = "0x4820029c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR104" {
        access = "memorymapped"
        width = "32"
        address = "0x482002a0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR105" {
        access = "memorymapped"
        width = "32"
        address = "0x482002a4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR106" {
        access = "memorymapped"
        width = "32"
        address = "0x482002a8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR107" {
        access = "memorymapped"
        width = "32"
        address = "0x482002ac"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR108" {
        access = "memorymapped"
        width = "32"
        address = "0x482002b0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR109" {
        access = "memorymapped"
        width = "32"
        address = "0x482002b4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR11" {
        access = "memorymapped"
        width = "32"
        address = "0x4820012c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR110" {
        access = "memorymapped"
        width = "32"
        address = "0x482002b8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR111" {
        access = "memorymapped"
        width = "32"
        address = "0x482002bc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR112" {
        access = "memorymapped"
        width = "32"
        address = "0x482002c0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR113" {
        access = "memorymapped"
        width = "32"
        address = "0x482002c4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR114" {
        access = "memorymapped"
        width = "32"
        address = "0x482002c8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR115" {
        access = "memorymapped"
        width = "32"
        address = "0x482002cc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR116" {
        access = "memorymapped"
        width = "32"
        address = "0x482002d0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR117" {
        access = "memorymapped"
        width = "32"
        address = "0x482002d4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR118" {
        access = "memorymapped"
        width = "32"
        address = "0x482002d8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR119" {
        access = "memorymapped"
        width = "32"
        address = "0x482002dc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR12" {
        access = "memorymapped"
        width = "32"
        address = "0x48200130"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR120" {
        access = "memorymapped"
        width = "32"
        address = "0x482002e0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR121" {
        access = "memorymapped"
        width = "32"
        address = "0x482002e4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR122" {
        access = "memorymapped"
        width = "32"
        address = "0x482002e8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR123" {
        access = "memorymapped"
        width = "32"
        address = "0x482002ec"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR124" {
        access = "memorymapped"
        width = "32"
        address = "0x482002f0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR125" {
        access = "memorymapped"
        width = "32"
        address = "0x482002f4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR126" {
        access = "memorymapped"
        width = "32"
        address = "0x482002f8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR127" {
        access = "memorymapped"
        width = "32"
        address = "0x482002fc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR13" {
        access = "memorymapped"
        width = "32"
        address = "0x48200134"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR14" {
        access = "memorymapped"
        width = "32"
        address = "0x48200138"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR15" {
        access = "memorymapped"
        width = "32"
        address = "0x4820013c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR16" {
        access = "memorymapped"
        width = "32"
        address = "0x48200140"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR17" {
        access = "memorymapped"
        width = "32"
        address = "0x48200144"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR18" {
        access = "memorymapped"
        width = "32"
        address = "0x48200148"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR19" {
        access = "memorymapped"
        width = "32"
        address = "0x4820014c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48200108"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR20" {
        access = "memorymapped"
        width = "32"
        address = "0x48200150"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR21" {
        access = "memorymapped"
        width = "32"
        address = "0x48200154"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR22" {
        access = "memorymapped"
        width = "32"
        address = "0x48200158"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR23" {
        access = "memorymapped"
        width = "32"
        address = "0x4820015c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR24" {
        access = "memorymapped"
        width = "32"
        address = "0x48200160"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR25" {
        access = "memorymapped"
        width = "32"
        address = "0x48200164"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR26" {
        access = "memorymapped"
        width = "32"
        address = "0x48200168"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR27" {
        access = "memorymapped"
        width = "32"
        address = "0x4820016c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR28" {
        access = "memorymapped"
        width = "32"
        address = "0x48200170"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR29" {
        access = "memorymapped"
        width = "32"
        address = "0x48200174"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR3" {
        access = "memorymapped"
        width = "32"
        address = "0x4820010c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR30" {
        access = "memorymapped"
        width = "32"
        address = "0x48200178"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR31" {
        access = "memorymapped"
        width = "32"
        address = "0x4820017c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR32" {
        access = "memorymapped"
        width = "32"
        address = "0x48200180"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR33" {
        access = "memorymapped"
        width = "32"
        address = "0x48200184"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR34" {
        access = "memorymapped"
        width = "32"
        address = "0x48200188"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR35" {
        access = "memorymapped"
        width = "32"
        address = "0x4820018c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR36" {
        access = "memorymapped"
        width = "32"
        address = "0x48200190"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR37" {
        access = "memorymapped"
        width = "32"
        address = "0x48200194"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR38" {
        access = "memorymapped"
        width = "32"
        address = "0x48200198"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR39" {
        access = "memorymapped"
        width = "32"
        address = "0x4820019c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR4" {
        access = "memorymapped"
        width = "32"
        address = "0x48200110"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR40" {
        access = "memorymapped"
        width = "32"
        address = "0x482001a0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR41" {
        access = "memorymapped"
        width = "32"
        address = "0x482001a4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR42" {
        access = "memorymapped"
        width = "32"
        address = "0x482001a8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR43" {
        access = "memorymapped"
        width = "32"
        address = "0x482001ac"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR44" {
        access = "memorymapped"
        width = "32"
        address = "0x482001b0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR45" {
        access = "memorymapped"
        width = "32"
        address = "0x482001b4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR46" {
        access = "memorymapped"
        width = "32"
        address = "0x482001b8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR47" {
        access = "memorymapped"
        width = "32"
        address = "0x482001bc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR48" {
        access = "memorymapped"
        width = "32"
        address = "0x482001c0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR49" {
        access = "memorymapped"
        width = "32"
        address = "0x482001c4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR5" {
        access = "memorymapped"
        width = "32"
        address = "0x48200114"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR50" {
        access = "memorymapped"
        width = "32"
        address = "0x482001c8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR51" {
        access = "memorymapped"
        width = "32"
        address = "0x482001cc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR52" {
        access = "memorymapped"
        width = "32"
        address = "0x482001d0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR53" {
        access = "memorymapped"
        width = "32"
        address = "0x482001d4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR54" {
        access = "memorymapped"
        width = "32"
        address = "0x482001d8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR55" {
        access = "memorymapped"
        width = "32"
        address = "0x482001dc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR56" {
        access = "memorymapped"
        width = "32"
        address = "0x482001e0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR57" {
        access = "memorymapped"
        width = "32"
        address = "0x482001e4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR58" {
        access = "memorymapped"
        width = "32"
        address = "0x482001e8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR59" {
        access = "memorymapped"
        width = "32"
        address = "0x482001ec"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR6" {
        access = "memorymapped"
        width = "32"
        address = "0x48200118"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR60" {
        access = "memorymapped"
        width = "32"
        address = "0x482001f0"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR61" {
        access = "memorymapped"
        width = "32"
        address = "0x482001f4"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR62" {
        access = "memorymapped"
        width = "32"
        address = "0x482001f8"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR63" {
        access = "memorymapped"
        width = "32"
        address = "0x482001fc"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR64" {
        access = "memorymapped"
        width = "32"
        address = "0x48200200"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR65" {
        access = "memorymapped"
        width = "32"
        address = "0x48200204"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR66" {
        access = "memorymapped"
        width = "32"
        address = "0x48200208"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR67" {
        access = "memorymapped"
        width = "32"
        address = "0x4820020c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR68" {
        access = "memorymapped"
        width = "32"
        address = "0x48200210"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR69" {
        access = "memorymapped"
        width = "32"
        address = "0x48200214"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR7" {
        access = "memorymapped"
        width = "32"
        address = "0x4820011c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR70" {
        access = "memorymapped"
        width = "32"
        address = "0x48200218"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR71" {
        access = "memorymapped"
        width = "32"
        address = "0x4820021c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR72" {
        access = "memorymapped"
        width = "32"
        address = "0x48200220"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR73" {
        access = "memorymapped"
        width = "32"
        address = "0x48200224"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR74" {
        access = "memorymapped"
        width = "32"
        address = "0x48200228"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR75" {
        access = "memorymapped"
        width = "32"
        address = "0x4820022c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR76" {
        access = "memorymapped"
        width = "32"
        address = "0x48200230"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR77" {
        access = "memorymapped"
        width = "32"
        address = "0x48200234"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR78" {
        access = "memorymapped"
        width = "32"
        address = "0x48200238"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR79" {
        access = "memorymapped"
        width = "32"
        address = "0x4820023c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR8" {
        access = "memorymapped"
        width = "32"
        address = "0x48200120"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR80" {
        access = "memorymapped"
        width = "32"
        address = "0x48200240"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR81" {
        access = "memorymapped"
        width = "32"
        address = "0x48200244"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR82" {
        access = "memorymapped"
        width = "32"
        address = "0x48200248"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR83" {
        access = "memorymapped"
        width = "32"
        address = "0x4820024c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR84" {
        access = "memorymapped"
        width = "32"
        address = "0x48200250"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR85" {
        access = "memorymapped"
        width = "32"
        address = "0x48200254"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR86" {
        access = "memorymapped"
        width = "32"
        address = "0x48200258"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR87" {
        access = "memorymapped"
        width = "32"
        address = "0x4820025c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR88" {
        access = "memorymapped"
        width = "32"
        address = "0x48200260"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR89" {
        access = "memorymapped"
        width = "32"
        address = "0x48200264"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR9" {
        access = "memorymapped"
        width = "32"
        address = "0x48200124"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR90" {
        access = "memorymapped"
        width = "32"
        address = "0x48200268"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR91" {
        access = "memorymapped"
        width = "32"
        address = "0x4820026c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR92" {
        access = "memorymapped"
        width = "32"
        address = "0x48200270"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR93" {
        access = "memorymapped"
        width = "32"
        address = "0x48200274"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR94" {
        access = "memorymapped"
        width = "32"
        address = "0x48200278"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR95" {
        access = "memorymapped"
        width = "32"
        address = "0x4820027c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR96" {
        access = "memorymapped"
        width = "32"
        address = "0x48200280"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR97" {
        access = "memorymapped"
        width = "32"
        address = "0x48200284"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR98" {
        access = "memorymapped"
        width = "32"
        address = "0x48200288"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_ILR99" {
        access = "memorymapped"
        width = "32"
        address = "0x4820028c"
        desc = "These registers contain the priority for the interrupts and the FIQ/IRQ steering.  "
        type = "INTC_ILR__bitfield"
    }
    "INTC_IRQ_PRIORITY" {
        access = "memorymapped"
        width = "32"
        address = "0x48200060"
        desc = "This register supplies the currently active IRQ priority level"
        type = "INTC_IRQ_PRIORITY__bitfield"
    }
    "INTC_ISR_CLEAR0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200094"
        desc = "This register is used to clear the software interrupt bits  "
        type = "INTC_ISR_CLEAR__bitfield"
    }
    "INTC_ISR_CLEAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000b4"
        desc = "This register is used to clear the software interrupt bits  "
        type = "INTC_ISR_CLEAR__bitfield"
    }
    "INTC_ISR_CLEAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000d4"
        desc = "This register is used to clear the software interrupt bits  "
        type = "INTC_ISR_CLEAR__bitfield"
    }
    "INTC_ISR_CLEAR3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000f4"
        desc = "This register is used to clear the software interrupt bits  "
        type = "INTC_ISR_CLEAR__bitfield"
    }
    "INTC_ISR_SET0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200090"
        desc = "This register is used to set the software interrupt bits.  It is also used to read the currently active software interrupts.  "
        type = "INTC_ISR_SET__bitfield"
    }
    "INTC_ISR_SET1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000b0"
        desc = "This register is used to set the software interrupt bits.  It is also used to read the currently active software interrupts.  "
        type = "INTC_ISR_SET__bitfield"
    }
    "INTC_ISR_SET2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000d0"
        desc = "This register is used to set the software interrupt bits.  It is also used to read the currently active software interrupts.  "
        type = "INTC_ISR_SET__bitfield"
    }
    "INTC_ISR_SET3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000f0"
        desc = "This register is used to set the software interrupt bits.  It is also used to read the currently active software interrupts.  "
        type = "INTC_ISR_SET__bitfield"
    }
    "INTC_ITR0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200080"
        desc = "This register shows the raw interrupt input status before masking  "
        type = "INTC_ITR__bitfield"
    }
    "INTC_ITR1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000a0"
        desc = "This register shows the raw interrupt input status before masking  "
        type = "INTC_ITR__bitfield"
    }
    "INTC_ITR2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000c0"
        desc = "This register shows the raw interrupt input status before masking  "
        type = "INTC_ITR__bitfield"
    }
    "INTC_ITR3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000e0"
        desc = "This register shows the raw interrupt input status before masking  "
        type = "INTC_ITR__bitfield"
    }
    "INTC_MIR0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200084"
        desc = "This register contains the interrupt mask  "
        type = "INTC_MIR__bitfield"
    }
    "INTC_MIR1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000a4"
        desc = "This register contains the interrupt mask  "
        type = "INTC_MIR__bitfield"
    }
    "INTC_MIR2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000c4"
        desc = "This register contains the interrupt mask  "
        type = "INTC_MIR__bitfield"
    }
    "INTC_MIR3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000e4"
        desc = "This register contains the interrupt mask  "
        type = "INTC_MIR__bitfield"
    }
    "INTC_MIR_CLEAR0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200088"
        desc = "This register is used to clear the interrupt mask bits.  "
        type = "INTC_MIR_CLEAR__bitfield"
    }
    "INTC_MIR_CLEAR1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000a8"
        desc = "This register is used to clear the interrupt mask bits.  "
        type = "INTC_MIR_CLEAR__bitfield"
    }
    "INTC_MIR_CLEAR2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000c8"
        desc = "This register is used to clear the interrupt mask bits.  "
        type = "INTC_MIR_CLEAR__bitfield"
    }
    "INTC_MIR_CLEAR3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000e8"
        desc = "This register is used to clear the interrupt mask bits.  "
        type = "INTC_MIR_CLEAR__bitfield"
    }
    "INTC_MIR_SET0" {
        access = "memorymapped"
        width = "32"
        address = "0x4820008c"
        desc = "This register is used to set the interrupt mask bits.  "
        type = "INTC_MIR_SET__bitfield"
    }
    "INTC_MIR_SET1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000ac"
        desc = "This register is used to set the interrupt mask bits.  "
        type = "INTC_MIR_SET__bitfield"
    }
    "INTC_MIR_SET2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000cc"
        desc = "This register is used to set the interrupt mask bits.  "
        type = "INTC_MIR_SET__bitfield"
    }
    "INTC_MIR_SET3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000ec"
        desc = "This register is used to set the interrupt mask bits.  "
        type = "INTC_MIR_SET__bitfield"
    }
    "INTC_PENDING_FIQ0" {
        access = "memorymapped"
        width = "32"
        address = "0x4820009c"
        desc = "This register contains the FIQ status after masking  "
        type = "INTC_PENDING_FIQ__bitfield"
    }
    "INTC_PENDING_FIQ1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000bc"
        desc = "This register contains the FIQ status after masking  "
        type = "INTC_PENDING_FIQ__bitfield"
    }
    "INTC_PENDING_FIQ2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000dc"
        desc = "This register contains the FIQ status after masking  "
        type = "INTC_PENDING_FIQ__bitfield"
    }
    "INTC_PENDING_FIQ3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000fc"
        desc = "This register contains the FIQ status after masking  "
        type = "INTC_PENDING_FIQ__bitfield"
    }
    "INTC_PENDING_IRQ0" {
        access = "memorymapped"
        width = "32"
        address = "0x48200098"
        desc = "This register contains the IRQ status after masking  "
        type = "INTC_PENDING_IRQ__bitfield"
    }
    "INTC_PENDING_IRQ1" {
        access = "memorymapped"
        width = "32"
        address = "0x482000b8"
        desc = "This register contains the IRQ status after masking  "
        type = "INTC_PENDING_IRQ__bitfield"
    }
    "INTC_PENDING_IRQ2" {
        access = "memorymapped"
        width = "32"
        address = "0x482000d8"
        desc = "This register contains the IRQ status after masking  "
        type = "INTC_PENDING_IRQ__bitfield"
    }
    "INTC_PENDING_IRQ3" {
        access = "memorymapped"
        width = "32"
        address = "0x482000f8"
        desc = "This register contains the IRQ status after masking  "
        type = "INTC_PENDING_IRQ__bitfield"
    }
    "INTC_PROTECTION" {
        access = "memorymapped"
        width = "32"
        address = "0x4820004c"
        desc = "This register controls protection of the other registers.  This register can only be accessed in priviledged mode, regardless of the curent value of the protection bit.  "
        type = "INTC_PROTECTION__bitfield"
    }
    "INTC_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x48200000"
        desc = "This register contains the IP revision code  "
        type = "REVISION__bitfield"
    }
    "INTC_SIR_FIQ" {
        access = "memorymapped"
        width = "32"
        address = "0x48200044"
        desc = "This register supplies the currently active FIQ interrupt number  "
        type = "INTC_SIR_FIQ__bitfield"
    }
    "INTC_SIR_IRQ" {
        access = "memorymapped"
        width = "32"
        address = "0x48200040"
        desc = "This register supplies the currently active IRQ interrupt number.  "
        type = "INTC_SIR_IRQ__bitfield"
    }
    "INTC_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48200010"
        desc = "This register controls the various parameters of the OCP interface  "
        type = "INTC_SYSCONFIG__bitfield"
    }
    "INTC_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48200014"
        desc = "This register provides status information about the module  "
        type = "INTC_SYSSTATUS__bitfield"
    }
    "INTC_THRESHOLD" {
        access = "memorymapped"
        width = "32"
        address = "0x48200068"
        desc = "This register sets the priority threshold"
        type = "INTC_THRESHOLD__bitfield"
    }
    "IRQENABLE_CLR_SYS" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000bc"
        type = "IRQENABLE_CLR_SYS__bitfield"
    }
    "IRQENABLE_SET_SYS" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000b4"
        type = "IRQENABLE_SET_SYS__bitfield"
    }
    "IRQSTATUS_RAW_SYS" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000a4"
        type = "IRQSTATUS_RAW_SYS__bitfield"
    }
    "IRQSTATUS_SYS" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000ac"
        type = "IRQSTATUS_SYS__bitfield"
    }
    "KICK0R" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e06c"
        desc = "The kick registers (KICKnR) are used to enable and disable write protection on the RTC registers. Out of reset, the RTC registers are write-protected. To disable write protection, correct keys must be written to the KICKnR registers. The Kick0 register allows writing to unlock the kick0 data. To disable RTC register write protection, the value of 83E7 0B13h must be written to KICK0R, followed by the value of 95A4 F1E0h written to KICK1R. RTC register write protection is enabled when any value is written to KICK0R."
        type = "KICK0R__bitfield"
    }
    "KICK1R" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e070"
        desc = "The kick registers (KICKnR) are used to enable and disable write protection on the RTC registers. Out of reset, the RTC registers are write-protected. To disable write protection, correct keys must be written to the KICKnR registers. The Kick1 register allows writing to unlock the kick1 data and the kicker mechanism to write to other MMRs. To disable RTC register write protection, the value of 83E7 0B13h must be written to KICK0R, followed by the value of 95A4 F1E0h written to KICK1R. "
        type = "KICK1R__bitfield"
    }
    "LCD_Controller_CLKC_ENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e06c"
        type = "LCD_Controller_CLKC_ENABLE__bitfield"
    }
    "LCD_Controller_CLKC_RESET" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e070"
        type = "LCD_Controller_CLKC_RESET__bitfield"
    }
    "LCD_Controller_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e004"
        type = "LCD_Controller_CTRL__bitfield"
    }
    "LCD_Controller_IRQENABLE_CLEAR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e064"
        type = "LCD_Controller_IRQENABLE_CLEAR__bitfield"
    }
    "LCD_Controller_IRQENABLE_SET" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e060"
        type = "LCD_Controller_IRQENABLE_SET__bitfield"
    }
    "LCD_Controller_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e05c"
        type = "LCD_Controller_IRQSTATUS__bitfield"
    }
    "LCD_Controller_IRQSTATUS_RAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e058"
        type = "LCD_Controller_IRQSTATUS_RAW__bitfield"
    }
    "LCD_Controller_LCDDMA_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e040"
        type = "LCD_Controller_LCDDMA_CTRL__bitfield"
    }
    "LCD_Controller_LCDDMA_FB0_BASE" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e044"
        type = "LCD_Controller_LCDDMA_FB0_BASE__bitfield"
    }
    "LCD_Controller_LCDDMA_FB0_CEILING" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e048"
        type = "LCD_Controller_LCDDMA_FB0_CEILING__bitfield"
    }
    "LCD_Controller_LCDDMA_FB1_BASE" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e04c"
        type = "LCD_Controller_LCDDMA_FB1_BASE__bitfield"
    }
    "LCD_Controller_LCDDMA_FB1_CEILING" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e050"
        type = "LCD_Controller_LCDDMA_FB1_CEILING__bitfield"
    }
    "LCD_Controller_LIDD_CS0_ADDR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e014"
        type = "LCD_Controller_LIDD_CS_ADDR__bitfield"
	permission = "both/none"
    }
    "LCD_Controller_LIDD_CS0_CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e010"
        type = "LCD_Controller_LIDD_CS0_CONF__bitfield"
    }
    "LCD_Controller_LIDD_CS0_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e018"
        type = "LCD_Controller_LIDD_CS_DATA__bitfield"
	permission = "both/none"
    }
    "LCD_Controller_LIDD_CS1_ADDR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e020"
        type = "LCD_Controller_LIDD_CS_ADDR__bitfield"
	permission = "both/none"
    }
    "LCD_Controller_LIDD_CS1_CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e01c"
        type = "LCD_Controller_LIDD_CS1_CONF__bitfield"
    }
    "LCD_Controller_LIDD_CS1_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e024"
        type = "LCD_Controller_LIDD_CS_DATA__bitfield"
	permission = "both/none"
    }
    "LCD_Controller_LIDD_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e00c"
        type = "LCD_Controller_LIDD_CTRL__bitfield"
    }
    "LCD_Controller_PID" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e000"
        type = "LCD_Controller_PID__bitfield"
    }
    "LCD_Controller_RASTER_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e028"
        type = "LCD_Controller_RASTER_CTRL__bitfield"
    }
    "LCD_Controller_RASTER_SUBPANEL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e038"
        type = "LCD_Controller_RASTER_SUBPANEL__bitfield"
    }
    "LCD_Controller_RASTER_SUBPANEL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e03c"
        type = "LCD_Controller_RASTER_SUBPANEL2__bitfield"
    }
    "LCD_Controller_RASTER_TIMING_0" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e02c"
        type = "LCD_Controller_RASTER_TIMING_0__bitfield"
    }
    "LCD_Controller_RASTER_TIMING_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e030"
        type = "LCD_Controller_RASTER_TIMING_1__bitfield"
    }
    "LCD_Controller_RASTER_TIMING_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e034"
        type = "LCD_Controller_RASTER_TIMING_2__bitfield"
    }
    "LCD_Controller_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830e054"
        type = "LCD_Controller_SYSCONFIG__bitfield"
    }
    "LRAM0BASE" {
        access = "memorymapped"
        width = "32"
        address = "0x47404080"
        type = "LRAM0BASE__bitfield"
    }
    "LRAM0SIZE" {
        access = "memorymapped"
        width = "32"
        address = "0x47404084"
        type = "LRAM0SIZE__bitfield"
    }
    "LRAM1BASE" {
        access = "memorymapped"
        width = "32"
        address = "0x47404088"
        type = "LRAM1BASE__bitfield"
    }
    "Late_Collisions" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100958"
    }
    "MAILBOX0_FIFOSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8080"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8084"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8088"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c808c"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_4" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8090"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_5" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8094"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_6" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8098"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_FIFOSTATUS_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480c809c"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_FIFOSTATUS___bitfield"
    }
    "MAILBOX0_IRQENABLE_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c810c"
        desc = "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c811c"
        desc = "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_CLR_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c812c"
        desc = "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_CLR_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c813c"
        desc = "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_SET_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8108"
        desc = "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_SET_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8118"
        desc = "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_SET_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8128"
        desc = "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQENABLE_SET_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8138"
        desc = "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_CLR_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8104"
        desc = "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_CLR_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8114"
        desc = "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_CLR_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8124"
        desc = "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_CLR_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8134"
        desc = "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_RAW_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8100"
        desc = "The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit. This register is mainly used for debug purpose."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_RAW_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8110"
        desc = "The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit. This register is mainly used for debug purpose."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_RAW_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8120"
        desc = "The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit. This register is mainly used for debug purpose."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_IRQSTATUS_RAW_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8130"
        desc = "The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit. This register is mainly used for debug purpose."
        type = "MAILBOX0_IRQ___bitfield"
    }
    "MAILBOX0_MESSAGE_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8040"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8044"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8048"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c804c"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_4" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8050"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_5" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8054"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_6" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8058"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MESSAGE_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480c805c"
        desc = "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue"
        type = "MAILBOX0_MESSAGE___bitfield"
    }
    "MAILBOX0_MSGSTATUS_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80c0"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80c4"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80c8"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80cc"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_4" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80d0"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_5" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80d4"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_6" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80d8"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_MSGSTATUS_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480c80dc"
        desc = "The message status register has the status of the messages in the mailbox"
        type = "MAILBOX0_MSGSTATUS___bitfield"
    }
    "MAILBOX0_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8000"
        desc = "This register contains the IP revision code  "
        type = "MAILBOX0_REVISION__bitfield"
    }
    "MAILBOX0_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x480c8010"
        desc = "This register controls the various parameters of the OCP interface  "
        type = "MAILBOX0_SYSCONFIG__bitfield"
    }
    "MDIOALIVE" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101008"
    }
    "MDIOCONTROL" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101004"
    }
    "MDIOLINK" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10100c"
    }
    "MDIOLINKINTMASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101014"
    }
    "MDIOLINKINTRAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101010"
    }
    "MDIOUSERACCESS0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101080"
    }
    "MDIOUSERACCESS1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101088"
    }
    "MDIOUSERINTMASKCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10102c"
    }
    "MDIOUSERINTMASKED" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101024"
    }
    "MDIOUSERINTMASKSET" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101028"
    }
    "MDIOUSERINTRAW" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101020"
    }
    "MDIOUSERPHYSEL0" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101084"
    }
    "MDIOUSERPHYSEL1" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10108c"
    }
    "MDIOVER" {
        access = "memorymapped"
        width = "32"
        address = "0x4a101000"
    }
    "MINUTES_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e004"
        desc = "The MINUTES_REG is used to program the minutes value of the current time. Minutes are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. If the minutes value is 32, then the value of MIN0 is 2 and value of MIN1 is 3."
        type = "MINUTES_REG__bitfield"
    }
    "MMC1_SD_AC12" {
        access = "memorymapped"
        width = "32"
        address = "0x481d823c"
        desc = "The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this SD_AC12 register when an auto CMD12 error interrupt occurs. This register is valid only when auto CMD12 is enabled (SD_CMD[2] ACEN bit) and auto CMD12Error (SD_STAT[24] ACE bit) is set to 1. These bits are automatically reset when starting a new adtc command with data."
        type = "MMC_SD_AC12__bitfield"
    }
    "MMC1_SD_ADMAES" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8254"
        desc = "When an ADMA Error Interrupt has occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address. ST_FDS: Current location set in the ADMA System Address register is the error descriptor address. ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address. In the case of a write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid = 0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor. "
        type = "MMC_SD_ADMAES__bitfield"
    }
    "MMC1_SD_ADMASAH" {
        access = "memorymapped"
        width = "32"
        address = "0x481d825c"
        type = "MMC_SD_ADMASAH__bitfield"
    }
    "MMC1_SD_ADMASAL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8258"
        desc = "This register holds the byte address of the executing command of the Descriptor table. The 32-bit Address Descriptor uses the lower 32 bits of this register. At the start of ADMA, the Host Driver shall set the start address of the Descriptor table. "
        type = "MMC_SD_ADMASAL__bitfield"
    }
    "MMC1_SD_ARG" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8208"
        desc = "This register contains command argument specified as bit 39-8 of Command-Format. These registers must be initialized prior to sending the command itself to the card (write action into the register SD_CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary."
        type = "MMC_SD_ARG__bitfield"
    }
    "MMC1_SD_BLK" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8204"
        desc = "This register shall be used for any card. SD_BLK[BLEN] is the block size register. SD_BLK[NBLK] is the block count register."
        type = "MMC_SD_BLK__bitfield"
    }
    "MMC1_SD_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8240"
        desc = "This register lists the capabilities of the MMC/SD/SDIO host controller."
        type = "MMC_SD_CAPA__bitfield"
    }
    "MMC1_SD_CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x481d820c"
        desc = "SD_CMD[31:16] = the command register. SD_CMD[15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into SD_CMD[15:0] registers during data transfer has no effect. This register can be used for any card. In SYSTEST mode, a write into SD_CMD register will not start a transfer. "
        type = "MMC_SD_CMD__bitfield"
    }
    "MMC1_SD_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x481d812c"
        desc = "This register is used: To select the functional mode for any card. To send an initialization sequence to any card. To send an initialization sequence to any card. To enable the detection on the mmc_dat[1] signal of a card interrupt for SDIO cards only. It also configures the parameters related to the card detect and write protect input signals"
        type = "MMC_SD_CON__bitfield"
    }
    "MMC1_SD_CSRE" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8124"
        desc = "This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit SD_CSRE[i] is set to 1, if the corresponding bit at the same position in the response SD_RSP10[I] is set to 1, the host controller indicates a card error (SD_STAT[28] CERR bit) interrupt status to avoid the host driver reading the response register (SD_RSP10). No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (SD_RSP76) for possible card errors. "
        type = "MMC_SD_CSRE__bitfield"
    }
    "MMC1_SD_CUR_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8248"
        desc = "This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (SD_CAPA). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        type = "MMC_SD_CUR_CAPA__bitfield"
    }
    "MMC1_SD_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8220"
        desc = "This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bitsx256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1Byte or 16-bit access: Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad."
        type = "MMC_SD_DATA__bitfield"
    }
    "MMC1_SD_FE" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8250"
        desc = "The Force Event register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set. "
        type = "MMC_SD_FE__bitfield"
    }
    "MMC1_SD_HCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8228"
        desc = "This register defines the host controls to set power, wake-up and transfer parameters. SD_HCTL[31:24] = Wake-up control. SD_HCTL[23:16] = Block gap control. SD_HCTL[15:8] = Power control. SD_HCTL[7:0] = Host control. If your device does not support MMC cards, then those bits in this register which are meant for MMC card use should be assumed to be reserved. "
        type = "MMC_SD_HCTL__bitfield"
    }
    "MMC1_SD_IE" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8234"
        desc = "This register allows to enable/disable the module to set status bits, on an event-by-event basis. SD_IE[31:16] = Error Interrupt Status Enable. SD_IE[15:0] = Normal Interrupt Status Enable."
        type = "MMC_SD_IE__bitfield"
    }
    "MMC1_SD_ISE" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8238"
        desc = "This register allows you to enable/disable the module to set status bits, on an event-by-event basis. SD_ISE[31:16] = Error Interrupt Signal Enable. SD_ISE[15:0] = Normal Interrupt Signal Enable."
        type = "MMC_SD_ISE__bitfield"
    }
    "MMC1_SD_PSTATE" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8224"
        desc = "The Host can get the status of the Host controller from this 32-bit read only register."
        type = "MMC_SD_PSTATE__bitfield"
    }
    "MMC1_SD_PWCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8130"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage."
        type = "MMC_SD_PWCNT__bitfield"
    }
    "MMC1_SD_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x481d82fc"
        desc = "This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. SD_REV[31:16] = Host Controller Version. SD_REV[15:0] = Slot Interrupt Status."
        type = "MMC_SD_REV__bitfield"
    }
    "MMC1_SD_RSP10" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8210"
        desc = "This 32-bit register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6."
        type = "MMC_SD_RSP10__bitfield"
    }
    "MMC1_SD_RSP32" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8214"
        desc = "This 32-bit register holds bits positions [63:32] of command response type R2."
        type = "MMC_SD_RSP32__bitfield"
    }
    "MMC1_SD_RSP54" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8218"
        desc = "This 32-bit register holds bits positions [95:64] of command response type R2."
        type = "MMC_SD_RSP54__bitfield"
    }
    "MMC1_SD_RSP76" {
        access = "memorymapped"
        width = "32"
        address = "0x481d821c"
        desc = "This 32-bit register holds bits positions [127:96] of command response type R2."
        type = "MMC_SD_RSP76__bitfield"
    }
    "MMC1_SD_SDMASA" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8200"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power. This value depends on PAD characteristics and voltage."
        type = "MMC_SD_SDMASA__bitfield"
    }
    "MMC1_SD_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8230"
        desc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt. SD_STAT[31:16] = Error Interrupt Status. SD_STAT[15:0] = Normal Interrupt Status. The error bits are located in the upper 16 bits of the SD_STAT register. All bits are cleared by writing a 1 to them. Additionally, bits 15 and 8 serve as special error bits. These cannot be cleared by writing a 1 to them. Bit 15 (ERRI) is automatically cleared when the error causing to ERRI to be set is handled. (that is, when bits 31:16 are cleared, bit 15 will be automatically cleared). Bit 8 (CIRQ) is cleared by writing a 0 to SD_IE[8] (masking the interrupt) and servicing the interrupt."
        type = "MMC_SD_STAT__bitfield"
    }
    "MMC1_SD_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8110"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "MMC_SD_SYSCONFIG__bitfield"
    }
    "MMC1_SD_SYSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x481d822c"
        desc = "This register defines the system controls to set software resets, clock frequency management and data timeout. SD_SYSCTL[31:24] = Software resets. SD_SYSCTL[23:16] = Timeout control. SD_SYSCTL[15:0] = Clock control."
        type = "MMC_SD_SYSCTL__bitfield"
    }
    "MMC1_SD_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8114"
        desc = "This register provides status information about the module excluding the interrupt status information."
        type = "MMC_SD_SYSSTATUS__bitfield"
    }
    "MMC1_SD_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x481d8128"
        desc = "This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. In SYSTEST mode, a write into SD_CMD register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size (SD_BLK[10:0] BLEN bits) and the Blocks count for current transfer (SD_BLK[31:16] NBLK bits) are needed to generate a Buffer write ready interrupt (SD_STAT[4] BWR bit) or a Buffer read ready interrupt (SD_STAT[5] BRR bit) and DMA requests if enabled. "
        type = "MMC_SD_SYSTEST__bitfield"
    }
    "MMCHS0_SD_AC12" {
        access = "memorymapped"
        width = "32"
        address = "0x4806023c"
        desc = "The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this SD_AC12 register when an auto CMD12 error interrupt occurs. This register is valid only when auto CMD12 is enabled (SD_CMD[2] ACEN bit) and auto CMD12Error (SD_STAT[24] ACE bit) is set to 1. These bits are automatically reset when starting a new adtc command with data."
        type = "MMC_SD_AC12__bitfield"
    }
    "MMCHS0_SD_ADMAES" {
        access = "memorymapped"
        width = "32"
        address = "0x48060254"
        desc = "When an ADMA Error Interrupt has occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address. ST_FDS: Current location set in the ADMA System Address register is the error descriptor address. ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address. In the case of a write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid = 0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor. "
        type = "MMC_SD_ADMAES__bitfield"
    }
    "MMCHS0_SD_ADMASAH" {
        access = "memorymapped"
        width = "32"
        address = "0x4806025c"
        type = "MMC_SD_ADMASAH__bitfield"
    }
    "MMCHS0_SD_ADMASAL" {
        access = "memorymapped"
        width = "32"
        address = "0x48060258"
        desc = "This register holds the byte address of the executing command of the Descriptor table. The 32-bit Address Descriptor uses the lower 32 bits of this register. At the start of ADMA, the Host Driver shall set the start address of the Descriptor table. "
        type = "MMC_SD_ADMASAL__bitfield"
    }
    "MMCHS0_SD_ARG" {
        access = "memorymapped"
        width = "32"
        address = "0x48060208"
        desc = "This register contains command argument specified as bit 39-8 of Command-Format. These registers must be initialized prior to sending the command itself to the card (write action into the register SD_CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary."
        type = "MMC_SD_ARG__bitfield"
    }
    "MMCHS0_SD_BLK" {
        access = "memorymapped"
        width = "32"
        address = "0x48060204"
        desc = "This register shall be used for any card. SD_BLK[BLEN] is the block size register. SD_BLK[NBLK] is the block count register."
        type = "MMC_SD_BLK__bitfield"
    }
    "MMCHS0_SD_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x48060240"
        desc = "This register lists the capabilities of the MMC/SD/SDIO host controller."
        type = "MMC_SD_CAPA__bitfield"
    }
    "MMCHS0_SD_CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x4806020c"
        desc = "SD_CMD[31:16] = the command register. SD_CMD[15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into SD_CMD[15:0] registers during data transfer has no effect. This register can be used for any card. In SYSTEST mode, a write into SD_CMD register will not start a transfer. "
        type = "MMC_SD_CMD__bitfield"
    }
    "MMCHS0_SD_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x4806012c"
        desc = "This register is used: To select the functional mode for any card. To send an initialization sequence to any card. To send an initialization sequence to any card. To enable the detection on the mmc_dat[1] signal of a card interrupt for SDIO cards only. It also configures the parameters related to the card detect and write protect input signals"
        type = "MMC_SD_CON__bitfield"
    }
    "MMCHS0_SD_CSRE" {
        access = "memorymapped"
        width = "32"
        address = "0x48060124"
        desc = "This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit SD_CSRE[i] is set to 1, if the corresponding bit at the same position in the response SD_RSP10[I] is set to 1, the host controller indicates a card error (SD_STAT[28] CERR bit) interrupt status to avoid the host driver reading the response register (SD_RSP10). No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (SD_RSP76) for possible card errors. "
        type = "MMC_SD_CSRE__bitfield"
    }
    "MMCHS0_SD_CUR_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x48060248"
        desc = "This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (SD_CAPA). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        type = "MMC_SD_CUR_CAPA__bitfield"
    }
    "MMCHS0_SD_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x48060220"
        desc = "This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bitsx256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1Byte or 16-bit access: Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad."
        type = "MMC_SD_DATA__bitfield"
    }
    "MMCHS0_SD_FE" {
        access = "memorymapped"
        width = "32"
        address = "0x48060250"
        desc = "The Force Event register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set. "
        type = "MMC_SD_FE__bitfield"
    }
    "MMCHS0_SD_HCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48060228"
        desc = "This register defines the host controls to set power, wake-up and transfer parameters. SD_HCTL[31:24] = Wake-up control. SD_HCTL[23:16] = Block gap control. SD_HCTL[15:8] = Power control. SD_HCTL[7:0] = Host control. If your device does not support MMC cards, then those bits in this register which are meant for MMC card use should be assumed to be reserved. "
        type = "MMC_SD_HCTL__bitfield"
    }
    "MMCHS0_SD_IE" {
        access = "memorymapped"
        width = "32"
        address = "0x48060234"
        desc = "This register allows to enable/disable the module to set status bits, on an event-by-event basis. SD_IE[31:16] = Error Interrupt Status Enable. SD_IE[15:0] = Normal Interrupt Status Enable."
        type = "MMC_SD_IE__bitfield"
    }
    "MMCHS0_SD_ISE" {
        access = "memorymapped"
        width = "32"
        address = "0x48060238"
        desc = "This register allows you to enable/disable the module to set status bits, on an event-by-event basis. SD_ISE[31:16] = Error Interrupt Signal Enable. SD_ISE[15:0] = Normal Interrupt Signal Enable."
        type = "MMC_SD_ISE__bitfield"
    }
    "MMCHS0_SD_PSTATE" {
        access = "memorymapped"
        width = "32"
        address = "0x48060224"
        desc = "The Host can get the status of the Host controller from this 32-bit read only register."
        type = "MMC_SD_PSTATE__bitfield"
    }
    "MMCHS0_SD_PWCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48060130"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage."
        type = "MMC_SD_PWCNT__bitfield"
    }
    "MMCHS0_SD_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x480602fc"
        desc = "This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. SD_REV[31:16] = Host Controller Version. SD_REV[15:0] = Slot Interrupt Status."
        type = "MMC_SD_REV__bitfield"
    }
    "MMCHS0_SD_RSP10" {
        access = "memorymapped"
        width = "32"
        address = "0x48060210"
        desc = "This 32-bit register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6."
        type = "MMC_SD_RSP10__bitfield"
    }
    "MMCHS0_SD_RSP32" {
        access = "memorymapped"
        width = "32"
        address = "0x48060214"
        desc = "This 32-bit register holds bits positions [63:32] of command response type R2."
        type = "MMC_SD_RSP32__bitfield"
    }
    "MMCHS0_SD_RSP54" {
        access = "memorymapped"
        width = "32"
        address = "0x48060218"
        desc = "This 32-bit register holds bits positions [95:64] of command response type R2."
        type = "MMC_SD_RSP54__bitfield"
    }
    "MMCHS0_SD_RSP76" {
        access = "memorymapped"
        width = "32"
        address = "0x4806021c"
        desc = "This 32-bit register holds bits positions [127:96] of command response type R2."
        type = "MMC_SD_RSP76__bitfield"
    }
    "MMCHS0_SD_SDMASA" {
        access = "memorymapped"
        width = "32"
        address = "0x48060200"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power. This value depends on PAD characteristics and voltage."
        type = "MMC_SD_SDMASA__bitfield"
    }
    "MMCHS0_SD_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48060230"
        desc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt. SD_STAT[31:16] = Error Interrupt Status. SD_STAT[15:0] = Normal Interrupt Status. The error bits are located in the upper 16 bits of the SD_STAT register. All bits are cleared by writing a 1 to them. Additionally, bits 15 and 8 serve as special error bits. These cannot be cleared by writing a 1 to them. Bit 15 (ERRI) is automatically cleared when the error causing to ERRI to be set is handled. (that is, when bits 31:16 are cleared, bit 15 will be automatically cleared). Bit 8 (CIRQ) is cleared by writing a 0 to SD_IE[8] (masking the interrupt) and servicing the interrupt."
        type = "MMC_SD_STAT__bitfield"
    }
    "MMCHS0_SD_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48060110"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "MMC_SD_SYSCONFIG__bitfield"
    }
    "MMCHS0_SD_SYSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4806022c"
        desc = "This register defines the system controls to set software resets, clock frequency management and data timeout. SD_SYSCTL[31:24] = Software resets. SD_SYSCTL[23:16] = Timeout control. SD_SYSCTL[15:0] = Clock control."
        type = "MMC_SD_SYSCTL__bitfield"
    }
    "MMCHS0_SD_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48060114"
        desc = "This register provides status information about the module excluding the interrupt status information."
        type = "MMC_SD_SYSSTATUS__bitfield"
    }
    "MMCHS0_SD_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x48060128"
        desc = "This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. In SYSTEST mode, a write into SD_CMD register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size (SD_BLK[10:0] BLEN bits) and the Blocks count for current transfer (SD_BLK[31:16] NBLK bits) are needed to generate a Buffer write ready interrupt (SD_STAT[4] BWR bit) or a Buffer read ready interrupt (SD_STAT[5] BRR bit) and DMA requests if enabled. "
        type = "MMC_SD_SYSTEST__bitfield"
    }
    "MMCHS2_SD_AC12" {
        access = "memorymapped"
        width = "32"
        address = "0x4781023c"
        desc = "The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this SD_AC12 register when an auto CMD12 error interrupt occurs. This register is valid only when auto CMD12 is enabled (SD_CMD[2] ACEN bit) and auto CMD12Error (SD_STAT[24] ACE bit) is set to 1. These bits are automatically reset when starting a new adtc command with data."
        type = "MMC_SD_AC12__bitfield"
    }
    "MMCHS2_SD_ADMAES" {
        access = "memorymapped"
        width = "32"
        address = "0x47810254"
        desc = "When an ADMA Error Interrupt has occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address. ST_FDS: Current location set in the ADMA System Address register is the error descriptor address. ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address. In the case of a write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid = 0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor. "
        type = "MMC_SD_ADMAES__bitfield"
    }
    "MMCHS2_SD_ADMASAH" {
        access = "memorymapped"
        width = "32"
        address = "0x4781025c"
        type = "MMC_SD_ADMASAH__bitfield"
    }
    "MMCHS2_SD_ADMASAL" {
        access = "memorymapped"
        width = "32"
        address = "0x47810258"
        desc = "This register holds the byte address of the executing command of the Descriptor table. The 32-bit Address Descriptor uses the lower 32 bits of this register. At the start of ADMA, the Host Driver shall set the start address of the Descriptor table. "
        type = "MMC_SD_ADMASAL__bitfield"
    }
    "MMCHS2_SD_ARG" {
        access = "memorymapped"
        width = "32"
        address = "0x47810208"
        desc = "This register contains command argument specified as bit 39-8 of Command-Format. These registers must be initialized prior to sending the command itself to the card (write action into the register SD_CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary."
        type = "MMC_SD_ARG__bitfield"
    }
    "MMCHS2_SD_BLK" {
        access = "memorymapped"
        width = "32"
        address = "0x47810204"
        desc = "This register shall be used for any card. SD_BLK[BLEN] is the block size register. SD_BLK[NBLK] is the block count register."
        type = "MMC_SD_BLK__bitfield"
    }
    "MMCHS2_SD_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x47810240"
        desc = "This register lists the capabilities of the MMC/SD/SDIO host controller."
        type = "MMC_SD_CAPA__bitfield"
    }
    "MMCHS2_SD_CMD" {
        access = "memorymapped"
        width = "32"
        address = "0x4781020c"
        desc = "SD_CMD[31:16] = the command register. SD_CMD[15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into SD_CMD[15:0] registers during data transfer has no effect. This register can be used for any card. In SYSTEST mode, a write into SD_CMD register will not start a transfer. "
        type = "MMC_SD_CMD__bitfield"
    }
    "MMCHS2_SD_CON" {
        access = "memorymapped"
        width = "32"
        address = "0x4781012c"
        desc = "This register is used: To select the functional mode for any card. To send an initialization sequence to any card. To send an initialization sequence to any card. To enable the detection on the mmc_dat[1] signal of a card interrupt for SDIO cards only. It also configures the parameters related to the card detect and write protect input signals"
        type = "MMC_SD_CON__bitfield"
    }
    "MMCHS2_SD_CSRE" {
        access = "memorymapped"
        width = "32"
        address = "0x47810124"
        desc = "This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit SD_CSRE[i] is set to 1, if the corresponding bit at the same position in the response SD_RSP10[I] is set to 1, the host controller indicates a card error (SD_STAT[28] CERR bit) interrupt status to avoid the host driver reading the response register (SD_RSP10). No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (SD_RSP76) for possible card errors. "
        type = "MMC_SD_CSRE__bitfield"
    }
    "MMCHS2_SD_CUR_CAPA" {
        access = "memorymapped"
        width = "32"
        address = "0x47810248"
        desc = "This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (SD_CAPA). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal)."
        type = "MMC_SD_CUR_CAPA__bitfield"
    }
    "MMCHS2_SD_DATA" {
        access = "memorymapped"
        width = "32"
        address = "0x47810220"
        desc = "This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bitsx256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1Byte or 16-bit access: Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK. Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad."
        type = "MMC_SD_DATA__bitfield"
    }
    "MMCHS2_SD_FE" {
        access = "memorymapped"
        width = "32"
        address = "0x47810250"
        desc = "The Force Event register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set. "
        type = "MMC_SD_FE__bitfield"
    }
    "MMCHS2_SD_HCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x47810228"
        desc = "This register defines the host controls to set power, wake-up and transfer parameters. SD_HCTL[31:24] = Wake-up control. SD_HCTL[23:16] = Block gap control. SD_HCTL[15:8] = Power control. SD_HCTL[7:0] = Host control. If your device does not support MMC cards, then those bits in this register which are meant for MMC card use should be assumed to be reserved. "
        type = "MMC_SD_HCTL__bitfield"
    }
    "MMCHS2_SD_IE" {
        access = "memorymapped"
        width = "32"
        address = "0x47810234"
        desc = "This register allows to enable/disable the module to set status bits, on an event-by-event basis. SD_IE[31:16] = Error Interrupt Status Enable. SD_IE[15:0] = Normal Interrupt Status Enable."
        type = "MMC_SD_IE__bitfield"
    }
    "MMCHS2_SD_ISE" {
        access = "memorymapped"
        width = "32"
        address = "0x47810238"
        desc = "This register allows you to enable/disable the module to set status bits, on an event-by-event basis. SD_ISE[31:16] = Error Interrupt Signal Enable. SD_ISE[15:0] = Normal Interrupt Signal Enable."
        type = "MMC_SD_ISE__bitfield"
    }
    "MMCHS2_SD_PSTATE" {
        access = "memorymapped"
        width = "32"
        address = "0x47810224"
        desc = "The Host can get the status of the Host controller from this 32-bit read only register."
        type = "MMC_SD_PSTATE__bitfield"
    }
    "MMCHS2_SD_PWCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x47810130"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage."
        type = "MMC_SD_PWCNT__bitfield"
    }
    "MMCHS2_SD_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x478102fc"
        desc = "This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. SD_REV[31:16] = Host Controller Version. SD_REV[15:0] = Slot Interrupt Status."
        type = "MMC_SD_REV__bitfield"
    }
    "MMCHS2_SD_RSP10" {
        access = "memorymapped"
        width = "32"
        address = "0x47810210"
        desc = "This 32-bit register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6."
        type = "MMC_SD_RSP10__bitfield"
    }
    "MMCHS2_SD_RSP32" {
        access = "memorymapped"
        width = "32"
        address = "0x47810214"
        desc = "This 32-bit register holds bits positions [63:32] of command response type R2."
        type = "MMC_SD_RSP32__bitfield"
    }
    "MMCHS2_SD_RSP54" {
        access = "memorymapped"
        width = "32"
        address = "0x47810218"
        desc = "This 32-bit register holds bits positions [95:64] of command response type R2."
        type = "MMC_SD_RSP54__bitfield"
    }
    "MMCHS2_SD_RSP76" {
        access = "memorymapped"
        width = "32"
        address = "0x4781021c"
        desc = "This 32-bit register holds bits positions [127:96] of command response type R2."
        type = "MMC_SD_RSP76__bitfield"
    }
    "MMCHS2_SD_SDMASA" {
        access = "memorymapped"
        width = "32"
        address = "0x47810200"
        desc = "This register is used to program a mmc counter to delay command transfers after activating the PAD power. This value depends on PAD characteristics and voltage."
        type = "MMC_SD_SDMASA__bitfield"
    }
    "MMCHS2_SD_STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47810230"
        desc = "The interrupt status regroups all the status of the module internal events that can generate an interrupt. SD_STAT[31:16] = Error Interrupt Status. SD_STAT[15:0] = Normal Interrupt Status. The error bits are located in the upper 16 bits of the SD_STAT register. All bits are cleared by writing a 1 to them. Additionally, bits 15 and 8 serve as special error bits. These cannot be cleared by writing a 1 to them. Bit 15 (ERRI) is automatically cleared when the error causing to ERRI to be set is handled. (that is, when bits 31:16 are cleared, bit 15 will be automatically cleared). Bit 8 (CIRQ) is cleared by writing a 0 to SD_IE[8] (masking the interrupt) and servicing the interrupt."
        type = "MMC_SD_STAT__bitfield"
    }
    "MMCHS2_SD_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x47810110"
        desc = "This register allows controlling various parameters of the OCP interface."
        type = "MMC_SD_SYSCONFIG__bitfield"
    }
    "MMCHS2_SD_SYSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4781022c"
        desc = "This register defines the system controls to set software resets, clock frequency management and data timeout. SD_SYSCTL[31:24] = Software resets. SD_SYSCTL[23:16] = Timeout control. SD_SYSCTL[15:0] = Clock control."
        type = "MMC_SD_SYSCTL__bitfield"
    }
    "MMCHS2_SD_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x47810114"
        desc = "This register provides status information about the module excluding the interrupt status information."
        type = "MMC_SD_SYSSTATUS__bitfield"
    }
    "MMCHS2_SD_SYSTEST" {
        access = "memorymapped"
        width = "32"
        address = "0x47810128"
        desc = "This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. In SYSTEST mode, a write into SD_CMD register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size (SD_BLK[10:0] BLEN bits) and the Blocks count for current transfer (SD_BLK[31:16] NBLK bits) are needed to generate a Buffer write ready interrupt (SD_STAT[4] BWR bit) or a Buffer read ready interrupt (SD_STAT[5] BRR bit) and DMA requests if enabled. "
        type = "MMC_SD_SYSTEST__bitfield"
    }
    "MONTHS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e010"
        desc = "The MONTHS_REG is used to set the month in the year value of the current date. Months are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. Usual notation is taken for month value: 1 = January, 2 = February, continuing until 12 = December."
        type = "MONTHS_REG__bitfield"
    }
    "McASP0_ACLKRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48038070"
    }
    "McASP0_ACLKXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380b0"
    }
    "McASP0_AFSRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803806c"
    }
    "McASP0_AFSXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380ac"
    }
    "McASP0_AHCLKRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48038074"
    }
    "McASP0_AHCLKXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380b4"
    }
    "McASP0_AMUTE" {
        access = "memorymapped"
        width = "32"
        address = "0x48038048"
    }
    "McASP0_DITCSRA0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038100"
    }
    "McASP0_DITCSRA1" {
        access = "memorymapped"
        width = "32"
        address = "0x48038104"
    }
    "McASP0_DITCSRA2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038108"
    }
    "McASP0_DITCSRA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803810c"
    }
    "McASP0_DITCSRA4" {
        access = "memorymapped"
        width = "32"
        address = "0x48038110"
    }
    "McASP0_DITCSRA5" {
        access = "memorymapped"
        width = "32"
        address = "0x48038114"
    }
    "McASP0_DITCSRB0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038118"
    }
    "McASP0_DITCSRB1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803811c"
    }
    "McASP0_DITCSRB2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038120"
    }
    "McASP0_DITCSRB3" {
        access = "memorymapped"
        width = "32"
        address = "0x48038124"
    }
    "McASP0_DITCSRB4" {
        access = "memorymapped"
        width = "32"
        address = "0x48038128"
    }
    "McASP0_DITCSRB5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803812c"
    }
    "McASP0_DITCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48038050"
    }
    "McASP0_DITUDRA0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038130"
    }
    "McASP0_DITUDRA1" {
        access = "memorymapped"
        width = "32"
        address = "0x48038134"
    }
    "McASP0_DITUDRA2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038138"
    }
    "McASP0_DITUDRA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803813c"
    }
    "McASP0_DITUDRA4" {
        access = "memorymapped"
        width = "32"
        address = "0x48038140"
    }
    "McASP0_DITUDRA5" {
        access = "memorymapped"
        width = "32"
        address = "0x48038144"
    }
    "McASP0_DITUDRB0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038148"
    }
    "McASP0_DITUDRB1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803814c"
    }
    "McASP0_DITUDRB2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038150"
    }
    "McASP0_DITUDRB3" {
        access = "memorymapped"
        width = "32"
        address = "0x48038154"
    }
    "McASP0_DITUDRB4" {
        access = "memorymapped"
        width = "32"
        address = "0x48038158"
    }
    "McASP0_DITUDRB5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803815c"
    }
    "McASP0_DLBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803804c"
    }
    "McASP0_GBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48038044"
    }
    "McASP0_PDCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48038020"
    }
    "McASP0_PDIN" {
        access = "memorymapped"
        width = "32"
        address = "0x4803801c"
    }
    "McASP0_PDIR" {
        access = "memorymapped"
        width = "32"
        address = "0x48038014"
    }
    "McASP0_PDOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x48038018"
    }
    "McASP0_PDSET" {
        access = "memorymapped"
        width = "32"
        address = "0x4803801c"
    }
    "McASP0_PFUNC" {
        access = "memorymapped"
        width = "32"
        address = "0x48038010"
    }
    "McASP0_RBUF0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038280"
    }
    "McASP0_RBUF1" {
        access = "memorymapped"
        width = "32"
        address = "0x48038284"
    }
    "McASP0_RBUF2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038288"
    }
    "McASP0_RBUF3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803828c"
    }
    "McASP0_RCLKCHK" {
        access = "memorymapped"
        width = "32"
        address = "0x48038088"
    }
    "McASP0_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x48038000"
    }
    "McASP0_REVTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803808c"
    }
    "McASP0_RFIFOCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48039008"
    }
    "McASP0_RFIFOSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x4803900c"
    }
    "McASP0_RFMT" {
        access = "memorymapped"
        width = "32"
        address = "0x48038068"
    }
    "McASP0_RGBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48038060"
    }
    "McASP0_RINTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803807c"
    }
    "McASP0_RMASK" {
        access = "memorymapped"
        width = "32"
        address = "0x48038064"
    }
    "McASP0_RSLOT" {
        access = "memorymapped"
        width = "32"
        address = "0x48038084"
    }
    "McASP0_RSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48038080"
    }
    "McASP0_RTDM" {
        access = "memorymapped"
        width = "32"
        address = "0x48038078"
    }
    "McASP0_SRCTL0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038180"
    }
    "McASP0_SRCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x48038184"
    }
    "McASP0_SRCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038188"
    }
    "McASP0_SRCTL3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803818c"
    }
    "McASP0_WFIFOCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48039000"
    }
    "McASP0_WFIFOSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x48039004"
    }
    "McASP0_XBUF0" {
        access = "memorymapped"
        width = "32"
        address = "0x48038200"
    }
    "McASP0_XBUF1" {
        access = "memorymapped"
        width = "32"
        address = "0x48038204"
    }
    "McASP0_XBUF2" {
        access = "memorymapped"
        width = "32"
        address = "0x48038208"
    }
    "McASP0_XBUF3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803820c"
    }
    "McASP0_XCLKCHK" {
        access = "memorymapped"
        width = "32"
        address = "0x480380c8"
    }
    "McASP0_XEVTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380cc"
    }
    "McASP0_XFMT" {
        access = "memorymapped"
        width = "32"
        address = "0x480380a8"
    }
    "McASP0_XGBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380a0"
    }
    "McASP0_XINTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x480380bc"
    }
    "McASP0_XMASK" {
        access = "memorymapped"
        width = "32"
        address = "0x480380a4"
    }
    "McASP0_XSLOT" {
        access = "memorymapped"
        width = "32"
        address = "0x480380c4"
    }
    "McASP0_XSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x480380c0"
    }
    "McASP0_XTDM" {
        access = "memorymapped"
        width = "32"
        address = "0x480380b8"
    }
    "McASP1_ACLKRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c070"
    }
    "McASP1_ACLKXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0b0"
    }
    "McASP1_AFSRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c06c"
    }
    "McASP1_AFSXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0ac"
    }
    "McASP1_AHCLKRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c074"
    }
    "McASP1_AHCLKXCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0b4"
    }
    "McASP1_AMUTE" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c048"
    }
    "McASP1_DITCSRA0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c100"
    }
    "McASP1_DITCSRA1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c104"
    }
    "McASP1_DITCSRA2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c108"
    }
    "McASP1_DITCSRA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c10c"
    }
    "McASP1_DITCSRA4" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c110"
    }
    "McASP1_DITCSRA5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c114"
    }
    "McASP1_DITCSRB0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c118"
    }
    "McASP1_DITCSRB1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c11c"
    }
    "McASP1_DITCSRB2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c120"
    }
    "McASP1_DITCSRB3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c124"
    }
    "McASP1_DITCSRB4" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c128"
    }
    "McASP1_DITCSRB5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c12c"
    }
    "McASP1_DITCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c050"
    }
    "McASP1_DITUDRA0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c130"
    }
    "McASP1_DITUDRA1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c134"
    }
    "McASP1_DITUDRA2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c138"
    }
    "McASP1_DITUDRA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c13c"
    }
    "McASP1_DITUDRA4" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c140"
    }
    "McASP1_DITUDRA5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c144"
    }
    "McASP1_DITUDRB0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c148"
    }
    "McASP1_DITUDRB1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c14c"
    }
    "McASP1_DITUDRB2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c150"
    }
    "McASP1_DITUDRB3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c154"
    }
    "McASP1_DITUDRB4" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c158"
    }
    "McASP1_DITUDRB5" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c15c"
    }
    "McASP1_DLBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c04c"
    }
    "McASP1_GBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c044"
    }
    "McASP1_PDCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c020"
    }
    "McASP1_PDIN" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c01c"
    }
    "McASP1_PDIR" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c014"
    }
    "McASP1_PDOUT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c018"
    }
    "McASP1_PDSET" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c01c"
    }
    "McASP1_PFUNC" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c010"
    }
    "McASP1_RBUF0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c280"
    }
    "McASP1_RBUF1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c284"
    }
    "McASP1_RBUF2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c288"
    }
    "McASP1_RBUF3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c28c"
    }
    "McASP1_RCLKCHK" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c088"
    }
    "McASP1_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c000"
    }
    "McASP1_REVTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c08c"
    }
    "McASP1_RFIFOCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803d008"
    }
    "McASP1_RFIFOSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x4803d00c"
    }
    "McASP1_RFMT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c068"
    }
    "McASP1_RGBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c060"
    }
    "McASP1_RINTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c07c"
    }
    "McASP1_RMASK" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c064"
    }
    "McASP1_RSLOT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c084"
    }
    "McASP1_RSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c080"
    }
    "McASP1_RTDM" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c078"
    }
    "McASP1_SRCTL0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c180"
    }
    "McASP1_SRCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c184"
    }
    "McASP1_SRCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c188"
    }
    "McASP1_SRCTL3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c18c"
    }
    "McASP1_WFIFOCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803d000"
    }
    "McASP1_WFIFOSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x4803d004"
    }
    "McASP1_XBUF0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c200"
    }
    "McASP1_XBUF1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c204"
    }
    "McASP1_XBUF2" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c208"
    }
    "McASP1_XBUF3" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c20c"
    }
    "McASP1_XCLKCHK" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0c8"
    }
    "McASP1_XEVTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0cc"
    }
    "McASP1_XFMT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0a8"
    }
    "McASP1_XGBLCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0a0"
    }
    "McASP1_XINTCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0bc"
    }
    "McASP1_XMASK" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0a4"
    }
    "McASP1_XSLOT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0c4"
    }
    "McASP1_XSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0c0"
    }
    "McASP1_XTDM" {
        access = "memorymapped"
        width = "32"
        address = "0x4803c0b8"
    }
    "McSPI0_CH0CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x4803012c"
    }
    "McSPI0_CH0CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x48030134"
    }
    "McSPI0_CH0STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48030130"
    }
    "McSPI0_CH1CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x48030140"
    }
    "McSPI0_CH1CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x48030148"
    }
    "McSPI0_CH1STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48030144"
    }
    "McSPI0_CH2CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x48030154"
    }
    "McSPI0_CH2CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803015c"
    }
    "McSPI0_CH2STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48030158"
    }
    "McSPI0_CH3CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x48030168"
    }
    "McSPI0_CH3CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x48030170"
    }
    "McSPI0_CH3STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x4803016c"
    }
    "McSPI0_DAFRX" {
        access = "memorymapped"
        width = "32"
        address = "0x480301a0"
    }
    "McSPI0_DAFTX" {
        access = "memorymapped"
        width = "32"
        address = "0x48030180"
    }
    "McSPI0_IRQENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x4803011c"
    }
    "McSPI0_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48030118"
    }
    "McSPI0_MODULCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x48030128"
    }
    "McSPI0_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x48030000"
    }
    "McSPI0_RX0" {
        access = "memorymapped"
        width = "32"
        address = "0x4803013c"
    }
    "McSPI0_RX1" {
        access = "memorymapped"
        width = "32"
        address = "0x48030150"
    }
    "McSPI0_RX2" {
        access = "memorymapped"
        width = "32"
        address = "0x48030164"
    }
    "McSPI0_RX3" {
        access = "memorymapped"
        width = "32"
        address = "0x48030178"
    }
    "McSPI0_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48030110"
    }
    "McSPI0_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x48030114"
    }
    "McSPI0_SYST" {
        access = "memorymapped"
        width = "32"
        address = "0x48030124"
    }
    "McSPI0_TX0" {
        access = "memorymapped"
        width = "32"
        address = "0x48030138"
    }
    "McSPI0_TX1" {
        access = "memorymapped"
        width = "32"
        address = "0x4803014c"
    }
    "McSPI0_TX2" {
        access = "memorymapped"
        width = "32"
        address = "0x48030160"
    }
    "McSPI0_TX3" {
        access = "memorymapped"
        width = "32"
        address = "0x48030174"
    }
    "McSPI0_XFERLEVEL" {
        access = "memorymapped"
        width = "32"
        address = "0x4803017c"
    }
    "McSPI1_CH0CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x481a012c"
    }
    "McSPI1_CH0CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0134"
    }
    "McSPI1_CH0STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0130"
    }
    "McSPI1_CH1CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0140"
    }
    "McSPI1_CH1CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0148"
    }
    "McSPI1_CH1STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0144"
    }
    "McSPI1_CH2CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0154"
    }
    "McSPI1_CH2CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a015c"
    }
    "McSPI1_CH2STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0158"
    }
    "McSPI1_CH3CONF" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0168"
    }
    "McSPI1_CH3CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0170"
    }
    "McSPI1_CH3STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x481a016c"
    }
    "McSPI1_DAFRX" {
        access = "memorymapped"
        width = "32"
        address = "0x481a01a0"
    }
    "McSPI1_DAFTX" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0180"
    }
    "McSPI1_IRQENABLE" {
        access = "memorymapped"
        width = "32"
        address = "0x481a011c"
    }
    "McSPI1_IRQSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0118"
    }
    "McSPI1_MODULCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0128"
    }
    "McSPI1_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0000"
    }
    "McSPI1_RX0" {
        access = "memorymapped"
        width = "32"
        address = "0x481a013c"
    }
    "McSPI1_RX1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0150"
    }
    "McSPI1_RX2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0164"
    }
    "McSPI1_RX3" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0178"
    }
    "McSPI1_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0110"
    }
    "McSPI1_SYSSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0114"
    }
    "McSPI1_SYST" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0124"
    }
    "McSPI1_TX0" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0138"
    }
    "McSPI1_TX1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a014c"
    }
    "McSPI1_TX2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0160"
    }
    "McSPI1_TX3" {
        access = "memorymapped"
        width = "32"
        address = "0x481a0174"
    }
    "McSPI1_XFERLEVEL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a017c"
    }
    "Multicast_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100908"
    }
    "Multicast_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10093c"
    }
    "Multiple_Collision_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100950"
    }
    "Net_Octets" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100980"
    }
    "Oversize_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100918"
    }
    "PEND0" {
        access = "memorymapped"
        width = "32"
        address = "0x47404090"
        type = "PEND0__bitfield"
    }
    "PEND1" {
        access = "memorymapped"
        width = "32"
        address = "0x47404094"
        type = "PEND1__bitfield"
    }
    "PEND2" {
        access = "memorymapped"
        width = "32"
        address = "0x47404098"
        type = "PEND2__bitfield"
    }
    "PEND3" {
        access = "memorymapped"
        width = "32"
        address = "0x4740409c"
        type = "PEND3__bitfield"
    }
    "PEND4" {
        access = "memorymapped"
        width = "32"
        address = "0x474040a0"
        type = "PEND4__bitfield"
    }
    "PERF_CNT_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000080"
        type = "PERF_CNT_1__bitfield"
    }
    "PERF_CNT_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000084"
        type = "PERF_CNT_2__bitfield"
    }
    "PERF_CNT_CFG" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000088"
        type = "PERF_CNT_CFG__bitfield"
    }
    "PERF_CNT_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00008c"
        type = "PERF_CNT_SEL__bitfield"
    }
    "PERF_CNT_TIM" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000090"
        type = "PERF_CNT_TIM__bitfield"
    }
    "PM_CEFUSE_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01200"
        desc = "This register controls the CEFUSE power state to reach upon a domain sleep transition"
        type = "PM_CEFUSE_PWRSTCTRL__bitfield"
    }
    "PM_CEFUSE_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01204"
        desc = "This register provides a status on the current CEFUSE power domain state. [warm reset insensitive]"
        type = "PM_CEFUSE_PWRSTST__bitfield"
    }
    "PM_GFX_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01100"
        desc = "This register controls the GFX power state to reach upon a domain sleep transition."
        type = "PM_GFX_PWRSTCTRL__bitfield"
    }
    "PM_GFX_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01110"
        desc = "This register provides a status on the current GFX power domain state.  [warm reset insensitive]"
        type = "PM_GFX_PWRSTST__bitfield"
    }
    "PM_MPU_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00e00"
        desc = "This register controls the MPU power state to reach upon mpu domain sleep transition"
        type = "PM_MPU_PWRSTCTRL__bitfield"
    }
    "PM_MPU_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00e04"
        desc = "This register provides a status on the current MPU power domain state0. [warm reset insensitive]"
        type = "PM_MPU_PWRSTST__bitfield"
    }
    "PM_PER_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00c0c"
        desc = "Controls the power state of PER power domain"
        type = "PM_PER_PWRSTCTRL__bitfield"
    }
    "PM_PER_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00c08"
        desc = "This register provides a status on the current PER power domain state. [warm reset insensitive]"
        type = "PM_PER_PWRSTST__bitfield"
    }
    "PM_RTC_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01000"
        desc = "This register controls the RTC power state to reach upon mpu domain sleep transition"
        type = "PM_RTC_PWRSTCTRL__bitfield"
    }
    "PM_RTC_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01004"
        desc = "This register provides a status on the current RTC power domain state0. [warm reset insensitive]"
        type = "PM_RTC_PWRSTST__bitfield"
    }
    "PM_WKUP_PWRSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00d04"
        desc = "Controls power state of WKUP power domain"
        type = "PM_WKUP_PWRSTCTRL__bitfield"
    }
    "PM_WKUP_PWRSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00d08"
        desc = "This register provides a status on the current WKUP power domain state. [warm reset insensitive]"
        type = "PM_WKUP_PWRSTST__bitfield"
    }
    "PRI_COS_MAP" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000100"
        type = "PRI_COS_MAP__bitfield"
    }
    "PRM_IRQENABLE_M3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00b10"
        desc = "This register is used to enable and disable events used to trigger MPU interrupt activation. "
        type = "PRM_IRQENABLE_M__bitfield"
    }
    "PRM_IRQENABLE_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00b08"
        desc = "This register is used to enable and disable events used to trigger MPU interrupt activation. "
        type = "PRM_IRQENABLE_M__bitfield"
    }
    "PRM_IRQSTATUS_M3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00b0c"
        desc = "This register provides status on MPU interrupt events. An event is logged whether interrupt generation for the event  is enabled or not. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared."
        type = "PRM_IRQSTATUS_M__bitfield"
    }
    "PRM_IRQSTATUS_MPU" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00b04"
        desc = "This register provides status on MPU interrupt events. An event is logged whether interrupt generation for the event  is enabled or not. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared."
        type = "PRM_IRQSTATUS_M__bitfield"
    }
    "PRM_LDO_SRAM_CORE_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f14"
        desc = "Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]"
        type = "PRM_LDO_SRAM__CTRL__bitfield"
    }
    "PRM_LDO_SRAM_CORE_SETUP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f10"
        desc = "Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive]"
        type = "PRM_LDO_SRAM__SETUP__bitfield"
    }
    "PRM_LDO_SRAM_MPU_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f1c"
        desc = "Control and status of the SRAM LDO for MPU voltage domain. [warm reset insensitive]"
        type = "PRM_LDO_SRAM__CTRL__bitfield"
    }
    "PRM_LDO_SRAM_MPU_SETUP" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f18"
        desc = "Setup of the SRAM LDO for MPU voltage domain. [warm reset insensitive]"
        type = "PRM_LDO_SRAM__SETUP__bitfield"
    }
    "PRM_RSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f00"
        desc = "Global software cold and warm reset control. This register is auto-cleared.  Only write 1 is possible. A read returns 0 only."
        type = "PRM_RSTCTRL__bitfield"
    }
    "PRM_RSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f08"
        desc = "This register logs the global reset sources. Each bit is set upon release of the domain reset signal.  Must be cleared by software. [warm reset insensitive]"
        type = "PRM_RSTST__bitfield"
    }
    "PRM_RSTTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f04"
        desc = "Reset duration control. [warm reset insensitive]"
        type = "PRM_RSTTIME__bitfield"
    }
    "PRM_SRAM_COUNT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00f0c"
        desc = "Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive]"
        type = "PRM_SRAM_COUNT__bitfield"
    }
    "PWMSS0_CLKCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48300008"
        desc = "The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control."
        type = "PWMSS_CLKCONFIG__bitfield"
    }
    "PWMSS0_CLKSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4830000c"
        desc = "The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status."
        type = "PWMSS_CLKSTATUS__bitfield"
    }
    "PWMSS0_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x48300000"
        desc = "The IP revision register is used by software to track features, bugs, and compatibility."
        type = "PWMSS_IDVER__bitfield"
    }
    "PWMSS0_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48300004"
        desc = "The system configuration register is used for clock management configuration."
        type = "PWMSS_SYSCONFIG__bitfield"
    }
    "PWMSS1_CLKCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48302008"
        desc = "The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control."
        type = "PWMSS_CLKCONFIG__bitfield"
    }
    "PWMSS1_CLKSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4830200c"
        desc = "The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status."
        type = "PWMSS_CLKSTATUS__bitfield"
    }
    "PWMSS1_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x48302000"
        desc = "The IP revision register is used by software to track features, bugs, and compatibility."
        type = "PWMSS_IDVER__bitfield"
    }
    "PWMSS1_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48302004"
        desc = "The system configuration register is used for clock management configuration."
        type = "PWMSS_SYSCONFIG__bitfield"
    }
    "PWMSS2_CLKCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48304008"
        desc = "The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control."
        type = "PWMSS_CLKCONFIG__bitfield"
    }
    "PWMSS2_CLKSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4830400c"
        desc = "The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status."
        type = "PWMSS_CLKSTATUS__bitfield"
    }
    "PWMSS2_IDVER" {
        access = "memorymapped"
        width = "32"
        address = "0x48304000"
        desc = "The IP revision register is used by software to track features, bugs, and compatibility."
        type = "PWMSS_IDVER__bitfield"
    }
    "PWMSS2_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x48304004"
        desc = "The system configuration register is used for clock management configuration."
        type = "PWMSS_SYSCONFIG__bitfield"
    }
    "PWR_MGMT_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000038"
        type = "PWR_MGMT_CTRL__bitfield"
    }
    "PWR_MGMT_CTRL_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00003c"
        type = "PWR_MGMT_CTRL_SHDW__bitfield"
    }
    "Pause_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10090c"
    }
    "Pause_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100940"
    }
    "QMEMCTRL0" {
        access = "memorymapped"
        width = "32"
        address = "0x47405004"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL1" {
        access = "memorymapped"
        width = "32"
        address = "0x47405014"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL2" {
        access = "memorymapped"
        width = "32"
        address = "0x47405024"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL3" {
        access = "memorymapped"
        width = "32"
        address = "0x47405034"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL4" {
        access = "memorymapped"
        width = "32"
        address = "0x47405044"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL5" {
        access = "memorymapped"
        width = "32"
        address = "0x47405054"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL6" {
        access = "memorymapped"
        width = "32"
        address = "0x47405064"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMCTRL7" {
        access = "memorymapped"
        width = "32"
        address = "0x47405074"
        type = "QMEMCTRL__bitfield"
    }
    "QMEMRBASE0" {
        access = "memorymapped"
        width = "32"
        address = "0x47405000"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE1" {
        access = "memorymapped"
        width = "32"
        address = "0x47405010"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE2" {
        access = "memorymapped"
        width = "32"
        address = "0x47405020"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE3" {
        access = "memorymapped"
        width = "32"
        address = "0x47405030"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE4" {
        access = "memorymapped"
        width = "32"
        address = "0x47405040"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE5" {
        access = "memorymapped"
        width = "32"
        address = "0x47405050"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE6" {
        access = "memorymapped"
        width = "32"
        address = "0x47405060"
        type = "QMEMRBASE__bitfield"
    }
    "QMEMRBASE7" {
        access = "memorymapped"
        width = "32"
        address = "0x47405070"
        type = "QMEMRBASE__bitfield"
    }
    "QMGRREVID" {
        access = "memorymapped"
        width = "32"
        address = "0x47404000"
        type = "QMGRREVID__bitfield"
    }
    "QMGRRST" {
        access = "memorymapped"
        width = "32"
        address = "0x47404008"
        type = "QMGRRST__bitfield"
    }
    "QUEUE_0_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406000"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_0_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406004"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_0_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406008"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_0_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740600c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_0_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407000"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_0_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407004"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_0_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407008"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_100_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406640"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_100_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406644"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_100_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406648"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_100_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740664c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_100_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407640"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_100_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407644"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_100_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407648"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_101_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406650"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_101_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406654"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_101_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406658"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_101_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740665c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_101_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407650"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_101_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407654"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_101_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407658"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_102_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406660"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_102_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406664"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_102_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406668"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_102_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740666c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_102_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407660"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_102_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407664"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_102_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407668"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_103_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406670"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_103_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406674"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_103_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406678"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_103_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740667c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_103_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407670"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_103_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407674"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_103_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407678"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_104_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406680"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_104_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406684"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_104_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406688"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_104_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740668c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_104_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407680"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_104_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407684"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_104_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407688"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_105_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406690"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_105_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406694"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_105_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406698"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_105_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740669c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_105_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407690"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_105_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407694"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_105_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407698"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_106_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_106_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_106_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_106_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_106_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_106_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_106_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_107_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_107_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_107_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_107_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_107_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_107_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_107_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_108_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_108_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_108_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_108_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_108_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_108_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_108_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_109_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_109_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_109_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_109_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_109_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_109_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_109_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_10_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_10_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_10_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_10_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_10_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_10_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_10_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_110_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_110_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_110_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_110_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_110_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_110_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_110_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_111_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474066f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_111_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474066f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_111_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474066f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_111_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474066fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_111_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474076f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_111_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474076f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_111_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474076f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_112_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406700"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_112_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406704"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_112_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406708"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_112_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740670c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_112_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407700"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_112_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407704"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_112_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407708"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_113_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406710"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_113_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406714"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_113_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406718"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_113_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740671c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_113_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407710"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_113_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407714"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_113_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407718"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_114_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406720"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_114_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406724"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_114_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406728"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_114_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740672c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_114_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407720"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_114_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407724"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_114_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407728"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_115_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406730"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_115_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406734"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_115_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406738"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_115_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740673c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_115_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407730"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_115_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407734"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_115_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407738"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_116_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406740"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_116_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406744"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_116_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406748"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_116_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740674c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_116_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407740"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_116_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407744"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_116_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407748"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_117_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406750"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_117_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406754"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_117_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406758"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_117_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740675c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_117_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407750"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_117_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407754"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_117_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407758"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_118_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406760"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_118_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406764"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_118_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406768"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_118_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740676c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_118_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407760"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_118_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407764"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_118_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407768"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_119_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406770"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_119_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406774"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_119_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406778"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_119_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740677c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_119_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407770"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_119_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407774"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_119_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407778"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_11_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_11_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_11_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_11_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_11_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_11_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_11_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_120_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406780"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_120_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406784"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_120_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406788"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_120_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740678c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_120_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407780"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_120_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407784"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_120_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407788"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_121_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406790"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_121_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406794"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_121_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406798"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_121_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740679c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_121_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407790"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_121_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407794"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_121_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407798"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_122_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_122_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_122_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_122_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_122_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_122_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_122_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_123_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_123_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_123_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_123_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_123_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_123_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_123_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_124_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_124_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_124_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_124_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_124_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_124_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_124_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_125_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_125_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_125_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_125_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_125_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_125_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_125_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_126_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_126_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_126_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_126_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_126_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_126_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_126_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_127_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474067f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_127_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474067f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_127_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474067f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_127_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474067fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_127_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474077f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_127_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474077f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_127_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474077f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_128_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406800"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_128_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406804"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_128_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406808"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_128_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740680c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_128_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407800"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_128_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407804"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_128_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407808"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_129_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406810"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_129_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406814"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_129_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406818"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_129_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740681c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_129_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407810"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_129_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407814"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_129_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407818"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_12_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_12_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_12_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_12_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_12_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_12_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_12_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_130_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406820"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_130_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406824"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_130_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406828"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_130_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740682c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_130_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407820"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_130_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407824"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_130_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407828"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_131_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406830"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_131_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406834"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_131_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406838"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_131_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740683c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_131_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407830"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_131_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407834"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_131_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407838"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_132_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406840"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_132_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406844"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_132_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406848"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_132_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740684c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_132_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407840"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_132_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407844"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_132_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407848"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_133_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406850"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_133_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406854"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_133_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406858"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_133_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740685c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_133_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407850"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_133_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407854"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_133_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407858"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_134_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406860"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_134_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406864"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_134_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406868"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_134_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740686c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_134_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407860"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_134_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407864"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_134_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407868"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_135_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406870"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_135_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406874"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_135_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406878"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_135_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740687c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_135_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407870"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_135_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407874"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_135_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407878"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_136_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406880"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_136_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406884"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_136_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406888"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_136_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740688c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_136_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407880"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_136_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407884"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_136_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407888"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_137_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406890"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_137_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406894"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_137_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406898"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_137_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740689c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_137_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407890"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_137_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407894"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_137_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407898"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_138_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_138_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_138_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_138_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_138_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_138_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_138_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_139_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_139_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_139_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_139_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_139_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_139_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_139_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_13_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_13_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_13_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_13_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_13_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_13_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_13_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_140_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_140_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_140_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_140_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_140_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_140_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_140_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_141_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_141_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_141_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_141_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_141_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_141_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_141_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_142_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_142_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_142_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_142_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_142_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_142_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_142_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_143_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474068f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_143_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474068f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_143_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474068f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_143_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474068fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_143_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474078f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_143_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474078f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_143_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474078f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_144_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406900"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_144_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406904"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_144_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406908"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_144_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740690c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_144_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407900"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_144_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407904"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_144_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407908"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_145_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406910"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_145_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406914"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_145_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406918"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_145_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740691c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_145_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407910"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_145_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407914"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_145_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407918"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_146_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406920"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_146_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406924"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_146_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406928"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_146_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740692c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_146_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407920"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_146_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407924"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_146_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407928"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_147_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406930"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_147_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406934"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_147_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406938"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_147_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740693c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_147_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407930"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_147_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407934"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_147_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407938"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_148_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406940"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_148_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406944"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_148_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406948"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_148_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740694c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_148_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407940"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_148_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407944"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_148_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407948"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_149_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406950"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_149_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406954"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_149_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406958"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_149_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740695c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_149_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407950"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_149_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407954"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_149_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407958"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_14_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_14_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_14_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_14_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_14_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_14_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_14_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_150_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406960"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_150_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406964"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_150_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406968"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_150_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740696c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_150_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407960"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_150_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407964"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_150_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407968"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_151_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406970"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_151_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406974"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_151_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406978"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_151_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740697c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_151_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407970"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_151_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407974"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_151_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407978"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_152_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406980"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_152_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406984"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_152_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406988"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_152_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740698c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_152_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407980"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_152_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407984"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_152_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407988"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_153_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406990"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_153_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406994"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_153_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406998"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_153_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740699c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_153_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407990"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_153_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407994"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_153_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407998"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_154_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474069a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_154_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474069a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_154_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474069a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_154_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474069ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_154_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474079a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_154_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474079a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_154_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474079a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_155_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474069b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_155_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474069b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_155_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474069b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_155_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474069bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_155_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474079b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_155_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474079b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_155_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474079b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_15_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474060f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_15_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474060f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_15_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474060f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_15_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474060fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_15_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474070f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_15_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474070f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_15_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474070f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_16_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406100"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_16_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406104"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_16_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406108"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_16_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740610c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_16_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407100"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_16_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407104"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_16_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407108"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_17_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406110"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_17_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406114"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_17_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406118"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_17_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740611c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_17_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407110"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_17_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407114"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_17_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407118"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_18_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406120"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_18_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406124"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_18_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406128"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_18_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740612c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_18_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407120"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_18_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407124"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_18_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407128"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_19_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406130"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_19_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406134"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_19_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406138"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_19_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740613c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_19_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407130"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_19_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407134"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_19_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407138"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_1_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406010"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_1_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406014"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_1_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406018"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_1_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740601c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_1_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407010"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_1_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407014"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_1_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407018"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_20_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406140"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_20_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406144"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_20_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406148"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_20_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740614c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_20_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407140"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_20_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407144"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_20_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407148"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_21_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406150"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_21_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406154"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_21_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406158"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_21_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740615c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_21_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407150"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_21_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407154"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_21_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407158"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_22_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406160"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_22_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406164"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_22_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406168"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_22_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740616c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_22_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407160"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_22_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407164"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_22_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407168"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_23_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406170"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_23_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406174"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_23_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406178"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_23_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740617c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_23_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407170"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_23_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407174"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_23_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407178"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_24_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406180"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_24_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406184"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_24_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406188"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_24_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740618c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_24_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407180"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_24_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407184"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_24_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407188"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_25_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406190"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_25_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406194"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_25_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406198"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_25_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740619c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_25_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407190"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_25_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407194"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_25_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407198"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_26_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_26_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_26_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_26_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_26_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_26_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_26_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_27_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_27_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_27_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_27_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_27_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_27_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_27_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_28_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_28_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_28_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_28_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_28_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_28_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_28_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_29_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_29_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_29_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_29_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_29_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_29_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_29_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_2_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406020"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_2_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406024"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_2_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406028"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_2_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740602c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_2_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407020"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_2_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407024"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_2_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407028"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_30_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_30_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_30_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_30_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_30_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_30_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_30_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_31_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474061f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_31_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474061f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_31_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474061f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_31_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474061fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_31_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474071f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_31_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474071f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_31_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474071f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_32_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406200"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_32_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406204"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_32_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406208"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_32_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740620c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_32_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407200"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_32_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407204"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_32_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407208"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_33_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406210"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_33_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406214"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_33_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406218"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_33_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740621c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_33_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407210"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_33_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407214"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_33_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407218"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_34_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406220"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_34_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406224"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_34_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406228"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_34_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740622c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_34_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407220"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_34_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407224"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_34_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407228"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_35_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406230"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_35_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406234"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_35_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406238"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_35_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740623c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_35_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407230"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_35_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407234"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_35_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407238"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_36_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406240"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_36_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406244"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_36_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406248"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_36_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740624c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_36_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407240"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_36_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407244"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_36_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407248"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_37_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406250"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_37_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406254"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_37_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406258"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_37_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740625c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_37_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407250"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_37_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407254"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_37_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407258"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_38_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406260"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_38_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406264"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_38_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406268"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_38_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740626c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_38_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407260"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_38_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407264"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_38_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407268"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_39_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406270"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_39_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406274"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_39_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406278"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_39_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740627c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_39_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407270"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_39_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407274"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_39_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407278"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_3_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406030"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_3_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406034"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_3_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406038"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_3_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740603c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_3_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407030"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_3_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407034"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_3_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407038"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_40_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406280"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_40_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406284"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_40_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406288"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_40_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740628c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_40_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407280"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_40_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407284"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_40_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407288"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_41_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406290"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_41_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406294"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_41_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406298"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_41_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740629c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_41_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407290"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_41_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407294"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_41_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407298"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_42_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_42_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_42_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_42_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_42_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_42_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_42_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_43_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_43_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_43_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_43_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_43_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_43_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_43_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_44_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_44_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_44_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_44_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_44_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_44_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_44_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_45_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_45_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_45_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_45_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_45_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_45_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_45_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_46_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_46_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_46_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_46_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_46_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_46_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_46_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_47_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474062f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_47_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474062f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_47_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474062f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_47_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474062fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_47_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474072f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_47_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474072f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_47_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474072f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_48_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406300"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_48_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406304"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_48_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406308"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_48_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740630c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_48_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407300"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_48_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407304"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_48_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407308"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_49_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406310"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_49_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406314"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_49_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406318"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_49_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740631c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_49_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407310"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_49_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407314"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_49_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407318"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_4_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406040"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_4_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406044"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_4_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406048"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_4_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740604c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_4_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407040"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_4_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407044"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_4_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407048"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_50_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406320"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_50_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406324"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_50_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406328"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_50_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740632c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_50_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407320"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_50_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407324"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_50_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407328"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_51_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406330"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_51_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406334"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_51_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406338"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_51_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740633c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_51_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407330"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_51_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407334"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_51_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407338"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_52_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406340"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_52_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406344"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_52_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406348"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_52_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740634c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_52_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407340"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_52_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407344"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_52_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407348"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_53_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406350"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_53_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406354"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_53_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406358"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_53_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740635c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_53_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407350"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_53_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407354"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_53_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407358"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_54_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406360"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_54_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406364"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_54_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406368"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_54_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740636c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_54_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407360"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_54_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407364"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_54_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407368"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_55_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406370"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_55_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406374"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_55_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406378"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_55_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740637c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_55_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407370"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_55_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407374"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_55_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407378"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_56_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406380"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_56_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406384"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_56_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406388"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_56_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740638c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_56_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407380"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_56_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407384"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_56_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407388"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_57_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406390"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_57_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406394"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_57_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406398"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_57_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740639c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_57_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407390"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_57_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407394"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_57_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407398"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_58_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_58_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_58_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_58_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_58_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_58_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_58_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_59_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_59_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_59_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_59_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_59_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_59_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_59_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_5_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406050"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_5_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406054"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_5_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406058"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_5_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740605c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_5_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407050"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_5_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407054"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_5_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407058"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_60_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_60_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_60_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_60_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_60_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_60_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_60_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_61_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_61_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_61_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_61_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_61_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_61_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_61_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_62_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_62_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_62_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_62_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_62_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_62_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_62_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_63_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474063f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_63_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474063f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_63_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474063f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_63_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474063fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_63_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474073f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_63_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474073f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_63_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474073f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_64_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406400"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_64_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406404"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_64_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406408"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_64_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740640c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_64_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407400"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_64_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407404"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_64_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407408"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_65_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406410"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_65_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406414"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_65_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406418"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_65_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740641c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_65_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407410"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_65_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407414"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_65_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407418"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_66_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406420"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_66_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406424"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_66_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406428"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_66_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740642c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_66_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407420"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_66_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407424"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_66_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407428"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_67_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406430"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_67_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406434"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_67_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406438"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_67_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740643c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_67_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407430"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_67_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407434"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_67_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407438"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_68_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406440"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_68_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406444"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_68_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406448"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_68_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740644c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_68_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407440"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_68_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407444"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_68_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407448"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_69_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406450"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_69_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406454"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_69_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406458"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_69_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740645c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_69_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407450"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_69_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407454"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_69_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407458"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_6_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406060"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_6_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406064"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_6_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406068"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_6_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740606c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_6_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407060"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_6_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407064"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_6_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407068"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_70_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406460"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_70_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406464"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_70_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406468"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_70_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740646c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_70_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407460"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_70_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407464"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_70_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407468"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_71_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406470"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_71_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406474"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_71_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406478"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_71_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740647c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_71_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407470"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_71_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407474"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_71_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407478"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_72_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406480"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_72_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406484"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_72_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406488"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_72_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740648c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_72_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407480"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_72_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407484"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_72_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407488"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_73_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406490"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_73_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406494"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_73_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406498"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_73_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740649c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_73_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407490"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_73_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407494"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_73_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407498"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_74_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_74_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_74_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_74_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_74_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_74_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_74_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_75_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_75_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_75_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_75_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_75_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_75_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_75_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_76_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_76_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_76_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_76_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_76_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_76_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_76_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_77_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_77_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_77_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_77_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_77_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_77_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_77_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_78_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_78_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_78_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_78_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_78_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_78_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_78_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_79_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474064f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_79_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474064f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_79_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474064f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_79_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474064fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_79_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474074f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_79_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474074f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_79_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474074f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_7_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406070"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_7_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406074"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_7_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406078"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_7_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740607c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_7_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407070"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_7_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407074"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_7_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407078"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_80_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406500"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_80_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406504"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_80_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406508"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_80_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740650c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_80_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407500"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_80_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407504"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_80_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407508"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_81_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406510"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_81_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406514"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_81_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406518"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_81_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740651c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_81_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407510"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_81_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407514"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_81_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407518"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_82_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406520"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_82_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406524"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_82_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406528"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_82_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740652c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_82_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407520"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_82_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407524"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_82_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407528"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_83_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406530"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_83_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406534"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_83_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406538"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_83_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740653c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_83_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407530"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_83_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407534"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_83_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407538"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_84_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406540"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_84_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406544"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_84_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406548"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_84_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740654c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_84_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407540"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_84_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407544"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_84_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407548"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_85_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406550"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_85_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406554"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_85_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406558"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_85_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740655c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_85_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407550"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_85_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407554"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_85_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407558"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_86_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406560"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_86_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406564"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_86_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406568"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_86_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740656c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_86_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407560"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_86_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407564"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_86_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407568"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_87_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406570"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_87_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406574"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_87_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406578"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_87_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740657c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_87_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407570"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_87_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407574"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_87_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407578"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_88_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406580"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_88_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406584"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_88_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406588"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_88_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740658c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_88_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407580"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_88_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407584"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_88_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407588"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_89_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406590"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_89_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406594"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_89_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406598"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_89_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740659c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_89_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407590"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_89_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407594"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_89_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407598"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_8_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406080"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_8_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406084"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_8_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406088"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_8_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740608c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_8_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407080"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_8_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407084"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_8_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407088"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_90_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065a0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_90_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065a4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_90_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065a8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_90_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065ac"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_90_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075a0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_90_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075a4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_90_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075a8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_91_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065b0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_91_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065b4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_91_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065b8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_91_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065bc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_91_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075b0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_91_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075b4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_91_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075b8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_92_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065c0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_92_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065c4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_92_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065c8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_92_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065cc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_92_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075c0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_92_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075c4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_92_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075c8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_93_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065d0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_93_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065d4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_93_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065d8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_93_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065dc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_93_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075d0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_93_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075d4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_93_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075d8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_94_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065e0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_94_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065e4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_94_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065e8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_94_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065ec"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_94_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075e0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_94_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075e4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_94_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075e8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_95_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474065f0"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_95_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474065f4"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_95_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474065f8"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_95_D" {
        access = "memorymapped"
        width = "32"
        address = "0x474065fc"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_95_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x474075f0"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_95_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x474075f4"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_95_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x474075f8"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_96_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406600"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_96_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406604"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_96_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406608"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_96_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740660c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_96_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407600"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_96_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407604"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_96_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407608"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_97_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406610"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_97_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406614"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_97_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406618"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_97_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740661c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_97_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407610"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_97_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407614"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_97_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407618"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_98_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406620"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_98_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406624"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_98_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406628"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_98_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740662c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_98_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407620"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_98_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407624"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_98_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407628"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_99_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406630"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_99_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406634"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_99_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406638"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_99_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740663c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_99_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407630"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_99_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407634"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_99_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407638"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "QUEUE_9_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47406090"
        type = "QUEUE__A__bitfield"
    }
    "QUEUE_9_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47406094"
        type = "QUEUE__B__bitfield"
    }
    "QUEUE_9_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47406098"
        type = "QUEUE__C__bitfield"
    }
    "QUEUE_9_D" {
        access = "memorymapped"
        width = "32"
        address = "0x4740609c"
        type = "QUEUE__D__bitfield"
    }
    "QUEUE_9_STATUS_A" {
        access = "memorymapped"
        width = "32"
        address = "0x47407090"
        type = "QUEUE__STATUS_A__bitfield"
    }
    "QUEUE_9_STATUS_B" {
        access = "memorymapped"
        width = "32"
        address = "0x47407094"
        type = "QUEUE__STATUS_B__bitfield"
    }
    "QUEUE_9_STATUS_C" {
        access = "memorymapped"
        width = "32"
        address = "0x47407098"
        type = "QUEUE__STATUS_C__bitfield"
    }
    "RDWR_LVL_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000dc"
        desc = "Read-Write Leveling Control Register"
        type = "RDWR_LVL_CTRL__bitfield"
    }
    "RDWR_LVL_RMP_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000d8"
        type = "RDWR_LVL_RMP_CTRL__bitfield"
    }
    "RDWR_LVL_RMP_WIN" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000d4"
        desc = " "
        type = "RDWR_LVL_RMP_WIN__bitfield"
    }
    "RD_WR_EXEC_THRSH" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000120"
        type = "RD_WR_EXEC_THRSH__bitfield"
    }
    "READ_IDLE_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000098"
        type = "READ_IDLE_CTRL__bitfield"
    }
    "READ_IDLE_CTRL_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00009c"
        type = "READ_IDLE_CTRL_SHDW__bitfield"
    }
    "REVISION_PRM" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00b00"
        desc = "This register contains the IP revision code for the PRCM"
        type = "REVISION__bitfield"
    }
    "RM_GFX_RSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01104"
        desc = "This register controls the release of the GFX Domain resets."
        type = "RM_GFX_RSTCTRL__bitfield"
    }
    "RM_GFX_RSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e01114"
        desc = "This register logs the different reset sources of the GFX domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]"
        type = "RM_GFX_RSTST__bitfield"
    }
    "RM_MPU_RSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00e08"
        desc = "This register  logs  the different reset sources of the ALWON domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]"
        type = "RM_MPU_RSTST__bitfield"
    }
    "RM_PER_RSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00c00"
        desc = "This register controls the release of the PER Domain resets."
        type = "RM_PER_RSTCTRL__bitfield"
    }
    "RM_WKUP_RSTCTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00d00"
        desc = "This register controls the release of the ALWAYS ON Domain resets."
        type = "RM_WKUP_RSTCTRL__bitfield"
    }
    "RM_WKUP_RSTST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e00d0c"
        desc = "This register  logs  the different reset sources of the ALWON domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]"
        type = "RM_WKUP_RSTST__bitfield"
    }
    "RTC_COMP_LSB_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e04c"
        desc = "The COMP_LSB_REG is used to program the LSB value of the 32 kHz periods to be added to the 32 kHz counter every hour. This is used to compensate the oscillator drift. The COMP_LSB_REG works together with the compensation (MSB) register (COMP_MSB_REG). The AUTOCOMP bit in the control register (CTRL_REG) must be enabled for compensation to take place. This register must be written in two's complement. That means that to add one 32-kHz oscillator period every hour, the ARM must write FFFFh into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. To remove one 32-kHz oscillator period every hour, the ARM must write 0001h into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. The 7FFFh value is forbidden."
        type = "RTC_COMP_LSB_REG__bitfield"
    }
    "RTC_COMP_MSB_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e050"
        desc = "The COMP_MSB_REG is used to program the MSB value of the 32 kHz periods to be added to the 32 kHz counter every hour. This is used to compensate the oscillator drift. The COMP_MSB_REG works together with the compensation (LSB) register (COMP_LSB_REG) to set the hourly oscillator compensation value. The AUTOCOMP bit in the control register (CTRL_REG) must be enabled for compensation to take place. This register must be written in two's complement. That means that to add one 32-kHz oscillator period every hour, the ARM must write FFFFh into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. To remove one 32-kHz oscillator period every hour, the ARM must write 0001h into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG. The 7FFFh value is forbidden."
        type = "RTC_COMP_MSB_REG__bitfield"
    }
    "RTC_CTRL_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e040"
        desc = "The RTC_CTRL_REG contains the controls to enable/disable the RTC, set the 12/24 hour time mode, to enable the 30 second rounding feature, and to STOP/START the RTC. The SET_32_COUNTER bit must only be used when the RTC is frozen. The RTC_DISABLE bit must only be used to completely disable the RTC function. When this bit is set, the 32 kHz clock is gated and the RTC is frozen. From this point, resetting this bit to zero can lead to unexpected behavior. This bit should only be used if the RTC function is unwanted in the application, in order to save power. MODE_12_24: It is possible to switch between the two modes at any time without disturbing the RTC. Read or write is always performed with the current mode. Auto compensation is enabled by the AUTO_COMP bit. If the COMP_REG value is positive, compensation occurs after the second change event. COMP_REG cycles are removed from the next second. If the COMP_REG value is negative, compensation occurs before the second change event. COMP_REG cycles are added to the current second. This enables it to compensate with one 32-kHz period accuracy each hour. The ROUND_30S bit is a toggle bit; the ARM can only write 1 and the RTC clears it. If the ARM sets the ROUND_30S bit and then reads it, the ARM reads 1 until the round-to-the-closest-minute is performed at the next second. The ARM can stop the RTC by clearing the STOP_RTC bit (owing to internal resynchronization, the RUN bit of the status register (STATUS_REG) must be checked to ensure that the RTC is frozen), then update TC values, and re-start the RTC by resetting the STOP_RTC bit."
        type = "RTC_CTRL_REG__bitfield"
    }
    "RTC_DEBOUNCE" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e09c"
        desc = "The debounce timer uses the 32768-Hz clock. It allows choosing the timing or the accuracy of debouncing . A register receives a bit from the reference pin. You will choose the timing if you use the debouncing like a timer, or you will choose the accuracy if you use the debouncing like a real debouncing. The debouncing will be finished when the reference pin will stay the same value (defined in DEBOUNCE_REG) for a defined time."
        type = "RTC_DEBOUNCE__bitfield"
    }
    "RTC_INTERRUPTS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e048"
        desc = "The RTC_INTERRUPTS_REG is used to enable or disable the RTC from generating interrupts. The timer interrupt and alarm interrupt can be controlled using this register. The ARM must respect the BUSY period to prevent spurious interrupt. To set a period timer interrupt, the respective period value must be set in the EVERY field. For example, to set a periodic timer interrupt for every hour, the EVERY field has to be set to 2. Along with this the IT_TIMER bit also has to be set for the periodic interrupt to be generated. IT_ALARM bit has to be set to generate an alarm interrupt."
        type = "RTC_INTERRUPTS_REG__bitfield"
    }
    "RTC_IRQWAKEEN" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e07c"
        type = "RTC_IRQWAKEEN__bitfield"
    }
    "RTC_OSC_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e054"
        type = "RTC_OSC_REG__bitfield"
    }
    "RTC_PMIC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e098"
        type = "RTC_PMIC__bitfield"
    }
    "RTC_REVISION" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e074"
        type = "RTC_REVISION__bitfield"
    }
    "RTC_SCRATCH0_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e060"
        desc = "The RTC_SCRATCH0_REG is used to hold some required values for the RTC register."
        type = "RTC_SCRATCH0_REG__bitfield"
    }
    "RTC_SCRATCH1_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e064"
        desc = "The RTC_SCRATCH1_REG is used to hold some required values for the RTC register."
        type = "RTC_SCRATCH1_REG__bitfield"
    }
    "RTC_SCRATCH2_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e068"
        desc = "The RTC_SCRATCH2_REG is used to hold some required values for the RTC register."
        type = "RTC_SCRATCH2_REG__bitfield"
    }
    "RTC_STATUS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e044"
        desc = "The RTC_STATUS_REG contains bits that signal the status of interrupts, events to the processor. Status for the alarm interrupt and timer events are notified by the register. The alarm interrupt keeps its low level until the ARM writes 1 in the ALARM bit of the RTC_STATUS_REG register. ALARM2: This bit will indicate the status of the alarm interrupt. Writing a 1 to the bit clears the interrupt. ALARM: This bit will indicate the status of the alarm interrupt. Writing a 1 to the bit clears the interrupt. 1D_EVENT1: This bit will indicate if a day event has occurred. An interrupt will be generated to the processor based on the masking of the interrupt controller. 1H_EVENT1: This bit will indicate if an hour event has occurred. An interrupt will be generated to the processor based on the masking of the interrupt controller. 1M_EVENT1: This bit will indicate if a minute event has occurred. An interrupt will be generated to the processor based on the masking of the interrupt controller. 1S_EVENT1: This bit will indicate if a second event has occurred. An interrupt will be generated to the processor based on the masking of the interrupt controller. RUN: This bit will indicate if RTC is frozen or it is running. The RUN bit shows the real state of the RTC. Indeed, because the STOP_RTC signal is resynchronized on 32-kHz clock the action of this bit is delayed. BUSY: This bit will give the status of RTC module. The Time and alarm registers can be modified only when this bit is 0. The timer interrupt is a negative edge sensitive low-level pulse (1 OCP cycle duration)."
        type = "RTC_STATUS_REG__bitfield"
    }
    "RTC_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e078"
        type = "RTC_SYSCONFIG__bitfield"
    }
    "RX0_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a60"
        desc = "CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX0_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a20"
        desc = "CPDMA_STATERAM RX 0 CHANNEL 0 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX1_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a64"
        desc = "CPDMA_STATERAM RX CHANNEL 1 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX1_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a24"
        desc = "CPDMA_STATERAM RX 1 CHANNEL 1 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX2_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a68"
        desc = "CPDMA_STATERAM RX CHANNEL 2 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX2_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a28"
        desc = "CPDMA_STATERAM RX 2 CHANNEL 2 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX3_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a6c"
        desc = "CPDMA_STATERAM RX CHANNEL 3 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX3_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a2c"
        desc = "CPDMA_STATERAM RX 3 CHANNEL 3 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX4_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a70"
        desc = "CPDMA_STATERAM RX CHANNEL 4 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX4_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a30"
        desc = "CPDMA_STATERAM RX 4 CHANNEL 4 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX5_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a74"
        desc = "CPDMA_STATERAM RX CHANNEL 5 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX5_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a34"
        desc = "CPDMA_STATERAM RX 5 CHANNEL 5 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX6_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a78"
        desc = "CPDMA_STATERAM RX CHANNEL 6 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX6_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a38"
        desc = "CPDMA_STATERAM RX 6 CHANNEL 6 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RX7_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a7c"
        desc = "CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER *"
        type = "RX_CP__bitfield"
    }
    "RX7_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a3c"
        desc = "CPDMA_STATERAM RX 7 CHANNEL 7 HEAD DESC POINTER *"
        type = "RX_HDP__bitfield"
    }
    "RXGCR0" {
        access = "memorymapped"
        width = "32"
        address = "0x47402808"
        type = "RXGCR__bitfield"
    }
    "RXGCR1" {
        access = "memorymapped"
        width = "32"
        address = "0x47402828"
        type = "RXGCR__bitfield"
    }
    "RXGCR10" {
        access = "memorymapped"
        width = "32"
        address = "0x47402948"
        type = "RXGCR__bitfield"
    }
    "RXGCR11" {
        access = "memorymapped"
        width = "32"
        address = "0x47402968"
        type = "RXGCR__bitfield"
    }
    "RXGCR12" {
        access = "memorymapped"
        width = "32"
        address = "0x47402988"
        type = "RXGCR__bitfield"
    }
    "RXGCR13" {
        access = "memorymapped"
        width = "32"
        address = "0x474029a8"
        type = "RXGCR__bitfield"
    }
    "RXGCR14" {
        access = "memorymapped"
        width = "32"
        address = "0x474029c8"
        type = "RXGCR__bitfield"
    }
    "RXGCR15" {
        access = "memorymapped"
        width = "32"
        address = "0x474029e8"
        type = "RXGCR__bitfield"
    }
    "RXGCR16" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a08"
        type = "RXGCR__bitfield"
    }
    "RXGCR17" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a28"
        type = "RXGCR__bitfield"
    }
    "RXGCR18" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a48"
        type = "RXGCR__bitfield"
    }
    "RXGCR19" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a68"
        type = "RXGCR__bitfield"
    }
    "RXGCR2" {
        access = "memorymapped"
        width = "32"
        address = "0x47402848"
        type = "RXGCR__bitfield"
    }
    "RXGCR20" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a88"
        type = "RXGCR__bitfield"
    }
    "RXGCR21" {
        access = "memorymapped"
        width = "32"
        address = "0x47402aa8"
        type = "RXGCR__bitfield"
    }
    "RXGCR22" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ac8"
        type = "RXGCR__bitfield"
    }
    "RXGCR23" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ae8"
        type = "RXGCR__bitfield"
    }
    "RXGCR24" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b08"
        type = "RXGCR__bitfield"
    }
    "RXGCR25" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b28"
        type = "RXGCR__bitfield"
    }
    "RXGCR26" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b48"
        type = "RXGCR__bitfield"
    }
    "RXGCR27" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b68"
        type = "RXGCR__bitfield"
    }
    "RXGCR28" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b88"
        type = "RXGCR__bitfield"
    }
    "RXGCR29" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ba8"
        type = "RXGCR__bitfield"
    }
    "RXGCR3" {
        access = "memorymapped"
        width = "32"
        address = "0x47402868"
        type = "RXGCR__bitfield"
    }
    "RXGCR4" {
        access = "memorymapped"
        width = "32"
        address = "0x47402888"
        type = "RXGCR__bitfield"
    }
    "RXGCR5" {
        access = "memorymapped"
        width = "32"
        address = "0x474028a8"
        type = "RXGCR__bitfield"
    }
    "RXGCR6" {
        access = "memorymapped"
        width = "32"
        address = "0x474028c8"
        type = "RXGCR__bitfield"
    }
    "RXGCR7" {
        access = "memorymapped"
        width = "32"
        address = "0x474028e8"
        type = "RXGCR__bitfield"
    }
    "RXGCR8" {
        access = "memorymapped"
        width = "32"
        address = "0x47402908"
        type = "RXGCR__bitfield"
    }
    "RXGCR9" {
        access = "memorymapped"
        width = "32"
        address = "0x47402928"
        type = "RXGCR__bitfield"
    }
    "RXHPCRA0" {
        access = "memorymapped"
        width = "32"
        address = "0x4740280c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740282c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA10" {
        access = "memorymapped"
        width = "32"
        address = "0x4740294c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA11" {
        access = "memorymapped"
        width = "32"
        address = "0x4740296c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA12" {
        access = "memorymapped"
        width = "32"
        address = "0x4740298c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA13" {
        access = "memorymapped"
        width = "32"
        address = "0x474029ac"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA14" {
        access = "memorymapped"
        width = "32"
        address = "0x474029cc"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA15" {
        access = "memorymapped"
        width = "32"
        address = "0x474029ec"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA16" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a0c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA17" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a2c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA18" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a4c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA19" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a6c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA2" {
        access = "memorymapped"
        width = "32"
        address = "0x4740284c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA20" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a8c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA21" {
        access = "memorymapped"
        width = "32"
        address = "0x47402aac"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA22" {
        access = "memorymapped"
        width = "32"
        address = "0x47402acc"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA23" {
        access = "memorymapped"
        width = "32"
        address = "0x47402aec"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA24" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b0c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA25" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b2c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA26" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b4c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA27" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b6c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA28" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b8c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA29" {
        access = "memorymapped"
        width = "32"
        address = "0x47402bac"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4740286c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA4" {
        access = "memorymapped"
        width = "32"
        address = "0x4740288c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA5" {
        access = "memorymapped"
        width = "32"
        address = "0x474028ac"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA6" {
        access = "memorymapped"
        width = "32"
        address = "0x474028cc"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA7" {
        access = "memorymapped"
        width = "32"
        address = "0x474028ec"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA8" {
        access = "memorymapped"
        width = "32"
        address = "0x4740290c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRA9" {
        access = "memorymapped"
        width = "32"
        address = "0x4740292c"
        type = "RXHPCRA__bitfield"
    }
    "RXHPCRB0" {
        access = "memorymapped"
        width = "32"
        address = "0x47402810"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB1" {
        access = "memorymapped"
        width = "32"
        address = "0x47402830"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB10" {
        access = "memorymapped"
        width = "32"
        address = "0x47402950"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB11" {
        access = "memorymapped"
        width = "32"
        address = "0x47402970"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB12" {
        access = "memorymapped"
        width = "32"
        address = "0x47402990"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB13" {
        access = "memorymapped"
        width = "32"
        address = "0x474029b0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB14" {
        access = "memorymapped"
        width = "32"
        address = "0x474029d0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB15" {
        access = "memorymapped"
        width = "32"
        address = "0x474029f0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB16" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a10"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB17" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a30"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB18" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a50"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB19" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a70"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB2" {
        access = "memorymapped"
        width = "32"
        address = "0x47402850"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB20" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a90"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB21" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ab0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB22" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ad0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB23" {
        access = "memorymapped"
        width = "32"
        address = "0x47402af0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB24" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b10"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB25" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b30"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB26" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b50"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB27" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b70"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB28" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b90"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB29" {
        access = "memorymapped"
        width = "32"
        address = "0x47402bb0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB3" {
        access = "memorymapped"
        width = "32"
        address = "0x47402870"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB4" {
        access = "memorymapped"
        width = "32"
        address = "0x47402890"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB5" {
        access = "memorymapped"
        width = "32"
        address = "0x474028b0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB6" {
        access = "memorymapped"
        width = "32"
        address = "0x474028d0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB7" {
        access = "memorymapped"
        width = "32"
        address = "0x474028f0"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB8" {
        access = "memorymapped"
        width = "32"
        address = "0x47402910"
        type = "RXHPCRB__bitfield"
    }
    "RXHPCRB9" {
        access = "memorymapped"
        width = "32"
        address = "0x47402930"
        type = "RXHPCRB__bitfield"
    }
    "Rx_Align_Code_Errors" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100914"
    }
    "Rx_CRC_Errors" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100910"
    }
    "Rx_DMA_Overruns" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10098c"
    }
    "Rx_Fragments" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100924"
    }
    "Rx_Jabbers" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10091c"
    }
    "Rx_Middle_of_Frame_Overruns" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100988"
    }
    "Rx_Octets" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100930"
    }
    "Rx_Start_of_Frame_Overruns" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100984"
    }
    "Rx_Tx_1024_Up_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10097c"
    }
    "Rx_Tx_128_255_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100970"
    }
    "Rx_Tx_256_511_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100974"
    }
    "Rx_Tx_512_1023_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100978"
    }
    "Rx_Tx_64_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100968"
    }
    "Rx_Tx_65_127_Octet_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10096c"
    }
    "SDRAM_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000008"
        type = "SDRAM_CONFIG__bitfield"
    }
    "SDRAM_CONFIG_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00000c"
        type = "SDRAM_CONFIG_2__bitfield"
    }
    "SDRAM_REF_CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000010"
        type = "SDRAM_REF_CTRL__bitfield"
    }
    "SDRAM_REF_CTRL_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000014"
        type = "SDRAM_REF_CTRL_SHDW__bitfield"
    }
    "SDRAM_TIM_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000018"
        type = "SDRAM_TIM_1__bitfield"
    }
    "SDRAM_TIM_1_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00001c"
        type = "SDRAM_TIM_1_SHDW__bitfield"
    }
    "SDRAM_TIM_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000020"
        type = "SDRAM_TIM_2__bitfield"
    }
    "SDRAM_TIM_2_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000024"
        type = "SDRAM_TIM_2_SHDW__bitfield"
    }
    "SDRAM_TIM_3" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000028"
        type = "SDRAM_TIM_3__bitfield"
    }
    "SDRAM_TIM_3_SHDW" {
        access = "memorymapped"
        width = "32"
        address = "0x4c00002c"
        type = "SDRAM_TIM_3__bitfield"
    }
    "SECONDS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e000"
        desc = "The SECONDS_REG is used to program the required seconds value of the current time. Seconds are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. If the seconds value is 45, then the value of SEC0 is 5 and value of SEC1 is 4."
        type = "SECONDS_REG__bitfield"
    }
    "STATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x4c000004"
        type = "STATUS__bitfield"
    }
    "Single_Collision_Tx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10094c"
    }
    "Spinlock_LOCK_REG_0" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca800"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_1" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca804"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_10" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca828"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_11" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca82c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_12" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca830"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_13" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca834"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_14" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca838"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_15" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca83c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_16" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca840"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_17" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca844"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_18" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca848"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_19" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca84c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_2" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca808"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_20" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca850"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_21" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca854"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_22" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca858"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_23" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca85c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_24" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca860"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_25" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca864"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_26" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca868"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_27" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca86c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_28" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca870"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_29" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca874"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_3" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca80c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_30" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca878"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_31" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca87c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_4" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca810"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_5" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca814"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_6" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca818"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_7" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca81c"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_8" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca820"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_LOCK_REG_9" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca824"
        desc = "This register is read when attempting to acquire a lock.  The lock is automatically taken if it was not taken and the value returned by the read is zero.  If the lock was already taken, then the read returns one.  Writing a zero to this register frees the lock."
        type = "Spinlock_LOCK_REG___bitfield"
    }
    "Spinlock_REV" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca000"
        desc = "Read-only IP revision identifier (X.Y.R) used by software to determine features, bugs and compatibility of an instance of this the Spin Lock module."
        type = "Spinlock_REV__bitfield"
    }
    "Spinlock_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca010"
        desc = "This register controls the various parameters of the OCP interface.  Note that several fields are present by read-only."
        type = "Spinlock_SYSCONFIG__bitfield"
    }
    "Spinlock_SYSTATUS" {
        access = "memorymapped"
        width = "32"
        address = "0x480ca014"
        desc = "This register provides status information about this instance of the Spin Lock module."
        type = "Spinlock_SYSTATUS__bitfield"
    }
    "TDFDQ" {
        access = "memorymapped"
        width = "32"
        address = "0x47402004"
        type = "TDFDQ__bitfield"
    }
    "TPCC_CCCFG" {
        access = "memorymapped"
        width = "32"
        address = "0x49000004"
    }
    "TPCC_CCERR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000318"
    }
    "TPCC_CCERRCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4900031c"
    }
    "TPCC_CCSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49000640"
    }
    "TPCC_CER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001018"
    }
    "TPCC_CERH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900101c"
    }
    "TPCC_DCHMAP0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000100"
    }
    "TPCC_DCHMAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000104"
    }
    "TPCC_DCHMAP10" {
        access = "memorymapped"
        width = "32"
        address = "0x49000128"
    }
    "TPCC_DCHMAP11" {
        access = "memorymapped"
        width = "32"
        address = "0x4900012c"
    }
    "TPCC_DCHMAP12" {
        access = "memorymapped"
        width = "32"
        address = "0x49000130"
    }
    "TPCC_DCHMAP13" {
        access = "memorymapped"
        width = "32"
        address = "0x49000134"
    }
    "TPCC_DCHMAP14" {
        access = "memorymapped"
        width = "32"
        address = "0x49000138"
    }
    "TPCC_DCHMAP15" {
        access = "memorymapped"
        width = "32"
        address = "0x4900013c"
    }
    "TPCC_DCHMAP16" {
        access = "memorymapped"
        width = "32"
        address = "0x49000140"
    }
    "TPCC_DCHMAP17" {
        access = "memorymapped"
        width = "32"
        address = "0x49000144"
    }
    "TPCC_DCHMAP18" {
        access = "memorymapped"
        width = "32"
        address = "0x49000148"
    }
    "TPCC_DCHMAP19" {
        access = "memorymapped"
        width = "32"
        address = "0x4900014c"
    }
    "TPCC_DCHMAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000108"
    }
    "TPCC_DCHMAP20" {
        access = "memorymapped"
        width = "32"
        address = "0x49000150"
    }
    "TPCC_DCHMAP21" {
        access = "memorymapped"
        width = "32"
        address = "0x49000154"
    }
    "TPCC_DCHMAP22" {
        access = "memorymapped"
        width = "32"
        address = "0x49000158"
    }
    "TPCC_DCHMAP23" {
        access = "memorymapped"
        width = "32"
        address = "0x4900015c"
    }
    "TPCC_DCHMAP24" {
        access = "memorymapped"
        width = "32"
        address = "0x49000160"
    }
    "TPCC_DCHMAP25" {
        access = "memorymapped"
        width = "32"
        address = "0x49000164"
    }
    "TPCC_DCHMAP26" {
        access = "memorymapped"
        width = "32"
        address = "0x49000168"
    }
    "TPCC_DCHMAP27" {
        access = "memorymapped"
        width = "32"
        address = "0x4900016c"
    }
    "TPCC_DCHMAP28" {
        access = "memorymapped"
        width = "32"
        address = "0x49000170"
    }
    "TPCC_DCHMAP29" {
        access = "memorymapped"
        width = "32"
        address = "0x49000174"
    }
    "TPCC_DCHMAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900010c"
    }
    "TPCC_DCHMAP30" {
        access = "memorymapped"
        width = "32"
        address = "0x49000178"
    }
    "TPCC_DCHMAP31" {
        access = "memorymapped"
        width = "32"
        address = "0x4900017c"
    }
    "TPCC_DCHMAP32" {
        access = "memorymapped"
        width = "32"
        address = "0x49000180"
    }
    "TPCC_DCHMAP33" {
        access = "memorymapped"
        width = "32"
        address = "0x49000184"
    }
    "TPCC_DCHMAP34" {
        access = "memorymapped"
        width = "32"
        address = "0x49000188"
    }
    "TPCC_DCHMAP35" {
        access = "memorymapped"
        width = "32"
        address = "0x4900018c"
    }
    "TPCC_DCHMAP36" {
        access = "memorymapped"
        width = "32"
        address = "0x49000190"
    }
    "TPCC_DCHMAP37" {
        access = "memorymapped"
        width = "32"
        address = "0x49000194"
    }
    "TPCC_DCHMAP38" {
        access = "memorymapped"
        width = "32"
        address = "0x49000198"
    }
    "TPCC_DCHMAP39" {
        access = "memorymapped"
        width = "32"
        address = "0x4900019c"
    }
    "TPCC_DCHMAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000110"
    }
    "TPCC_DCHMAP40" {
        access = "memorymapped"
        width = "32"
        address = "0x490001a0"
    }
    "TPCC_DCHMAP41" {
        access = "memorymapped"
        width = "32"
        address = "0x490001a4"
    }
    "TPCC_DCHMAP42" {
        access = "memorymapped"
        width = "32"
        address = "0x490001a8"
    }
    "TPCC_DCHMAP43" {
        access = "memorymapped"
        width = "32"
        address = "0x490001ac"
    }
    "TPCC_DCHMAP44" {
        access = "memorymapped"
        width = "32"
        address = "0x490001b0"
    }
    "TPCC_DCHMAP45" {
        access = "memorymapped"
        width = "32"
        address = "0x490001b4"
    }
    "TPCC_DCHMAP46" {
        access = "memorymapped"
        width = "32"
        address = "0x490001b8"
    }
    "TPCC_DCHMAP47" {
        access = "memorymapped"
        width = "32"
        address = "0x490001bc"
    }
    "TPCC_DCHMAP48" {
        access = "memorymapped"
        width = "32"
        address = "0x490001c0"
    }
    "TPCC_DCHMAP49" {
        access = "memorymapped"
        width = "32"
        address = "0x490001c4"
    }
    "TPCC_DCHMAP5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000114"
    }
    "TPCC_DCHMAP50" {
        access = "memorymapped"
        width = "32"
        address = "0x490001c8"
    }
    "TPCC_DCHMAP51" {
        access = "memorymapped"
        width = "32"
        address = "0x490001cc"
    }
    "TPCC_DCHMAP52" {
        access = "memorymapped"
        width = "32"
        address = "0x490001d0"
    }
    "TPCC_DCHMAP53" {
        access = "memorymapped"
        width = "32"
        address = "0x490001d4"
    }
    "TPCC_DCHMAP54" {
        access = "memorymapped"
        width = "32"
        address = "0x490001d8"
    }
    "TPCC_DCHMAP55" {
        access = "memorymapped"
        width = "32"
        address = "0x490001dc"
    }
    "TPCC_DCHMAP56" {
        access = "memorymapped"
        width = "32"
        address = "0x490001e0"
    }
    "TPCC_DCHMAP57" {
        access = "memorymapped"
        width = "32"
        address = "0x490001e4"
    }
    "TPCC_DCHMAP58" {
        access = "memorymapped"
        width = "32"
        address = "0x490001e8"
    }
    "TPCC_DCHMAP59" {
        access = "memorymapped"
        width = "32"
        address = "0x490001ec"
    }
    "TPCC_DCHMAP6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000118"
    }
    "TPCC_DCHMAP60" {
        access = "memorymapped"
        width = "32"
        address = "0x490001f0"
    }
    "TPCC_DCHMAP61" {
        access = "memorymapped"
        width = "32"
        address = "0x490001f4"
    }
    "TPCC_DCHMAP62" {
        access = "memorymapped"
        width = "32"
        address = "0x490001f8"
    }
    "TPCC_DCHMAP63" {
        access = "memorymapped"
        width = "32"
        address = "0x490001fc"
    }
    "TPCC_DCHMAP7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900011c"
    }
    "TPCC_DCHMAP8" {
        access = "memorymapped"
        width = "32"
        address = "0x49000120"
    }
    "TPCC_DCHMAP9" {
        access = "memorymapped"
        width = "32"
        address = "0x49000124"
    }
    "TPCC_DMAQNUM0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000240"
    }
    "TPCC_DMAQNUM1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000244"
    }
    "TPCC_DMAQNUM2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000248"
    }
    "TPCC_DMAQNUM3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900024c"
    }
    "TPCC_DMAQNUM4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000250"
    }
    "TPCC_DMAQNUM5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000254"
    }
    "TPCC_DMAQNUM6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000258"
    }
    "TPCC_DMAQNUM7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900025c"
    }
    "TPCC_DRAE0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000340"
    }
    "TPCC_DRAE1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000348"
    }
    "TPCC_DRAE2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000350"
    }
    "TPCC_DRAE3" {
        access = "memorymapped"
        width = "32"
        address = "0x49000358"
    }
    "TPCC_DRAE4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000360"
    }
    "TPCC_DRAE5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000368"
    }
    "TPCC_DRAE6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000370"
    }
    "TPCC_DRAE7" {
        access = "memorymapped"
        width = "32"
        address = "0x49000378"
    }
    "TPCC_DRAEH0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000344"
    }
    "TPCC_DRAEH1" {
        access = "memorymapped"
        width = "32"
        address = "0x4900034c"
    }
    "TPCC_DRAEH2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000354"
    }
    "TPCC_DRAEH3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900035c"
    }
    "TPCC_DRAEH4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000364"
    }
    "TPCC_DRAEH5" {
        access = "memorymapped"
        width = "32"
        address = "0x4900036c"
    }
    "TPCC_DRAEH6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000374"
    }
    "TPCC_DRAEH7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900037c"
    }
    "TPCC_ECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001008"
    }
    "TPCC_ECRH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900100c"
    }
    "TPCC_EECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001028"
    }
    "TPCC_EECRH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900102c"
    }
    "TPCC_EER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001020"
    }
    "TPCC_EERH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001024"
    }
    "TPCC_EESR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001030"
    }
    "TPCC_EESRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001034"
    }
    "TPCC_EEVAL" {
        access = "memorymapped"
        width = "32"
        address = "0x49000320"
    }
    "TPCC_EMCR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000308"
    }
    "TPCC_EMCRH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900030c"
    }
    "TPCC_EMR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000300"
    }
    "TPCC_EMRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49000304"
    }
    "TPCC_ER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001000"
    }
    "TPCC_ERH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001004"
    }
    "TPCC_ESR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001010"
    }
    "TPCC_ESRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001014"
    }
    "TPCC_ICR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001070"
    }
    "TPCC_ICRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001074"
    }
    "TPCC_IECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001058"
    }
    "TPCC_IECRH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900105c"
    }
    "TPCC_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001050"
    }
    "TPCC_IERH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001054"
    }
    "TPCC_IESR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001060"
    }
    "TPCC_IESRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001064"
    }
    "TPCC_IEVAL" {
        access = "memorymapped"
        width = "32"
        address = "0x49001078"
    }
    "TPCC_IPR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001068"
    }
    "TPCC_IPRH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900106c"
    }
    "TPCC_MPFAR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000800"
    }
    "TPCC_MPFCR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000808"
    }
    "TPCC_MPFSR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000804"
    }
    "TPCC_MPPA0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000810"
    }
    "TPCC_MPPA1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000814"
    }
    "TPCC_MPPA2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000818"
    }
    "TPCC_MPPA3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900081c"
    }
    "TPCC_MPPA4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000820"
    }
    "TPCC_MPPA5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000824"
    }
    "TPCC_MPPA6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000828"
    }
    "TPCC_MPPA7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900082c"
    }
    "TPCC_MPPAG" {
        access = "memorymapped"
        width = "32"
        address = "0x4900080c"
    }
    "TPCC_PID" {
        access = "memorymapped"
        width = "32"
        address = "0x49000000"
    }
    "TPCC_Q0E0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000400"
    }
    "TPCC_Q0E1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000404"
    }
    "TPCC_Q0E10" {
        access = "memorymapped"
        width = "32"
        address = "0x49000428"
    }
    "TPCC_Q0E11" {
        access = "memorymapped"
        width = "32"
        address = "0x4900042c"
    }
    "TPCC_Q0E12" {
        access = "memorymapped"
        width = "32"
        address = "0x49000430"
    }
    "TPCC_Q0E13" {
        access = "memorymapped"
        width = "32"
        address = "0x49000434"
    }
    "TPCC_Q0E14" {
        access = "memorymapped"
        width = "32"
        address = "0x49000438"
    }
    "TPCC_Q0E15" {
        access = "memorymapped"
        width = "32"
        address = "0x4900043c"
    }
    "TPCC_Q0E2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000408"
    }
    "TPCC_Q0E3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900040c"
    }
    "TPCC_Q0E4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000410"
    }
    "TPCC_Q0E5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000414"
    }
    "TPCC_Q0E6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000418"
    }
    "TPCC_Q0E7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900041c"
    }
    "TPCC_Q0E8" {
        access = "memorymapped"
        width = "32"
        address = "0x49000420"
    }
    "TPCC_Q0E9" {
        access = "memorymapped"
        width = "32"
        address = "0x49000424"
    }
    "TPCC_Q1E0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000440"
    }
    "TPCC_Q1E1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000444"
    }
    "TPCC_Q1E10" {
        access = "memorymapped"
        width = "32"
        address = "0x49000468"
    }
    "TPCC_Q1E11" {
        access = "memorymapped"
        width = "32"
        address = "0x4900046c"
    }
    "TPCC_Q1E12" {
        access = "memorymapped"
        width = "32"
        address = "0x49000470"
    }
    "TPCC_Q1E13" {
        access = "memorymapped"
        width = "32"
        address = "0x49000474"
    }
    "TPCC_Q1E14" {
        access = "memorymapped"
        width = "32"
        address = "0x49000478"
    }
    "TPCC_Q1E15" {
        access = "memorymapped"
        width = "32"
        address = "0x4900047c"
    }
    "TPCC_Q1E2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000448"
    }
    "TPCC_Q1E3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900044c"
    }
    "TPCC_Q1E4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000450"
    }
    "TPCC_Q1E5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000454"
    }
    "TPCC_Q1E6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000458"
    }
    "TPCC_Q1E7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900045c"
    }
    "TPCC_Q1E8" {
        access = "memorymapped"
        width = "32"
        address = "0x49000460"
    }
    "TPCC_Q1E9" {
        access = "memorymapped"
        width = "32"
        address = "0x49000464"
    }
    "TPCC_Q2E0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000480"
    }
    "TPCC_Q2E1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000484"
    }
    "TPCC_Q2E10" {
        access = "memorymapped"
        width = "32"
        address = "0x490004a8"
    }
    "TPCC_Q2E11" {
        access = "memorymapped"
        width = "32"
        address = "0x490004ac"
    }
    "TPCC_Q2E12" {
        access = "memorymapped"
        width = "32"
        address = "0x490004b0"
    }
    "TPCC_Q2E13" {
        access = "memorymapped"
        width = "32"
        address = "0x490004b4"
    }
    "TPCC_Q2E14" {
        access = "memorymapped"
        width = "32"
        address = "0x490004b8"
    }
    "TPCC_Q2E15" {
        access = "memorymapped"
        width = "32"
        address = "0x490004bc"
    }
    "TPCC_Q2E2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000488"
    }
    "TPCC_Q2E3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900048c"
    }
    "TPCC_Q2E4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000490"
    }
    "TPCC_Q2E5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000494"
    }
    "TPCC_Q2E6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000498"
    }
    "TPCC_Q2E7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900049c"
    }
    "TPCC_Q2E8" {
        access = "memorymapped"
        width = "32"
        address = "0x490004a0"
    }
    "TPCC_Q2E9" {
        access = "memorymapped"
        width = "32"
        address = "0x490004a4"
    }
    "TPCC_Q3E0" {
        access = "memorymapped"
        width = "32"
        address = "0x490004c0"
    }
    "TPCC_Q3E1" {
        access = "memorymapped"
        width = "32"
        address = "0x490004c4"
    }
    "TPCC_Q3E10" {
        access = "memorymapped"
        width = "32"
        address = "0x490004e8"
    }
    "TPCC_Q3E11" {
        access = "memorymapped"
        width = "32"
        address = "0x490004ec"
    }
    "TPCC_Q3E12" {
        access = "memorymapped"
        width = "32"
        address = "0x490004f0"
    }
    "TPCC_Q3E13" {
        access = "memorymapped"
        width = "32"
        address = "0x490004f4"
    }
    "TPCC_Q3E14" {
        access = "memorymapped"
        width = "32"
        address = "0x490004f8"
    }
    "TPCC_Q3E15" {
        access = "memorymapped"
        width = "32"
        address = "0x490004fc"
    }
    "TPCC_Q3E2" {
        access = "memorymapped"
        width = "32"
        address = "0x490004c8"
    }
    "TPCC_Q3E3" {
        access = "memorymapped"
        width = "32"
        address = "0x490004cc"
    }
    "TPCC_Q3E4" {
        access = "memorymapped"
        width = "32"
        address = "0x490004d0"
    }
    "TPCC_Q3E5" {
        access = "memorymapped"
        width = "32"
        address = "0x490004d4"
    }
    "TPCC_Q3E6" {
        access = "memorymapped"
        width = "32"
        address = "0x490004d8"
    }
    "TPCC_Q3E7" {
        access = "memorymapped"
        width = "32"
        address = "0x490004dc"
    }
    "TPCC_Q3E8" {
        access = "memorymapped"
        width = "32"
        address = "0x490004e0"
    }
    "TPCC_Q3E9" {
        access = "memorymapped"
        width = "32"
        address = "0x490004e4"
    }
    "TPCC_QCHMAP0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000200"
    }
    "TPCC_QCHMAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000204"
    }
    "TPCC_QCHMAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000208"
    }
    "TPCC_QCHMAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900020c"
    }
    "TPCC_QCHMAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000210"
    }
    "TPCC_QCHMAP5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000214"
    }
    "TPCC_QCHMAP6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000218"
    }
    "TPCC_QCHMAP7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900021c"
    }
    "TPCC_QDMAQNUM" {
        access = "memorymapped"
        width = "32"
        address = "0x49000260"
    }
    "TPCC_QEECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001088"
    }
    "TPCC_QEER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001084"
    }
    "TPCC_QEESR" {
        access = "memorymapped"
        width = "32"
        address = "0x4900108c"
    }
    "TPCC_QEMCR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000314"
    }
    "TPCC_QEMR" {
        access = "memorymapped"
        width = "32"
        address = "0x49000310"
    }
    "TPCC_QER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001080"
    }
    "TPCC_QRAE0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000380"
    }
    "TPCC_QRAE1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000384"
    }
    "TPCC_QRAE2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000388"
    }
    "TPCC_QRAE3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900038c"
    }
    "TPCC_QRAE4" {
        access = "memorymapped"
        width = "32"
        address = "0x49000390"
    }
    "TPCC_QRAE5" {
        access = "memorymapped"
        width = "32"
        address = "0x49000394"
    }
    "TPCC_QRAE6" {
        access = "memorymapped"
        width = "32"
        address = "0x49000398"
    }
    "TPCC_QRAE7" {
        access = "memorymapped"
        width = "32"
        address = "0x4900039c"
    }
    "TPCC_QSECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001094"
    }
    "TPCC_QSER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001090"
    }
    "TPCC_QSTAT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49000600"
    }
    "TPCC_QSTAT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49000604"
    }
    "TPCC_QSTAT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49000608"
    }
    "TPCC_QSTAT3" {
        access = "memorymapped"
        width = "32"
        address = "0x4900060c"
    }
    "TPCC_QUEPRI" {
        access = "memorymapped"
        width = "32"
        address = "0x49000284"
    }
    "TPCC_QWMTHRA" {
        access = "memorymapped"
        width = "32"
        address = "0x49000620"
    }
    "TPCC_SECR" {
        access = "memorymapped"
        width = "32"
        address = "0x49001040"
    }
    "TPCC_SECRH" {
        access = "memorymapped"
        width = "32"
        address = "0x49001044"
    }
    "TPCC_SER" {
        access = "memorymapped"
        width = "32"
        address = "0x49001038"
    }
    "TPCC_SERH" {
        access = "memorymapped"
        width = "32"
        address = "0x4900103c"
    }
    "TPTC0_DFBIDX0" {
        access = "memorymapped"
        width = "32"
        address = "0x49800310"
    }
    "TPTC0_DFBIDX1" {
        access = "memorymapped"
        width = "32"
        address = "0x49800350"
    }
    "TPTC0_DFBIDX2" {
        access = "memorymapped"
        width = "32"
        address = "0x49800390"
    }
    "TPTC0_DFBIDX3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003d0"
    }
    "TPTC0_DFCNT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49800308"
    }
    "TPTC0_DFCNT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49800348"
    }
    "TPTC0_DFCNT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49800388"
    }
    "TPTC0_DFCNT3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003c8"
    }
    "TPTC0_DFCNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49800280"
    }
    "TPTC0_DFDST0" {
        access = "memorymapped"
        width = "32"
        address = "0x4980030c"
    }
    "TPTC0_DFDST1" {
        access = "memorymapped"
        width = "32"
        address = "0x4980034c"
    }
    "TPTC0_DFDST2" {
        access = "memorymapped"
        width = "32"
        address = "0x4980038c"
    }
    "TPTC0_DFDST3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003cc"
    }
    "TPTC0_DFDSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49800288"
    }
    "TPTC0_DFMPPRXY0" {
        access = "memorymapped"
        width = "32"
        address = "0x49800314"
    }
    "TPTC0_DFMPPRXY1" {
        access = "memorymapped"
        width = "32"
        address = "0x49800354"
    }
    "TPTC0_DFMPPRXY2" {
        access = "memorymapped"
        width = "32"
        address = "0x49800394"
    }
    "TPTC0_DFMPPRXY3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003d4"
    }
    "TPTC0_DFOPT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49800300"
    }
    "TPTC0_DFOPT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49800340"
    }
    "TPTC0_DFOPT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49800380"
    }
    "TPTC0_DFOPT3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003c0"
    }
    "TPTC0_DFSRC0" {
        access = "memorymapped"
        width = "32"
        address = "0x49800304"
    }
    "TPTC0_DFSRC1" {
        access = "memorymapped"
        width = "32"
        address = "0x49800344"
    }
    "TPTC0_DFSRC2" {
        access = "memorymapped"
        width = "32"
        address = "0x49800384"
    }
    "TPTC0_DFSRC3" {
        access = "memorymapped"
        width = "32"
        address = "0x498003c4"
    }
    "TPTC0_DFSRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49800284"
    }
    "TPTC0_ERRCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x49800128"
    }
    "TPTC0_ERRCMD" {
        access = "memorymapped"
        width = "32"
        address = "0x49800130"
    }
    "TPTC0_ERRDET" {
        access = "memorymapped"
        width = "32"
        address = "0x4980012c"
    }
    "TPTC0_ERREN" {
        access = "memorymapped"
        width = "32"
        address = "0x49800124"
    }
    "TPTC0_ERRSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49800120"
    }
    "TPTC0_PID" {
        access = "memorymapped"
        width = "32"
        address = "0x49800000"
    }
    "TPTC0_RDRATE" {
        access = "memorymapped"
        width = "32"
        address = "0x49800140"
    }
    "TPTC0_SABIDX" {
        access = "memorymapped"
        width = "32"
        address = "0x49800250"
    }
    "TPTC0_SACNT" {
        access = "memorymapped"
        width = "32"
        address = "0x49800248"
    }
    "TPTC0_SACNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49800258"
    }
    "TPTC0_SADST" {
        access = "memorymapped"
        width = "32"
        address = "0x4980024c"
    }
    "TPTC0_SADSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49800260"
    }
    "TPTC0_SAMPPRXY" {
        access = "memorymapped"
        width = "32"
        address = "0x49800254"
    }
    "TPTC0_SAOPT" {
        access = "memorymapped"
        width = "32"
        address = "0x49800240"
    }
    "TPTC0_SASRC" {
        access = "memorymapped"
        width = "32"
        address = "0x49800244"
    }
    "TPTC0_SASRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x4980025c"
    }
    "TPTC0_TCCFG" {
        access = "memorymapped"
        width = "32"
        address = "0x49800004"
    }
    "TPTC0_TCSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49800100"
    }
    "TPTC1_DFBIDX0" {
        access = "memorymapped"
        width = "32"
        address = "0x49900310"
    }
    "TPTC1_DFBIDX1" {
        access = "memorymapped"
        width = "32"
        address = "0x49900350"
    }
    "TPTC1_DFBIDX2" {
        access = "memorymapped"
        width = "32"
        address = "0x49900390"
    }
    "TPTC1_DFBIDX3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003d0"
    }
    "TPTC1_DFCNT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49900308"
    }
    "TPTC1_DFCNT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49900348"
    }
    "TPTC1_DFCNT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49900388"
    }
    "TPTC1_DFCNT3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003c8"
    }
    "TPTC1_DFCNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49900280"
    }
    "TPTC1_DFDST0" {
        access = "memorymapped"
        width = "32"
        address = "0x4990030c"
    }
    "TPTC1_DFDST1" {
        access = "memorymapped"
        width = "32"
        address = "0x4990034c"
    }
    "TPTC1_DFDST2" {
        access = "memorymapped"
        width = "32"
        address = "0x4990038c"
    }
    "TPTC1_DFDST3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003cc"
    }
    "TPTC1_DFDSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49900288"
    }
    "TPTC1_DFMPPRXY0" {
        access = "memorymapped"
        width = "32"
        address = "0x49900314"
    }
    "TPTC1_DFMPPRXY1" {
        access = "memorymapped"
        width = "32"
        address = "0x49900354"
    }
    "TPTC1_DFMPPRXY2" {
        access = "memorymapped"
        width = "32"
        address = "0x49900394"
    }
    "TPTC1_DFMPPRXY3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003d4"
    }
    "TPTC1_DFOPT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49900300"
    }
    "TPTC1_DFOPT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49900340"
    }
    "TPTC1_DFOPT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49900380"
    }
    "TPTC1_DFOPT3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003c0"
    }
    "TPTC1_DFSRC0" {
        access = "memorymapped"
        width = "32"
        address = "0x49900304"
    }
    "TPTC1_DFSRC1" {
        access = "memorymapped"
        width = "32"
        address = "0x49900344"
    }
    "TPTC1_DFSRC2" {
        access = "memorymapped"
        width = "32"
        address = "0x49900384"
    }
    "TPTC1_DFSRC3" {
        access = "memorymapped"
        width = "32"
        address = "0x499003c4"
    }
    "TPTC1_DFSRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49900284"
    }
    "TPTC1_ERRCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x49900128"
    }
    "TPTC1_ERRCMD" {
        access = "memorymapped"
        width = "32"
        address = "0x49900130"
    }
    "TPTC1_ERRDET" {
        access = "memorymapped"
        width = "32"
        address = "0x4990012c"
    }
    "TPTC1_ERREN" {
        access = "memorymapped"
        width = "32"
        address = "0x49900124"
    }
    "TPTC1_ERRSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49900120"
    }
    "TPTC1_PID" {
        access = "memorymapped"
        width = "32"
        address = "0x49900000"
    }
    "TPTC1_RDRATE" {
        access = "memorymapped"
        width = "32"
        address = "0x49900140"
    }
    "TPTC1_SABIDX" {
        access = "memorymapped"
        width = "32"
        address = "0x49900250"
    }
    "TPTC1_SACNT" {
        access = "memorymapped"
        width = "32"
        address = "0x49900248"
    }
    "TPTC1_SACNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49900258"
    }
    "TPTC1_SADST" {
        access = "memorymapped"
        width = "32"
        address = "0x4990024c"
    }
    "TPTC1_SADSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49900260"
    }
    "TPTC1_SAMPPRXY" {
        access = "memorymapped"
        width = "32"
        address = "0x49900254"
    }
    "TPTC1_SAOPT" {
        access = "memorymapped"
        width = "32"
        address = "0x49900240"
    }
    "TPTC1_SASRC" {
        access = "memorymapped"
        width = "32"
        address = "0x49900244"
    }
    "TPTC1_SASRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x4990025c"
    }
    "TPTC1_TCCFG" {
        access = "memorymapped"
        width = "32"
        address = "0x49900004"
    }
    "TPTC1_TCSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49900100"
    }
    "TPTC2_DFBIDX0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00310"
    }
    "TPTC2_DFBIDX1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00350"
    }
    "TPTC2_DFBIDX2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00390"
    }
    "TPTC2_DFBIDX3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003d0"
    }
    "TPTC2_DFCNT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00308"
    }
    "TPTC2_DFCNT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00348"
    }
    "TPTC2_DFCNT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00388"
    }
    "TPTC2_DFCNT3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003c8"
    }
    "TPTC2_DFCNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00280"
    }
    "TPTC2_DFDST0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0030c"
    }
    "TPTC2_DFDST1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0034c"
    }
    "TPTC2_DFDST2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0038c"
    }
    "TPTC2_DFDST3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003cc"
    }
    "TPTC2_DFDSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00288"
    }
    "TPTC2_DFMPPRXY0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00314"
    }
    "TPTC2_DFMPPRXY1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00354"
    }
    "TPTC2_DFMPPRXY2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00394"
    }
    "TPTC2_DFMPPRXY3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003d4"
    }
    "TPTC2_DFOPT0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00300"
    }
    "TPTC2_DFOPT1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00340"
    }
    "TPTC2_DFOPT2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00380"
    }
    "TPTC2_DFOPT3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003c0"
    }
    "TPTC2_DFSRC0" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00304"
    }
    "TPTC2_DFSRC1" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00344"
    }
    "TPTC2_DFSRC2" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00384"
    }
    "TPTC2_DFSRC3" {
        access = "memorymapped"
        width = "32"
        address = "0x49a003c4"
    }
    "TPTC2_DFSRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00284"
    }
    "TPTC2_ERRCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00128"
    }
    "TPTC2_ERRCMD" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00130"
    }
    "TPTC2_ERRDET" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0012c"
    }
    "TPTC2_ERREN" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00124"
    }
    "TPTC2_ERRSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00120"
    }
    "TPTC2_PID" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00000"
    }
    "TPTC2_RDRATE" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00140"
    }
    "TPTC2_SABIDX" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00250"
    }
    "TPTC2_SACNT" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00248"
    }
    "TPTC2_SACNTRLD" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00258"
    }
    "TPTC2_SADST" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0024c"
    }
    "TPTC2_SADSTBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00260"
    }
    "TPTC2_SAMPPRXY" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00254"
    }
    "TPTC2_SAOPT" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00240"
    }
    "TPTC2_SASRC" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00244"
    }
    "TPTC2_SASRCBREF" {
        access = "memorymapped"
        width = "32"
        address = "0x49a0025c"
    }
    "TPTC2_TCCFG" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00004"
    }
    "TPTC2_TCSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x49a00100"
    }
    "TX0_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a40"
        desc = "CPDMA_STATERAM TX CHANNEL 0 COMPLETION POINTER REGISTER"
        type = "TX_CP__bitfield"
    }
    "TX0_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a00"
        desc = "CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX1_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a44"
        desc = "CPDMA_STATERAM TX CHANNEL 1 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX1_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a04"
        desc = "CPDMA_STATERAM TX CHANNEL 1 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX2_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a48"
        desc = "CPDMA_STATERAM TX CHANNEL 2 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX2_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a08"
        desc = "CPDMA_STATERAM TX CHANNEL 2 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX3_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a4c"
        desc = "CPDMA_STATERAM TX CHANNEL 3 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX3_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a0c"
        desc = "CPDMA_STATERAM TX CHANNEL 3 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX4_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a50"
        desc = "CPDMA_STATERAM TX CHANNEL 4 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX4_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a10"
        desc = "CPDMA_STATERAM TX CHANNEL 4 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX5_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a54"
        desc = "CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX5_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a14"
        desc = "CPDMA_STATERAM TX CHANNEL 5 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX6_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a58"
        desc = "CPDMA_STATERAM TX CHANNEL 6 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX6_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a18"
        desc = "CPDMA_STATERAM TX CHANNEL 6 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TX7_CP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a5c"
        desc = "CPDMA_STATERAM TX CHANNEL 7 COMPLETION POINTER REGISTER *"
        type = "TX_CP__bitfield"
    }
    "TX7_HDP" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100a1c"
        desc = "CPDMA_STATERAM TX CHANNEL 7 HEAD DESC POINTER *"
        type = "TX_HDP__bitfield"
    }
    "TXGCR0" {
        access = "memorymapped"
        width = "32"
        address = "0x47402800"
        type = "TXGCR__bitfield"
    }
    "TXGCR1" {
        access = "memorymapped"
        width = "32"
        address = "0x47402820"
        type = "TXGCR__bitfield"
    }
    "TXGCR10" {
        access = "memorymapped"
        width = "32"
        address = "0x47402940"
        type = "TXGCR__bitfield"
    }
    "TXGCR11" {
        access = "memorymapped"
        width = "32"
        address = "0x47402960"
        type = "TXGCR__bitfield"
    }
    "TXGCR12" {
        access = "memorymapped"
        width = "32"
        address = "0x47402980"
        type = "TXGCR__bitfield"
    }
    "TXGCR13" {
        access = "memorymapped"
        width = "32"
        address = "0x474029a0"
        type = "TXGCR__bitfield"
    }
    "TXGCR14" {
        access = "memorymapped"
        width = "32"
        address = "0x474029c0"
        type = "TXGCR__bitfield"
    }
    "TXGCR15" {
        access = "memorymapped"
        width = "32"
        address = "0x474029e0"
        type = "TXGCR__bitfield"
    }
    "TXGCR16" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a00"
        type = "TXGCR__bitfield"
    }
    "TXGCR17" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a20"
        type = "TXGCR__bitfield"
    }
    "TXGCR18" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a40"
        type = "TXGCR__bitfield"
    }
    "TXGCR19" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a60"
        type = "TXGCR__bitfield"
    }
    "TXGCR2" {
        access = "memorymapped"
        width = "32"
        address = "0x47402840"
        type = "TXGCR__bitfield"
    }
    "TXGCR20" {
        access = "memorymapped"
        width = "32"
        address = "0x47402a80"
        type = "TXGCR__bitfield"
    }
    "TXGCR21" {
        access = "memorymapped"
        width = "32"
        address = "0x47402aa0"
        type = "TXGCR__bitfield"
    }
    "TXGCR22" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ac0"
        type = "TXGCR__bitfield"
    }
    "TXGCR23" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ae0"
        type = "TXGCR__bitfield"
    }
    "TXGCR24" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b00"
        type = "TXGCR__bitfield"
    }
    "TXGCR25" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b20"
        type = "TXGCR__bitfield"
    }
    "TXGCR26" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b40"
        type = "TXGCR__bitfield"
    }
    "TXGCR27" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b60"
        type = "TXGCR__bitfield"
    }
    "TXGCR28" {
        access = "memorymapped"
        width = "32"
        address = "0x47402b80"
        type = "TXGCR__bitfield"
    }
    "TXGCR29" {
        access = "memorymapped"
        width = "32"
        address = "0x47402ba0"
        type = "TXGCR__bitfield"
    }
    "TXGCR3" {
        access = "memorymapped"
        width = "32"
        address = "0x47402860"
        type = "TXGCR__bitfield"
    }
    "TXGCR4" {
        access = "memorymapped"
        width = "32"
        address = "0x47402880"
        type = "TXGCR__bitfield"
    }
    "TXGCR5" {
        access = "memorymapped"
        width = "32"
        address = "0x474028a0"
        type = "TXGCR__bitfield"
    }
    "TXGCR6" {
        access = "memorymapped"
        width = "32"
        address = "0x474028c0"
        type = "TXGCR__bitfield"
    }
    "TXGCR7" {
        access = "memorymapped"
        width = "32"
        address = "0x474028e0"
        type = "TXGCR__bitfield"
    }
    "TXGCR8" {
        access = "memorymapped"
        width = "32"
        address = "0x47402900"
        type = "TXGCR__bitfield"
    }
    "TXGCR9" {
        access = "memorymapped"
        width = "32"
        address = "0x47402920"
        type = "TXGCR__bitfield"
    }
    "Tx_Octets" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100964"
    }
    "Tx_Underrun" {
        access = "memorymapped"
        width = "32"
        address = "0x4a10095c"
    }
    "UART0_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0903c"
    }
    "UART0_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09010"
    }
    "UART0_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09014"
    }
    "UART0_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09038"
    }
    "UART0_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09060"
    }
    "UART0_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09004"
    }
    "UART0_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09000"
    }
    "UART0_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09048"
    }
    "UART0_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09008"
    }
    "UART0_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09008"
    }
    "UART0_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09074"
    }
    "UART0_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09004"
    }
    "UART0_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0906c"
    }
    "UART0_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09008"
    }
    "UART0_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09070"
    }
    "UART0_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0900c"
    }
    "UART0_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09014"
    }
    "UART0_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09010"
    }
    "UART0_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09020"
    }
    "UART0_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09024"
    }
    "UART0_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09080"
    }
    "UART0_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09018"
    }
    "UART0_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09050"
    }
    "UART0_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0902c"
    }
    "UART0_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09000"
    }
    "UART0_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09064"
    }
    "UART0_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09034"
    }
    "UART0_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09030"
    }
    "UART0_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09040"
    }
    "UART0_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09028"
    }
    "UART0_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09034"
    }
    "UART0_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09030"
    }
    "UART0_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0901c"
    }
    "UART0_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09044"
    }
    "UART0_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09054"
    }
    "UART0_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09058"
    }
    "UART0_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09018"
    }
    "UART0_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09000"
    }
    "UART0_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0901c"
    }
    "UART0_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09084"
    }
    "UART0_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09068"
    }
    "UART0_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0902c"
    }
    "UART0_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09028"
    }
    "UART0_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09038"
    }
    "UART0_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0905c"
    }
    "UART0_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09018"
    }
    "UART0_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e0901c"
    }
    "UART0_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09010"
    }
    "UART0_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e09014"
    }
    "UART1_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x4802203c"
    }
    "UART1_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48022010"
    }
    "UART1_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48022014"
    }
    "UART1_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022038"
    }
    "UART1_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48022060"
    }
    "UART1_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x48022004"
    }
    "UART1_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48022000"
    }
    "UART1_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022048"
    }
    "UART1_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022008"
    }
    "UART1_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022008"
    }
    "UART1_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48022074"
    }
    "UART1_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x48022004"
    }
    "UART1_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x4802206c"
    }
    "UART1_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022008"
    }
    "UART1_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48022070"
    }
    "UART1_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802200c"
    }
    "UART1_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022014"
    }
    "UART1_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022010"
    }
    "UART1_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48022020"
    }
    "UART1_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48022024"
    }
    "UART1_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x48022080"
    }
    "UART1_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022018"
    }
    "UART1_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022050"
    }
    "UART1_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x4802202c"
    }
    "UART1_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022000"
    }
    "UART1_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x48022064"
    }
    "UART1_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x48022034"
    }
    "UART1_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48022030"
    }
    "UART1_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022040"
    }
    "UART1_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022028"
    }
    "UART1_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x48022034"
    }
    "UART1_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x48022030"
    }
    "UART1_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802201c"
    }
    "UART1_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022044"
    }
    "UART1_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x48022054"
    }
    "UART1_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x48022058"
    }
    "UART1_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022018"
    }
    "UART1_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022000"
    }
    "UART1_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802201c"
    }
    "UART1_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x48022084"
    }
    "UART1_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x48022068"
    }
    "UART1_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x4802202c"
    }
    "UART1_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48022028"
    }
    "UART1_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x48022038"
    }
    "UART1_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x4802205c"
    }
    "UART1_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x48022018"
    }
    "UART1_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x4802201c"
    }
    "UART1_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x48022010"
    }
    "UART1_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x48022014"
    }
    "UART2_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x4802403c"
    }
    "UART2_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48024010"
    }
    "UART2_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48024014"
    }
    "UART2_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024038"
    }
    "UART2_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48024060"
    }
    "UART2_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x48024004"
    }
    "UART2_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48024000"
    }
    "UART2_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024048"
    }
    "UART2_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024008"
    }
    "UART2_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024008"
    }
    "UART2_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48024074"
    }
    "UART2_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x48024004"
    }
    "UART2_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x4802406c"
    }
    "UART2_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024008"
    }
    "UART2_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48024070"
    }
    "UART2_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802400c"
    }
    "UART2_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024014"
    }
    "UART2_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024010"
    }
    "UART2_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x48024020"
    }
    "UART2_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x48024024"
    }
    "UART2_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x48024080"
    }
    "UART2_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024018"
    }
    "UART2_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024050"
    }
    "UART2_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x4802402c"
    }
    "UART2_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024000"
    }
    "UART2_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x48024064"
    }
    "UART2_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x48024034"
    }
    "UART2_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48024030"
    }
    "UART2_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024040"
    }
    "UART2_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024028"
    }
    "UART2_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x48024034"
    }
    "UART2_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x48024030"
    }
    "UART2_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802401c"
    }
    "UART2_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024044"
    }
    "UART2_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x48024054"
    }
    "UART2_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x48024058"
    }
    "UART2_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024018"
    }
    "UART2_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024000"
    }
    "UART2_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4802401c"
    }
    "UART2_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x48024084"
    }
    "UART2_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x48024068"
    }
    "UART2_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x4802402c"
    }
    "UART2_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x48024028"
    }
    "UART2_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x48024038"
    }
    "UART2_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x4802405c"
    }
    "UART2_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x48024018"
    }
    "UART2_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x4802401c"
    }
    "UART2_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x48024010"
    }
    "UART2_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x48024014"
    }
    "UART3_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x481a603c"
    }
    "UART3_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6010"
    }
    "UART3_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6014"
    }
    "UART3_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6038"
    }
    "UART3_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6060"
    }
    "UART3_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6004"
    }
    "UART3_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6000"
    }
    "UART3_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6048"
    }
    "UART3_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6008"
    }
    "UART3_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6008"
    }
    "UART3_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6074"
    }
    "UART3_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6004"
    }
    "UART3_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a606c"
    }
    "UART3_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6008"
    }
    "UART3_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6070"
    }
    "UART3_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a600c"
    }
    "UART3_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6014"
    }
    "UART3_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6010"
    }
    "UART3_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6020"
    }
    "UART3_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6024"
    }
    "UART3_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6080"
    }
    "UART3_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6018"
    }
    "UART3_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6050"
    }
    "UART3_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x481a602c"
    }
    "UART3_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6000"
    }
    "UART3_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6064"
    }
    "UART3_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6034"
    }
    "UART3_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6030"
    }
    "UART3_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6040"
    }
    "UART3_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6028"
    }
    "UART3_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6034"
    }
    "UART3_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6030"
    }
    "UART3_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a601c"
    }
    "UART3_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6044"
    }
    "UART3_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6054"
    }
    "UART3_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6058"
    }
    "UART3_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6018"
    }
    "UART3_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6000"
    }
    "UART3_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a601c"
    }
    "UART3_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6084"
    }
    "UART3_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6068"
    }
    "UART3_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a602c"
    }
    "UART3_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6028"
    }
    "UART3_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6038"
    }
    "UART3_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x481a605c"
    }
    "UART3_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6018"
    }
    "UART3_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a601c"
    }
    "UART3_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6010"
    }
    "UART3_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a6014"
    }
    "UART4_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x481a803c"
    }
    "UART4_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8010"
    }
    "UART4_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8014"
    }
    "UART4_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8038"
    }
    "UART4_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8060"
    }
    "UART4_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8004"
    }
    "UART4_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8000"
    }
    "UART4_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8048"
    }
    "UART4_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8008"
    }
    "UART4_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8008"
    }
    "UART4_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8074"
    }
    "UART4_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8004"
    }
    "UART4_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a806c"
    }
    "UART4_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8008"
    }
    "UART4_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8070"
    }
    "UART4_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a800c"
    }
    "UART4_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8014"
    }
    "UART4_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8010"
    }
    "UART4_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8020"
    }
    "UART4_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8024"
    }
    "UART4_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8080"
    }
    "UART4_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8018"
    }
    "UART4_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8050"
    }
    "UART4_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x481a802c"
    }
    "UART4_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8000"
    }
    "UART4_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8064"
    }
    "UART4_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8034"
    }
    "UART4_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8030"
    }
    "UART4_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8040"
    }
    "UART4_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8028"
    }
    "UART4_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8034"
    }
    "UART4_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8030"
    }
    "UART4_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a801c"
    }
    "UART4_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8044"
    }
    "UART4_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8054"
    }
    "UART4_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8058"
    }
    "UART4_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8018"
    }
    "UART4_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8000"
    }
    "UART4_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a801c"
    }
    "UART4_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8084"
    }
    "UART4_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8068"
    }
    "UART4_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481a802c"
    }
    "UART4_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8028"
    }
    "UART4_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8038"
    }
    "UART4_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x481a805c"
    }
    "UART4_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8018"
    }
    "UART4_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a801c"
    }
    "UART4_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8010"
    }
    "UART4_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x481a8014"
    }
    "UART5_ACREG" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa03c"
    }
    "UART5_ADDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa010"
    }
    "UART5_ADDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa014"
    }
    "UART5_BLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa038"
    }
    "UART5_CFPS" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa060"
    }
    "UART5_DLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa004"
    }
    "UART5_DLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa000"
    }
    "UART5_EBLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa048"
    }
    "UART5_EFR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa008"
    }
    "UART5_FCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa008"
    }
    "UART5_FREQ_SEL" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa074"
    }
    "UART5_IER" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa004"
    }
    "UART5_IER2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa06c"
    }
    "UART5_IIR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa008"
    }
    "UART5_ISR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa070"
    }
    "UART5_LCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa00c"
    }
    "UART5_LSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa014"
    }
    "UART5_MCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa010"
    }
    "UART5_MDR1" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa020"
    }
    "UART5_MDR2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa024"
    }
    "UART5_MDR3" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa080"
    }
    "UART5_MSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa018"
    }
    "UART5_MVR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa050"
    }
    "UART5_RESUME" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa02c"
    }
    "UART5_RHR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa000"
    }
    "UART5_RXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa064"
    }
    "UART5_RXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa034"
    }
    "UART5_RXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa030"
    }
    "UART5_SCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa040"
    }
    "UART5_SFLSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa028"
    }
    "UART5_SFREGH" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa034"
    }
    "UART5_SFREGL" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa030"
    }
    "UART5_SPR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa01c"
    }
    "UART5_SSR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa044"
    }
    "UART5_SYSC" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa054"
    }
    "UART5_SYSS" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa058"
    }
    "UART5_TCR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa018"
    }
    "UART5_THR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa000"
    }
    "UART5_TLR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa01c"
    }
    "UART5_TXDMA" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa084"
    }
    "UART5_TXFIFO" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa068"
    }
    "UART5_TXFLH" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa02c"
    }
    "UART5_TXFLL" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa028"
    }
    "UART5_UASR" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa038"
    }
    "UART5_WER" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa05c"
    }
    "UART5_XOFF1" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa018"
    }
    "UART5_XOFF2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa01c"
    }
    "UART5_XON1" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa010"
    }
    "UART5_XON2" {
        access = "memorymapped"
        width = "32"
        address = "0x481aa014"
    }
    "USB0AUTOREQ" {
        access = "memorymapped"
        width = "32"
        address = "0x474010d0"
        type = "USB0AUTOREQ__bitfield"
    }
    "USB0CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x47401014"
        type = "USB0CTRL__bitfield"
    }
    "USB0GENRNDISEP1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401080"
        type = "USB0GENRNDISEP1__bitfield"
    }
    "USB0GENRNDISEP10" {
        access = "memorymapped"
        width = "32"
        address = "0x474010a4"
        type = "USB0GENRNDISEP10__bitfield"
    }
    "USB0GENRNDISEP11" {
        access = "memorymapped"
        width = "32"
        address = "0x474010a8"
        type = "USB0GENRNDISEP11__bitfield"
    }
    "USB0GENRNDISEP12" {
        access = "memorymapped"
        width = "32"
        address = "0x474010ac"
        type = "USB0GENRNDISEP12__bitfield"
    }
    "USB0GENRNDISEP13" {
        access = "memorymapped"
        width = "32"
        address = "0x474010b0"
        type = "USB0GENRNDISEP13__bitfield"
    }
    "USB0GENRNDISEP14" {
        access = "memorymapped"
        width = "32"
        address = "0x474010b4"
        type = "USB0GENRNDISEP14__bitfield"
    }
    "USB0GENRNDISEP15" {
        access = "memorymapped"
        width = "32"
        address = "0x474010b8"
        type = "USB0GENRNDISEP15__bitfield"
    }
    "USB0GENRNDISEP2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401084"
        type = "USB0GENRNDISEP2__bitfield"
    }
    "USB0GENRNDISEP3" {
        access = "memorymapped"
        width = "32"
        address = "0x47401088"
        type = "USB0GENRNDISEP3__bitfield"
    }
    "USB0GENRNDISEP4" {
        access = "memorymapped"
        width = "32"
        address = "0x4740108c"
        type = "USB0GENRNDISEP4__bitfield"
    }
    "USB0GENRNDISEP5" {
        access = "memorymapped"
        width = "32"
        address = "0x47401090"
        type = "USB0GENRNDISEP5__bitfield"
    }
    "USB0GENRNDISEP6" {
        access = "memorymapped"
        width = "32"
        address = "0x47401094"
        type = "USB0GENRNDISEP6__bitfield"
    }
    "USB0GENRNDISEP7" {
        access = "memorymapped"
        width = "32"
        address = "0x47401098"
        type = "USB0GENRNDISEP7__bitfield"
    }
    "USB0GENRNDISEP8" {
        access = "memorymapped"
        width = "32"
        address = "0x4740109c"
        type = "USB0GENRNDISEP8__bitfield"
    }
    "USB0GENRNDISEP9" {
        access = "memorymapped"
        width = "32"
        address = "0x474010a0"
        type = "USB0GENRNDISEP9__bitfield"
    }
    "USB0IRQENABLECLR0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401040"
        type = "USB0IRQENABLECLR0__bitfield"
    }
    "USB0IRQENABLECLR1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401044"
        type = "USB0IRQENABLECLR1__bitfield"
    }
    "USB0IRQENABLESET0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401038"
        type = "USB0IRQENABLESET0__bitfield"
    }
    "USB0IRQENABLESET1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740103c"
        type = "USB0IRQENABLESET1__bitfield"
    }
    "USB0IRQMSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47401020"
        type = "USB0IRQMSTAT__bitfield"
    }
    "USB0IRQSTAT0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401030"
        type = "USB0IRQSTAT0__bitfield"
    }
    "USB0IRQSTAT1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401034"
        type = "USB0IRQSTAT1__bitfield"
    }
    "USB0IRQSTATRAW0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401028"
        type = "USB0IRQSTATRAW0__bitfield"
    }
    "USB0IRQSTATRAW1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740102c"
        type = "USB0IRQSTATRAW1__bitfield"
    }
    "USB0MGCUTMILB" {
        access = "memorymapped"
        width = "32"
        address = "0x474010e4"
        type = "USBUTMILB__bitfield"
    }
    "USB0MODE" {
        access = "memorymapped"
        width = "32"
        address = "0x474010e8"
        type = "USB0MODE__bitfield"
    }
    "USB0REV" {
        access = "memorymapped"
        width = "32"
        address = "0x47401000"
        type = "USB0REV__bitfield"
    }
    "USB0RXMODE" {
        access = "memorymapped"
        width = "32"
        address = "0x47401074"
        type = "USB0RXMODE__bitfield"
    }
    "USB0SRPFIXTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x474010d4"
        type = "USB0SRPFIXTIME__bitfield"
    }
    "USB0STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47401018"
        type = "USB0STAT__bitfield"
    }
    "USB0TXMODE" {
        access = "memorymapped"
        width = "32"
        address = "0x47401070"
        type = "USB0TXMODE__bitfield"
    }
    "USB0UTMI" {
        access = "memorymapped"
        width = "32"
        address = "0x474010e0"
        type = "USB0UTMI__bitfield"
    }
    "USB0_PHY_AD_INTERFACE_REG1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401344"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG1__bitfield"
    }
    "USB0_PHY_AD_INTERFACE_REG2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401348"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG2__bitfield"
    }
    "USB0_PHY_AD_INTERFACE_REG3" {
        access = "memorymapped"
        width = "32"
        address = "0x4740134c"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG3__bitfield"
    }
    "USB0_PHY_ANA_CONFIG1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401350"
        desc = "used to configure and debug the analog blocks. definitions are in DFT spec (if applicable)"
        type = "USB_PHY_ANA_CONFIG1__bitfield"
    }
    "USB0_PHY_ANA_CONFIG2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401354"
        desc = "used to configure and debug the analog blocks. definitions are in DFT spec (if applicable)"
        type = "USB_PHY_ANA_CONFIG2__bitfield"
    }
    "USB0_PHY_BIST" {
        access = "memorymapped"
        width = "32"
        address = "0x47401324"
        desc = "COntains bits related to the built in self test of the phy"
        type = "USB_PHY_BIST__bitfield"
    }
    "USB0_PHY_BIST_CRC" {
        access = "memorymapped"
        width = "32"
        address = "0x47401328"
        desc = "the CRC code for BIST test"
        type = "USB_PHY_BIST_CRC__bitfield"
    }
    "USB0_PHY_CDR_BIST2" {
        access = "memorymapped"
        width = "32"
        address = "0x4740132c"
        desc = "clock data recovery register and BIST register 2"
        type = "USB_PHY_CDR_BIST2__bitfield"
    }
    "USB0_PHY_CHRG_DET" {
        access = "memorymapped"
        width = "32"
        address = "0x47401314"
        desc = "this is the charger detect register. this register is not used in the dead battery case."
        type = "USB_PHY_CHRG_DET__bitfield"
    }
    "USB0_PHY_DLLHS" {
        access = "memorymapped"
        width = "32"
        address = "0x47401334"
        desc = "bits for control and debug of the DLL inside the phy"
        type = "USB_PHY_DLLHS__bitfield"
    }
    "USB0_PHY_DLLHS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401308"
        desc = "the 2nd DLLHS control register. bits 4:0 are unrelated to the DLLHS and are linestate filter settings"
        type = "USB_PHY_DLLHS_2__bitfield"
    }
    "USB0_PHY_GPIO" {
        access = "memorymapped"
        width = "32"
        address = "0x47401330"
        desc = "GPIO mode configurations and reads"
        type = "USB_PHY_GPIO__bitfield"
    }
    "USB0_PHY_PWR_CNTL" {
        access = "memorymapped"
        width = "32"
        address = "0x47401318"
        desc = "has all the power control bits"
        type = "USB_PHY_PWR_CNTL__bitfield"
    }
    "USB0_PHY_RX_CALIB" {
        access = "memorymapped"
        width = "32"
        address = "0x47401304"
        desc = "Contains bits related to RX calibration"
        type = "USB_PHY_RX_CALIB__bitfield"
    }
    "USB0_PHY_RX_DEBUG_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x47401358"
        desc = "not implemented"
        type = "USB_PHY_RX_DEBUG_REG__bitfield"
    }
    "USB0_PHY_RX_TEST_2" {
        access = "memorymapped"
        width = "32"
        address = "0x4740130c"
        desc = "the 2nd receiver test register"
        type = "USB_PHY_RX_TEST_2__bitfield"
    }
    "USB0_PHY_Termination_control" {
        access = "memorymapped"
        width = "32"
        address = "0x47401300"
        desc = "contains bits related to control of terminations in USB2PHY"
        type = "USB_PHY_Termination_control__bitfield"
    }
    "USB0_PHY_USB2PHYCM_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x4740133c"
        desc = "Config and status register for the USB2PHYCM and LDO"
        type = "USB_PHY_USB2PHYCM_CONFIG__bitfield"
    }
    "USB0_PHY_USB2PHYCM_TRIM" {
        access = "memorymapped"
        width = "32"
        address = "0x47401338"
        desc = "contains trim bit overrides for the USB2PHYCM"
        type = "USB_PHY_USB2PHYCM_TRIM__bitfield"
    }
    "USB0_PHY_USBOTG" {
        access = "memorymapped"
        width = "32"
        address = "0x47401340"
        type = "USB_PHY_USBOTG__bitfield"
    }
    "USB0_PHY_UTMI_INTERFACE_CNTL_1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740131c"
        desc = "register to override UTMI interface control pins."
        type = "USB_PHY_UTMI_INTERFACE_CNTL_1__bitfield"
    }
    "USB0_PHY_UTMI_INTERFACE_CNTL_2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401320"
        desc = "UTMI interface override and observe register 2"
        type = "USB_PHY_UTMI_INTERFACE_CNTL_2__bitfield"
    }
    "USB0_TDOWN" {
        access = "memorymapped"
        width = "32"
        address = "0x474010d8"
        type = "USBTDOWN__bitfield"
    }
    "USB1AUTOREQ" {
        access = "memorymapped"
        width = "32"
        address = "0x474018d0"
        type = "USB1AUTOREQ__bitfield"
    }
    "USB1CTRL" {
        access = "memorymapped"
        width = "32"
        address = "0x47401814"
        type = "USB1CTRL__bitfield"
    }
    "USB1GENRNDISEP1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401880"
        type = "USB1GENRNDISEP1__bitfield"
    }
    "USB1GENRNDISEP10" {
        access = "memorymapped"
        width = "32"
        address = "0x474018a4"
        type = "USB1GENRNDISEP10__bitfield"
    }
    "USB1GENRNDISEP11" {
        access = "memorymapped"
        width = "32"
        address = "0x474018a8"
        type = "USB1GENRNDISEP11__bitfield"
    }
    "USB1GENRNDISEP12" {
        access = "memorymapped"
        width = "32"
        address = "0x474018ac"
        type = "USB1GENRNDISEP12__bitfield"
    }
    "USB1GENRNDISEP13" {
        access = "memorymapped"
        width = "32"
        address = "0x474018b0"
        type = "USB1GENRNDISEP13__bitfield"
    }
    "USB1GENRNDISEP14" {
        access = "memorymapped"
        width = "32"
        address = "0x474018b4"
        type = "USB1GENRNDISEP14__bitfield"
    }
    "USB1GENRNDISEP15" {
        access = "memorymapped"
        width = "32"
        address = "0x474018b8"
        type = "USB1GENRNDISEP15__bitfield"
    }
    "USB1GENRNDISEP2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401884"
        type = "USB1GENRNDISEP2__bitfield"
    }
    "USB1GENRNDISEP3" {
        access = "memorymapped"
        width = "32"
        address = "0x47401888"
        type = "USB1GENRNDISEP3__bitfield"
    }
    "USB1GENRNDISEP4" {
        access = "memorymapped"
        width = "32"
        address = "0x4740188c"
        type = "USB1GENRNDISEP4__bitfield"
    }
    "USB1GENRNDISEP5" {
        access = "memorymapped"
        width = "32"
        address = "0x47401890"
        type = "USB1GENRNDISEP5__bitfield"
    }
    "USB1GENRNDISEP6" {
        access = "memorymapped"
        width = "32"
        address = "0x47401894"
        type = "USB1GENRNDISEP6__bitfield"
    }
    "USB1GENRNDISEP7" {
        access = "memorymapped"
        width = "32"
        address = "0x47401898"
        type = "USB1GENRNDISEP7__bitfield"
    }
    "USB1GENRNDISEP8" {
        access = "memorymapped"
        width = "32"
        address = "0x4740189c"
        type = "USB1GENRNDISEP8__bitfield"
    }
    "USB1GENRNDISEP9" {
        access = "memorymapped"
        width = "32"
        address = "0x474018a0"
        type = "USB1GENRNDISEP9__bitfield"
    }
    "USB1IRQENABLECLR0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401840"
        type = "USB1IRQENABLECLR0__bitfield"
    }
    "USB1IRQENABLECLR1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401844"
        type = "USB1IRQENABLECLR1__bitfield"
    }
    "USB1IRQENABLESET0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401838"
        type = "USB1IRQENABLESET0__bitfield"
    }
    "USB1IRQENABLESET1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740183c"
        type = "USB1IRQENABLESET1__bitfield"
    }
    "USB1IRQMSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47401820"
        type = "USB1IRQMSTAT__bitfield"
    }
    "USB1IRQSTAT0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401830"
        type = "USB1IRQSTAT0__bitfield"
    }
    "USB1IRQSTAT1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401834"
        type = "USB1IRQSTAT1__bitfield"
    }
    "USB1IRQSTATRAW0" {
        access = "memorymapped"
        width = "32"
        address = "0x47401828"
        type = "USB1IRQSTATRAW0__bitfield"
    }
    "USB1IRQSTATRAW1" {
        access = "memorymapped"
        width = "32"
        address = "0x4740182c"
        type = "USB1IRQSTATRAW1__bitfield"
    }
    "USB1MODE" {
        access = "memorymapped"
        width = "32"
        address = "0x474018e8"
        type = "USB1MODE__bitfield"
    }
    "USB1REV" {
        access = "memorymapped"
        width = "32"
        address = "0x47401800"
        type = "USB1REV__bitfield"
    }
    "USB1RXMODE" {
        access = "memorymapped"
        width = "32"
        address = "0x47401874"
        type = "USB1RXMODE__bitfield"
    }
    "USB1SRPFIXTIME" {
        access = "memorymapped"
        width = "32"
        address = "0x474018d4"
        type = "USB1SRPFIXTIME__bitfield"
    }
    "USB1STAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47401818"
        type = "USB1STAT__bitfield"
    }
    "USB1TDOWN" {
        access = "memorymapped"
        width = "32"
        address = "0x474018d8"
        type = "USBTDOWN__bitfield"
    }
    "USB1TXMODE" {
        access = "memorymapped"
        width = "32"
        address = "0x47401870"
        type = "USB1TXMODE__bitfield"
    }
    "USB1UTMI" {
        access = "memorymapped"
        width = "32"
        address = "0x474018e0"
        type = "USB1UTMI__bitfield"
    }
    "USB1UTMILB" {
        access = "memorymapped"
        width = "32"
        address = "0x474018e4"
        type = "USBUTMILB__bitfield"
    }
    "USB1_PHY_AD_INTERFACE_REG1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b44"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG1__bitfield"
    }
    "USB1_PHY_AD_INTERFACE_REG2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b48"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG2__bitfield"
    }
    "USB1_PHY_AD_INTERFACE_REG3" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b4c"
        desc = "All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name.  All the bits of this register, except the over-ride bits return a '0' on read, if  VDDLDO is off."
        type = "USB_PHY_AD_INTERFACE_REG3__bitfield"
    }
    "USB1_PHY_ANA_CONFIG1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b50"
        desc = "used to configure and debug the analog blocks. definitions are in DFT spec (if applicable)"
        type = "USB_PHY_ANA_CONFIG1__bitfield"
    }
    "USB1_PHY_ANA_CONFIG2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b54"
        desc = "used to configure and debug the analog blocks. definitions are in DFT spec (if applicable)"
        type = "USB_PHY_ANA_CONFIG2__bitfield"
    }
    "USB1_PHY_BIST" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b24"
        desc = "COntains bits related to the built in self test of the phy"
        type = "USB_PHY_BIST__bitfield"
    }
    "USB1_PHY_BIST_CRC" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b28"
        desc = "the CRC code for BIST test"
        type = "USB_PHY_BIST_CRC__bitfield"
    }
    "USB1_PHY_CDR_BIST2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b2c"
        desc = "clock data recovery register and BIST register 2"
        type = "USB_PHY_CDR_BIST2__bitfield"
    }
    "USB1_PHY_CHRG_DET" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b14"
        desc = "this is the charger detect register. this register is not used in the dead battery case."
        type = "USB_PHY_CHRG_DET__bitfield"
    }
    "USB1_PHY_DLLHS" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b34"
        desc = "bits for control and debug of the DLL inside the phy"
        type = "USB_PHY_DLLHS__bitfield"
    }
    "USB1_PHY_DLLHS_2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b08"
        desc = "the 2nd DLLHS control register. bits 4:0 are unrelated to the DLLHS and are linestate filter settings"
        type = "USB_PHY_DLLHS_2__bitfield"
    }
    "USB1_PHY_GPIO" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b30"
        desc = "GPIO mode configurations and reads"
        type = "USB_PHY_GPIO__bitfield"
    }
    "USB1_PHY_PWR_CNTL" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b18"
        desc = "has all the power control bits"
        type = "USB_PHY_PWR_CNTL__bitfield"
    }
    "USB1_PHY_RX_CALIB" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b04"
        desc = "Contains bits related to RX calibration"
        type = "USB_PHY_RX_CALIB__bitfield"
    }
    "USB1_PHY_RX_DEBUG_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b58"
        desc = "not implemented"
        type = "USB_PHY_RX_DEBUG_REG__bitfield"
    }
    "USB1_PHY_RX_TEST_2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b0c"
        desc = "the 2nd receiver test register"
        type = "USB_PHY_RX_TEST_2__bitfield"
    }
    "USB1_PHY_Termination_control" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b00"
        desc = "contains bits related to control of terminations in USB2PHY"
        type = "USB_PHY_Termination_control__bitfield"
    }
    "USB1_PHY_USB2PHYCM_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b3c"
        desc = "Config and status register for the USB2PHYCM and LDO"
        type = "USB_PHY_USB2PHYCM_CONFIG__bitfield"
    }
    "USB1_PHY_USB2PHYCM_TRIM" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b38"
        desc = "contains trim bit overrides for the USB2PHYCM"
        type = "USB_PHY_USB2PHYCM_TRIM__bitfield"
    }
    "USB1_PHY_USBOTG" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b40"
        type = "USB_PHY_USBOTG__bitfield"
    }
    "USB1_PHY_UTMI_INTERFACE_CNTL_1" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b1c"
        desc = "register to override UTMI interface control pins."
        type = "USB_PHY_UTMI_INTERFACE_CNTL_1__bitfield"
    }
    "USB1_PHY_UTMI_INTERFACE_CNTL_2" {
        access = "memorymapped"
        width = "32"
        address = "0x47401b20"
        desc = "UTMI interface override and observe register 2"
        type = "USB_PHY_UTMI_INTERFACE_CNTL_2__bitfield"
    }
    "USBSS_IRQCLEARR" {
        access = "memorymapped"
        width = "32"
        address = "0x47400030"
        type = "USBSS_IRQCLEARR__bitfield"
    }
    "USBSS_IRQDMAENABLE0" {
        access = "memorymapped"
        width = "32"
        address = "0x47400140"
        type = "USBSS_IRQDMAENABLE0__bitfield"
    }
    "USBSS_IRQDMAENABLE1" {
        access = "memorymapped"
        width = "32"
        address = "0x47400144"
        type = "USBSS_IRQDMAENABLE1__bitfield"
    }
    "USBSS_IRQDMATHOLDRX00" {
        access = "memorymapped"
        width = "32"
        address = "0x47400110"
        type = "USBSS_IRQDMATHOLDRX00__bitfield"
    }
    "USBSS_IRQDMATHOLDRX01" {
        access = "memorymapped"
        width = "32"
        address = "0x47400114"
        type = "USBSS_IRQDMATHOLDRX01__bitfield"
    }
    "USBSS_IRQDMATHOLDRX02" {
        access = "memorymapped"
        width = "32"
        address = "0x47400118"
        type = "USBSS_IRQDMATHOLDRX02__bitfield"
    }
    "USBSS_IRQDMATHOLDRX03" {
        access = "memorymapped"
        width = "32"
        address = "0x4740011c"
        type = "USBSS_IRQDMATHOLDRX03__bitfield"
    }
    "USBSS_IRQDMATHOLDRX10" {
        access = "memorymapped"
        width = "32"
        address = "0x47400130"
        type = "USBSS_IRQDMATHOLDRX10__bitfield"
    }
    "USBSS_IRQDMATHOLDRX11" {
        access = "memorymapped"
        width = "32"
        address = "0x47400134"
        type = "USBSS_IRQDMATHOLDRX11__bitfield"
    }
    "USBSS_IRQDMATHOLDRX12" {
        access = "memorymapped"
        width = "32"
        address = "0x47400138"
        type = "USBSS_IRQDMATHOLDRX12__bitfield"
    }
    "USBSS_IRQDMATHOLDRX13" {
        access = "memorymapped"
        width = "32"
        address = "0x4740013c"
        type = "USBSS_IRQDMATHOLDRX13__bitfield"
    }
    "USBSS_IRQDMATHOLDTX00" {
        access = "memorymapped"
        width = "32"
        address = "0x47400100"
        type = "USBSS_IRQDMATHOLDTX00__bitfield"
    }
    "USBSS_IRQDMATHOLDTX01" {
        access = "memorymapped"
        width = "32"
        address = "0x47400104"
        type = "USBSS_IRQDMATHOLDTX01__bitfield"
    }
    "USBSS_IRQDMATHOLDTX02" {
        access = "memorymapped"
        width = "32"
        address = "0x47400108"
        type = "USBSS_IRQDMATHOLDTX02__bitfield"
    }
    "USBSS_IRQDMATHOLDTX03" {
        access = "memorymapped"
        width = "32"
        address = "0x4740010c"
        type = "USBSS_IRQDMATHOLDTX03__bitfield"
    }
    "USBSS_IRQDMATHOLDTX10" {
        access = "memorymapped"
        width = "32"
        address = "0x47400120"
        type = "USBSS_IRQDMATHOLDTX10__bitfield"
    }
    "USBSS_IRQDMATHOLDTX11" {
        access = "memorymapped"
        width = "32"
        address = "0x47400124"
        type = "USBSS_IRQDMATHOLDTX11__bitfield"
    }
    "USBSS_IRQDMATHOLDTX12" {
        access = "memorymapped"
        width = "32"
        address = "0x47400128"
        type = "USBSS_IRQDMATHOLDTX12__bitfield"
    }
    "USBSS_IRQDMATHOLDTX13" {
        access = "memorymapped"
        width = "32"
        address = "0x4740012c"
        type = "USBSS_IRQDMATHOLDTX13__bitfield"
    }
    "USBSS_IRQENABLER" {
        access = "memorymapped"
        width = "32"
        address = "0x4740002c"
        type = "USBSS_IRQENABLER__bitfield"
    }
    "USBSS_IRQFRAMEENABLE0" {
        access = "memorymapped"
        width = "32"
        address = "0x47400240"
        type = "USBSS_IRQFRAMEENABLE0__bitfield"
    }
    "USBSS_IRQFRAMEENABLE1" {
        access = "memorymapped"
        width = "32"
        address = "0x47400244"
        type = "USBSS_IRQFRAMEENABLE1__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX00" {
        access = "memorymapped"
        width = "32"
        address = "0x47400210"
        type = "USBSS_IRQFRAMETHOLDRX00__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX01" {
        access = "memorymapped"
        width = "32"
        address = "0x47400214"
        type = "USBSS_IRQFRAMETHOLDRX01__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX02" {
        access = "memorymapped"
        width = "32"
        address = "0x47400218"
        type = "USBSS_IRQFRAMETHOLDRX02__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX03" {
        access = "memorymapped"
        width = "32"
        address = "0x4740021c"
        type = "USBSS_IRQFRAMETHOLDRX03__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX10" {
        access = "memorymapped"
        width = "32"
        address = "0x47400230"
        type = "USBSS_IRQFRAMETHOLDRX10__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX11" {
        access = "memorymapped"
        width = "32"
        address = "0x47400234"
        type = "USBSS_IRQFRAMETHOLDRX11__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX12" {
        access = "memorymapped"
        width = "32"
        address = "0x47400238"
        type = "USBSS_IRQFRAMETHOLDRX12__bitfield"
    }
    "USBSS_IRQFRAMETHOLDRX13" {
        access = "memorymapped"
        width = "32"
        address = "0x4740023c"
        type = "USBSS_IRQFRAMETHOLDRX13__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX00" {
        access = "memorymapped"
        width = "32"
        address = "0x47400200"
        type = "USBSS_IRQFRAMETHOLDTX00__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX01" {
        access = "memorymapped"
        width = "32"
        address = "0x47400204"
        type = "USBSS_IRQFRAMETHOLDTX01__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX02" {
        access = "memorymapped"
        width = "32"
        address = "0x47400208"
        type = "USBSS_IRQFRAMETHOLDTX02__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX03" {
        access = "memorymapped"
        width = "32"
        address = "0x4740020c"
        type = "USBSS_IRQFRAMETHOLDTX03__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX10" {
        access = "memorymapped"
        width = "32"
        address = "0x47400220"
        type = "USBSS_IRQFRAMETHOLDTX10__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX11" {
        access = "memorymapped"
        width = "32"
        address = "0x47400224"
        type = "USBSS_IRQFRAMETHOLDTX11__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX12" {
        access = "memorymapped"
        width = "32"
        address = "0x47400228"
        type = "USBSS_IRQFRAMETHOLDTX12__bitfield"
    }
    "USBSS_IRQFRAMETHOLDTX13" {
        access = "memorymapped"
        width = "32"
        address = "0x4740022c"
        type = "USBSS_IRQFRAMETHOLDTX13__bitfield"
    }
    "USBSS_IRQSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x47400028"
        type = "USBSS_IRQSTAT__bitfield"
    }
    "USBSS_IRQSTATRAW" {
        access = "memorymapped"
        width = "32"
        address = "0x47400024"
        type = "USBSS_IRQSTATRAW__bitfield"
    }
    "USBSS_REVREG" {
        access = "memorymapped"
        width = "32"
        address = "0x47400000"
        type = "USBSS_REVREG__bitfield"
    }
    "USBSS_SYSCONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x47400010"
        type = "USBSS_SYSCONFIG__bitfield"
    }
    "Undersize_Rx_Frames" {
        access = "memorymapped"
        width = "32"
        address = "0x4a100920"
    }
    "WDT_WCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35024"
        desc = "The WDT_WCLR register controls the prescaler stage of the counter."
        type = "WDT_WCLR__bitfield"
    }
    "WDT_WCRR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35028"
        desc = "The WDT_WCRR register holds the value of the internal counter."
        type = "WDT_WCRR__bitfield"
    }
    "WDT_WDLY" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35044"
        desc = "ThE WDT_WDLY register holds the delay value that controls the internal pre-overflow event detection."
        type = "WDT_WDLY__bitfield"
    }
    "WDT_WDSC" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35010"
        desc = "This register controls the various parameters of the L4 interface."
        type = "WDT_WDSC__bitfield"
    }
    "WDT_WDST" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35014"
        desc = "The WDT_WDST register provides status information about the module."
        type = "WDT_WDST__bitfield"
    }
    "WDT_WIDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35000"
        type = "WDT_WIDR__bitfield"
    }
    "WDT_WIER" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3501c"
        desc = "The WDT_WIERs register controls (enable/disable) the interrupt events."
        type = "WDT_WIER__bitfield"
    }
    "WDT_WIRQENCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35060"
        desc = "IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
        type = "WDT_WIRQEN__bitfield"
    }
    "WDT_WIRQENSET" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3505c"
        desc = "IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
        type = "WDT_WIRQEN__bitfield"
    }
    "WDT_WIRQSTAT" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35058"
        desc = "IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
        type = "WDT_WIRQSTAT__bitfield"
    }
    "WDT_WIRQSTATRAW" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35054"
        desc = "IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
        type = "WDT_WIRQSTATRAW__bitfield"
    }
    "WDT_WISR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35018"
        desc = "This register shows which interrupt events are pending inside the module."
        type = "WDT_WISR__bitfield"
    }
    "WDT_WLDR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3502c"
        desc = "The WDT_WLDR register holds the timer load value."
        type = "WDT_WLDR__bitfield"
    }
    "WDT_WSPR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35048"
        desc = "The WDT_WSPR register holds the start-stop value that controls the internal start-stop FSM."
        type = "WDT_WSPR__bitfield"
    }
    "WDT_WTGR" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35030"
        desc = "Writing a different value than the one already written in this register does a watchdog counter reload."
        type = "WDT_WTGR__bitfield"
    }
    "WDT_WWPS" {
        access = "memorymapped"
        width = "32"
        address = "0x44e35034"
        desc = "This register contains the write posting bits for all writeable functional registers."
        type = "WDT_WWPS__bitfield"
    }
    "WEEKS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e018"
        desc = "The WEEKS_REG is used to program the day of the week value of the current date. The day of the week is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. Sunday is treated as 0, Monday 1, and ending at Saturday with 6."
        type = "WEEKS_REG__bitfield"
    }
    "WORD0" {
        access = "memorymapped"
        width = "32"
        address = "0x47403800"
        type = "WORD__bitfield"
    }
    "WORD1" {
        access = "memorymapped"
        width = "32"
        address = "0x47403804"
        type = "WORD__bitfield"
    }
    "WORD10" {
        access = "memorymapped"
        width = "32"
        address = "0x47403828"
        type = "WORD__bitfield"
    }
    "WORD11" {
        access = "memorymapped"
        width = "32"
        address = "0x4740382c"
        type = "WORD__bitfield"
    }
    "WORD12" {
        access = "memorymapped"
        width = "32"
        address = "0x47403830"
        type = "WORD__bitfield"
    }
    "WORD13" {
        access = "memorymapped"
        width = "32"
        address = "0x47403834"
        type = "WORD__bitfield"
    }
    "WORD14" {
        access = "memorymapped"
        width = "32"
        address = "0x47403838"
        type = "WORD__bitfield"
    }
    "WORD15" {
        access = "memorymapped"
        width = "32"
        address = "0x4740383c"
        type = "WORD__bitfield"
    }
    "WORD16" {
        access = "memorymapped"
        width = "32"
        address = "0x47403840"
        type = "WORD__bitfield"
    }
    "WORD17" {
        access = "memorymapped"
        width = "32"
        address = "0x47403844"
        type = "WORD__bitfield"
    }
    "WORD18" {
        access = "memorymapped"
        width = "32"
        address = "0x47403848"
        type = "WORD__bitfield"
    }
    "WORD19" {
        access = "memorymapped"
        width = "32"
        address = "0x4740384c"
        type = "WORD__bitfield"
    }
    "WORD2" {
        access = "memorymapped"
        width = "32"
        address = "0x47403808"
        type = "WORD__bitfield"
    }
    "WORD20" {
        access = "memorymapped"
        width = "32"
        address = "0x47403850"
        type = "WORD__bitfield"
    }
    "WORD21" {
        access = "memorymapped"
        width = "32"
        address = "0x47403854"
        type = "WORD__bitfield"
    }
    "WORD22" {
        access = "memorymapped"
        width = "32"
        address = "0x47403858"
        type = "WORD__bitfield"
    }
    "WORD23" {
        access = "memorymapped"
        width = "32"
        address = "0x4740385c"
        type = "WORD__bitfield"
    }
    "WORD24" {
        access = "memorymapped"
        width = "32"
        address = "0x47403860"
        type = "WORD__bitfield"
    }
    "WORD25" {
        access = "memorymapped"
        width = "32"
        address = "0x47403864"
        type = "WORD__bitfield"
    }
    "WORD26" {
        access = "memorymapped"
        width = "32"
        address = "0x47403868"
        type = "WORD__bitfield"
    }
    "WORD27" {
        access = "memorymapped"
        width = "32"
        address = "0x4740386c"
        type = "WORD__bitfield"
    }
    "WORD28" {
        access = "memorymapped"
        width = "32"
        address = "0x47403870"
        type = "WORD__bitfield"
    }
    "WORD29" {
        access = "memorymapped"
        width = "32"
        address = "0x47403874"
        type = "WORD__bitfield"
    }
    "WORD30" {
        access = "memorymapped"
        width = "32"
        address = "0x47403878"
        type = "WORD__bitfield"
    }
    "WORD31" {
        access = "memorymapped"
        width = "32"
        address = "0x4740387c"
        type = "WORD__bitfield"
    }
    "WORD32" {
        access = "memorymapped"
        width = "32"
        address = "0x47403880"
        type = "WORD__bitfield"
    }
    "WORD33" {
        access = "memorymapped"
        width = "32"
        address = "0x47403884"
        type = "WORD__bitfield"
    }
    "WORD34" {
        access = "memorymapped"
        width = "32"
        address = "0x47403888"
        type = "WORD__bitfield"
    }
    "WORD35" {
        access = "memorymapped"
        width = "32"
        address = "0x4740388c"
        type = "WORD__bitfield"
    }
    "WORD36" {
        access = "memorymapped"
        width = "32"
        address = "0x47403890"
        type = "WORD__bitfield"
    }
    "WORD37" {
        access = "memorymapped"
        width = "32"
        address = "0x47403894"
        type = "WORD__bitfield"
    }
    "WORD38" {
        access = "memorymapped"
        width = "32"
        address = "0x47403898"
        type = "WORD__bitfield"
    }
    "WORD39" {
        access = "memorymapped"
        width = "32"
        address = "0x4740389c"
        type = "WORD__bitfield"
    }
    "WORD40" {
        access = "memorymapped"
        width = "32"
        address = "0x474038a0"
        type = "WORD__bitfield"
    }
    "WORD41" {
        access = "memorymapped"
        width = "32"
        address = "0x474038a4"
        type = "WORD__bitfield"
    }
    "WORD42" {
        access = "memorymapped"
        width = "32"
        address = "0x474038a8"
        type = "WORD__bitfield"
    }
    "WORD43" {
        access = "memorymapped"
        width = "32"
        address = "0x474038ac"
        type = "WORD__bitfield"
    }
    "WORD44" {
        access = "memorymapped"
        width = "32"
        address = "0x474038b0"
        type = "WORD__bitfield"
    }
    "WORD45" {
        access = "memorymapped"
        width = "32"
        address = "0x474038b4"
        type = "WORD__bitfield"
    }
    "WORD46" {
        access = "memorymapped"
        width = "32"
        address = "0x474038b8"
        type = "WORD__bitfield"
    }
    "WORD47" {
        access = "memorymapped"
        width = "32"
        address = "0x474038bc"
        type = "WORD__bitfield"
    }
    "WORD48" {
        access = "memorymapped"
        width = "32"
        address = "0x474038c0"
        type = "WORD__bitfield"
    }
    "WORD49" {
        access = "memorymapped"
        width = "32"
        address = "0x474038c4"
        type = "WORD__bitfield"
    }
    "WORD5" {
        access = "memorymapped"
        width = "32"
        address = "0x47403814"
        type = "WORD__bitfield"
    }
    "WORD50" {
        access = "memorymapped"
        width = "32"
        address = "0x474038c8"
        type = "WORD__bitfield"
    }
    "WORD51" {
        access = "memorymapped"
        width = "32"
        address = "0x474038cc"
        type = "WORD__bitfield"
    }
    "WORD52" {
        access = "memorymapped"
        width = "32"
        address = "0x474038d0"
        type = "WORD__bitfield"
    }
    "WORD53" {
        access = "memorymapped"
        width = "32"
        address = "0x474038d4"
        type = "WORD__bitfield"
    }
    "WORD54" {
        access = "memorymapped"
        width = "32"
        address = "0x474038d8"
        type = "WORD__bitfield"
    }
    "WORD55" {
        access = "memorymapped"
        width = "32"
        address = "0x474038dc"
        type = "WORD__bitfield"
    }
    "WORD56" {
        access = "memorymapped"
        width = "32"
        address = "0x474038e0"
        type = "WORD__bitfield"
    }
    "WORD57" {
        access = "memorymapped"
        width = "32"
        address = "0x474038e4"
        type = "WORD__bitfield"
    }
    "WORD58" {
        access = "memorymapped"
        width = "32"
        address = "0x474038e8"
        type = "WORD__bitfield"
    }
    "WORD59" {
        access = "memorymapped"
        width = "32"
        address = "0x474038ec"
        type = "WORD__bitfield"
    }
    "WORD6" {
        access = "memorymapped"
        width = "32"
        address = "0x47403818"
        type = "WORD__bitfield"
    }
    "WORD60" {
        access = "memorymapped"
        width = "32"
        address = "0x474038f0"
        type = "WORD__bitfield"
    }
    "WORD61" {
        access = "memorymapped"
        width = "32"
        address = "0x474038f4"
        type = "WORD__bitfield"
    }
    "WORD62" {
        access = "memorymapped"
        width = "32"
        address = "0x474038f8"
        type = "WORD__bitfield"
    }
    "WORD63" {
        access = "memorymapped"
        width = "32"
        address = "0x474038fc"
        type = "WORD__bitfield"
    }
    "WORD7" {
        access = "memorymapped"
        width = "32"
        address = "0x4740381c"
        type = "WORD__bitfield"
    }
    "WORD8" {
        access = "memorymapped"
        width = "32"
        address = "0x47403820"
        type = "WORD__bitfield"
    }
    "WORD9" {
        access = "memorymapped"
        width = "32"
        address = "0x47403824"
        type = "WORD__bitfield"
    }
    "YEARS_REG" {
        access = "memorymapped"
        width = "32"
        address = "0x44e3e014"
        desc = "The YEARS_REG is used to program the year value of the current date. The year value is represented by only the last 2 digits and is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. The year 1979 is programmed as 79 with YEAR0 set as 9 and YEAR1 set as 7."
        type = "YEARS_REG__bitfield"
    }
    "ZQ_CONFIG" {
        access = "memorymapped"
        width = "32"
        address = "0x4c0000c8"
        type = "ZQ_CONFIG__bitfield"
    }
    "adc_evt_capt" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fd8"
    }
    "bandgap_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10448"
    }
    "bandgap_trim" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1044c"
    }
    "bb_scale" {
        access = "memorymapped"
        width = "32"
        address = "0x44e107d0"
    }
    "clk32kdivratio_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10444"
    }
    "control_hwinfo" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10004"
    }
    "control_revision" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10000"
    }
    "control_status" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10040"
    }
    "control_sysconfig" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10010"
    }
    "core_sldo_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10428"
    }
    "cortex_vbbldo_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1041c"
    }
    "cqdetect_status" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10e00"
    }
    "dcan_raminit" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10644"
    }
    "ddr_cke_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1131c"
    }
    "ddr_cmd0_ioctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11404"
    }
    "ddr_cmd1_ioctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11408"
    }
    "ddr_cmd2_ioctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1140c"
    }
    "ddr_data0_ioctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11440"
    }
    "ddr_data1_ioctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11444"
    }
    "ddr_io_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10e04"
    }
    "deepsleep_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10470"
    }
    "dev_feature" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10604"
    }
    "device_id" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10600"
    }
    "eCAP0_CAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x48300108"
    }
    "eCAP0_CAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830010c"
    }
    "eCAP0_CAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x48300110"
    }
    "eCAP0_CAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x48300114"
    }
    "eCAP0_CTRPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48300104"
    }
    "eCAP0_ECCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48300130"
    }
    "eCAP0_ECCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x48300128"
    }
    "eCAP0_ECCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830012a"
    }
    "eCAP0_ECEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830012c"
    }
    "eCAP0_ECFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830012e"
    }
    "eCAP0_ECFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48300132"
    }
    "eCAP0_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x4830015c"
    }
    "eCAP0_TSCTR" {
        access = "memorymapped"
        width = "32"
        address = "0x48300100"
    }
    "eCAP1_CAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x48302108"
    }
    "eCAP1_CAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830210c"
    }
    "eCAP1_CAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x48302110"
    }
    "eCAP1_CAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x48302114"
    }
    "eCAP1_CTRPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48302104"
    }
    "eCAP1_ECCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48302130"
    }
    "eCAP1_ECCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x48302128"
    }
    "eCAP1_ECCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830212a"
    }
    "eCAP1_ECEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830212c"
    }
    "eCAP1_ECFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830212e"
    }
    "eCAP1_ECFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48302132"
    }
    "eCAP1_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x4830215c"
    }
    "eCAP1_TSCTR" {
        access = "memorymapped"
        width = "32"
        address = "0x48302100"
    }
    "eCAP2_CAP1" {
        access = "memorymapped"
        width = "32"
        address = "0x48304108"
    }
    "eCAP2_CAP2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830410c"
    }
    "eCAP2_CAP3" {
        access = "memorymapped"
        width = "32"
        address = "0x48304110"
    }
    "eCAP2_CAP4" {
        access = "memorymapped"
        width = "32"
        address = "0x48304114"
    }
    "eCAP2_CTRPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48304104"
    }
    "eCAP2_ECCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48304130"
    }
    "eCAP2_ECCTL1" {
        access = "memorymapped"
        width = "32"
        address = "0x48304128"
    }
    "eCAP2_ECCTL2" {
        access = "memorymapped"
        width = "32"
        address = "0x4830412a"
    }
    "eCAP2_ECEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830412c"
    }
    "eCAP2_ECFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830412e"
    }
    "eCAP2_ECFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48304132"
    }
    "eCAP2_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x4830415c"
    }
    "eCAP2_TSCTR" {
        access = "memorymapped"
        width = "32"
        address = "0x48304100"
    }
    "ePWM0_AQCSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830021c"
    }
    "ePWM0_AQCTLA" {
        access = "memorymapped"
        width = "32"
        address = "0x48300216"
    }
    "ePWM0_AQCTLB" {
        access = "memorymapped"
        width = "32"
        address = "0x48300218"
    }
    "ePWM0_AQSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830021a"
    }
    "ePWM0_CMPA" {
        access = "memorymapped"
        width = "32"
        address = "0x48300212"
    }
    "ePWM0_CMPAHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48300210"
    }
    "ePWM0_CMPB" {
        access = "memorymapped"
        width = "32"
        address = "0x48300214"
    }
    "ePWM0_CMPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830020e"
    }
    "ePWM0_DBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830021e"
    }
    "ePWM0_DBFED" {
        access = "memorymapped"
        width = "32"
        address = "0x48300222"
    }
    "ePWM0_DBRED" {
        access = "memorymapped"
        width = "32"
        address = "0x48300220"
    }
    "ePWM0_ETCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48300238"
    }
    "ePWM0_ETFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x48300236"
    }
    "ePWM0_ETFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830023a"
    }
    "ePWM0_ETPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48300234"
    }
    "ePWM0_ETSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48300232"
    }
    "ePWM0_HRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48300240"
    }
    "ePWM0_PCCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830023c"
    }
    "ePWM0_TBCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300208"
    }
    "ePWM0_TBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48300200"
    }
    "ePWM0_TBPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48300206"
    }
    "ePWM0_TBPHSHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48300204"
    }
    "ePWM0_TBPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x4830020a"
    }
    "ePWM0_TBSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x48300202"
    }
    "ePWM0_TZCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830022e"
    }
    "ePWM0_TZCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48300228"
    }
    "ePWM0_TZEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830022a"
    }
    "ePWM0_TZFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830022c"
    }
    "ePWM0_TZFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48300230"
    }
    "ePWM0_TZSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48300224"
    }
    "ePWM1_AQCSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830221c"
    }
    "ePWM1_AQCTLA" {
        access = "memorymapped"
        width = "32"
        address = "0x48302216"
    }
    "ePWM1_AQCTLB" {
        access = "memorymapped"
        width = "32"
        address = "0x48302218"
    }
    "ePWM1_AQSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830221a"
    }
    "ePWM1_CMPA" {
        access = "memorymapped"
        width = "32"
        address = "0x48302212"
    }
    "ePWM1_CMPAHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48302210"
    }
    "ePWM1_CMPB" {
        access = "memorymapped"
        width = "32"
        address = "0x48302214"
    }
    "ePWM1_CMPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830220e"
    }
    "ePWM1_DBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830221e"
    }
    "ePWM1_DBFED" {
        access = "memorymapped"
        width = "32"
        address = "0x48302222"
    }
    "ePWM1_DBRED" {
        access = "memorymapped"
        width = "32"
        address = "0x48302220"
    }
    "ePWM1_ETCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48302238"
    }
    "ePWM1_ETFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x48302236"
    }
    "ePWM1_ETFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830223a"
    }
    "ePWM1_ETPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48302234"
    }
    "ePWM1_ETSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48302232"
    }
    "ePWM1_HRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48302240"
    }
    "ePWM1_PCCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830223c"
    }
    "ePWM1_TBCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302208"
    }
    "ePWM1_TBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48302200"
    }
    "ePWM1_TBPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48302206"
    }
    "ePWM1_TBPHSHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48302204"
    }
    "ePWM1_TBPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x4830220a"
    }
    "ePWM1_TBSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x48302202"
    }
    "ePWM1_TZCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830222e"
    }
    "ePWM1_TZCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48302228"
    }
    "ePWM1_TZEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830222a"
    }
    "ePWM1_TZFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830222c"
    }
    "ePWM1_TZFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48302230"
    }
    "ePWM1_TZSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48302224"
    }
    "ePWM2_AQCSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830421c"
    }
    "ePWM2_AQCTLA" {
        access = "memorymapped"
        width = "32"
        address = "0x48304216"
    }
    "ePWM2_AQCTLB" {
        access = "memorymapped"
        width = "32"
        address = "0x48304218"
    }
    "ePWM2_AQSFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830421a"
    }
    "ePWM2_CMPA" {
        access = "memorymapped"
        width = "32"
        address = "0x48304212"
    }
    "ePWM2_CMPAHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48304210"
    }
    "ePWM2_CMPB" {
        access = "memorymapped"
        width = "32"
        address = "0x48304214"
    }
    "ePWM2_CMPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830420e"
    }
    "ePWM2_DBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830421e"
    }
    "ePWM2_DBFED" {
        access = "memorymapped"
        width = "32"
        address = "0x48304222"
    }
    "ePWM2_DBRED" {
        access = "memorymapped"
        width = "32"
        address = "0x48304220"
    }
    "ePWM2_ETCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x48304238"
    }
    "ePWM2_ETFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x48304236"
    }
    "ePWM2_ETFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x4830423a"
    }
    "ePWM2_ETPS" {
        access = "memorymapped"
        width = "32"
        address = "0x48304234"
    }
    "ePWM2_ETSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48304232"
    }
    "ePWM2_HRCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48304240"
    }
    "ePWM2_PCCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x4830423c"
    }
    "ePWM2_TBCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304208"
    }
    "ePWM2_TBCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48304200"
    }
    "ePWM2_TBPHS" {
        access = "memorymapped"
        width = "32"
        address = "0x48304206"
    }
    "ePWM2_TBPHSHR" {
        access = "memorymapped"
        width = "32"
        address = "0x48304204"
    }
    "ePWM2_TBPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x4830420a"
    }
    "ePWM2_TBSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x48304202"
    }
    "ePWM2_TZCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830422e"
    }
    "ePWM2_TZCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x48304228"
    }
    "ePWM2_TZEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x4830422a"
    }
    "ePWM2_TZFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x4830422c"
    }
    "ePWM2_TZFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x48304230"
    }
    "ePWM2_TZSEL" {
        access = "memorymapped"
        width = "32"
        address = "0x48304224"
    }
    "eQEP0_QCAPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483001ac"
    }
    "eQEP0_QCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x483001b4"
    }
    "eQEP0_QCPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483001bc"
    }
    "eQEP0_QCPRDLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483001c0"
    }
    "eQEP0_QCTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483001ba"
    }
    "eQEP0_QCTMRLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483001be"
    }
    "eQEP0_QDECCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483001a8"
    }
    "eQEP0_QEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x483001b0"
    }
    "eQEP0_QEPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483001aa"
    }
    "eQEP0_QEPSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x483001b8"
    }
    "eQEP0_QFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x483001b2"
    }
    "eQEP0_QFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x483001b6"
    }
    "eQEP0_QPOSCMP" {
        access = "memorymapped"
        width = "32"
        address = "0x4830018c"
    }
    "eQEP0_QPOSCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300180"
    }
    "eQEP0_QPOSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483001ae"
    }
    "eQEP0_QPOSILAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300190"
    }
    "eQEP0_QPOSINIT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300184"
    }
    "eQEP0_QPOSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300198"
    }
    "eQEP0_QPOSMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x48300188"
    }
    "eQEP0_QPOSSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48300194"
    }
    "eQEP0_QUPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483001a0"
    }
    "eQEP0_QUTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830019c"
    }
    "eQEP0_QWDPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483001a6"
    }
    "eQEP0_QWDTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483001a4"
    }
    "eQEP0_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x483001dc"
    }
    "eQEP1_QCAPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483021ac"
    }
    "eQEP1_QCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x483021b4"
    }
    "eQEP1_QCPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483021bc"
    }
    "eQEP1_QCPRDLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483021c0"
    }
    "eQEP1_QCTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483021ba"
    }
    "eQEP1_QCTMRLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483021be"
    }
    "eQEP1_QDECCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483021a8"
    }
    "eQEP1_QEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x483021b0"
    }
    "eQEP1_QEPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483021aa"
    }
    "eQEP1_QEPSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x483021b8"
    }
    "eQEP1_QFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x483021b2"
    }
    "eQEP1_QFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x483021b6"
    }
    "eQEP1_QPOSCMP" {
        access = "memorymapped"
        width = "32"
        address = "0x4830218c"
    }
    "eQEP1_QPOSCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302180"
    }
    "eQEP1_QPOSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483021ae"
    }
    "eQEP1_QPOSILAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302190"
    }
    "eQEP1_QPOSINIT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302184"
    }
    "eQEP1_QPOSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302198"
    }
    "eQEP1_QPOSMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x48302188"
    }
    "eQEP1_QPOSSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48302194"
    }
    "eQEP1_QUPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483021a0"
    }
    "eQEP1_QUTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830219c"
    }
    "eQEP1_QWDPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483021a6"
    }
    "eQEP1_QWDTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483021a4"
    }
    "eQEP1_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x483021dc"
    }
    "eQEP2_QCAPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483041ac"
    }
    "eQEP2_QCLR" {
        access = "memorymapped"
        width = "32"
        address = "0x483041b4"
    }
    "eQEP2_QCPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483041bc"
    }
    "eQEP2_QCPRDLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483041c0"
    }
    "eQEP2_QCTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483041ba"
    }
    "eQEP2_QCTMRLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x483041be"
    }
    "eQEP2_QDECCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483041a8"
    }
    "eQEP2_QEINT" {
        access = "memorymapped"
        width = "32"
        address = "0x483041b0"
    }
    "eQEP2_QEPCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483041aa"
    }
    "eQEP2_QEPSTS" {
        access = "memorymapped"
        width = "32"
        address = "0x483041b8"
    }
    "eQEP2_QFLG" {
        access = "memorymapped"
        width = "32"
        address = "0x483041b2"
    }
    "eQEP2_QFRC" {
        access = "memorymapped"
        width = "32"
        address = "0x483041b6"
    }
    "eQEP2_QPOSCMP" {
        access = "memorymapped"
        width = "32"
        address = "0x4830418c"
    }
    "eQEP2_QPOSCNT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304180"
    }
    "eQEP2_QPOSCTL" {
        access = "memorymapped"
        width = "32"
        address = "0x483041ae"
    }
    "eQEP2_QPOSILAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304190"
    }
    "eQEP2_QPOSINIT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304184"
    }
    "eQEP2_QPOSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304198"
    }
    "eQEP2_QPOSMAX" {
        access = "memorymapped"
        width = "32"
        address = "0x48304188"
    }
    "eQEP2_QPOSSLAT" {
        access = "memorymapped"
        width = "32"
        address = "0x48304194"
    }
    "eQEP2_QUPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483041a0"
    }
    "eQEP2_QUTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x4830419c"
    }
    "eQEP2_QWDPRD" {
        access = "memorymapped"
        width = "32"
        address = "0x483041a6"
    }
    "eQEP2_QWDTMR" {
        access = "memorymapped"
        width = "32"
        address = "0x483041a4"
    }
    "eQEP2_REVID" {
        access = "memorymapped"
        width = "32"
        address = "0x483041dc"
    }
    "ecap_evt_capt" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fd4"
    }
    "gmii_sel" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10650"
    }
    "hw_event_sel_grp1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10690"
    }
    "hw_event_sel_grp2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10694"
    }
    "hw_event_sel_grp3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10698"
    }
    "hw_event_sel_grp4" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1069c"
    }
    "init_priority_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10608"
    }
    "init_priority_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1060c"
    }
    "ipc_msg_reg0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11328"
    }
    "ipc_msg_reg1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1132c"
    }
    "ipc_msg_reg2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11330"
    }
    "ipc_msg_reg3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11334"
    }
    "ipc_msg_reg4" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11338"
    }
    "ipc_msg_reg5" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1133c"
    }
    "ipc_msg_reg6" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11340"
    }
    "ipc_msg_reg7" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11344"
    }
    "m3_txev_eoi" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11324"
    }
    "mac_id0_hi" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10634"
    }
    "mac_id0_lo" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10630"
    }
    "mac_id1_hi" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1063c"
    }
    "mac_id1_lo" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10638"
    }
    "mmu_cfg" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10610"
    }
    "mosc_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10468"
    }
    "mpu_sldo_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1042c"
    }
    "mpuss_hw_dbg_info" {
        access = "memorymapped"
        width = "32"
        address = "0x44e106a8"
    }
    "mpuss_hw_debug_sel" {
        access = "memorymapped"
        width = "32"
        address = "0x44e106a4"
    }
    "mreqprio_0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10670"
    }
    "mreqprio_1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10674"
    }
    "pll_clkinpulow_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10458"
    }
    "pwmss_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10664"
    }
    "rcosc_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1046c"
    }
    "reset_iso" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11000"
    }
    "sma2" {
        access = "memorymapped"
        width = "32"
        address = "0x44e11320"
    }
    "smrt_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e106a0"
    }
    "timer_evt_capt" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fd0"
    }
    "tpcc_evt_mux_0_3" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10f90"
    }
    "tpcc_evt_mux_12_15" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10f9c"
    }
    "tpcc_evt_mux_16_19" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fa0"
    }
    "tpcc_evt_mux_20_23" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fa4"
    }
    "tpcc_evt_mux_24_27" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fa8"
    }
    "tpcc_evt_mux_28_31" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fac"
    }
    "tpcc_evt_mux_32_35" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fb0"
    }
    "tpcc_evt_mux_36_39" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fb4"
    }
    "tpcc_evt_mux_40_43" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fb8"
    }
    "tpcc_evt_mux_44_47" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fbc"
    }
    "tpcc_evt_mux_48_51" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fc0"
    }
    "tpcc_evt_mux_4_7" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10f94"
    }
    "tpcc_evt_mux_52_55" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fc4"
    }
    "tpcc_evt_mux_56_59" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fc8"
    }
    "tpcc_evt_mux_60_63" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10fcc"
    }
    "tpcc_evt_mux_8_11" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10f98"
    }
    "tptc_cfg" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10614"
    }
    "usb_ctrl0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10620"
    }
    "usb_ctrl1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10628"
    }
    "usb_sts0" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10624"
    }
    "usb_sts1" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1062c"
    }
    "usb_vid_pid" {
        access = "memorymapped"
        width = "32"
        address = "0x44e107f4"
    }
    "usb_wkup_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10648"
    }
    "vdd_core_opp_050" {
        access = "memorymapped"
        width = "32"
        address = "0x44e107b8"
    }
    "vdd_core_opp_100" {
        access = "memorymapped"
        width = "32"
        address = "0x44e107bc"
    }
    "vdd_mpu_opp_050" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10770"
    }
    "vdd_mpu_opp_100" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10774"
    }
    "vdd_mpu_opp_120" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10778"
    }
    "vdd_mpu_opp_turbo" {
        access = "memorymapped"
        width = "32"
        address = "0x44e1077c"
    }
    "vref_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10e14"
    }
    "vtp_ctrl" {
        access = "memorymapped"
        width = "32"
        address = "0x44e10e0c"
    }
}
"group" {
    "ADC_TSC" {
        collapse = true
        register = {"ADC_TSC_REVISION", "ADC_TSC_SYSCONFIG", "ADC_TSC_IRQSTATUS_RAW"}
        register += {"ADC_TSC_IRQSTATUS", "ADC_TSC_IRQENABLE_SET", "ADC_TSC_IRQENABLE_CLR"}
        register += {"ADC_TSC_IRQWAKEUP", "ADC_TSC_DMAENABLE_SET", "ADC_TSC_DMAENABLE_CLR"}
        register += {"ADC_TSC_CTRL", "ADC_TSC_ADCSTAT", "ADC_TSC_ADCRANGE", "ADC_TSC_ADC_CLKDIV"}
        register += {"ADC_TSC_ADC_MISC", "ADC_TSC_STEPENABLE", "ADC_TSC_IDLECONFIG"}
        register += {"ADC_TSC_TS_CHARGE_STEPCONFIG", "ADC_TSC_TS_CHARGE_DELAY", "ADC_TSC_STEPCONFIG1"}
        register += {"ADC_TSC_STEPDELAY1", "ADC_TSC_STEPCONFIG2", "ADC_TSC_STEPDELAY2"}
        register += {"ADC_TSC_STEPCONFIG3", "ADC_TSC_STEPDELAY3", "ADC_TSC_STEPCONFIG4"}
        register += {"ADC_TSC_STEPDELAY4", "ADC_TSC_STEPCONFIG5", "ADC_TSC_STEPDELAY5"}
        register += {"ADC_TSC_STEPCONFIG6", "ADC_TSC_STEPDELAY6", "ADC_TSC_STEPCONFIG7"}
        register += {"ADC_TSC_STEPDELAY7", "ADC_TSC_STEPCONFIG8", "ADC_TSC_STEPDELAY8"}
        register += {"ADC_TSC_STEPCONFIG9", "ADC_TSC_STEPDELAY9", "ADC_TSC_STEPCONFIG10"}
        register += {"ADC_TSC_STEPDELAY10", "ADC_TSC_STEPCONFIG11", "ADC_TSC_STEPDELAY11"}
        register += {"ADC_TSC_STEPCONFIG12", "ADC_TSC_STEPDELAY12", "ADC_TSC_STEPCONFIG13"}
        register += {"ADC_TSC_STEPDELAY13", "ADC_TSC_STEPCONFIG14", "ADC_TSC_STEPDELAY14"}
        register += {"ADC_TSC_STEPCONFIG15", "ADC_TSC_STEPDELAY15", "ADC_TSC_STEPCONFIG16"}
        register += {"ADC_TSC_STEPDELAY16", "ADC_TSC_FIFO0COUNT", "ADC_TSC_FIFO0THRESHOLD"}
        register += {"ADC_TSC_DMA0REQ", "ADC_TSC_FIFO1COUNT", "ADC_TSC_FIFO1THRESHOLD"}
        register += {"ADC_TSC_DMA1REQ", "ADC_TSC_FIFO0DATA", "ADC_TSC_FIFO1DATA"}
    }
    "CM_CEFUSE" {
        collapse = true
        register = {"CM_CEFUSE_CLKSTCTRL", "CM_CEFUSE_CEFUSE_CLKCTRL"}
    }
    "CM_DEVICE" {
        collapse = true
        register = {"CM_CLKOUT_CTRL"}
    }
    "CM_DPLL" {
        collapse = true
        register = {"CLKSEL_TIMER7_CLK", "CLKSEL_TIMER2_CLK", "CLKSEL_TIMER3_CLK"}
        register += {"CLKSEL_TIMER4_CLK", "CM_MAC_CLKSEL", "CLKSEL_TIMER5_CLK", "CLKSEL_TIMER6_CLK"}
        register += {"CM_CPTS_RFT_CLKSEL", "CLKSEL_TIMER1MS_CLK", "CLKSEL_GFX_FCLK"}
        register += {"CLKSEL_PRU_ICSS_OCP_CLK", "CLKSEL_LCDC_PIXEL_CLK", "CLKSEL_WDT1_CLK"}
        register += {"CLKSEL_GPIO0_DBCLK"}
    }
    "CM_GFX" {
        collapse = true
        register = {"CM_GFX_L3_CLKSTCTRL", "CM_GFX_GFX_CLKCTRL", "CM_GFX_L4LS_GFX_CLKSTCTRL"}
        register += {"CM_GFX_MMUCFG_CLKCTRL", "CM_GFX_MMUDATA_CLKCTRL"}
    }
    "CM_MPU" {
        collapse = true
        register = {"CM_MPU_CLKSTCTRL", "CM_MPU_MPU_CLKCTRL"}
    }
    "CM_PER" {
        collapse = true
        register = {"CM_PER_L4LS_CLKSTCTRL", "CM_PER_L3S_CLKSTCTRL", "CM_PER_L3_CLKSTCTRL"}
        register += {"CM_PER_CPGMAC0_CLKCTRL", "CM_PER_LCDC_CLKCTRL", "CM_PER_USB0_CLKCTRL"}
        register += {"CM_PER_TPTC0_CLKCTRL", "CM_PER_EMIF_CLKCTRL", "CM_PER_OCMCRAM_CLKCTRL"}
        register += {"CM_PER_GPMC_CLKCTRL", "CM_PER_MCASP0_CLKCTRL", "CM_PER_UART5_CLKCTRL"}
        register += {"CM_PER_MMC0_CLKCTRL", "CM_PER_ELM_CLKCTRL", "CM_PER_I2C2_CLKCTRL"}
        register += {"CM_PER_I2C1_CLKCTRL", "CM_PER_SPI0_CLKCTRL", "CM_PER_SPI1_CLKCTRL"}
        register += {"CM_PER_L4LS_CLKCTRL", "CM_PER_L4FW_CLKCTRL", "CM_PER_MCASP1_CLKCTRL"}
        register += {"CM_PER_UART1_CLKCTRL", "CM_PER_UART2_CLKCTRL", "CM_PER_UART3_CLKCTRL"}
        register += {"CM_PER_UART4_CLKCTRL", "CM_PER_TIMER7_CLKCTRL", "CM_PER_TIMER2_CLKCTRL"}
        register += {"CM_PER_TIMER3_CLKCTRL", "CM_PER_TIMER4_CLKCTRL", "CM_PER_GPIO1_CLKCTRL"}
        register += {"CM_PER_GPIO2_CLKCTRL", "CM_PER_GPIO3_CLKCTRL", "CM_PER_TPCC_CLKCTRL"}
        register += {"CM_PER_DCAN0_CLKCTRL", "CM_PER_DCAN1_CLKCTRL", "CM_PER_EPWMSS1_CLKCTRL"}
        register += {"CM_PER_EPWMSS0_CLKCTRL", "CM_PER_EPWMSS2_CLKCTRL", "CM_PER_L3_INSTR_CLKCTRL"}
        register += {"CM_PER_L3_CLKCTRL", "CM_PER_IEEE5000_CLKCTRL", "CM_PER_PRU_ICSS_CLKCTRL"}
        register += {"CM_PER_TIMER5_CLKCTRL", "CM_PER_TIMER6_CLKCTRL", "CM_PER_MMC1_CLKCTRL"}
        register += {"CM_PER_MMC2_CLKCTRL", "CM_PER_TPTC1_CLKCTRL", "CM_PER_TPTC2_CLKCTRL"}
        register += {"CM_PER_SPINLOCK_CLKCTRL", "CM_PER_MAILBOX0_CLKCTRL", "CM_PER_L4HS_CLKSTCTRL"}
        register += {"CM_PER_L4HS_CLKCTRL", "CM_PER_OCPWP_L3_CLKSTCTRL", "CM_PER_OCPWP_CLKCTRL"}
        register += {"CM_PER_PRU_ICSS_CLKSTCTRL", "CM_PER_CPSW_CLKSTCTRL", "CM_PER_LCDC_CLKSTCTRL"}
        register += {"CM_PER_CLKDIV32K_CLKCTRL", "CM_PER_CLK_24MHZ_CLKSTCTRL"}
    }
    "CM_RTC" {
        collapse = true
        register = {"CM_RTC_RTC_CLKCTRL", "CM_RTC_CLKSTCTRL"}
    }
    "CM_WKUP" {
        collapse = true
        register = {"CM_WKUP_CLKSTCTRL", "CM_WKUP_CONTROL_CLKCTRL", "CM_WKUP_GPIO0_CLKCTRL"}
        register += {"CM_WKUP_L4WKUP_CLKCTRL", "CM_WKUP_TIMER0_CLKCTRL", "CM_WKUP_DEBUGSS_CLKCTRL"}
        register += {"CM_L3_AON_CLKSTCTRL", "CM_AUTOIDLE_DPLL_MPU", "CM_IDLEST_DPLL_MPU"}
        register += {"CM_SSC_DELTAMSTEP_DPLL_MPU", "CM_SSC_MODFREQDIV_DPLL_MPU", "CM_CLKSEL_DPLL_MPU"}
        register += {"CM_AUTOIDLE_DPLL_DDR", "CM_IDLEST_DPLL_DDR", "CM_SSC_DELTAMSTEP_DPLL_DDR"}
        register += {"CM_SSC_MODFREQDIV_DPLL_DDR", "CM_CLKSEL_DPLL_DDR", "CM_AUTOIDLE_DPLL_DISP"}
        register += {"CM_IDLEST_DPLL_DISP", "CM_SSC_DELTAMSTEP_DPLL_DISP", "CM_SSC_MODFREQDIV_DPLL_DISP"}
        register += {"CM_CLKSEL_DPLL_DISP", "CM_AUTOIDLE_DPLL_CORE", "CM_IDLEST_DPLL_CORE"}
        register += {"CM_SSC_DELTAMSTEP_DPLL_CORE", "CM_SSC_MODFREQDIV_DPLL_CORE"}
        register += {"CM_CLKSEL_DPLL_CORE", "CM_AUTOIDLE_DPLL_PER", "CM_IDLEST_DPLL_PER"}
        register += {"CM_SSC_DELTAMSTEP_DPLL_PER", "CM_SSC_MODFREQDIV_DPLL_PER", "CM_CLKDCOLDO_DPLL_PER"}
        register += {"CM_DIV_M4_DPLL_CORE", "CM_DIV_M5_DPLL_CORE", "CM_CLKMODE_DPLL_MPU"}
        register += {"CM_CLKMODE_DPLL_PER", "CM_CLKMODE_DPLL_CORE", "CM_CLKMODE_DPLL_DDR"}
        register += {"CM_CLKMODE_DPLL_DISP", "CM_CLKSEL_DPLL_PERIPH", "CM_DIV_M2_DPLL_DDR"}
        register += {"CM_DIV_M2_DPLL_DISP", "CM_DIV_M2_DPLL_MPU", "CM_DIV_M2_DPLL_PER"}
        register += {"CM_WKUP_WKUP_M3_CLKCTRL", "CM_WKUP_UART0_CLKCTRL", "CM_WKUP_I2C0_CLKCTRL"}
        register += {"CM_WKUP_ADC_TSC_CLKCTRL", "CM_WKUP_SMARTREFLEX0_CLKCTRL", "CM_WKUP_TIMER1_CLKCTRL"}
        register += {"CM_WKUP_SMARTREFLEX1_CLKCTRL", "CM_L4_WKUP_AON_CLKSTCTRL", "CM_WKUP_WDT1_CLKCTRL"}
        register += {"CM_DIV_M6_DPLL_CORE"}
    }
    "CPSW_ALE" {
        collapse = true
        register = {"CPSW_ALE_IDVER", "CPSW_ALE_CONTROL", "CPSW_ALE_PRESCALE", "CPSW_ALE_UNKNOWN_VLAN"}
        register += {"CPSW_ALE_TBLCTL", "CPSW_ALE_TBLW2", "CPSW_ALE_TBLW1", "CPSW_ALE_TBLW0"}
        register += {"CPSW_ALE_PORTCTL0", "CPSW_ALE_PORTCTL1", "CPSW_ALE_PORTCTL2"}
        register += {"CPSW_ALE_PORTCTL3", "CPSW_ALE_PORTCTL4", "CPSW_ALE_PORTCTL5"}
    }
    "CPSW_CPDMA" {
        collapse = true
        register = {"CPSW_CPDMA_TX_IDVER", "CPSW_CPDMA_TX_CONTROL", "CPSW_CPDMA_TX_TEARDOWN"}
        register += {"CPSW_CPDMA_RX_IDVER", "CPSW_CPDMA_RX_CONTROL", "CPSW_CPDMA_RX_TEARDOWN"}
        register += {"CPSW_CPDMA_CPDMA_SOFT_RESET", "CPSW_CPDMA_DMACONTROL", "CPSW_CPDMA_DMASTATUS"}
        register += {"CPSW_CPDMA_RX_BUFFER_OFFSET", "CPSW_CPDMA_EMCONTROL", "CPSW_CPDMA_TX_PRI0_RATE"}
        register += {"CPSW_CPDMA_TX_PRI1_RATE", "CPSW_CPDMA_TX_PRI2_RATE", "CPSW_CPDMA_TX_PRI3_RATE"}
        register += {"CPSW_CPDMA_TX_PRI4_RATE", "CPSW_CPDMA_TX_PRI5_RATE", "CPSW_CPDMA_TX_PRI6_RATE"}
        register += {"CPSW_CPDMA_TX_PRI7_RATE", "CPSW_CPDMA_TX_INTSTAT_RAW", "CPSW_CPDMA_TX_INTSTAT_MASKED"}
        register += {"CPSW_CPDMA_TX_INTMASK_SET", "CPSW_CPDMA_TX_INTMASK_CLEAR", "CPSW_CPDMA_CPDMA_IN_VECTOR"}
        register += {"CPSW_CPDMA_CPDMA_EOI_VECTOR", "CPSW_CPDMA_RX_INTSTAT_RAW", "CPSW_CPDMA_RX_INTSTAT_MASKED"}
        register += {"CPSW_CPDMA_RX_INTMASK_SET", "CPSW_CPDMA_RX_INTMASK_CLEAR", "CPSW_CPDMA_DMA_INTSTAT_RAW"}
        register += {"CPSW_CPDMA_DMA_INTSTAT_MASKED", "CPSW_CPDMA_DMA_INTMASK_SET"}
        register += {"CPSW_CPDMA_DMA_INTMASK_CLEAR", "CPSW_CPDMA_RX0_PENDTHRESH"}
        register += {"CPSW_CPDMA_RX1_PENDTHRESH", "CPSW_CPDMA_RX2_PENDTHRESH", "CPSW_CPDMA_RX3_PENDTHRESH"}
        register += {"CPSW_CPDMA_RX4_PENDTHRESH", "CPSW_CPDMA_RX5_PENDTHRESH", "CPSW_CPDMA_RX6_PENDTHRESH"}
        register += {"CPSW_CPDMA_RX7_PENDTHRESH", "CPSW_CPDMA_RX0_FREEBUFFER", "CPSW_CPDMA_RX1_FREEBUFFER"}
        register += {"CPSW_CPDMA_RX2_FREEBUFFER", "CPSW_CPDMA_RX3_FREEBUFFER", "CPSW_CPDMA_RX4_FREEBUFFER"}
        register += {"CPSW_CPDMA_RX5_FREEBUFFER", "CPSW_CPDMA_RX6_FREEBUFFER", "CPSW_CPDMA_RX7_FREEBUFFER"}
    }
    "CPSW_CPTS" {
        collapse = true
        register = {"CPTS_IDVER", "CPTS_CONTROL", "CPTS_TS_PUSH", "CPTS_TS_LOAD_VAL"}
        register += {"CPTS_TS_LOAD_EN", "CPTS_INTSTAT_RAW", "CPTS_INTSTAT_MASKED"}
        register += {"CPTS_INT_ENABLE", "CPTS_EVENT_POP", "CPTS_EVENT_LOW", "CPTS_EVENT_HIGH"}
    }
    "CPSW_PORT" {
        collapse = true
        register = {"CPSW_PORT_P0_CONTROL", "CPSW_PORT_P0_MAX_BLKS", "CPSW_PORT_P0_BLK_CNT"}
        register += {"CPSW_PORT_P0_TX_IN_CTL", "CPSW_PORT_P0_PORT_VLAN", "CPSW_PORT_P0_TX_PRI_MAP"}
        register += {"CPSW_PORT_P0_CPDMA_TX_PRI_MAP", "CPSW_PORT_P0_CPDMA_RX_CH_MAP"}
        register += {"CPSW_PORT_P0_RX_DSCP_PRI_MAP0", "CPSW_PORT_P0_RX_DSCP_PRI_MAP1"}
        register += {"CPSW_PORT_P0_RX_DSCP_PRI_MAP2", "CPSW_PORT_P0_RX_DSCP_PRI_MAP3"}
        register += {"CPSW_PORT_P0_RX_DSCP_PRI_MAP4", "CPSW_PORT_P0_RX_DSCP_PRI_MAP5"}
        register += {"CPSW_PORT_P0_RX_DSCP_PRI_MAP6", "CPSW_PORT_P0_RX_DSCP_PRI_MAP7"}
        register += {"CPSW_PORT_P1_CONTROL", "CPSW_PORT_P1_MAX_BLKS", "CPSW_PORT_P1_BLK_CNT"}
        register += {"CPSW_PORT_P1_TX_IN_CTL", "CPSW_PORT_P1_PORT_VLAN", "CPSW_PORT_P1_TX_PRI_MAP"}
        register += {"CPSW_PORT_P1_TS_SEQ_MTYPE", "CPSW_PORT_P1_SA_LO", "CPSW_PORT_P1_SA_HI"}
        register += {"CPSW_PORT_P1_SEND_PERCENT", "CPSW_PORT_P1_RX_DSCP_PRI_MAP0"}
        register += {"CPSW_PORT_P1_RX_DSCP_PRI_MAP1", "CPSW_PORT_P1_RX_DSCP_PRI_MAP2"}
        register += {"CPSW_PORT_P1_RX_DSCP_PRI_MAP3", "CPSW_PORT_P1_RX_DSCP_PRI_MAP4"}
        register += {"CPSW_PORT_P1_RX_DSCP_PRI_MAP5", "CPSW_PORT_P1_RX_DSCP_PRI_MAP6"}
        register += {"CPSW_PORT_P1_RX_DSCP_PRI_MAP7", "CPSW_PORT_P2_CONTROL", "CPSW_PORT_P2_MAX_BLKS"}
        register += {"CPSW_PORT_P2_BLK_CNT", "CPSW_PORT_P2_TX_IN_CTL", "CPSW_PORT_P2_PORT_VLAN"}
        register += {"CPSW_PORT_P2_TX_PRI_MAP", "CPSW_PORT_P2_TS_SEQ_MTYPE", "CPSW_PORT_P2_SA_LO"}
        register += {"CPSW_PORT_P2_SA_HI", "CPSW_PORT_P2_SEND_PERCENT", "CPSW_PORT_P2_RX_DSCP_PRI_MAP0"}
        register += {"CPSW_PORT_P2_RX_DSCP_PRI_MAP1", "CPSW_PORT_P2_RX_DSCP_PRI_MAP2"}
        register += {"CPSW_PORT_P2_RX_DSCP_PRI_MAP3", "CPSW_PORT_P2_RX_DSCP_PRI_MAP4"}
        register += {"CPSW_PORT_P2_RX_DSCP_PRI_MAP5", "CPSW_PORT_P2_RX_DSCP_PRI_MAP6"}
        register += {"CPSW_PORT_P2_RX_DSCP_PRI_MAP7"}
    }
    "CPSW_SL1" {
        collapse = true
        register = {"CPSW_SL1_IDVER", "CPSW_SL1_MACCONTROL", "CPSW_SL1_MACSTATUS"}
        register += {"CPSW_SL1_SOFT_RESET", "CPSW_SL1_RX_MAXLEN", "CPSW_SL1_BOFFTEST"}
        register += {"CPSW_SL1_RX_PAUSE", "CPSW_SL1_TX_PAUSE", "CPSW_SL1_EMCONTROL"}
        register += {"CPSW_SL1_RX_PRI_MAP", "CPSW_SL1_TX_GAP"}
    }
    "CPSW_SL2" {
        collapse = true
        register = {"CPSW_SL2_IDVER", "CPSW_SL2_MACCONTROL", "CPSW_SL2_MACSTATUS"}
        register += {"CPSW_SL2_SOFT_RESET", "CPSW_SL2_RX_MAXLEN", "CPSW_SL2_BOFFTEST"}
        register += {"CPSW_SL2_RX_PAUSE", "CPSW_SL2_TX_PAUSE", "CPSW_SL2_EMCONTROL"}
        register += {"CPSW_SL2_RX_PRI_MAP", "CPSW_SL2_TX_GAP"}
    }
    "CPSW_SS" {
        collapse = true
        register = {"CPSW_SS_ID_VER", "CPSW_SS_CONTROL", "CPSW_SS_SOFT_RESET", "CPSW_SS_STAT_PORT_EN"}
        register += {"CPSW_SS_PTYPE", "CPSW_SS_SOFT_IDLE", "CPSW_SS_THRU_RATE", "CPSW_SS_GAP_THRESH"}
        register += {"CPSW_SS_TX_START_WDS", "CPSW_SS_FLOW_CONTROL", "CPSW_SS_VLAN_LTYPE"}
        register += {"CPSW_SS_TS_LTYPE", "CPSW_SS_DLR_LTYPE"}
    }
    "CPSW_STATERAM" {
        collapse = true
        register = {"TX0_HDP", "TX1_HDP", "TX2_HDP", "TX3_HDP", "TX4_HDP", "TX5_HDP"}
        register += {"TX6_HDP", "TX7_HDP", "RX0_HDP", "RX1_HDP", "RX2_HDP", "RX3_HDP"}
        register += {"RX4_HDP", "RX5_HDP", "RX6_HDP", "RX7_HDP", "TX0_CP", "TX1_CP"}
        register += {"TX2_CP", "TX3_CP", "TX4_CP", "TX5_CP", "TX6_CP", "TX7_CP", "RX0_CP"}
        register += {"RX1_CP", "RX2_CP", "RX3_CP", "RX4_CP", "RX5_CP", "RX6_CP", "RX7_CP"}
        register += {"CPSW_STATERAM_TX0_HDP", "CPSW_STATERAM_TX1_HDP", "CPSW_STATERAM_TX2_HDP"}
        register += {"CPSW_STATERAM_TX3_HDP", "CPSW_STATERAM_TX4_HDP", "CPSW_STATERAM_TX5_HDP"}
        register += {"CPSW_STATERAM_TX6_HDP", "CPSW_STATERAM_TX7_HDP", "CPSW_STATERAM_RX0_HDP"}
        register += {"CPSW_STATERAM_RX1_HDP", "CPSW_STATERAM_RX2_HDP", "CPSW_STATERAM_RX3_HDP"}
        register += {"CPSW_STATERAM_RX4_HDP", "CPSW_STATERAM_RX5_HDP", "CPSW_STATERAM_RX6_HDP"}
        register += {"CPSW_STATERAM_RX7_HDP", "CPSW_STATERAM_TX0_CP", "CPSW_STATERAM_TX1_CP"}
        register += {"CPSW_STATERAM_TX2_CP", "CPSW_STATERAM_TX3_CP", "CPSW_STATERAM_TX4_CP"}
        register += {"CPSW_STATERAM_TX5_CP", "CPSW_STATERAM_TX6_CP", "CPSW_STATERAM_TX7_CP"}
        register += {"CPSW_STATERAM_RX0_CP", "CPSW_STATERAM_RX1_CP", "CPSW_STATERAM_RX2_CP"}
        register += {"CPSW_STATERAM_RX3_CP", "CPSW_STATERAM_RX4_CP", "CPSW_STATERAM_RX5_CP"}
        register += {"CPSW_STATERAM_RX6_CP", "CPSW_STATERAM_RX7_CP"}
    }
    "CPSW_STATUS" {
        collapse = true
        register = {"Good_Rx_Frames", "Broadcast_Rx_Frames", "Multicast_Rx_Frames"}
        register += {"Pause_Rx_Frames", "Rx_CRC_Errors", "Rx_Align_Code_Errors", "Oversize_Rx_Frames"}
        register += {"Rx_Jabbers", "Undersize_Rx_Frames", "Rx_Fragments", "Rx_Octets"}
        register += {"Good_Tx_Frames", "Broadcast_Tx_Frames", "Multicast_Tx_Frames"}
        register += {"Pause_Tx_Frames", "Deferred_Tx_Frames", "Collisions", "Single_Collision_Tx_Frames"}
        register += {"Multiple_Collision_Tx_Frames", "Excessive_Collisions", "Late_Collisions"}
        register += {"Tx_Underrun", "Carrier_Sense_Errors", "Tx_Octets", "Rx_Tx_64_Octet_Frames"}
        register += {"Rx_Tx_65_127_Octet_Frames", "Rx_Tx_128_255_Octet_Frames", "Rx_Tx_256_511_Octet_Frames"}
        register += {"Rx_Tx_512_1023_Octet_Frames", "Rx_Tx_1024_Up_Octet_Frames"}
        register += {"Net_Octets", "Rx_Start_of_Frame_Overruns", "Rx_Middle_of_Frame_Overruns"}
        register += {"Rx_DMA_Overruns"}
    }
    "CPSW_WR" {
        collapse = true
        register = {"CPSW_WR_IDVER", "CPSW_WR_SOFT_RESET", "CPSW_WR_CONTROL", "CPSW_WR_INT_CONTROL"}
        register += {"CPSW_WR_C0_RX_THRESH_EN", "CPSW_WR_C0_RX_EN", "CPSW_WR_C0_TX_EN"}
        register += {"CPSW_WR_C0_MISC_EN", "CPSW_WR_C1_RX_THRESH_EN", "CPSW_WR_C1_RX_EN"}
        register += {"CPSW_WR_C1_TX_EN", "CPSW_WR_C1_MISC_EN", "CPSW_WR_C2_RX_THRESH_EN"}
        register += {"CPSW_WR_C2_RX_EN", "CPSW_WR_C2_TX_EN", "CPSW_WR_C2_MISC_EN"}
        register += {"CPSW_WR_C0_RX_THRESH_STAT", "CPSW_WR_C0_RX_STAT", "CPSW_WR_C0_TX_STAT"}
        register += {"CPSW_WR_C0_MISC_STAT", "CPSW_WR_C1_RX_THRESH_STAT", "CPSW_WR_C1_RX_STAT"}
        register += {"CPSW_WR_C1_TX_STAT", "CPSW_WR_C1_MISC_STAT", "CPSW_WR_C2_RX_THRESH_STAT"}
        register += {"CPSW_WR_C2_RX_STAT", "CPSW_WR_C2_TX_STAT", "CPSW_WR_C2_MISC_STAT"}
        register += {"CPSW_WR_C0_RX_IMAX", "CPSW_WR_C0_TX_IMAX", "CPSW_WR_C1_RX_IMAX"}
        register += {"CPSW_WR_C1_TX_IMAX", "CPSW_WR_C2_RX_IMAX", "CPSW_WR_C2_TX_IMAX"}
        register += {"CPSW_WR_RGMII_CTL"}
    }
    "Control Module" {
        collapse = true
        register = {"control_revision", "device_id", "control_hwinfo", "control_sysconfig"}
        register += {"control_status", "cortex_vbbldo_ctrl", "core_sldo_ctrl", "mpu_sldo_ctrl"}
        register += {"clk32kdivratio_ctrl", "bandgap_ctrl", "bandgap_trim", "pll_clkinpulow_ctrl"}
        register += {"mosc_ctrl", "rcosc_ctrl", "deepsleep_ctrl", "dev_feature", "init_priority_0"}
        register += {"init_priority_1", "mmu_cfg", "tptc_cfg", "usb_ctrl0", "usb_sts0"}
        register += {"usb_ctrl1", "usb_sts1", "mac_id0_lo", "mac_id0_hi", "mac_id1_lo"}
        register += {"mac_id1_hi", "dcan_raminit", "usb_wkup_ctrl", "gmii_sel", "pwmss_ctrl"}
        register += {"mreqprio_0", "mreqprio_1", "hw_event_sel_grp1", "hw_event_sel_grp2"}
        register += {"hw_event_sel_grp3", "hw_event_sel_grp4", "smrt_ctrl", "mpuss_hw_debug_sel"}
        register += {"mpuss_hw_dbg_info", "vdd_mpu_opp_050", "vdd_mpu_opp_100", "vdd_mpu_opp_120"}
        register += {"vdd_mpu_opp_turbo", "vdd_core_opp_050", "vdd_core_opp_100"}
        register += {"bb_scale", "usb_vid_pid", "cqdetect_status", "ddr_io_ctrl"}
        register += {"vtp_ctrl", "vref_ctrl", "tpcc_evt_mux_0_3", "tpcc_evt_mux_4_7"}
        register += {"tpcc_evt_mux_8_11", "tpcc_evt_mux_12_15", "tpcc_evt_mux_16_19"}
        register += {"tpcc_evt_mux_20_23", "tpcc_evt_mux_24_27", "tpcc_evt_mux_28_31"}
        register += {"tpcc_evt_mux_32_35", "tpcc_evt_mux_36_39", "tpcc_evt_mux_40_43"}
        register += {"tpcc_evt_mux_44_47", "tpcc_evt_mux_48_51", "tpcc_evt_mux_52_55"}
        register += {"tpcc_evt_mux_56_59", "tpcc_evt_mux_60_63", "timer_evt_capt"}
        register += {"ecap_evt_capt", "adc_evt_capt", "reset_iso", "ddr_cke_ctrl"}
        register += {"sma2", "m3_txev_eoi", "ipc_msg_reg0", "ipc_msg_reg1", "ipc_msg_reg2"}
        register += {"ipc_msg_reg3", "ipc_msg_reg4", "ipc_msg_reg5", "ipc_msg_reg6"}
        register += {"ipc_msg_reg7", "ddr_cmd0_ioctrl", "ddr_cmd1_ioctrl", "ddr_cmd2_ioctrl"}
        register += {"ddr_data0_ioctrl", "ddr_data1_ioctrl"}
    }
    "DCAN0" {
        collapse = true
        register = {"DCAN0_CTL", "DCAN0_ES", "DCAN0_PARITYERR_EOI", "DCAN0_ERRC"}
        register += {"DCAN0_BTR", "DCAN0_INT", "DCAN0_TEST", "DCAN0_PERR", "DCAN0_ABOTR"}
        register += {"DCAN0_TXRQ_X", "DCAN0_TXRQ12", "DCAN0_TXRQ34", "DCAN0_TXRQ56"}
        register += {"DCAN0_TXRQ78", "DCAN0_NWDAT_X", "DCAN0_NWDAT12", "DCAN0_NWDAT34"}
        register += {"DCAN0_NWDAT56", "DCAN0_NWDAT78", "DCAN0_INTPND_X", "DCAN0_INTPND12"}
        register += {"DCAN0_INTPND34", "DCAN0_INTPND56", "DCAN0_INTPND78", "DCAN0_MSGVAL_X"}
        register += {"DCAN0_MSGVAL12", "DCAN0_MSGVAL34", "DCAN0_MSGVAL56", "DCAN0_MSGVAL78"}
        register += {"DCAN0_INTMUX12", "DCAN0_INTMUX34", "DCAN0_INTMUX56", "DCAN0_INTMUX78"}
        register += {"DCAN0_IF1CMD", "DCAN0_IF2CMD", "DCAN0_IF1MSK", "DCAN0_IF2MSK"}
        register += {"DCAN0_IF1ARB", "DCAN0_IF2ARB", "DCAN0_IF1MCTL", "DCAN0_IF2MCTL"}
        register += {"DCAN0_IF1DATA", "DCAN0_IF1DATB", "DCAN0_IF2DATA", "DCAN0_IF2DATB"}
        register += {"DCAN0_IF3OBS", "DCAN0_IF3MSK", "DCAN0_IF3ARB", "DCAN0_IF3MCTL"}
        register += {"DCAN0_IF3DATA", "DCAN0_IF3DATB", "DCAN0_IF3UPD12", "DCAN0_IF3UPD34"}
        register += {"DCAN0_IF3UPD56", "DCAN0_IF3UPD78", "DCAN0_TIOC", "DCAN0_RIOC"}
    }
    "DCAN1" {
        collapse = true
        register = {"DCAN1_CTL", "DCAN1_ES", "DCAN1_PARITYERR_EOI", "DCAN1_ERRC"}
        register += {"DCAN1_BTR", "DCAN1_INT", "DCAN1_TEST", "DCAN1_PERR", "DCAN1_ABOTR"}
        register += {"DCAN1_TXRQ_X", "DCAN1_TXRQ12", "DCAN1_TXRQ34", "DCAN1_TXRQ56"}
        register += {"DCAN1_TXRQ78", "DCAN1_NWDAT_X", "DCAN1_NWDAT12", "DCAN1_NWDAT34"}
        register += {"DCAN1_NWDAT56", "DCAN1_NWDAT78", "DCAN1_INTPND_X", "DCAN1_INTPND12"}
        register += {"DCAN1_INTPND34", "DCAN1_INTPND56", "DCAN1_INTPND78", "DCAN1_MSGVAL_X"}
        register += {"DCAN1_MSGVAL12", "DCAN1_MSGVAL34", "DCAN1_MSGVAL56", "DCAN1_MSGVAL78"}
        register += {"DCAN1_INTMUX12", "DCAN1_INTMUX34", "DCAN1_INTMUX56", "DCAN1_INTMUX78"}
        register += {"DCAN1_IF1CMD", "DCAN1_IF2CMD", "DCAN1_IF1MSK", "DCAN1_IF2MSK"}
        register += {"DCAN1_IF1ARB", "DCAN1_IF2ARB", "DCAN1_IF1MCTL", "DCAN1_IF2MCTL"}
        register += {"DCAN1_IF1DATA", "DCAN1_IF1DATB", "DCAN1_IF2DATA", "DCAN1_IF2DATB"}
        register += {"DCAN1_IF3OBS", "DCAN1_IF3MSK", "DCAN1_IF3ARB", "DCAN1_IF3MCTL"}
        register += {"DCAN1_IF3DATA", "DCAN1_IF3DATB", "DCAN1_IF3UPD12", "DCAN1_IF3UPD34"}
        register += {"DCAN1_IF3UPD56", "DCAN1_IF3UPD78", "DCAN1_TIOC", "DCAN1_RIOC"}
    }
    "DDR PHY" {
        collapse = true
        register = {"CMD0_REG_PHY_CTRL_SLAVE_RATIO_0", "CMD0_REG_PHY_DLL_LOCK_DIFF_0"}
        register += {"CMD0_REG_PHY_INVERT_CLKOUT_0", "CMD1_REG_PHY_CTRL_SLAVE_RATIO_0"}
        register += {"CMD1_REG_PHY_DLL_LOCK_DIFF_0", "CMD1_REG_PHY_INVERT_CLKOUT_0"}
        register += {"CMD2_REG_PHY_CTRL_SLAVE_RATIO_0", "CMD2_REG_PHY_DLL_LOCK_DIFF_0"}
        register += {"CMD2_REG_PHY_INVERT_CLKOUT_0", "DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0"}
        register += {"DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0", "DATA0_REG_PHY_WRLVL_INIT_RATIO_0"}
        register += {"DATA0_REG_PHY_WRLVL_INIT_MODE_0", "DATA0_REG_PHY_GATELVL_INIT_RATIO_0"}
        register += {"DATA0_REG_PHY_GATELVL_INIT_MODE_0", "DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0"}
        register += {"DATA0_REG_PHY_DQ_OFFSET_0", "DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0"}
        register += {"DATA0_REG_PHY_USE_RANK0_DELAYS", "DATA0_REG_PHY_DLL_LOCK_DIFF_0"}
        register += {"DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0", "DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0"}
        register += {"DATA1_REG_PHY_WRLVL_INIT_RATIO_0", "DATA1_REG_PHY_WRLVL_INIT_MODE_0"}
        register += {"DATA1_REG_PHY_GATELVL_INIT_RATIO_0", "DATA1_REG_PHY_GATELVL_INIT_MODE_0"}
        register += {"DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0", "DATA1_REG_PHY_DQ_OFFSET_1"}
        register += {"DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0", "DATA1_REG_PHY_USE_RANK0_DELAYS"}
        register += {"DATA1_REG_PHY_DLL_LOCK_DIFF_0"}
    }
    "DMTIMER0" {
        collapse = true
        register = {"DMTIMER0_TIDR", "DMTIMER0_TIOCP_CFG", "DMTIMER0_IRQSTATUS_RAW"}
        register += {"DMTIMER0_IRQSTATUS", "DMTIMER0_IRQENABLE_SET", "DMTIMER0_IRQENABLE_CLR"}
        register += {"DMTIMER0_IRQWAKEEN", "DMTIMER0_TCLR", "DMTIMER0_TCRR", "DMTIMER0_TLDR"}
        register += {"DMTIMER0_TTGR", "DMTIMER0_TWPS", "DMTIMER0_TMAR", "DMTIMER0_TCAR1"}
        register += {"DMTIMER0_TSICR", "DMTIMER0_TCAR2"}
    }
    "DMTIMER1_1MS" {
        collapse = true
        register = {"DMTIMER1_1MS_TIDR", "DMTIMER1_1MS_TIOCP_CFG", "DMTIMER1_1MS_TISTAT"}
        register += {"DMTIMER1_1MS_TISR", "DMTIMER1_1MS_TIER", "DMTIMER1_1MS_TWER"}
        register += {"DMTIMER1_1MS_TCLR", "DMTIMER1_1MS_TCRR", "DMTIMER1_1MS_TLDR"}
        register += {"DMTIMER1_1MS_TTGR", "DMTIMER1_1MS_TWPS", "DMTIMER1_1MS_TMAR"}
        register += {"DMTIMER1_1MS_TCAR1", "DMTIMER1_1MS_TSICR", "DMTIMER1_1MS_TCAR2"}
        register += {"DMTIMER1_1MS_TPIR", "DMTIMER1_1MS_TNIR", "DMTIMER1_1MS_TCVR"}
        register += {"DMTIMER1_1MS_TOCR", "DMTIMER1_1MS_TOWR"}
    }
    "DMTIMER2" {
        collapse = true
        register = {"DMTIMER2_TIDR", "DMTIMER2_TIOCP_CFG", "DMTIMER2_IRQSTATUS_RAW"}
        register += {"DMTIMER2_IRQSTATUS", "DMTIMER2_IRQENABLE_SET", "DMTIMER2_IRQENABLE_CLR"}
        register += {"DMTIMER2_IRQWAKEEN", "DMTIMER2_TCLR", "DMTIMER2_TCRR", "DMTIMER2_TLDR"}
        register += {"DMTIMER2_TTGR", "DMTIMER2_TWPS", "DMTIMER2_TMAR", "DMTIMER2_TCAR1"}
        register += {"DMTIMER2_TSICR", "DMTIMER2_TCAR2"}
    }
    "DMTIMER3" {
        collapse = true
        register = {"DMTIMER3_TIDR", "DMTIMER3_TIOCP_CFG", "DMTIMER3_IRQSTATUS_RAW"}
        register += {"DMTIMER3_IRQSTATUS", "DMTIMER3_IRQENABLE_SET", "DMTIMER3_IRQENABLE_CLR"}
        register += {"DMTIMER3_IRQWAKEEN", "DMTIMER3_TCLR", "DMTIMER3_TCRR", "DMTIMER3_TLDR"}
        register += {"DMTIMER3_TTGR", "DMTIMER3_TWPS", "DMTIMER3_TMAR", "DMTIMER3_TCAR1"}
        register += {"DMTIMER3_TSICR", "DMTIMER3_TCAR2"}
    }
    "DMTIMER4" {
        collapse = true
        register = {"DMTIMER4_TIDR", "DMTIMER4_TIOCP_CFG", "DMTIMER4_IRQSTATUS_RAW"}
        register += {"DMTIMER4_IRQSTATUS", "DMTIMER4_IRQENABLE_SET", "DMTIMER4_IRQENABLE_CLR"}
        register += {"DMTIMER4_IRQWAKEEN", "DMTIMER4_TCLR", "DMTIMER4_TCRR", "DMTIMER4_TLDR"}
        register += {"DMTIMER4_TTGR", "DMTIMER4_TWPS", "DMTIMER4_TMAR", "DMTIMER4_TCAR1"}
        register += {"DMTIMER4_TSICR", "DMTIMER4_TCAR2"}
    }
    "DMTIMER5" {
        collapse = true
        register = {"DMTIMER5_TIDR", "DMTIMER5_TIOCP_CFG", "DMTIMER5_IRQSTATUS_RAW"}
        register += {"DMTIMER5_IRQSTATUS", "DMTIMER5_IRQENABLE_SET", "DMTIMER5_IRQENABLE_CLR"}
        register += {"DMTIMER5_IRQWAKEEN", "DMTIMER5_TCLR", "DMTIMER5_TCRR", "DMTIMER5_TLDR"}
        register += {"DMTIMER5_TTGR", "DMTIMER5_TWPS", "DMTIMER5_TMAR", "DMTIMER5_TCAR1"}
        register += {"DMTIMER5_TSICR", "DMTIMER5_TCAR2"}
    }
    "DMTIMER6" {
        collapse = true
        register = {"DMTIMER6_TIDR", "DMTIMER6_TIOCP_CFG", "DMTIMER6_IRQSTATUS_RAW"}
        register += {"DMTIMER6_IRQSTATUS", "DMTIMER6_IRQENABLE_SET", "DMTIMER6_IRQENABLE_CLR"}
        register += {"DMTIMER6_IRQWAKEEN", "DMTIMER6_TCLR", "DMTIMER6_TCRR", "DMTIMER6_TLDR"}
        register += {"DMTIMER6_TTGR", "DMTIMER6_TWPS", "DMTIMER6_TMAR", "DMTIMER6_TCAR1"}
        register += {"DMTIMER6_TSICR", "DMTIMER6_TCAR2"}
    }
    "DMTIMER7" {
        collapse = true
        register = {"DMTIMER7_TIDR", "DMTIMER7_TIOCP_CFG", "DMTIMER7_IRQSTATUS_RAW"}
        register += {"DMTIMER7_IRQSTATUS", "DMTIMER7_IRQENABLE_SET", "DMTIMER7_IRQENABLE_CLR"}
        register += {"DMTIMER7_IRQWAKEEN", "DMTIMER7_TCLR", "DMTIMER7_TCRR", "DMTIMER7_TLDR"}
        register += {"DMTIMER7_TTGR", "DMTIMER7_TWPS", "DMTIMER7_TMAR", "DMTIMER7_TCAR1"}
        register += {"DMTIMER7_TSICR", "DMTIMER7_TCAR2"}
    }
    "EDMA3CC" {
        collapse = true
        register = {"TPCC_PID", "TPCC_CCCFG", "TPCC_DCHMAP0", "TPCC_DCHMAP1", "TPCC_DCHMAP2"}
        register += {"TPCC_DCHMAP3", "TPCC_DCHMAP4", "TPCC_DCHMAP5", "TPCC_DCHMAP6"}
        register += {"TPCC_DCHMAP7", "TPCC_DCHMAP8", "TPCC_DCHMAP9", "TPCC_DCHMAP10"}
        register += {"TPCC_DCHMAP11", "TPCC_DCHMAP12", "TPCC_DCHMAP13", "TPCC_DCHMAP14"}
        register += {"TPCC_DCHMAP15", "TPCC_DCHMAP16", "TPCC_DCHMAP17", "TPCC_DCHMAP18"}
        register += {"TPCC_DCHMAP19", "TPCC_DCHMAP20", "TPCC_DCHMAP21", "TPCC_DCHMAP22"}
        register += {"TPCC_DCHMAP23", "TPCC_DCHMAP24", "TPCC_DCHMAP25", "TPCC_DCHMAP26"}
        register += {"TPCC_DCHMAP27", "TPCC_DCHMAP28", "TPCC_DCHMAP29", "TPCC_DCHMAP30"}
        register += {"TPCC_DCHMAP31", "TPCC_DCHMAP32", "TPCC_DCHMAP33", "TPCC_DCHMAP34"}
        register += {"TPCC_DCHMAP35", "TPCC_DCHMAP36", "TPCC_DCHMAP37", "TPCC_DCHMAP38"}
        register += {"TPCC_DCHMAP39", "TPCC_DCHMAP40", "TPCC_DCHMAP41", "TPCC_DCHMAP42"}
        register += {"TPCC_DCHMAP43", "TPCC_DCHMAP44", "TPCC_DCHMAP45", "TPCC_DCHMAP46"}
        register += {"TPCC_DCHMAP47", "TPCC_DCHMAP48", "TPCC_DCHMAP49", "TPCC_DCHMAP50"}
        register += {"TPCC_DCHMAP51", "TPCC_DCHMAP52", "TPCC_DCHMAP53", "TPCC_DCHMAP54"}
        register += {"TPCC_DCHMAP55", "TPCC_DCHMAP56", "TPCC_DCHMAP57", "TPCC_DCHMAP58"}
        register += {"TPCC_DCHMAP59", "TPCC_DCHMAP60", "TPCC_DCHMAP61", "TPCC_DCHMAP62"}
        register += {"TPCC_DCHMAP63", "TPCC_QCHMAP0", "TPCC_QCHMAP1", "TPCC_QCHMAP2"}
        register += {"TPCC_QCHMAP3", "TPCC_QCHMAP4", "TPCC_QCHMAP5", "TPCC_QCHMAP6"}
        register += {"TPCC_QCHMAP7", "TPCC_DMAQNUM0", "TPCC_DMAQNUM1", "TPCC_DMAQNUM2"}
        register += {"TPCC_DMAQNUM3", "TPCC_DMAQNUM4", "TPCC_DMAQNUM5", "TPCC_DMAQNUM6"}
        register += {"TPCC_DMAQNUM7", "TPCC_QDMAQNUM", "TPCC_QUEPRI", "TPCC_EMR"}
        register += {"TPCC_EMRH", "TPCC_EMCR", "TPCC_EMCRH", "TPCC_QEMR", "TPCC_QEMCR"}
        register += {"TPCC_CCERR", "TPCC_CCERRCLR", "TPCC_EEVAL", "TPCC_DRAE0", "TPCC_DRAEH0"}
        register += {"TPCC_DRAE1", "TPCC_DRAEH1", "TPCC_DRAE2", "TPCC_DRAEH2", "TPCC_DRAE3"}
        register += {"TPCC_DRAEH3", "TPCC_DRAE4", "TPCC_DRAEH4", "TPCC_DRAE5", "TPCC_DRAEH5"}
        register += {"TPCC_DRAE6", "TPCC_DRAEH6", "TPCC_DRAE7", "TPCC_DRAEH7", "TPCC_QRAE0"}
        register += {"TPCC_QRAE1", "TPCC_QRAE2", "TPCC_QRAE3", "TPCC_QRAE4", "TPCC_QRAE5"}
        register += {"TPCC_QRAE6", "TPCC_QRAE7", "TPCC_Q0E0", "TPCC_Q0E1", "TPCC_Q0E2"}
        register += {"TPCC_Q0E3", "TPCC_Q0E4", "TPCC_Q0E5", "TPCC_Q0E6", "TPCC_Q0E7"}
        register += {"TPCC_Q0E8", "TPCC_Q0E9", "TPCC_Q0E10", "TPCC_Q0E11", "TPCC_Q0E12"}
        register += {"TPCC_Q0E13", "TPCC_Q0E14", "TPCC_Q0E15", "TPCC_Q1E0", "TPCC_Q1E1"}
        register += {"TPCC_Q1E2", "TPCC_Q1E3", "TPCC_Q1E4", "TPCC_Q1E5", "TPCC_Q1E6"}
        register += {"TPCC_Q1E7", "TPCC_Q1E8", "TPCC_Q1E9", "TPCC_Q1E10", "TPCC_Q1E11"}
        register += {"TPCC_Q1E12", "TPCC_Q1E13", "TPCC_Q1E14", "TPCC_Q1E15", "TPCC_Q2E0"}
        register += {"TPCC_Q2E1", "TPCC_Q2E2", "TPCC_Q2E3", "TPCC_Q2E4", "TPCC_Q2E5"}
        register += {"TPCC_Q2E6", "TPCC_Q2E7", "TPCC_Q2E8", "TPCC_Q2E9", "TPCC_Q2E10"}
        register += {"TPCC_Q2E11", "TPCC_Q2E12", "TPCC_Q2E13", "TPCC_Q2E14", "TPCC_Q2E15"}
        register += {"TPCC_Q3E0", "TPCC_Q3E1", "TPCC_Q3E2", "TPCC_Q3E3", "TPCC_Q3E4"}
        register += {"TPCC_Q3E5", "TPCC_Q3E6", "TPCC_Q3E7", "TPCC_Q3E8", "TPCC_Q3E9"}
        register += {"TPCC_Q3E10", "TPCC_Q3E11", "TPCC_Q3E12", "TPCC_Q3E13", "TPCC_Q3E14"}
        register += {"TPCC_Q3E15", "TPCC_QSTAT0", "TPCC_QSTAT1", "TPCC_QSTAT2", "TPCC_QSTAT3"}
        register += {"TPCC_QWMTHRA", "TPCC_CCSTAT", "TPCC_MPFAR", "TPCC_MPFSR", "TPCC_MPFCR"}
        register += {"TPCC_MPPAG", "TPCC_MPPA0", "TPCC_MPPA1", "TPCC_MPPA2", "TPCC_MPPA3"}
        register += {"TPCC_MPPA4", "TPCC_MPPA5", "TPCC_MPPA6", "TPCC_MPPA7", "TPCC_ER"}
        register += {"TPCC_ERH", "TPCC_ECR", "TPCC_ECRH", "TPCC_ESR", "TPCC_ESRH"}
        register += {"TPCC_CER", "TPCC_CERH", "TPCC_EER", "TPCC_EERH", "TPCC_EECR"}
        register += {"TPCC_EECRH", "TPCC_EESR", "TPCC_EESRH", "TPCC_SER", "TPCC_SERH"}
        register += {"TPCC_SECR", "TPCC_SECRH", "TPCC_IER", "TPCC_IERH", "TPCC_IECR"}
        register += {"TPCC_IECRH", "TPCC_IESR", "TPCC_IESRH", "TPCC_IPR", "TPCC_IPRH"}
        register += {"TPCC_ICR", "TPCC_ICRH", "TPCC_IEVAL", "TPCC_QER", "TPCC_QEER"}
        register += {"TPCC_QEECR", "TPCC_QEESR", "TPCC_QSER", "TPCC_QSECR"}
    }
    "EDMA3TC0" {
        collapse = true
        register = {"TPTC0_PID", "TPTC0_TCCFG", "TPTC0_TCSTAT", "TPTC0_ERRSTAT", "TPTC0_ERREN"}
        register += {"TPTC0_ERRCLR", "TPTC0_ERRDET", "TPTC0_ERRCMD", "TPTC0_RDRATE"}
        register += {"TPTC0_SAOPT", "TPTC0_SASRC", "TPTC0_SACNT", "TPTC0_SADST", "TPTC0_SABIDX"}
        register += {"TPTC0_SAMPPRXY", "TPTC0_SACNTRLD", "TPTC0_SASRCBREF", "TPTC0_SADSTBREF"}
        register += {"TPTC0_DFCNTRLD", "TPTC0_DFSRCBREF", "TPTC0_DFDSTBREF", "TPTC0_DFOPT0"}
        register += {"TPTC0_DFSRC0", "TPTC0_DFCNT0", "TPTC0_DFDST0", "TPTC0_DFBIDX0"}
        register += {"TPTC0_DFMPPRXY0", "TPTC0_DFOPT1", "TPTC0_DFSRC1", "TPTC0_DFCNT1"}
        register += {"TPTC0_DFDST1", "TPTC0_DFBIDX1", "TPTC0_DFMPPRXY1", "TPTC0_DFOPT2"}
        register += {"TPTC0_DFSRC2", "TPTC0_DFCNT2", "TPTC0_DFDST2", "TPTC0_DFBIDX2"}
        register += {"TPTC0_DFMPPRXY2", "TPTC0_DFOPT3", "TPTC0_DFSRC3", "TPTC0_DFCNT3"}
        register += {"TPTC0_DFDST3", "TPTC0_DFBIDX3", "TPTC0_DFMPPRXY3"}
    }
    "EDMA3TC1" {
        collapse = true
        register = {"TPTC1_PID", "TPTC1_TCCFG", "TPTC1_TCSTAT", "TPTC1_ERRSTAT", "TPTC1_ERREN"}
        register += {"TPTC1_ERRCLR", "TPTC1_ERRDET", "TPTC1_ERRCMD", "TPTC1_RDRATE"}
        register += {"TPTC1_SAOPT", "TPTC1_SASRC", "TPTC1_SACNT", "TPTC1_SADST", "TPTC1_SABIDX"}
        register += {"TPTC1_SAMPPRXY", "TPTC1_SACNTRLD", "TPTC1_SASRCBREF", "TPTC1_SADSTBREF"}
        register += {"TPTC1_DFCNTRLD", "TPTC1_DFSRCBREF", "TPTC1_DFDSTBREF", "TPTC1_DFOPT0"}
        register += {"TPTC1_DFSRC0", "TPTC1_DFCNT0", "TPTC1_DFDST0", "TPTC1_DFBIDX0"}
        register += {"TPTC1_DFMPPRXY0", "TPTC1_DFOPT1", "TPTC1_DFSRC1", "TPTC1_DFCNT1"}
        register += {"TPTC1_DFDST1", "TPTC1_DFBIDX1", "TPTC1_DFMPPRXY1", "TPTC1_DFOPT2"}
        register += {"TPTC1_DFSRC2", "TPTC1_DFCNT2", "TPTC1_DFDST2", "TPTC1_DFBIDX2"}
        register += {"TPTC1_DFMPPRXY2", "TPTC1_DFOPT3", "TPTC1_DFSRC3", "TPTC1_DFCNT3"}
        register += {"TPTC1_DFDST3", "TPTC1_DFBIDX3", "TPTC1_DFMPPRXY3"}
    }
    "EDMA3TC2" {
        collapse = true
        register = {"TPTC2_PID", "TPTC2_TCCFG", "TPTC2_TCSTAT", "TPTC2_ERRSTAT", "TPTC2_ERREN"}
        register += {"TPTC2_ERRCLR", "TPTC2_ERRDET", "TPTC2_ERRCMD", "TPTC2_RDRATE"}
        register += {"TPTC2_SAOPT", "TPTC2_SASRC", "TPTC2_SACNT", "TPTC2_SADST", "TPTC2_SABIDX"}
        register += {"TPTC2_SAMPPRXY", "TPTC2_SACNTRLD", "TPTC2_SASRCBREF", "TPTC2_SADSTBREF"}
        register += {"TPTC2_DFCNTRLD", "TPTC2_DFSRCBREF", "TPTC2_DFDSTBREF", "TPTC2_DFOPT0"}
        register += {"TPTC2_DFSRC0", "TPTC2_DFCNT0", "TPTC2_DFDST0", "TPTC2_DFBIDX0"}
        register += {"TPTC2_DFMPPRXY0", "TPTC2_DFOPT1", "TPTC2_DFSRC1", "TPTC2_DFCNT1"}
        register += {"TPTC2_DFDST1", "TPTC2_DFBIDX1", "TPTC2_DFMPPRXY1", "TPTC2_DFOPT2"}
        register += {"TPTC2_DFSRC2", "TPTC2_DFCNT2", "TPTC2_DFDST2", "TPTC2_DFBIDX2"}
        register += {"TPTC2_DFMPPRXY2", "TPTC2_DFOPT3", "TPTC2_DFSRC3", "TPTC2_DFCNT3"}
        register += {"TPTC2_DFDST3", "TPTC2_DFBIDX3", "TPTC2_DFMPPRXY3"}
    }
    "ELM" {
        collapse = true
        register = {"ELM_REVISION", "ELM_SYSCONFIG", "ELM_SYSSTATUS", "ELM_IRQSTATUS"}
        register += {"ELM_IRQENABLE", "ELM_LOCATION_CONFIG", "ELM_PAGE_CTRL", "ELM_SYNDROME_FRAGMENT_0_0"}
        register += {"ELM_SYNDROME_FRAGMENT_0_1", "ELM_SYNDROME_FRAGMENT_0_2", "ELM_SYNDROME_FRAGMENT_0_3"}
        register += {"ELM_SYNDROME_FRAGMENT_0_4", "ELM_SYNDROME_FRAGMENT_0_5", "ELM_SYNDROME_FRAGMENT_0_6"}
        register += {"ELM_SYNDROME_FRAGMENT_0_7", "ELM_SYNDROME_FRAGMENT_1_0", "ELM_SYNDROME_FRAGMENT_1_1"}
        register += {"ELM_SYNDROME_FRAGMENT_1_2", "ELM_SYNDROME_FRAGMENT_1_3", "ELM_SYNDROME_FRAGMENT_1_4"}
        register += {"ELM_SYNDROME_FRAGMENT_1_5", "ELM_SYNDROME_FRAGMENT_1_6", "ELM_SYNDROME_FRAGMENT_1_7"}
        register += {"ELM_SYNDROME_FRAGMENT_2_0", "ELM_SYNDROME_FRAGMENT_2_1", "ELM_SYNDROME_FRAGMENT_2_2"}
        register += {"ELM_SYNDROME_FRAGMENT_2_3", "ELM_SYNDROME_FRAGMENT_2_4", "ELM_SYNDROME_FRAGMENT_2_5"}
        register += {"ELM_SYNDROME_FRAGMENT_2_6", "ELM_SYNDROME_FRAGMENT_2_7", "ELM_SYNDROME_FRAGMENT_3_0"}
        register += {"ELM_SYNDROME_FRAGMENT_3_1", "ELM_SYNDROME_FRAGMENT_3_2", "ELM_SYNDROME_FRAGMENT_3_3"}
        register += {"ELM_SYNDROME_FRAGMENT_3_4", "ELM_SYNDROME_FRAGMENT_3_5", "ELM_SYNDROME_FRAGMENT_3_6"}
        register += {"ELM_SYNDROME_FRAGMENT_3_7", "ELM_SYNDROME_FRAGMENT_4_0", "ELM_SYNDROME_FRAGMENT_4_1"}
        register += {"ELM_SYNDROME_FRAGMENT_4_2", "ELM_SYNDROME_FRAGMENT_4_3", "ELM_SYNDROME_FRAGMENT_4_4"}
        register += {"ELM_SYNDROME_FRAGMENT_4_5", "ELM_SYNDROME_FRAGMENT_4_6", "ELM_SYNDROME_FRAGMENT_4_7"}
        register += {"ELM_SYNDROME_FRAGMENT_5_0", "ELM_SYNDROME_FRAGMENT_5_1", "ELM_SYNDROME_FRAGMENT_5_2"}
        register += {"ELM_SYNDROME_FRAGMENT_5_3", "ELM_SYNDROME_FRAGMENT_5_4", "ELM_SYNDROME_FRAGMENT_5_5"}
        register += {"ELM_SYNDROME_FRAGMENT_5_6", "ELM_SYNDROME_FRAGMENT_5_7", "ELM_SYNDROME_FRAGMENT_6_0"}
        register += {"ELM_SYNDROME_FRAGMENT_6_1", "ELM_SYNDROME_FRAGMENT_6_2", "ELM_SYNDROME_FRAGMENT_6_3"}
        register += {"ELM_SYNDROME_FRAGMENT_6_4", "ELM_SYNDROME_FRAGMENT_6_5", "ELM_SYNDROME_FRAGMENT_6_6"}
        register += {"ELM_SYNDROME_FRAGMENT_6_7", "ELM_LOCATION_STATUS_0", "ELM_LOCATION_STATUS_1"}
        register += {"ELM_LOCATION_STATUS_2", "ELM_LOCATION_STATUS_3", "ELM_LOCATION_STATUS_4"}
        register += {"ELM_LOCATION_STATUS_5", "ELM_LOCATION_STATUS_6", "ELM_LOCATION_STATUS_7"}
        register += {"ELM_ERROR_LOCATION_0_0", "ELM_ERROR_LOCATION_0_1", "ELM_ERROR_LOCATION_0_2"}
        register += {"ELM_ERROR_LOCATION_0_3", "ELM_ERROR_LOCATION_0_4", "ELM_ERROR_LOCATION_0_5"}
        register += {"ELM_ERROR_LOCATION_0_6", "ELM_ERROR_LOCATION_0_7", "ELM_ERROR_LOCATION_1_0"}
        register += {"ELM_ERROR_LOCATION_1_1", "ELM_ERROR_LOCATION_1_2", "ELM_ERROR_LOCATION_1_3"}
        register += {"ELM_ERROR_LOCATION_1_4", "ELM_ERROR_LOCATION_1_5", "ELM_ERROR_LOCATION_1_6"}
        register += {"ELM_ERROR_LOCATION_1_7", "ELM_ERROR_LOCATION_2_0", "ELM_ERROR_LOCATION_2_1"}
        register += {"ELM_ERROR_LOCATION_2_2", "ELM_ERROR_LOCATION_2_3", "ELM_ERROR_LOCATION_2_4"}
        register += {"ELM_ERROR_LOCATION_2_5", "ELM_ERROR_LOCATION_2_6", "ELM_ERROR_LOCATION_2_7"}
        register += {"ELM_ERROR_LOCATION_3_0", "ELM_ERROR_LOCATION_3_1", "ELM_ERROR_LOCATION_3_2"}
        register += {"ELM_ERROR_LOCATION_3_3", "ELM_ERROR_LOCATION_3_4", "ELM_ERROR_LOCATION_3_5"}
        register += {"ELM_ERROR_LOCATION_3_6", "ELM_ERROR_LOCATION_3_7", "ELM_ERROR_LOCATION_4_0"}
        register += {"ELM_ERROR_LOCATION_4_1", "ELM_ERROR_LOCATION_4_2", "ELM_ERROR_LOCATION_4_3"}
        register += {"ELM_ERROR_LOCATION_4_4", "ELM_ERROR_LOCATION_4_5", "ELM_ERROR_LOCATION_4_6"}
        register += {"ELM_ERROR_LOCATION_4_7", "ELM_ERROR_LOCATION_5_0", "ELM_ERROR_LOCATION_5_1"}
        register += {"ELM_ERROR_LOCATION_5_2", "ELM_ERROR_LOCATION_5_3", "ELM_ERROR_LOCATION_5_4"}
        register += {"ELM_ERROR_LOCATION_5_5", "ELM_ERROR_LOCATION_5_6", "ELM_ERROR_LOCATION_5_7"}
        register += {"ELM_ERROR_LOCATION_6_0", "ELM_ERROR_LOCATION_6_1", "ELM_ERROR_LOCATION_6_2"}
        register += {"ELM_ERROR_LOCATION_6_3", "ELM_ERROR_LOCATION_6_4", "ELM_ERROR_LOCATION_6_5"}
        register += {"ELM_ERROR_LOCATION_6_6", "ELM_ERROR_LOCATION_6_7", "ELM_ERROR_LOCATION_7_0"}
        register += {"ELM_ERROR_LOCATION_7_1", "ELM_ERROR_LOCATION_7_2", "ELM_ERROR_LOCATION_7_3"}
        register += {"ELM_ERROR_LOCATION_7_4", "ELM_ERROR_LOCATION_7_5", "ELM_ERROR_LOCATION_7_6"}
        register += {"ELM_ERROR_LOCATION_7_7", "ELM_ERROR_LOCATION_8_0", "ELM_ERROR_LOCATION_8_1"}
        register += {"ELM_ERROR_LOCATION_8_2", "ELM_ERROR_LOCATION_8_3", "ELM_ERROR_LOCATION_8_4"}
        register += {"ELM_ERROR_LOCATION_8_5", "ELM_ERROR_LOCATION_8_6", "ELM_ERROR_LOCATION_8_7"}
        register += {"ELM_ERROR_LOCATION_9_0", "ELM_ERROR_LOCATION_9_1", "ELM_ERROR_LOCATION_9_2"}
        register += {"ELM_ERROR_LOCATION_9_3", "ELM_ERROR_LOCATION_9_4", "ELM_ERROR_LOCATION_9_5"}
        register += {"ELM_ERROR_LOCATION_9_6", "ELM_ERROR_LOCATION_9_7", "ELM_ERROR_LOCATION_10_0"}
        register += {"ELM_ERROR_LOCATION_10_1", "ELM_ERROR_LOCATION_10_2", "ELM_ERROR_LOCATION_10_3"}
        register += {"ELM_ERROR_LOCATION_10_4", "ELM_ERROR_LOCATION_10_5", "ELM_ERROR_LOCATION_10_6"}
        register += {"ELM_ERROR_LOCATION_10_7", "ELM_ERROR_LOCATION_11_0", "ELM_ERROR_LOCATION_11_1"}
        register += {"ELM_ERROR_LOCATION_11_2", "ELM_ERROR_LOCATION_11_3", "ELM_ERROR_LOCATION_11_4"}
        register += {"ELM_ERROR_LOCATION_11_5", "ELM_ERROR_LOCATION_11_6", "ELM_ERROR_LOCATION_11_7"}
        register += {"ELM_ERROR_LOCATION_12_0", "ELM_ERROR_LOCATION_12_1", "ELM_ERROR_LOCATION_12_2"}
        register += {"ELM_ERROR_LOCATION_12_3", "ELM_ERROR_LOCATION_12_4", "ELM_ERROR_LOCATION_12_5"}
        register += {"ELM_ERROR_LOCATION_12_6", "ELM_ERROR_LOCATION_12_7", "ELM_ERROR_LOCATION_13_0"}
        register += {"ELM_ERROR_LOCATION_13_1", "ELM_ERROR_LOCATION_13_2", "ELM_ERROR_LOCATION_13_3"}
        register += {"ELM_ERROR_LOCATION_13_4", "ELM_ERROR_LOCATION_13_5", "ELM_ERROR_LOCATION_13_6"}
        register += {"ELM_ERROR_LOCATION_13_7", "ELM_ERROR_LOCATION_14_0", "ELM_ERROR_LOCATION_14_1"}
        register += {"ELM_ERROR_LOCATION_14_2", "ELM_ERROR_LOCATION_14_3", "ELM_ERROR_LOCATION_14_4"}
        register += {"ELM_ERROR_LOCATION_14_5", "ELM_ERROR_LOCATION_14_6", "ELM_ERROR_LOCATION_14_7"}
        register += {"ELM_ERROR_LOCATION_15_0", "ELM_ERROR_LOCATION_15_1", "ELM_ERROR_LOCATION_15_2"}
        register += {"ELM_ERROR_LOCATION_15_3", "ELM_ERROR_LOCATION_15_4", "ELM_ERROR_LOCATION_15_5"}
        register += {"ELM_ERROR_LOCATION_15_6", "ELM_ERROR_LOCATION_15_7"}
    }
    "EMIF0" {
        collapse = true
        register = {"EMIF_MOD_ID_REV", "STATUS", "SDRAM_CONFIG", "SDRAM_CONFIG_2"}
        register += {"SDRAM_REF_CTRL", "SDRAM_REF_CTRL_SHDW", "SDRAM_TIM_1", "SDRAM_TIM_1_SHDW"}
        register += {"SDRAM_TIM_2", "SDRAM_TIM_2_SHDW", "SDRAM_TIM_3", "SDRAM_TIM_3_SHDW"}
        register += {"PWR_MGMT_CTRL", "PWR_MGMT_CTRL_SHDW", "PERF_CNT_1", "PERF_CNT_2"}
        register += {"PERF_CNT_CFG", "PERF_CNT_SEL", "PERF_CNT_TIM", "READ_IDLE_CTRL"}
        register += {"READ_IDLE_CTRL_SHDW", "IRQSTATUS_RAW_SYS", "IRQSTATUS_SYS"}
        register += {"IRQENABLE_SET_SYS", "IRQENABLE_CLR_SYS", "ZQ_CONFIG", "RDWR_LVL_RMP_WIN"}
        register += {"RDWR_LVL_RMP_CTRL", "RDWR_LVL_CTRL", "DDR_PHY_CTRL_1", "DDR_PHY_CTRL_1_SHDW"}
        register += {"PRI_COS_MAP", "CONNID_COS_1_MAP", "CONNID_COS_2_MAP", "RD_WR_EXEC_THRSH"}
    }
    "GPIO0" {
        collapse = true
        register = {"GPIO0_REVISION", "GPIO0_SYSCONFIG", "GPIO0_IRQSTATUS_RAW_0"}
        register += {"GPIO0_IRQSTATUS_RAW_1", "GPIO0_IRQSTATUS_0", "GPIO0_IRQSTATUS_1"}
        register += {"GPIO0_IRQSTATUS_SET_0", "GPIO0_IRQSTATUS_SET_1", "GPIO0_IRQSTATUS_CLR_0"}
        register += {"GPIO0_IRQSTATUS_CLR_1", "GPIO0_IRQWAKEN_0", "GPIO0_IRQWAKEN_1"}
        register += {"GPIO0_SYSSTATUS", "GPIO0_CTRL", "GPIO0_OE", "GPIO0_DATAIN"}
        register += {"GPIO0_DATAOUT", "GPIO0_LEVELDETECT0", "GPIO0_LEVELDETECT1"}
        register += {"GPIO0_RISINGDETECT", "GPIO0_FALLINGDETECT", "GPIO0_DEBOUNCENABLE"}
        register += {"GPIO0_DEBOUNCINGTIME", "GPIO0_CLEARDATAOUT", "GPIO0_SETDATAOUT"}
    }
    "GPIO1" {
        collapse = true
        register = {"GPIO1_REVISION", "GPIO1_SYSCONFIG", "GPIO1_IRQSTATUS_RAW_0"}
        register += {"GPIO1_IRQSTATUS_RAW_1", "GPIO1_IRQSTATUS_0", "GPIO1_IRQSTATUS_1"}
        register += {"GPIO1_IRQSTATUS_SET_0", "GPIO1_IRQSTATUS_SET_1", "GPIO1_IRQSTATUS_CLR_0"}
        register += {"GPIO1_IRQSTATUS_CLR_1", "GPIO1_IRQWAKEN_0", "GPIO1_IRQWAKEN_1"}
        register += {"GPIO1_SYSSTATUS", "GPIO1_CTRL", "GPIO1_OE", "GPIO1_DATAIN"}
        register += {"GPIO1_DATAOUT", "GPIO1_LEVELDETECT0", "GPIO1_LEVELDETECT1"}
        register += {"GPIO1_RISINGDETECT", "GPIO1_FALLINGDETECT", "GPIO1_DEBOUNCENABLE"}
        register += {"GPIO1_DEBOUNCINGTIME", "GPIO1_CLEARDATAOUT", "GPIO1_SETDATAOUT"}
    }
    "GPIO2" {
        collapse = true
        register = {"GPIO2_REVISION", "GPIO2_SYSCONFIG", "GPIO2_IRQSTATUS_RAW_0"}
        register += {"GPIO2_IRQSTATUS_RAW_1", "GPIO2_IRQSTATUS_0", "GPIO2_IRQSTATUS_1"}
        register += {"GPIO2_IRQSTATUS_SET_0", "GPIO2_IRQSTATUS_SET_1", "GPIO2_IRQSTATUS_CLR_0"}
        register += {"GPIO2_IRQSTATUS_CLR_1", "GPIO2_IRQWAKEN_0", "GPIO2_IRQWAKEN_1"}
        register += {"GPIO2_SYSSTATUS", "GPIO2_CTRL", "GPIO2_OE", "GPIO2_DATAIN"}
        register += {"GPIO2_DATAOUT", "GPIO2_LEVELDETECT0", "GPIO2_LEVELDETECT1"}
        register += {"GPIO2_RISINGDETECT", "GPIO2_FALLINGDETECT", "GPIO2_DEBOUNCENABLE"}
        register += {"GPIO2_DEBOUNCINGTIME", "GPIO2_CLEARDATAOUT", "GPIO2_SETDATAOUT"}
    }
    "GPIO3" {
        collapse = true
        register = {"GPIO3_REVISION", "GPIO3_SYSCONFIG", "GPIO3_IRQSTATUS_RAW_0"}
        register += {"GPIO3_IRQSTATUS_RAW_1", "GPIO3_IRQSTATUS_0", "GPIO3_IRQSTATUS_1"}
        register += {"GPIO3_IRQSTATUS_SET_0", "GPIO3_IRQSTATUS_SET_1", "GPIO3_IRQSTATUS_CLR_0"}
        register += {"GPIO3_IRQSTATUS_CLR_1", "GPIO3_IRQWAKEN_0", "GPIO3_IRQWAKEN_1"}
        register += {"GPIO3_SYSSTATUS", "GPIO3_CTRL", "GPIO3_OE", "GPIO3_DATAIN"}
        register += {"GPIO3_DATAOUT", "GPIO3_LEVELDETECT0", "GPIO3_LEVELDETECT1"}
        register += {"GPIO3_RISINGDETECT", "GPIO3_FALLINGDETECT", "GPIO3_DEBOUNCENABLE"}
        register += {"GPIO3_DEBOUNCINGTIME", "GPIO3_CLEARDATAOUT", "GPIO3_SETDATAOUT"}
    }
    "GPMC" {
        collapse = true
        register = {"GPMC_REVISION", "GPMC_SYSCONFIG", "GPMC_SYSSTATUS", "GPMC_IRQSTATUS"}
        register += {"GPMC_IRQENABLE", "GPMC_TIMEOUT_CONTROL", "GPMC_ERR_ADDRESS"}
        register += {"GPMC_ERR_TYPE", "GPMC_CONFIG", "GPMC_STATUS", "GPMC_PREFETCH_CONFIG1"}
        register += {"GPMC_PREFETCH_CONFIG2", "GPMC_PREFETCH_CONTROL", "GPMC_PREFETCH_STATUS"}
        register += {"GPMC_ECC_CONFIG", "GPMC_ECC_CONTROL", "GPMC_ECC_SIZE_CONFIG"}
        register += {"GPMC_BCH_SWDATA", "GPMC_CONFIG1_0", "GPMC_CONFIG2_0", "GPMC_CONFIG3_0"}
        register += {"GPMC_CONFIG4_0", "GPMC_CONFIG5_0", "GPMC_CONFIG6_0", "GPMC_CONFIG7_0"}
        register += {"GPMC_CONFIG1_1", "GPMC_CONFIG2_1", "GPMC_CONFIG3_1", "GPMC_CONFIG4_1"}
        register += {"GPMC_CONFIG5_1", "GPMC_CONFIG6_1", "GPMC_CONFIG7_1", "GPMC_CONFIG1_2"}
        register += {"GPMC_CONFIG2_2", "GPMC_CONFIG3_2", "GPMC_CONFIG4_2", "GPMC_CONFIG5_2"}
        register += {"GPMC_CONFIG6_2", "GPMC_CONFIG7_2", "GPMC_CONFIG1_3", "GPMC_CONFIG2_3"}
        register += {"GPMC_CONFIG3_3", "GPMC_CONFIG4_3", "GPMC_CONFIG5_3", "GPMC_CONFIG6_3"}
        register += {"GPMC_CONFIG7_3", "GPMC_CONFIG1_4", "GPMC_CONFIG2_4", "GPMC_CONFIG3_4"}
        register += {"GPMC_CONFIG4_4", "GPMC_CONFIG5_4", "GPMC_CONFIG6_4", "GPMC_CONFIG7_4"}
        register += {"GPMC_CONFIG1_5", "GPMC_CONFIG2_5", "GPMC_CONFIG3_5", "GPMC_CONFIG4_5"}
        register += {"GPMC_CONFIG5_5", "GPMC_CONFIG6_5", "GPMC_CONFIG7_5", "GPMC_CONFIG1_6"}
        register += {"GPMC_CONFIG2_6", "GPMC_CONFIG3_6", "GPMC_CONFIG4_6", "GPMC_CONFIG5_6"}
        register += {"GPMC_CONFIG6_6", "GPMC_CONFIG7_6", "GPMC_NAND_COMMAND_0", "GPMC_NAND_COMMAND_1"}
        register += {"GPMC_NAND_COMMAND_2", "GPMC_NAND_COMMAND_3", "GPMC_NAND_COMMAND_4"}
        register += {"GPMC_NAND_COMMAND_5", "GPMC_NAND_COMMAND_6", "GPMC_NAND_ADDRESS_0"}
        register += {"GPMC_NAND_ADDRESS_1", "GPMC_NAND_ADDRESS_2", "GPMC_NAND_ADDRESS_3"}
        register += {"GPMC_NAND_ADDRESS_4", "GPMC_NAND_ADDRESS_5", "GPMC_NAND_ADDRESS_6"}
        register += {"GPMC_NAND_DATA_0", "GPMC_NAND_DATA_1", "GPMC_NAND_DATA_2", "GPMC_NAND_DATA_3"}
        register += {"GPMC_NAND_DATA_4", "GPMC_NAND_DATA_5", "GPMC_NAND_DATA_6", "GPMC_ECC1_RESULT"}
        register += {"GPMC_ECC2_RESULT", "GPMC_ECC3_RESULT", "GPMC_ECC4_RESULT", "GPMC_ECC5_RESULT"}
        register += {"GPMC_ECC6_RESULT", "GPMC_ECC7_RESULT", "GPMC_ECC8_RESULT", "GPMC_ECC9_RESULT"}
        register += {"GPMC_BCH_RESULT0_0", "GPMC_BCH_RESULT0_1", "GPMC_BCH_RESULT0_2"}
        register += {"GPMC_BCH_RESULT0_3", "GPMC_BCH_RESULT0_4", "GPMC_BCH_RESULT0_5"}
        register += {"GPMC_BCH_RESULT0_6", "GPMC_BCH_RESULT1_0", "GPMC_BCH_RESULT1_1"}
        register += {"GPMC_BCH_RESULT1_2", "GPMC_BCH_RESULT1_3", "GPMC_BCH_RESULT1_4"}
        register += {"GPMC_BCH_RESULT1_5", "GPMC_BCH_RESULT1_6", "GPMC_BCH_RESULT2_0"}
        register += {"GPMC_BCH_RESULT2_1", "GPMC_BCH_RESULT2_2", "GPMC_BCH_RESULT2_3"}
        register += {"GPMC_BCH_RESULT2_4", "GPMC_BCH_RESULT2_5", "GPMC_BCH_RESULT2_6"}
        register += {"GPMC_BCH_RESULT3_0", "GPMC_BCH_RESULT3_1", "GPMC_BCH_RESULT3_2"}
        register += {"GPMC_BCH_RESULT3_3", "GPMC_BCH_RESULT3_4", "GPMC_BCH_RESULT3_5"}
        register += {"GPMC_BCH_RESULT3_6", "GPMC_BCH_RESULT4_0", "GPMC_BCH_RESULT4_1"}
        register += {"GPMC_BCH_RESULT4_2", "GPMC_BCH_RESULT4_3", "GPMC_BCH_RESULT4_4"}
        register += {"GPMC_BCH_RESULT4_5", "GPMC_BCH_RESULT4_6", "GPMC_BCH_RESULT5_0"}
        register += {"GPMC_BCH_RESULT5_1", "GPMC_BCH_RESULT5_2", "GPMC_BCH_RESULT5_3"}
        register += {"GPMC_BCH_RESULT5_4", "GPMC_BCH_RESULT5_5", "GPMC_BCH_RESULT5_6"}
        register += {"GPMC_BCH_RESULT6_0", "GPMC_BCH_RESULT6_1", "GPMC_BCH_RESULT6_2"}
        register += {"GPMC_BCH_RESULT6_3", "GPMC_BCH_RESULT6_4", "GPMC_BCH_RESULT6_5"}
        register += {"GPMC_BCH_RESULT6_6"}
    }
    "I2C0" {
        collapse = true
        register = {"I2C0_REVNB_LO", "I2C0_REVNB_HI", "I2C0_SYSC", "I2C0_EOI", "I2C0_IRQSTATUS_RAW"}
        register += {"I2C0_IRQSTATUS", "I2C0_IRQENABLE_SET", "I2C0_IRQENABLE_CLR"}
        register += {"I2C0_WE", "I2C0_DMARXENABLE_SET", "I2C0_DMATXENABLE_SET", "I2C0_DMARXENABLE_CLR"}
        register += {"I2C0_DMATXENABLE_CLR", "I2C0_DMARXWAKE_EN", "I2C0_DMATXWAKE_EN"}
        register += {"I2C0_SYSS", "I2C0_BUF", "I2C0_CNT", "I2C0_DATA", "I2C0_CON"}
        register += {"I2C0_OA", "I2C0_SA", "I2C0_PSC", "I2C0_SCLL", "I2C0_SCLH", "I2C0_SYSTEST"}
        register += {"I2C0_BUFSTAT", "I2C0_OA1", "I2C0_OA2", "I2C0_OA3", "I2C0_ACTOA"}
        register += {"I2C0_SBLOCK"}
    }
    "I2C1" {
        collapse = true
        register = {"I2C1_REVNB_LO", "I2C1_REVNB_HI", "I2C1_SYSC", "I2C1_EOI", "I2C1_IRQSTATUS_RAW"}
        register += {"I2C1_IRQSTATUS", "I2C1_IRQENABLE_SET", "I2C1_IRQENABLE_CLR"}
        register += {"I2C1_WE", "I2C1_DMARXENABLE_SET", "I2C1_DMATXENABLE_SET", "I2C1_DMARXENABLE_CLR"}
        register += {"I2C1_DMATXENABLE_CLR", "I2C1_DMARXWAKE_EN", "I2C1_DMATXWAKE_EN"}
        register += {"I2C1_SYSS", "I2C1_BUF", "I2C1_CNT", "I2C1_DATA", "I2C1_CON"}
        register += {"I2C1_OA", "I2C1_SA", "I2C1_PSC", "I2C1_SCLL", "I2C1_SCLH", "I2C1_SYSTEST"}
        register += {"I2C1_BUFSTAT", "I2C1_OA1", "I2C1_OA2", "I2C1_OA3", "I2C1_ACTOA"}
        register += {"I2C1_SBLOCK"}
    }
    "I2C2" {
        collapse = true
        register = {"I2C2_REVNB_LO", "I2C2_REVNB_HI", "I2C2_SYSC", "I2C2_EOI", "I2C2_IRQSTATUS_RAW"}
        register += {"I2C2_IRQSTATUS", "I2C2_IRQENABLE_SET", "I2C2_IRQENABLE_CLR"}
        register += {"I2C2_WE", "I2C2_DMARXENABLE_SET", "I2C2_DMATXENABLE_SET", "I2C2_DMARXENABLE_CLR"}
        register += {"I2C2_DMATXENABLE_CLR", "I2C2_DMARXWAKE_EN", "I2C2_DMATXWAKE_EN"}
        register += {"I2C2_SYSS", "I2C2_BUF", "I2C2_CNT", "I2C2_DATA", "I2C2_CON"}
        register += {"I2C2_OA", "I2C2_SA", "I2C2_PSC", "I2C2_SCLL", "I2C2_SCLH", "I2C2_SYSTEST"}
        register += {"I2C2_BUFSTAT", "I2C2_OA1", "I2C2_OA2", "I2C2_OA3", "I2C2_ACTOA"}
        register += {"I2C2_SBLOCK"}
    }
    "INTCPS" {
        collapse = true
        register = {"INTC_REVISION", "INTC_SYSCONFIG", "INTC_SYSSTATUS", "INTC_SIR_IRQ"}
        register += {"INTC_SIR_FIQ", "INTC_CONTROL", "INTC_PROTECTION", "INTC_IDLE"}
        register += {"INTC_IRQ_PRIORITY", "INTC_FIQ_PRIORITY", "INTC_THRESHOLD", "INTC_ITR0"}
        register += {"INTC_MIR0", "INTC_MIR_CLEAR0", "INTC_MIR_SET0", "INTC_ISR_SET0"}
        register += {"INTC_ISR_CLEAR0", "INTC_PENDING_IRQ0", "INTC_PENDING_FIQ0"}
        register += {"INTC_ITR1", "INTC_MIR1", "INTC_MIR_CLEAR1", "INTC_MIR_SET1"}
        register += {"INTC_ISR_SET1", "INTC_ISR_CLEAR1", "INTC_PENDING_IRQ1", "INTC_PENDING_FIQ1"}
        register += {"INTC_ITR2", "INTC_MIR2", "INTC_MIR_CLEAR2", "INTC_MIR_SET2"}
        register += {"INTC_ISR_SET2", "INTC_ISR_CLEAR2", "INTC_PENDING_IRQ2", "INTC_PENDING_FIQ2"}
        register += {"INTC_ITR3", "INTC_MIR3", "INTC_MIR_CLEAR3", "INTC_MIR_SET3"}
        register += {"INTC_ISR_SET3", "INTC_ISR_CLEAR3", "INTC_PENDING_IRQ3", "INTC_PENDING_FIQ3"}
        register += {"INTC_ILR0", "INTC_ILR1", "INTC_ILR2", "INTC_ILR3", "INTC_ILR4"}
        register += {"INTC_ILR5", "INTC_ILR6", "INTC_ILR7", "INTC_ILR8", "INTC_ILR9"}
        register += {"INTC_ILR10", "INTC_ILR11", "INTC_ILR12", "INTC_ILR13", "INTC_ILR14"}
        register += {"INTC_ILR15", "INTC_ILR16", "INTC_ILR17", "INTC_ILR18", "INTC_ILR19"}
        register += {"INTC_ILR20", "INTC_ILR21", "INTC_ILR22", "INTC_ILR23", "INTC_ILR24"}
        register += {"INTC_ILR25", "INTC_ILR26", "INTC_ILR27", "INTC_ILR28", "INTC_ILR29"}
        register += {"INTC_ILR30", "INTC_ILR31", "INTC_ILR32", "INTC_ILR33", "INTC_ILR34"}
        register += {"INTC_ILR35", "INTC_ILR36", "INTC_ILR37", "INTC_ILR38", "INTC_ILR39"}
        register += {"INTC_ILR40", "INTC_ILR41", "INTC_ILR42", "INTC_ILR43", "INTC_ILR44"}
        register += {"INTC_ILR45", "INTC_ILR46", "INTC_ILR47", "INTC_ILR48", "INTC_ILR49"}
        register += {"INTC_ILR50", "INTC_ILR51", "INTC_ILR52", "INTC_ILR53", "INTC_ILR54"}
        register += {"INTC_ILR55", "INTC_ILR56", "INTC_ILR57", "INTC_ILR58", "INTC_ILR59"}
        register += {"INTC_ILR60", "INTC_ILR61", "INTC_ILR62", "INTC_ILR63", "INTC_ILR64"}
        register += {"INTC_ILR65", "INTC_ILR66", "INTC_ILR67", "INTC_ILR68", "INTC_ILR69"}
        register += {"INTC_ILR70", "INTC_ILR71", "INTC_ILR72", "INTC_ILR73", "INTC_ILR74"}
        register += {"INTC_ILR75", "INTC_ILR76", "INTC_ILR77", "INTC_ILR78", "INTC_ILR79"}
        register += {"INTC_ILR80", "INTC_ILR81", "INTC_ILR82", "INTC_ILR83", "INTC_ILR84"}
        register += {"INTC_ILR85", "INTC_ILR86", "INTC_ILR87", "INTC_ILR88", "INTC_ILR89"}
        register += {"INTC_ILR90", "INTC_ILR91", "INTC_ILR92", "INTC_ILR93", "INTC_ILR94"}
        register += {"INTC_ILR95", "INTC_ILR96", "INTC_ILR97", "INTC_ILR98", "INTC_ILR99"}
        register += {"INTC_ILR100", "INTC_ILR101", "INTC_ILR102", "INTC_ILR103", "INTC_ILR104"}
        register += {"INTC_ILR105", "INTC_ILR106", "INTC_ILR107", "INTC_ILR108", "INTC_ILR109"}
        register += {"INTC_ILR110", "INTC_ILR111", "INTC_ILR112", "INTC_ILR113", "INTC_ILR114"}
        register += {"INTC_ILR115", "INTC_ILR116", "INTC_ILR117", "INTC_ILR118", "INTC_ILR119"}
        register += {"INTC_ILR120", "INTC_ILR121", "INTC_ILR122", "INTC_ILR123", "INTC_ILR124"}
        register += {"INTC_ILR125", "INTC_ILR126", "INTC_ILR127"}
    }
    "LCD_Controller" {
        collapse = true
        register = {"LCD_Controller_PID", "LCD_Controller_CTRL", "LCD_Controller_LIDD_CTRL"}
        register += {"LCD_Controller_LIDD_CS0_CONF", "LCD_Controller_LIDD_CS0_ADDR"}
        register += {"LCD_Controller_LIDD_CS0_DATA", "LCD_Controller_LIDD_CS1_CONF"}
        register += {"LCD_Controller_LIDD_CS1_ADDR", "LCD_Controller_LIDD_CS1_DATA"}
        register += {"LCD_Controller_RASTER_CTRL", "LCD_Controller_RASTER_TIMING_0"}
        register += {"LCD_Controller_RASTER_TIMING_1", "LCD_Controller_RASTER_TIMING_2"}
        register += {"LCD_Controller_RASTER_SUBPANEL", "LCD_Controller_RASTER_SUBPANEL2"}
        register += {"LCD_Controller_LCDDMA_CTRL", "LCD_Controller_LCDDMA_FB0_BASE"}
        register += {"LCD_Controller_LCDDMA_FB0_CEILING", "LCD_Controller_LCDDMA_FB1_BASE"}
        register += {"LCD_Controller_LCDDMA_FB1_CEILING", "LCD_Controller_SYSCONFIG"}
        register += {"LCD_Controller_IRQSTATUS_RAW", "LCD_Controller_IRQSTATUS", "LCD_Controller_IRQENABLE_SET"}
        register += {"LCD_Controller_IRQENABLE_CLEAR", "LCD_Controller_CLKC_ENABLE"}
        register += {"LCD_Controller_CLKC_RESET"}
    }
    "MAILBOX0" {
        collapse = true
        register = {"MAILBOX0_REVISION", "MAILBOX0_SYSCONFIG", "MAILBOX0_MESSAGE_0"}
        register += {"MAILBOX0_MESSAGE_1", "MAILBOX0_MESSAGE_2", "MAILBOX0_MESSAGE_3"}
        register += {"MAILBOX0_MESSAGE_4", "MAILBOX0_MESSAGE_5", "MAILBOX0_MESSAGE_6"}
        register += {"MAILBOX0_MESSAGE_7", "MAILBOX0_FIFOSTATUS_0", "MAILBOX0_FIFOSTATUS_1"}
        register += {"MAILBOX0_FIFOSTATUS_2", "MAILBOX0_FIFOSTATUS_3", "MAILBOX0_FIFOSTATUS_4"}
        register += {"MAILBOX0_FIFOSTATUS_5", "MAILBOX0_FIFOSTATUS_6", "MAILBOX0_FIFOSTATUS_7"}
        register += {"MAILBOX0_MSGSTATUS_0", "MAILBOX0_MSGSTATUS_1", "MAILBOX0_MSGSTATUS_2"}
        register += {"MAILBOX0_MSGSTATUS_3", "MAILBOX0_MSGSTATUS_4", "MAILBOX0_MSGSTATUS_5"}
        register += {"MAILBOX0_MSGSTATUS_6", "MAILBOX0_MSGSTATUS_7", "MAILBOX0_IRQSTATUS_RAW_0"}
        register += {"MAILBOX0_IRQSTATUS_CLR_0", "MAILBOX0_IRQENABLE_SET_0", "MAILBOX0_IRQENABLE_CLR_0"}
        register += {"MAILBOX0_IRQSTATUS_RAW_1", "MAILBOX0_IRQSTATUS_CLR_1", "MAILBOX0_IRQENABLE_SET_1"}
        register += {"MAILBOX0_IRQENABLE_CLR_1", "MAILBOX0_IRQSTATUS_RAW_2", "MAILBOX0_IRQSTATUS_CLR_2"}
        register += {"MAILBOX0_IRQENABLE_SET_2", "MAILBOX0_IRQENABLE_CLR_2", "MAILBOX0_IRQSTATUS_RAW_3"}
        register += {"MAILBOX0_IRQSTATUS_CLR_3", "MAILBOX0_IRQENABLE_SET_3", "MAILBOX0_IRQENABLE_CLR_3"}
    }
    "MDIO" {
        collapse = true
        register = {"MDIOVER", "MDIOCONTROL", "MDIOALIVE", "MDIOLINK", "MDIOLINKINTRAW"}
        register += {"MDIOLINKINTMASKED", "MDIOUSERINTRAW", "MDIOUSERINTMASKED", "MDIOUSERINTMASKSET"}
        register += {"MDIOUSERINTMASKCLR", "MDIOUSERACCESS0", "MDIOUSERPHYSEL0", "MDIOUSERACCESS1"}
        register += {"MDIOUSERPHYSEL1"}
    }
    "MMC1" {
        collapse = true
        register = {"MMC1_SD_SYSCONFIG", "MMC1_SD_SYSSTATUS", "MMC1_SD_CSRE", "MMC1_SD_SYSTEST"}
        register += {"MMC1_SD_CON", "MMC1_SD_PWCNT", "MMC1_SD_SDMASA", "MMC1_SD_BLK"}
        register += {"MMC1_SD_ARG", "MMC1_SD_CMD", "MMC1_SD_RSP10", "MMC1_SD_RSP32"}
        register += {"MMC1_SD_RSP54", "MMC1_SD_RSP76", "MMC1_SD_DATA", "MMC1_SD_PSTATE"}
        register += {"MMC1_SD_HCTL", "MMC1_SD_SYSCTL", "MMC1_SD_STAT", "MMC1_SD_IE"}
        register += {"MMC1_SD_ISE", "MMC1_SD_AC12", "MMC1_SD_CAPA", "MMC1_SD_CUR_CAPA"}
        register += {"MMC1_SD_FE", "MMC1_SD_ADMAES", "MMC1_SD_ADMASAL", "MMC1_SD_ADMASAH"}
        register += {"MMC1_SD_REV"}
    }
    "MMCHS0" {
        collapse = true
        register = {"MMCHS0_SD_SYSCONFIG", "MMCHS0_SD_SYSSTATUS", "MMCHS0_SD_CSRE"}
        register += {"MMCHS0_SD_SYSTEST", "MMCHS0_SD_CON", "MMCHS0_SD_PWCNT", "MMCHS0_SD_SDMASA"}
        register += {"MMCHS0_SD_BLK", "MMCHS0_SD_ARG", "MMCHS0_SD_CMD", "MMCHS0_SD_RSP10"}
        register += {"MMCHS0_SD_RSP32", "MMCHS0_SD_RSP54", "MMCHS0_SD_RSP76", "MMCHS0_SD_DATA"}
        register += {"MMCHS0_SD_PSTATE", "MMCHS0_SD_HCTL", "MMCHS0_SD_SYSCTL", "MMCHS0_SD_STAT"}
        register += {"MMCHS0_SD_IE", "MMCHS0_SD_ISE", "MMCHS0_SD_AC12", "MMCHS0_SD_CAPA"}
        register += {"MMCHS0_SD_CUR_CAPA", "MMCHS0_SD_FE", "MMCHS0_SD_ADMAES", "MMCHS0_SD_ADMASAL"}
        register += {"MMCHS0_SD_ADMASAH", "MMCHS0_SD_REV"}
    }
    "MMCHS2" {
        collapse = true
        register = {"MMCHS2_SD_SYSCONFIG", "MMCHS2_SD_SYSSTATUS", "MMCHS2_SD_CSRE"}
        register += {"MMCHS2_SD_SYSTEST", "MMCHS2_SD_CON", "MMCHS2_SD_PWCNT", "MMCHS2_SD_SDMASA"}
        register += {"MMCHS2_SD_BLK", "MMCHS2_SD_ARG", "MMCHS2_SD_CMD", "MMCHS2_SD_RSP10"}
        register += {"MMCHS2_SD_RSP32", "MMCHS2_SD_RSP54", "MMCHS2_SD_RSP76", "MMCHS2_SD_DATA"}
        register += {"MMCHS2_SD_PSTATE", "MMCHS2_SD_HCTL", "MMCHS2_SD_SYSCTL", "MMCHS2_SD_STAT"}
        register += {"MMCHS2_SD_IE", "MMCHS2_SD_ISE", "MMCHS2_SD_AC12", "MMCHS2_SD_CAPA"}
        register += {"MMCHS2_SD_CUR_CAPA", "MMCHS2_SD_FE", "MMCHS2_SD_ADMAES", "MMCHS2_SD_ADMASAL"}
        register += {"MMCHS2_SD_ADMASAH", "MMCHS2_SD_REV"}
    }
    "McASP0 CFG" {
        collapse = true
        register = {"McASP0_REV", "McASP0_PFUNC", "McASP0_PDIR", "McASP0_PDOUT", "McASP0_PDIN"}
        register += {"McASP0_PDSET", "McASP0_PDCLR", "McASP0_GBLCTL", "McASP0_AMUTE"}
        register += {"McASP0_DLBCTL", "McASP0_DITCTL", "McASP0_RGBLCTL", "McASP0_RMASK"}
        register += {"McASP0_RFMT", "McASP0_AFSRCTL", "McASP0_ACLKRCTL", "McASP0_AHCLKRCTL"}
        register += {"McASP0_RTDM", "McASP0_RINTCTL", "McASP0_RSTAT", "McASP0_RSLOT"}
        register += {"McASP0_RCLKCHK", "McASP0_REVTCTL", "McASP0_XGBLCTL", "McASP0_XMASK"}
        register += {"McASP0_XFMT", "McASP0_AFSXCTL", "McASP0_ACLKXCTL", "McASP0_AHCLKXCTL"}
        register += {"McASP0_XTDM", "McASP0_XINTCTL", "McASP0_XSTAT", "McASP0_XSLOT"}
        register += {"McASP0_XCLKCHK", "McASP0_XEVTCTL", "McASP0_DITCSRA0", "McASP0_DITCSRA1"}
        register += {"McASP0_DITCSRA2", "McASP0_DITCSRA3", "McASP0_DITCSRA4", "McASP0_DITCSRA5"}
        register += {"McASP0_DITCSRB0", "McASP0_DITCSRB1", "McASP0_DITCSRB2", "McASP0_DITCSRB3"}
        register += {"McASP0_DITCSRB4", "McASP0_DITCSRB5", "McASP0_DITUDRA0", "McASP0_DITUDRA1"}
        register += {"McASP0_DITUDRA2", "McASP0_DITUDRA3", "McASP0_DITUDRA4", "McASP0_DITUDRA5"}
        register += {"McASP0_DITUDRB0", "McASP0_DITUDRB1", "McASP0_DITUDRB2", "McASP0_DITUDRB3"}
        register += {"McASP0_DITUDRB4", "McASP0_DITUDRB5", "McASP0_SRCTL0", "McASP0_SRCTL1"}
        register += {"McASP0_SRCTL2", "McASP0_SRCTL3", "McASP0_XBUF0", "McASP0_XBUF1"}
        register += {"McASP0_XBUF2", "McASP0_XBUF3", "McASP0_RBUF0", "McASP0_RBUF1"}
        register += {"McASP0_RBUF2", "McASP0_RBUF3", "McASP0_WFIFOCTL", "McASP0_WFIFOSTS"}
        register += {"McASP0_RFIFOCTL", "McASP0_RFIFOSTS"}
    }
    "McASP1 CFG" {
        collapse = true
        register = {"McASP1_REV", "McASP1_PFUNC", "McASP1_PDIR", "McASP1_PDOUT", "McASP1_PDIN"}
        register += {"McASP1_PDSET", "McASP1_PDCLR", "McASP1_GBLCTL", "McASP1_AMUTE"}
        register += {"McASP1_DLBCTL", "McASP1_DITCTL", "McASP1_RGBLCTL", "McASP1_RMASK"}
        register += {"McASP1_RFMT", "McASP1_AFSRCTL", "McASP1_ACLKRCTL", "McASP1_AHCLKRCTL"}
        register += {"McASP1_RTDM", "McASP1_RINTCTL", "McASP1_RSTAT", "McASP1_RSLOT"}
        register += {"McASP1_RCLKCHK", "McASP1_REVTCTL", "McASP1_XGBLCTL", "McASP1_XMASK"}
        register += {"McASP1_XFMT", "McASP1_AFSXCTL", "McASP1_ACLKXCTL", "McASP1_AHCLKXCTL"}
        register += {"McASP1_XTDM", "McASP1_XINTCTL", "McASP1_XSTAT", "McASP1_XSLOT"}
        register += {"McASP1_XCLKCHK", "McASP1_XEVTCTL", "McASP1_DITCSRA0", "McASP1_DITCSRA1"}
        register += {"McASP1_DITCSRA2", "McASP1_DITCSRA3", "McASP1_DITCSRA4", "McASP1_DITCSRA5"}
        register += {"McASP1_DITCSRB0", "McASP1_DITCSRB1", "McASP1_DITCSRB2", "McASP1_DITCSRB3"}
        register += {"McASP1_DITCSRB4", "McASP1_DITCSRB5", "McASP1_DITUDRA0", "McASP1_DITUDRA1"}
        register += {"McASP1_DITUDRA2", "McASP1_DITUDRA3", "McASP1_DITUDRA4", "McASP1_DITUDRA5"}
        register += {"McASP1_DITUDRB0", "McASP1_DITUDRB1", "McASP1_DITUDRB2", "McASP1_DITUDRB3"}
        register += {"McASP1_DITUDRB4", "McASP1_DITUDRB5", "McASP1_SRCTL0", "McASP1_SRCTL1"}
        register += {"McASP1_SRCTL2", "McASP1_SRCTL3", "McASP1_XBUF0", "McASP1_XBUF1"}
        register += {"McASP1_XBUF2", "McASP1_XBUF3", "McASP1_RBUF0", "McASP1_RBUF1"}
        register += {"McASP1_RBUF2", "McASP1_RBUF3", "McASP1_WFIFOCTL", "McASP1_WFIFOSTS"}
        register += {"McASP1_RFIFOCTL", "McASP1_RFIFOSTS"}
    }
    "McSPI0" {
        collapse = true
        register = {"McSPI0_REVISION", "McSPI0_SYSCONFIG", "McSPI0_SYSSTATUS", "McSPI0_IRQSTATUS"}
        register += {"McSPI0_IRQENABLE", "McSPI0_SYST", "McSPI0_MODULCTRL", "McSPI0_CH0CONF"}
        register += {"McSPI0_CH0STAT", "McSPI0_CH0CTRL", "McSPI0_TX0", "McSPI0_RX0"}
        register += {"McSPI0_CH1CONF", "McSPI0_CH1STAT", "McSPI0_CH1CTRL", "McSPI0_TX1"}
        register += {"McSPI0_RX1", "McSPI0_CH2CONF", "McSPI0_CH2STAT", "McSPI0_CH2CTRL"}
        register += {"McSPI0_TX2", "McSPI0_RX2", "McSPI0_CH3CONF", "McSPI0_CH3STAT"}
        register += {"McSPI0_CH3CTRL", "McSPI0_TX3", "McSPI0_RX3", "McSPI0_XFERLEVEL"}
        register += {"McSPI0_DAFTX", "McSPI0_DAFRX"}
    }
    "McSPI1" {
        collapse = true
        register = {"McSPI1_REVISION", "McSPI1_SYSCONFIG", "McSPI1_SYSSTATUS", "McSPI1_IRQSTATUS"}
        register += {"McSPI1_IRQENABLE", "McSPI1_SYST", "McSPI1_MODULCTRL", "McSPI1_CH0CONF"}
        register += {"McSPI1_CH0STAT", "McSPI1_CH0CTRL", "McSPI1_TX0", "McSPI1_RX0"}
        register += {"McSPI1_CH1CONF", "McSPI1_CH1STAT", "McSPI1_CH1CTRL", "McSPI1_TX1"}
        register += {"McSPI1_RX1", "McSPI1_CH2CONF", "McSPI1_CH2STAT", "McSPI1_CH2CTRL"}
        register += {"McSPI1_TX2", "McSPI1_RX2", "McSPI1_CH3CONF", "McSPI1_CH3STAT"}
        register += {"McSPI1_CH3CTRL", "McSPI1_TX3", "McSPI1_RX3", "McSPI1_XFERLEVEL"}
        register += {"McSPI1_DAFTX", "McSPI1_DAFRX"}
    }
    "PRM_CEFUSE" {
        collapse = true
        register = {"PM_CEFUSE_PWRSTCTRL", "PM_CEFUSE_PWRSTST"}
    }
    "PRM_DEVICE" {
        collapse = true
        register = {"PRM_RSTCTRL", "PRM_RSTTIME", "PRM_RSTST", "PRM_SRAM_COUNT", "PRM_LDO_SRAM_CORE_SETUP"}
        register += {"PRM_LDO_SRAM_CORE_CTRL", "PRM_LDO_SRAM_MPU_SETUP", "PRM_LDO_SRAM_MPU_CTRL"}
    }
    "PRM_GFX" {
        collapse = true
        register = {"PM_GFX_PWRSTCTRL", "RM_GFX_RSTCTRL", "PM_GFX_PWRSTST", "RM_GFX_RSTST"}
    }
    "PRM_IRQ" {
        collapse = true
        register = {"REVISION_PRM", "PRM_IRQSTATUS_MPU", "PRM_IRQENABLE_MPU", "PRM_IRQSTATUS_M3"}
        register += {"PRM_IRQENABLE_M3"}
    }
    "PRM_MPU" {
        collapse = true
        register = {"PM_MPU_PWRSTCTRL", "PM_MPU_PWRSTST", "RM_MPU_RSTST"}
    }
    "PRM_PER" {
        collapse = true
        register = {"RM_PER_RSTCTRL", "PM_PER_PWRSTST", "PM_PER_PWRSTCTRL"}
    }
    "PRM_RTC" {
        collapse = true
        register = {"PM_RTC_PWRSTCTRL", "PM_RTC_PWRSTST"}
    }
    "PRM_WKUP" {
        collapse = true
        register = {"RM_WKUP_RSTCTRL", "PM_WKUP_PWRSTCTRL", "PM_WKUP_PWRSTST", "RM_WKUP_RSTST"}
    }
    "PWMSS0" {
        collapse = true
        register = {"PWMSS0_IDVER", "PWMSS0_SYSCONFIG", "PWMSS0_CLKCONFIG", "PWMSS0_CLKSTATUS"}
    }
    "PWMSS1" {
        collapse = true
        register = {"PWMSS1_IDVER", "PWMSS1_SYSCONFIG", "PWMSS1_CLKCONFIG", "PWMSS1_CLKSTATUS"}
    }
    "PWMSS2" {
        collapse = true
        register = {"PWMSS2_IDVER", "PWMSS2_SYSCONFIG", "PWMSS2_CLKCONFIG", "PWMSS2_CLKSTATUS"}
    }
    "RTCSS" {
        collapse = true
        register = {"SECONDS_REG", "MINUTES_REG", "HOURS_REG", "DAYS_REG", "MONTHS_REG"}
        register += {"YEARS_REG", "WEEKS_REG", "ALARM_SECONDS_REG", "ALARM_MINUTES_REG"}
        register += {"ALARM_HOURS_REG", "ALARM_DAYS_REG", "ALARM_MONTHS_REG", "ALARM_YEARS_REG"}
        register += {"RTC_CTRL_REG", "RTC_STATUS_REG", "RTC_INTERRUPTS_REG", "RTC_COMP_LSB_REG"}
        register += {"RTC_COMP_MSB_REG", "RTC_OSC_REG", "RTC_SCRATCH0_REG", "RTC_SCRATCH1_REG"}
        register += {"RTC_SCRATCH2_REG", "KICK0R", "KICK1R", "RTC_REVISION", "RTC_SYSCONFIG"}
        register += {"RTC_IRQWAKEEN", "ALARM2_SECONDS_REG", "ALARM2_MINUTES_REG"}
        register += {"ALARM2_HOURS_REG", "ALARM2_DAYS_REG", "ALARM2_MONTHS_REG", "ALARM2_YEARS_REG"}
        register += {"RTC_PMIC", "RTC_DEBOUNCE"}
    }
    "Spinlock" {
        collapse = true
        register = {"Spinlock_REV", "Spinlock_SYSCONFIG", "Spinlock_SYSTATUS", "Spinlock_LOCK_REG_0"}
        register += {"Spinlock_LOCK_REG_1", "Spinlock_LOCK_REG_2", "Spinlock_LOCK_REG_3"}
        register += {"Spinlock_LOCK_REG_4", "Spinlock_LOCK_REG_5", "Spinlock_LOCK_REG_6"}
        register += {"Spinlock_LOCK_REG_7", "Spinlock_LOCK_REG_8", "Spinlock_LOCK_REG_9"}
        register += {"Spinlock_LOCK_REG_10", "Spinlock_LOCK_REG_11", "Spinlock_LOCK_REG_12"}
        register += {"Spinlock_LOCK_REG_13", "Spinlock_LOCK_REG_14", "Spinlock_LOCK_REG_15"}
        register += {"Spinlock_LOCK_REG_16", "Spinlock_LOCK_REG_17", "Spinlock_LOCK_REG_18"}
        register += {"Spinlock_LOCK_REG_19", "Spinlock_LOCK_REG_20", "Spinlock_LOCK_REG_21"}
        register += {"Spinlock_LOCK_REG_22", "Spinlock_LOCK_REG_23", "Spinlock_LOCK_REG_24"}
        register += {"Spinlock_LOCK_REG_25", "Spinlock_LOCK_REG_26", "Spinlock_LOCK_REG_27"}
        register += {"Spinlock_LOCK_REG_28", "Spinlock_LOCK_REG_29", "Spinlock_LOCK_REG_30"}
        register += {"Spinlock_LOCK_REG_31"}
    }
    "UART0" {
        collapse = true
        register = {"UART0_DLL", "UART0_RHR", "UART0_THR", "UART0_DLH", "UART0_IER"}
        register += {"UART0_EFR", "UART0_FCR", "UART0_IIR", "UART0_LCR", "UART0_ADDR1"}
        register += {"UART0_MCR", "UART0_XON1", "UART0_ADDR2", "UART0_LSR", "UART0_XON2"}
        register += {"UART0_MSR", "UART0_TCR", "UART0_XOFF1", "UART0_SPR", "UART0_TLR"}
        register += {"UART0_XOFF2", "UART0_MDR1", "UART0_MDR2", "UART0_SFLSR", "UART0_TXFLL"}
        register += {"UART0_RESUME", "UART0_TXFLH", "UART0_RXFLL", "UART0_SFREGL"}
        register += {"UART0_RXFLH", "UART0_SFREGH", "UART0_BLR", "UART0_UASR", "UART0_ACREG"}
        register += {"UART0_SCR", "UART0_SSR", "UART0_EBLR", "UART0_MVR", "UART0_SYSC"}
        register += {"UART0_SYSS", "UART0_WER", "UART0_CFPS", "UART0_RXFIFO", "UART0_TXFIFO"}
        register += {"UART0_IER2", "UART0_ISR2", "UART0_FREQ_SEL", "UART0_MDR3", "UART0_TXDMA"}
    }
    "UART1" {
        collapse = true
        register = {"UART1_DLL", "UART1_RHR", "UART1_THR", "UART1_DLH", "UART1_IER"}
        register += {"UART1_EFR", "UART1_FCR", "UART1_IIR", "UART1_LCR", "UART1_ADDR1"}
        register += {"UART1_MCR", "UART1_XON1", "UART1_ADDR2", "UART1_LSR", "UART1_XON2"}
        register += {"UART1_MSR", "UART1_TCR", "UART1_XOFF1", "UART1_SPR", "UART1_TLR"}
        register += {"UART1_XOFF2", "UART1_MDR1", "UART1_MDR2", "UART1_SFLSR", "UART1_TXFLL"}
        register += {"UART1_RESUME", "UART1_TXFLH", "UART1_RXFLL", "UART1_SFREGL"}
        register += {"UART1_RXFLH", "UART1_SFREGH", "UART1_BLR", "UART1_UASR", "UART1_ACREG"}
        register += {"UART1_SCR", "UART1_SSR", "UART1_EBLR", "UART1_MVR", "UART1_SYSC"}
        register += {"UART1_SYSS", "UART1_WER", "UART1_CFPS", "UART1_RXFIFO", "UART1_TXFIFO"}
        register += {"UART1_IER2", "UART1_ISR2", "UART1_FREQ_SEL", "UART1_MDR3", "UART1_TXDMA"}
    }
    "UART2" {
        collapse = true
        register = {"UART2_DLL", "UART2_RHR", "UART2_THR", "UART2_DLH", "UART2_IER"}
        register += {"UART2_EFR", "UART2_FCR", "UART2_IIR", "UART2_LCR", "UART2_ADDR1"}
        register += {"UART2_MCR", "UART2_XON1", "UART2_ADDR2", "UART2_LSR", "UART2_XON2"}
        register += {"UART2_MSR", "UART2_TCR", "UART2_XOFF1", "UART2_SPR", "UART2_TLR"}
        register += {"UART2_XOFF2", "UART2_MDR1", "UART2_MDR2", "UART2_SFLSR", "UART2_TXFLL"}
        register += {"UART2_RESUME", "UART2_TXFLH", "UART2_RXFLL", "UART2_SFREGL"}
        register += {"UART2_RXFLH", "UART2_SFREGH", "UART2_BLR", "UART2_UASR", "UART2_ACREG"}
        register += {"UART2_SCR", "UART2_SSR", "UART2_EBLR", "UART2_MVR", "UART2_SYSC"}
        register += {"UART2_SYSS", "UART2_WER", "UART2_CFPS", "UART2_RXFIFO", "UART2_TXFIFO"}
        register += {"UART2_IER2", "UART2_ISR2", "UART2_FREQ_SEL", "UART2_MDR3", "UART2_TXDMA"}
    }
    "UART3" {
        collapse = true
        register = {"UART3_DLL", "UART3_RHR", "UART3_THR", "UART3_DLH", "UART3_IER"}
        register += {"UART3_EFR", "UART3_FCR", "UART3_IIR", "UART3_LCR", "UART3_ADDR1"}
        register += {"UART3_MCR", "UART3_XON1", "UART3_ADDR2", "UART3_LSR", "UART3_XON2"}
        register += {"UART3_MSR", "UART3_TCR", "UART3_XOFF1", "UART3_SPR", "UART3_TLR"}
        register += {"UART3_XOFF2", "UART3_MDR1", "UART3_MDR2", "UART3_SFLSR", "UART3_TXFLL"}
        register += {"UART3_RESUME", "UART3_TXFLH", "UART3_RXFLL", "UART3_SFREGL"}
        register += {"UART3_RXFLH", "UART3_SFREGH", "UART3_BLR", "UART3_UASR", "UART3_ACREG"}
        register += {"UART3_SCR", "UART3_SSR", "UART3_EBLR", "UART3_MVR", "UART3_SYSC"}
        register += {"UART3_SYSS", "UART3_WER", "UART3_CFPS", "UART3_RXFIFO", "UART3_TXFIFO"}
        register += {"UART3_IER2", "UART3_ISR2", "UART3_FREQ_SEL", "UART3_MDR3", "UART3_TXDMA"}
    }
    "UART4" {
        collapse = true
        register = {"UART4_DLL", "UART4_RHR", "UART4_THR", "UART4_DLH", "UART4_IER"}
        register += {"UART4_EFR", "UART4_FCR", "UART4_IIR", "UART4_LCR", "UART4_ADDR1"}
        register += {"UART4_MCR", "UART4_XON1", "UART4_ADDR2", "UART4_LSR", "UART4_XON2"}
        register += {"UART4_MSR", "UART4_TCR", "UART4_XOFF1", "UART4_SPR", "UART4_TLR"}
        register += {"UART4_XOFF2", "UART4_MDR1", "UART4_MDR2", "UART4_SFLSR", "UART4_TXFLL"}
        register += {"UART4_RESUME", "UART4_TXFLH", "UART4_RXFLL", "UART4_SFREGL"}
        register += {"UART4_RXFLH", "UART4_SFREGH", "UART4_BLR", "UART4_UASR", "UART4_ACREG"}
        register += {"UART4_SCR", "UART4_SSR", "UART4_EBLR", "UART4_MVR", "UART4_SYSC"}
        register += {"UART4_SYSS", "UART4_WER", "UART4_CFPS", "UART4_RXFIFO", "UART4_TXFIFO"}
        register += {"UART4_IER2", "UART4_ISR2", "UART4_FREQ_SEL", "UART4_MDR3", "UART4_TXDMA"}
    }
    "UART5" {
        collapse = true
        register = {"UART5_DLL", "UART5_RHR", "UART5_THR", "UART5_DLH", "UART5_IER"}
        register += {"UART5_EFR", "UART5_FCR", "UART5_IIR", "UART5_LCR", "UART5_ADDR1"}
        register += {"UART5_MCR", "UART5_XON1", "UART5_ADDR2", "UART5_LSR", "UART5_XON2"}
        register += {"UART5_MSR", "UART5_TCR", "UART5_XOFF1", "UART5_SPR", "UART5_TLR"}
        register += {"UART5_XOFF2", "UART5_MDR1", "UART5_MDR2", "UART5_SFLSR", "UART5_TXFLL"}
        register += {"UART5_RESUME", "UART5_TXFLH", "UART5_RXFLL", "UART5_SFREGL"}
        register += {"UART5_RXFLH", "UART5_SFREGH", "UART5_BLR", "UART5_UASR", "UART5_ACREG"}
        register += {"UART5_SCR", "UART5_SSR", "UART5_EBLR", "UART5_MVR", "UART5_SYSC"}
        register += {"UART5_SYSS", "UART5_WER", "UART5_CFPS", "UART5_RXFIFO", "UART5_TXFIFO"}
        register += {"UART5_IER2", "UART5_ISR2", "UART5_FREQ_SEL", "UART5_MDR3", "UART5_TXDMA"}
    }
    "USB0" {
        collapse = true
        register = {"USB0REV", "USB0CTRL", "USB0STAT", "USB0IRQMSTAT", "USB0IRQSTATRAW0"}
        register += {"USB0IRQSTATRAW1", "USB0IRQSTAT0", "USB0IRQSTAT1", "USB0IRQENABLESET0"}
        register += {"USB0IRQENABLESET1", "USB0IRQENABLECLR0", "USB0IRQENABLECLR1"}
        register += {"USB0TXMODE", "USB0RXMODE", "USB0GENRNDISEP1", "USB0GENRNDISEP2"}
        register += {"USB0GENRNDISEP3", "USB0GENRNDISEP4", "USB0GENRNDISEP5", "USB0GENRNDISEP6"}
        register += {"USB0GENRNDISEP7", "USB0GENRNDISEP8", "USB0GENRNDISEP9", "USB0GENRNDISEP10"}
        register += {"USB0GENRNDISEP11", "USB0GENRNDISEP12", "USB0GENRNDISEP13", "USB0GENRNDISEP14"}
        register += {"USB0GENRNDISEP15", "USB0AUTOREQ", "USB0SRPFIXTIME", "USB0_TDOWN"}
        register += {"USB0UTMI", "USB0MGCUTMILB", "USB0MODE"}
    }
    "USB0_PHY" {
        collapse = true
        register = {"USB0_PHY_Termination_control", "USB0_PHY_RX_CALIB", "USB0_PHY_DLLHS_2"}
        register += {"USB0_PHY_RX_TEST_2", "USB0_PHY_CHRG_DET", "USB0_PHY_PWR_CNTL"}
        register += {"USB0_PHY_UTMI_INTERFACE_CNTL_1", "USB0_PHY_UTMI_INTERFACE_CNTL_2"}
        register += {"USB0_PHY_BIST", "USB0_PHY_BIST_CRC", "USB0_PHY_CDR_BIST2", "USB0_PHY_GPIO"}
        register += {"USB0_PHY_DLLHS", "USB0_PHY_USB2PHYCM_TRIM", "USB0_PHY_USB2PHYCM_CONFIG"}
        register += {"USB0_PHY_USBOTG", "USB0_PHY_AD_INTERFACE_REG1", "USB0_PHY_AD_INTERFACE_REG2"}
        register += {"USB0_PHY_AD_INTERFACE_REG3", "USB0_PHY_ANA_CONFIG1", "USB0_PHY_ANA_CONFIG2"}
        register += {"USB0_PHY_RX_DEBUG_REG"}
    }
    "USB1" {
        collapse = true
        register = {"USB1REV", "USB1CTRL", "USB1STAT", "USB1IRQMSTAT", "USB1IRQSTATRAW0"}
        register += {"USB1IRQSTATRAW1", "USB1IRQSTAT0", "USB1IRQSTAT1", "USB1IRQENABLESET0"}
        register += {"USB1IRQENABLESET1", "USB1IRQENABLECLR0", "USB1IRQENABLECLR1"}
        register += {"USB1TXMODE", "USB1RXMODE", "USB1GENRNDISEP1", "USB1GENRNDISEP2"}
        register += {"USB1GENRNDISEP3", "USB1GENRNDISEP4", "USB1GENRNDISEP5", "USB1GENRNDISEP6"}
        register += {"USB1GENRNDISEP7", "USB1GENRNDISEP8", "USB1GENRNDISEP9", "USB1GENRNDISEP10"}
        register += {"USB1GENRNDISEP11", "USB1GENRNDISEP12", "USB1GENRNDISEP13", "USB1GENRNDISEP14"}
        register += {"USB1GENRNDISEP15", "USB1AUTOREQ", "USB1SRPFIXTIME", "USB1TDOWN"}
        register += {"USB1UTMI", "USB1UTMILB", "USB1MODE"}
    }
    "USB1_PHY" {
        collapse = true
        register = {"USB1_PHY_Termination_control", "USB1_PHY_RX_CALIB", "USB1_PHY_DLLHS_2"}
        register += {"USB1_PHY_RX_TEST_2", "USB1_PHY_CHRG_DET", "USB1_PHY_PWR_CNTL"}
        register += {"USB1_PHY_UTMI_INTERFACE_CNTL_1", "USB1_PHY_UTMI_INTERFACE_CNTL_2"}
        register += {"USB1_PHY_BIST", "USB1_PHY_BIST_CRC", "USB1_PHY_CDR_BIST2", "USB1_PHY_GPIO"}
        register += {"USB1_PHY_DLLHS", "USB1_PHY_USB2PHYCM_TRIM", "USB1_PHY_USB2PHYCM_CONFIG"}
        register += {"USB1_PHY_USBOTG", "USB1_PHY_AD_INTERFACE_REG1", "USB1_PHY_AD_INTERFACE_REG2"}
        register += {"USB1_PHY_AD_INTERFACE_REG3", "USB1_PHY_ANA_CONFIG1", "USB1_PHY_ANA_CONFIG2"}
        register += {"USB1_PHY_RX_DEBUG_REG"}
    }
    "USBSS" {
        collapse = true
        register = {"USBSS_REVREG", "USBSS_SYSCONFIG", "USBSS_IRQSTATRAW", "USBSS_IRQSTAT"}
        register += {"USBSS_IRQENABLER", "USBSS_IRQCLEARR", "USBSS_IRQDMATHOLDTX00"}
        register += {"USBSS_IRQDMATHOLDTX01", "USBSS_IRQDMATHOLDTX02", "USBSS_IRQDMATHOLDTX03"}
        register += {"USBSS_IRQDMATHOLDRX00", "USBSS_IRQDMATHOLDRX01", "USBSS_IRQDMATHOLDRX02"}
        register += {"USBSS_IRQDMATHOLDRX03", "USBSS_IRQDMATHOLDTX10", "USBSS_IRQDMATHOLDTX11"}
        register += {"USBSS_IRQDMATHOLDTX12", "USBSS_IRQDMATHOLDTX13", "USBSS_IRQDMATHOLDRX10"}
        register += {"USBSS_IRQDMATHOLDRX11", "USBSS_IRQDMATHOLDRX12", "USBSS_IRQDMATHOLDRX13"}
        register += {"USBSS_IRQDMAENABLE0", "USBSS_IRQDMAENABLE1", "USBSS_IRQFRAMETHOLDTX00"}
        register += {"USBSS_IRQFRAMETHOLDTX01", "USBSS_IRQFRAMETHOLDTX02", "USBSS_IRQFRAMETHOLDTX03"}
        register += {"USBSS_IRQFRAMETHOLDRX00", "USBSS_IRQFRAMETHOLDRX01", "USBSS_IRQFRAMETHOLDRX02"}
        register += {"USBSS_IRQFRAMETHOLDRX03", "USBSS_IRQFRAMETHOLDTX10", "USBSS_IRQFRAMETHOLDTX11"}
        register += {"USBSS_IRQFRAMETHOLDTX12", "USBSS_IRQFRAMETHOLDTX13", "USBSS_IRQFRAMETHOLDRX10"}
        register += {"USBSS_IRQFRAMETHOLDRX11", "USBSS_IRQFRAMETHOLDRX12", "USBSS_IRQFRAMETHOLDRX13"}
        register += {"USBSS_IRQFRAMEENABLE0", "USBSS_IRQFRAMEENABLE1"}
    }
    "USB_CPPI_DMA_CTRL" {
        collapse = true
        register = {"DMAREVID", "TDFDQ", "DMAEMU", "TXGCR0", "RXGCR0", "RXHPCRA0"}
        register += {"RXHPCRB0", "TXGCR1", "RXGCR1", "RXHPCRA1", "RXHPCRB1", "TXGCR2"}
        register += {"RXGCR2", "RXHPCRA2", "RXHPCRB2", "TXGCR3", "RXGCR3", "RXHPCRA3"}
        register += {"RXHPCRB3", "TXGCR4", "RXGCR4", "RXHPCRA4", "RXHPCRB4", "TXGCR5"}
        register += {"RXGCR5", "RXHPCRA5", "RXHPCRB5", "TXGCR6", "RXGCR6", "RXHPCRA6"}
        register += {"RXHPCRB6", "TXGCR7", "RXGCR7", "RXHPCRA7", "RXHPCRB7", "TXGCR8"}
        register += {"RXGCR8", "RXHPCRA8", "RXHPCRB8", "TXGCR9", "RXGCR9", "RXHPCRA9"}
        register += {"RXHPCRB9", "TXGCR10", "RXGCR10", "RXHPCRA10", "RXHPCRB10", "TXGCR11"}
        register += {"RXGCR11", "RXHPCRA11", "RXHPCRB11", "TXGCR12", "RXGCR12", "RXHPCRA12"}
        register += {"RXHPCRB12", "TXGCR13", "RXGCR13", "RXHPCRA13", "RXHPCRB13"}
        register += {"TXGCR14", "RXGCR14", "RXHPCRA14", "RXHPCRB14", "TXGCR15", "RXGCR15"}
        register += {"RXHPCRA15", "RXHPCRB15", "TXGCR16", "RXGCR16", "RXHPCRA16"}
        register += {"RXHPCRB16", "TXGCR17", "RXGCR17", "RXHPCRA17", "RXHPCRB17"}
        register += {"TXGCR18", "RXGCR18", "RXHPCRA18", "RXHPCRB18", "TXGCR19", "RXGCR19"}
        register += {"RXHPCRA19", "RXHPCRB19", "TXGCR20", "RXGCR20", "RXHPCRA20"}
        register += {"RXHPCRB20", "TXGCR21", "RXGCR21", "RXHPCRA21", "RXHPCRB21"}
        register += {"TXGCR22", "RXGCR22", "RXHPCRA22", "RXHPCRB22", "TXGCR23", "RXGCR23"}
        register += {"RXHPCRA23", "RXHPCRB23", "TXGCR24", "RXGCR24", "RXHPCRA24"}
        register += {"RXHPCRB24", "TXGCR25", "RXGCR25", "RXHPCRA25", "RXHPCRB25"}
        register += {"TXGCR26", "RXGCR26", "RXHPCRA26", "RXHPCRB26", "TXGCR27", "RXGCR27"}
        register += {"RXHPCRA27", "RXHPCRB27", "TXGCR28", "RXGCR28", "RXHPCRA28"}
        register += {"RXHPCRB28", "TXGCR29", "RXGCR29", "RXHPCRA29", "RXHPCRB29"}
    }
    "USB_CPPI_DMA_SCH" {
        collapse = true
        register = {"DMA_SCHED_CTRL", "WORD0", "WORD1", "WORD2", "WORD5", "WORD6"}
        register += {"WORD7", "WORD8", "WORD9", "WORD10", "WORD11", "WORD12", "WORD13"}
        register += {"WORD14", "WORD15", "WORD16", "WORD17", "WORD18", "WORD19", "WORD20"}
        register += {"WORD21", "WORD22", "WORD23", "WORD24", "WORD25", "WORD26", "WORD27"}
        register += {"WORD28", "WORD29", "WORD30", "WORD31", "WORD32", "WORD33", "WORD34"}
        register += {"WORD35", "WORD36", "WORD37", "WORD38", "WORD39", "WORD40", "WORD41"}
        register += {"WORD42", "WORD43", "WORD44", "WORD45", "WORD46", "WORD47", "WORD48"}
        register += {"WORD49", "WORD50", "WORD51", "WORD52", "WORD53", "WORD54", "WORD55"}
        register += {"WORD56", "WORD57", "WORD58", "WORD59", "WORD60", "WORD61", "WORD62"}
        register += {"WORD63"}
    }
    "USB_Queue_MGR" {
        collapse = true
        register = {"QMGRREVID", "QMGRRST", "FDBSC0", "FDBSC1", "FDBSC2", "FDBSC3"}
        register += {"FDBSC4", "FDBSC5", "FDBSC6", "FDBSC7", "LRAM0BASE", "LRAM0SIZE"}
        register += {"LRAM1BASE", "PEND0", "PEND1", "PEND2", "PEND3", "PEND4", "QMEMRBASE0"}
        register += {"QMEMCTRL0", "QMEMRBASE1", "QMEMCTRL1", "QMEMRBASE2", "QMEMCTRL2"}
        register += {"QMEMRBASE3", "QMEMCTRL3", "QMEMRBASE4", "QMEMCTRL4", "QMEMRBASE5"}
        register += {"QMEMCTRL5", "QMEMRBASE6", "QMEMCTRL6", "QMEMRBASE7", "QMEMCTRL7"}
        register += {"QUEUE_0_A", "QUEUE_0_B", "QUEUE_0_C", "QUEUE_0_D", "QUEUE_1_A"}
        register += {"QUEUE_1_B", "QUEUE_1_C", "QUEUE_1_D", "QUEUE_2_A", "QUEUE_2_B"}
        register += {"QUEUE_2_C", "QUEUE_2_D", "QUEUE_3_A", "QUEUE_3_B", "QUEUE_3_C"}
        register += {"QUEUE_3_D", "QUEUE_4_A", "QUEUE_4_B", "QUEUE_4_C", "QUEUE_4_D"}
        register += {"QUEUE_5_A", "QUEUE_5_B", "QUEUE_5_C", "QUEUE_5_D", "QUEUE_6_A"}
        register += {"QUEUE_6_B", "QUEUE_6_C", "QUEUE_6_D", "QUEUE_7_A", "QUEUE_7_B"}
        register += {"QUEUE_7_C", "QUEUE_7_D", "QUEUE_8_A", "QUEUE_8_B", "QUEUE_8_C"}
        register += {"QUEUE_8_D", "QUEUE_9_A", "QUEUE_9_B", "QUEUE_9_C", "QUEUE_9_D"}
        register += {"QUEUE_10_A", "QUEUE_10_B", "QUEUE_10_C", "QUEUE_10_D", "QUEUE_11_A"}
        register += {"QUEUE_11_B", "QUEUE_11_C", "QUEUE_11_D", "QUEUE_12_A", "QUEUE_12_B"}
        register += {"QUEUE_12_C", "QUEUE_12_D", "QUEUE_13_A", "QUEUE_13_B", "QUEUE_13_C"}
        register += {"QUEUE_13_D", "QUEUE_14_A", "QUEUE_14_B", "QUEUE_14_C", "QUEUE_14_D"}
        register += {"QUEUE_15_A", "QUEUE_15_B", "QUEUE_15_C", "QUEUE_15_D", "QUEUE_16_A"}
        register += {"QUEUE_16_B", "QUEUE_16_C", "QUEUE_16_D", "QUEUE_17_A", "QUEUE_17_B"}
        register += {"QUEUE_17_C", "QUEUE_17_D", "QUEUE_18_A", "QUEUE_18_B", "QUEUE_18_C"}
        register += {"QUEUE_18_D", "QUEUE_19_A", "QUEUE_19_B", "QUEUE_19_C", "QUEUE_19_D"}
        register += {"QUEUE_20_A", "QUEUE_20_B", "QUEUE_20_C", "QUEUE_20_D", "QUEUE_21_A"}
        register += {"QUEUE_21_B", "QUEUE_21_C", "QUEUE_21_D", "QUEUE_22_A", "QUEUE_22_B"}
        register += {"QUEUE_22_C", "QUEUE_22_D", "QUEUE_23_A", "QUEUE_23_B", "QUEUE_23_C"}
        register += {"QUEUE_23_D", "QUEUE_24_A", "QUEUE_24_B", "QUEUE_24_C", "QUEUE_24_D"}
        register += {"QUEUE_25_A", "QUEUE_25_B", "QUEUE_25_C", "QUEUE_25_D", "QUEUE_26_A"}
        register += {"QUEUE_26_B", "QUEUE_26_C", "QUEUE_26_D", "QUEUE_27_A", "QUEUE_27_B"}
        register += {"QUEUE_27_C", "QUEUE_27_D", "QUEUE_28_A", "QUEUE_28_B", "QUEUE_28_C"}
        register += {"QUEUE_28_D", "QUEUE_29_A", "QUEUE_29_B", "QUEUE_29_C", "QUEUE_29_D"}
        register += {"QUEUE_30_A", "QUEUE_30_B", "QUEUE_30_C", "QUEUE_30_D", "QUEUE_31_A"}
        register += {"QUEUE_31_B", "QUEUE_31_C", "QUEUE_31_D", "QUEUE_32_A", "QUEUE_32_B"}
        register += {"QUEUE_32_C", "QUEUE_32_D", "QUEUE_33_A", "QUEUE_33_B", "QUEUE_33_C"}
        register += {"QUEUE_33_D", "QUEUE_34_A", "QUEUE_34_B", "QUEUE_34_C", "QUEUE_34_D"}
        register += {"QUEUE_35_A", "QUEUE_35_B", "QUEUE_35_C", "QUEUE_35_D", "QUEUE_36_A"}
        register += {"QUEUE_36_B", "QUEUE_36_C", "QUEUE_36_D", "QUEUE_37_A", "QUEUE_37_B"}
        register += {"QUEUE_37_C", "QUEUE_37_D", "QUEUE_38_A", "QUEUE_38_B", "QUEUE_38_C"}
        register += {"QUEUE_38_D", "QUEUE_39_A", "QUEUE_39_B", "QUEUE_39_C", "QUEUE_39_D"}
        register += {"QUEUE_40_A", "QUEUE_40_B", "QUEUE_40_C", "QUEUE_40_D", "QUEUE_41_A"}
        register += {"QUEUE_41_B", "QUEUE_41_C", "QUEUE_41_D", "QUEUE_42_A", "QUEUE_42_B"}
        register += {"QUEUE_42_C", "QUEUE_42_D", "QUEUE_43_A", "QUEUE_43_B", "QUEUE_43_C"}
        register += {"QUEUE_43_D", "QUEUE_44_A", "QUEUE_44_B", "QUEUE_44_C", "QUEUE_44_D"}
        register += {"QUEUE_45_A", "QUEUE_45_B", "QUEUE_45_C", "QUEUE_45_D", "QUEUE_46_A"}
        register += {"QUEUE_46_B", "QUEUE_46_C", "QUEUE_46_D", "QUEUE_47_A", "QUEUE_47_B"}
        register += {"QUEUE_47_C", "QUEUE_47_D", "QUEUE_48_A", "QUEUE_48_B", "QUEUE_48_C"}
        register += {"QUEUE_48_D", "QUEUE_49_A", "QUEUE_49_B", "QUEUE_49_C", "QUEUE_49_D"}
        register += {"QUEUE_50_A", "QUEUE_50_B", "QUEUE_50_C", "QUEUE_50_D", "QUEUE_51_A"}
        register += {"QUEUE_51_B", "QUEUE_51_C", "QUEUE_51_D", "QUEUE_52_A", "QUEUE_52_B"}
        register += {"QUEUE_52_C", "QUEUE_52_D", "QUEUE_53_A", "QUEUE_53_B", "QUEUE_53_C"}
        register += {"QUEUE_53_D", "QUEUE_54_A", "QUEUE_54_B", "QUEUE_54_C", "QUEUE_54_D"}
        register += {"QUEUE_55_A", "QUEUE_55_B", "QUEUE_55_C", "QUEUE_55_D", "QUEUE_56_A"}
        register += {"QUEUE_56_B", "QUEUE_56_C", "QUEUE_56_D", "QUEUE_57_A", "QUEUE_57_B"}
        register += {"QUEUE_57_C", "QUEUE_57_D", "QUEUE_58_A", "QUEUE_58_B", "QUEUE_58_C"}
        register += {"QUEUE_58_D", "QUEUE_59_A", "QUEUE_59_B", "QUEUE_59_C", "QUEUE_59_D"}
        register += {"QUEUE_60_A", "QUEUE_60_B", "QUEUE_60_C", "QUEUE_60_D", "QUEUE_61_A"}
        register += {"QUEUE_61_B", "QUEUE_61_C", "QUEUE_61_D", "QUEUE_62_A", "QUEUE_62_B"}
        register += {"QUEUE_62_C", "QUEUE_62_D", "QUEUE_63_A", "QUEUE_63_B", "QUEUE_63_C"}
        register += {"QUEUE_63_D", "QUEUE_64_A", "QUEUE_64_B", "QUEUE_64_C", "QUEUE_64_D"}
        register += {"QUEUE_65_A", "QUEUE_65_B", "QUEUE_65_C", "QUEUE_65_D", "QUEUE_66_A"}
        register += {"QUEUE_66_B", "QUEUE_66_C", "QUEUE_66_D", "QUEUE_67_A", "QUEUE_67_B"}
        register += {"QUEUE_67_C", "QUEUE_67_D", "QUEUE_68_A", "QUEUE_68_B", "QUEUE_68_C"}
        register += {"QUEUE_68_D", "QUEUE_69_A", "QUEUE_69_B", "QUEUE_69_C", "QUEUE_69_D"}
        register += {"QUEUE_70_A", "QUEUE_70_B", "QUEUE_70_C", "QUEUE_70_D", "QUEUE_71_A"}
        register += {"QUEUE_71_B", "QUEUE_71_C", "QUEUE_71_D", "QUEUE_72_A", "QUEUE_72_B"}
        register += {"QUEUE_72_C", "QUEUE_72_D", "QUEUE_73_A", "QUEUE_73_B", "QUEUE_73_C"}
        register += {"QUEUE_73_D", "QUEUE_74_A", "QUEUE_74_B", "QUEUE_74_C", "QUEUE_74_D"}
        register += {"QUEUE_75_A", "QUEUE_75_B", "QUEUE_75_C", "QUEUE_75_D", "QUEUE_76_A"}
        register += {"QUEUE_76_B", "QUEUE_76_C", "QUEUE_76_D", "QUEUE_77_A", "QUEUE_77_B"}
        register += {"QUEUE_77_C", "QUEUE_77_D", "QUEUE_78_A", "QUEUE_78_B", "QUEUE_78_C"}
        register += {"QUEUE_78_D", "QUEUE_79_A", "QUEUE_79_B", "QUEUE_79_C", "QUEUE_79_D"}
        register += {"QUEUE_80_A", "QUEUE_80_B", "QUEUE_80_C", "QUEUE_80_D", "QUEUE_81_A"}
        register += {"QUEUE_81_B", "QUEUE_81_C", "QUEUE_81_D", "QUEUE_82_A", "QUEUE_82_B"}
        register += {"QUEUE_82_C", "QUEUE_82_D", "QUEUE_83_A", "QUEUE_83_B", "QUEUE_83_C"}
        register += {"QUEUE_83_D", "QUEUE_84_A", "QUEUE_84_B", "QUEUE_84_C", "QUEUE_84_D"}
        register += {"QUEUE_85_A", "QUEUE_85_B", "QUEUE_85_C", "QUEUE_85_D", "QUEUE_86_A"}
        register += {"QUEUE_86_B", "QUEUE_86_C", "QUEUE_86_D", "QUEUE_87_A", "QUEUE_87_B"}
        register += {"QUEUE_87_C", "QUEUE_87_D", "QUEUE_88_A", "QUEUE_88_B", "QUEUE_88_C"}
        register += {"QUEUE_88_D", "QUEUE_89_A", "QUEUE_89_B", "QUEUE_89_C", "QUEUE_89_D"}
        register += {"QUEUE_90_A", "QUEUE_90_B", "QUEUE_90_C", "QUEUE_90_D", "QUEUE_91_A"}
        register += {"QUEUE_91_B", "QUEUE_91_C", "QUEUE_91_D", "QUEUE_92_A", "QUEUE_92_B"}
        register += {"QUEUE_92_C", "QUEUE_92_D", "QUEUE_93_A", "QUEUE_93_B", "QUEUE_93_C"}
        register += {"QUEUE_93_D", "QUEUE_94_A", "QUEUE_94_B", "QUEUE_94_C", "QUEUE_94_D"}
        register += {"QUEUE_95_A", "QUEUE_95_B", "QUEUE_95_C", "QUEUE_95_D", "QUEUE_96_A"}
        register += {"QUEUE_96_B", "QUEUE_96_C", "QUEUE_96_D", "QUEUE_97_A", "QUEUE_97_B"}
        register += {"QUEUE_97_C", "QUEUE_97_D", "QUEUE_98_A", "QUEUE_98_B", "QUEUE_98_C"}
        register += {"QUEUE_98_D", "QUEUE_99_A", "QUEUE_99_B", "QUEUE_99_C", "QUEUE_99_D"}
        register += {"QUEUE_100_A", "QUEUE_100_B", "QUEUE_100_C", "QUEUE_100_D", "QUEUE_101_A"}
        register += {"QUEUE_101_B", "QUEUE_101_C", "QUEUE_101_D", "QUEUE_102_A", "QUEUE_102_B"}
        register += {"QUEUE_102_C", "QUEUE_102_D", "QUEUE_103_A", "QUEUE_103_B", "QUEUE_103_C"}
        register += {"QUEUE_103_D", "QUEUE_104_A", "QUEUE_104_B", "QUEUE_104_C", "QUEUE_104_D"}
        register += {"QUEUE_105_A", "QUEUE_105_B", "QUEUE_105_C", "QUEUE_105_D", "QUEUE_106_A"}
        register += {"QUEUE_106_B", "QUEUE_106_C", "QUEUE_106_D", "QUEUE_107_A", "QUEUE_107_B"}
        register += {"QUEUE_107_C", "QUEUE_107_D", "QUEUE_108_A", "QUEUE_108_B", "QUEUE_108_C"}
        register += {"QUEUE_108_D", "QUEUE_109_A", "QUEUE_109_B", "QUEUE_109_C", "QUEUE_109_D"}
        register += {"QUEUE_110_A", "QUEUE_110_B", "QUEUE_110_C", "QUEUE_110_D", "QUEUE_111_A"}
        register += {"QUEUE_111_B", "QUEUE_111_C", "QUEUE_111_D", "QUEUE_112_A", "QUEUE_112_B"}
        register += {"QUEUE_112_C", "QUEUE_112_D", "QUEUE_113_A", "QUEUE_113_B", "QUEUE_113_C"}
        register += {"QUEUE_113_D", "QUEUE_114_A", "QUEUE_114_B", "QUEUE_114_C", "QUEUE_114_D"}
        register += {"QUEUE_115_A", "QUEUE_115_B", "QUEUE_115_C", "QUEUE_115_D", "QUEUE_116_A"}
        register += {"QUEUE_116_B", "QUEUE_116_C", "QUEUE_116_D", "QUEUE_117_A", "QUEUE_117_B"}
        register += {"QUEUE_117_C", "QUEUE_117_D", "QUEUE_118_A", "QUEUE_118_B", "QUEUE_118_C"}
        register += {"QUEUE_118_D", "QUEUE_119_A", "QUEUE_119_B", "QUEUE_119_C", "QUEUE_119_D"}
        register += {"QUEUE_120_A", "QUEUE_120_B", "QUEUE_120_C", "QUEUE_120_D", "QUEUE_121_A"}
        register += {"QUEUE_121_B", "QUEUE_121_C", "QUEUE_121_D", "QUEUE_122_A", "QUEUE_122_B"}
        register += {"QUEUE_122_C", "QUEUE_122_D", "QUEUE_123_A", "QUEUE_123_B", "QUEUE_123_C"}
        register += {"QUEUE_123_D", "QUEUE_124_A", "QUEUE_124_B", "QUEUE_124_C", "QUEUE_124_D"}
        register += {"QUEUE_125_A", "QUEUE_125_B", "QUEUE_125_C", "QUEUE_125_D", "QUEUE_126_A"}
        register += {"QUEUE_126_B", "QUEUE_126_C", "QUEUE_126_D", "QUEUE_127_A", "QUEUE_127_B"}
        register += {"QUEUE_127_C", "QUEUE_127_D", "QUEUE_128_A", "QUEUE_128_B", "QUEUE_128_C"}
        register += {"QUEUE_128_D", "QUEUE_129_A", "QUEUE_129_B", "QUEUE_129_C", "QUEUE_129_D"}
        register += {"QUEUE_130_A", "QUEUE_130_B", "QUEUE_130_C", "QUEUE_130_D", "QUEUE_131_A"}
        register += {"QUEUE_131_B", "QUEUE_131_C", "QUEUE_131_D", "QUEUE_132_A", "QUEUE_132_B"}
        register += {"QUEUE_132_C", "QUEUE_132_D", "QUEUE_133_A", "QUEUE_133_B", "QUEUE_133_C"}
        register += {"QUEUE_133_D", "QUEUE_134_A", "QUEUE_134_B", "QUEUE_134_C", "QUEUE_134_D"}
        register += {"QUEUE_135_A", "QUEUE_135_B", "QUEUE_135_C", "QUEUE_135_D", "QUEUE_136_A"}
        register += {"QUEUE_136_B", "QUEUE_136_C", "QUEUE_136_D", "QUEUE_137_A", "QUEUE_137_B"}
        register += {"QUEUE_137_C", "QUEUE_137_D", "QUEUE_138_A", "QUEUE_138_B", "QUEUE_138_C"}
        register += {"QUEUE_138_D", "QUEUE_139_A", "QUEUE_139_B", "QUEUE_139_C", "QUEUE_139_D"}
        register += {"QUEUE_140_A", "QUEUE_140_B", "QUEUE_140_C", "QUEUE_140_D", "QUEUE_141_A"}
        register += {"QUEUE_141_B", "QUEUE_141_C", "QUEUE_141_D", "QUEUE_142_A", "QUEUE_142_B"}
        register += {"QUEUE_142_C", "QUEUE_142_D", "QUEUE_143_A", "QUEUE_143_B", "QUEUE_143_C"}
        register += {"QUEUE_143_D", "QUEUE_144_A", "QUEUE_144_B", "QUEUE_144_C", "QUEUE_144_D"}
        register += {"QUEUE_145_A", "QUEUE_145_B", "QUEUE_145_C", "QUEUE_145_D", "QUEUE_146_A"}
        register += {"QUEUE_146_B", "QUEUE_146_C", "QUEUE_146_D", "QUEUE_147_A", "QUEUE_147_B"}
        register += {"QUEUE_147_C", "QUEUE_147_D", "QUEUE_148_A", "QUEUE_148_B", "QUEUE_148_C"}
        register += {"QUEUE_148_D", "QUEUE_149_A", "QUEUE_149_B", "QUEUE_149_C", "QUEUE_149_D"}
        register += {"QUEUE_150_A", "QUEUE_150_B", "QUEUE_150_C", "QUEUE_150_D", "QUEUE_151_A"}
        register += {"QUEUE_151_B", "QUEUE_151_C", "QUEUE_151_D", "QUEUE_152_A", "QUEUE_152_B"}
        register += {"QUEUE_152_C", "QUEUE_152_D", "QUEUE_153_A", "QUEUE_153_B", "QUEUE_153_C"}
        register += {"QUEUE_153_D", "QUEUE_154_A", "QUEUE_154_B", "QUEUE_154_C", "QUEUE_154_D"}
        register += {"QUEUE_155_A", "QUEUE_155_B", "QUEUE_155_C", "QUEUE_155_D", "QUEUE_0_STATUS_A"}
        register += {"QUEUE_0_STATUS_B", "QUEUE_0_STATUS_C", "QUEUE_1_STATUS_A", "QUEUE_1_STATUS_B"}
        register += {"QUEUE_1_STATUS_C", "QUEUE_2_STATUS_A", "QUEUE_2_STATUS_B", "QUEUE_2_STATUS_C"}
        register += {"QUEUE_3_STATUS_A", "QUEUE_3_STATUS_B", "QUEUE_3_STATUS_C", "QUEUE_4_STATUS_A"}
        register += {"QUEUE_4_STATUS_B", "QUEUE_4_STATUS_C", "QUEUE_5_STATUS_A", "QUEUE_5_STATUS_B"}
        register += {"QUEUE_5_STATUS_C", "QUEUE_6_STATUS_A", "QUEUE_6_STATUS_B", "QUEUE_6_STATUS_C"}
        register += {"QUEUE_7_STATUS_A", "QUEUE_7_STATUS_B", "QUEUE_7_STATUS_C", "QUEUE_8_STATUS_A"}
        register += {"QUEUE_8_STATUS_B", "QUEUE_8_STATUS_C", "QUEUE_9_STATUS_A", "QUEUE_9_STATUS_B"}
        register += {"QUEUE_9_STATUS_C", "QUEUE_10_STATUS_A", "QUEUE_10_STATUS_B"}
        register += {"QUEUE_10_STATUS_C", "QUEUE_11_STATUS_A", "QUEUE_11_STATUS_B"}
        register += {"QUEUE_11_STATUS_C", "QUEUE_12_STATUS_A", "QUEUE_12_STATUS_B"}
        register += {"QUEUE_12_STATUS_C", "QUEUE_13_STATUS_A", "QUEUE_13_STATUS_B"}
        register += {"QUEUE_13_STATUS_C", "QUEUE_14_STATUS_A", "QUEUE_14_STATUS_B"}
        register += {"QUEUE_14_STATUS_C", "QUEUE_15_STATUS_A", "QUEUE_15_STATUS_B"}
        register += {"QUEUE_15_STATUS_C", "QUEUE_16_STATUS_A", "QUEUE_16_STATUS_B"}
        register += {"QUEUE_16_STATUS_C", "QUEUE_17_STATUS_A", "QUEUE_17_STATUS_B"}
        register += {"QUEUE_17_STATUS_C", "QUEUE_18_STATUS_A", "QUEUE_18_STATUS_B"}
        register += {"QUEUE_18_STATUS_C", "QUEUE_19_STATUS_A", "QUEUE_19_STATUS_B"}
        register += {"QUEUE_19_STATUS_C", "QUEUE_20_STATUS_A", "QUEUE_20_STATUS_B"}
        register += {"QUEUE_20_STATUS_C", "QUEUE_21_STATUS_A", "QUEUE_21_STATUS_B"}
        register += {"QUEUE_21_STATUS_C", "QUEUE_22_STATUS_A", "QUEUE_22_STATUS_B"}
        register += {"QUEUE_22_STATUS_C", "QUEUE_23_STATUS_A", "QUEUE_23_STATUS_B"}
        register += {"QUEUE_23_STATUS_C", "QUEUE_24_STATUS_A", "QUEUE_24_STATUS_B"}
        register += {"QUEUE_24_STATUS_C", "QUEUE_25_STATUS_A", "QUEUE_25_STATUS_B"}
        register += {"QUEUE_25_STATUS_C", "QUEUE_26_STATUS_A", "QUEUE_26_STATUS_B"}
        register += {"QUEUE_26_STATUS_C", "QUEUE_27_STATUS_A", "QUEUE_27_STATUS_B"}
        register += {"QUEUE_27_STATUS_C", "QUEUE_28_STATUS_A", "QUEUE_28_STATUS_B"}
        register += {"QUEUE_28_STATUS_C", "QUEUE_29_STATUS_A", "QUEUE_29_STATUS_B"}
        register += {"QUEUE_29_STATUS_C", "QUEUE_30_STATUS_A", "QUEUE_30_STATUS_B"}
        register += {"QUEUE_30_STATUS_C", "QUEUE_31_STATUS_A", "QUEUE_31_STATUS_B"}
        register += {"QUEUE_31_STATUS_C", "QUEUE_32_STATUS_A", "QUEUE_32_STATUS_B"}
        register += {"QUEUE_32_STATUS_C", "QUEUE_33_STATUS_A", "QUEUE_33_STATUS_B"}
        register += {"QUEUE_33_STATUS_C", "QUEUE_34_STATUS_A", "QUEUE_34_STATUS_B"}
        register += {"QUEUE_34_STATUS_C", "QUEUE_35_STATUS_A", "QUEUE_35_STATUS_B"}
        register += {"QUEUE_35_STATUS_C", "QUEUE_36_STATUS_A", "QUEUE_36_STATUS_B"}
        register += {"QUEUE_36_STATUS_C", "QUEUE_37_STATUS_A", "QUEUE_37_STATUS_B"}
        register += {"QUEUE_37_STATUS_C", "QUEUE_38_STATUS_A", "QUEUE_38_STATUS_B"}
        register += {"QUEUE_38_STATUS_C", "QUEUE_39_STATUS_A", "QUEUE_39_STATUS_B"}
        register += {"QUEUE_39_STATUS_C", "QUEUE_40_STATUS_A", "QUEUE_40_STATUS_B"}
        register += {"QUEUE_40_STATUS_C", "QUEUE_41_STATUS_A", "QUEUE_41_STATUS_B"}
        register += {"QUEUE_41_STATUS_C", "QUEUE_42_STATUS_A", "QUEUE_42_STATUS_B"}
        register += {"QUEUE_42_STATUS_C", "QUEUE_43_STATUS_A", "QUEUE_43_STATUS_B"}
        register += {"QUEUE_43_STATUS_C", "QUEUE_44_STATUS_A", "QUEUE_44_STATUS_B"}
        register += {"QUEUE_44_STATUS_C", "QUEUE_45_STATUS_A", "QUEUE_45_STATUS_B"}
        register += {"QUEUE_45_STATUS_C", "QUEUE_46_STATUS_A", "QUEUE_46_STATUS_B"}
        register += {"QUEUE_46_STATUS_C", "QUEUE_47_STATUS_A", "QUEUE_47_STATUS_B"}
        register += {"QUEUE_47_STATUS_C", "QUEUE_48_STATUS_A", "QUEUE_48_STATUS_B"}
        register += {"QUEUE_48_STATUS_C", "QUEUE_49_STATUS_A", "QUEUE_49_STATUS_B"}
        register += {"QUEUE_49_STATUS_C", "QUEUE_50_STATUS_A", "QUEUE_50_STATUS_B"}
        register += {"QUEUE_50_STATUS_C", "QUEUE_51_STATUS_A", "QUEUE_51_STATUS_B"}
        register += {"QUEUE_51_STATUS_C", "QUEUE_52_STATUS_A", "QUEUE_52_STATUS_B"}
        register += {"QUEUE_52_STATUS_C", "QUEUE_53_STATUS_A", "QUEUE_53_STATUS_B"}
        register += {"QUEUE_53_STATUS_C", "QUEUE_54_STATUS_A", "QUEUE_54_STATUS_B"}
        register += {"QUEUE_54_STATUS_C", "QUEUE_55_STATUS_A", "QUEUE_55_STATUS_B"}
        register += {"QUEUE_55_STATUS_C", "QUEUE_56_STATUS_A", "QUEUE_56_STATUS_B"}
        register += {"QUEUE_56_STATUS_C", "QUEUE_57_STATUS_A", "QUEUE_57_STATUS_B"}
        register += {"QUEUE_57_STATUS_C", "QUEUE_58_STATUS_A", "QUEUE_58_STATUS_B"}
        register += {"QUEUE_58_STATUS_C", "QUEUE_59_STATUS_A", "QUEUE_59_STATUS_B"}
        register += {"QUEUE_59_STATUS_C", "QUEUE_60_STATUS_A", "QUEUE_60_STATUS_B"}
        register += {"QUEUE_60_STATUS_C", "QUEUE_61_STATUS_A", "QUEUE_61_STATUS_B"}
        register += {"QUEUE_61_STATUS_C", "QUEUE_62_STATUS_A", "QUEUE_62_STATUS_B"}
        register += {"QUEUE_62_STATUS_C", "QUEUE_63_STATUS_A", "QUEUE_63_STATUS_B"}
        register += {"QUEUE_63_STATUS_C", "QUEUE_64_STATUS_A", "QUEUE_64_STATUS_B"}
        register += {"QUEUE_64_STATUS_C", "QUEUE_65_STATUS_A", "QUEUE_65_STATUS_B"}
        register += {"QUEUE_65_STATUS_C", "QUEUE_66_STATUS_A", "QUEUE_66_STATUS_B"}
        register += {"QUEUE_66_STATUS_C", "QUEUE_67_STATUS_A", "QUEUE_67_STATUS_B"}
        register += {"QUEUE_67_STATUS_C", "QUEUE_68_STATUS_A", "QUEUE_68_STATUS_B"}
        register += {"QUEUE_68_STATUS_C", "QUEUE_69_STATUS_A", "QUEUE_69_STATUS_B"}
        register += {"QUEUE_69_STATUS_C", "QUEUE_70_STATUS_A", "QUEUE_70_STATUS_B"}
        register += {"QUEUE_70_STATUS_C", "QUEUE_71_STATUS_A", "QUEUE_71_STATUS_B"}
        register += {"QUEUE_71_STATUS_C", "QUEUE_72_STATUS_A", "QUEUE_72_STATUS_B"}
        register += {"QUEUE_72_STATUS_C", "QUEUE_73_STATUS_A", "QUEUE_73_STATUS_B"}
        register += {"QUEUE_73_STATUS_C", "QUEUE_74_STATUS_A", "QUEUE_74_STATUS_B"}
        register += {"QUEUE_74_STATUS_C", "QUEUE_75_STATUS_A", "QUEUE_75_STATUS_B"}
        register += {"QUEUE_75_STATUS_C", "QUEUE_76_STATUS_A", "QUEUE_76_STATUS_B"}
        register += {"QUEUE_76_STATUS_C", "QUEUE_77_STATUS_A", "QUEUE_77_STATUS_B"}
        register += {"QUEUE_77_STATUS_C", "QUEUE_78_STATUS_A", "QUEUE_78_STATUS_B"}
        register += {"QUEUE_78_STATUS_C", "QUEUE_79_STATUS_A", "QUEUE_79_STATUS_B"}
        register += {"QUEUE_79_STATUS_C", "QUEUE_80_STATUS_A", "QUEUE_80_STATUS_B"}
        register += {"QUEUE_80_STATUS_C", "QUEUE_81_STATUS_A", "QUEUE_81_STATUS_B"}
        register += {"QUEUE_81_STATUS_C", "QUEUE_82_STATUS_A", "QUEUE_82_STATUS_B"}
        register += {"QUEUE_82_STATUS_C", "QUEUE_83_STATUS_A", "QUEUE_83_STATUS_B"}
        register += {"QUEUE_83_STATUS_C", "QUEUE_84_STATUS_A", "QUEUE_84_STATUS_B"}
        register += {"QUEUE_84_STATUS_C", "QUEUE_85_STATUS_A", "QUEUE_85_STATUS_B"}
        register += {"QUEUE_85_STATUS_C", "QUEUE_86_STATUS_A", "QUEUE_86_STATUS_B"}
        register += {"QUEUE_86_STATUS_C", "QUEUE_87_STATUS_A", "QUEUE_87_STATUS_B"}
        register += {"QUEUE_87_STATUS_C", "QUEUE_88_STATUS_A", "QUEUE_88_STATUS_B"}
        register += {"QUEUE_88_STATUS_C", "QUEUE_89_STATUS_A", "QUEUE_89_STATUS_B"}
        register += {"QUEUE_89_STATUS_C", "QUEUE_90_STATUS_A", "QUEUE_90_STATUS_B"}
        register += {"QUEUE_90_STATUS_C", "QUEUE_91_STATUS_A", "QUEUE_91_STATUS_B"}
        register += {"QUEUE_91_STATUS_C", "QUEUE_92_STATUS_A", "QUEUE_92_STATUS_B"}
        register += {"QUEUE_92_STATUS_C", "QUEUE_93_STATUS_A", "QUEUE_93_STATUS_B"}
        register += {"QUEUE_93_STATUS_C", "QUEUE_94_STATUS_A", "QUEUE_94_STATUS_B"}
        register += {"QUEUE_94_STATUS_C", "QUEUE_95_STATUS_A", "QUEUE_95_STATUS_B"}
        register += {"QUEUE_95_STATUS_C", "QUEUE_96_STATUS_A", "QUEUE_96_STATUS_B"}
        register += {"QUEUE_96_STATUS_C", "QUEUE_97_STATUS_A", "QUEUE_97_STATUS_B"}
        register += {"QUEUE_97_STATUS_C", "QUEUE_98_STATUS_A", "QUEUE_98_STATUS_B"}
        register += {"QUEUE_98_STATUS_C", "QUEUE_99_STATUS_A", "QUEUE_99_STATUS_B"}
        register += {"QUEUE_99_STATUS_C", "QUEUE_100_STATUS_A", "QUEUE_100_STATUS_B"}
        register += {"QUEUE_100_STATUS_C", "QUEUE_101_STATUS_A", "QUEUE_101_STATUS_B"}
        register += {"QUEUE_101_STATUS_C", "QUEUE_102_STATUS_A", "QUEUE_102_STATUS_B"}
        register += {"QUEUE_102_STATUS_C", "QUEUE_103_STATUS_A", "QUEUE_103_STATUS_B"}
        register += {"QUEUE_103_STATUS_C", "QUEUE_104_STATUS_A", "QUEUE_104_STATUS_B"}
        register += {"QUEUE_104_STATUS_C", "QUEUE_105_STATUS_A", "QUEUE_105_STATUS_B"}
        register += {"QUEUE_105_STATUS_C", "QUEUE_106_STATUS_A", "QUEUE_106_STATUS_B"}
        register += {"QUEUE_106_STATUS_C", "QUEUE_107_STATUS_A", "QUEUE_107_STATUS_B"}
        register += {"QUEUE_107_STATUS_C", "QUEUE_108_STATUS_A", "QUEUE_108_STATUS_B"}
        register += {"QUEUE_108_STATUS_C", "QUEUE_109_STATUS_A", "QUEUE_109_STATUS_B"}
        register += {"QUEUE_109_STATUS_C", "QUEUE_110_STATUS_A", "QUEUE_110_STATUS_B"}
        register += {"QUEUE_110_STATUS_C", "QUEUE_111_STATUS_A", "QUEUE_111_STATUS_B"}
        register += {"QUEUE_111_STATUS_C", "QUEUE_112_STATUS_A", "QUEUE_112_STATUS_B"}
        register += {"QUEUE_112_STATUS_C", "QUEUE_113_STATUS_A", "QUEUE_113_STATUS_B"}
        register += {"QUEUE_113_STATUS_C", "QUEUE_114_STATUS_A", "QUEUE_114_STATUS_B"}
        register += {"QUEUE_114_STATUS_C", "QUEUE_115_STATUS_A", "QUEUE_115_STATUS_B"}
        register += {"QUEUE_115_STATUS_C", "QUEUE_116_STATUS_A", "QUEUE_116_STATUS_B"}
        register += {"QUEUE_116_STATUS_C", "QUEUE_117_STATUS_A", "QUEUE_117_STATUS_B"}
        register += {"QUEUE_117_STATUS_C", "QUEUE_118_STATUS_A", "QUEUE_118_STATUS_B"}
        register += {"QUEUE_118_STATUS_C", "QUEUE_119_STATUS_A", "QUEUE_119_STATUS_B"}
        register += {"QUEUE_119_STATUS_C", "QUEUE_120_STATUS_A", "QUEUE_120_STATUS_B"}
        register += {"QUEUE_120_STATUS_C", "QUEUE_121_STATUS_A", "QUEUE_121_STATUS_B"}
        register += {"QUEUE_121_STATUS_C", "QUEUE_122_STATUS_A", "QUEUE_122_STATUS_B"}
        register += {"QUEUE_122_STATUS_C", "QUEUE_123_STATUS_A", "QUEUE_123_STATUS_B"}
        register += {"QUEUE_123_STATUS_C", "QUEUE_124_STATUS_A", "QUEUE_124_STATUS_B"}
        register += {"QUEUE_124_STATUS_C", "QUEUE_125_STATUS_A", "QUEUE_125_STATUS_B"}
        register += {"QUEUE_125_STATUS_C", "QUEUE_126_STATUS_A", "QUEUE_126_STATUS_B"}
        register += {"QUEUE_126_STATUS_C", "QUEUE_127_STATUS_A", "QUEUE_127_STATUS_B"}
        register += {"QUEUE_127_STATUS_C", "QUEUE_128_STATUS_A", "QUEUE_128_STATUS_B"}
        register += {"QUEUE_128_STATUS_C", "QUEUE_129_STATUS_A", "QUEUE_129_STATUS_B"}
        register += {"QUEUE_129_STATUS_C", "QUEUE_130_STATUS_A", "QUEUE_130_STATUS_B"}
        register += {"QUEUE_130_STATUS_C", "QUEUE_131_STATUS_A", "QUEUE_131_STATUS_B"}
        register += {"QUEUE_131_STATUS_C", "QUEUE_132_STATUS_A", "QUEUE_132_STATUS_B"}
        register += {"QUEUE_132_STATUS_C", "QUEUE_133_STATUS_A", "QUEUE_133_STATUS_B"}
        register += {"QUEUE_133_STATUS_C", "QUEUE_134_STATUS_A", "QUEUE_134_STATUS_B"}
        register += {"QUEUE_134_STATUS_C", "QUEUE_135_STATUS_A", "QUEUE_135_STATUS_B"}
        register += {"QUEUE_135_STATUS_C", "QUEUE_136_STATUS_A", "QUEUE_136_STATUS_B"}
        register += {"QUEUE_136_STATUS_C", "QUEUE_137_STATUS_A", "QUEUE_137_STATUS_B"}
        register += {"QUEUE_137_STATUS_C", "QUEUE_138_STATUS_A", "QUEUE_138_STATUS_B"}
        register += {"QUEUE_138_STATUS_C", "QUEUE_139_STATUS_A", "QUEUE_139_STATUS_B"}
        register += {"QUEUE_139_STATUS_C", "QUEUE_140_STATUS_A", "QUEUE_140_STATUS_B"}
        register += {"QUEUE_140_STATUS_C", "QUEUE_141_STATUS_A", "QUEUE_141_STATUS_B"}
        register += {"QUEUE_141_STATUS_C", "QUEUE_142_STATUS_A", "QUEUE_142_STATUS_B"}
        register += {"QUEUE_142_STATUS_C", "QUEUE_143_STATUS_A", "QUEUE_143_STATUS_B"}
        register += {"QUEUE_143_STATUS_C", "QUEUE_144_STATUS_A", "QUEUE_144_STATUS_B"}
        register += {"QUEUE_144_STATUS_C", "QUEUE_145_STATUS_A", "QUEUE_145_STATUS_B"}
        register += {"QUEUE_145_STATUS_C", "QUEUE_146_STATUS_A", "QUEUE_146_STATUS_B"}
        register += {"QUEUE_146_STATUS_C", "QUEUE_147_STATUS_A", "QUEUE_147_STATUS_B"}
        register += {"QUEUE_147_STATUS_C", "QUEUE_148_STATUS_A", "QUEUE_148_STATUS_B"}
        register += {"QUEUE_148_STATUS_C", "QUEUE_149_STATUS_A", "QUEUE_149_STATUS_B"}
        register += {"QUEUE_149_STATUS_C", "QUEUE_150_STATUS_A", "QUEUE_150_STATUS_B"}
        register += {"QUEUE_150_STATUS_C", "QUEUE_151_STATUS_A", "QUEUE_151_STATUS_B"}
        register += {"QUEUE_151_STATUS_C", "QUEUE_152_STATUS_A", "QUEUE_152_STATUS_B"}
        register += {"QUEUE_152_STATUS_C", "QUEUE_153_STATUS_A", "QUEUE_153_STATUS_B"}
        register += {"QUEUE_153_STATUS_C", "QUEUE_154_STATUS_A", "QUEUE_154_STATUS_B"}
        register += {"QUEUE_154_STATUS_C", "QUEUE_155_STATUS_A", "QUEUE_155_STATUS_B"}
        register += {"QUEUE_155_STATUS_C"}
    }
    "WDT1" {
        collapse = true
        register = {"WDT_WIDR", "WDT_WDSC", "WDT_WDST", "WDT_WISR", "WDT_WIER", "WDT_WCLR"}
        register += {"WDT_WCRR", "WDT_WLDR", "WDT_WTGR", "WDT_WWPS", "WDT_WDLY", "WDT_WSPR"}
        register += {"WDT_WIRQSTATRAW", "WDT_WIRQSTAT", "WDT_WIRQENSET", "WDT_WIRQENCLR"}
    }
    "eCAP0" {
        collapse = true
        register = {"eCAP0_TSCTR", "eCAP0_CTRPHS", "eCAP0_CAP1", "eCAP0_CAP2", "eCAP0_CAP3"}
        register += {"eCAP0_CAP4", "eCAP0_ECCTL1", "eCAP0_ECCTL2", "eCAP0_ECEINT"}
        register += {"eCAP0_ECFLG", "eCAP0_ECCLR", "eCAP0_ECFRC", "eCAP0_REVID"}
    }
    "eCAP1" {
        collapse = true
        register = {"eCAP1_TSCTR", "eCAP1_CTRPHS", "eCAP1_CAP1", "eCAP1_CAP2", "eCAP1_CAP3"}
        register += {"eCAP1_CAP4", "eCAP1_ECCTL1", "eCAP1_ECCTL2", "eCAP1_ECEINT"}
        register += {"eCAP1_ECFLG", "eCAP1_ECCLR", "eCAP1_ECFRC", "eCAP1_REVID"}
    }
    "eCAP2" {
        collapse = true
        register = {"eCAP2_TSCTR", "eCAP2_CTRPHS", "eCAP2_CAP1", "eCAP2_CAP2", "eCAP2_CAP3"}
        register += {"eCAP2_CAP4", "eCAP2_ECCTL1", "eCAP2_ECCTL2", "eCAP2_ECEINT"}
        register += {"eCAP2_ECFLG", "eCAP2_ECCLR", "eCAP2_ECFRC", "eCAP2_REVID"}
    }
    "ePWM0" {
        collapse = true
        register = {"ePWM0_TBCTL", "ePWM0_TBSTS", "ePWM0_TBPHSHR", "ePWM0_TBPHS"}
        register += {"ePWM0_TBCNT", "ePWM0_TBPRD", "ePWM0_CMPCTL", "ePWM0_CMPAHR"}
        register += {"ePWM0_CMPA", "ePWM0_CMPB", "ePWM0_AQCTLA", "ePWM0_AQCTLB", "ePWM0_AQSFRC"}
        register += {"ePWM0_AQCSFRC", "ePWM0_DBCTL", "ePWM0_DBRED", "ePWM0_DBFED"}
        register += {"ePWM0_TZSEL", "ePWM0_TZCTL", "ePWM0_TZEINT", "ePWM0_TZFLG"}
        register += {"ePWM0_TZCLR", "ePWM0_TZFRC", "ePWM0_ETSEL", "ePWM0_ETPS", "ePWM0_ETFLG"}
        register += {"ePWM0_ETCLR", "ePWM0_ETFRC", "ePWM0_PCCTL", "ePWM0_HRCTL"}
    }
    "ePWM1" {
        collapse = true
        register = {"ePWM1_TBCTL", "ePWM1_TBSTS", "ePWM1_TBPHSHR", "ePWM1_TBPHS"}
        register += {"ePWM1_TBCNT", "ePWM1_TBPRD", "ePWM1_CMPCTL", "ePWM1_CMPAHR"}
        register += {"ePWM1_CMPA", "ePWM1_CMPB", "ePWM1_AQCTLA", "ePWM1_AQCTLB", "ePWM1_AQSFRC"}
        register += {"ePWM1_AQCSFRC", "ePWM1_DBCTL", "ePWM1_DBRED", "ePWM1_DBFED"}
        register += {"ePWM1_TZSEL", "ePWM1_TZCTL", "ePWM1_TZEINT", "ePWM1_TZFLG"}
        register += {"ePWM1_TZCLR", "ePWM1_TZFRC", "ePWM1_ETSEL", "ePWM1_ETPS", "ePWM1_ETFLG"}
        register += {"ePWM1_ETCLR", "ePWM1_ETFRC", "ePWM1_PCCTL", "ePWM1_HRCTL"}
    }
    "ePWM2" {
        collapse = true
        register = {"ePWM2_TBCTL", "ePWM2_TBSTS", "ePWM2_TBPHSHR", "ePWM2_TBPHS"}
        register += {"ePWM2_TBCNT", "ePWM2_TBPRD", "ePWM2_CMPCTL", "ePWM2_CMPAHR"}
        register += {"ePWM2_CMPA", "ePWM2_CMPB", "ePWM2_AQCTLA", "ePWM2_AQCTLB", "ePWM2_AQSFRC"}
        register += {"ePWM2_AQCSFRC", "ePWM2_DBCTL", "ePWM2_DBRED", "ePWM2_DBFED"}
        register += {"ePWM2_TZSEL", "ePWM2_TZCTL", "ePWM2_TZEINT", "ePWM2_TZFLG"}
        register += {"ePWM2_TZCLR", "ePWM2_TZFRC", "ePWM2_ETSEL", "ePWM2_ETPS", "ePWM2_ETFLG"}
        register += {"ePWM2_ETCLR", "ePWM2_ETFRC", "ePWM2_PCCTL", "ePWM2_HRCTL"}
    }
    "eQEP0" {
        collapse = true
        register = {"eQEP0_QPOSCNT", "eQEP0_QPOSINIT", "eQEP0_QPOSMAX", "eQEP0_QPOSCMP"}
        register += {"eQEP0_QPOSILAT", "eQEP0_QPOSSLAT", "eQEP0_QPOSLAT", "eQEP0_QUTMR"}
        register += {"eQEP0_QUPRD", "eQEP0_QWDTMR", "eQEP0_QWDPRD", "eQEP0_QDECCTL"}
        register += {"eQEP0_QEPCTL", "eQEP0_QCAPCTL", "eQEP0_QPOSCTL", "eQEP0_QEINT"}
        register += {"eQEP0_QFLG", "eQEP0_QCLR", "eQEP0_QFRC", "eQEP0_QEPSTS", "eQEP0_QCTMR"}
        register += {"eQEP0_QCPRD", "eQEP0_QCTMRLAT", "eQEP0_QCPRDLAT", "eQEP0_REVID"}
    }
    "eQEP1" {
        collapse = true
        register = {"eQEP1_QPOSCNT", "eQEP1_QPOSINIT", "eQEP1_QPOSMAX", "eQEP1_QPOSCMP"}
        register += {"eQEP1_QPOSILAT", "eQEP1_QPOSSLAT", "eQEP1_QPOSLAT", "eQEP1_QUTMR"}
        register += {"eQEP1_QUPRD", "eQEP1_QWDTMR", "eQEP1_QWDPRD", "eQEP1_QDECCTL"}
        register += {"eQEP1_QEPCTL", "eQEP1_QCAPCTL", "eQEP1_QPOSCTL", "eQEP1_QEINT"}
        register += {"eQEP1_QFLG", "eQEP1_QCLR", "eQEP1_QFRC", "eQEP1_QEPSTS", "eQEP1_QCTMR"}
        register += {"eQEP1_QCPRD", "eQEP1_QCTMRLAT", "eQEP1_QCPRDLAT", "eQEP1_REVID"}
    }
    "eQEP2" {
        collapse = true
        register = {"eQEP2_QPOSCNT", "eQEP2_QPOSINIT", "eQEP2_QPOSMAX", "eQEP2_QPOSCMP"}
        register += {"eQEP2_QPOSILAT", "eQEP2_QPOSSLAT", "eQEP2_QPOSLAT", "eQEP2_QUTMR"}
        register += {"eQEP2_QUPRD", "eQEP2_QWDTMR", "eQEP2_QWDPRD", "eQEP2_QDECCTL"}
        register += {"eQEP2_QEPCTL", "eQEP2_QCAPCTL", "eQEP2_QPOSCTL", "eQEP2_QEINT"}
        register += {"eQEP2_QFLG", "eQEP2_QCLR", "eQEP2_QFRC", "eQEP2_QEPSTS", "eQEP2_QCTMR"}
        register += {"eQEP2_QCPRD", "eQEP2_QCTMRLAT", "eQEP2_QCPRDLAT", "eQEP2_REVID"}
    }
}