# ARM11 MPCore Coprocessor 15 (system coprocessor) registers

bitfield {
    aux_control_mp11_bf {
	Reserved {
	    loc = "31..7"
	    desc = "Reserved - must be updated using read-modify-write"
	}
	L1_parity { loc = "6"; desc = "L1 parity checking enable bit" }
	SMP_AMP {
	    loc = "5"
	    desc = "SMP/nAMP mode. Signals if the CPU is taking part in coherency."
	}
	EXCL {
	    loc = "4"
	    desc = "Enables the exclusive behavior of L1 if the processor is used in conjunction with an L2 cache supporting that behavior"
	}
	F { loc = "3"; desc = "Instruction folding enable (if program flow prediction is enabled)" }
	SB { loc = "2"; desc = "Static branch prediction enable (if program flow prediction is enabled)" }
	DB { loc = "1"; desc = "Dynamic branch prediction enable (if program flow prediction is enabled)" }
	RS { loc = "0"; desc = "Return stack enable (if program flow prediction is enabled)" }
    }
}

# Register definitions
register {
    id {
	ln="ID Code Register c0"
	address=338
	type="id_bitfield"
	permission = "write/none"
    }
    cache_type {
	ln="Cache Type Register c0"
	address=339
	type="cachetype_bitfield"
	permission = "write/none"
    }
    tlb_type {
	ln="TLB Type Register c0"
	address=341
	type="tlbtype_bitfield"
	permission = "write/none"
    }
    id_pfr0  { ln="Processor Feature Register 0"; address=560 }
    id_pfr1  { ln="Processor Feature Register 1"; address=561 }
    id_dfr0  { ln="Debug Feature Register 0"; address=562 }
    id_mmfr0 { ln="Memory Model Feature Register 0"; address=564 }
    id_mmfr1 { ln="Memory Model Feature Register 1"; address=565 }
    id_mmfr2 { ln="Memory Model Feature Register 2"; address=566 }
    id_mmfr3 { ln="Memory Model Feature Register 3"; address=567 }
    id_isar0 { ln="Instruction Set Attributes Register 0"; address=568 }
    id_isar1 { ln="Instruction Set Attributes Register 1"; address=569 }
    id_isar2 { ln="Instruction Set Attributes Register 2"; address=570 }
    id_isar3 { ln="Instruction Set Attributes Register 3"; address=571 }
    id_isar4 { ln="Instruction Set Attributes Register 4"; address=572 }
    cpu_id {
	ln="CPU ID"
	address=696
	permission = "write/none"
    }
    control {
	ln="Control Register c1"
	address=342
	type="control_bitfield"
    }
    aux_control {
	ln="Auxiliary Control Register c1"
	address=343
	type="aux_control_mp11_bf"
    }
    cp_access {
	ln="Coprocessor Access Control Register c1"
	address=344
    }
    ttbr0 {
	ln="Translation Table Base Register 0 c2"
	address=345
	type="ttbase_bitfield"
    }
    ttbase0 { access="synonym"; address="ttbr0"; hide=true }
    ttbr1 {
	ln="Translation Table Base Register 1 c2"
	address=346
	type="ttbase_bitfield"
    }
    ttbase1 { access="synonym"; address="ttbr1"; hide=true }
    ttbcr {
	ln="Translation Table Base Control Register c2"
	address=347
    }
    ttbase_ctrl { access="synonym"; address="ttbcr"; hide=true }
    dactl {
	ln="Domain Access Control Register c3"
	address=348
	type="dactl_bitfield"
    }
    dfsr {
	ln="Data Fault Status Register c5"
	address=349
	type="faultstatus_bitfield"
    }
    ifsr {
	ln="Instruction Fault Status Register c5"
	address=350
	type="faultstatus_bitfield"
    }
    far {
	ln="Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the data access being attempted when a Data Abort occurred."
	address=351
    }
    wfar {
	ln="Watchpoint Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the instruction access being attempted when a Data Abort occurred."
	address=352
    }
    dcache_lock {
	ln="Data Cache Lockdown Register c9"
	address=353
	type="cachelock_bitfield"
    }
    tlb_lock {
	ln="TLB Lockdown Register c10"
	address=357
	type="tlblock_bitfield"
    }
    primary_region_remap {
	ln="Primary Region Remap Register c10"
	address=583
	type="primary_region_remap_bitfield"
    }
    normal_region_remap {
	ln="Normal Region Remap Register c10"
	address=640
	type="normal_memory_remap_bitfield"
    }
    pid {
	ln="Fast Context Switch Extension (FCSE) Process Identifier (PID) Register c13"
	address=373
	type="pid_bitfield"
    }
    contextid {
	ln="Context ID Register c13"
	address=374
    }
    user_ro_threadid {
	ln="User RO Thread ID c13"
	address=601
    }
    user_rw_threadid {
	ln="User RW Thread ID c13"
	address=602
    }
    priv_threadid {
	ln="Privileged Thread ID c13"
	address=590
    }
    perfmon_ctrl	{ address=379 }
    cycle_count		{ address=380 }
    count0		{ address=381 }
    count1		{ address=382 }
    read_maintlb_entry	{ address=394 }
    write_maintlb_entry	{ address=395 }
    maintlb_va		{ address=398 }
    maintlb_pa		{ address=401 }
    maintlb_attrib	{ address=404 }
    tlb_debug_ctrl	{ address=407 }
}


# Group definitions
group {
    arm11mp_CP15_C15 {
	sn = "CP15_C15"
	register += { "perfmon_ctrl", "cycle_count", "count0", "count1" }
	register += { "read_maintlb_entry", "write_maintlb_entry" }	
	register += { "maintlb_va" }		
	register += { "maintlb_pa" }		
	register += { "maintlb_attrib" }
	register += { "tlb_debug_ctrl" }
    }
    arm11mp_CP15 {
	sn = "CP15"
	register += { "id", "cache_type", "tlb_type", "cpu_id" }
	register += { "id_pfr0", "id_pfr1", "id_dfr0", "id_mmfr0" }
	register += { "id_mmfr1", "id_mmfr2", "id_mmfr3" }
	register += { "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4" }
	register += { "control", "aux_control", "cp_access" }
	register += { "ttbr0", "ttbr1", "ttbcr" }
	register += { "dactl", "dfsr", "ifsr", "far", "wfar" }
	register += { "dcache_lock" }
	register += { "tlb_lock" }
	register += { "primary_region_remap", "normal_region_remap" }	
	register += { "pid", "contextid", "user_ro_threadid" }
	register += { "user_rw_threadid", "priv_threadid" }

	group += {"arm11mp_CP15_C15" }
    }
}