; Generated peripheral file for Z20K14xM by TRACE32 internal SVD converter
AUTOINDENT.CONFIG.MBL 100.
AUTOINDENT.ON LEFT GRID
CSV.ON,,,,,,,,
PERCMD,Address,AccessWidth,Name,Tooltip,From,To,Choices,RW
base ad:0x40008000
tree "DMA"
,0x00000000,32.,DMA_CONF,'DMA configure register(DMA_CONF)',,,,rw
,,,HALT,'DMA operation halt',0.,0.,,rw
,,,HOEE,'Halt on error enable',1.,1.,,rw
,,,RRCAE,'Round robin channel arbitration enable',2.,2.,,rw
,,,DBGE,'Debug enable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'DMA busy status ',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,DMA_DMAE,'DMA request enable register(DMA_DMAE)',,,,rw
,,,DMAE0,'Channel 0 DMA request enable',0.,0.,,rw
,,,DMAE1,'Channel 1 DMA request enable',1.,1.,,rw
,,,DMAE2,'Channel 2 DMA request enable',2.,2.,,rw
,,,DMAE3,'Channel 3 DMA request enable',3.,3.,,rw
,,,DMAE4,'Channel 4 DMA request enable',4.,4.,,rw
,,,DMAE5,'Channel 5 DMA request enable',5.,5.,,rw
,,,DMAE6,'Channel 6 DMA request enable',6.,6.,,rw
,,,DMAE7,'Channel 7 DMA request enable',7.,7.,,rw
,,,DMAE8,'Channel 8 DMA request enable',8.,8.,,rw
,,,DMAE9,'Channel 9 DMA request enable',9.,9.,,rw
,,,DMAE10,'Channel 10 DMA request enable',10.,10.,,rw
,,,DMAE11,'Channel 11 DMA request enable',11.,11.,,rw
,,,DMAE12,'Channel 12 DMA request enable',12.,12.,,rw
,,,DMAE13,'Channel 13 DMA request enable',13.,13.,,rw
,,,DMAE14,'Channel 14 DMA request enable',14.,14.,,rw
,,,DMAE15,'Channel 15 DMA request enable',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,DMA_EIE,'DMA errror interrupt enable register(DMA_EIE)',,,,rw
,,,EIE0,'Channel 0 error interrupt enable',0.,0.,,rw
,,,EIE1,'Channel 1 error interrupt enable',1.,1.,,rw
,,,EIE2,'Channel 2 error interrupt enable',2.,2.,,rw
,,,EIE3,'Channel 3 error interrupt enable',3.,3.,,rw
,,,EIE4,'Channel 4 error interrupt enable',4.,4.,,rw
,,,EIE5,'Channel 5 error interrupt enable',5.,5.,,rw
,,,EIE6,'Channel 6 error interrupt enable',6.,6.,,rw
,,,EIE7,'Channel 7 error interrupt enable',7.,7.,,rw
,,,EIE8,'Channel 8 error interrupt enable',8.,8.,,rw
,,,EIE9,'Channel 9 error interrupt enable',9.,9.,,rw
,,,EIE10,'Channel 10 error interrupt enable',10.,10.,,rw
,,,EIE11,'Channel 11 error interrupt enable',11.,11.,,rw
,,,EIE12,'Channel 12 error interrupt enable',12.,12.,,rw
,,,EIE13,'Channel 13 error interrupt enable',13.,13.,,rw
,,,EIE14,'Channel 14 error interrupt enable',14.,14.,,rw
,,,EIE15,'Channel 15 error interrupt enable',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000014,32.,DMA_GCC,'DMA global channel control register(DMA_GCC)',,,,wr
,,,CCDONE,'Clear channel DONE bit of DMA_CSx[DONE]',0.,3.,,wr
,,,RSVD_5_4,'Reserved',4.,5.,,wr
,,,CACDONE,'Clear all channels DONE bit of DMA_CSx[DONE]',6.,6.,,wr
,,,WPEN0,'Write protection for this register byte 0 bits',7.,7.,,wr
,,,SCSTART,'Set channel START bit of DMA_CSx[START]',8.,11.,,wr
,,,RSVD_13_12,'Reserved',12.,13.,,wr
,,,SACSTART,'Set all channels START bit of DMA_CSx[START]',14.,14.,,wr
,,,WPEN1,'Write protection for this register byte 1 bits',15.,15.,,wr
,,,CCES,'Clear channel error status in CES register',16.,19.,,wr
,,,RSVD_21_20,'Reserved',20.,21.,,wr
,,,CACES,'Clear all channels error status in CES register',22.,22.,,wr
,,,WPEN2,'Write protection for this register byte 2 bits',23.,23.,,wr
,,,CCIS,'Clear channel interrupt status in CIS register',24.,27.,,wr
,,,RSVD_29_28,'Reserved',28.,29.,,wr
,,,CACIS,'Clear all channels interrupt status in CIS register',30.,30.,,wr
,,,WPEN3,'Write protection for this register byte 3 bits',31.,31.,,wr
,0x00000018,32.,DMA_ES,'DMA error status register (DMA_ES)',,,,rd
,,,DBEF,'Destination bus error flag',0.,0.,,rd
,,,SBEF,'Source bus error flag',1.,1.,,rd
,,,RSVD_2,'Reserved',2.,2.,,rd
,,,NUMEF,'Number of transfer data error flag',3.,3.,,rd
,,,DOEF,'destination address offset error flag',4.,4.,,rd
,,,DAEF,'destination address error flag',5.,5.,,rd
,,,SOEF,'Source address offset error flag',6.,6.,,rd
,,,SAEF,'Source address error flag',7.,7.,,rd
,,,CHEF,'Channel error flag',8.,11.,,rd
,,,RSVD_12,'Reserved',12.,12.,,rd
,,,PRIEF,'Priority error flag',13.,13.,,rd
,,,RSVD_14,'Reserved',14.,14.,,rd
,,,ERRF,'Error flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x0000001C,32.,DMA_CES,'DMA channel error status register(DMA_CES)',,,,rd
,,,ERR0,'Channel 0 error flag',0.,0.,,rd
,,,ERR1,'Channel 1 error flag',1.,1.,,rd
,,,ERR2,'Channel 2 error flag',2.,2.,,rd
,,,ERR3,'Channel 3 error flag',3.,3.,,rd
,,,ERR4,'Channel 4 error flag',4.,4.,,rd
,,,ERR5,'Channel 5 error flag',5.,5.,,rd
,,,ERR6,'Channel 6 error flag',6.,6.,,rd
,,,ERR7,'Channel 7 error flag',7.,7.,,rd
,,,ERR8,'Channel 8 error flag',8.,8.,,rd
,,,ERR9,'Channel 9 error flag',9.,9.,,rd
,,,ERR10,'Channel 10 error flag',10.,10.,,rd
,,,ERR11,'Channel 11 error flag',11.,11.,,rd
,,,ERR12,'Channel 12 error flag',12.,12.,,rd
,,,ERR13,'Channel 13 error flag',13.,13.,,rd
,,,ERR14,'Channel 14 error flag',14.,14.,,rd
,,,ERR15,'Channel 15 error flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000020,32.,DMA_CIS,'DMA channel interrupt status register(DMA_CIS)',,,,rd
,,,INT0,'Channel 0 interrupt flag',0.,0.,,rd
,,,INT1,'Channel 1 interrupt flag',1.,1.,,rd
,,,INT2,'Channel 2 interrupt flag',2.,2.,,rd
,,,INT3,'Channel 3 interrupt flag',3.,3.,,rd
,,,INT4,'Channel 4 interrupt flag',4.,4.,,rd
,,,INT5,'Channel 5 interrupt flag',5.,5.,,rd
,,,INT6,'Channel 6 interrupt flag',6.,6.,,rd
,,,INT7,'Channel 7 interrupt flag',7.,7.,,rd
,,,INT8,'Channel 8 interrupt flag',8.,8.,,rd
,,,INT9,'Channel 9 interrupt flag',9.,9.,,rd
,,,INT10,'Channel 10 interrupt flag',10.,10.,,rd
,,,INT11,'Channel 11 interrupt flag',11.,11.,,rd
,,,INT12,'Channel 12 interrupt flag',12.,12.,,rd
,,,INT13,'Channel 13 interrupt flag',13.,13.,,rd
,,,INT14,'Channel 14 interrupt flag',14.,14.,,rd
,,,INT15,'Channel 15 interrupt flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000024,32.,DMA_CHRS,'DMA channel hardware request status register(DMA_CHRS)',,,,rd
,,,HRS0,'Channel 0 hardware request flag',0.,0.,,rd
,,,HRS1,'Channel 1 hardware request flag',1.,1.,,rd
,,,HRS2,'Channel 2 hardware request flag',2.,2.,,rd
,,,HRS3,'Channel 3 hardware request flag',3.,3.,,rd
,,,HRS4,'Channel 4 hardware request flag',4.,4.,,rd
,,,HRS5,'Channel 5 hardware request flag',5.,5.,,rd
,,,HRS6,'Channel 6 hardware request flag',6.,6.,,rd
,,,HRS7,'Channel 7 hardware request flag',7.,7.,,rd
,,,HRS8,'Channel 8 hardware request flag',8.,8.,,rd
,,,HRS9,'Channel 9 hardware request flag',9.,9.,,rd
,,,HRS10,'Channel 10 hardware request flag',10.,10.,,rd
,,,HRS11,'Channel 11 hardware request flag',11.,11.,,rd
,,,HRS12,'Channel 12 hardware request flag',12.,12.,,rd
,,,HRS13,'Channel 13 hardware request flag',13.,13.,,rd
,,,HRS14,'Channel 14 hardware request flag',14.,14.,,rd
,,,HRS15,'Channel 15 hardware request flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000028,32.,DMA_CPRI0,'DMA channel priority register 0(DMA_CPRI0)',,,,rw
,,,CPRI3,'Channel 3 priority',0.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,CPDIS3,'Channel 3 preempt disable',6.,6.,,rw
,,,CSE3,'Channel 3 suspend enable',7.,7.,,rw
,,,CPRI2,'Channel 2 priority',8.,11.,,rw
,,,RSVD_13_12,'Reserved',12.,13.,,rw
,,,CPDIS2,'Channel 2 preempt disable',14.,14.,,rw
,,,CSE2,'Channel 2 suspend enable',15.,15.,,rw
,,,CPRI1,'Channel 1 priority',16.,19.,,rw
,,,RSVD_21_20,'Reserved',20.,21.,,rw
,,,CPDIS1,'Channel 1 preempt disable',22.,22.,,rw
,,,CSE1,'Channel 1 suspend enable',23.,23.,,rw
,,,CPRI0,'Channel 0 priority',24.,27.,,rw
,,,RSVD_29_28,'Reserved',28.,29.,,rw
,,,CPDIS0,'Channel 0 preempt disable',30.,30.,,rw
,,,CSE0,'Channel 0 suspend enable',31.,31.,,rw
,0x0000002C,32.,DMA_CPRI1,'DMA channel priority register 1(DMA_CPRI1)',,,,rw
,,,CPRI7,'Channel 7 priority',0.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,CPDIS7,'Channel 7 preempt disable',6.,6.,,rw
,,,CSE7,'Channel 7 suspend enable',7.,7.,,rw
,,,CPRI6,'Channel 6 priority',8.,11.,,rw
,,,RSVD_13_12,'Reserved',12.,13.,,rw
,,,CPDIS6,'Channel 6 preempt disable',14.,14.,,rw
,,,CSE6,'Channel 6 suspend enable',15.,15.,,rw
,,,CPRI5,'Channel 5 priority',16.,19.,,rw
,,,RSVD_21_20,'Reserved',20.,21.,,rw
,,,CPDIS5,'Channel 5 preempt disable',22.,22.,,rw
,,,CSE5,'Channel 5 suspend enable',23.,23.,,rw
,,,CPRI4,'Channel 4 priority',24.,27.,,rw
,,,RSVD_29_28,'Reserved',28.,29.,,rw
,,,CPDIS4,'Channel 4 preempt disable',30.,30.,,rw
,,,CSE4,'Channel 4 suspend enable',31.,31.,,rw
,0x00000030,32.,DMA_CPRI2,'DMA channel priority register 2(DMA_CPRI2)',,,,rw
,,,CPRI11,'Channel 11 priority',0.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,CPDIS11,'Channel 11 preempt disable',6.,6.,,rw
,,,CSE11,'Channel 11 suspend enable',7.,7.,,rw
,,,CPRI10,'Channel 10 priority',8.,11.,,rw
,,,RSVD_13_12,'Reserved',12.,13.,,rw
,,,CPDIS10,'Channel 10 preempt disable',14.,14.,,rw
,,,CSE10,'Channel 10 suspend enable',15.,15.,,rw
,,,CPRI9,'Channel 9 priority',16.,19.,,rw
,,,RSVD_21_20,'Reserved',20.,21.,,rw
,,,CPDIS9,'Channel 9 preempt disable',22.,22.,,rw
,,,CSE9,'Channel 9 suspend enable',23.,23.,,rw
,,,CPRI8,'Channel 8 priority',24.,27.,,rw
,,,RSVD_29_28,'Reserved',28.,29.,,rw
,,,CPDIS8,'Channel 8 preempt disable',30.,30.,,rw
,,,CSE8,'Channel 8 suspend enable',31.,31.,,rw
,0x00000034,32.,DMA_CPRI3,'DMA channel priority register 3(DMA_CPRI3)',,,,rw
,,,CPRI15,'Channel 15 priority',0.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,CPDIS15,'Channel 15 preempt disable',6.,6.,,rw
,,,CSE15,'Channel 15 suspend enable',7.,7.,,rw
,,,CPRI14,'Channel 14 priority',8.,11.,,rw
,,,RSVD_13_12,'Reserved',12.,13.,,rw
,,,CPDIS14,'Channel 14 preempt disable',14.,14.,,rw
,,,CSE14,'Channel 14 suspend enable',15.,15.,,rw
,,,CPRI13,'Channel 13 priority',16.,19.,,rw
,,,RSVD_21_20,'Reserved',20.,21.,,rw
,,,CPDIS13,'Channel 13 preempt disable',22.,22.,,rw
,,,CSE13,'Channel 13 suspend enable',23.,23.,,rw
,,,CPRI12,'Channel 12 priority',24.,27.,,rw
,,,RSVD_29_28,'Reserved',28.,29.,,rw
,,,CPDIS12,'Channel 12 preempt disable',30.,30.,,rw
,,,CSE12,'Channel 12 suspend enable',31.,31.,,rw
,0x00000200,32.,DMA_SADDRn0,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000204,32.,DMA_DADDRn0,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000208,32.,DMA_AOFFn0,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000020C,32.,DMA_MLAOFFn0,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000210,32.,DMA_NUMn0,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000214,32.,DMA_ITERn0,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000218,32.,DMA_CSn0,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000220,32.,DMA_SADDRn1,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000224,32.,DMA_DADDRn1,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000228,32.,DMA_AOFFn1,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000022C,32.,DMA_MLAOFFn1,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000230,32.,DMA_NUMn1,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000234,32.,DMA_ITERn1,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000238,32.,DMA_CSn1,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000240,32.,DMA_SADDRn2,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000244,32.,DMA_DADDRn2,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000248,32.,DMA_AOFFn2,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000024C,32.,DMA_MLAOFFn2,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000250,32.,DMA_NUMn2,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000254,32.,DMA_ITERn2,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000258,32.,DMA_CSn2,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000260,32.,DMA_SADDRn3,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000264,32.,DMA_DADDRn3,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000268,32.,DMA_AOFFn3,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000026C,32.,DMA_MLAOFFn3,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000270,32.,DMA_NUMn3,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000274,32.,DMA_ITERn3,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000278,32.,DMA_CSn3,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000280,32.,DMA_SADDRn4,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000284,32.,DMA_DADDRn4,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000288,32.,DMA_AOFFn4,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000028C,32.,DMA_MLAOFFn4,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000290,32.,DMA_NUMn4,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000294,32.,DMA_ITERn4,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000298,32.,DMA_CSn4,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000002A0,32.,DMA_SADDRn5,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000002A4,32.,DMA_DADDRn5,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000002A8,32.,DMA_AOFFn5,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000002AC,32.,DMA_MLAOFFn5,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000002B0,32.,DMA_NUMn5,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000002B4,32.,DMA_ITERn5,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000002B8,32.,DMA_CSn5,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000002C0,32.,DMA_SADDRn6,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000002C4,32.,DMA_DADDRn6,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000002C8,32.,DMA_AOFFn6,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000002CC,32.,DMA_MLAOFFn6,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000002D0,32.,DMA_NUMn6,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000002D4,32.,DMA_ITERn6,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000002D8,32.,DMA_CSn6,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000002E0,32.,DMA_SADDRn7,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000002E4,32.,DMA_DADDRn7,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000002E8,32.,DMA_AOFFn7,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000002EC,32.,DMA_MLAOFFn7,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000002F0,32.,DMA_NUMn7,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000002F4,32.,DMA_ITERn7,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000002F8,32.,DMA_CSn7,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000300,32.,DMA_SADDRn8,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000304,32.,DMA_DADDRn8,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000308,32.,DMA_AOFFn8,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000030C,32.,DMA_MLAOFFn8,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000310,32.,DMA_NUMn8,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000314,32.,DMA_ITERn8,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000318,32.,DMA_CSn8,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000320,32.,DMA_SADDRn9,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000324,32.,DMA_DADDRn9,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000328,32.,DMA_AOFFn9,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000032C,32.,DMA_MLAOFFn9,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000330,32.,DMA_NUMn9,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000334,32.,DMA_ITERn9,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000338,32.,DMA_CSn9,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000340,32.,DMA_SADDRn10,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000344,32.,DMA_DADDRn10,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000348,32.,DMA_AOFFn10,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000034C,32.,DMA_MLAOFFn10,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000350,32.,DMA_NUMn10,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000354,32.,DMA_ITERn10,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000358,32.,DMA_CSn10,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000360,32.,DMA_SADDRn11,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000364,32.,DMA_DADDRn11,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000368,32.,DMA_AOFFn11,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000036C,32.,DMA_MLAOFFn11,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000370,32.,DMA_NUMn11,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000374,32.,DMA_ITERn11,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000378,32.,DMA_CSn11,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x00000380,32.,DMA_SADDRn12,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x00000384,32.,DMA_DADDRn12,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x00000388,32.,DMA_AOFFn12,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x0000038C,32.,DMA_MLAOFFn12,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x00000390,32.,DMA_NUMn12,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x00000394,32.,DMA_ITERn12,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x00000398,32.,DMA_CSn12,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000003A0,32.,DMA_SADDRn13,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000003A4,32.,DMA_DADDRn13,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000003A8,32.,DMA_AOFFn13,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000003AC,32.,DMA_MLAOFFn13,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000003B0,32.,DMA_NUMn13,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000003B4,32.,DMA_ITERn13,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000003B8,32.,DMA_CSn13,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000003C0,32.,DMA_SADDRn14,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000003C4,32.,DMA_DADDRn14,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000003C8,32.,DMA_AOFFn14,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000003CC,32.,DMA_MLAOFFn14,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000003D0,32.,DMA_NUMn14,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000003D4,32.,DMA_ITERn14,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000003D8,32.,DMA_CSn14,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x000003E0,32.,DMA_SADDRn15,'DMA channel n source address register(DMA_SADDRn)',,,,rw
,,,SADDR,'Channel n source address',0.,31.,,rw
,0x000003E4,32.,DMA_DADDRn15,'DMA channel n destination address register(DMA_DADDRn)',,,,rw
,,,DADDR,'Channel n destination address',0.,31.,,rw
,0x000003E8,32.,DMA_AOFFn15,'DMA channel n address offset register(DMA_AOFFn)',,,,rw
,,,SAOFF,'Channel n source address offset',0.,15.,,rw
,,,DAOFF,'Channel n destination address offset',16.,31.,,rw
,0x000003EC,32.,DMA_MLAOFFn15,'DMA channel n Major loop address offset register(DMA_MLAOFFn)',,,,rw
,,,MLSAOFF,'Channel n major loop source address offset',0.,15.,,rw
,,,MLDAOFF,'Channel n major loop destination address offset',16.,31.,,rw
,0x000003F0,32.,DMA_NUMn15,'DMA channel n number of transfer data(DMA_NUMn)',,,,rw
,,,NUM,'Channel n number of transfer data in a minor loop',0.,31.,,rw
,0x000003F4,32.,DMA_ITERn15,'DMA channel n Iteration number register(DMA_ITERn)',,,,rw
,,,MLITER,'Channel n minor loop iteration number',0.,15.,,rw
,,,MLSTA,'Channel n minor loop status',16.,31.,,rw
,0x000003F8,32.,DMA_CSn15,'DMA channel n control and status register(DMA_CSn)',,,,rw
,,,START,'Channel n software start',0.,0.,,rw
,,,INTE,'Channel n DMA major loop done interrupt enable',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,REQDIS,'Channel n DMA hardware request disable',3.,3.,,rw
,,,RSVD_5_4,'Reserved',4.,5.,,rw
,,,BUSY,'Channel n busy status',6.,6.,,rw
,,,DONE,'Channel n DMA transfer done flag',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,DSIZE,'Channel n destination data transfer size',16.,17.,,rw
,,,RSVD_23_18,'Reserved',18.,23.,,rw
,,,SSIZE,'Channel n source data transfer size',24.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
tree.end
base ad:0x40009000
tree "DMUX"
,0x00000000,32.,DMA_MUX_CHn_CFG0,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,DMA_MUX_CHn_CFG1,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000008,32.,DMA_MUX_CHn_CFG2,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000000C,32.,DMA_MUX_CHn_CFG3,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000010,32.,DMA_MUX_CHn_CFG4,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000014,32.,DMA_MUX_CHn_CFG5,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000018,32.,DMA_MUX_CHn_CFG6,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000001C,32.,DMA_MUX_CHn_CFG7,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000020,32.,DMA_MUX_CHn_CFG8,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000024,32.,DMA_MUX_CHn_CFG9,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000028,32.,DMA_MUX_CHn_CFG10,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000002C,32.,DMA_MUX_CHn_CFG11,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000030,32.,DMA_MUX_CHn_CFG12,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000034,32.,DMA_MUX_CHn_CFG13,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000038,32.,DMA_MUX_CHn_CFG14,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000003C,32.,DMA_MUX_CHn_CFG15,'DMA Channel Mux Configuration Register(DMA_MUX_CHn_CFG)',,,,rw
,,,ENABLE,'DMA MUX Enable',0.,0.,,rw
,,,SRC_MUX,'DMA MUX Source',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
tree.end
base ad:0x4000A000
tree "SMPU"
,0x00000000,32.,SMPU_VERID,'Version ID register(SMPU_VERID)',,,,rd
,,,VERID,'version ID',0.,3.,,rd
,,,NSP,'number of slave ports',4.,7.,,rd
,,,NMRC,'number of memory region configuration',8.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000004,32.,SMPU_CS,'control and status register(SMPU_CS)',,,,rw
,,,S0ERR,'slave port 0 error status',0.,0.,,rw
,,,S1ERR,'slave port 1 error status',1.,1.,,rw
,,,S2ERR,'slave port 2 error status',2.,2.,,rw
,,,S3ERR,'slave port 3 error status',3.,3.,,rw
,,,RSVD_7_4,'Reserved',4.,7.,,rw
,,,GLBEN,'global SMPU enable',8.,8.,,rw
,,,RSVD_31_9,'Reserved',9.,31.,,rw
,0x00000010,32.,SMPU_Sn_EA0,'slave port n error address register(SMPU_Sn_EA)',,,,rd
,,,EADDR,'slave port n error address',0.,31.,,rd
,0x00000014,32.,SMPU_Sn_EA1,'slave port n error address register(SMPU_Sn_EA)',,,,rd
,,,EADDR,'slave port n error address',0.,31.,,rd
,0x00000018,32.,SMPU_Sn_EA2,'slave port n error address register(SMPU_Sn_EA)',,,,rd
,,,EADDR,'slave port n error address',0.,31.,,rd
,0x0000001C,32.,SMPU_Sn_EA3,'slave port n error address register(SMPU_Sn_EA)',,,,rd
,,,EADDR,'slave port n error address',0.,31.,,rd
,0x00000030,32.,SMPU_Sn_ES0,'slave port n error status register(SMPU_Sn_ES)',,,,rd
,,,EMRC,'error detected by memory region configuration',0.,15.,,rd
,,,RSVD_23_16,'Reserved',16.,23.,,rd
,,,EMN,'error access master number',24.,27.,,rd
,,,EATTR,'error instruction/data access ',28.,28.,,rd
,,,EUS,'error user/supervisor access',29.,29.,,rd
,,,RSVD_30,'Reserved',30.,30.,,rd
,,,ERW,'error read/write access',31.,31.,,rd
,0x00000034,32.,SMPU_Sn_ES1,'slave port n error status register(SMPU_Sn_ES)',,,,rd
,,,EMRC,'error detected by memory region configuration',0.,15.,,rd
,,,RSVD_23_16,'Reserved',16.,23.,,rd
,,,EMN,'error access master number',24.,27.,,rd
,,,EATTR,'error instruction/data access ',28.,28.,,rd
,,,EUS,'error user/supervisor access',29.,29.,,rd
,,,RSVD_30,'Reserved',30.,30.,,rd
,,,ERW,'error read/write access',31.,31.,,rd
,0x00000038,32.,SMPU_Sn_ES2,'slave port n error status register(SMPU_Sn_ES)',,,,rd
,,,EMRC,'error detected by memory region configuration',0.,15.,,rd
,,,RSVD_23_16,'Reserved',16.,23.,,rd
,,,EMN,'error access master number',24.,27.,,rd
,,,EATTR,'error instruction/data access ',28.,28.,,rd
,,,EUS,'error user/supervisor access',29.,29.,,rd
,,,RSVD_30,'Reserved',30.,30.,,rd
,,,ERW,'error read/write access',31.,31.,,rd
,0x0000003C,32.,SMPU_Sn_ES3,'slave port n error status register(SMPU_Sn_ES)',,,,rd
,,,EMRC,'error detected by memory region configuration',0.,15.,,rd
,,,RSVD_23_16,'Reserved',16.,23.,,rd
,,,EMN,'error access master number',24.,27.,,rd
,,,EATTR,'error instruction/data access ',28.,28.,,rd
,,,EUS,'error user/supervisor access',29.,29.,,rd
,,,RSVD_30,'Reserved',30.,30.,,rd
,,,ERW,'error read/write access',31.,31.,,rd
,0x00000100,32.,SMPU_MRCn_W00,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000104,32.,SMPU_MRCn_W10,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000108,32.,SMPU_MRCn_W20,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000010C,32.,SMPU_MRCn_W30,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000110,32.,SMPU_MRCn_W01,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000114,32.,SMPU_MRCn_W11,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000118,32.,SMPU_MRCn_W21,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000011C,32.,SMPU_MRCn_W31,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000120,32.,SMPU_MRCn_W02,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000124,32.,SMPU_MRCn_W12,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000128,32.,SMPU_MRCn_W22,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000012C,32.,SMPU_MRCn_W32,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000130,32.,SMPU_MRCn_W03,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000134,32.,SMPU_MRCn_W13,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000138,32.,SMPU_MRCn_W23,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000013C,32.,SMPU_MRCn_W33,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000140,32.,SMPU_MRCn_W04,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000144,32.,SMPU_MRCn_W14,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000148,32.,SMPU_MRCn_W24,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000014C,32.,SMPU_MRCn_W34,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000150,32.,SMPU_MRCn_W05,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000154,32.,SMPU_MRCn_W15,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000158,32.,SMPU_MRCn_W25,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000015C,32.,SMPU_MRCn_W35,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000160,32.,SMPU_MRCn_W06,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000164,32.,SMPU_MRCn_W16,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000168,32.,SMPU_MRCn_W26,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000016C,32.,SMPU_MRCn_W36,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000170,32.,SMPU_MRCn_W07,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000174,32.,SMPU_MRCn_W17,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000178,32.,SMPU_MRCn_W27,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000017C,32.,SMPU_MRCn_W37,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000180,32.,SMPU_MRCn_W08,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000184,32.,SMPU_MRCn_W18,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000188,32.,SMPU_MRCn_W28,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000018C,32.,SMPU_MRCn_W38,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x00000190,32.,SMPU_MRCn_W09,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x00000194,32.,SMPU_MRCn_W19,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x00000198,32.,SMPU_MRCn_W29,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000019C,32.,SMPU_MRCn_W39,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001A0,32.,SMPU_MRCn_W010,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001A4,32.,SMPU_MRCn_W110,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001A8,32.,SMPU_MRCn_W210,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001AC,32.,SMPU_MRCn_W310,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001B0,32.,SMPU_MRCn_W011,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001B4,32.,SMPU_MRCn_W111,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001B8,32.,SMPU_MRCn_W211,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001BC,32.,SMPU_MRCn_W311,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001C0,32.,SMPU_MRCn_W012,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001C4,32.,SMPU_MRCn_W112,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001C8,32.,SMPU_MRCn_W212,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001CC,32.,SMPU_MRCn_W312,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001D0,32.,SMPU_MRCn_W013,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001D4,32.,SMPU_MRCn_W113,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001D8,32.,SMPU_MRCn_W213,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001DC,32.,SMPU_MRCn_W313,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001E0,32.,SMPU_MRCn_W014,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001E4,32.,SMPU_MRCn_W114,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001E8,32.,SMPU_MRCn_W214,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001EC,32.,SMPU_MRCn_W314,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
,0x000001F0,32.,SMPU_MRCn_W015,'memory region n configuration word 0 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,SADDR,'memory region n configuration start address',5.,31.,,rw
,0x000001F4,32.,SMPU_MRCn_W115,'memory region n configuration word 1 register',,,,rw
,,,RSVD_4_0,'Reserved',0.,4.,,rw
,,,EADDR,'memory region n configuration end address',5.,31.,,rw
,0x000001F8,32.,SMPU_MRCn_W215,'memory region n configuration word 2 register',,,,rw
,,,M0UX,'Bus master 0 user mode execute access control',0.,0.,,rw
,,,M0UW,'Bus master 0 user mode write access control',1.,1.,,rw
,,,M0UR,'Bus master 0 user mode read access control',2.,2.,,rw
,,,M0SM,'Bus master 0 supervisor mode access control',3.,4.,,rw
,,,RSVD_5,'Reserved',5.,5.,,rw
,,,M1UX,'Bus master 1 user mode execute access control',6.,6.,,rw
,,,M1UW,'Bus master 1 user mode write access control',7.,7.,,rw
,,,M1UR,'Bus master 1 user mode read access control',8.,8.,,rw
,,,M1SM,'Bus master 1 supervisor mode access control',9.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,M2UX,'Bus master 2 user mode execute access control',12.,12.,,rw
,,,M2UW,'Bus master 2 user mode write access control',13.,13.,,rw
,,,M2UR,'Bus master 2 user mode read access control',14.,14.,,rw
,,,M2SM,'Bus master 2 supervisor mode access control',15.,16.,,rw
,,,RSVD_17,'Reserved',17.,17.,,rw
,,,M3UX,'Bus master 3 user mode execute access control',18.,18.,,rw
,,,M3UW,'Bus master 3 user mode write access control',19.,19.,,rw
,,,M3UR,'Bus master 3 user mode read access control',20.,20.,,rw
,,,M3SM,'Bus master 3 supervisor mode access control',21.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x000001FC,32.,SMPU_MRCn_W315,'memory region n configuration word 3 register',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,EN,'memory region n configuration enable',16.,16.,,rw
,,,RSVD_31_17,'Reserved and read as 0',17.,31.,,rw
tree.end
base ad:0x4000B000
tree "EIRU"
,0x00000000,32.,EIRU_CR,'EIRU control register(EIRU_CR)',,,,rd
,,,SRAM0_ER_DIS,'SRAM0 ECC Read Disable',0.,0.,,rd
,,,SRAM0_EW_DIS,'SRAM0 ECC Write Disable',1.,1.,,rd
,,,SRAM0_ESB_DIS,'SRAM0 ECC Single Bit Disable',2.,2.,,rd
,,,SRAM0_EMB_DIS,'SRAM0 ECC Multi Bit Disable',3.,3.,,rd
,,,SRAM0_EEI_EN,'SRAM0 ECC Error Injection Enable',4.,4.,,rd
,,,RSVD_7_5,'Reserved',5.,7.,,rd
,,,SRAM1_ER_DIS,'SRAM1 ECC Read Disable',8.,8.,,rd
,,,SRAM1_EW_DIS,'SRAM1 ECC Write Disable',9.,9.,,rd
,,,SRAM1_ESB_DIS,'SRAM1 ECC Single Bit Disable',10.,10.,,rd
,,,SRAM1_EMB_DIS,'SRAM1 ECC Multi Bit Disable',11.,11.,,rd
,,,SRAM1_EEI_EN,'SRAM1 ECC Error Injection Enable',12.,12.,,rd
,,,RSVD_30_13,'Reserved',13.,30.,,rd
,,,LOCK,'Global EIRU Lock Bit',31.,31.,,rd
,0x00000004,32.,EIRU_EEIADDR,'EIRU ECC Error Injection Address(EIRU_EEIADDR)',,,,rw
,,,RSVD_1_0,'Reserved',0.,1.,,rw
,,,EEIADDR,'ECC Error Injection Address',2.,31.,,rw
,0x00000010,32.,EIRU_SRAMn_EESR0,'EIRU SRAM n ECC Error Status Register(EIRU_SRAMn_EESR)',,,,rd
,,,EFPROT,'ECC Fault HPROT',0.,3.,,rd
,,,EFSIZE,'ECC Fault HSIZE',4.,6.,,rd
,,,EFW,'ECC Fault Write',7.,7.,,rd
,,,EFMST,'ECC Fault Master',8.,15.,,rd
,,,RSVD_28_16,'Reserved',16.,28.,,rd
,,,SBERR,'ECC Single-bit Error',29.,29.,,rd
,,,MBERR,'ECC Multi-bit Error',30.,30.,,rd
,,,OVERRUN,'ECC Error Overrun',31.,31.,,rd
,0x00000014,32.,EIRU_SRAMn_FADDR0,'EIRU SRAM n ECC Fault Address Register(EIRU_SRAMn_FADDR)',,,,rd
,,,EFADDR,'ECC Fault Address',0.,31.,,rd
,0x00000018,32.,EIRU_SRAMn_FDATA0,'EIRU SRAM n ECC Fault Data Register(EIRU_SRAMn_FDATA)',,,,rd
,,,EFDATA,'ECC Fault Data',0.,31.,,rd
,0x0000001C,32.,EIRU_SRAMn_ECCMASK0,'EIRU SRAM n ECC Check Bit MASK(EIRU_SRAMn_ECCMASK)',,,,rw
,,,ECCMASK,'ECC Bit Mask',0.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000020,32.,EIRU_SRAMn_DATAMASK0,'EIRU SRAM n DATA Bit MASK(EIRU_CHn_DATAMASK)',,,,rw
,,,DATAMASK,'Data bit mask',0.,31.,,rw
,0x00000030,32.,EIRU_SRAMn_EESR1,'EIRU SRAM n ECC Error Status Register(EIRU_SRAMn_EESR)',,,,rd
,,,EFPROT,'ECC Fault HPROT',0.,3.,,rd
,,,EFSIZE,'ECC Fault HSIZE',4.,6.,,rd
,,,EFW,'ECC Fault Write',7.,7.,,rd
,,,EFMST,'ECC Fault Master',8.,15.,,rd
,,,RSVD_28_16,'Reserved',16.,28.,,rd
,,,SBERR,'ECC Single-bit Error',29.,29.,,rd
,,,MBERR,'ECC Multi-bit Error',30.,30.,,rd
,,,OVERRUN,'ECC Error Overrun',31.,31.,,rd
,0x00000034,32.,EIRU_SRAMn_FADDR1,'EIRU SRAM n ECC Fault Address Register(EIRU_SRAMn_FADDR)',,,,rd
,,,EFADDR,'ECC Fault Address',0.,31.,,rd
,0x00000038,32.,EIRU_SRAMn_FDATA1,'EIRU SRAM n ECC Fault Data Register(EIRU_SRAMn_FDATA)',,,,rd
,,,EFDATA,'ECC Fault Data',0.,31.,,rd
,0x0000003C,32.,EIRU_SRAMn_ECCMASK1,'EIRU SRAM n ECC Check Bit MASK(EIRU_SRAMn_ECCMASK)',,,,rw
,,,ECCMASK,'ECC Bit Mask',0.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000040,32.,EIRU_SRAMn_DATAMASK1,'EIRU SRAM n DATA Bit MASK(EIRU_CHn_DATAMASK)',,,,rw
,,,DATAMASK,'Data bit mask',0.,31.,,rw
tree.end
base ad:0x4000C000
tree "TIM0"
,0x00000000,32.,TIM0_TIM_TIMEBASE,'TIM timebase register(TIM_TIMEBASE)',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,TIM0_TIM_CNT,'TIM counter register(TIM_CNT)',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,TIM0_TIM_CNTINIT,'TIM counter initial value register(TIM_CNTINIT)',,,,rw
,,,CNTINIT,'16-bit counter initial value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,TIM0_TIM_MOD,'TIM counter modulo value register(TIM_MOD)',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,TIM0_TIM_GLBCR,'TIM global control register(TIM_GLBCR)',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,RLDIE,'Reload interrupt enable',8.,8.,,rw
,,,TOIE,'Timer overflow interrupt enable',9.,9.,,rw
,,,CNTMODE,'16-bit counter counting mode',10.,10.,,rw
,,,INIT,'Initialize the channels output',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000014,32.,TIM0_TIM_GLBSR,'TIM global status register(TIM_GLBSR)',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF,'Reload flag',8.,8.,,rw
,,,TOF,'Timer overflow flag',9.,9.,,rw
,,,WPDIS,'Write protection disable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000018,32.,TIM0_TIM_CMCn0,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000001C,32.,TIM0_TIM_CMCn1,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000020,32.,TIM0_TIM_CMCn2,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000024,32.,TIM0_TIM_CMCn3,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000028,32.,TIM0_TIM_CMCn4,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000002C,32.,TIM0_TIM_CMCn5,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000030,32.,TIM0_TIM_CMCn6,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000034,32.,TIM0_TIM_CMCn7,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000038,32.,TIM0_TIM_CCVn0,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TIM0_TIM_CCVn1,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TIM0_TIM_CCVn2,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000044,32.,TIM0_TIM_CCVn3,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TIM0_TIM_CCVn4,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TIM0_TIM_CCVn5,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TIM0_TIM_CCVn6,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TIM0_TIM_CCVn7,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TIM0_TIM_OUTCR,'TIM output control register(TIM_OUTCR)',,,,rw
,,,INIT0,'Channel 0 initialization value ',0.,0.,,rw
,,,INIT1,'Channel 1 initialization value ',1.,1.,,rw
,,,INIT2,'Channel 2 initialization value ',2.,2.,,rw
,,,INIT3,'Channel 3 initialization value ',3.,3.,,rw
,,,INIT4,'Channel 4 initialization value ',4.,4.,,rw
,,,INIT5,'Channel 5 initialization value ',5.,5.,,rw
,,,INIT6,'Channel 6 initialization value ',6.,6.,,rw
,,,INIT7,'Channel 7 initialization value ',7.,7.,,rw
,,,POL0,'Channel 0 output polarity ',8.,8.,,rw
,,,POL1,'Channel 1 output polarity ',9.,9.,,rw
,,,POL2,'Channel 2 output polarity ',10.,10.,,rw
,,,POL3,'Channel 3 output polarity ',11.,11.,,rw
,,,POL4,'Channel 4 output polarity ',12.,12.,,rw
,,,POL5,'Channel 5 output polarity ',13.,13.,,rw
,,,POL6,'Channel 6 output polarity ',14.,14.,,rw
,,,POL7,'Channel 7 output polarity ',15.,15.,,rw
,,,TRIGE0,'Channel 0 match trigger enable',16.,16.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',17.,17.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',18.,18.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',19.,19.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',20.,20.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',21.,21.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',22.,22.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',23.,23.,,rw
,,,INITRIGE,'Initialization trigger enable',24.,24.,,rw
,,,TRIGF,'Channel output trigger flag',25.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x0000005C,32.,TIM0_TIM_OUTSWCR,'TIM channel output software control register(TIM_OUTSWCR)',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TIM0_TIM_PCR,'TIM pairs of channel control register(TIM_PCR)',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',2.,2.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',3.,3.,,rw
,,,DECAPEN0,'Dual edge capture enable for pairs of channel 0',4.,4.,,rw
,,,DECAP0,'Dual edge capture mode for pairs of channel 0',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',10.,10.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',11.,11.,,rw
,,,DECAPEN1,'Dual edge capture enable for pairs of channel 1',12.,12.,,rw
,,,DECAP1,'Dual edge capture mode for pairs of channel 1',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',18.,18.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',19.,19.,,rw
,,,DECAPEN2,'Dual edge capture enable for pairs of channel 2',20.,20.,,rw
,,,DECAP2,'Dual edge capture mode for pairs of channel 2',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',26.,26.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',27.,27.,,rw
,,,DECAPEN3,'Dual edge capture enable for pairs of channel 3',28.,28.,,rw
,,,DECAP3,'Dual edge capture mode for pairs of channel 3',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000064,32.,TIM0_TIM_FILTER,'TIM input filter register(TIM_FILTER)',,,,rw
,,,FILVAL0,'Channel 0 input filter value',0.,3.,,rw
,,,FILVAL1,'Channel 1 input filter value',4.,7.,,rw
,,,FILVAL2,'Channel 2 input filter value',8.,11.,,rw
,,,FILVAL3,'Channel 3 input filter value',12.,15.,,rw
,,,DTPS,'Deadtime prescaler value',16.,17.,,rw
,,,DTVAL,'Deadtime insertion value',18.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
,0x00000068,32.,TIM0_TIM_FLTCR,'TIM fault control register(TIM_FLTCR)',,,,rw
,,,FAULTEN0,'Fault input enable 0',0.,0.,,rw
,,,FIFEN0,'Fault input filter enable 0 ',1.,1.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity ',2.,2.,,rw
,,,FAULTEN1,'Fault input enable 1',3.,3.,,rw
,,,FIFEN1,'Fault input filter enable 1 ',4.,4.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity ',5.,5.,,rw
,,,FLTIE,'Fault interrupt enable',6.,6.,,rw
,,,FLTCEN,'Falut control enable',7.,7.,,rw
,,,FLTCM,'Falut clear mode',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,FIFVAL,'Fault input filter value',11.,14.,,rw
,,,FSTATE,'Fault output status ',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,TIM0_TIM_FLTSR,'TIM fault status register(TIM_FLTSR)',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FAULTF,'Fault detection flag',4.,4.,,rw
,,,FAULTIN,'Fault inputs value',5.,5.,,rw
,,,WPEN,'Write protection enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000070,32.,TIM0_TIM_SYNC,'TIM synchronization register(TIM_SYNC)',,,,rw
,,,SWTRIG,'PWM synchronization software trigger',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,SYNCINIT,'CNTINIT register synchronization',8.,8.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',9.,9.,,rw
,,,RSVD_17_10,'Reserved',10.,17.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',18.,18.,,rw
,,,SWRSTCNT,'Software trigger activate CNT register synchronization',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000074,32.,TIM0_TIM_RELOAD,'TIM reload register(TIM_RELOAD)',,,,rw
,,,CH0SEL,'Channel 0 select',0.,0.,,rw
,,,CH1SEL,'Channel 1 select',1.,1.,,rw
,,,CH2SEL,'Channel 2 select',2.,2.,,rw
,,,CH3SEL,'Channel 3 select',3.,3.,,rw
,,,CH4SEL,'Channel 4 select',4.,4.,,rw
,,,CH5SEL,'Channel 5 select',5.,5.,,rw
,,,CH6SEL,'Channel 6 select',6.,6.,,rw
,,,CH7SEL,'Channel 7 select',7.,7.,,rw
,,,LOADEN,'Reload enable',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,HCSEL,'Half cycle reload select',11.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,LDFREQ,'Reload frequency',16.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000078,32.,TIM0_TIM_HCV,'TIM half cycle reload value register(TIM_HCV)',,,,rw
,,,HCV,'Half cycle reload value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
tree.end
base ad:0x4000D000
tree "TIM1"
,0x00000000,32.,TIM1_TIM_TIMEBASE,'TIM timebase register(TIM_TIMEBASE)',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,TIM1_TIM_CNT,'TIM counter register(TIM_CNT)',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,TIM1_TIM_CNTINIT,'TIM counter initial value register(TIM_CNTINIT)',,,,rw
,,,CNTINIT,'16-bit counter initial value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,TIM1_TIM_MOD,'TIM counter modulo value register(TIM_MOD)',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,TIM1_TIM_GLBCR,'TIM global control register(TIM_GLBCR)',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,RLDIE,'Reload interrupt enable',8.,8.,,rw
,,,TOIE,'Timer overflow interrupt enable',9.,9.,,rw
,,,CNTMODE,'16-bit counter counting mode',10.,10.,,rw
,,,INIT,'Initialize the channels output',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000014,32.,TIM1_TIM_GLBSR,'TIM global status register(TIM_GLBSR)',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF,'Reload flag',8.,8.,,rw
,,,TOF,'Timer overflow flag',9.,9.,,rw
,,,WPDIS,'Write protection disable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000018,32.,TIM1_TIM_CMCn0,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000001C,32.,TIM1_TIM_CMCn1,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000020,32.,TIM1_TIM_CMCn2,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000024,32.,TIM1_TIM_CMCn3,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000028,32.,TIM1_TIM_CMCn4,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000002C,32.,TIM1_TIM_CMCn5,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000030,32.,TIM1_TIM_CMCn6,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000034,32.,TIM1_TIM_CMCn7,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000038,32.,TIM1_TIM_CCVn0,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TIM1_TIM_CCVn1,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TIM1_TIM_CCVn2,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000044,32.,TIM1_TIM_CCVn3,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TIM1_TIM_CCVn4,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TIM1_TIM_CCVn5,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TIM1_TIM_CCVn6,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TIM1_TIM_CCVn7,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TIM1_TIM_OUTCR,'TIM output control register(TIM_OUTCR)',,,,rw
,,,INIT0,'Channel 0 initialization value ',0.,0.,,rw
,,,INIT1,'Channel 1 initialization value ',1.,1.,,rw
,,,INIT2,'Channel 2 initialization value ',2.,2.,,rw
,,,INIT3,'Channel 3 initialization value ',3.,3.,,rw
,,,INIT4,'Channel 4 initialization value ',4.,4.,,rw
,,,INIT5,'Channel 5 initialization value ',5.,5.,,rw
,,,INIT6,'Channel 6 initialization value ',6.,6.,,rw
,,,INIT7,'Channel 7 initialization value ',7.,7.,,rw
,,,POL0,'Channel 0 output polarity ',8.,8.,,rw
,,,POL1,'Channel 1 output polarity ',9.,9.,,rw
,,,POL2,'Channel 2 output polarity ',10.,10.,,rw
,,,POL3,'Channel 3 output polarity ',11.,11.,,rw
,,,POL4,'Channel 4 output polarity ',12.,12.,,rw
,,,POL5,'Channel 5 output polarity ',13.,13.,,rw
,,,POL6,'Channel 6 output polarity ',14.,14.,,rw
,,,POL7,'Channel 7 output polarity ',15.,15.,,rw
,,,TRIGE0,'Channel 0 match trigger enable',16.,16.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',17.,17.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',18.,18.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',19.,19.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',20.,20.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',21.,21.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',22.,22.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',23.,23.,,rw
,,,INITRIGE,'Initialization trigger enable',24.,24.,,rw
,,,TRIGF,'Channel output trigger flag',25.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x0000005C,32.,TIM1_TIM_OUTSWCR,'TIM channel output software control register(TIM_OUTSWCR)',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TIM1_TIM_PCR,'TIM pairs of channel control register(TIM_PCR)',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',2.,2.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',3.,3.,,rw
,,,DECAPEN0,'Dual edge capture enable for pairs of channel 0',4.,4.,,rw
,,,DECAP0,'Dual edge capture mode for pairs of channel 0',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',10.,10.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',11.,11.,,rw
,,,DECAPEN1,'Dual edge capture enable for pairs of channel 1',12.,12.,,rw
,,,DECAP1,'Dual edge capture mode for pairs of channel 1',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',18.,18.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',19.,19.,,rw
,,,DECAPEN2,'Dual edge capture enable for pairs of channel 2',20.,20.,,rw
,,,DECAP2,'Dual edge capture mode for pairs of channel 2',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',26.,26.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',27.,27.,,rw
,,,DECAPEN3,'Dual edge capture enable for pairs of channel 3',28.,28.,,rw
,,,DECAP3,'Dual edge capture mode for pairs of channel 3',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000064,32.,TIM1_TIM_FILTER,'TIM input filter register(TIM_FILTER)',,,,rw
,,,FILVAL0,'Channel 0 input filter value',0.,3.,,rw
,,,FILVAL1,'Channel 1 input filter value',4.,7.,,rw
,,,FILVAL2,'Channel 2 input filter value',8.,11.,,rw
,,,FILVAL3,'Channel 3 input filter value',12.,15.,,rw
,,,DTPS,'Deadtime prescaler value',16.,17.,,rw
,,,DTVAL,'Deadtime insertion value',18.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
,0x00000068,32.,TIM1_TIM_FLTCR,'TIM fault control register(TIM_FLTCR)',,,,rw
,,,FAULTEN0,'Fault input enable 0',0.,0.,,rw
,,,FIFEN0,'Fault input filter enable 0 ',1.,1.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity ',2.,2.,,rw
,,,FAULTEN1,'Fault input enable 1',3.,3.,,rw
,,,FIFEN1,'Fault input filter enable 1 ',4.,4.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity ',5.,5.,,rw
,,,FLTIE,'Fault interrupt enable',6.,6.,,rw
,,,FLTCEN,'Falut control enable',7.,7.,,rw
,,,FLTCM,'Falut clear mode',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,FIFVAL,'Fault input filter value',11.,14.,,rw
,,,FSTATE,'Fault output status ',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,TIM1_TIM_FLTSR,'TIM fault status register(TIM_FLTSR)',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FAULTF,'Fault detection flag',4.,4.,,rw
,,,FAULTIN,'Fault inputs value',5.,5.,,rw
,,,WPEN,'Write protection enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000070,32.,TIM1_TIM_SYNC,'TIM synchronization register(TIM_SYNC)',,,,rw
,,,SWTRIG,'PWM synchronization software trigger',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,SYNCINIT,'CNTINIT register synchronization',8.,8.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',9.,9.,,rw
,,,RSVD_17_10,'Reserved',10.,17.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',18.,18.,,rw
,,,SWRSTCNT,'Software trigger activate CNT register synchronization',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000074,32.,TIM1_TIM_RELOAD,'TIM reload register(TIM_RELOAD)',,,,rw
,,,CH0SEL,'Channel 0 select',0.,0.,,rw
,,,CH1SEL,'Channel 1 select',1.,1.,,rw
,,,CH2SEL,'Channel 2 select',2.,2.,,rw
,,,CH3SEL,'Channel 3 select',3.,3.,,rw
,,,CH4SEL,'Channel 4 select',4.,4.,,rw
,,,CH5SEL,'Channel 5 select',5.,5.,,rw
,,,CH6SEL,'Channel 6 select',6.,6.,,rw
,,,CH7SEL,'Channel 7 select',7.,7.,,rw
,,,LOADEN,'Reload enable',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,HCSEL,'Half cycle reload select',11.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,LDFREQ,'Reload frequency',16.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000078,32.,TIM1_TIM_HCV,'TIM half cycle reload value register(TIM_HCV)',,,,rw
,,,HCV,'Half cycle reload value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
tree.end
base ad:0x4000E000
tree "MCPWM0"
,0x00000000,32.,MCPWM0_MCPWM_TIMEBASE,'MCPWM time base register',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,MCPWM0_MCPWM_CNTn0,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,MCPWM0_MCPWM_CNTn1,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,MCPWM0_MCPWM_CNTn2,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,MCPWM0_MCPWM_CNTn3,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000014,32.,MCPWM0_MCPWM_MODn0,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000018,32.,MCPWM0_MCPWM_MODn1,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000001C,32.,MCPWM0_MCPWM_MODn2,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000020,32.,MCPWM0_MCPWM_MODn3,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000024,32.,MCPWM0_MCPWM_DTVALn0,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000028,32.,MCPWM0_MCPWM_DTVALn1,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x0000002C,32.,MCPWM0_MCPWM_DTVALn2,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000030,32.,MCPWM0_MCPWM_DTVALn3,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000034,32.,MCPWM0_MCPWM_GLBCR,'MCPWM global control register',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,CNTM0,'counter 0 counting mode',8.,8.,,rw
,,,CNTM1,'counter 1 counting mode',9.,9.,,rw
,,,CNTM2,'counter 2 counting mode',10.,10.,,rw
,,,CNTM3,'counter 3 counting mode',11.,11.,,rw
,,,CNTEN0,'counter 0 enable',12.,12.,,rw
,,,CNTEN1,'counter 1 enable',13.,13.,,rw
,,,CNTEN2,'counter 2 enable',14.,14.,,rw
,,,CNTEN3,'counter 3 enable',15.,15.,,rw
,,,RLDIE0,'Reload interrupt enable 0',16.,16.,,rw
,,,RLDIE1,'Reload interrupt enable 1',17.,17.,,rw
,,,RLDIE2,'Reload interrupt enable 2',18.,18.,,rw
,,,RLDIE3,'Reload interrupt enable 3',19.,19.,,rw
,,,TOIE0,'counter 0 overflow interrupt enable',20.,20.,,rw
,,,TOIE1,'counter 1 overflow interrupt enable',21.,21.,,rw
,,,TOIE2,'counter 2 overflow interrupt enable',22.,22.,,rw
,,,TOIE3,'counter 3 overflow interrupt enable',23.,23.,,rw
,,,RSVD_29_24,'Reserved',24.,29.,,rw
,,,WPEN,'Write protection enable',30.,30.,,rw
,,,GLBCNTEN,'global counter enable',31.,31.,,rw
,0x00000038,32.,MCPWM0_MCPWM_GLBSR,'MCPWM global status register',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF0,'counter 0 reload flag',8.,8.,,rw
,,,RLDF1,'counter 1 reload flag',9.,9.,,rw
,,,RLDF2,'counter 2 reload flag',10.,10.,,rw
,,,RLDF3,'counter 3 reload flag',11.,11.,,rw
,,,TOF0,'counter 0 timer overflow flag',12.,12.,,rw
,,,TOF1,'counter 1 timer overflow flag',13.,13.,,rw
,,,TOF2,'counter 2 timer overflow flag',14.,14.,,rw
,,,TOF3,'counter 3 timer overflow flag',15.,15.,,rw
,,,WPDIS,'Write protection disable',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x0000003C,32.,MCPWM0_MCPWM_CFGn0,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000040,32.,MCPWM0_MCPWM_CFGn1,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000044,32.,MCPWM0_MCPWM_CFGn2,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000048,32.,MCPWM0_MCPWM_CFGn3,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x0000004C,32.,MCPWM0_MCPWM_CFGn4,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000050,32.,MCPWM0_MCPWM_CFGn5,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000054,32.,MCPWM0_MCPWM_CFGn6,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000058,32.,MCPWM0_MCPWM_CFGn7,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x0000005C,32.,MCPWM0_MCPWM_CVn0,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,MCPWM0_MCPWM_CVn1,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000064,32.,MCPWM0_MCPWM_CVn2,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000068,32.,MCPWM0_MCPWM_CVn3,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,MCPWM0_MCPWM_CVn4,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000070,32.,MCPWM0_MCPWM_CVn5,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000074,32.,MCPWM0_MCPWM_CVn6,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000078,32.,MCPWM0_MCPWM_CVn7,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000007C,32.,MCPWM0_MCPWM_OUTCR,'MCPWM  output control register ',,,,rw
,,,POL0,'Channel 0 output polarity ',0.,0.,,rw
,,,POL1,'Channel 1 output polarity ',1.,1.,,rw
,,,POL2,'Channel 2 output polarity ',2.,2.,,rw
,,,POL3,'Channel 3 output polarity ',3.,3.,,rw
,,,POL4,'Channel 4 output polarity ',4.,4.,,rw
,,,POL5,'Channel 5 output polarity ',5.,5.,,rw
,,,POL6,'Channel 6 output polarity ',6.,6.,,rw
,,,POL7,'Channel 7 output polarity ',7.,7.,,rw
,,,OFFVAL0,'channel 0 output value when counter is off',8.,8.,,rw
,,,OFFVAL1,'channel 1 output value when counter is off',9.,9.,,rw
,,,OFFVAL2,'channel 2 output value when counter is off',10.,10.,,rw
,,,OFFVAL3,'channel 3 output value when counter is off',11.,11.,,rw
,,,OFFVAL4,'channel 4 output value when counter is off',12.,12.,,rw
,,,OFFVAL5,'channel 5 output value when counter is off',13.,13.,,rw
,,,OFFVAL6,'channel 6 output value when counter is off',14.,14.,,rw
,,,OFFVAL7,'channel 7 output value when counter is off',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000080,32.,MCPWM0_MCPWM_OUTTRIG,'MCPWM output trigger register ',,,,rw
,,,TRIGE0,'Channel 0 match trigger enable',0.,0.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',1.,1.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',2.,2.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',3.,3.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',4.,4.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',5.,5.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',6.,6.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',7.,7.,,rw
,,,INITRIGE,'Initialization trigger enable',8.,8.,,rw
,,,TRIGF,'Channel output trigger flag',9.,9.,,rw
,,,RSVD_31_10,'Reserved',10.,31.,,rw
,0x00000084,32.,MCPWM0_MCPWM_OUTSWCR,'MCPWM channel output software control register ',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000088,32.,MCPWM0_MCPWM_PCR,'MCPWM pairs of channel control register',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',2.,2.,,rw
,,,ASYMEN0,'asymmetric PWM output enable for pairs of channel 0',3.,3.,,rw
,,,CVSEL0,'channel value selection of PWM output for pairs of channel 0',4.,4.,,rw
,,,PEC0,'pulse edge control for pairs of channel 0',5.,5.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',6.,6.,,rw
,,,RSVD_7,'Reserved',7.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',10.,10.,,rw
,,,ASYMEN1,'asymmetric PWM output enable for pairs of channel 1',11.,11.,,rw
,,,CVSEL1,'channel value selection of PWM output for pairs of channel 1',12.,12.,,rw
,,,PEC1,'pulse edge control for pairs of channel 1',13.,13.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',14.,14.,,rw
,,,RSVD_15,'Reserved',15.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',18.,18.,,rw
,,,ASYMEN2,'asymmetric PWM output enable for pairs of channel 2',19.,19.,,rw
,,,CVSEL2,'channel value selection of PWM output for pairs of channel 2',20.,20.,,rw
,,,PEC2,'pulse edge control for pairs of channel 2',21.,21.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',22.,22.,,rw
,,,RSVD_23,'Reserved',23.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',26.,26.,,rw
,,,ASYMEN3,'asymmetric PWM output enable for pairs of channel 3',27.,27.,,rw
,,,CVSEL3,'channel value selection of PWM output for pairs of channel 3',28.,28.,,rw
,,,PEC3,'pulse edge control for pairs of channel 3',29.,29.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',30.,30.,,rw
,,,RSVD_31,'Reserved',31.,31.,,rw
,0x0000008C,32.,MCPWM0_MCPWM_FLTCR,'MCPWM fault control control register',,,,rw
,,,FIFEN0,'Fault input filter enable 0',0.,0.,,rw
,,,FIFEN1,'Fault input filter enable 1',1.,1.,,rw
,,,FIFEN2,'Fault input filter enable 2 ',2.,2.,,rw
,,,FIFEN3,'Fault input filter enable 3 ',3.,3.,,rw
,,,FLTEN0,'Fault input enable 0',4.,4.,,rw
,,,FLTEN1,'Fault input enable 1',5.,5.,,rw
,,,FLTEN2,'Fault input enable 2',6.,6.,,rw
,,,FLTEN3,'Fault input enable 3',7.,7.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity',8.,8.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity',9.,9.,,rw
,,,FLTPOL2,'Fault input channel 2 polarity ',10.,10.,,rw
,,,FLTPOL3,'Fault input channel 3 polarity ',11.,11.,,rw
,,,FLTIE,'Fault interrupt enable',12.,12.,,rw
,,,FLTCM,'Falut clear mode',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FIFVAL,'Fault input filter value',16.,19.,,rw
,,,FSTATE,'Fault output status ',20.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000090,32.,MCPWM0_MCPWM_FLTSR,'MCPWM fault status register',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,FAULTF2,'Fault detection flag of fault channel 2',2.,2.,,rw
,,,FAULTF3,'Fault detection flag of fault channel 3',3.,3.,,rw
,,,FAULTFA,'Fault detection flag A',4.,4.,,rw
,,,FAULTFB,'Fault detection flag B',5.,5.,,rw
,,,FAULTINA,'Fault input A value',6.,6.,,rw
,,,FAULTINB,'Fault input B value',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000094,32.,MCPWM0_MCPWM_FLTASS,'MCPWM fault A safe status value register',,,,rw
,,,FLTASS0,'Channel 0 safe status value for fault A',0.,0.,,rw
,,,FLTASS1,'Channel 1 safe status value for fault A',1.,1.,,rw
,,,FLTASS2,'Channel 2 safe status value for fault A',2.,2.,,rw
,,,FLTASS3,'Channel 3 safe status value for fault A',3.,3.,,rw
,,,FLTASS4,'Channel 4 safe status value for fault A',4.,4.,,rw
,,,FLTASS5,'Channel 5 safe status value for fault A',5.,5.,,rw
,,,FLTASS6,'Channel 6 safe status value for fault A',6.,6.,,rw
,,,FLTASS7,'Channel 7 safe status value for fault A',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000098,32.,MCPWM0_MCPWM_FLTBSS,'MCPWM fault B safe status value register',,,,rw
,,,FLTBSS0,'Channel 0 safe status value for fault B',0.,0.,,rw
,,,FLTBSS1,'Channel 1 safe status value for fault B',1.,1.,,rw
,,,FLTBSS2,'Channel 2 safe status value for fault B',2.,2.,,rw
,,,FLTBSS3,'Channel 3 safe status value for fault B',3.,3.,,rw
,,,FLTBSS4,'Channel 4 safe status value for fault B',4.,4.,,rw
,,,FLTBSS5,'Channel 5 safe status value for fault B',5.,5.,,rw
,,,FLTBSS6,'Channel 6 safe status value for fault B',6.,6.,,rw
,,,FLTBSS7,'Channel 7 safe status value for fault B',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000009C,32.,MCPWM0_MCPWM_SYNC,'MCPWM synchronization register',,,,rw
,,,SWTRIG,'software trigger synchronization',0.,0.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',1.,1.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',2.,2.,,rw
,,,SWRSTCNT,'Software trigger reset counter ',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000A0,32.,MCPWM0_MCPWM_RELOAD,'MCPWM reload register',,,,rw
,,,CPWMFCR0,'CPWM full cycle reload enable 0',0.,0.,,rw
,,,CPWMFCR1,'CPWM full cycle reload enable 1',1.,1.,,rw
,,,CPWMFCR2,'CPWM full cycle reload enable 2',2.,2.,,rw
,,,CPWMFCR3,'CPWM full cycle reload enable 3',3.,3.,,rw
,,,CPWMHCR0,'CPWM half cycle reload enable 0',4.,4.,,rw
,,,CPWMHCR1,'CPWM half cycle reload enable 1',5.,5.,,rw
,,,CPWMHCR2,'CPWM half cycle reload enable 2',6.,6.,,rw
,,,CPWMHCR3,'CPWM half cycle reload enable 3',7.,7.,,rw
,,,LOADEN0,'Reload enable for pairs of channel 0',8.,8.,,rw
,,,LOADEN1,'Reload enable for pairs of channel 1',9.,9.,,rw
,,,LOADEN2,'Reload enable for pairs of channel 2',10.,10.,,rw
,,,LOADEN3,'Reload enable for pairs of channel 3',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x000000A4,32.,MCPWM0_MCPWM_LDFREQ,'MCPWM reload frequency register',,,,rw
,,,LDFREQ0,'Reload frequency 0',0.,4.,,rw
,,,RSVD_7_5,'Reserved',5.,7.,,rw
,,,LDFREQ1,'Reload frequency 1',8.,12.,,rw
,,,RSVD_15_13,'Reserved',13.,15.,,rw
,,,LDFREQ2,'Reload frequency 2',16.,20.,,rw
,,,RSVD_23_21,'Reserved',21.,23.,,rw
,,,LDFREQ3,'Reload frequency 3',24.,28.,,rw
,,,RSVD_31_29,'Reserved',29.,31.,,rw
,0x00000100,32.,MCPWM0_MCPWM_MODn_DITHER0,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,MCPWM0_MCPWM_MODn_DITHER1,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000108,32.,MCPWM0_MCPWM_MODn_DITHER2,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000010C,32.,MCPWM0_MCPWM_MODn_DITHER3,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000110,32.,MCPWM0_MCPWM_CVn_DITHER0,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000114,32.,MCPWM0_MCPWM_CVn_DITHER1,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000118,32.,MCPWM0_MCPWM_CVn_DITHER2,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000011C,32.,MCPWM0_MCPWM_CVn_DITHER3,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000120,32.,MCPWM0_MCPWM_CVn_DITHER4,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000124,32.,MCPWM0_MCPWM_CVn_DITHER5,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000128,32.,MCPWM0_MCPWM_CVn_DITHER6,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000012C,32.,MCPWM0_MCPWM_CVn_DITHER7,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
tree.end
base ad:0x4000F000
tree "TDG0"
,0x00000000,32.,TDG0_TDG_VERID,'TDG Version Idenfication(TDG_VERID)',,,,rd
,,,MINOR,'Minor version',0.,3.,,rd
,,,MAJOR,'Major version',4.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,TDG0_TDG_PARAM,'TDG Parameter(TDG_PARAM)',,,,rd
,,,DOPNUM,'Delay output point number',0.,3.,,rd
,,,CHNUM,'Channel number',4.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,TDG0_TDG_CTRL1,'TDG Control Registers 1(TDG_CTRL1)',,,,rw
,,,TDGEN,'TDG enabled.',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,TRIGS,'Trig source select',4.,4.,,rw
,,,CNTMD,'Count mode',5.,5.,,rw
,,,CLRMD,'Counter clear mode',6.,6.,,rw
,,,RSVD_7,'Reserved',7.,7.,,rw
,,,PRES,'Prescalar',8.,10.,,rw
,,,RSVD_15_11,'Reserved',11.,15.,,rw
,,,CFGUP,'Configuration update',16.,16.,,rw
,,,SWTRG,'Software trig',17.,17.,,rw
,,,RSVD_19_18,'Reserved',18.,19.,,rw
,,,UPMD,'Channel configulation update mode',20.,21.,,rw
,,,RSVD_31_22,'Reserved',22.,31.,,rw
,0x0000000C,32.,TDG0_TDG_CTRL2,'TDG Control Register 2(TDG_CTRL2)',,,,rw
,,,CDO0IE,'Channel 0 complete delay output interrupt enable',0.,0.,,rw
,,,CDO1IE,'Channel 1 complete delay output interrupt enable',1.,1.,,rw
,,,CDO2IE,'Channel 2 complete delay output interrupt enable',2.,2.,,rw
,,,CDO3IE,'Channel 3 complete delay output interrupt enable',3.,3.,,rw
,,,CDO4IE,'Channel 4 complete delay output interrupt enable',4.,4.,,rw
,,,CDO5IE,'Channel 5 complete delay output interrupt enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,ERRIE,'Error interrupt enable',8.,8.,,rw
,,,RSVD_15_9,'Reserved',9.,15.,,rw
,,,CH0E,'Channel 0 enable',16.,16.,,rw
,,,CH1E,'Channel 1 enable',17.,17.,,rw
,,,CH2E,'Channel 2 enable',18.,18.,,rw
,,,CH3E,'Channel 3 enable',19.,19.,,rw
,,,CH4E,'Channel 4 enable',20.,20.,,rw
,,,CH5E,'Channel 5 enable',21.,21.,,rw
,,,RSVD_31_22,'Reserved',22.,31.,,rw
,0x00000010,32.,TDG0_TDG_STAT,'TDG Status Register(TDG_STAT)',,,,rw
,,,CDO0IF,'Channel 0 complete delay output interrupt flag',0.,0.,,rw
,,,CDO1IF,'Channel 1 complete delay output interrupt flag',1.,1.,,rw
,,,CDO2IF,'Channel 2 complete delay output interrupt flag',2.,2.,,rw
,,,CDO3IF,'Channel 3 complete delay output interrupt flag',3.,3.,,rw
,,,CDO4IF,'Channel 4 complete delay output interrupt flag',4.,4.,,rw
,,,CDO5IF,'Channel 5 complete delay output interrupt flag',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,ERRIF,'Error interrupt flag',8.,8.,,rw
,,,RSVD_31_9,'Reserved',9.,31.,,rw
,0x00000014,32.,TDG0_TDG_MOD,'TDG Modulate Register(TDG_MOD)',,,,rw
,,,MOD,'TDG Modulate value. ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000018,32.,TDG0_TDG_CNT,'TDG Counter Register(TDG_CNT)',,,,rd
,,,CNT,'TDG counter value. ',0.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x0000001C,32.,TDG0_TDG_CHnCTRL0,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000020,32.,TDG0_TDG_CHnDO0OFS0,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000024,32.,TDG0_TDG_CHnDO1OFS0,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000028,32.,TDG0_TDG_CHnDO2OFS0,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000002C,32.,TDG0_TDG_CHnDO3OFS0,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000030,32.,TDG0_TDG_CHnDO4OFS0,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000034,32.,TDG0_TDG_CHnDO5OFS0,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000038,32.,TDG0_TDG_CHnDO6OFS0,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TDG0_TDG_CHnDO7OFS0,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TDG0_TDG_CHnCDOINTDLY0,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000044,32.,TDG0_TDG_CHnCTRL1,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TDG0_TDG_CHnDO0OFS1,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TDG0_TDG_CHnDO1OFS1,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TDG0_TDG_CHnDO2OFS1,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TDG0_TDG_CHnDO3OFS1,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TDG0_TDG_CHnDO4OFS1,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000005C,32.,TDG0_TDG_CHnDO5OFS1,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TDG0_TDG_CHnDO6OFS1,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000064,32.,TDG0_TDG_CHnDO7OFS1,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000068,32.,TDG0_TDG_CHnCDOINTDLY1,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x0000006C,32.,TDG0_TDG_CHnCTRL2,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000070,32.,TDG0_TDG_CHnDO0OFS2,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000074,32.,TDG0_TDG_CHnDO1OFS2,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000078,32.,TDG0_TDG_CHnDO2OFS2,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000007C,32.,TDG0_TDG_CHnDO3OFS2,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000080,32.,TDG0_TDG_CHnDO4OFS2,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000084,32.,TDG0_TDG_CHnDO5OFS2,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000088,32.,TDG0_TDG_CHnDO6OFS2,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000008C,32.,TDG0_TDG_CHnDO7OFS2,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000090,32.,TDG0_TDG_CHnCDOINTDLY2,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000094,32.,TDG0_TDG_CHnCTRL3,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000098,32.,TDG0_TDG_CHnDO0OFS3,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000009C,32.,TDG0_TDG_CHnDO1OFS3,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A0,32.,TDG0_TDG_CHnDO2OFS3,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A4,32.,TDG0_TDG_CHnDO3OFS3,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A8,32.,TDG0_TDG_CHnDO4OFS3,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000AC,32.,TDG0_TDG_CHnDO5OFS3,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B0,32.,TDG0_TDG_CHnDO6OFS3,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B4,32.,TDG0_TDG_CHnDO7OFS3,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B8,32.,TDG0_TDG_CHnCDOINTDLY3,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x000000BC,32.,TDG0_TDG_CHnCTRL4,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C0,32.,TDG0_TDG_CHnDO0OFS4,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C4,32.,TDG0_TDG_CHnDO1OFS4,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C8,32.,TDG0_TDG_CHnDO2OFS4,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000CC,32.,TDG0_TDG_CHnDO3OFS4,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D0,32.,TDG0_TDG_CHnDO4OFS4,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D4,32.,TDG0_TDG_CHnDO5OFS4,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D8,32.,TDG0_TDG_CHnDO6OFS4,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000DC,32.,TDG0_TDG_CHnDO7OFS4,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000E0,32.,TDG0_TDG_CHnCDOINTDLY4,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x000000E4,32.,TDG0_TDG_CHnCTRL5,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000E8,32.,TDG0_TDG_CHnDO0OFS5,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000EC,32.,TDG0_TDG_CHnDO1OFS5,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F0,32.,TDG0_TDG_CHnDO2OFS5,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F4,32.,TDG0_TDG_CHnDO3OFS5,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F8,32.,TDG0_TDG_CHnDO4OFS5,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000FC,32.,TDG0_TDG_CHnDO5OFS5,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000100,32.,TDG0_TDG_CHnDO6OFS5,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000104,32.,TDG0_TDG_CHnDO7OFS5,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000108,32.,TDG0_TDG_CHnCDOINTDLY5,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
tree.end
base ad:0x40018000
tree "TIM2"
,0x00000000,32.,TIM2_TIM_TIMEBASE,'TIM timebase register(TIM_TIMEBASE)',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,TIM2_TIM_CNT,'TIM counter register(TIM_CNT)',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,TIM2_TIM_CNTINIT,'TIM counter initial value register(TIM_CNTINIT)',,,,rw
,,,CNTINIT,'16-bit counter initial value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,TIM2_TIM_MOD,'TIM counter modulo value register(TIM_MOD)',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,TIM2_TIM_GLBCR,'TIM global control register(TIM_GLBCR)',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,RLDIE,'Reload interrupt enable',8.,8.,,rw
,,,TOIE,'Timer overflow interrupt enable',9.,9.,,rw
,,,CNTMODE,'16-bit counter counting mode',10.,10.,,rw
,,,INIT,'Initialize the channels output',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000014,32.,TIM2_TIM_GLBSR,'TIM global status register(TIM_GLBSR)',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF,'Reload flag',8.,8.,,rw
,,,TOF,'Timer overflow flag',9.,9.,,rw
,,,WPDIS,'Write protection disable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000018,32.,TIM2_TIM_CMCn0,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000001C,32.,TIM2_TIM_CMCn1,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000020,32.,TIM2_TIM_CMCn2,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000024,32.,TIM2_TIM_CMCn3,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000028,32.,TIM2_TIM_CMCn4,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000002C,32.,TIM2_TIM_CMCn5,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000030,32.,TIM2_TIM_CMCn6,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000034,32.,TIM2_TIM_CMCn7,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000038,32.,TIM2_TIM_CCVn0,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TIM2_TIM_CCVn1,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TIM2_TIM_CCVn2,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000044,32.,TIM2_TIM_CCVn3,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TIM2_TIM_CCVn4,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TIM2_TIM_CCVn5,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TIM2_TIM_CCVn6,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TIM2_TIM_CCVn7,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TIM2_TIM_OUTCR,'TIM output control register(TIM_OUTCR)',,,,rw
,,,INIT0,'Channel 0 initialization value ',0.,0.,,rw
,,,INIT1,'Channel 1 initialization value ',1.,1.,,rw
,,,INIT2,'Channel 2 initialization value ',2.,2.,,rw
,,,INIT3,'Channel 3 initialization value ',3.,3.,,rw
,,,INIT4,'Channel 4 initialization value ',4.,4.,,rw
,,,INIT5,'Channel 5 initialization value ',5.,5.,,rw
,,,INIT6,'Channel 6 initialization value ',6.,6.,,rw
,,,INIT7,'Channel 7 initialization value ',7.,7.,,rw
,,,POL0,'Channel 0 output polarity ',8.,8.,,rw
,,,POL1,'Channel 1 output polarity ',9.,9.,,rw
,,,POL2,'Channel 2 output polarity ',10.,10.,,rw
,,,POL3,'Channel 3 output polarity ',11.,11.,,rw
,,,POL4,'Channel 4 output polarity ',12.,12.,,rw
,,,POL5,'Channel 5 output polarity ',13.,13.,,rw
,,,POL6,'Channel 6 output polarity ',14.,14.,,rw
,,,POL7,'Channel 7 output polarity ',15.,15.,,rw
,,,TRIGE0,'Channel 0 match trigger enable',16.,16.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',17.,17.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',18.,18.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',19.,19.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',20.,20.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',21.,21.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',22.,22.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',23.,23.,,rw
,,,INITRIGE,'Initialization trigger enable',24.,24.,,rw
,,,TRIGF,'Channel output trigger flag',25.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x0000005C,32.,TIM2_TIM_OUTSWCR,'TIM channel output software control register(TIM_OUTSWCR)',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TIM2_TIM_PCR,'TIM pairs of channel control register(TIM_PCR)',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',2.,2.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',3.,3.,,rw
,,,DECAPEN0,'Dual edge capture enable for pairs of channel 0',4.,4.,,rw
,,,DECAP0,'Dual edge capture mode for pairs of channel 0',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',10.,10.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',11.,11.,,rw
,,,DECAPEN1,'Dual edge capture enable for pairs of channel 1',12.,12.,,rw
,,,DECAP1,'Dual edge capture mode for pairs of channel 1',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',18.,18.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',19.,19.,,rw
,,,DECAPEN2,'Dual edge capture enable for pairs of channel 2',20.,20.,,rw
,,,DECAP2,'Dual edge capture mode for pairs of channel 2',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',26.,26.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',27.,27.,,rw
,,,DECAPEN3,'Dual edge capture enable for pairs of channel 3',28.,28.,,rw
,,,DECAP3,'Dual edge capture mode for pairs of channel 3',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000064,32.,TIM2_TIM_FILTER,'TIM input filter register(TIM_FILTER)',,,,rw
,,,FILVAL0,'Channel 0 input filter value',0.,3.,,rw
,,,FILVAL1,'Channel 1 input filter value',4.,7.,,rw
,,,FILVAL2,'Channel 2 input filter value',8.,11.,,rw
,,,FILVAL3,'Channel 3 input filter value',12.,15.,,rw
,,,DTPS,'Deadtime prescaler value',16.,17.,,rw
,,,DTVAL,'Deadtime insertion value',18.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
,0x00000068,32.,TIM2_TIM_FLTCR,'TIM fault control register(TIM_FLTCR)',,,,rw
,,,FAULTEN0,'Fault input enable 0',0.,0.,,rw
,,,FIFEN0,'Fault input filter enable 0 ',1.,1.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity ',2.,2.,,rw
,,,FAULTEN1,'Fault input enable 1',3.,3.,,rw
,,,FIFEN1,'Fault input filter enable 1 ',4.,4.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity ',5.,5.,,rw
,,,FLTIE,'Fault interrupt enable',6.,6.,,rw
,,,FLTCEN,'Falut control enable',7.,7.,,rw
,,,FLTCM,'Falut clear mode',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,FIFVAL,'Fault input filter value',11.,14.,,rw
,,,FSTATE,'Fault output status ',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,TIM2_TIM_FLTSR,'TIM fault status register(TIM_FLTSR)',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FAULTF,'Fault detection flag',4.,4.,,rw
,,,FAULTIN,'Fault inputs value',5.,5.,,rw
,,,WPEN,'Write protection enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000070,32.,TIM2_TIM_SYNC,'TIM synchronization register(TIM_SYNC)',,,,rw
,,,SWTRIG,'PWM synchronization software trigger',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,SYNCINIT,'CNTINIT register synchronization',8.,8.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',9.,9.,,rw
,,,RSVD_17_10,'Reserved',10.,17.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',18.,18.,,rw
,,,SWRSTCNT,'Software trigger activate CNT register synchronization',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000074,32.,TIM2_TIM_RELOAD,'TIM reload register(TIM_RELOAD)',,,,rw
,,,CH0SEL,'Channel 0 select',0.,0.,,rw
,,,CH1SEL,'Channel 1 select',1.,1.,,rw
,,,CH2SEL,'Channel 2 select',2.,2.,,rw
,,,CH3SEL,'Channel 3 select',3.,3.,,rw
,,,CH4SEL,'Channel 4 select',4.,4.,,rw
,,,CH5SEL,'Channel 5 select',5.,5.,,rw
,,,CH6SEL,'Channel 6 select',6.,6.,,rw
,,,CH7SEL,'Channel 7 select',7.,7.,,rw
,,,LOADEN,'Reload enable',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,HCSEL,'Half cycle reload select',11.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,LDFREQ,'Reload frequency',16.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000078,32.,TIM2_TIM_HCV,'TIM half cycle reload value register(TIM_HCV)',,,,rw
,,,HCV,'Half cycle reload value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
tree.end
base ad:0x40019000
tree "TIM3"
,0x00000000,32.,TIM3_TIM_TIMEBASE,'TIM timebase register(TIM_TIMEBASE)',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,TIM3_TIM_CNT,'TIM counter register(TIM_CNT)',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,TIM3_TIM_CNTINIT,'TIM counter initial value register(TIM_CNTINIT)',,,,rw
,,,CNTINIT,'16-bit counter initial value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,TIM3_TIM_MOD,'TIM counter modulo value register(TIM_MOD)',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,TIM3_TIM_GLBCR,'TIM global control register(TIM_GLBCR)',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,RLDIE,'Reload interrupt enable',8.,8.,,rw
,,,TOIE,'Timer overflow interrupt enable',9.,9.,,rw
,,,CNTMODE,'16-bit counter counting mode',10.,10.,,rw
,,,INIT,'Initialize the channels output',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000014,32.,TIM3_TIM_GLBSR,'TIM global status register(TIM_GLBSR)',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF,'Reload flag',8.,8.,,rw
,,,TOF,'Timer overflow flag',9.,9.,,rw
,,,WPDIS,'Write protection disable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000018,32.,TIM3_TIM_CMCn0,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000001C,32.,TIM3_TIM_CMCn1,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000020,32.,TIM3_TIM_CMCn2,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000024,32.,TIM3_TIM_CMCn3,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000028,32.,TIM3_TIM_CMCn4,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000002C,32.,TIM3_TIM_CMCn5,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000030,32.,TIM3_TIM_CMCn6,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000034,32.,TIM3_TIM_CMCn7,'TIM channel n mode configuration register(TIM_CMCn)',,,,rw
,,,ELS,'Edge or level select',0.,1.,,rw
,,,CMS,'Channel mode select',2.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,ICRST,'Input capture reset',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000038,32.,TIM3_TIM_CCVn0,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TIM3_TIM_CCVn1,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TIM3_TIM_CCVn2,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000044,32.,TIM3_TIM_CCVn3,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TIM3_TIM_CCVn4,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TIM3_TIM_CCVn5,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TIM3_TIM_CCVn6,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TIM3_TIM_CCVn7,'TIM channel n capture/compare value register(TIM_CCVn)',,,,rw
,,,CCV,'Channel capture/compare value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TIM3_TIM_OUTCR,'TIM output control register(TIM_OUTCR)',,,,rw
,,,INIT0,'Channel 0 initialization value ',0.,0.,,rw
,,,INIT1,'Channel 1 initialization value ',1.,1.,,rw
,,,INIT2,'Channel 2 initialization value ',2.,2.,,rw
,,,INIT3,'Channel 3 initialization value ',3.,3.,,rw
,,,INIT4,'Channel 4 initialization value ',4.,4.,,rw
,,,INIT5,'Channel 5 initialization value ',5.,5.,,rw
,,,INIT6,'Channel 6 initialization value ',6.,6.,,rw
,,,INIT7,'Channel 7 initialization value ',7.,7.,,rw
,,,POL0,'Channel 0 output polarity ',8.,8.,,rw
,,,POL1,'Channel 1 output polarity ',9.,9.,,rw
,,,POL2,'Channel 2 output polarity ',10.,10.,,rw
,,,POL3,'Channel 3 output polarity ',11.,11.,,rw
,,,POL4,'Channel 4 output polarity ',12.,12.,,rw
,,,POL5,'Channel 5 output polarity ',13.,13.,,rw
,,,POL6,'Channel 6 output polarity ',14.,14.,,rw
,,,POL7,'Channel 7 output polarity ',15.,15.,,rw
,,,TRIGE0,'Channel 0 match trigger enable',16.,16.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',17.,17.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',18.,18.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',19.,19.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',20.,20.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',21.,21.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',22.,22.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',23.,23.,,rw
,,,INITRIGE,'Initialization trigger enable',24.,24.,,rw
,,,TRIGF,'Channel output trigger flag',25.,25.,,rw
,,,RSVD_31_26,'Reserved',26.,31.,,rw
,0x0000005C,32.,TIM3_TIM_OUTSWCR,'TIM channel output software control register(TIM_OUTSWCR)',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TIM3_TIM_PCR,'TIM pairs of channel control register(TIM_PCR)',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',2.,2.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',3.,3.,,rw
,,,DECAPEN0,'Dual edge capture enable for pairs of channel 0',4.,4.,,rw
,,,DECAP0,'Dual edge capture mode for pairs of channel 0',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',10.,10.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',11.,11.,,rw
,,,DECAPEN1,'Dual edge capture enable for pairs of channel 1',12.,12.,,rw
,,,DECAP1,'Dual edge capture mode for pairs of channel 1',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',18.,18.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',19.,19.,,rw
,,,DECAPEN2,'Dual edge capture enable for pairs of channel 2',20.,20.,,rw
,,,DECAP2,'Dual edge capture mode for pairs of channel 2',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',26.,26.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',27.,27.,,rw
,,,DECAPEN3,'Dual edge capture enable for pairs of channel 3',28.,28.,,rw
,,,DECAP3,'Dual edge capture mode for pairs of channel 3',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000064,32.,TIM3_TIM_FILTER,'TIM input filter register(TIM_FILTER)',,,,rw
,,,FILVAL0,'Channel 0 input filter value',0.,3.,,rw
,,,FILVAL1,'Channel 1 input filter value',4.,7.,,rw
,,,FILVAL2,'Channel 2 input filter value',8.,11.,,rw
,,,FILVAL3,'Channel 3 input filter value',12.,15.,,rw
,,,DTPS,'Deadtime prescaler value',16.,17.,,rw
,,,DTVAL,'Deadtime insertion value',18.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
,0x00000068,32.,TIM3_TIM_FLTCR,'TIM fault control register(TIM_FLTCR)',,,,rw
,,,FAULTEN0,'Fault input enable 0',0.,0.,,rw
,,,FIFEN0,'Fault input filter enable 0 ',1.,1.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity ',2.,2.,,rw
,,,FAULTEN1,'Fault input enable 1',3.,3.,,rw
,,,FIFEN1,'Fault input filter enable 1 ',4.,4.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity ',5.,5.,,rw
,,,FLTIE,'Fault interrupt enable',6.,6.,,rw
,,,FLTCEN,'Falut control enable',7.,7.,,rw
,,,FLTCM,'Falut clear mode',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,FIFVAL,'Fault input filter value',11.,14.,,rw
,,,FSTATE,'Fault output status ',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,TIM3_TIM_FLTSR,'TIM fault status register(TIM_FLTSR)',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FAULTF,'Fault detection flag',4.,4.,,rw
,,,FAULTIN,'Fault inputs value',5.,5.,,rw
,,,WPEN,'Write protection enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000070,32.,TIM3_TIM_SYNC,'TIM synchronization register(TIM_SYNC)',,,,rw
,,,SWTRIG,'PWM synchronization software trigger',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,SYNCINIT,'CNTINIT register synchronization',8.,8.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',9.,9.,,rw
,,,RSVD_17_10,'Reserved',10.,17.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',18.,18.,,rw
,,,SWRSTCNT,'Software trigger activate CNT register synchronization',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000074,32.,TIM3_TIM_RELOAD,'TIM reload register(TIM_RELOAD)',,,,rw
,,,CH0SEL,'Channel 0 select',0.,0.,,rw
,,,CH1SEL,'Channel 1 select',1.,1.,,rw
,,,CH2SEL,'Channel 2 select',2.,2.,,rw
,,,CH3SEL,'Channel 3 select',3.,3.,,rw
,,,CH4SEL,'Channel 4 select',4.,4.,,rw
,,,CH5SEL,'Channel 5 select',5.,5.,,rw
,,,CH6SEL,'Channel 6 select',6.,6.,,rw
,,,CH7SEL,'Channel 7 select',7.,7.,,rw
,,,LOADEN,'Reload enable',8.,8.,,rw
,,,RSVD_10_9,'Reserved',9.,10.,,rw
,,,HCSEL,'Half cycle reload select',11.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,LDFREQ,'Reload frequency',16.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000078,32.,TIM3_TIM_HCV,'TIM half cycle reload value register(TIM_HCV)',,,,rw
,,,HCV,'Half cycle reload value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
tree.end
base ad:0x4001A000
tree "MCPWM1"
,0x00000000,32.,MCPWM1_MCPWM_TIMEBASE,'MCPWM time base register',,,,rw
,,,CKSRC,'clock source',0.,1.,,rw
,,,PSDIV,'Prescaler divider',2.,4.,,rw
,,,DBGM,'Debug mode',5.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000004,32.,MCPWM1_MCPWM_CNTn0,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,MCPWM1_MCPWM_CNTn1,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,MCPWM1_MCPWM_CNTn2,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,MCPWM1_MCPWM_CNTn3,'MCPWM counter n register',,,,rw
,,,CNT,'16-bit counter',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000014,32.,MCPWM1_MCPWM_MODn0,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000018,32.,MCPWM1_MCPWM_MODn1,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000001C,32.,MCPWM1_MCPWM_MODn2,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000020,32.,MCPWM1_MCPWM_MODn3,'MCPWM counter n modulo value register',,,,rw
,,,MOD,'16-bit counter modulo value',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000024,32.,MCPWM1_MCPWM_DTVALn0,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000028,32.,MCPWM1_MCPWM_DTVALn1,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x0000002C,32.,MCPWM1_MCPWM_DTVALn2,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000030,32.,MCPWM1_MCPWM_DTVALn3,'MCPWM deadtime value n register',,,,rw
,,,DTVAL,'deadtime value ',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000034,32.,MCPWM1_MCPWM_GLBCR,'MCPWM global control register',,,,rw
,,,CHOE0,'Channel 0 output enable',0.,0.,,rw
,,,CHOE1,'Channel 1 output enable',1.,1.,,rw
,,,CHOE2,'Channel 2 output enable',2.,2.,,rw
,,,CHOE3,'Channel 3 output enable',3.,3.,,rw
,,,CHOE4,'Channel 4 output enable',4.,4.,,rw
,,,CHOE5,'Channel 5 output enable',5.,5.,,rw
,,,CHOE6,'Channel 6 output enable',6.,6.,,rw
,,,CHOE7,'Channel 7 output enable',7.,7.,,rw
,,,CNTM0,'counter 0 counting mode',8.,8.,,rw
,,,CNTM1,'counter 1 counting mode',9.,9.,,rw
,,,CNTM2,'counter 2 counting mode',10.,10.,,rw
,,,CNTM3,'counter 3 counting mode',11.,11.,,rw
,,,CNTEN0,'counter 0 enable',12.,12.,,rw
,,,CNTEN1,'counter 1 enable',13.,13.,,rw
,,,CNTEN2,'counter 2 enable',14.,14.,,rw
,,,CNTEN3,'counter 3 enable',15.,15.,,rw
,,,RLDIE0,'Reload interrupt enable 0',16.,16.,,rw
,,,RLDIE1,'Reload interrupt enable 1',17.,17.,,rw
,,,RLDIE2,'Reload interrupt enable 2',18.,18.,,rw
,,,RLDIE3,'Reload interrupt enable 3',19.,19.,,rw
,,,TOIE0,'counter 0 overflow interrupt enable',20.,20.,,rw
,,,TOIE1,'counter 1 overflow interrupt enable',21.,21.,,rw
,,,TOIE2,'counter 2 overflow interrupt enable',22.,22.,,rw
,,,TOIE3,'counter 3 overflow interrupt enable',23.,23.,,rw
,,,RSVD_29_24,'Reserved',24.,29.,,rw
,,,WPEN,'Write protection enable',30.,30.,,rw
,,,GLBCNTEN,'global counter enable',31.,31.,,rw
,0x00000038,32.,MCPWM1_MCPWM_GLBSR,'MCPWM global status register',,,,rw
,,,CH0F,'Channel 0 flag',0.,0.,,rw
,,,CH1F,'Channel 1 flag',1.,1.,,rw
,,,CH2F,'Channel 2 flag',2.,2.,,rw
,,,CH3F,'Channel 3 flag',3.,3.,,rw
,,,CH4F,'Channel 4 flag',4.,4.,,rw
,,,CH5F,'Channel 5 flag',5.,5.,,rw
,,,CH6F,'Channel 6 flag',6.,6.,,rw
,,,CH7F,'Channel 7 flag',7.,7.,,rw
,,,RLDF0,'counter 0 reload flag',8.,8.,,rw
,,,RLDF1,'counter 1 reload flag',9.,9.,,rw
,,,RLDF2,'counter 2 reload flag',10.,10.,,rw
,,,RLDF3,'counter 3 reload flag',11.,11.,,rw
,,,TOF0,'counter 0 timer overflow flag',12.,12.,,rw
,,,TOF1,'counter 1 timer overflow flag',13.,13.,,rw
,,,TOF2,'counter 2 timer overflow flag',14.,14.,,rw
,,,TOF3,'counter 3 timer overflow flag',15.,15.,,rw
,,,WPDIS,'Write protection disable',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x0000003C,32.,MCPWM1_MCPWM_CFGn0,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000040,32.,MCPWM1_MCPWM_CFGn1,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000044,32.,MCPWM1_MCPWM_CFGn2,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000048,32.,MCPWM1_MCPWM_CFGn3,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x0000004C,32.,MCPWM1_MCPWM_CFGn4,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000050,32.,MCPWM1_MCPWM_CFGn5,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000054,32.,MCPWM1_MCPWM_CFGn6,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000058,32.,MCPWM1_MCPWM_CFGn7,'MCPWM channel n mode configuration register ',,,,rw
,,,CPP,'channel pulse polarity',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CHIE,'Channel interrupt enable',4.,4.,,rw
,,,CHF,'Channel flag',5.,5.,,rw
,,,DMA,'DMA enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x0000005C,32.,MCPWM1_MCPWM_CVn0,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,MCPWM1_MCPWM_CVn1,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000064,32.,MCPWM1_MCPWM_CVn2,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000068,32.,MCPWM1_MCPWM_CVn3,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000006C,32.,MCPWM1_MCPWM_CVn4,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000070,32.,MCPWM1_MCPWM_CVn5,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000074,32.,MCPWM1_MCPWM_CVn6,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000078,32.,MCPWM1_MCPWM_CVn7,'MCPWM channel n value register ',,,,rw
,,,CV,'channel value ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000007C,32.,MCPWM1_MCPWM_OUTCR,'MCPWM  output control register ',,,,rw
,,,POL0,'Channel 0 output polarity ',0.,0.,,rw
,,,POL1,'Channel 1 output polarity ',1.,1.,,rw
,,,POL2,'Channel 2 output polarity ',2.,2.,,rw
,,,POL3,'Channel 3 output polarity ',3.,3.,,rw
,,,POL4,'Channel 4 output polarity ',4.,4.,,rw
,,,POL5,'Channel 5 output polarity ',5.,5.,,rw
,,,POL6,'Channel 6 output polarity ',6.,6.,,rw
,,,POL7,'Channel 7 output polarity ',7.,7.,,rw
,,,OFFVAL0,'channel 0 output value when counter is off',8.,8.,,rw
,,,OFFVAL1,'channel 1 output value when counter is off',9.,9.,,rw
,,,OFFVAL2,'channel 2 output value when counter is off',10.,10.,,rw
,,,OFFVAL3,'channel 3 output value when counter is off',11.,11.,,rw
,,,OFFVAL4,'channel 4 output value when counter is off',12.,12.,,rw
,,,OFFVAL5,'channel 5 output value when counter is off',13.,13.,,rw
,,,OFFVAL6,'channel 6 output value when counter is off',14.,14.,,rw
,,,OFFVAL7,'channel 7 output value when counter is off',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000080,32.,MCPWM1_MCPWM_OUTTRIG,'MCPWM output trigger register ',,,,rw
,,,TRIGE0,'Channel 0 match trigger enable',0.,0.,,rw
,,,TRIGE1,'Channel 1 match trigger enable',1.,1.,,rw
,,,TRIGE2,'Channel 2 match trigger enable',2.,2.,,rw
,,,TRIGE3,'Channel 3 match trigger enable',3.,3.,,rw
,,,TRIGE4,'Channel 4 match trigger enable',4.,4.,,rw
,,,TRIGE5,'Channel 5 match trigger enable',5.,5.,,rw
,,,TRIGE6,'Channel 6 match trigger enable',6.,6.,,rw
,,,TRIGE7,'Channel 7 match trigger enable',7.,7.,,rw
,,,INITRIGE,'Initialization trigger enable',8.,8.,,rw
,,,TRIGF,'Channel output trigger flag',9.,9.,,rw
,,,RSVD_31_10,'Reserved',10.,31.,,rw
,0x00000084,32.,MCPWM1_MCPWM_OUTSWCR,'MCPWM channel output software control register ',,,,rw
,,,CH0OC,'Channel 0 output software control enable',0.,0.,,rw
,,,CH1OC,'Channel 1 output software control enable',1.,1.,,rw
,,,CH2OC,'Channel 2 output software control enable',2.,2.,,rw
,,,CH3OC,'Channel 3 output software control enable',3.,3.,,rw
,,,CH4OC,'Channel 4 output software control enable',4.,4.,,rw
,,,CH5OC,'Channel 5 output software control enable',5.,5.,,rw
,,,CH6OC,'Channel 6 output software control enable',6.,6.,,rw
,,,CH7OC,'Channel 7 output software control enable',7.,7.,,rw
,,,CH0OCV,'Channel 0 output software control value',8.,8.,,rw
,,,CH1OCV,'Channel 1 output software control value',9.,9.,,rw
,,,CH2OCV,'Channel 2 output software control value',10.,10.,,rw
,,,CH3OCV,'Channel 3 output software control value',11.,11.,,rw
,,,CH4OCV,'Channel 4 output software control value',12.,12.,,rw
,,,CH5OCV,'Channel 5 output software control value',13.,13.,,rw
,,,CH6OCV,'Channel 6 output software control value',14.,14.,,rw
,,,CH7OCV,'Channel 7 output software control value',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000088,32.,MCPWM1_MCPWM_PCR,'MCPWM pairs of channel control register',,,,rw
,,,FCTLEN0,'Fault control enabled for pairs of channel 0',0.,0.,,rw
,,,DTEN0,'Deadtime insertion enable for pairs of channel 0',1.,1.,,rw
,,,SYNCEN0,'Synchronization enable for pairs of channel 0',2.,2.,,rw
,,,ASYMEN0,'asymmetric PWM output enable for pairs of channel 0',3.,3.,,rw
,,,CVSEL0,'channel value selection of PWM output for pairs of channel 0',4.,4.,,rw
,,,PEC0,'pulse edge control for pairs of channel 0',5.,5.,,rw
,,,COMB0,'Combine enable for pairs of channel 0',6.,6.,,rw
,,,RSVD_7,'Reserved',7.,7.,,rw
,,,FCTLEN1,'Fault control enabled for pairs of channel 1',8.,8.,,rw
,,,DTEN1,'Deadtime insertion enable for pairs of channel 1',9.,9.,,rw
,,,SYNCEN1,'Synchronization enable for pairs of channel 1',10.,10.,,rw
,,,ASYMEN1,'asymmetric PWM output enable for pairs of channel 1',11.,11.,,rw
,,,CVSEL1,'channel value selection of PWM output for pairs of channel 1',12.,12.,,rw
,,,PEC1,'pulse edge control for pairs of channel 1',13.,13.,,rw
,,,COMB1,'Combine enable for pairs of channel 1',14.,14.,,rw
,,,RSVD_15,'Reserved',15.,15.,,rw
,,,FCTLEN2,'Fault control enabled for pairs of channel 2',16.,16.,,rw
,,,DTEN2,'Deadtime insertion enable for pairs of channel 2',17.,17.,,rw
,,,SYNCEN2,'Synchronization enable for pairs of channel 2',18.,18.,,rw
,,,ASYMEN2,'asymmetric PWM output enable for pairs of channel 2',19.,19.,,rw
,,,CVSEL2,'channel value selection of PWM output for pairs of channel 2',20.,20.,,rw
,,,PEC2,'pulse edge control for pairs of channel 2',21.,21.,,rw
,,,COMB2,'Combine enable for pairs of channel 2',22.,22.,,rw
,,,RSVD_23,'Reserved',23.,23.,,rw
,,,FCTLEN3,'Fault control enabled for pairs of channel 3',24.,24.,,rw
,,,DTEN3,'Deadtime insertion enable for pairs of channel 3',25.,25.,,rw
,,,SYNCEN3,'Synchronization enable for pairs of channel 3',26.,26.,,rw
,,,ASYMEN3,'asymmetric PWM output enable for pairs of channel 3',27.,27.,,rw
,,,CVSEL3,'channel value selection of PWM output for pairs of channel 3',28.,28.,,rw
,,,PEC3,'pulse edge control for pairs of channel 3',29.,29.,,rw
,,,COMB3,'Combine enable for pairs of channel 3',30.,30.,,rw
,,,RSVD_31,'Reserved',31.,31.,,rw
,0x0000008C,32.,MCPWM1_MCPWM_FLTCR,'MCPWM fault control control register',,,,rw
,,,FIFEN0,'Fault input filter enable 0',0.,0.,,rw
,,,FIFEN1,'Fault input filter enable 1',1.,1.,,rw
,,,FIFEN2,'Fault input filter enable 2 ',2.,2.,,rw
,,,FIFEN3,'Fault input filter enable 3 ',3.,3.,,rw
,,,FLTEN0,'Fault input enable 0',4.,4.,,rw
,,,FLTEN1,'Fault input enable 1',5.,5.,,rw
,,,FLTEN2,'Fault input enable 2',6.,6.,,rw
,,,FLTEN3,'Fault input enable 3',7.,7.,,rw
,,,FLTPOL0,'Fault input channel 0 polarity',8.,8.,,rw
,,,FLTPOL1,'Fault input channel 1 polarity',9.,9.,,rw
,,,FLTPOL2,'Fault input channel 2 polarity ',10.,10.,,rw
,,,FLTPOL3,'Fault input channel 3 polarity ',11.,11.,,rw
,,,FLTIE,'Fault interrupt enable',12.,12.,,rw
,,,FLTCM,'Falut clear mode',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FIFVAL,'Fault input filter value',16.,19.,,rw
,,,FSTATE,'Fault output status ',20.,20.,,rw
,,,RSVD_31_21,'Reserved',21.,31.,,rw
,0x00000090,32.,MCPWM1_MCPWM_FLTSR,'MCPWM fault status register',,,,rw
,,,FAULTF0,'Fault detection flag of fault channel 0',0.,0.,,rw
,,,FAULTF1,'Fault detection flag of fault channel 1',1.,1.,,rw
,,,FAULTF2,'Fault detection flag of fault channel 2',2.,2.,,rw
,,,FAULTF3,'Fault detection flag of fault channel 3',3.,3.,,rw
,,,FAULTFA,'Fault detection flag A',4.,4.,,rw
,,,FAULTFB,'Fault detection flag B',5.,5.,,rw
,,,FAULTINA,'Fault input A value',6.,6.,,rw
,,,FAULTINB,'Fault input B value',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000094,32.,MCPWM1_MCPWM_FLTASS,'MCPWM fault A safe status value register',,,,rw
,,,FLTASS0,'Channel 0 safe status value for fault A',0.,0.,,rw
,,,FLTASS1,'Channel 1 safe status value for fault A',1.,1.,,rw
,,,FLTASS2,'Channel 2 safe status value for fault A',2.,2.,,rw
,,,FLTASS3,'Channel 3 safe status value for fault A',3.,3.,,rw
,,,FLTASS4,'Channel 4 safe status value for fault A',4.,4.,,rw
,,,FLTASS5,'Channel 5 safe status value for fault A',5.,5.,,rw
,,,FLTASS6,'Channel 6 safe status value for fault A',6.,6.,,rw
,,,FLTASS7,'Channel 7 safe status value for fault A',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000098,32.,MCPWM1_MCPWM_FLTBSS,'MCPWM fault B safe status value register',,,,rw
,,,FLTBSS0,'Channel 0 safe status value for fault B',0.,0.,,rw
,,,FLTBSS1,'Channel 1 safe status value for fault B',1.,1.,,rw
,,,FLTBSS2,'Channel 2 safe status value for fault B',2.,2.,,rw
,,,FLTBSS3,'Channel 3 safe status value for fault B',3.,3.,,rw
,,,FLTBSS4,'Channel 4 safe status value for fault B',4.,4.,,rw
,,,FLTBSS5,'Channel 5 safe status value for fault B',5.,5.,,rw
,,,FLTBSS6,'Channel 6 safe status value for fault B',6.,6.,,rw
,,,FLTBSS7,'Channel 7 safe status value for fault B',7.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x0000009C,32.,MCPWM1_MCPWM_SYNC,'MCPWM synchronization register',,,,rw
,,,SWTRIG,'software trigger synchronization',0.,0.,,rw
,,,SYNCOSWC,'OUTSWCR register synchronization',1.,1.,,rw
,,,SWWRBUF,'Software trigger activate write buffer synchronization',2.,2.,,rw
,,,SWRSTCNT,'Software trigger reset counter ',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000A0,32.,MCPWM1_MCPWM_RELOAD,'MCPWM reload register',,,,rw
,,,CPWMFCR0,'CPWM full cycle reload enable 0',0.,0.,,rw
,,,CPWMFCR1,'CPWM full cycle reload enable 1',1.,1.,,rw
,,,CPWMFCR2,'CPWM full cycle reload enable 2',2.,2.,,rw
,,,CPWMFCR3,'CPWM full cycle reload enable 3',3.,3.,,rw
,,,CPWMHCR0,'CPWM half cycle reload enable 0',4.,4.,,rw
,,,CPWMHCR1,'CPWM half cycle reload enable 1',5.,5.,,rw
,,,CPWMHCR2,'CPWM half cycle reload enable 2',6.,6.,,rw
,,,CPWMHCR3,'CPWM half cycle reload enable 3',7.,7.,,rw
,,,LOADEN0,'Reload enable for pairs of channel 0',8.,8.,,rw
,,,LOADEN1,'Reload enable for pairs of channel 1',9.,9.,,rw
,,,LOADEN2,'Reload enable for pairs of channel 2',10.,10.,,rw
,,,LOADEN3,'Reload enable for pairs of channel 3',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x000000A4,32.,MCPWM1_MCPWM_LDFREQ,'MCPWM reload frequency register',,,,rw
,,,LDFREQ0,'Reload frequency 0',0.,4.,,rw
,,,RSVD_7_5,'Reserved',5.,7.,,rw
,,,LDFREQ1,'Reload frequency 1',8.,12.,,rw
,,,RSVD_15_13,'Reserved',13.,15.,,rw
,,,LDFREQ2,'Reload frequency 2',16.,20.,,rw
,,,RSVD_23_21,'Reserved',21.,23.,,rw
,,,LDFREQ3,'Reload frequency 3',24.,28.,,rw
,,,RSVD_31_29,'Reserved',29.,31.,,rw
,0x00000100,32.,MCPWM1_MCPWM_MODn_DITHER0,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,MCPWM1_MCPWM_MODn_DITHER1,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000108,32.,MCPWM1_MCPWM_MODn_DITHER2,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000010C,32.,MCPWM1_MCPWM_MODn_DITHER3,'MCPWM MODn dither register',,,,rw
,,,MOD_DITHER,'MOD dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000110,32.,MCPWM1_MCPWM_CVn_DITHER0,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000114,32.,MCPWM1_MCPWM_CVn_DITHER1,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000118,32.,MCPWM1_MCPWM_CVn_DITHER2,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000011C,32.,MCPWM1_MCPWM_CVn_DITHER3,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000120,32.,MCPWM1_MCPWM_CVn_DITHER4,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000124,32.,MCPWM1_MCPWM_CVn_DITHER5,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000128,32.,MCPWM1_MCPWM_CVn_DITHER6,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000012C,32.,MCPWM1_MCPWM_CVn_DITHER7,'MCPWM CVn dither register',,,,rw
,,,CV_DITHER,'CV dither value',0.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
tree.end
base ad:0x4001B000
tree "TDG1"
,0x00000000,32.,TDG1_TDG_VERID,'TDG Version Idenfication(TDG_VERID)',,,,rd
,,,MINOR,'Minor version',0.,3.,,rd
,,,MAJOR,'Major version',4.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,TDG1_TDG_PARAM,'TDG Parameter(TDG_PARAM)',,,,rd
,,,DOPNUM,'Delay output point number',0.,3.,,rd
,,,CHNUM,'Channel number',4.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,TDG1_TDG_CTRL1,'TDG Control Registers 1(TDG_CTRL1)',,,,rw
,,,TDGEN,'TDG enabled.',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,TRIGS,'Trig source select',4.,4.,,rw
,,,CNTMD,'Count mode',5.,5.,,rw
,,,CLRMD,'Counter clear mode',6.,6.,,rw
,,,RSVD_7,'Reserved',7.,7.,,rw
,,,PRES,'Prescalar',8.,10.,,rw
,,,RSVD_15_11,'Reserved',11.,15.,,rw
,,,CFGUP,'Configuration update',16.,16.,,rw
,,,SWTRG,'Software trig',17.,17.,,rw
,,,RSVD_19_18,'Reserved',18.,19.,,rw
,,,UPMD,'Channel configulation update mode',20.,21.,,rw
,,,RSVD_31_22,'Reserved',22.,31.,,rw
,0x0000000C,32.,TDG1_TDG_CTRL2,'TDG Control Register 2(TDG_CTRL2)',,,,rw
,,,CDO0IE,'Channel 0 complete delay output interrupt enable',0.,0.,,rw
,,,CDO1IE,'Channel 1 complete delay output interrupt enable',1.,1.,,rw
,,,CDO2IE,'Channel 2 complete delay output interrupt enable',2.,2.,,rw
,,,CDO3IE,'Channel 3 complete delay output interrupt enable',3.,3.,,rw
,,,CDO4IE,'Channel 4 complete delay output interrupt enable',4.,4.,,rw
,,,CDO5IE,'Channel 5 complete delay output interrupt enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,ERRIE,'Error interrupt enable',8.,8.,,rw
,,,RSVD_15_9,'Reserved',9.,15.,,rw
,,,CH0E,'Channel 0 enable',16.,16.,,rw
,,,CH1E,'Channel 1 enable',17.,17.,,rw
,,,CH2E,'Channel 2 enable',18.,18.,,rw
,,,CH3E,'Channel 3 enable',19.,19.,,rw
,,,CH4E,'Channel 4 enable',20.,20.,,rw
,,,CH5E,'Channel 5 enable',21.,21.,,rw
,,,RSVD_31_22,'Reserved',22.,31.,,rw
,0x00000010,32.,TDG1_TDG_STAT,'TDG Status Register(TDG_STAT)',,,,rw
,,,CDO0IF,'Channel 0 complete delay output interrupt flag',0.,0.,,rw
,,,CDO1IF,'Channel 1 complete delay output interrupt flag',1.,1.,,rw
,,,CDO2IF,'Channel 2 complete delay output interrupt flag',2.,2.,,rw
,,,CDO3IF,'Channel 3 complete delay output interrupt flag',3.,3.,,rw
,,,CDO4IF,'Channel 4 complete delay output interrupt flag',4.,4.,,rw
,,,CDO5IF,'Channel 5 complete delay output interrupt flag',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,ERRIF,'Error interrupt flag',8.,8.,,rw
,,,RSVD_31_9,'Reserved',9.,31.,,rw
,0x00000014,32.,TDG1_TDG_MOD,'TDG Modulate Register(TDG_MOD)',,,,rw
,,,MOD,'TDG Modulate value. ',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000018,32.,TDG1_TDG_CNT,'TDG Counter Register(TDG_CNT)',,,,rd
,,,CNT,'TDG counter value. ',0.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x0000001C,32.,TDG1_TDG_CHnCTRL0,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000020,32.,TDG1_TDG_CHnDO0OFS0,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000024,32.,TDG1_TDG_CHnDO1OFS0,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000028,32.,TDG1_TDG_CHnDO2OFS0,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000002C,32.,TDG1_TDG_CHnDO3OFS0,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000030,32.,TDG1_TDG_CHnDO4OFS0,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000034,32.,TDG1_TDG_CHnDO5OFS0,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000038,32.,TDG1_TDG_CHnDO6OFS0,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000003C,32.,TDG1_TDG_CHnDO7OFS0,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000040,32.,TDG1_TDG_CHnCDOINTDLY0,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000044,32.,TDG1_TDG_CHnCTRL1,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000048,32.,TDG1_TDG_CHnDO0OFS1,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000004C,32.,TDG1_TDG_CHnDO1OFS1,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000050,32.,TDG1_TDG_CHnDO2OFS1,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000054,32.,TDG1_TDG_CHnDO3OFS1,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000058,32.,TDG1_TDG_CHnDO4OFS1,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000005C,32.,TDG1_TDG_CHnDO5OFS1,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000060,32.,TDG1_TDG_CHnDO6OFS1,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000064,32.,TDG1_TDG_CHnDO7OFS1,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000068,32.,TDG1_TDG_CHnCDOINTDLY1,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x0000006C,32.,TDG1_TDG_CHnCTRL2,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000070,32.,TDG1_TDG_CHnDO0OFS2,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000074,32.,TDG1_TDG_CHnDO1OFS2,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000078,32.,TDG1_TDG_CHnDO2OFS2,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000007C,32.,TDG1_TDG_CHnDO3OFS2,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000080,32.,TDG1_TDG_CHnDO4OFS2,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000084,32.,TDG1_TDG_CHnDO5OFS2,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000088,32.,TDG1_TDG_CHnDO6OFS2,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000008C,32.,TDG1_TDG_CHnDO7OFS2,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000090,32.,TDG1_TDG_CHnCDOINTDLY2,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000094,32.,TDG1_TDG_CHnCTRL3,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000098,32.,TDG1_TDG_CHnDO0OFS3,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000009C,32.,TDG1_TDG_CHnDO1OFS3,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A0,32.,TDG1_TDG_CHnDO2OFS3,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A4,32.,TDG1_TDG_CHnDO3OFS3,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000A8,32.,TDG1_TDG_CHnDO4OFS3,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000AC,32.,TDG1_TDG_CHnDO5OFS3,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B0,32.,TDG1_TDG_CHnDO6OFS3,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B4,32.,TDG1_TDG_CHnDO7OFS3,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000B8,32.,TDG1_TDG_CHnCDOINTDLY3,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x000000BC,32.,TDG1_TDG_CHnCTRL4,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C0,32.,TDG1_TDG_CHnDO0OFS4,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C4,32.,TDG1_TDG_CHnDO1OFS4,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000C8,32.,TDG1_TDG_CHnDO2OFS4,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000CC,32.,TDG1_TDG_CHnDO3OFS4,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D0,32.,TDG1_TDG_CHnDO4OFS4,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D4,32.,TDG1_TDG_CHnDO5OFS4,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000D8,32.,TDG1_TDG_CHnDO6OFS4,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000DC,32.,TDG1_TDG_CHnDO7OFS4,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000E0,32.,TDG1_TDG_CHnCDOINTDLY4,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x000000E4,32.,TDG1_TDG_CHnCTRL5,'TDG Channel n Control Register(TDG_CHnCTRL)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,DO0E,'Delay output 0 enable on channel n',8.,8.,,rw
,,,DO1E,'Delay output 1 enable on channel n',9.,9.,,rw
,,,DO2E,'Delay output 2 enable on channel n',10.,10.,,rw
,,,DO3E,'Delay output 3 enable on channel n',11.,11.,,rw
,,,DO4E,'Delay output 4 enable on channel n',12.,12.,,rw
,,,DO5E,'Delay output 5 enable on channel n',13.,13.,,rw
,,,DO6E,'Delay output 6 enable on channel n',14.,14.,,rw
,,,DO7E,'Delay output 7 enable on channel n',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000E8,32.,TDG1_TDG_CHnDO0OFS5,'TDG Channel n Delay Output 0 Offset Register(TDG_CHnDO0OFS)',,,,rw
,,,DO0OFS,'TDG Delay Output 0 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000EC,32.,TDG1_TDG_CHnDO1OFS5,'TDG Channel n Delay Output 1 Offset Register(TDG_CHnDO1OFS)',,,,rw
,,,DO1OFS,'TDG Delay Output 1 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F0,32.,TDG1_TDG_CHnDO2OFS5,'TDG Channel n Delay Output 2 Offset Register(TDG_CHnDO2OFS)',,,,rw
,,,DO2OFS,'TDG Delay Output 2 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F4,32.,TDG1_TDG_CHnDO3OFS5,'TDG Channel n Delay Output 3 Offset Register(TDG_CHnDO3OFS)',,,,rw
,,,DO3OFS,'TDG Delay Output 3 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000F8,32.,TDG1_TDG_CHnDO4OFS5,'TDG Channel n Delay Output 4 Offset Register(TDG_CHnDO4OFS)',,,,rw
,,,DO4OFS,'TDG Delay Output 4 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x000000FC,32.,TDG1_TDG_CHnDO5OFS5,'TDG Channel n Delay Output 5 Offset Register(TDG_CHnDO5OFS)',,,,rw
,,,DO5OFS,'TDG Delay Output 5 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000100,32.,TDG1_TDG_CHnDO6OFS5,'TDG Channel n Delay Output 6 Offset Register(TDG_CHnDO6OFS)',,,,rw
,,,DO6OFS,'TDG Delay Output 6 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000104,32.,TDG1_TDG_CHnDO7OFS5,'TDG Channel n Delay Output 7 Offset Register(TDG_CHnDO7OFS)',,,,rw
,,,DO7OFS,'TDG Delay Output 7 Offset',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000108,32.,TDG1_TDG_CHnCDOINTDLY5,'TDG Channel n Complete Delay Output Interrupt Delay Register(TDG_CHnCDOINTDLY)',,,,rw
,,,CDOINTDLY,'TDG Complete Delay Output Interrupt Delay',0.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,LDCO,'CDO Interrupt Delay Configuration Load Complete',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
tree.end
base ad:0x40020000
tree "FLASHC"
,0x00000000,32.,FLASH_FSTAT,'Flash Status Register',,,,rw
,,,FAIL,'Command Fail Flag',0.,0.,,rw
,,,RSVD_1,'This field is reserved',1.,1.,,rw
,,,CMDABT,'Command Abort Flag',2.,2.,,rw
,,,RSVD_4_3,'This field is reserved',3.,4.,,rw
,,,ACCERR,'Command Access Error Flag',5.,5.,,rw
,,,PREABT,'Pre-command Abort Flag',6.,6.,,rw
,,,CCIF,'Command Complete Interrupt Flag',7.,7.,,rw
,,,RSVD_10_8,'This field is reserved',8.,10.,,rw
,,,CMDWRF,'Command writing flag',11.,11.,,rw
,,,RSVD_15_12,'This field is reserved',12.,15.,,rw
,,,DFDIF,'Double-bit Fault Detect Interrupt Flag',16.,16.,,rw
,,,SFDIF,'Single-bit Fault Detect Interrupt Flag',17.,17.,,rw
,,,RSVD_29_18,'This field is reserved',18.,29.,,rw
,,,DBG_ERSALL_DIS,'debug erase all request disable',30.,30.,,rw
,,,FSEC,'Flash Security bit',31.,31.,,rw
,0x00000004,32.,FLASH_FCNFG,'Flash Configuration Register',,,,rw
,,,BK_QUERY,'Backdoor query',0.,0.,,rw
,,,RSVD_6_1,'This field is reserved',1.,6.,,rw
,,,CCIE,'Command Complete Interrupt Enable',7.,7.,,rw
,,,DBG_ERS_FLG,'Debug Erase All Request',8.,8.,,rw
,,,RSVD_15_9,'This field is reserved',9.,15.,,rw
,,,DFDIE,'Double Bit Fault Detect Interrupt Enable',16.,16.,,rw
,,,SFDIE,'Single-bit Fault Detect Interrupt Enable',17.,17.,,rw
,,,RSVD_31_18,'This field is reserved',18.,31.,,rw
,0x00000008,32.,FLASH_FCTRL,'Flash Control Register ',,,,rw
,,,RWSC,'Read Wait-State Control',0.,3.,,rw
,,,RSVD_7_4,'This field is reserved',4.,7.,,rw
,,,LSMODE,'Low speed active mode',8.,8.,,rw
,,,RSVD_15_9,'This field is reserved',9.,15.,,rw
,,,FECCF,'Force ECC Fault',16.,16.,,rw
,,,RSVD_23_17,'This field is reserved',17.,23.,,rw
,,,ABTREQ,'Abort Request',24.,24.,,rw
,,,RSVD_31_25,'This field is reserved',25.,31.,,rw
,0x00000010,32.,FLASH_FCMD,'Flash Command Register',,,,rw
,,,CMDCODE,'Flash Command',0.,7.,,rw
,,,RSVD_31_8,'This field is reserved',8.,31.,,rw
,0x00000014,32.,FLASH_FCMD_OPT,'Flash Command Option Register',,,,rw
,,,CMDOPT,'Flash option command',0.,7.,,rw
,,,RSVD_31_8,'This field is reserved',8.,31.,,rw
,0x00000018,32.,FLASH_FADDR,'Flash Address Register',,,,rw
,,,CMDADDR,'flash sector/page/phrase address',0.,31.,,rw
,0x0000001C,32.,FLASH_FADDR_END,'Flash End Address Register',,,,rw
,,,CMDADDRE,'flash end address for page/phrase',0.,31.,,rw
,0x00000020,32.,FLASH_FDATA0,'Flash Data0 Register',,,,rw
,,,CMDDATA0,'Flash Data0 Register',0.,31.,,rw
,0x00000024,32.,FLASH_FDATA1,'Flash Data1 Register',,,,rw
,,,CMDDATA1,'Flash Data1 Register',0.,31.,,rw
,0x00000028,32.,FLASH_FDATA2,'Flash Data2 Register',,,,rw
,,,CMDDATA2,'Flash Data2 Register',0.,31.,,rw
,0x0000002C,32.,FLASH_FDATA3,'Flash Data3 Register',,,,rw
,,,CMDDATA3,'Flash Data3 Register',0.,31.,,rw
,0x00000030,32.,FLASH_BED_ADDR_STRT,'Flash Bus Error Ignored Start Address Register',,,,rw
,,,RSVD_3_0,'This field is reserved',0.,3.,,rw
,,,BED_ADDR_STRT,'start address for bus error disable',4.,31.,,rw
,0x00000034,32.,FLASH_BED_ADDR_END,'Flash Bus Error Ignored End Phrase Address Register',,,,rw
,,,RSVD_3_0,'This field is reserved',0.,3.,,rw
,,,BED_ADDR_END,'end address for bus error disable',4.,31.,,rw
,0x00000038,32.,FLASH_ECC_IN_ADDR,'Flash ECC Injection Address Register',,,,rw
,,,RSVD_3_0,'This field is reserved',0.,3.,,rw
,,,ECC_IN_ADDR,'ECC injection address',4.,31.,,rw
,0x0000003C,32.,FLASH_ECC_IN_CTRL,'Flash ECC Injection Control Register',,,,rw
,,,ECC_9BIT,'ECC injection on 9-bit ECC data',0.,8.,,rw
,,,ECC_IN_EN,'ECC injection enable',9.,9.,,rw
,,,RSVD_30_10,'This field is reserved',10.,30.,,rw
,,,LOCK,'ECC register LOCK bit',31.,31.,,rw
,0x00000040,32.,FLASH_MBE_STATE,'Flash Multi-bit Error State Register',,,,rw
,,,MBE_FLAG,'multi-bit error flag',0.,0.,,rw
,,,MBE_OVERRUN,'multi-bit error overrun',1.,1.,,rw
,,,RSVD_3_2,'This field is reserved',2.,3.,,rw
,,,MBE_ADDR,'multi-bit error address',4.,31.,,rw
,0x00000044,32.,FLASH_SBE_STATE,'Flash Single-bit Error State Register',,,,rw
,,,SBE_FLAG,'single-bit error flag',0.,0.,,rw
,,,SBE_OVERRUN,'single-bit error overrun',1.,1.,,rw
,,,RSVD_3_2,'This field is reserved',2.,3.,,rw
,,,SBE_ADDR,'single-bit error address',4.,31.,,rw
tree.end
base ad:0x40024000
tree "CAN0"
,0x00000000,32.,CAN0_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN0_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN0_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN0_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN0_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN0_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN0_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN0_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN0_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN0_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN0_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN0_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN0_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN0_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN0_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN0_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN0_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN0_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN0_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN0_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN0_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN0_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN0_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN0_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN0_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN0_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN0_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN0_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN0_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN0_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN0_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN0_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN0_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN0_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN0_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN0_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN0_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN0_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN0_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN0_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN0_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN0_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN0_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN0_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN0_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN0_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN0_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN0_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN0_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN0_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN0_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN0_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN0_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN0_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN0_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN0_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN0_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN0_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN0_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN0_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN0_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN0_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN0_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN0_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40025000
tree "CAN1"
,0x00000000,32.,CAN1_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN1_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN1_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN1_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN1_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN1_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN1_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN1_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN1_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN1_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN1_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN1_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN1_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN1_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN1_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN1_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN1_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN1_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN1_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN1_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN1_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN1_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN1_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN1_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN1_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN1_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN1_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN1_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN1_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN1_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN1_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN1_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN1_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN1_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN1_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN1_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN1_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN1_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN1_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN1_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN1_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN1_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN1_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN1_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN1_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN1_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN1_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN1_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN1_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN1_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN1_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN1_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN1_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN1_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN1_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN1_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN1_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN1_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN1_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN1_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN1_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN1_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN1_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN1_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40027000
tree "ADC1"
,0x00000000,32.,ADC1_ADC_VERID,'ADC version ID Register(ADC_VERID)',,,,rd
,,,DIFFEN,'Differential Supported',0.,0.,,rd
,,,CALOFSI,'Calibration Function Implemented',1.,1.,,rd
,,,RSVD_15_2,'Reserved',2.,15.,,rd
,,,FIFO_NUM,'The number of FIFO',16.,23.,,rd
,,,MINOR,'Minor Version Number',24.,27.,,rd
,,,MAJOR,'Major Version Number',28.,31.,,rd
,0x00000004,32.,ADC1_ADC_PARAM,'ADC PARAMETER Register(ADC_PARAM)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,FIFO_SIZE,'FIFO Depth field',8.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000008,32.,ADC1_ADC_CTRL,'ADC Control Register(ADC_CTRL)',,,,rw
,,,ADC_EN,'ADC Enable',0.,0.,,rw
,,,CAL_REQ,'Auto-Calibration Request',1.,1.,,rw
,,,RST,'Software Reset',2.,2.,,rw
,,,DOZEN,'Doze Enable',3.,3.,,rw
,,,TRIG_MODE_ENABLE,'trig mode enable',4.,4.,,rw
,,,TRIG_MODE,'Trigger mode',5.,5.,,rw
,,,MODE1_RST,'mode1 loop reset bit',6.,6.,,rw
,,,LMD,'loop mode depth',7.,9.,,rw
,,,IREF_SEL,'iref source select ',10.,10.,,rw
,,,STABLE_T,'adc stable time',11.,21.,,rw
,,,TS_EN,'temperature sensor enable',22.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000000C,32.,ADC1_ADC_STAT,'ADC STATUS Register(ADC_STAT)',,,,rd
,,,FWM_INT,'FIFO Watermark Interrupt',0.,0.,,rd
,,,FOF,'Result FIFO Overflow Flag',1.,1.,,rd
,,,TCOMP_INT,'Complete Interrupt ',2.,2.,,rd
,,,CMP_INT,'Compare Interrupt ',3.,3.,,rd
,,,DMA_REQ,'DMA Request ',4.,4.,,rd
,,,RDY,'Result FIFO Ready Flag',5.,5.,,rd
,,,CAL_RDY,'Calibration Ready',6.,6.,,rd
,,,ADC_ACTIVE,'ADC Active',7.,7.,,rd
,,,LSI,'loop state idle',8.,8.,,rd
,,,TC_ERR,'trigger confict err',9.,9.,,rd
,,,RSVD_31_10,'Reserved',10.,31.,,rd
,0x00000010,32.,ADC1_ADC_IE,'ADC Interrupt Enable Register(ADC_IE)',,,,rw
,,,FWM_IE,'FIFO Watermark Interrupt Enable',0.,0.,,rw
,,,FOF_IE,'Result FIFO Overflow Interrupt Enable',1.,1.,,rw
,,,TCOM_IE,'Trigger Completion Interrupt Enable',2.,2.,,rw
,,,CMP_IE,'Compare Interrupt Enable',3.,3.,,rw
,,,FWMDE,'FIFO Watermark DMA Enable',4.,4.,,rw
,,,ERR_INT_IE,'trigger confict err Interrupt Enable',5.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x00000014,32.,ADC1_ADC_CFG,'ADC Configure information(ADC_CFG)',,,,rw
,,,DIFF_MODE,'Differential Mode Select',0.,0.,,rw
,,,CHSELP,'Input Channel-P Select',1.,5.,,rw
,,,CHSELN,'Input Channel-N Select',6.,7.,,rw
,,,RSVD_10_8,'Reserved',8.,10.,,rw
,,,CTYPE,'Conversion Type',11.,11.,,rw
,,,CMPS,'Compare Select',12.,14.,,rw
,,,HWT_EN,'HardWareTrigger Enable',15.,15.,,rw
,,,REF_SEL,'Reference Select',16.,16.,,rw
,,,RES,'Resolution Select',17.,18.,,rw
,,,AVGS,'Hardware Average Select',19.,21.,,rw
,,,STS,'Sample Time Select',22.,31.,,rw
,0x00000018,32.,ADC1_ADC_CV,'ADC Compare Value Register(ADC_CV)',,,,rw
,,,CVL,'Compare Value Low',0.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,CVH,'Compare Value High',16.,27.,,rw
,,,RSVD_31_28,'Reserved',28.,31.,,rw
,0x0000001C,32.,ADC1_ADC_TRIM,'ADC Trim Value Register(ADC_TRIM)',,,,rw
,,,ADC_BTRIM,'ADC BTRIM Value',0.,5.,,rw
,,,ADC_BTRIM_POLAR,'ADC BTRIM POLAR Value',6.,6.,,rw
,,,ADC_KTRIM,'ADC KTRIM Value',7.,10.,,rw
,,,RSVD_30_11,'Reserved',11.,30.,,rw
,,,ADC_TRIM_EN,'ADC Trim Write Enable',31.,31.,,rw
,0x00000020,32.,ADC1_ADC_DATA_RD,'ADC Data Register(ADC_DATA_RD)',,,,rd
,,,ADC_DATA_RD,'conversion result',0.,16.,,rd
,,,RSVD_31_17,'Reserved',17.,31.,,rd
,0x00000024,32.,ADC1_ADC_FCTRL,'ADC FIFO Configuration Register(ADC_FCTRL)',,,,rw
,,,FCOUNT,'FIFO Counter',0.,4.,,rw
,,,RSVD_15_5,'Reserved',5.,15.,,rw
,,,FWMARK,'FIFO Watermark',16.,19.,,rw
,,,FDRD,'FIFO Depth Redefine',20.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000028,32.,ADC1_ADC_SWTRIG,'ADC SoftWareTrigger Register(ADC_SWTRIG)',,,,rw
,,,ADC_SWTRIG,'ADC SoftWare Trigger',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x0000002C,32.,ADC1_ADC_CAL_VAL,'ADC Calibration Value(ADC_CAL_VAL)',,,,rd
,,,ADC_CAL_VAL,'ADC Calibration Value',0.,12.,,rd
,,,RSVD_31_13,'Reserved',13.,31.,,rd
,0x00000030,32.,ADC1_ADC_CMD_BUFF0,'ADC Commond Buff Register0(ADC_CMD_BUFF0)',,,,rw
,,,CMD0,'cmd_buff0',0.,4.,,rw
,,,CMD0_INT_EN,'cmd0 complete int enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,CMD1,'cmd_buff1',8.,12.,,rw
,,,CMD1_INT_EN,'cmd1 complete int enable',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,CMD2,'cmd_buff2',16.,20.,,rw
,,,CMD2_INT_EN,'cmd2 complete int enable',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,CMD3,'cmd_buff3',24.,28.,,rw
,,,CMD3_INT_EN,'cmd3 complete int enable',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000034,32.,ADC1_ADC_CMD_BUFF1,'ADC Command Buff Register1(ADC_CMD_BUFF1)',,,,rw
,,,CMD4,'cmd_buff4',0.,4.,,rw
,,,CMD4_INT_EN,'cmd4 complete int enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,CMD5,'cmd_buff5',8.,12.,,rw
,,,CMD5_INT_EN,'cmd5 complete int enable',13.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000038,32.,ADC1_ADC_GAIN,'ADC gain trim register',,,,rw
,,,GAIN0,'gain trim0',0.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,GAIN1,'gain trim1',16.,27.,,rw
,,,RSVD_31_28,'Reserved',28.,31.,,rw
tree.end
base ad:0x4002C000
tree "SPI0"
,0x00000000,32.,SPI0_SPI_CTRLR0,'Control Register 0(SPI_CTRLR0)',,,,rw
,,,RSVD_5_0,'Reserved',0.,5.,,rw
,,,SCPH,'Serial Clock Phase',6.,6.,,rw
,,,SCPOL,'Serial Clock Polarity',7.,7.,,rw
,,,TMOD,'Transfer Mode',8.,9.,,rw
,,,SLV_OE,'Slave Output Enable.',10.,10.,,rw
,,,SRL,'Shift Register Loop',11.,11.,,rw
,,,CFS,'Control Frame Size',12.,15.,,rw
,,,DFS_32,'Data Frame Size in 32-bit mode',16.,20.,,rw
,,,MST_MODE,'Master mode enable',21.,21.,,rw
,,,MWMOD,'Microwire Transfer Mode',22.,22.,,rw
,,,MDD,'Microwire Control',23.,23.,,rw
,,,MHS,'Microwire Handshaking',24.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000004,32.,SPI0_SPI_CTRLR1,'Control Register 1(SPI_CTRLR1)',,,,rw
,,,NDF,'Number of Data Frames',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,SPI0_SPI_SSENR,'SPI Enable Register(SPI_SSENR)',,,,rw
,,,SPI_EN,'SPI enable trigger',0.,0.,,rw
,,,RSVD_15_1,'Reserved',1.,15.,,rw
,,,SER,'Slave Select Enable Flag',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x0000000C,32.,SPI0_SPI_BAUDR,'Baud Rate Select Register(SPI_BAUDR)',,,,rw
,,,SCKDV,' SPI Clock Divider',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,SPI0_SPI_FTLR,'FIFO Threshold Level Register(SPI_FTLR)',,,,rw
,,,TFT,'Transmit FIFO Threshold',0.,1.,,rw
,,,RSVD_15_2,'Reserved',2.,15.,,rw
,,,RFT,'Receive FIFO Threshold.',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000014,32.,SPI0_SPI_FLR,'FIFO Level Register(SPI_FLR)',,,,rd
,,,TXTFL,'Transmit FIFO Level',0.,2.,,rd
,,,RSVD_15_3,'Reserved',3.,15.,,rd
,,,RXTFL,'Receive FIFO Level',16.,18.,,rd
,,,RSVD_31_19,'Reserved',19.,31.,,rd
,0x00000018,32.,SPI0_SPI_SR,'Status Register(SPI_SR)',,,,rd
,,,BUSY,'SPI Busy Flag',0.,0.,,rd
,,,TFNF,'Transmit FIFO Not Full',1.,1.,,rd
,,,TFE,'Transmit FIFO Empty',2.,2.,,rd
,,,RFNE,'Receive FIFO Not Empty',3.,3.,,rd
,,,RFF,'Receive FIFO Full',4.,4.,,rd
,,,TXE,'Transmission Error',5.,5.,,rd
,,,RSVD_31_6,'Reserved',6.,31.,,rd
,0x0000001C,32.,SPI0_SPI_IER,'Interrupt Enable Register(SPI_IER)',,,,rw
,,,TXEIE,'Transmit FIFO Empty Interrupt Mask',0.,0.,,rw
,,,TXOIE,'Transmit FIFO Overflow Interrupt Mask',1.,1.,,rw
,,,RXUIE,'Receive FIFO Underflow Interrupt Mask',2.,2.,,rw
,,,RXOIE,'Receive FIFO Overflow Interrupt Mask',3.,3.,,rw
,,,RXFIE,'Receive FIFO Full Interrupt Mask',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000020,32.,SPI0_SPI_ISR,'Interrupt Status Register(SPI_ISR)',,,,rd
,,,TXEIS,'Transmit FIFO Empty Interrupt Status',0.,0.,,rd
,,,TXOIS,'Transmit FIFO Overflow Interrupt Status',1.,1.,,rd
,,,RXUIS,'Receive FIFO Underflow Interrupt Status',2.,2.,,rd
,,,RXOIS,'Receive FIFO Overflow Interrupt Status',3.,3.,,rd
,,,RXFIS,'Receive FIFO Full Interrupt Status',4.,4.,,rd
,,,RSVD_15_5,'Reserved',5.,15.,,rd
,,,TXEIR,'Transmit FIFO Empty Raw Interrupt Status',16.,16.,,rd
,,,TXOIR,'Transmit FIFO Overflow Raw Interrupt Status',17.,17.,,rd
,,,RXUIR,'Receive FIFO Underflow Raw Interrupt Status',18.,18.,,rd
,,,RXOIR,'Receive FIFO Overflow Raw Interrupt Status',19.,19.,,rd
,,,RXFIR,'Receive FIFO Full Raw Interrupt Status',20.,20.,,rd
,,,RSVD_31_21,'Reserved',21.,31.,,rd
,0x00000024,32.,SPI0_SPI_TXOICR,'Transmit FIFO Overflow Interrupt Clear Register(SPI_TXOICR)',,,,rd
,,,TXOICR,'Clear Transmit FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000028,32.,SPI0_SPI_RXOICR,'Receive FIFO Overflow Interrupt Clear Register(SPI_RXOICR)',,,,rd
,,,RXOICR,'Clear Receive FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x0000002C,32.,SPI0_SPI_RXUICR,'Receive FIFO Underflow Interrupt Clear Register(SPI_RXUICR)',,,,rd
,,,RXUICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000034,32.,SPI0_SPI_ICR,'Interrupt Clear Register(SPI_ICR)',,,,rd
,,,ICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000038,32.,SPI0_SPI_DMACR,'DMA Control Register(SPI_DMACR)',,,,rw
,,,RDMAE,'Receive DMA Enable',0.,0.,,rw
,,,TDMAE,'Transmit DMA Enable',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000003C,32.,SPI0_SPI_DMATDLR,'DMA Transmit Data Level(SPI_DMATDLR)',,,,rw
,,,DMATDL,'Transmit Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000040,32.,SPI0_SPI_DMARDLR,'DMA Receive Data Level(SPI_DMARDLR)',,,,rw
,,,DMARDL,'Receive Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000044,32.,SPI0_SPI_IDR,'Identification Register(SPI_IDR)',,,,rd
,,,IDCODE,'Identification Code.',0.,31.,,rd
,0x00000048,32.,SPI0_SPI_VIDR,'Version ID register(SPI_VIDR)',,,,rd
,,,VID,'SPI version ID',0.,31.,,rd
,0x00000060,32.,SPI0_SPI_DR_LOW,'Data Register(SPI_DR_LOW)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
,0x000000EC,32.,SPI0_SPI_DR_HIGH,'Data Register(SPI_DR_HIGH)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
tree.end
base ad:0x4002D000
tree "SPI1"
,0x00000000,32.,SPI1_SPI_CTRLR0,'Control Register 0(SPI_CTRLR0)',,,,rw
,,,RSVD_5_0,'Reserved',0.,5.,,rw
,,,SCPH,'Serial Clock Phase',6.,6.,,rw
,,,SCPOL,'Serial Clock Polarity',7.,7.,,rw
,,,TMOD,'Transfer Mode',8.,9.,,rw
,,,SLV_OE,'Slave Output Enable.',10.,10.,,rw
,,,SRL,'Shift Register Loop',11.,11.,,rw
,,,CFS,'Control Frame Size',12.,15.,,rw
,,,DFS_32,'Data Frame Size in 32-bit mode',16.,20.,,rw
,,,MST_MODE,'Master mode enable',21.,21.,,rw
,,,MWMOD,'Microwire Transfer Mode',22.,22.,,rw
,,,MDD,'Microwire Control',23.,23.,,rw
,,,MHS,'Microwire Handshaking',24.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000004,32.,SPI1_SPI_CTRLR1,'Control Register 1(SPI_CTRLR1)',,,,rw
,,,NDF,'Number of Data Frames',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,SPI1_SPI_SSENR,'SPI Enable Register(SPI_SSENR)',,,,rw
,,,SPI_EN,'SPI enable trigger',0.,0.,,rw
,,,RSVD_15_1,'Reserved',1.,15.,,rw
,,,SER,'Slave Select Enable Flag',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x0000000C,32.,SPI1_SPI_BAUDR,'Baud Rate Select Register(SPI_BAUDR)',,,,rw
,,,SCKDV,' SPI Clock Divider',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,SPI1_SPI_FTLR,'FIFO Threshold Level Register(SPI_FTLR)',,,,rw
,,,TFT,'Transmit FIFO Threshold',0.,1.,,rw
,,,RSVD_15_2,'Reserved',2.,15.,,rw
,,,RFT,'Receive FIFO Threshold.',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000014,32.,SPI1_SPI_FLR,'FIFO Level Register(SPI_FLR)',,,,rd
,,,TXTFL,'Transmit FIFO Level',0.,2.,,rd
,,,RSVD_15_3,'Reserved',3.,15.,,rd
,,,RXTFL,'Receive FIFO Level',16.,18.,,rd
,,,RSVD_31_19,'Reserved',19.,31.,,rd
,0x00000018,32.,SPI1_SPI_SR,'Status Register(SPI_SR)',,,,rd
,,,BUSY,'SPI Busy Flag',0.,0.,,rd
,,,TFNF,'Transmit FIFO Not Full',1.,1.,,rd
,,,TFE,'Transmit FIFO Empty',2.,2.,,rd
,,,RFNE,'Receive FIFO Not Empty',3.,3.,,rd
,,,RFF,'Receive FIFO Full',4.,4.,,rd
,,,TXE,'Transmission Error',5.,5.,,rd
,,,RSVD_31_6,'Reserved',6.,31.,,rd
,0x0000001C,32.,SPI1_SPI_IER,'Interrupt Enable Register(SPI_IER)',,,,rw
,,,TXEIE,'Transmit FIFO Empty Interrupt Mask',0.,0.,,rw
,,,TXOIE,'Transmit FIFO Overflow Interrupt Mask',1.,1.,,rw
,,,RXUIE,'Receive FIFO Underflow Interrupt Mask',2.,2.,,rw
,,,RXOIE,'Receive FIFO Overflow Interrupt Mask',3.,3.,,rw
,,,RXFIE,'Receive FIFO Full Interrupt Mask',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000020,32.,SPI1_SPI_ISR,'Interrupt Status Register(SPI_ISR)',,,,rd
,,,TXEIS,'Transmit FIFO Empty Interrupt Status',0.,0.,,rd
,,,TXOIS,'Transmit FIFO Overflow Interrupt Status',1.,1.,,rd
,,,RXUIS,'Receive FIFO Underflow Interrupt Status',2.,2.,,rd
,,,RXOIS,'Receive FIFO Overflow Interrupt Status',3.,3.,,rd
,,,RXFIS,'Receive FIFO Full Interrupt Status',4.,4.,,rd
,,,RSVD_15_5,'Reserved',5.,15.,,rd
,,,TXEIR,'Transmit FIFO Empty Raw Interrupt Status',16.,16.,,rd
,,,TXOIR,'Transmit FIFO Overflow Raw Interrupt Status',17.,17.,,rd
,,,RXUIR,'Receive FIFO Underflow Raw Interrupt Status',18.,18.,,rd
,,,RXOIR,'Receive FIFO Overflow Raw Interrupt Status',19.,19.,,rd
,,,RXFIR,'Receive FIFO Full Raw Interrupt Status',20.,20.,,rd
,,,RSVD_31_21,'Reserved',21.,31.,,rd
,0x00000024,32.,SPI1_SPI_TXOICR,'Transmit FIFO Overflow Interrupt Clear Register(SPI_TXOICR)',,,,rd
,,,TXOICR,'Clear Transmit FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000028,32.,SPI1_SPI_RXOICR,'Receive FIFO Overflow Interrupt Clear Register(SPI_RXOICR)',,,,rd
,,,RXOICR,'Clear Receive FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x0000002C,32.,SPI1_SPI_RXUICR,'Receive FIFO Underflow Interrupt Clear Register(SPI_RXUICR)',,,,rd
,,,RXUICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000034,32.,SPI1_SPI_ICR,'Interrupt Clear Register(SPI_ICR)',,,,rd
,,,ICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000038,32.,SPI1_SPI_DMACR,'DMA Control Register(SPI_DMACR)',,,,rw
,,,RDMAE,'Receive DMA Enable',0.,0.,,rw
,,,TDMAE,'Transmit DMA Enable',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000003C,32.,SPI1_SPI_DMATDLR,'DMA Transmit Data Level(SPI_DMATDLR)',,,,rw
,,,DMATDL,'Transmit Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000040,32.,SPI1_SPI_DMARDLR,'DMA Receive Data Level(SPI_DMARDLR)',,,,rw
,,,DMARDL,'Receive Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000044,32.,SPI1_SPI_IDR,'Identification Register(SPI_IDR)',,,,rd
,,,IDCODE,'Identification Code.',0.,31.,,rd
,0x00000048,32.,SPI1_SPI_VIDR,'Version ID register(SPI_VIDR)',,,,rd
,,,VID,'SPI version ID',0.,31.,,rd
,0x00000060,32.,SPI1_SPI_DR_LOW,'Data Register(SPI_DR_LOW)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
,0x000000EC,32.,SPI1_SPI_DR_HIGH,'Data Register(SPI_DR_HIGH)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
tree.end
base ad:0x40030000
tree "SPI2"
,0x00000000,32.,SPI2_SPI_CTRLR0,'Control Register 0(SPI_CTRLR0)',,,,rw
,,,RSVD_5_0,'Reserved',0.,5.,,rw
,,,SCPH,'Serial Clock Phase',6.,6.,,rw
,,,SCPOL,'Serial Clock Polarity',7.,7.,,rw
,,,TMOD,'Transfer Mode',8.,9.,,rw
,,,SLV_OE,'Slave Output Enable.',10.,10.,,rw
,,,SRL,'Shift Register Loop',11.,11.,,rw
,,,CFS,'Control Frame Size',12.,15.,,rw
,,,DFS_32,'Data Frame Size in 32-bit mode',16.,20.,,rw
,,,MST_MODE,'Master mode enable',21.,21.,,rw
,,,MWMOD,'Microwire Transfer Mode',22.,22.,,rw
,,,MDD,'Microwire Control',23.,23.,,rw
,,,MHS,'Microwire Handshaking',24.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000004,32.,SPI2_SPI_CTRLR1,'Control Register 1(SPI_CTRLR1)',,,,rw
,,,NDF,'Number of Data Frames',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,SPI2_SPI_SSENR,'SPI Enable Register(SPI_SSENR)',,,,rw
,,,SPI_EN,'SPI enable trigger',0.,0.,,rw
,,,RSVD_15_1,'Reserved',1.,15.,,rw
,,,SER,'Slave Select Enable Flag',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x0000000C,32.,SPI2_SPI_BAUDR,'Baud Rate Select Register(SPI_BAUDR)',,,,rw
,,,SCKDV,' SPI Clock Divider',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,SPI2_SPI_FTLR,'FIFO Threshold Level Register(SPI_FTLR)',,,,rw
,,,TFT,'Transmit FIFO Threshold',0.,1.,,rw
,,,RSVD_15_2,'Reserved',2.,15.,,rw
,,,RFT,'Receive FIFO Threshold.',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000014,32.,SPI2_SPI_FLR,'FIFO Level Register(SPI_FLR)',,,,rd
,,,TXTFL,'Transmit FIFO Level',0.,2.,,rd
,,,RSVD_15_3,'Reserved',3.,15.,,rd
,,,RXTFL,'Receive FIFO Level',16.,18.,,rd
,,,RSVD_31_19,'Reserved',19.,31.,,rd
,0x00000018,32.,SPI2_SPI_SR,'Status Register(SPI_SR)',,,,rd
,,,BUSY,'SPI Busy Flag',0.,0.,,rd
,,,TFNF,'Transmit FIFO Not Full',1.,1.,,rd
,,,TFE,'Transmit FIFO Empty',2.,2.,,rd
,,,RFNE,'Receive FIFO Not Empty',3.,3.,,rd
,,,RFF,'Receive FIFO Full',4.,4.,,rd
,,,TXE,'Transmission Error',5.,5.,,rd
,,,RSVD_31_6,'Reserved',6.,31.,,rd
,0x0000001C,32.,SPI2_SPI_IER,'Interrupt Enable Register(SPI_IER)',,,,rw
,,,TXEIE,'Transmit FIFO Empty Interrupt Mask',0.,0.,,rw
,,,TXOIE,'Transmit FIFO Overflow Interrupt Mask',1.,1.,,rw
,,,RXUIE,'Receive FIFO Underflow Interrupt Mask',2.,2.,,rw
,,,RXOIE,'Receive FIFO Overflow Interrupt Mask',3.,3.,,rw
,,,RXFIE,'Receive FIFO Full Interrupt Mask',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000020,32.,SPI2_SPI_ISR,'Interrupt Status Register(SPI_ISR)',,,,rd
,,,TXEIS,'Transmit FIFO Empty Interrupt Status',0.,0.,,rd
,,,TXOIS,'Transmit FIFO Overflow Interrupt Status',1.,1.,,rd
,,,RXUIS,'Receive FIFO Underflow Interrupt Status',2.,2.,,rd
,,,RXOIS,'Receive FIFO Overflow Interrupt Status',3.,3.,,rd
,,,RXFIS,'Receive FIFO Full Interrupt Status',4.,4.,,rd
,,,RSVD_15_5,'Reserved',5.,15.,,rd
,,,TXEIR,'Transmit FIFO Empty Raw Interrupt Status',16.,16.,,rd
,,,TXOIR,'Transmit FIFO Overflow Raw Interrupt Status',17.,17.,,rd
,,,RXUIR,'Receive FIFO Underflow Raw Interrupt Status',18.,18.,,rd
,,,RXOIR,'Receive FIFO Overflow Raw Interrupt Status',19.,19.,,rd
,,,RXFIR,'Receive FIFO Full Raw Interrupt Status',20.,20.,,rd
,,,RSVD_31_21,'Reserved',21.,31.,,rd
,0x00000024,32.,SPI2_SPI_TXOICR,'Transmit FIFO Overflow Interrupt Clear Register(SPI_TXOICR)',,,,rd
,,,TXOICR,'Clear Transmit FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000028,32.,SPI2_SPI_RXOICR,'Receive FIFO Overflow Interrupt Clear Register(SPI_RXOICR)',,,,rd
,,,RXOICR,'Clear Receive FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x0000002C,32.,SPI2_SPI_RXUICR,'Receive FIFO Underflow Interrupt Clear Register(SPI_RXUICR)',,,,rd
,,,RXUICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000034,32.,SPI2_SPI_ICR,'Interrupt Clear Register(SPI_ICR)',,,,rd
,,,ICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000038,32.,SPI2_SPI_DMACR,'DMA Control Register(SPI_DMACR)',,,,rw
,,,RDMAE,'Receive DMA Enable',0.,0.,,rw
,,,TDMAE,'Transmit DMA Enable',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000003C,32.,SPI2_SPI_DMATDLR,'DMA Transmit Data Level(SPI_DMATDLR)',,,,rw
,,,DMATDL,'Transmit Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000040,32.,SPI2_SPI_DMARDLR,'DMA Receive Data Level(SPI_DMARDLR)',,,,rw
,,,DMARDL,'Receive Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000044,32.,SPI2_SPI_IDR,'Identification Register(SPI_IDR)',,,,rd
,,,IDCODE,'Identification Code.',0.,31.,,rd
,0x00000048,32.,SPI2_SPI_VIDR,'Version ID register(SPI_VIDR)',,,,rd
,,,VID,'SPI version ID',0.,31.,,rd
,0x00000060,32.,SPI2_SPI_DR_LOW,'Data Register(SPI_DR_LOW)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
,0x000000EC,32.,SPI2_SPI_DR_HIGH,'Data Register(SPI_DR_HIGH)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
tree.end
base ad:0x40031000
tree "SPI3"
,0x00000000,32.,SPI3_SPI_CTRLR0,'Control Register 0(SPI_CTRLR0)',,,,rw
,,,RSVD_5_0,'Reserved',0.,5.,,rw
,,,SCPH,'Serial Clock Phase',6.,6.,,rw
,,,SCPOL,'Serial Clock Polarity',7.,7.,,rw
,,,TMOD,'Transfer Mode',8.,9.,,rw
,,,SLV_OE,'Slave Output Enable.',10.,10.,,rw
,,,SRL,'Shift Register Loop',11.,11.,,rw
,,,CFS,'Control Frame Size',12.,15.,,rw
,,,DFS_32,'Data Frame Size in 32-bit mode',16.,20.,,rw
,,,MST_MODE,'Master mode enable',21.,21.,,rw
,,,MWMOD,'Microwire Transfer Mode',22.,22.,,rw
,,,MDD,'Microwire Control',23.,23.,,rw
,,,MHS,'Microwire Handshaking',24.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000004,32.,SPI3_SPI_CTRLR1,'Control Register 1(SPI_CTRLR1)',,,,rw
,,,NDF,'Number of Data Frames',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000008,32.,SPI3_SPI_SSENR,'SPI Enable Register(SPI_SSENR)',,,,rw
,,,SPI_EN,'SPI enable trigger',0.,0.,,rw
,,,RSVD_15_1,'Reserved',1.,15.,,rw
,,,SER,'Slave Select Enable Flag',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x0000000C,32.,SPI3_SPI_BAUDR,'Baud Rate Select Register(SPI_BAUDR)',,,,rw
,,,SCKDV,' SPI Clock Divider',0.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000010,32.,SPI3_SPI_FTLR,'FIFO Threshold Level Register(SPI_FTLR)',,,,rw
,,,TFT,'Transmit FIFO Threshold',0.,1.,,rw
,,,RSVD_15_2,'Reserved',2.,15.,,rw
,,,RFT,'Receive FIFO Threshold.',16.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000014,32.,SPI3_SPI_FLR,'FIFO Level Register(SPI_FLR)',,,,rd
,,,TXTFL,'Transmit FIFO Level',0.,2.,,rd
,,,RSVD_15_3,'Reserved',3.,15.,,rd
,,,RXTFL,'Receive FIFO Level',16.,18.,,rd
,,,RSVD_31_19,'Reserved',19.,31.,,rd
,0x00000018,32.,SPI3_SPI_SR,'Status Register(SPI_SR)',,,,rd
,,,BUSY,'SPI Busy Flag',0.,0.,,rd
,,,TFNF,'Transmit FIFO Not Full',1.,1.,,rd
,,,TFE,'Transmit FIFO Empty',2.,2.,,rd
,,,RFNE,'Receive FIFO Not Empty',3.,3.,,rd
,,,RFF,'Receive FIFO Full',4.,4.,,rd
,,,TXE,'Transmission Error',5.,5.,,rd
,,,RSVD_31_6,'Reserved',6.,31.,,rd
,0x0000001C,32.,SPI3_SPI_IER,'Interrupt Enable Register(SPI_IER)',,,,rw
,,,TXEIE,'Transmit FIFO Empty Interrupt Mask',0.,0.,,rw
,,,TXOIE,'Transmit FIFO Overflow Interrupt Mask',1.,1.,,rw
,,,RXUIE,'Receive FIFO Underflow Interrupt Mask',2.,2.,,rw
,,,RXOIE,'Receive FIFO Overflow Interrupt Mask',3.,3.,,rw
,,,RXFIE,'Receive FIFO Full Interrupt Mask',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000020,32.,SPI3_SPI_ISR,'Interrupt Status Register(SPI_ISR)',,,,rd
,,,TXEIS,'Transmit FIFO Empty Interrupt Status',0.,0.,,rd
,,,TXOIS,'Transmit FIFO Overflow Interrupt Status',1.,1.,,rd
,,,RXUIS,'Receive FIFO Underflow Interrupt Status',2.,2.,,rd
,,,RXOIS,'Receive FIFO Overflow Interrupt Status',3.,3.,,rd
,,,RXFIS,'Receive FIFO Full Interrupt Status',4.,4.,,rd
,,,RSVD_15_5,'Reserved',5.,15.,,rd
,,,TXEIR,'Transmit FIFO Empty Raw Interrupt Status',16.,16.,,rd
,,,TXOIR,'Transmit FIFO Overflow Raw Interrupt Status',17.,17.,,rd
,,,RXUIR,'Receive FIFO Underflow Raw Interrupt Status',18.,18.,,rd
,,,RXOIR,'Receive FIFO Overflow Raw Interrupt Status',19.,19.,,rd
,,,RXFIR,'Receive FIFO Full Raw Interrupt Status',20.,20.,,rd
,,,RSVD_31_21,'Reserved',21.,31.,,rd
,0x00000024,32.,SPI3_SPI_TXOICR,'Transmit FIFO Overflow Interrupt Clear Register(SPI_TXOICR)',,,,rd
,,,TXOICR,'Clear Transmit FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000028,32.,SPI3_SPI_RXOICR,'Receive FIFO Overflow Interrupt Clear Register(SPI_RXOICR)',,,,rd
,,,RXOICR,'Clear Receive FIFO Overflow Interrupt',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x0000002C,32.,SPI3_SPI_RXUICR,'Receive FIFO Underflow Interrupt Clear Register(SPI_RXUICR)',,,,rd
,,,RXUICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000034,32.,SPI3_SPI_ICR,'Interrupt Clear Register(SPI_ICR)',,,,rd
,,,ICR,'Reserved',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000038,32.,SPI3_SPI_DMACR,'DMA Control Register(SPI_DMACR)',,,,rw
,,,RDMAE,'Receive DMA Enable',0.,0.,,rw
,,,TDMAE,'Transmit DMA Enable',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000003C,32.,SPI3_SPI_DMATDLR,'DMA Transmit Data Level(SPI_DMATDLR)',,,,rw
,,,DMATDL,'Transmit Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000040,32.,SPI3_SPI_DMARDLR,'DMA Receive Data Level(SPI_DMARDLR)',,,,rw
,,,DMARDL,'Receive Data Level',0.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x00000044,32.,SPI3_SPI_IDR,'Identification Register(SPI_IDR)',,,,rd
,,,IDCODE,'Identification Code.',0.,31.,,rd
,0x00000048,32.,SPI3_SPI_VIDR,'Version ID register(SPI_VIDR)',,,,rd
,,,VID,'SPI version ID',0.,31.,,rd
,0x00000060,32.,SPI3_SPI_DR_LOW,'Data Register(SPI_DR_LOW)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
,0x000000EC,32.,SPI3_SPI_DR_HIGH,'Data Register(SPI_DR_HIGH)',,,,rw
,,,DR,'Data Register',0.,31.,,rw
tree.end
base ad:0x40032000
tree "CRC"
,0x00000000,32.,CRC_VERID,'CRC Version Number(CRC_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00000004,32.,CRC_PARAM,'CRC Parameter Register(CRC_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00000008,32.,CRC_DATA,'CRC Data register(CRC_DATA)',,,,rw
,,,BYTE0,'CRC Data Byte0',0.,7.,,rw
,,,BYTE1,'CRC Data Byte1',8.,15.,,rw
,,,BYTE2,'CRC Data Byte2',16.,23.,,rw
,,,BYTE3,'CRC Data Byte3',24.,31.,,rw
,0x0000000C,32.,CRC_POLY,'CRC Polynomial register(CRC_POLY)',,,,rw
,,,LPHW,'Low Polynominal Half-word',0.,15.,,rw
,,,HPHW,'High Polynominal Half-word',16.,31.,,rw
,0x00000010,32.,CRC_CTRL,'CRC Control register(CRC_CTRL)',,,,rw
,,,MODE,'CRC mode',0.,0.,,rw
,,,WS,'Write seed',1.,1.,,rw
,,,CR,'Complement Read',2.,2.,,rw
,,,RSVD_3,'This field is reserved',3.,3.,,rw
,,,RT,'Read Type Of Transpose',4.,5.,,rw
,,,WT,'Write Type Of Transpose',6.,7.,,rw
,,,RSVD_31_8,'This field is reserved',8.,31.,,rw
tree.end
base ad:0x400332000
tree "AES"
,0x00000000,32.,AES_VERSION,'Version register',,,,rw
,,,VERSION,'Version number of the IP',0.,31.,,rw
,0x00000004,32.,AES_STATUS,'Status register',,,,rw
,,,R,'R ready bit',0.,0.,,rw
,,,ERR,'error code',1.,8.,,rw
,,,RSVD_31_9,'Reserved',9.,31.,,rw
,0x00000008,32.,AES_CONTROL,'Control register',,,,rw
,,,S,'operation start bit',0.,0.,,rw
,,,RND,'4-bit random data',1.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x0000000C,32.,AES_CONFIG,'Config register',,,,rw
,,,CD,'operation command',0.,0.,,rw
,,,KSS,'Reserved',1.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,RSVD_7_4,'Reserved',4.,7.,,rw
,,,MODE,'operation mode',8.,15.,,rw
,,,BS,'Block Size',16.,23.,,rw
,,,ALGO,'Reserved',24.,31.,,rw
,0x0000001C,32.,AES_DATA_I0,'Data input 0 registers.',,,,rw
,,,DATA_I,'data input',0.,31.,,rw
,0x00000020,32.,AES_DATA_I1,'Data input 1 registers.',,,,rw
,,,DATA_I,'data input',0.,31.,,rw
,0x00000024,32.,AES_DATA_I2,'Data input 2 registers.',,,,rw
,,,DATA_I,'data input',0.,31.,,rw
,0x00000028,32.,AES_DATA_I3,'Data input 3 registers.',,,,rw
,,,DATA_I,'data input',0.,31.,,rw
,0x0000002C,32.,AES_DATA_O0,'Data output 0 registers.',,,,rw
,,,DATA_O,'data output',0.,31.,,rw
,0x00000030,32.,AES_DATA_O1,'Data output 1 registers.',,,,rw
,,,DATA_O,'data output',0.,31.,,rw
,0x00000034,32.,AES_DATA_O2,'Data output 2 registers.',,,,rw
,,,DATA_O,'data output',0.,31.,,rw
,0x00000038,32.,AES_DATA_O3,'Data output 3 registers.',,,,rw
,,,DATA_O,'data output',0.,31.,,rw
,0x0000003C,32.,AES_KEY0,'Key 0  registers.',,,,rw
,,,KEY0,'input KEY 0 ',0.,31.,,rw
,0x00000040,32.,AES_KEY1,'Key 1  registers.',,,,rw
,,,KEY1,'input KEY 1',0.,31.,,rw
,0x00000044,32.,AES_KEY2,'Key 2  registers.',,,,rw
,,,KEY2,'input KEY 2',0.,31.,,rw
,0x00000048,32.,AES_KEY3,'Key 3  registers.',,,,rw
,,,KEY3,'input KEY 3',0.,31.,,rw
,0x0000005C,32.,AES_IV0,'Initialization Vector (IV) input 0 registers.',,,,rw
,,,IV0,'Initialization Vector 0',0.,31.,,rw
,0x00000060,32.,AES_IV1,'Initialization Vector (IV) input 1 registers.',,,,rw
,,,IV1,'Initialization Vector 1',0.,31.,,rw
,0x00000064,32.,AES_IV2,'Initialization Vector (IV) input 2 registers.',,,,rw
,,,IV2,'Initialization Vector 2',0.,31.,,rw
,0x00000068,32.,AES_IV3,'Initialization Vector (IV) input 3 registers.',,,,rw
,,,IV3,'Initialization Vector 3',0.,31.,,rw
tree.end
base ad:0x40034000
tree "TRNG"
,0x00000000,32.,TRNG_VERSION,'TRNG Version register',,,,rw
,,,VERSION,'Version number of the IP',0.,31.,,rw
,0x00000004,32.,CTR_DRBG_VERSION,'CTR-DRBG Version register',,,,rw
,,,VERSION,'Version number of the IP',0.,31.,,rw
,0x00000008,32.,TRNG_STATUS,'TRNG Status register',,,,rw
,,,RD,'CTR-DRBG ready',0.,0.,,rw
,,,IN,'CTR-DRBG instantiated bit.',1.,1.,,rw
,,,TA,'TRNG Alarms Valid bit',2.,2.,,rw
,,,CA,'CTR-DRBG Alarms Valid bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x0000000C,32.,TRNG_CONFIG,'TRNG Config register',,,,rw
,,,EN,'CTR-DRBG enable bit',0.,0.,,rw
,,,SM,'Stream mode enable bit',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,DEC,'Decimation parameter',4.,13.,,rw
,,,LP,'Latency Parameter',14.,18.,,rw
,,,RSVD_31_19,'Reserved',19.,31.,,rw
,0x00000010,32.,CTR_DRBG_CONTROL,'CTR-DRBG Control register',,,,rw
,,,GE,'CTR-DRBG generate bit',0.,0.,,rw
,,,IN,'CTR-DTRB instantiate bit',1.,1.,,rw
,,,HT,'CTR-DRBG health test bit',2.,2.,,rw
,,,UN,'CTR-DRBG uninstantiate bit',3.,3.,,rw
,,,RS,'CTR-DRBG release bit',4.,4.,,rw
,,,AK,'CTR-DRBG Alram acknowledgement bit',5.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x00000014,32.,CTR_DRBG_REQUEST_SIZE,'CTR-DRBG Request Size register',,,,rw
,,,RS,'Number of 128-bit words that are requested.',0.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000018,32.,CTR_DRBG_CONFIG_1,'CTR-DRBG Config register 1',,,,rw
,,,RP,'Number of generate requests between two reseeds.',0.,31.,,rw
,0x0000001C,32.,CTR_DRBG_CONFIG_2,'CTR-DRBG Config register 2',,,,rw
,,,HTP,'Number of random generations between two periodic health tests.',0.,31.,,rw
,0x00000020,32.,TRNG_ALARM,'TRNG Alarm register',,,,rw
,,,AL0,'TRNG Alarm bit 0(Monobit test)',0.,0.,,rw
,,,AL1,'TRNG Alarm bit 1(poker test)',1.,1.,,rw
,,,AL2,'TRNG Alarm bit 2(run test)',2.,2.,,rw
,,,AL3,'TRNG Alarm bit 3(Long run test)',3.,3.,,rw
,,,VA,'TRNG Alarm valid bit',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000024,32.,CTR_DRBG_ALARM,'CTR-DRBG Alarm register',,,,rw
,,,AL0,'CTR-DRBG Alarm bit 0',0.,0.,,rw
,,,AL1,'CTR-DRBG Alarm bit 1',1.,1.,,rw
,,,AL2,'CTR-DRBG Alarm bit 2',2.,2.,,rw
,,,VA,'CTR-DRBG Alarm valid bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000028,32.,TRNG_RAW_RANDOM_CONTROL,'TRNG Raw Random Control register',,,,rw
,,,FL,'Raw data fifo flush bit',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x0000002C,32.,TRNG_RAW_RANDOM_DATA,'TRNG Raw Random Data register',,,,rw
,,,DATA,'Raw random data',0.,15.,,rw
,,,VA,'TRNG raw random data valid bit',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000030,32.,CTR_DRBG_RANDOM_DATA,'CTR-DRBG Random Data register',,,,rw
,,,DATA,'CTR-TRBG random data',0.,15.,,rw
,,,VA,'CTR-DRBG random data valid bit',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000034,32.,ADDITIONAL_CONFIG_0,'Additional Config register 0',,,,rw
,,,I0,'Monobit test(TRNG embedded tests) ignore bit',0.,0.,,rw
,,,I1,'Poker run test(TRNG embedded tests) ignore bit',1.,1.,,rw
,,,I2,'Run test(TRNG embedded tests) ignore bit',2.,2.,,rw
,,,I3,'Long run test(TRNG embedded tests) ignore bit',3.,3.,,rw
,,,MC,'Manual control enable bit',4.,4.,,rw
,,,RE,'Raw data recording enable bit',5.,5.,,rw
,,,E0,'Monobit test(TRNG embedded tests) enable bit',6.,6.,,rw
,,,E1,'Poker run test(TRNG embedded tests) enable bit',7.,7.,,rw
,,,E2,'Run test(TRNG embedded tests) enable bit',8.,8.,,rw
,,,E3,'Long run test(TRNG embedded tests) enable bit',9.,9.,,rw
,,,SE,'Noise module enable bit(Manual control)',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000038,32.,ADDITIONAL_CONFIG_1,'Additional Config register 1',,,,rw
,,,AC1,'Additional configuration word 1',0.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x0000003C,32.,ADDITIONAL_CONFIG_2,'Additional Config register 2',,,,rw
,,,AC2,'Additional configuration word 2',0.,31.,,rw
,0x00000040,32.,ADDITIONAL_MEAS_CONTROL,'Additional Measurement Control register',,,,rw
,,,NS,'Noise measurement start signal',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x00000044,32.,ADDITIONAL_MEAS_CONFIG,'Additional Measurement Config register',,,,rw
,,,TIME,'Noise measuremnt time',0.,29.,,rw
,,,SEL,'Noise measurement selection',30.,31.,,rw
,0x00000048,32.,ADDITIONAL_MEAS_STATUS,'Additional Measurement Status register',,,,rw
,,,RD,'Ready',0.,0.,,rw
,,,OV,'Over',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000004C,32.,ADDITIONAL_MEAS_DATA_0,'Additional Measurement Data register 0',,,,rw
,,,D0,'noise measurement data 0',0.,31.,,rw
,0x00000050,32.,ADDITIONAL_MEAS_DATA_1,'Additional Measurement Data register 1',,,,rw
,,,D1,'noise measurement data 1',0.,31.,,rw
,0x00000054,32.,IRQ_STATUS,'Interrupt Request Status register',,,,rw
,,,IS0,'IRQ status bit 0',0.,0.,,rw
,,,IS1,'IRQ status bit 1',1.,1.,,rw
,,,IS2,'IRQ status bit 2',2.,2.,,rw
,,,IS3,'IRQ status bit 3',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000058,32.,IRQ_CLEAR,'Interrupt Request Clear register',,,,rw
,,,CL0,'IRQ clear bit 0',0.,0.,,rw
,,,CL1,'IRQ clear bit 1',1.,1.,,rw
,,,CL2,'IRQ clear bit 2',2.,2.,,rw
,,,CL3,'IRQ clear bit 3',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x0000005C,32.,IRQ_CONFIG,'Interrupt Request Config register',,,,rw
,,,E0,'IRQ Enable 0',0.,0.,,rw
,,,E1,'IRQ Enable 1',1.,1.,,rw
,,,E2,'IRQ Enable 2',2.,2.,,rw
,,,E3,'IRQ Enable 3',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000060,32.,ERROR_CONFIG,'Error Config register',,,,rw
,,,TIMEOUT,'Timeout value',0.,31.,,rw
,0x00000064,32.,ERROR_CONTROL,'Error Control register',,,,rw
,,,ST,'Timeout start bit',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x00000068,32.,ERROR_STATUS,'Error Status register',,,,rw
,,,RD,'Timeout module ready',0.,0.,,rw
,,,OV,'Timeout module over',1.,1.,,rw
,,,TR,'Timeout error',2.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x0000006C,32.,STATS_CONFIG,'TRNG Monitoring Feature Config register',,,,rw
,,,MO,'Monitoring feature enable',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x00000070,32.,STATS_CONTROL,'TRNG Monitoring Feature Control register',,,,rw
,,,CL,'Monitoring feature counter clear',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x00000074,32.,STATS_DATA,'TRNG Monitoring Feature status register',,,,rw
,,,EV,'Reserved',0.,15.,,rw
,,,PA,'Reserved',16.,31.,,rw
tree.end
base ad:0x40038000
tree "CAN2"
,0x00000000,32.,CAN2_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN2_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN2_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN2_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN2_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN2_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN2_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN2_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN2_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN2_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN2_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN2_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN2_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN2_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN2_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN2_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN2_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN2_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN2_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN2_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN2_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN2_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN2_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN2_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN2_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN2_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN2_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN2_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN2_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN2_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN2_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN2_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN2_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN2_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN2_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN2_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN2_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN2_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN2_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN2_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN2_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN2_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN2_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN2_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN2_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN2_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN2_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN2_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN2_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN2_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN2_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN2_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN2_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN2_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN2_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN2_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN2_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN2_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN2_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN2_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN2_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN2_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN2_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN2_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40039000
tree "CAN3"
,0x00000000,32.,CAN3_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN3_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN3_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN3_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN3_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN3_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN3_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN3_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN3_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN3_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN3_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN3_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN3_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN3_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN3_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN3_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN3_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN3_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN3_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN3_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN3_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN3_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN3_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN3_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN3_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN3_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN3_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN3_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN3_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN3_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN3_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN3_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN3_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN3_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN3_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN3_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN3_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN3_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN3_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN3_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN3_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN3_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN3_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN3_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN3_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN3_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN3_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN3_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN3_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN3_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN3_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN3_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN3_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN3_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN3_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN3_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN3_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN3_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN3_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN3_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN3_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN3_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN3_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN3_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x4003B000
tree "ADC0"
,0x00000000,32.,ADC0_ADC_VERID,'ADC version ID Register(ADC_VERID)',,,,rd
,,,DIFFEN,'Differential Supported',0.,0.,,rd
,,,CALOFSI,'Calibration Function Implemented',1.,1.,,rd
,,,RSVD_15_2,'Reserved',2.,15.,,rd
,,,FIFO_NUM,'The number of FIFO',16.,23.,,rd
,,,MINOR,'Minor Version Number',24.,27.,,rd
,,,MAJOR,'Major Version Number',28.,31.,,rd
,0x00000004,32.,ADC0_ADC_PARAM,'ADC PARAMETER Register(ADC_PARAM)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,FIFO_SIZE,'FIFO Depth field',8.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000008,32.,ADC0_ADC_CTRL,'ADC Control Register(ADC_CTRL)',,,,rw
,,,ADC_EN,'ADC Enable',0.,0.,,rw
,,,CAL_REQ,'Auto-Calibration Request',1.,1.,,rw
,,,RST,'Software Reset',2.,2.,,rw
,,,DOZEN,'Doze Enable',3.,3.,,rw
,,,TRIG_MODE_ENABLE,'trig mode enable',4.,4.,,rw
,,,TRIG_MODE,'Trigger mode',5.,5.,,rw
,,,MODE1_RST,'mode1 loop reset bit',6.,6.,,rw
,,,LMD,'loop mode depth',7.,9.,,rw
,,,IREF_SEL,'iref source select ',10.,10.,,rw
,,,STABLE_T,'adc stable time',11.,21.,,rw
,,,TS_EN,'temperature sensor enable',22.,22.,,rw
,,,RSVD_31_23,'Reserved',23.,31.,,rw
,0x0000000C,32.,ADC0_ADC_STAT,'ADC STATUS Register(ADC_STAT)',,,,rd
,,,FWM_INT,'FIFO Watermark Interrupt',0.,0.,,rd
,,,FOF,'Result FIFO Overflow Flag',1.,1.,,rd
,,,TCOMP_INT,'Complete Interrupt ',2.,2.,,rd
,,,CMP_INT,'Compare Interrupt ',3.,3.,,rd
,,,DMA_REQ,'DMA Request ',4.,4.,,rd
,,,RDY,'Result FIFO Ready Flag',5.,5.,,rd
,,,CAL_RDY,'Calibration Ready',6.,6.,,rd
,,,ADC_ACTIVE,'ADC Active',7.,7.,,rd
,,,LSI,'loop state idle',8.,8.,,rd
,,,TC_ERR,'trigger confict err',9.,9.,,rd
,,,RSVD_31_10,'Reserved',10.,31.,,rd
,0x00000010,32.,ADC0_ADC_IE,'ADC Interrupt Enable Register(ADC_IE)',,,,rw
,,,FWM_IE,'FIFO Watermark Interrupt Enable',0.,0.,,rw
,,,FOF_IE,'Result FIFO Overflow Interrupt Enable',1.,1.,,rw
,,,TCOM_IE,'Trigger Completion Interrupt Enable',2.,2.,,rw
,,,CMP_IE,'Compare Interrupt Enable',3.,3.,,rw
,,,FWMDE,'FIFO Watermark DMA Enable',4.,4.,,rw
,,,ERR_INT_IE,'trigger confict err Interrupt Enable',5.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x00000014,32.,ADC0_ADC_CFG,'ADC Configure information(ADC_CFG)',,,,rw
,,,DIFF_MODE,'Differential Mode Select',0.,0.,,rw
,,,CHSELP,'Input Channel-P Select',1.,5.,,rw
,,,CHSELN,'Input Channel-N Select',6.,7.,,rw
,,,RSVD_10_8,'Reserved',8.,10.,,rw
,,,CTYPE,'Conversion Type',11.,11.,,rw
,,,CMPS,'Compare Select',12.,14.,,rw
,,,HWT_EN,'HardWareTrigger Enable',15.,15.,,rw
,,,REF_SEL,'Reference Select',16.,16.,,rw
,,,RES,'Resolution Select',17.,18.,,rw
,,,AVGS,'Hardware Average Select',19.,21.,,rw
,,,STS,'Sample Time Select',22.,31.,,rw
,0x00000018,32.,ADC0_ADC_CV,'ADC Compare Value Register(ADC_CV)',,,,rw
,,,CVL,'Compare Value Low',0.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,CVH,'Compare Value High',16.,27.,,rw
,,,RSVD_31_28,'Reserved',28.,31.,,rw
,0x0000001C,32.,ADC0_ADC_TRIM,'ADC Trim Value Register(ADC_TRIM)',,,,rw
,,,ADC_BTRIM,'ADC BTRIM Value',0.,5.,,rw
,,,ADC_BTRIM_POLAR,'ADC BTRIM POLAR Value',6.,6.,,rw
,,,ADC_KTRIM,'ADC KTRIM Value',7.,10.,,rw
,,,RSVD_30_11,'Reserved',11.,30.,,rw
,,,ADC_TRIM_EN,'ADC Trim Write Enable',31.,31.,,rw
,0x00000020,32.,ADC0_ADC_DATA_RD,'ADC Data Register(ADC_DATA_RD)',,,,rd
,,,ADC_DATA_RD,'conversion result',0.,16.,,rd
,,,RSVD_31_17,'Reserved',17.,31.,,rd
,0x00000024,32.,ADC0_ADC_FCTRL,'ADC FIFO Configuration Register(ADC_FCTRL)',,,,rw
,,,FCOUNT,'FIFO Counter',0.,4.,,rw
,,,RSVD_15_5,'Reserved',5.,15.,,rw
,,,FWMARK,'FIFO Watermark',16.,19.,,rw
,,,FDRD,'FIFO Depth Redefine',20.,24.,,rw
,,,RSVD_31_25,'Reserved',25.,31.,,rw
,0x00000028,32.,ADC0_ADC_SWTRIG,'ADC SoftWareTrigger Register(ADC_SWTRIG)',,,,rw
,,,ADC_SWTRIG,'ADC SoftWare Trigger',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x0000002C,32.,ADC0_ADC_CAL_VAL,'ADC Calibration Value(ADC_CAL_VAL)',,,,rd
,,,ADC_CAL_VAL,'ADC Calibration Value',0.,12.,,rd
,,,RSVD_31_13,'Reserved',13.,31.,,rd
,0x00000030,32.,ADC0_ADC_CMD_BUFF0,'ADC Commond Buff Register0(ADC_CMD_BUFF0)',,,,rw
,,,CMD0,'cmd_buff0',0.,4.,,rw
,,,CMD0_INT_EN,'cmd0 complete int enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,CMD1,'cmd_buff1',8.,12.,,rw
,,,CMD1_INT_EN,'cmd1 complete int enable',13.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,CMD2,'cmd_buff2',16.,20.,,rw
,,,CMD2_INT_EN,'cmd2 complete int enable',21.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,CMD3,'cmd_buff3',24.,28.,,rw
,,,CMD3_INT_EN,'cmd3 complete int enable',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000034,32.,ADC0_ADC_CMD_BUFF1,'ADC Command Buff Register1(ADC_CMD_BUFF1)',,,,rw
,,,CMD4,'cmd_buff4',0.,4.,,rw
,,,CMD4_INT_EN,'cmd4 complete int enable',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,CMD5,'cmd_buff5',8.,12.,,rw
,,,CMD5_INT_EN,'cmd5 complete int enable',13.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000038,32.,ADC0_ADC_GAIN,'ADC gain trim register',,,,rw
,,,GAIN0,'gain trim0',0.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,GAIN1,'gain trim1',16.,27.,,rw
,,,RSVD_31_28,'Reserved',28.,31.,,rw
tree.end
base ad:0x4003E000
tree "CMU0"
,0x00000000,32.,CMU0_CMU_VERID,'Clock Monitor Unit Version Idenfication(CMU_VERID)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,MINOR,'Minor version',8.,15.,,rd
,,,MAJOR,'Major version',16.,23.,,rd
,,,RSVD_31_24,'Reserved',24.,31.,,rd
,0x00000004,32.,CMU0_CMU_PARAM,'Clock Monitor Unit Parameter(CMU_PARAM)',,,,rd
,,,RST_IMP,'Reset generation implemented',0.,0.,,rd
,,,RSVD_30_1,'Reserved',1.,30.,,rd
,0x00000008,32.,CMU0_CMU_CTRL,'Clock Monitor Unit Control(CMU_CTRL)',,,,rw
,,,CME,'Clock Monitor Enable',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CMMD,'Clock Monitor Mode',4.,4.,,rw
,,,RSVD_7_5,'Reserved',5.,7.,,rw
,,,FAHTRSTE,'Frequency Above High Threshold Reset Enable',8.,8.,,rw
,,,FBLTRSTE,'Frequency Below Low Threshold Reset Enable',9.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,FAHTIE,'Frequency Above High Threshold Interrupt Enable',16.,16.,,rw
,,,FBLTIE,'Frequency Below Low Threshold Interrupt Enable',17.,17.,,rw
,,,RSVD_30_18,'Reserved',18.,30.,,rw
,,,LOCK,'Write register lock',31.,31.,,rw
,0x0000000C,32.,CMU0_CMU_STAT,'Clock Monitor Unit Status(CMU_STAT)',,,,rw
,,,MONST,'Monitor State',0.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,STARTMEA,'Start to measure',4.,4.,,rw
,,,RSVD_15_5,'Reserved',5.,15.,,rw
,,,FAHTIF,'Frequency Above High Threshold Interrupt Flag',16.,16.,,rw
,,,FBLTIF,'Frequency Below Low Threshold Interrupt Flag',17.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000010,32.,CMU0_CMU_MONWIN,'Clock Monitor Unit Monitor Window(CMU_MONWIN)',,,,rw
,,,MONWIN,'Monitor Window',0.,31.,,rw
,0x00000014,32.,CMU0_CMU_CUMHCT4INT,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Interrupt(CMU_CUMHCT4INT)',,,,rw
,,,HCT4INT,'High Compare Threshold For Interrupt',0.,31.,,rw
,0x00000018,32.,CMU0_CMU_CUMLCT4INT,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Interrupt(CMU_CUMLCT4INT)',,,,rw
,,,LCT4INT,'Low Compare Threshold For Interrupt',0.,31.,,rw
,0x0000001C,32.,CMU0_CMU_CUMHCT4RST,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Reset(CMU_CUMHCT4RST)',,,,rw
,,,HCT4RST,'High Compare Threshold For Reset',0.,31.,,rw
,0x00000020,32.,CMU0_CMU_CUMLCT4RST,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Reset(CMU_CUMLCT4RST)',,,,rw
,,,LCT4RST,'Low Compare Threshold For Reset',0.,31.,,rw
,0x00000024,32.,CMU0_CMU_CUMMEARSLT,'Clock Monitor Unit Clock Under Monitor Measurement Result',,,,rw
,,,MEARSLT,'Measurement result',0.,31.,,rw
tree.end
base ad:0x40040000
tree "STIM"
,0x00000000,32.,STIM_VERID,'stim version ID register(STIM_VERID)',,,,rd
,,,VERID,'Version ID',0.,31.,,rd
,0x00000004,32.,STIM_CNTn0,'stim channel n counter register(STIM_CNTn)',,,,rd
,,,CNT,'32-bit counter',0.,31.,,rd
,0x00000008,32.,STIM_CNTn1,'stim channel n counter register(STIM_CNTn)',,,,rd
,,,CNT,'32-bit counter',0.,31.,,rd
,0x0000000C,32.,STIM_CNTn2,'stim channel n counter register(STIM_CNTn)',,,,rd
,,,CNT,'32-bit counter',0.,31.,,rd
,0x00000010,32.,STIM_CNTn3,'stim channel n counter register(STIM_CNTn)',,,,rd
,,,CNT,'32-bit counter',0.,31.,,rd
,0x00000014,32.,STIM_CVn0,'stim channel n compare value register(STIM_CVn)',,,,rw
,,,CV,'stim compare value',0.,31.,,rw
,0x00000018,32.,STIM_CVn1,'stim channel n compare value register(STIM_CVn)',,,,rw
,,,CV,'stim compare value',0.,31.,,rw
,0x0000001C,32.,STIM_CVn2,'stim channel n compare value register(STIM_CVn)',,,,rw
,,,CV,'stim compare value',0.,31.,,rw
,0x00000020,32.,STIM_CVn3,'stim channel n compare value register(STIM_CVn)',,,,rw
,,,CV,'stim compare value',0.,31.,,rw
,0x00000024,32.,STIM_SCn0,'stim channel n status and control register(STIM_SCn)',,,,rw
,,,CLKS,'clock source select',0.,1.,,rw
,,,PSDIV,'Prescaler divider factor/Glitch filter value',2.,5.,,rw
,,,PSEN,'Prescaler/Glitch filter enable',6.,6.,,rw
,,,POL,'input pin polarity',7.,7.,,rw
,,,PSRC,'input pin source select',8.,9.,,rw
,,,MODE,'timer mode select',10.,10.,,rw
,,,RSTDIS,'counter reset disable on match',11.,11.,,rw
,,,DMAE,'dma enable',12.,12.,,rw
,,,IE,'interrupt enable',13.,13.,,rw
,,,EN,'stim enable',14.,14.,,rw
,,,FLAG,'timer flag',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000028,32.,STIM_SCn1,'stim channel n status and control register(STIM_SCn)',,,,rw
,,,CLKS,'clock source select',0.,1.,,rw
,,,PSDIV,'Prescaler divider factor/Glitch filter value',2.,5.,,rw
,,,PSEN,'Prescaler/Glitch filter enable',6.,6.,,rw
,,,POL,'input pin polarity',7.,7.,,rw
,,,PSRC,'input pin source select',8.,9.,,rw
,,,MODE,'timer mode select',10.,10.,,rw
,,,RSTDIS,'counter reset disable on match',11.,11.,,rw
,,,DMAE,'dma enable',12.,12.,,rw
,,,IE,'interrupt enable',13.,13.,,rw
,,,EN,'stim enable',14.,14.,,rw
,,,FLAG,'timer flag',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000002C,32.,STIM_SCn2,'stim channel n status and control register(STIM_SCn)',,,,rw
,,,CLKS,'clock source select',0.,1.,,rw
,,,PSDIV,'Prescaler divider factor/Glitch filter value',2.,5.,,rw
,,,PSEN,'Prescaler/Glitch filter enable',6.,6.,,rw
,,,POL,'input pin polarity',7.,7.,,rw
,,,PSRC,'input pin source select',8.,9.,,rw
,,,MODE,'timer mode select',10.,10.,,rw
,,,RSTDIS,'counter reset disable on match',11.,11.,,rw
,,,DMAE,'dma enable',12.,12.,,rw
,,,IE,'interrupt enable',13.,13.,,rw
,,,EN,'stim enable',14.,14.,,rw
,,,FLAG,'timer flag',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000030,32.,STIM_SCn3,'stim channel n status and control register(STIM_SCn)',,,,rw
,,,CLKS,'clock source select',0.,1.,,rw
,,,PSDIV,'Prescaler divider factor/Glitch filter value',2.,5.,,rw
,,,PSEN,'Prescaler/Glitch filter enable',6.,6.,,rw
,,,POL,'input pin polarity',7.,7.,,rw
,,,PSRC,'input pin source select',8.,9.,,rw
,,,MODE,'timer mode select',10.,10.,,rw
,,,RSTDIS,'counter reset disable on match',11.,11.,,rw
,,,DMAE,'dma enable',12.,12.,,rw
,,,IE,'interrupt enable',13.,13.,,rw
,,,EN,'stim enable',14.,14.,,rw
,,,FLAG,'timer flag',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
tree.end
base ad:0x40042000
tree "CMU1"
,0x00000000,32.,CMU1_CMU_VERID,'Clock Monitor Unit Version Idenfication(CMU_VERID)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,MINOR,'Minor version',8.,15.,,rd
,,,MAJOR,'Major version',16.,23.,,rd
,,,RSVD_31_24,'Reserved',24.,31.,,rd
,0x00000004,32.,CMU1_CMU_PARAM,'Clock Monitor Unit Parameter(CMU_PARAM)',,,,rd
,,,RST_IMP,'Reset generation implemented',0.,0.,,rd
,,,RSVD_30_1,'Reserved',1.,30.,,rd
,0x00000008,32.,CMU1_CMU_CTRL,'Clock Monitor Unit Control(CMU_CTRL)',,,,rw
,,,CME,'Clock Monitor Enable',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CMMD,'Clock Monitor Mode',4.,4.,,rw
,,,RSVD_7_5,'Reserved',5.,7.,,rw
,,,FAHTRSTE,'Frequency Above High Threshold Reset Enable',8.,8.,,rw
,,,FBLTRSTE,'Frequency Below Low Threshold Reset Enable',9.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,FAHTIE,'Frequency Above High Threshold Interrupt Enable',16.,16.,,rw
,,,FBLTIE,'Frequency Below Low Threshold Interrupt Enable',17.,17.,,rw
,,,RSVD_30_18,'Reserved',18.,30.,,rw
,,,LOCK,'Write register lock',31.,31.,,rw
,0x0000000C,32.,CMU1_CMU_STAT,'Clock Monitor Unit Status(CMU_STAT)',,,,rw
,,,MONST,'Monitor State',0.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,STARTMEA,'Start to measure',4.,4.,,rw
,,,RSVD_15_5,'Reserved',5.,15.,,rw
,,,FAHTIF,'Frequency Above High Threshold Interrupt Flag',16.,16.,,rw
,,,FBLTIF,'Frequency Below Low Threshold Interrupt Flag',17.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000010,32.,CMU1_CMU_MONWIN,'Clock Monitor Unit Monitor Window(CMU_MONWIN)',,,,rw
,,,MONWIN,'Monitor Window',0.,31.,,rw
,0x00000014,32.,CMU1_CMU_CUMHCT4INT,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Interrupt(CMU_CUMHCT4INT)',,,,rw
,,,HCT4INT,'High Compare Threshold For Interrupt',0.,31.,,rw
,0x00000018,32.,CMU1_CMU_CUMLCT4INT,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Interrupt(CMU_CUMLCT4INT)',,,,rw
,,,LCT4INT,'Low Compare Threshold For Interrupt',0.,31.,,rw
,0x0000001C,32.,CMU1_CMU_CUMHCT4RST,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Reset(CMU_CUMHCT4RST)',,,,rw
,,,HCT4RST,'High Compare Threshold For Reset',0.,31.,,rw
,0x00000020,32.,CMU1_CMU_CUMLCT4RST,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Reset(CMU_CUMLCT4RST)',,,,rw
,,,LCT4RST,'Low Compare Threshold For Reset',0.,31.,,rw
,0x00000024,32.,CMU1_CMU_CUMMEARSLT,'Clock Monitor Unit Clock Under Monitor Measurement Result',,,,rw
,,,MEARSLT,'Measurement result',0.,31.,,rw
tree.end
base ad:0x40043000
tree "CMU2"
,0x00000000,32.,CMU2_CMU_VERID,'Clock Monitor Unit Version Idenfication(CMU_VERID)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,MINOR,'Minor version',8.,15.,,rd
,,,MAJOR,'Major version',16.,23.,,rd
,,,RSVD_31_24,'Reserved',24.,31.,,rd
,0x00000004,32.,CMU2_CMU_PARAM,'Clock Monitor Unit Parameter(CMU_PARAM)',,,,rd
,,,RST_IMP,'Reset generation implemented',0.,0.,,rd
,,,RSVD_30_1,'Reserved',1.,30.,,rd
,0x00000008,32.,CMU2_CMU_CTRL,'Clock Monitor Unit Control(CMU_CTRL)',,,,rw
,,,CME,'Clock Monitor Enable',0.,0.,,rw
,,,RSVD_3_1,'Reserved',1.,3.,,rw
,,,CMMD,'Clock Monitor Mode',4.,4.,,rw
,,,RSVD_7_5,'Reserved',5.,7.,,rw
,,,FAHTRSTE,'Frequency Above High Threshold Reset Enable',8.,8.,,rw
,,,FBLTRSTE,'Frequency Below Low Threshold Reset Enable',9.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,FAHTIE,'Frequency Above High Threshold Interrupt Enable',16.,16.,,rw
,,,FBLTIE,'Frequency Below Low Threshold Interrupt Enable',17.,17.,,rw
,,,RSVD_30_18,'Reserved',18.,30.,,rw
,,,LOCK,'Write register lock',31.,31.,,rw
,0x0000000C,32.,CMU2_CMU_STAT,'Clock Monitor Unit Status(CMU_STAT)',,,,rw
,,,MONST,'Monitor State',0.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,STARTMEA,'Start to measure',4.,4.,,rw
,,,RSVD_15_5,'Reserved',5.,15.,,rw
,,,FAHTIF,'Frequency Above High Threshold Interrupt Flag',16.,16.,,rw
,,,FBLTIF,'Frequency Below Low Threshold Interrupt Flag',17.,17.,,rw
,,,RSVD_31_18,'Reserved',18.,31.,,rw
,0x00000010,32.,CMU2_CMU_MONWIN,'Clock Monitor Unit Monitor Window(CMU_MONWIN)',,,,rw
,,,MONWIN,'Monitor Window',0.,31.,,rw
,0x00000014,32.,CMU2_CMU_CUMHCT4INT,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Interrupt(CMU_CUMHCT4INT)',,,,rw
,,,HCT4INT,'High Compare Threshold For Interrupt',0.,31.,,rw
,0x00000018,32.,CMU2_CMU_CUMLCT4INT,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Interrupt(CMU_CUMLCT4INT)',,,,rw
,,,LCT4INT,'Low Compare Threshold For Interrupt',0.,31.,,rw
,0x0000001C,32.,CMU2_CMU_CUMHCT4RST,'Clock Monitor Unit Clock Under Monitor High Compare Threshold For Reset(CMU_CUMHCT4RST)',,,,rw
,,,HCT4RST,'High Compare Threshold For Reset',0.,31.,,rw
,0x00000020,32.,CMU2_CMU_CUMLCT4RST,'Clock Monitor Unit Clock Under Monitor Low Compare Threshold For Reset(CMU_CUMLCT4RST)',,,,rw
,,,LCT4RST,'Low Compare Threshold For Reset',0.,31.,,rw
,0x00000024,32.,CMU2_CMU_CUMMEARSLT,'Clock Monitor Unit Clock Under Monitor Measurement Result',,,,rw
,,,MEARSLT,'Measurement result',0.,31.,,rw
tree.end
base ad:0x40044000
tree "CAN4"
,0x00000000,32.,CAN4_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN4_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN4_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN4_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN4_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN4_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN4_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN4_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN4_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN4_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN4_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN4_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN4_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN4_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN4_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN4_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN4_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN4_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN4_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN4_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN4_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN4_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN4_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN4_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN4_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN4_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN4_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN4_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN4_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN4_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN4_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN4_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN4_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN4_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN4_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN4_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN4_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN4_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN4_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN4_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN4_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN4_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN4_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN4_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN4_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN4_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN4_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN4_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN4_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN4_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN4_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN4_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN4_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN4_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN4_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN4_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN4_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN4_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN4_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN4_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN4_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN4_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN4_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN4_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40045000
tree "CAN5"
,0x00000000,32.,CAN5_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN5_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN5_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN5_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN5_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN5_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN5_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN5_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN5_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN5_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN5_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN5_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN5_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN5_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN5_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN5_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN5_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN5_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN5_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN5_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN5_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN5_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN5_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN5_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN5_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN5_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN5_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN5_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN5_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN5_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN5_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN5_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN5_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN5_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN5_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN5_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN5_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN5_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN5_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN5_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN5_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN5_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN5_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN5_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN5_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN5_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN5_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN5_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN5_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN5_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN5_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN5_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN5_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN5_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN5_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN5_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN5_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN5_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN5_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN5_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN5_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN5_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN5_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN5_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40048000
tree "SCM"
,0x00000000,32.,SCM_CHIPCTL,'Chip Control register (SCM_CHIPCTL)',,,,rw
,,,RSVD_3_0,'Reserved',0.,3.,,rw
,,,CLKOUTSEL,'CLKOUT Source selection',4.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,CLKOUTDIV,'CLKOUT Divide Ratio',8.,10.,,rw
,,,CLKOUTEN,'CLKOUT enable',11.,11.,,rw
,,,RSVD_31_12,'Reserved',12.,31.,,rw
,0x00000004,32.,SCM_MISCCTL1,'Misc Control register 1(SCM_MISCCTL1)',,,,rw
,,,SWTRIG,'Software Trigger to TMU',0.,3.,,rw
,,,SRAML_READ_BUFF_EN,'Software Trigger to TMU',4.,4.,,rw
,,,SRAMU_READ_BUFF_EN,'Software Trigger to TMU',5.,5.,,rw
,,,XBAR_ROUND_ROBIN,'Software Trigger to TMU',6.,6.,,rw
,,,BOOT_FROM_SRAMU,'Enable boot from sramu',7.,7.,,rw
,,,CCACHE_DIS_WB,'write buffer disable',8.,8.,,rw
,,,CCACHE_LIM_WB,'write buffer limit',9.,9.,,rw
,,,RSVD_10,'force no cache allocation(reserved, only for test)',10.,10.,,rw
,,,CCACHE_CLR,'active high clears cache',11.,11.,,rw
,,,CCACHE_PARITY_MISS_EN,'cache parity miss enable ',12.,12.,,rw
,,,CCACHE_PARITY_FAULT_EN,'cache parity fault enable ',13.,13.,,rw
,,,CACHE_DIS,'cache disable control bit ',14.,14.,,rw
,,,CCACHE_WBE_INT_EN,'cache write buffer error interrupt enable ',15.,15.,,rw
,,,CCACHE_BE_INT_EN,'cache bit error interrupt enable ',16.,16.,,rw
,,,TRACE_CLK_DIV,'trace clock divider ',17.,21.,,rw
,,,TRACE_CLK_EN,'trace clock output enable',22.,22.,,rw
,,,RSVD_23,'Reserved',23.,23.,,rw
,,,FPU_INEXACT_INT_EN,'fpu inexat interrupt enable',24.,24.,,rw
,,,FPU_OVERFLOW_INT_EN,'fpu overflow interrupt enable',25.,25.,,rw
,,,FPU_UNDERFLOW_INT_EN,'fpu underflow interrupt enable',26.,26.,,rw
,,,FPU_INVALIDOP_INT_EN,'fpu invalidop interrupt enable',27.,27.,,rw
,,,FPU_DIVZERO_INT_EN,'fpu divzero interrupt enable',28.,28.,,rw
,,,FPU_DENORMALIN_INT_EN,'fpu denormain interrupt enable',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000028,32.,SCM_MISCCTL2,'Misc Control register 2(SCM_MISCCTL2)',,,,rw
,,,ENET_PHY_INTF_SEL,'ENET phy select ',0.,2.,,rw
,,,RSVD_7_3,'Reserved',3.,7.,,rw
,,,MCPWM0_TCLK_SEL,'MCPWM0 external input clock select ',8.,9.,,rw
,,,MCPWM1_TCLK_SEL,'MCPWM1 external input clock select ',10.,11.,,rw
,,,TIM0_TCLK_SEL,'TIM0 external input clock select ',12.,13.,,rw
,,,TIM1_TCLK_SEL,'TIM1 external input clock select ',14.,15.,,rw
,,,TIM2_TCLK_SEL,'TIM2 external input clock select ',16.,17.,,rw
,,,TIM3_TCLK_SEL,'TIM3 external input clock select ',18.,19.,,rw
,,,RSVD_23_20,'Reserved',20.,23.,,rw
,,,ADC0_CH8_SEL,'ADC0 channel 8 mux select ',24.,24.,,rw
,,,ADC0_CH9_SEL,'ADC0 channel 9 mux select ',25.,25.,,rw
,,,ADC1_CH14_SEL,'ADC1 channel 14 mux select ',26.,26.,,rw
,,,ADC1_CH15_SEL,'ADC1 channel 15 mux select ',27.,27.,,rw
,,,RSVD_31_28,'Reserved',28.,31.,,rw
,0x00000040,32.,SCM_MISCSTAT1,'Misc Status register 1(SCM_MISCSTAT1)',,,,rw
,,,RSVD_14_0,'Reserved',0.,14.,,rw
,,,CCACHE_WBE_FLAG,'cache write buffer error flag',15.,15.,,rw
,,,CCACHE_BE_FLAG,'cache bit error flag',16.,23.,,rw
,,,FPU_INEXACT_FLAG,'FPU in exact flag',24.,24.,,rw
,,,FPU_OVERFLOW_FLAG,'FPU over flow flag',25.,25.,,rw
,,,FPU_UNDERFLOW_FLAG,'FPU under flow flag',26.,26.,,rw
,,,FPU_INVALIDOP_FLAG,'FPU invalid op flag',27.,27.,,rw
,,,FPU_DIVZERO_FLAG,'FPU divzero flag',28.,28.,,rw
,,,FPU_DENORMALIN_FLAG,'FPU denormalin flag',29.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000044,32.,SCM_MISCDATA1,'Misc Data register 1(SCM_MISCDATA1)',,,,rw
,,,CACHE_BE_ADDR,'Reserved',0.,31.,,rw
,0x00000048,32.,SCM_MISCDATA2,'Misc Data register 2(SCM_MISCDATA2)',,,,rw
,,,CACHE_BE_DATA,'Reserved',0.,31.,,rw
,0x00000100,32.,SCM_CHIPOPT,'Chip Option Register (SCM_CHIPOPT)',,,,rd
,,,RSVD_31_0,'Reserved',0.,31.,,rd
,0x00000104,32.,SCM_FLSCFG,'Flash Configuration Register (SCM_FLSCFG)',,,,rd
,,,RSVD_23_0,'Reserved',0.,23.,,rd
,,,PFSIZE,'Program Flash Size',24.,27.,,rd
,,,DFSIZE,'Data Flash Size',28.,31.,,rd
,0x00000108,32.,SCM_RAMCFG,'RAM Configuration Register (SCM_RAMCFG)',,,,rd
,,,CACHESIZE,'CACHE Size',0.,3.,,rd
,,,RSVD_27_4,'Reserved',4.,27.,,rd
,,,RAMSIZE,'SRAM Size',28.,31.,,rd
,0x0000010C,32.,SCM_RAMRMC1,'RAM Read Margin Control Register 1(SCM_RAMRMC1)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,SRAML_RM,'SRAML read margin',8.,11.,,rd
,,,SRAML_RM_DIS,'SRAML read margin disable',12.,12.,,rd
,,,RSVD_23_13,'Reserved',13.,23.,,rd
,,,SRAMU_RM,'SRAMU read margin',24.,27.,,rd
,,,SRAMU_RM_DIS,'SRAMU read margin disable',28.,28.,,rd
,,,RSVD_31_29,'Reserved',29.,31.,,rd
,0x00000110,32.,SCM_RAMRMC2,'RAM Read Margin Control Register 2(SCM_RAMRMC2)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,CACHE_RM,'CACHE read margin',8.,11.,,rd
,,,CACHE_RME,'CACHE read margin enable',12.,12.,,rd
,,,RSVD_31_13,'Reserved',13.,31.,,rd
,0x0000011C,32.,SCM_DEVID,'System Device Identification Register (SCM_SDID)',,,,rd
,,,MEMSIZE_ID,'Memory size ID load from IFR during reset',0.,3.,,rd
,,,SERIES_ID,'Series ID load from IFR during reset',4.,6.,,rd
,,,SUBFAMILY_ID,'Sub family ID load from IFR during reset',7.,11.,,rd
,,,FAMILY_ID,'Family ID load from IFR during reset',12.,15.,,rd
,,,REV_ID,'Revision ID load from IFR during reset',16.,19.,,rd
,,,FEATURE_ID,'Feature ID load from IFR during reset',20.,26.,,rd
,,,PACKAGE_ID,'Package ID load from IFR during reset',27.,31.,,rd
,0x00000120,32.,SCM_UNIQUE0,'Unique Identification Register 0 (SCM_UID0)',,,,rd
,,,UID_31_0,'Reserved',0.,31.,,rd
,0x00000124,32.,SCM_UNIQUE1,'Unique Identification Register 1 (SCM_UID1)',,,,rd
,,,UID_63_32,'Reserved',0.,31.,,rd
,0x00000128,32.,SCM_UNIQUE2,'Unique Identification Register 2 (SCM_UID2)',,,,rd
,,,UID_95_64,'Reserved',0.,31.,,rd
,0x0000012C,32.,SCM_UNIQUE3,'Unique Identification Register 3 (SCM_UID3)',,,,rd
,,,UID_127_96,'Reserved',0.,31.,,rd
tree.end
base ad:0x40049000
tree "PORT"
,0x00000000,32.,PORTA_VERID,'Port Version Number(PORTA_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00000004,32.,PORTA_PARAM,'PORT Parameter Register(PORTA_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00000008,32.,PORTA_GLBDAT,'Global Pin Data Register(PORTA_GLBDAT)',,,,rw
,,,GPWD,'Global Pin Write Data',0.,31.,,rw
,0x0000000C,32.,PORTA_GLBCTL,'Global Pin Control Register(PORTA_GLBCTL)',,,,wr
,,,GPWE,'Global Pin Write Enable',0.,31.,,wr
,0x00000010,32.,PORTA_PCRn0,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000014,32.,PORTA_PCRn1,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000018,32.,PORTA_PCRn2,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000001C,32.,PORTA_PCRn3,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000020,32.,PORTA_PCRn4,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000024,32.,PORTA_PCRn5,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000028,32.,PORTA_PCRn6,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000002C,32.,PORTA_PCRn7,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000030,32.,PORTA_PCRn8,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000034,32.,PORTA_PCRn9,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000038,32.,PORTA_PCRn10,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000003C,32.,PORTA_PCRn11,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000040,32.,PORTA_PCRn12,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000044,32.,PORTA_PCRn13,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000048,32.,PORTA_PCRn14,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000004C,32.,PORTA_PCRn15,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000050,32.,PORTA_PCRn16,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000054,32.,PORTA_PCRn17,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000058,32.,PORTA_PCRn18,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000005C,32.,PORTA_PCRn19,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000060,32.,PORTA_PCRn20,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000064,32.,PORTA_PCRn21,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000068,32.,PORTA_PCRn22,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000006C,32.,PORTA_PCRn23,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000070,32.,PORTA_PCRn24,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000074,32.,PORTA_PCRn25,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000078,32.,PORTA_PCRn26,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000007C,32.,PORTA_PCRn27,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000080,32.,PORTA_PCRn28,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000084,32.,PORTA_PCRn29,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000088,32.,PORTA_PCRn30,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000008C,32.,PORTA_PCRn31,'Pin Control Register(PORTA_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00000090,32.,PORTA_IRQFLG,'Interrupt Status Flag Register (PORTA_IRQFLG)',,,,rw
,,,ISF,'Interrupt Status Flag',0.,31.,,rw
,0x00001000,32.,PORTB_VERID,'Port Version Number(PORTB_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00001004,32.,PORTB_PARAM,'PORT Parameter Register(PORTB_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00001008,32.,PORTB_GLBDAT,'Global Pin Data Register(PORTB_GLBDAT)',,,,rw
,,,GPWD,'Global Pin Write Data',0.,31.,,rw
,0x0000100C,32.,PORTB_GLBCTL,'Global Pin Control Register(PORTB_GLBCTL)',,,,wr
,,,GPWE,'Global Pin Write Enable',0.,31.,,wr
,0x00001010,32.,PORTB_PCRn0,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001014,32.,PORTB_PCRn1,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001018,32.,PORTB_PCRn2,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000101C,32.,PORTB_PCRn3,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001020,32.,PORTB_PCRn4,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001024,32.,PORTB_PCRn5,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001028,32.,PORTB_PCRn6,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000102C,32.,PORTB_PCRn7,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001030,32.,PORTB_PCRn8,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001034,32.,PORTB_PCRn9,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001038,32.,PORTB_PCRn10,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000103C,32.,PORTB_PCRn11,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001040,32.,PORTB_PCRn12,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001044,32.,PORTB_PCRn13,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001048,32.,PORTB_PCRn14,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000104C,32.,PORTB_PCRn15,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001050,32.,PORTB_PCRn16,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001054,32.,PORTB_PCRn17,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001058,32.,PORTB_PCRn18,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000105C,32.,PORTB_PCRn19,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001060,32.,PORTB_PCRn20,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001064,32.,PORTB_PCRn21,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001068,32.,PORTB_PCRn22,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000106C,32.,PORTB_PCRn23,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001070,32.,PORTB_PCRn24,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001074,32.,PORTB_PCRn25,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001078,32.,PORTB_PCRn26,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000107C,32.,PORTB_PCRn27,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001080,32.,PORTB_PCRn28,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001084,32.,PORTB_PCRn29,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001088,32.,PORTB_PCRn30,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000108C,32.,PORTB_PCRn31,'Pin Control Register(PORTB_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00001090,32.,PORTB_IRQFLG,'Interrupt Status Flag Register (PORTB_IRQFLG)',,,,rw
,,,ISF,'Interrupt Status Flag',0.,31.,,rw
,0x00002000,32.,PORTC_VERID,'Port Version Number(PORTC_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00002004,32.,PORTC_PARAM,'PORT Parameter Register(PORTC_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00002008,32.,PORTC_GLBDAT,'Global Pin Data Register(PORTC_GLBDAT)',,,,rw
,,,GPWD,'Global Pin Write Data',0.,31.,,rw
,0x0000200C,32.,PORTC_GLBCTL,'Global Pin Control Register(PORTC_GLBCTL)',,,,wr
,,,GPWE,'Global Pin Write Enable',0.,31.,,wr
,0x00002010,32.,PORTC_PCRn0,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002014,32.,PORTC_PCRn1,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002018,32.,PORTC_PCRn2,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000201C,32.,PORTC_PCRn3,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002020,32.,PORTC_PCRn4,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002024,32.,PORTC_PCRn5,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002028,32.,PORTC_PCRn6,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000202C,32.,PORTC_PCRn7,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002030,32.,PORTC_PCRn8,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002034,32.,PORTC_PCRn9,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002038,32.,PORTC_PCRn10,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000203C,32.,PORTC_PCRn11,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002040,32.,PORTC_PCRn12,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002044,32.,PORTC_PCRn13,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002048,32.,PORTC_PCRn14,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000204C,32.,PORTC_PCRn15,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002050,32.,PORTC_PCRn16,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002054,32.,PORTC_PCRn17,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002058,32.,PORTC_PCRn18,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000205C,32.,PORTC_PCRn19,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002060,32.,PORTC_PCRn20,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002064,32.,PORTC_PCRn21,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002068,32.,PORTC_PCRn22,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000206C,32.,PORTC_PCRn23,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002070,32.,PORTC_PCRn24,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002074,32.,PORTC_PCRn25,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002078,32.,PORTC_PCRn26,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000207C,32.,PORTC_PCRn27,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002080,32.,PORTC_PCRn28,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002084,32.,PORTC_PCRn29,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002088,32.,PORTC_PCRn30,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000208C,32.,PORTC_PCRn31,'Pin Control Register(PORTC_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00002090,32.,PORTC_IRQFLG,'Interrupt Status Flag Register (PORTC_IRQFLG)',,,,rw
,,,ISF,'Interrupt Status Flag',0.,31.,,rw
,0x00007000,32.,PORTD_VERID,'Port Version Number(PORTD_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00007004,32.,PORTD_PARAM,'PORT Parameter Register(PORTD_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00007008,32.,PORTD_GLBDAT,'Global Pin Data Register(PORTD_GLBDAT)',,,,rw
,,,GPWD,'Global Pin Write Data',0.,31.,,rw
,0x0000700C,32.,PORTD_GLBCTL,'Global Pin Control Register(PORTD_GLBCTL)',,,,wr
,,,GPWE,'Global Pin Write Enable',0.,31.,,wr
,0x00007010,32.,PORTD_PCRn0,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007014,32.,PORTD_PCRn1,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007018,32.,PORTD_PCRn2,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000701C,32.,PORTD_PCRn3,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007020,32.,PORTD_PCRn4,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007024,32.,PORTD_PCRn5,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007028,32.,PORTD_PCRn6,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000702C,32.,PORTD_PCRn7,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007030,32.,PORTD_PCRn8,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007034,32.,PORTD_PCRn9,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007038,32.,PORTD_PCRn10,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000703C,32.,PORTD_PCRn11,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007040,32.,PORTD_PCRn12,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007044,32.,PORTD_PCRn13,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007048,32.,PORTD_PCRn14,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000704C,32.,PORTD_PCRn15,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007050,32.,PORTD_PCRn16,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007054,32.,PORTD_PCRn17,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007058,32.,PORTD_PCRn18,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000705C,32.,PORTD_PCRn19,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007060,32.,PORTD_PCRn20,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007064,32.,PORTD_PCRn21,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007068,32.,PORTD_PCRn22,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000706C,32.,PORTD_PCRn23,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007070,32.,PORTD_PCRn24,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007074,32.,PORTD_PCRn25,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007078,32.,PORTD_PCRn26,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000707C,32.,PORTD_PCRn27,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007080,32.,PORTD_PCRn28,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007084,32.,PORTD_PCRn29,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007088,32.,PORTD_PCRn30,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000708C,32.,PORTD_PCRn31,'Pin Control Register(PORTD_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00007090,32.,PORTD_IRQFLG,'Interrupt Status Flag Register (PORTD_IRQFLG)',,,,rw
,,,ISF,'Interrupt Status Flag',0.,31.,,rw
,0x00008000,32.,PORTE_VERID,'Port Version Number(PORTE_VERID)',,,,rd
,,,FEATURE,'Module Identification Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00008004,32.,PORTE_PARAM,'PORT Parameter Register(PORTE_PARAM)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00008008,32.,PORTE_GLBDAT,'Global Pin Data Register(PORTE_GLBDAT)',,,,rw
,,,GPWD,'Global Pin Write Data',0.,31.,,rw
,0x0000800C,32.,PORTE_GLBCTL,'Global Pin Control Register(PORTE_GLBCTL)',,,,wr
,,,GPWE,'Global Pin Write Enable',0.,31.,,wr
,0x00008010,32.,PORTE_PCRn0,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008014,32.,PORTE_PCRn1,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008018,32.,PORTE_PCRn2,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000801C,32.,PORTE_PCRn3,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008020,32.,PORTE_PCRn4,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008024,32.,PORTE_PCRn5,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008028,32.,PORTE_PCRn6,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000802C,32.,PORTE_PCRn7,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008030,32.,PORTE_PCRn8,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008034,32.,PORTE_PCRn9,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008038,32.,PORTE_PCRn10,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000803C,32.,PORTE_PCRn11,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008040,32.,PORTE_PCRn12,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008044,32.,PORTE_PCRn13,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008048,32.,PORTE_PCRn14,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000804C,32.,PORTE_PCRn15,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008050,32.,PORTE_PCRn16,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008054,32.,PORTE_PCRn17,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008058,32.,PORTE_PCRn18,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000805C,32.,PORTE_PCRn19,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008060,32.,PORTE_PCRn20,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008064,32.,PORTE_PCRn21,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008068,32.,PORTE_PCRn22,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000806C,32.,PORTE_PCRn23,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008070,32.,PORTE_PCRn24,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008074,32.,PORTE_PCRn25,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008078,32.,PORTE_PCRn26,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000807C,32.,PORTE_PCRn27,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008080,32.,PORTE_PCRn28,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008084,32.,PORTE_PCRn29,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008088,32.,PORTE_PCRn30,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x0000808C,32.,PORTE_PCRn31,'Pin Control Register(PORTE_PCRn)',,,,rw
,,,PS,'Pull Select',0.,0.,,rw
,,,PE,'Pull Enable',1.,1.,,rw
,,,RSVD_2,'This field is reserved',2.,2.,,rw
,,,SRE,'Slew Rate Enable',3.,3.,,rw
,,,PFE,'Passive Filter Enable',4.,4.,,rw
,,,ODE,'Open Drain Enable',5.,5.,,rw
,,,DSE,'Drive Strength Enable',6.,6.,,rw
,,,RSVD_7,'This field is reserved',7.,7.,,rw
,,,MUX,'Pin Mux Control',8.,10.,,rw
,,,RSVD_14_11,'This field is reserved',11.,14.,,rw
,,,LK,'Lock Register',15.,15.,,rw
,,,IRQC,'Interrupt Configuration',16.,19.,,rw
,,,RSVD_22_20,'This field is reserved',20.,22.,,rw
,,,ISF,'Interrupt Status Flag',23.,23.,,rw
,,,FLT,'filter configuration',24.,28.,,rw
,,,RSVD_30_29,'This field is reserved',29.,30.,,rw
,,,FLTEN,'filter enable',31.,31.,,rw
,0x00008090,32.,PORTE_IRQFLG,'Interrupt Status Flag Register (PORTE_IRQFLG)',,,,rw
,,,ISF,'Interrupt Status Flag',0.,31.,,rw
tree.end
base ad:0x40052000
tree "WDOG"
,0x00000000,32.,WDOG_VERID,'Watchdog Version Idenfication(WDOG_VERID)',,,,rd
,,,MINOR,'Minor version',0.,3.,,rd
,,,MAJOR,'Major version',4.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,WDOG_PARAM,'Watchdog Parameter(WDOG_PARAM)',,,,rd
,,,INT_PRESENT,'Interrrupt function is present.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x00000008,32.,WDOG_CS,'Watchdog Control and Status Registers(WDOG_CS)',,,,rw
,,,WDOGE,'Watchdog enabled.',0.,0.,,rw
,,,DEBUGE,'Watchdog counter enabled in debug mode.',1.,1.,,rw
,,,WAITE,'Watchdog counter enabled in wait mode.',2.,2.,,rw
,,,STOPE,'Watchdog counter enabled in stop mode.',3.,3.,,rw
,,,INTE,'Watchdog interrupt enable.',4.,4.,,rw
,,,WINE,'Watchdog window mode enable.',5.,5.,,rw
,,,CFGUA,'Configuration update allow.',6.,6.,,rw
,,,RSVD_7,'Reserved',7.,7.,,rw
,,,CLKS,'wdog clock source',8.,9.,,rw
,,,RSVD_15_10,'Reserved',10.,15.,,rw
,,,TSTM,'Fast test mode.',16.,18.,,rw
,,,RSVD_23_19,'Reserved',19.,23.,,rw
,,,CFGUF,'Flag indcates configuration update is accompished. ',24.,24.,,rw
,,,UNLKF,'Flag indcates all registers are locked or unlocked. ',25.,25.,,rw
,,,INTF,'Counter overflow interrupt flag. Write 1 to clear.',26.,26.,,rw
,,,RSVD_31_27,'Reserved',27.,31.,,rw
,0x0000000C,32.,WDOG_TMO,'Watchdog Timeout Register(WDOG_TMO)',,,,rw
,,,TMO,'Watchdog Timeout Value. ',0.,31.,,rw
,0x00000010,32.,WDOG_WIN,'Watchdog Window Register(WDOG_WIN)',,,,rw
,,,WIN,'Watchdog Window value. ',0.,31.,,rw
,0x00000014,32.,WDOG_CNT,'Watchdog Counter Register(WDOG_CNT)',,,,rw
,,,CNT,'Watchdog counter value. ',0.,31.,,rw
tree.end
base ad:0x40054000
tree "I2S0"
,0x00000000,32.,I2S0_I2S_CONTROL,'I2S control register(I2S_CONTROL)',,,,rw
,,,I2S_MODULE_EN,'I2S module enable',0.,0.,,rw
,,,I2S_TE,'I2S transmit enable',1.,1.,,rw
,,,I2S_RE,'I2S receiver enable',2.,2.,,rw
,,,I2S_TXFIFO_RESET,'I2S TXFIFO reset bit',3.,3.,,rw
,,,I2S_RXFIFO_RESET,'I2S RXFIFO reset bit',4.,4.,,rw
,,,RSVD_31_5,'reserve',5.,31.,,rw
,0x00000004,32.,I2S0_I2S_MASTER_CONFIG,'I2S master configure register(I2S_MASTER_CONFIG)',,,,rw
,,,I2S_MASTER_EN,'I2S master mode enable bit',0.,0.,,rw
,,,I2S_NUM_BCLK,'I2S number of bclk cycles ',1.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,I2S_NUM_BCLK_GATE,'I2S gated after the number of bclk cycles ',5.,7.,,rw
,,,MCK_DIV,'i2s mclk divider',8.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000008,32.,I2S0_I2S_CHANNEL0_LEFT_DATA,'I2S left data0 register(I2S_LEFT_DATA0)',,,,rw
,,,LEFT_DATA0,'channel0 left data',0.,31.,,rw
,0x0000000C,32.,I2S0_I2S_CHANNEL0_RIGHT_DATA,'I2S right data0 register(I2S_RIGHT_DATA0)',,,,rw
,,,RIGHT_DATA0,'channel0 right data',0.,31.,,rw
,0x00000010,32.,I2S0_I2S_CHANNEL0_CFG,'I2S channel0 configure (I2S_CHANNEL0_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000014,32.,I2S0_I2S_CHANNEL0_INT_CFG,'I2S channel0 interrupt register(I2S_CHANNEL0_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000018,32.,I2S0_I2S_CHANNEL0_TRIGGER_LEVEL_CFG,'I2S channel0 trigger level configure(I2S_CHANNEL0_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000001C,32.,I2S0_I2S_CHANNEL1_LEFT_DATA,'I2S left data0 register(I2S_LEFT_DATA1)',,,,rw
,,,LEFT_DATA1,'channel1 left data',0.,31.,,rw
,0x00000020,32.,I2S0_I2S_CHANNEL1_RIGHT_DATA,'I2S right data1 register(I2S_RIGHT_DATA1)',,,,rw
,,,RIGHT_DATA1,'channel1 right data',0.,31.,,rw
,0x00000024,32.,I2S0_I2S_CHANNEL1_CFG,'I2S channel1 configure (I2S_CHANNEL1_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000028,32.,I2S0_I2S_CHANNEL1_INT_CFG,'I2S channel1 interrupt register(I2S_CHANNEL1_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000002C,32.,I2S0_I2S_CHANNEL1_TRIGGER_LEVEL_CFG,'I2S channel1 trigger level configure(I2S_CHANNEL1_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000030,32.,I2S0_I2S_CHANNEL2_LEFT_DATA,'I2S left data2 register(I2S_LEFT_DATA0)',,,,rw
,,,LEFT_DATA0,'channel2 left data',0.,31.,,rw
,0x00000034,32.,I2S0_I2S_CHANNEL2_RIGHT_DATA,'I2S right data2 register(I2S_RIGHT_DATA0)',,,,rw
,,,RIGHT_DATA0,'channel2 right data',0.,31.,,rw
,0x00000038,32.,I2S0_I2S_CHANNEL2_CFG,'I2S channel2 configure (I2S_CHANNEL0_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000003C,32.,I2S0_I2S_CHANNEL2_INT_CFG,'I2S channel2 interrupt register(I2S_CHANNEL2_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000040,32.,I2S0_I2S_CHANNEL2_TRIGGER_LEVEL_CFG,'I2S channel2 trigger level configure(I2S_CHANNEL2_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000044,32.,I2S0_I2S_CHANNEL3_LEFT_DATA,'I2S left data3 register(I2S_LEFT_DATA3)',,,,rw
,,,LEFT_DATA3,'channel3 left data',0.,31.,,rw
,0x00000048,32.,I2S0_I2S_CHANNEL3_RIGHT_DATA,'I2S right data3 register(I2S_RIGHT_DATA3)',,,,rw
,,,RIGHT_DATA3,'channel3 right data',0.,31.,,rw
,0x0000004C,32.,I2S0_I2S_CHANNEL3_CFG,'I2S channel3 configure (I2S_CHANNEL3_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000050,32.,I2S0_I2S_CHANNEL3_INT_CFG,'I2S channel3 interrupt register(I2S_CHANNEL3_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000054,32.,I2S0_I2S_CHANNEL3_TRIGGER_LEVEL_CFG,'I2S channel3 trigger level configure(I2S_CHANNEL3_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000058,32.,I2S0_I2S_CYCLE_TX_DATA,'I2S cycle tx data register',,,,rw
,,,CYCLE_TX_DATA,'cycle repeatedly tx data',0.,31.,,rw
,0x0000005C,32.,I2S0_I2S_CYCLE_TX_RESET,'  I2S cycle tx data reset register(I2S_CYCLE_TX_RESET)',,,,rw
,,,CYCLE_TX_RESET,'i2s cycle tx reset ',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
,0x00000060,32.,I2S0_I2S_CYCLE_RX_DATA,'I2S cycle RX data register(I2S_CYCLE_RX_DATA)',,,,rw
,,,CYCLE_RX_DATA,'cycle repeatedly rx data',0.,31.,,rw
,0x00000064,32.,I2S0_I2S_CYCLE_RX_RESET,'  I2S cycle rx data reset register(I2S_CYCLE_RX_RESET)',,,,rw
,,,CYCLE_RX_RESET,'i2s cycle rx reset ',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
tree.end
base ad:0x40055000
tree "I2S1"
,0x00000000,32.,I2S1_I2S_CONTROL,'I2S control register(I2S_CONTROL)',,,,rw
,,,I2S_MODULE_EN,'I2S module enable',0.,0.,,rw
,,,I2S_TE,'I2S transmit enable',1.,1.,,rw
,,,I2S_RE,'I2S receiver enable',2.,2.,,rw
,,,I2S_TXFIFO_RESET,'I2S TXFIFO reset bit',3.,3.,,rw
,,,I2S_RXFIFO_RESET,'I2S RXFIFO reset bit',4.,4.,,rw
,,,RSVD_31_5,'reserve',5.,31.,,rw
,0x00000004,32.,I2S1_I2S_MASTER_CONFIG,'I2S master configure register(I2S_MASTER_CONFIG)',,,,rw
,,,I2S_MASTER_EN,'I2S master mode enable bit',0.,0.,,rw
,,,I2S_NUM_BCLK,'I2S number of bclk cycles ',1.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,I2S_NUM_BCLK_GATE,'I2S gated after the number of bclk cycles ',5.,7.,,rw
,,,MCK_DIV,'i2s mclk divider',8.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000008,32.,I2S1_I2S_CHANNEL0_LEFT_DATA,'I2S left data0 register(I2S_LEFT_DATA0)',,,,rw
,,,LEFT_DATA0,'channel0 left data',0.,31.,,rw
,0x0000000C,32.,I2S1_I2S_CHANNEL0_RIGHT_DATA,'I2S right data0 register(I2S_RIGHT_DATA0)',,,,rw
,,,RIGHT_DATA0,'channel0 right data',0.,31.,,rw
,0x00000010,32.,I2S1_I2S_CHANNEL0_CFG,'I2S channel0 configure (I2S_CHANNEL0_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000014,32.,I2S1_I2S_CHANNEL0_INT_CFG,'I2S channel0 interrupt register(I2S_CHANNEL0_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000018,32.,I2S1_I2S_CHANNEL0_TRIGGER_LEVEL_CFG,'I2S channel0 trigger level configure(I2S_CHANNEL0_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000001C,32.,I2S1_I2S_CHANNEL1_LEFT_DATA,'I2S left data0 register(I2S_LEFT_DATA1)',,,,rw
,,,LEFT_DATA1,'channel1 left data',0.,31.,,rw
,0x00000020,32.,I2S1_I2S_CHANNEL1_RIGHT_DATA,'I2S right data1 register(I2S_RIGHT_DATA1)',,,,rw
,,,RIGHT_DATA1,'channel1 right data',0.,31.,,rw
,0x00000024,32.,I2S1_I2S_CHANNEL1_CFG,'I2S channel1 configure (I2S_CHANNEL1_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000028,32.,I2S1_I2S_CHANNEL1_INT_CFG,'I2S channel1 interrupt register(I2S_CHANNEL1_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000002C,32.,I2S1_I2S_CHANNEL1_TRIGGER_LEVEL_CFG,'I2S channel1 trigger level configure(I2S_CHANNEL1_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000030,32.,I2S1_I2S_CHANNEL2_LEFT_DATA,'I2S left data2 register(I2S_LEFT_DATA0)',,,,rw
,,,LEFT_DATA0,'channel2 left data',0.,31.,,rw
,0x00000034,32.,I2S1_I2S_CHANNEL2_RIGHT_DATA,'I2S right data2 register(I2S_RIGHT_DATA0)',,,,rw
,,,RIGHT_DATA0,'channel2 right data',0.,31.,,rw
,0x00000038,32.,I2S1_I2S_CHANNEL2_CFG,'I2S channel2 configure (I2S_CHANNEL0_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000003C,32.,I2S1_I2S_CHANNEL2_INT_CFG,'I2S channel2 interrupt register(I2S_CHANNEL2_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000040,32.,I2S1_I2S_CHANNEL2_TRIGGER_LEVEL_CFG,'I2S channel2 trigger level configure(I2S_CHANNEL2_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000044,32.,I2S1_I2S_CHANNEL3_LEFT_DATA,'I2S left data3 register(I2S_LEFT_DATA3)',,,,rw
,,,LEFT_DATA3,'channel3 left data',0.,31.,,rw
,0x00000048,32.,I2S1_I2S_CHANNEL3_RIGHT_DATA,'I2S right data3 register(I2S_RIGHT_DATA3)',,,,rw
,,,RIGHT_DATA3,'channel3 right data',0.,31.,,rw
,0x0000004C,32.,I2S1_I2S_CHANNEL3_CFG,'I2S channel3 configure (I2S_CHANNEL3_CFG)',,,,rw
,,,TX_EN,'channeln  transmit enable',0.,0.,,rw
,,,RX_EN,'channeln  receive enable',1.,1.,,rw
,,,TX_AUDIO_RESOLUTION,'channeln  tx audio resolution',2.,4.,,rw
,,,RX_AUDIO_RESOLUTION,'channeln rx audio resolution',5.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000050,32.,I2S1_I2S_CHANNEL3_INT_CFG,'I2S channel3 interrupt register(I2S_CHANNEL3_INT_REG)',,,,rw
,,,RXFIFO_AVAILABLE_IE,'RXFIFO data avaliable interrupt enable',0.,0.,,rw
,,,RXFIFO_OVERUN_IE,'RXFIFO overun interrupt enable',1.,1.,,rw
,,,TXFIFO_EMPTY_IE,'TXFIFO empty interrupt enable',2.,2.,,rw
,,,TXFIFO_OVERUN_IE,'TXFIFO overun interrupt enable',3.,3.,,rw
,,,RXFIFO_DAF,'RXFIFO data avaliable flag',4.,4.,,rw
,,,RXFIFO_ORF,'RXFIFO overun flag',5.,5.,,rw
,,,TXFIFO_EMPTYF,'TXFIFO empty flag',6.,6.,,rw
,,,TXFIFO_ORF,'TXFIFO overun flag',7.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000054,32.,I2S1_I2S_CHANNEL3_TRIGGER_LEVEL_CFG,'I2S channel3 trigger level configure(I2S_CHANNEL3_TRIGGER_LEVEL_CFG)',,,,rw
,,,RXFIFO_FULL_TRIG_LEV,'channel RXFIFO full trigger level ',0.,3.,,rw
,,,TXFIFO_EMPTY_TRIG_LEV,'channel TXFIFO empty trigger level ',4.,7.,,rw
,,,CH_TXFIFO_RESET,'channel  TXFIFO channel reset',8.,8.,,rw
,,,CH_RXFIFO_RESET,'channel RXFIFO channel reset',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000058,32.,I2S1_I2S_CYCLE_TX_DATA,'I2S cycle tx data register',,,,rw
,,,CYCLE_TX_DATA,'cycle repeatedly tx data',0.,31.,,rw
,0x0000005C,32.,I2S1_I2S_CYCLE_TX_RESET,'  I2S cycle tx data reset register(I2S_CYCLE_TX_RESET)',,,,rw
,,,CYCLE_TX_RESET,'i2s cycle tx reset ',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
,0x00000060,32.,I2S1_I2S_CYCLE_RX_DATA,'I2S cycle RX data register(I2S_CYCLE_RX_DATA)',,,,rw
,,,CYCLE_RX_DATA,'cycle repeatedly rx data',0.,31.,,rw
,0x00000064,32.,I2S1_I2S_CYCLE_RX_RESET,'  I2S cycle rx data reset register(I2S_CYCLE_RX_RESET)',,,,rw
,,,CYCLE_RX_RESET,'i2s cycle rx reset ',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
tree.end
base ad:0x40056000
tree "CAN6"
,0x00000000,32.,CAN6_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN6_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN6_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN6_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN6_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN6_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN6_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN6_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN6_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN6_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN6_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN6_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN6_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN6_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN6_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN6_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN6_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN6_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN6_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN6_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN6_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN6_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN6_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN6_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN6_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN6_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN6_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN6_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN6_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN6_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN6_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN6_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN6_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN6_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN6_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN6_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN6_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN6_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN6_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN6_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN6_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN6_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN6_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN6_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN6_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN6_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN6_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN6_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN6_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN6_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN6_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN6_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN6_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN6_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN6_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN6_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN6_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN6_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN6_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN6_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN6_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN6_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN6_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN6_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40057000
tree "CAN7"
,0x00000000,32.,CAN7_CAN_MCR,'CAN module configure register(CAN_MCR)',,,,rw
,,,MAXMB,'Reserved',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,IDAM,'ID Acceptance Mode ',8.,9.,,rw
,,,RSVD_10,'reserve',10.,10.,,rw
,,,FDEN,'CAN FD operation enable',11.,11.,,rw
,,,AEN,'Abort Enable',12.,12.,,rw
,,,LPRIOEN,'Local Priority Enable',13.,13.,,rw
,,,PNET_EN,'Pretended Networking Enable ',14.,14.,,rw
,,,DMAE,'DMA Enable',15.,15.,,rw
,,,IRMQ,'Individual Rx Masking And Queue Enable',16.,16.,,rw
,,,SRXDIS,'Self Reception Disable',17.,17.,,rw
,,,DOZE,'Doze Mode Enable ',18.,18.,,rw
,,,WAKSRC,'Wake Up Source ',19.,19.,,rw
,,,LPMACK,'Low-Power Mode Acknowledge ',20.,20.,,rw
,,,WRNEN,'Warning Interrupt Enable ',21.,21.,,rw
,,,SLFWAK,'Self Wake Up ',22.,22.,,rw
,,,SUPV,'Supervisor Mode ',23.,23.,,rw
,,,FRZACK,'Freeze Mode Acknowledge ',24.,24.,,rw
,,,SOFTRST,'Soft Reset ',25.,25.,,rw
,,,WAKMSK,'Wake Up Interrupt Mask ',26.,26.,,rw
,,,NOTRDY,'CAN Not Ready ',27.,27.,,rw
,,,HALT,'Halt CAN ',28.,28.,,rw
,,,RFEN,'Legacy Rx FIFO Enable ',29.,29.,,rw
,,,FRZ,'Freeze Enable',30.,30.,,rw
,,,MDIS,'Module Disable ',31.,31.,,rw
,0x00000004,32.,CAN7_CAN_CTRL1,'CONTROL 1 register(CAN_CTRL1)',,,,rw
,,,PROPSEG,'Propagation Segment ',0.,2.,,rw
,,,LOM,'Listen-Only Mode ',3.,3.,,rw
,,,LBUF,'Lowest Buffer Transmitted First ',4.,4.,,rw
,,,TSYC,'Timer Sync ',5.,5.,,rw
,,,BOFFREC,'Bus Off Recovery ',6.,6.,,rw
,,,SMP,'CAN Bit Sampling ',7.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,RWRNMSK,'Rx Warning Interrupt Mask ',10.,10.,,rw
,,,TWRNMSK,'Tx Warning Interrupt Mask ',11.,11.,,rw
,,,LPB,'Loop Back Mode ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,ERRMSK,'Error interrupt mask',14.,14.,,rw
,,,BOFFMSK,'Bus off interrupt mask',15.,15.,,rw
,,,PSEG2,'Phase segment 2',16.,18.,,rw
,,,PSEG1,'Phase segment 1',19.,21.,,rw
,,,RJW,'Resync Jump Width ',22.,23.,,rw
,,,PRESDIV,'Prescaler Division Factor',24.,31.,,rw
,0x00000008,32.,CAN7_CAN_TIMER,'Free Running Timer register(CAN_TIMER)',,,,rw
,,,TIMER,'free running counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000010,32.,CAN7_CAN_RXMGMSK,'Rx mailbox global mask register(CAN_RXMGMSK)',,,,rw
,,,MG,'Rx mailbox global mask',0.,31.,,rw
,0x00000014,32.,CAN7_CAN_RX14MASK,'Rx 14 mask register(CAN_RX14MASK)',,,,rw
,,,RX14M,'Rx Buffer 14 Mask Bits ',0.,31.,,rw
,0x00000018,32.,CAN7_CAN_RX15MASK,'Rx 15 mask register(CAN_RX15MASK)',,,,rw
,,,RX15M,'Rx Buffer 15 Mask Bits',0.,31.,,rw
,0x0000001C,32.,CAN7_CAN_ECR,'Error counter register(CAN_ECR)',,,,rw
,,,TXERRCNT,'Transmit Error Counter ',0.,7.,,rw
,,,RXERRCNT,'Receive Error Counter ',8.,15.,,rw
,,,TX_ERRCNT_FAST,'Transmit Error Counter for fast bits ',16.,23.,,rw
,,,RX_ERRCNT_FAST,'Receive Error Counter for fast bits ',24.,31.,,rw
,0x00000020,32.,CAN7_CAN_ESR1,'CAN error status register(CAN_ESR1)',,,,rw
,,,WAKINT,'wakeup interrupt',0.,0.,,rw
,,,ERRINT,'error interrupt',1.,1.,,rw
,,,BOFFINT,'bus off interrupt',2.,2.,,rw
,,,RX,'Flexcan in Reception',3.,3.,,rw
,,,FLTCONF,'Fault confinement state',4.,5.,,rw
,,,TX,'Flexcan in transmission',6.,6.,,rw
,,,IDLE,'IDLE',7.,7.,,rw
,,,RXWRN,'Rx warning ',8.,8.,,rw
,,,TXWRN,'tx warning',9.,9.,,rw
,,,STFERR,'stuff erro of non-fd',10.,10.,,rw
,,,FRAMERR,'frame error of non-fd',11.,11.,,rw
,,,CRCERR,'CRC error of non-fd ',12.,12.,,rw
,,,ACKERR,'Acknowledge error of non-fd',13.,13.,,rw
,,,BIT0ERR,'Bit0 error of CAN non-fd',14.,14.,,rw
,,,BIT1ERR,'Bit error of CAN non-fd ',15.,15.,,rw
,,,RWRNINT,'Rx warning Interrupt',16.,16.,,rw
,,,TWRNINT,'Tx Warning Interrupt',17.,17.,,rw
,,,SYNCH,'Synchronous ',18.,18.,,rw
,,,BUSOFFDONEINT,'Bus off done interrupt',19.,19.,,rw
,,,ERRINT_FAST,'error interrupt of errors detect in CAN_FD data phase',20.,20.,,rw
,,,ERROVR,'error of overrun',21.,21.,,rw
,,,RSVD_25_22,'reserve',22.,25.,,rw
,,,STFERR_FAST,'Stuff erro of CAN_FD data phase.',26.,26.,,rw
,,,FRAMERR_FAST,'Frame error of CAN_FD data phase',27.,27.,,rw
,,,CRCERR_FAST,'CRC error in CAN_FD CRC phase',28.,28.,,rw
,,,RSVD_29,'reserve',29.,29.,,rw
,,,BIT0ERR_FAST,'Bit0 error in CAN_FD data phase',30.,30.,,rw
,,,BIT1ERR_FAST,'Bit1 error in CAN_FD data phase',31.,31.,,rw
,0x00000024,32.,CAN7_CAN_IMASK2,'Interrupt mask 2 register(CAN_IMASK2)',,,,rw
,,,BUF63TO32M,'Buffer MB i Mask ',0.,31.,,rw
,0x00000028,32.,CAN7_CAN_IMASK1,'Interrupt mask 1 register(CAN_IMASK1)',,,,rw
,,,BUF31TO0M,'Buffer MB31 -0 Mask',0.,31.,,rw
,0x0000002C,32.,CAN7_CAN_IFLAG2,'Interrupt flag 2 register(CAN_IFLAG2)',,,,rw
,,,BUF63TO32I,'Buffer MB63-32 Mask',0.,31.,,rw
,0x00000030,32.,CAN7_CAN_IFLAG1,'Interrupt flag 1 register(CAN_IFLAG1)',,,,rw
,,,BUF0I,'Buffer0 interrupt',0.,0.,,rw
,,,BUF4TO1I,'Buffer 1-4 interrupt',1.,4.,,rw
,,,BUF5I,'Buffer5 interrupt',5.,5.,,rw
,,,BUF6I,'Buffer6 interrupt',6.,6.,,rw
,,,BUF7I,'Buffer7 interrupt',7.,7.,,rw
,,,BUF31TO8I,'Buffer8-31 interrupt',8.,31.,,rw
,0x00000034,32.,CAN7_CAN_CTRL2,'Control 2 register(CAN_CTRL2)',,,,rw
,,,RSVD_10_0,'reserve',0.,10.,,rw
,,,EDFLTDIS,'Edge Filter Disable ',11.,11.,,rw
,,,ISOCANFDEN,'ISO CAN FD Enable ',12.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,PREXCEN,'Protocol Exception Enable ',14.,14.,,rw
,,,TIMER_SRC,'Timer Source',15.,15.,,rw
,,,EACEN,'Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes',16.,16.,,rw
,,,RRS,'Remote Request Storing',17.,17.,,rw
,,,MRP,'Mailboxes Reception Priority',18.,18.,,rw
,,,TASD,'Tx Arbitration Start Delay',19.,23.,,rw
,,,RFFN,'Number of Rx FIFO Filters ',24.,27.,,rw
,,,WRMFRZ,'Write-Access To Memory In Freeze Mode',28.,28.,,rw
,,,ECRWRE,'error correction register write enable',29.,29.,,rw
,,,BOFFDONEMSK,'bus off done mask ',30.,30.,,rw
,,,ERRMASK_FAST,'error mask of can-fd',31.,31.,,rw
,0x00000038,32.,CAN7_CAN_ESR2,'Error and Status 2 register(CAN_ESR2)',,,,rw
,,,RSVD_12_0,'reserve',0.,12.,,rw
,,,IMB,'Inactive Mailbox',13.,13.,,rw
,,,VPS,'Valid Priority Status',14.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,LPTM,'Lowest Priority Tx Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000044,32.,CAN7_CAN_CRCR,'CRC register(CAN_CRCR)',,,,rw
,,,TXCRC,'Transmitted CRC Value',0.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,MBCRC,'CRC Mailbox',16.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000048,32.,CAN7_CAN_RXFGMASK,'Leagacy FIFO global mask register(CAN_RXFGMASK)',,,,rw
,,,FGM,'Rx FIFO Global Mask Bits',0.,31.,,rw
,0x0000004C,32.,CAN7_CAN_RXFIR,'RX FIFO ID indicator(CAN_RXFIR)',,,,rw
,,,IDHIT,'ID Hit incicator',0.,8.,,rw
,,,RSVD_31_9,'reserve',9.,31.,,rw
,0x00000050,32.,CAN7_CAN_CBT,'CAN bit timing register(CAN_CBT)',,,,rw
,,,EPSEG2,'Extended Phase Segment 2',0.,4.,,rw
,,,EPSEG1,'Extended Phase Segment 1',5.,9.,,rw
,,,EPROPSEG,'Extended Propagation Segment',10.,15.,,rw
,,,ERJW,'Extended Resync Jump Width',16.,20.,,rw
,,,EPRESDIV,'Extended Prescaler Division Factor',21.,30.,,rw
,,,BTF,'Bit Timing Format Enable ',31.,31.,,rw
,0x00000068,32.,CAN7_CAN_IMASK4,'Interrupt mask 4 register(CAN_IMASK4)',,,,rw
,,,BUF127TO96M,'Buffer MB 127-96 Mask',0.,31.,,rw
,0x0000006C,32.,CAN7_CAN_IMASK3,'Interrupt mask 3 register(CAN_IMASK3)',,,,rw
,,,BUF95TO64M,'Buffer MB 95-64 Mask',0.,31.,,rw
,0x00000070,32.,CAN7_CAN_IFLAG4,'Interrupt flag 4 register(CAN_IFLAG4)',,,,rw
,,,BUF127TO96I,'Buffer MB 127-96 Interrupt',0.,31.,,rw
,0x00000074,32.,CAN7_CAN_IFLAG3,'Interrupt flag 3 register(CAN_IFLAG3)',,,,rw
,,,BUF95TO64I,'Buffer MB 95-64 Interrupt',0.,31.,,rw
,0x00000080,32.,CAN7_CAN_MB0_CS,'reserve',,,,rw
,,,TIME_STAMP,'Free-Running Counter Time Stamp ',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request ',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_23,'reserve',23.,23.,,rw
,,,CODE,'Message Buffer Code ',24.,27.,,rw
,,,RSVD_28,'reserve',28.,28.,,rw
,,,ESI,'Error State Indicator ',29.,29.,,rw
,,,BRS,'Bit Rate Switch ',30.,30.,,rw
,,,EDL,'Extended Data Length ',31.,31.,,rw
,0x00000084,32.,CAN7_CAN_MB0_ID,'Message buffer ID register(CAN_MB0_ID)',,,,rw
,,,ID_EXTEND,'Frame Identifier ',0.,17.,,rw
,,,ID_STD_EXD,'Frame Identifier ',18.,28.,,rw
,,,PRIO,' Local priority ',29.,31.,,rw
,0x00000088,32.,CAN7_CAN_MB0_DATA03,'Message buffer date03 register(CAN_MB0_DATA03)',,,,rw
,,,DATA_BYTE03,'data byte0-3',0.,31.,,rw
,0x0000008C,32.,CAN7_CAN_MB0_DATA47,'Message buffer date47 register(CAN_MB0_DAT47)',,,,rw
,,,DATA_BYTE47,'data byte0-3',0.,31.,,rw
,0x00000880,32.,CAN7_CAN_RXIMRn,'RX individual mask register(CAN_RXIMRn)',,,,rw
,,,MI,'Individual Mask Bits',0.,31.,,rw
,0x00000AE0,32.,CAN7_CAN_MECR,'Memory error control register(CAN_MECR)',,,,rw
,,,RSVD_6_0,'reserve',0.,6.,,rw
,,,NCEFAFRZ,'Non-Correctable Errors In CAN Access Put Device In Freeze Mode ',7.,7.,,rw
,,,ECCDIS,'Error Correction Disable ',8.,8.,,rw
,,,RERRDIS,'Error Report Disable ',9.,9.,,rw
,,,RSVD_12_10,'reserve',10.,12.,,rw
,,,EXTERRIE,'Extended Error Injection ',13.,13.,,rw
,,,FAERRIE,'CAN Access Error Injection Enable ',14.,14.,,rw
,,,HAERRI,'Host Access Error Injection Enable ',15.,15.,,rw
,,,CEI_MSK,'Correctable Errors Interrupt Mask',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEI_MSK,'CAN Access With Non-Correctable Errors Interrupt Mask ',18.,18.,,rw
,,,HANCEI_MSK,'Host Access with Non-Correctable Errors Interrupt Mask',19.,19.,,rw
,,,RSVD_30_20,'reserve',20.,30.,,rw
,,,ECRWRDIS,'Error Configuration Register Write Disable ',31.,31.,,rw
,0x00000AE4,32.,CAN7_CAN_ERRIAR,'Error injection address regsiter(CAN_ERRIAR)',,,,rw
,,,INJADDR_L,'Error Injection Address Low ',0.,1.,,rw
,,,INJADDR_H,'Error Injection Address High',2.,13.,,rw
,,,RSVD_31_14,'Reserved',14.,31.,,rw
,0x00000AE8,32.,CAN7_CAN_ERRIDPR,'Error injection data pattern register(CAN_ERRIDPR)',,,,rw
,,,DFLIP,'Data Flip Pattern',0.,31.,,rw
,0x00000AEC,32.,CAN7_CAN_ERRIPPR,'Error injection parity pattern register(CAN_ERRIPPR)',,,,rw
,,,PFLIP0,'Parity Flip Pattern For Byte 0',0.,4.,,rw
,,,RSVD_7_5,'reserve',5.,7.,,rw
,,,PFLIP1,'Parity Flip Pattern For Byte 1',8.,12.,,rw
,,,RSVD_15_13,'reserve',13.,15.,,rw
,,,PFLIP2,'Parity Flip Pattern For Byte 2',16.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,PFLIP3,'Parity Flip Pattern For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000AF0,32.,CAN7_CAN_RERRAR,'Error report address register(CAN_RERRAR)',,,,rw
,,,ERRADDR,'Address Where the Error was Detected',0.,13.,,rw
,,,RSVD_15_14,'reserve',14.,15.,,rw
,,,SAID,'SAID[2]: Identification of the requestor of the memory read request',16.,18.,,rw
,,,RSVD_23_19,'reserve',19.,23.,,rw
,,,NCE,'Non-Correctable Error: Indicates that the report is due to a non-correctable error',24.,24.,,rw
,,,RSVD_31_25,'reserve',25.,31.,,rw
,0x00000AF4,32.,CAN7_CAN_RERRDR,'Error report data register(CAN_RERRDR)',,,,rw
,,,RDATA,'Raw data word read from memory with error',0.,31.,,rw
,0x00000AF8,32.,CAN7_CAN_RERRSYNR,'Error report Syndrome reigster(CAN_RERRSYNR)',,,,rw
,,,SYND0,'Error Syndrome For Byte 0',0.,4.,,rw
,,,RSVD_6_5,'reserve',5.,6.,,rw
,,,BE0,'Byte Enabled For Byte 0 (least significant)',7.,7.,,rw
,,,SYND1,'Error Syndrome For Byte 1',8.,12.,,rw
,,,RSVD_14_13,'reserve',13.,14.,,rw
,,,BE1,'Byte Enabled For Byte 1',15.,15.,,rw
,,,SYND2,'Error Syndrome For Byte 2',16.,20.,,rw
,,,RSVD_22_21,'reserve',21.,22.,,rw
,,,BE2,'Error Syndrome For Byte 3 (most significant)',23.,23.,,rw
,,,SYND3,'Error Syndrome For Byte 3 (most significant)',24.,28.,,rw
,,,RSVD_30_29,'reserve',29.,30.,,rw
,,,BE3,'Byte Enabled For Byte 3 (most significant)',31.,31.,,rw
,0x00000AFC,32.,CAN7_CAN_ERRSR,'Error status register(CAN_ERRSR)',,,,rw
,,,CEIOF,'Correctable Error Interrupt Overrun Flag',0.,0.,,rw
,,,RSVD_1,'reserve',1.,1.,,rw
,,,FANCEIOF,'CAN Access With Non-Correctable Error Interrupt Overrun Flag',2.,2.,,rw
,,,HANCEIOF,'Host Access with Non-Correctable Error Interrupt Overrun Flag',3.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,CEIF,'Correctable Error Interrupt Flag',16.,16.,,rw
,,,RSVD_17,'reserve',17.,17.,,rw
,,,FANCEIF,'CAN Access with Non-Correctable Error Interrupt Flag',18.,18.,,rw
,,,HANCEIF,'Host Access with Non-Correctable Error Interrupt Flag',19.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B00,32.,CAN7_CAN_CTRL1_PN,'Pretend network control 1 register(CAN_CTRL1_PN)',,,,rw
,,,FCS,'Filtering Combination Selection',0.,1.,,rw
,,,IDFS,'ID Filtering Selection ',2.,3.,,rw
,,,PLFS,'Payload Filtering Selection ',4.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,NMATCH,'Number of Messages Matching the Same Filtering Criteria ',8.,15.,,rw
,,,WUMF_MSK,'Wake Up by Match Flag Mask Bit ',16.,16.,,rw
,,,WTOF_MSK,'Wake Up by Timeout Flag Mask Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B04,32.,CAN7_CAN_CTRL2_PN,'Pretend network control 2 register(CAN_CTRL2_PN)',,,,rw
,,,MATCHTO,'Timeout for No Message Matching the Filtering Criteria ',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000B08,32.,CAN7_CAN_WU_MTC,'Pretend network wakeup match register(CAN_WU_MTC)',,,,rw
,,,RSVD_7_0,'Reserved',0.,7.,,rw
,,,MCOUNTER,'Number of Matches when in Pretended Networking ',8.,15.,,rw
,,,WUMF,'Wake Up by Match Flag Bit ',16.,16.,,rw
,,,WTOF,'Wake Up by Timeout Flag Bit ',17.,17.,,rw
,,,RSVD_31_18,'reserve',18.,31.,,rw
,0x00000B0C,32.,CAN7_CAN_FLT_ID1,'Pretend network ID filter 1 register(CAN_FLT_ID1)',,,,rw
,,,FLT_ID1,'ID Filter 1 for Pretended Networking Filtering',0.,28.,,rw
,,,FLT_RTR,'Remote Transmission Request Filter ',29.,29.,,rw
,,,FLT_IDE,'Number of Matches when in Pretended Networking ',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B10,32.,CAN7_CAN_FLT_DLC,'Pretend network DLC filter register(CAN_FLT_DLC)',,,,rw
,,,FLT_DLC_HI,'Upper Limit for Length of Data Bytes Filter ',0.,3.,,rw
,,,RSVD_15_4,'reserve',4.,15.,,rw
,,,FLT_DLC_LO,'Lower Limit for Length of Data Bytes Filter ',16.,19.,,rw
,,,RSVD_31_20,'reserve',20.,31.,,rw
,0x00000B14,32.,CAN7_CAN_PL1_LO,'Pretend network payload low filter 1 register(CAN_PL1_LO)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B18,32.,CAN7_CAN_PL1_HI,'Pretend network payload high filter 1 register(CAN_PL1_HI)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B1C,32.,CAN7_CAN_FLT_ID2_IDMASK,'Pretended Networking ID Filter 2 Register / ID Mask',,,,rw
,,,FLT_ID2_IDMASK,'ID Filter 2 for Pretended Networking Filtering/ ID Mask Bits for Pretended Networking ID Filtering ',0.,28.,,rw
,,,RTR_MSK,'Remote Transmission Request Mask Bit',29.,29.,,rw
,,,IDE_MSK,'ID Extended Mask Bit',30.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
,0x00000B20,32.,CAN7_CAN_PL2_PLMASK_LO,'Pretended Networking Payload Low Filter 2 Register /',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B24,32.,CAN7_CAN_PL2_PLMASK_HI,' Pretended Networking Payload High Filter 2 low order',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B40,32.,CAN7_CAN_WMBn_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B44,32.,CAN7_CAN_WMBn_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B48,32.,CAN7_CAN_WMBn_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B4C,32.,CAN7_CAN_WMBn_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B50,32.,CAN7_CAN_WMB1_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B54,32.,CAN7_CAN_WMB1_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B58,32.,CAN7_CAN_WMB1_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B5C,32.,CAN7_CAN_WMB1_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B60,32.,CAN7_CAN_WMB2_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B64,32.,CAN7_CAN_WMB2_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B68,32.,CAN7_CAN_WMB2_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B6C,32.,CAN7_CAN_WMB2_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000B70,32.,CAN7_CAN_WMB3_CS,'Wake Up Message Buffer Register for C/S(CAN_WMBn_CS)',,,,rw
,,,RSVD_15_0,'reserve',0.,15.,,rw
,,,DLC,' Length of Data in Bytes ',16.,19.,,rw
,,,RTR,'Remote Transmission Request Bit',20.,20.,,rw
,,,IDE,'ID Extended Bit ',21.,21.,,rw
,,,SRR,'Substitute Remote Request ',22.,22.,,rw
,,,RSVD_31_23,'reserve',23.,31.,,rw
,0x00000B74,32.,CAN7_CAN_WMB3_ID,'Wake Up Message Buffer Register for ID(CAN_WMBn_ID)',,,,rw
,,,ID,'Received ID under Pretended Networking mode ',0.,28.,,rw
,,,RSVD_31_29,'reserve',29.,31.,,rw
,0x00000B78,32.,CAN7_CAN_WMB3_D03,'Wake Up Message Buffer Register for Data 0-3(CAN_WMBn_D03)',,,,rw
,,,DATA_BYTE_3,'Reserved',0.,7.,,rw
,,,DATA_BYTE_2,'Reserved',8.,15.,,rw
,,,DATA_BYTE_1,'Reserved',16.,23.,,rw
,,,DATA_BYTE_0,'Reserved',24.,31.,,rw
,0x00000B7C,32.,CAN7_CAN_WMB3_D47,'Wake Up Message Buffer Register for Data 4-7(CAN_WMBn_D47)',,,,rw
,,,DATA_BYTE_7,'Reserved',0.,7.,,rw
,,,DATA_BYTE_6,'Reserved',8.,15.,,rw
,,,DATA_BYTE_5,'Reserved',16.,23.,,rw
,,,DATA_BYTE_4,'Reserved',24.,31.,,rw
,0x00000C00,32.,CAN7_CAN_FDCTRL,'CAN FD control register(CAN_FDCTRL)',,,,rw
,,,TDCVAL,'Transceiver Delay Compensation Value ',0.,5.,,rw
,,,RSVD_7_6,'reserve',6.,7.,,rw
,,,TDCOFF,'Transceiver Delay Compensation Offset ',8.,12.,,rw
,,,RSVD_13,'reserve',13.,13.,,rw
,,,TDCFAIL,'Transceiver Delay Compensation Fail ',14.,14.,,rw
,,,TDCEN,'Transceiver Delay Compensation Enable ',15.,15.,,rw
,,,MBDSR0,'Message Buffer Data Size for Region 0 ',16.,17.,,rw
,,,RSVD_18,'reserve',18.,18.,,rw
,,,MBDSR1,'Message Buffer Data Size for Region 1 ',19.,20.,,rw
,,,RSVD_21,'reserve',21.,21.,,rw
,,,MBDSR2,'Message Buffer Data Size for Region 2',22.,23.,,rw
,,,RSVD_24,'reserve',24.,24.,,rw
,,,MBDSR3,'Message Buffer Data Size for Region 3 ',25.,26.,,rw
,,,RSVD_30_27,'reserve',27.,30.,,rw
,,,FD_RATE,'Bit Rate Switch Enable ',31.,31.,,rw
,0x00000C04,32.,CAN7_CAN_FDCBT,'CAN FD bit timing control register(CAN_FDCBT)',,,,rw
,,,FPSEG2,'Fast Phase Segment 2 ',0.,2.,,rw
,,,RSVD_4_3,'reserve',3.,4.,,rw
,,,FPSEG1,'Fast Phase Segment 1 ',5.,7.,,rw
,,,RSVD_9_8,'reserve',8.,9.,,rw
,,,FPROPSEG,'Fast Propagation Segment ',10.,14.,,rw
,,,RSVD_15,'reserve',15.,15.,,rw
,,,FRJW,'Fast Resync Jump Width ',16.,18.,,rw
,,,RSVD_19,'reserve',19.,19.,,rw
,,,FPRESDIV,'Fast Prescaler Division Factor ',20.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000C08,32.,CAN7_CAN_FDCRC,'CAN FD CRC register(CAN_FDCRC)',,,,rw
,,,FD_TXCRC,'Extended Transmitted CRC value ',0.,20.,,rw
,,,RSVD_23_21,'reserve',21.,23.,,rw
,,,FD_MBCRC,'CRC Mailbox Number for FD_TXCRC ',24.,30.,,rw
,,,RSVD_31,'reserve',31.,31.,,rw
tree.end
base ad:0x40058000
tree "I2C1"
,0x00000000,32.,I2C1_I2C_VERID,'I2C Version ID(I2C_VERID)',,,,rw
,,,VERID,'version ID',0.,31.,,rw
,0x00000004,32.,I2C1_I2C_PARAMETER,'I2C Parameter Register(I2C_PARAMETER)',,,,rw
,,,I2C_SUPPORT_SPEED,'I2C transfer speed  supported',0.,1.,,rw
,,,DMA_SUPPORT,'DMA support bit',2.,2.,,rw
,,,TXFIFO_DEPTH,'TX FIFO depth',3.,6.,,rw
,,,RXFIFO_DEPTH,'RX FIFO depth',7.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000008,32.,I2C1_I2C_CONFIG0,'I2C Configure0  Register(I2C_CONFIG0)',,,,rw
,,,MODULE_EN,'module enable bit',0.,0.,,rw
,,,SLAVE_ACK_GENCALL,'slave general call ack',1.,1.,,rw
,,,SLAVE_NACK,'slave nack bit',2.,2.,,rw
,,,SDA_RECOVER_EN,'SDA recover feature enable ',3.,3.,,rw
,,,MASTER_ABORT,'master abort transfer bit',4.,4.,,rw
,,,MASTER_BUS_RECOVER_EN,'enable I2C master bus recover feature',5.,5.,,rw
,,,MASTER_BLK_TXFIFO,'block master TX FIFO transfer',6.,6.,,rw
,,,H_MCODE,'high speed master code',7.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000000C,32.,I2C1_I2C_CONFIG1,'I2C Configure1 Register(I2C_CONFIG1)',,,,rw
,,,SLAVE_MODE_DIS,'slave mode disable',0.,0.,,rw
,,,MASTER_MODE_EN,'master mode enable',1.,1.,,rw
,,,MASTER_RESTART_EN,'enable restart feature during master mode',2.,2.,,rw
,,,SLAVE_STOP_DET_EN,'stop detect feature enable during slave mode',3.,3.,,rw
,,,MASTER_STOP_DET_EN,'stop detect feature enable during master mode',4.,4.,,rw
,,,TXFIFO_EMPTY_EN,'allow generate TXFIFO empty flag.',5.,5.,,rw
,,,SPEED_SEL,'I2C speed select',6.,7.,,rw
,,,HOLD_EN_RXFIFO_FULL,'hold I2C bus feature enable when RXFIFO is full.',8.,8.,,rw
,,,SLAVE_10BIT_ADDR_SEL,'slave 10bit address mode select',9.,9.,,rw
,,,MASTER_10BIT_ADDR_SEL,'master 10bit address mode select',10.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000010,32.,I2C1_I2C_SDA_SETUP_TIMING,'I2C SDA Setup Timing Register(I2C_SDA_SETUP_TIMING)',,,,rw
,,,SDA_SETUP_TIMING,'SDA setup timing value',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000014,32.,I2C1_I2C_SDA_HOLD_TIMING,'I2C SDA Hold Timing Register(I2C_SDA_HOLD_TIMING)',,,,rw
,,,SDA_TX_HOLD_TIMING,'SDA TX hold timing value',0.,15.,,rw
,,,SDA_RX_HOLD_TIMING,'SDA RX hold timing value',16.,23.,,rw
,,,RSVD_31_24,'reserve',24.,31.,,rw
,0x00000018,32.,I2C1_I2C_DMA_CTRL,'I2C DMA Control Register(I2C_DMA_CTRL)',,,,rw
,,,RXFIFO_DMA_EN,'RXFIFO DMA enable',0.,0.,,rw
,,,TXFIFO_DMA_EN,'TXFIFO DMA enable',1.,1.,,rw
,,,DMA_TXFIFO_WATERMARK,'DMA TXFIFO watermark',2.,3.,,rw
,,,DMA_RXFIFO_WATERMARK,'DMA RXFIFO watermark ',4.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x0000001C,32.,I2C1_I2C_INT_ENABLE,'I2C Interrupt Enable Register(I2C_INT_ENABLE)',,,,rw
,,,I2C_CALL_IE,'I2C general call interrupt enable',0.,0.,,rw
,,,I2C_TX_OVF_IE,'I2C TX overun interrupt enable',1.,1.,,rw
,,,I2C_ERROR_ABORT_IE,'I2C Error abort interrupt enable',2.,2.,,rw
,,,I2C_ACTIVITY_DET_IE,'I2C activity detect interrupt enable',3.,3.,,rw
,,,I2C_STOP_DET_IE,'I2C stop detect interrupt enable',4.,4.,,rw
,,,I2C_START_DET_IE,'I2C start detect interrupt enable',5.,5.,,rw
,,,RSVD_21_6,'reserve',6.,21.,,rw
,,,SLAVE_RD_REQ_IE,'slave read request interrupt enable',22.,22.,,rw
,,,RX_DONE_IE,'RX done interrupt enable',23.,23.,,rw
,,,RX_UNDER_IE,'RX under interrupt enable',24.,24.,,rw
,,,RX_OVF_IE,'RX overun interrupt enable',25.,25.,,rw
,,,RESTART_DET_IE,'restart detect interrupt enable',26.,26.,,rw
,,,SCL_STUCK_AT_LOW_IE,'SCL stuck at low interrupt enable',27.,27.,,rw
,,,RSVD_29_28,'reserve',28.,29.,,rw
,,,RX_FULL_IE,'RXFIFO interrupt enable',30.,30.,,rw
,,,TX_EMPTY_IE,'TXFIFO interrupt enable',31.,31.,,rw
,0x00000020,32.,I2C1_I2C_COMMAND_DATA,'I2C Rx/Tx Data Buffer and Command Register(I2C_COMMAND_DATA)',,,,rw
,,,DATA,'data',0.,7.,,rw
,,,CMD_MASTER_DIRECTION,'command direction',8.,8.,,rw
,,,CMD_STOP,'command stop',9.,9.,,rw
,,,CMD_RESTART,'command restart',10.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000024,32.,I2C1_I2C_DEST_ADDR,'I2C Target Address Register(I2C_DEST_ADDR)',,,,rw
,,,DEST_ADDR,'destination addresss',0.,9.,,rw
,,,MASTER_CMD_SEL,'master command select',10.,11.,,rw
,,,RSVD_31_12,'reserve',12.,31.,,rw
,0x00000028,32.,I2C1_I2C_SLAVE_ADDR,'I2C Slave Address Register(I2C_SLAVE_ADDR)',,,,rw
,,,SLV_ADDR,'slave address',0.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000002C,32.,I2C1_I2C_STD_SCL_HCNT,' Standard Speed I2C SCL High Count register(I2C_STD_SCL_HCNT)',,,,rw
,,,STD_SCL_HCNT,'standard SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000030,32.,I2C1_I2C_STD_SCL_LCNT,' Standard Speed  I2C SCL Low Count Register(I2C_STD_SCL_LCNT)',,,,rw
,,,STD_SCL_LCNT,'standard SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000034,32.,I2C1_I2C_FST_SCL_HCNT,'Fast Mode I2C SCL High Count Register(I2C_FST_SCL_HCNT)',,,,rw
,,,FST_SCL_HCNT,'Fast SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000038,32.,I2C1_I2C_FST_SCL_LCNT,'Fast Mode  I2C SCL Low Count Register(I2C_FST_SCL_LCNT)',,,,rw
,,,FST_SCL_LCNT,'Fast SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x0000003C,32.,I2C1_I2C_HS_SCL_HCNT,'High Speed  I2C SCL High Count Register(2C_HS_SCL_HCNT)',,,,rw
,,,HS_SCL_HCNT,'High speed SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000040,32.,I2C1_I2C_HS_SCL_LCNT,'High Speed  I2C SCL Low Count Register(I2C_HS_SCL_LCNT)',,,,rw
,,,HS_SCL_LCNT,'High speed SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000044,32.,I2C1_I2C_RXFIFO_WATER_MARK,'I2C Receive FIFO Water Mark Register(I2C_RXFIFO_WATER_MARK)',,,,rw
,,,RXFIFO_WATER_MARK,'RX FIFO water mark',0.,1.,,rw
,,,RSVD_31_2,'reserve',2.,31.,,rw
,0x00000048,32.,I2C1_I2C_TXFIFO_WATER_MARK,'I2C Transmit FIFO Water Mark Register(I2C_TXFIFO_WATER_MARK)',,,,rw
,,,TXFIFO_WATER_MARK,'TX FIFO water mark',0.,1.,,rw
,,,RSVD_31_2,'reserve',2.,31.,,rw
,0x0000004C,32.,I2C1_I2C_TX_FIFO_CNT,'I2C Transmit FIFO Valid Entry Counter Register(I2C_TX_FIFO_CNT)',,,,rw
,,,TX_FIFO_CNT,'TX FIFO valid entries',0.,2.,,rw
,,,RSVD_31_3,'reserve',3.,31.,,rw
,0x00000050,32.,I2C1_I2C_RX_FIFO_CNT,'I2C Receive FIFO Valid Entry Counter Register(I2C_RX_FIFO_CNT)',,,,rw
,,,RX_FIFO_CNT,'RX FIFO valid entries',0.,2.,,rw
,,,RSVD_31_3,'reserve',3.,31.,,rw
,0x00000054,32.,I2C1_I2C_FSTD_SPKCNT,'I2C Fast and Standard Spike Suppression Limit Register(I2C_FSTD_SPKCNT)',,,,rw
,,,FSTD_SPKLEN,'fast and standard spike counter length',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000058,32.,I2C1_I2C_HS_SPKCNT,'I2C High Speed Spike Suppression Limit Register(I2C_HS_SPKCNT)',,,,rw
,,,HS_SPKLEN,'High speed spike counter',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000005C,32.,I2C1_I2C_STATUS0,'I2C Interrupt Status Register(I2C_STATUS0)',,,,rw
,,,GENERAL_CALL,'general call flag',0.,0.,,rw
,,,TXFIFO_OVERUN,'TXFIFO overrun flag',1.,1.,,rw
,,,ERROR_ABORT,'transfer abort flag',2.,2.,,rw
,,,ACTIVITY,'I2C activity flag',3.,3.,,rw
,,,STOP_DETECT,'stop detect flag',4.,4.,,rw
,,,START_DETECT,'start detect flag',5.,5.,,rw
,,,RSVD_21_6,'reserve',6.,21.,,rw
,,,SLAVE_READ_REQ,'RXFIFO slave read request flag',22.,22.,,rw
,,,RXFIFO_DONE,'RX FIFO done flag',23.,23.,,rw
,,,RXFIFO_UNDERUN,'RXFIFO underun flag',24.,24.,,rw
,,,RXFIFO_OVERUN,'RXFIFO overun flag',25.,25.,,rw
,,,RESTART_DET,'restart detect flag',26.,26.,,rw
,,,SCL_STUCK_AT_LOW,'SCL stuck at low flag',27.,27.,,rw
,,,RSVD_29_28,'reserve',28.,29.,,rw
,,,RXFIFO_FULL,'RXFIFO full flag',30.,30.,,rw
,,,TXFIFO_EMPTY,'TXFIFO empty flag',31.,31.,,rw
,0x00000060,32.,I2C1_I2C_STATUS1,'I2C Status Register(I2C_STATUS1)',,,,rw
,,,MASTER_IS_ACTIVE,'master is active flag',0.,0.,,rw
,,,SLAVE_IS_ACTIVE,'slave is active flag',1.,1.,,rw
,,,TXFIFO_EMPTY_MASTER_HOLD,'master hold bus when TXFIFO empty',2.,2.,,rw
,,,TXFIFO_EMPTY_SLAVE_HOLD,'slave hold bus when TXFIFO empty',3.,3.,,rw
,,,RXFIFO_FULL_MASTER_HOLD,'master RXFIFO hold bus when RXFIFO full',4.,4.,,rw
,,,RXFIFO_FULL_SLAVE_HOLD,'slave RXFIFO hold bus when RXFIFO full',5.,5.,,rw
,,,TXFIO_IS_NOT_FULL,'TXFIFO is not full flag.',6.,6.,,rw
,,,TXFIFO_IS_EMPTY,'TXFIFO is empty flag.',7.,7.,,rw
,,,RXFIFO_IS_NOT_EMPTY,'RXFIFO is not empty flag.',8.,8.,,rw
,,,RXFIO_IS_FULL,'RXFIFO full flag',9.,9.,,rw
,,,SDA_ERR_RECOVER_STUCK_LOW,'SDA error recover from stucking at low flag.',10.,10.,,rw
,,,SLAVE_IS_DISABLED_UNDER_ACT,'slave disabled under active ',11.,11.,,rw
,,,SLAVE_RX_DATA_DISCARD,'slave receive data discard flag.',12.,12.,,rw
,,,I2C_IS_ENABLE,'I2C is enabled flag',13.,13.,,rw
,,,RSVD_31_14,'reserve',14.,31.,,rw
,0x00000064,32.,I2C1_I2C_ERROR_STATUS,'I2C Error Status Register(I2C_ERROR_STATUS)',,,,rw
,,,ERR_GEN_CALL_NO_ACK,'error flag of no ack from general call',0.,0.,,rw
,,,ERR_GEN_CALL_READ,'error flag of reading from general call',1.,1.,,rw
,,,ERR_START_BYTE_ACK_DET,'error flag of ack from start byte',2.,2.,,rw
,,,ERR_SBYTE_NORSTRT,'error flag of sending start byte under restart_en=0',3.,3.,,rw
,,,ERR_H_NO_RSTRT,'error flag of high speed under restart_en=0',4.,4.,,rw
,,,ERR_H_MCODE_ACK_DET,'error flag of high speed master code ack',5.,5.,,rw
,,,ERR_7BIT_ADDR_NO_ACK,'error flag of 7bit address no ack',6.,6.,,rw
,,,ERR_10BIT_ADDR1_NO_ACK,'error flag of 10bit first address no ack ',7.,7.,,rw
,,,ERR_10BIT_ADDR2_NO_ACK,'error flag of 10bit second address no ack ',8.,8.,,rw
,,,ERR_10BIT_READ_NO_RSTRT,'error flag of 10bit read under restart_en=0',9.,9.,,rw
,,,ERR_DATA_NO_ACK,'error flag of master data no_ack',10.,10.,,rw
,,,ERR_MASTER_ABRT,'error flag of master abort',11.,11.,,rw
,,,ERR_MASTER_DIS,'error flag of master disable',12.,12.,,rw
,,,ERR_SLAVE_ARBLOST,'error flag of slave lost',13.,13.,,rw
,,,ERR_MASTER_LOST,'error flag of master lost',14.,14.,,rw
,,,ERR_SLAVE_READ_REQ,'error flag of slave read request',15.,15.,,rw
,,,ERR_SLAVE_FLUSH_TXFIFO,'error flag of slave flush TXFIFO',16.,16.,,rw
,,,ERR_SDA_LOW_TIMEOUT,'error flag of SDA stuck low timeout',17.,17.,,rw
,,,ERR_TXFIFO_FLUSH_CNT,'error counter of TXFIFO flush',18.,20.,,rw
,,,RSVD_31_21,'reserve',21.,31.,,rw
,0x00000068,32.,I2C1_I2C_SCL_LOW_TIMEOUT,'I2C SCL Stuck at Low Timeout Register(I2C_SCL_LOW_TIMEOUT)',,,,rw
,,,SCL_LOW_TIMEOUT,'SCL stuck at low timeout',0.,31.,,rw
,0x0000006C,32.,I2C1_I2C_SDA_LOW_TIMEOUT,'I2C SDA Stuck at Low Timeout Register(I2C_SDA_LOW_TIMEOUT)',,,,rw
,,,SDA_LOW_TIMEOUT,'SDA stuck at low timeout',0.,31.,,rw
,0x00000070,32.,I2C1_I2C_RD_CLR_ERR_STATUS,'I2C Read Clear Error Status Register(I2C_RD_CLR_ERR_STATUS)',,,,rw
,,,CLR_ERR,'read clear I2C_ERROR_STATUS flags.',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
tree.end
base ad:0x40061000
tree "EWDT"
tree.end
base ad:0x40063000
tree "TMU"
,0x00000000,32.,TMU_CFGn,'Trig Mux Unit Configuration(TMU_CFG)',,,,rw
,,,SEL,'Mux Input Select',0.,15.,,rw
,,,EN,'Mux Output Enable',16.,16.,,rw
,,,RSVD_30_17,'Reserved',17.,30.,,rw
,,,LOCK,'Write register lock',31.,31.,,rw
tree.end
base ad:0x40064000
tree "SCC"
,0x00000000,32.,SCC_VERID,'System Clock Control Version Idenfication(SCC_VERID)',,,,rd
,,,RSVD_7_0,'Reserved',0.,7.,,rd
,,,MINOR,'Minor version',8.,15.,,rd
,,,MAJOR,'Major version',16.,23.,,rd
,,,RSVD_31_24,'Reserved',24.,31.,,rd
,0x00000004,32.,SCC_PARAM,'System Clock Control Parameter(SCC_PARAM)',,,,rd
,,,CLKSPRES,'Clock Source Present',0.,4.,,rd
,,,RSVD_27_5,'Reserved',5.,27.,,rd
,,,DIVPRES,'Divider Present',28.,30.,,rd
,,,RSVD_31,'Reserved',31.,31.,,rd
,0x00000008,32.,SCC_CST,'System Clock Control Clock Status Registers(SCC_CST)',,,,rd
,,,DIVSLOW,'Slow Clock Divide Ratio',0.,3.,,rd
,,,DIVBUS,'Bus Clock Divide Ratio',4.,7.,,rd
,,,DIVCORE,'Core Clock Divide Ratio',8.,11.,,rd
,,,RSVD_15_12,'Reserved',12.,15.,,rd
,,,SCS,'System Clock Source',16.,18.,,rd
,,,RSVD_31_19,'Reserved',19.,31.,,rd
,0x0000000C,32.,SCC_CFG,'System Clock Control Clock Configuration Registers(SCC_CFG)',,,,rw
,,,DIVSLOW,'Slow Clock Divide Ratio',0.,3.,,rw
,,,DIVBUS,'Bus Clock Divide Ratio',4.,7.,,rw
,,,DIVCORE,'Core Clock Divide Ratio',8.,11.,,rw
,,,RSVD_15_12,'Reserved',12.,15.,,rw
,,,SCS,'System Clock Source',16.,18.,,rw
,,,RSVD_30_19,'Reserved',19.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000010,32.,SCC_CLKOUTCFG,'System Clock Control Clock Out Configuration Registers(SCC_CLKOUTCFG)',,,,rw
,,,RSVD_15_0,'Reserved',0.,15.,,rw
,,,CLKOUTSEL,'SCC CLKOUT Configuration',16.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000014,32.,SCC_OSCCS,'System Clock Control OSC Control Status Registers(SCC_OSCCS)',,,,rw
,,,OSCEN,'OSC Enable',0.,0.,,rw
,,,OSCSTOPEN,'OSC Stop Mode Enable',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,OSCLOCINTEN,'OSC loss of clock interrupt enable',4.,4.,,rw
,,,RSVD_8_5,'Reserved',5.,8.,,rw
,,,OSCCME,'OSC Clock Monitor Enable',9.,9.,,rw
,,,OSCCMRE,'OSC Clock Monitor Reset Enabled',10.,10.,,rw
,,,RSVD_15_11,'Reserved',11.,15.,,rw
,,,OSCRDY,'OSC is ready for use',16.,16.,,rw
,,,OSCSELD,'OSC is selected as system clock source ',17.,17.,,rw
,,,OSCLOC,'OSC Loss Of Clock',18.,18.,,rw
,,,RSVD_30_19,'Reserved',19.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000018,32.,SCC_OSCCFG,'System Clock Control OSC Configuration Register(SCC_OSCCFG)',,,,rw
,,,EXCLKS,'OSC External Clock Select',0.,0.,,rw
,,,OLMEN,'Open Loop Mode',1.,1.,,rw
,,,HFREQ,'High Frequency Mode',2.,2.,,rw
,,,RSVD_7_3,'Reserved',3.,7.,,rw
,,,ITRIM,'Current Trim',8.,9.,,rw
,,,RSVD_30_10,'Reserved',10.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x0000001C,32.,SCC_FIRCCS,'System Clock Control FIRC Control Status Registers(SCC_FIRCCS)',,,,rw
,,,FIRCEN,'FIRC Enable',0.,0.,,rw
,,,FIRCSTOPEN,'FIRC Stop Mode Enable',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FIRCLOCINTEN,'FIRC loss of clock interrupt enable',4.,4.,,rw
,,,RSVD_8_5,'Reserved',5.,8.,,rw
,,,FIRCCME,'FIRC Clock Monitor Enable',9.,9.,,rw
,,,FIRCCMRE,'FIRC Clock Monitor Reset Enabled',10.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,FIRCTRIMEN,'Enable FIRC64M trim update',12.,12.,,rw
,,,RSVD_15_13,'Reserved',13.,15.,,rw
,,,FIRCRDY,'FIRC64M is ready for use',16.,16.,,rw
,,,FIRCSELD,'FIRC64M is selected as system clock source ',17.,17.,,rw
,,,FIRCLOC,'FIRC Loss Of Clock',18.,18.,,rw
,,,RSVD_30_19,'Reserved',19.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000020,32.,SCC_FIRCCFG,'System Clock Control FIRC Configuration Register(SCC_FIRCCFG)',,,,rw
,,,FREQMS,'Frequency Mode Select',0.,1.,,rw
,,,RSVD_30_2,'Reserved',2.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000024,32.,SCC_FIRCTRIM,'System Clock Control FIRC Trim Register(SCC_FIRCTRIM)',,,,rw
,,,TRIM,'FRIC64M Trim',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x00000028,32.,SCC_SPLLCS,'System Clock Control SPLL Control Status Registers(SCC_SPLLCS)',,,,rw
,,,SPLLEN,'SPLL Enable',0.,0.,,rw
,,,SPLLSTOPEN,'SPLL Stop Mode Enable',1.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,LOLINTEN,'Loss of lock interrupt request enable',4.,4.,,rw
,,,RSVD_8_5,'Reserved',5.,8.,,rw
,,,LOLDEN,'Loss of lock detector enable',9.,9.,,rw
,,,LOLRESTEN,'Loss of lock reset enable',10.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,LOCKWIN,'SPLL phase lock window',12.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,SPLLRDY,'SPLL is ready for use',16.,16.,,rw
,,,SPLLSELD,'SPLL is selected as system clock source ',17.,17.,,rw
,,,LOL,'SPLL Loss Of Lock',18.,18.,,rw
,,,RSVD_30_19,'Reserved',19.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x0000002C,32.,SCC_SPLLCFG1,'System Clock Control SPLL Configuration Register 1(SCC_SPLLCFG1)',,,,rw
,,,PREDIV,'Pre-divider',0.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,FBPRESEN,'Feedback pre-scaler enable',4.,4.,,rw
,,,REFCKS,'Reference clock select',5.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,MULT,'SPLL multiplier',8.,15.,,rw
,,,POSTDIV,'Post divider',16.,18.,,rw
,,,RSVD_30_19,'Reserved',19.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000030,32.,SCC_SPLLCFG2,'System Clock Control SPLL Configuration Register 2(SCC_SPLLCFG2)',,,,rw
,,,CPIR,'charge pump proportional path current setting',0.,1.,,rw
,,,CPIC,'charge pump integral path current setting',2.,3.,,rw
,,,CS,'LPF cap 2nd pole setting',4.,5.,,rw
,,,CAP,'LPF cap setting',6.,7.,,rw
,,,RES,'LPF resistor setting',8.,10.,,rw
,,,KVCO,'kvco gain setting',11.,11.,,rw
,,,VCODIV,'pll VCO /2 option',12.,12.,,rw
,,,PFDDIEN,'dither enable',13.,13.,,rw
,,,CPISEL,'pll cp bias option',14.,14.,,rw
,,,RSVD_15,'Reserved',15.,15.,,rw
,,,RSVD_23_16,'Reserved',16.,23.,,rw
,,,LDOODEN,'LDO over drive enable',24.,24.,,rw
,,,RSVD_30_25,'Reserved',25.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
,0x00000034,32.,SCC_SPLLTEST,'System Clock Control SPLL Test Register 2(SCC_SPLLTEST)',,,,rw
,,,CKTSTEN,'pll clock test enable',0.,0.,,rw
,,,CKTSTMUX,'pll clock test mux slection',1.,2.,,rw
,,,RSVD_7_3,'Reserved',3.,7.,,rw
,,,VTSTEN,'pll voltage test enable',8.,8.,,rw
,,,VTSTMUX,'pll voltage test mux slection',9.,10.,,rw
,,,RSVD_30_11,'Reserved',11.,30.,,rw
,,,LOCK,'Lock register access',31.,31.,,rw
tree.end
base ad:0x40065000
tree "PARCC"
,0x00000000,32.,PARCC_x,'Peripheral Access&Reset&Clock Control (PARCC_x)',,,,rd
,,,PCKMD,'Peripheral Clock Mode',0.,1.,,rd
,,,RSVD_3_2,'Reserved',2.,3.,,rd
,,,CLKMUX,'Peripheral funcional clock source mux',4.,6.,,rd
,,,RSVD_7,'Reserved',7.,7.,,rd
,,,CLKDIV,'Peripheral funcional clock divider',8.,11.,,rd
,,,RSVD_15_12,'Reserved',12.,15.,,rd
,,,PWLK,'Peripheral write lock ',16.,16.,,rd
,,,RSVD_19_17,'Reserved',17.,19.,,rd
,,,PSUPVACEN,'Peripheral supervisor access control enable ',20.,20.,,rd
,,,PRSTB,'Peripheral reset_b',21.,21.,,rd
,,,RSVD_23_22,'Reserved',22.,23.,,rd
,,,PPR,'Peripheral present',24.,24.,,rd
,,,PCLKMUXPR,'Peripheral clock mux present',25.,25.,,rd
,,,PCLKDIVPR,'Peripheral clock divider present',26.,26.,,rd
,,,PSUPVACPR,'Peripheral supervisor access control present',27.,27.,,rd
,,,RSVD_30_28,'Reserved',28.,30.,,rd
,,,LOCK,'Write register lock',31.,31.,,rd
tree.end
base ad:0x40066000
tree "I2C0"
,0x00000000,32.,I2C0_I2C_VERID,'I2C Version ID(I2C_VERID)',,,,rw
,,,VERID,'version ID',0.,31.,,rw
,0x00000004,32.,I2C0_I2C_PARAMETER,'I2C Parameter Register(I2C_PARAMETER)',,,,rw
,,,I2C_SUPPORT_SPEED,'I2C transfer speed  supported',0.,1.,,rw
,,,DMA_SUPPORT,'DMA support bit',2.,2.,,rw
,,,TXFIFO_DEPTH,'TX FIFO depth',3.,6.,,rw
,,,RXFIFO_DEPTH,'RX FIFO depth',7.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000008,32.,I2C0_I2C_CONFIG0,'I2C Configure0  Register(I2C_CONFIG0)',,,,rw
,,,MODULE_EN,'module enable bit',0.,0.,,rw
,,,SLAVE_ACK_GENCALL,'slave general call ack',1.,1.,,rw
,,,SLAVE_NACK,'slave nack bit',2.,2.,,rw
,,,SDA_RECOVER_EN,'SDA recover feature enable ',3.,3.,,rw
,,,MASTER_ABORT,'master abort transfer bit',4.,4.,,rw
,,,MASTER_BUS_RECOVER_EN,'enable I2C master bus recover feature',5.,5.,,rw
,,,MASTER_BLK_TXFIFO,'block master TX FIFO transfer',6.,6.,,rw
,,,H_MCODE,'high speed master code',7.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000000C,32.,I2C0_I2C_CONFIG1,'I2C Configure1 Register(I2C_CONFIG1)',,,,rw
,,,SLAVE_MODE_DIS,'slave mode disable',0.,0.,,rw
,,,MASTER_MODE_EN,'master mode enable',1.,1.,,rw
,,,MASTER_RESTART_EN,'enable restart feature during master mode',2.,2.,,rw
,,,SLAVE_STOP_DET_EN,'stop detect feature enable during slave mode',3.,3.,,rw
,,,MASTER_STOP_DET_EN,'stop detect feature enable during master mode',4.,4.,,rw
,,,TXFIFO_EMPTY_EN,'allow generate TXFIFO empty flag.',5.,5.,,rw
,,,SPEED_SEL,'I2C speed select',6.,7.,,rw
,,,HOLD_EN_RXFIFO_FULL,'hold I2C bus feature enable when RXFIFO is full.',8.,8.,,rw
,,,SLAVE_10BIT_ADDR_SEL,'slave 10bit address mode select',9.,9.,,rw
,,,MASTER_10BIT_ADDR_SEL,'master 10bit address mode select',10.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000010,32.,I2C0_I2C_SDA_SETUP_TIMING,'I2C SDA Setup Timing Register(I2C_SDA_SETUP_TIMING)',,,,rw
,,,SDA_SETUP_TIMING,'SDA setup timing value',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000014,32.,I2C0_I2C_SDA_HOLD_TIMING,'I2C SDA Hold Timing Register(I2C_SDA_HOLD_TIMING)',,,,rw
,,,SDA_TX_HOLD_TIMING,'SDA TX hold timing value',0.,15.,,rw
,,,SDA_RX_HOLD_TIMING,'SDA RX hold timing value',16.,23.,,rw
,,,RSVD_31_24,'reserve',24.,31.,,rw
,0x00000018,32.,I2C0_I2C_DMA_CTRL,'I2C DMA Control Register(I2C_DMA_CTRL)',,,,rw
,,,RXFIFO_DMA_EN,'RXFIFO DMA enable',0.,0.,,rw
,,,TXFIFO_DMA_EN,'TXFIFO DMA enable',1.,1.,,rw
,,,DMA_TXFIFO_WATERMARK,'DMA TXFIFO watermark',2.,3.,,rw
,,,DMA_RXFIFO_WATERMARK,'DMA RXFIFO watermark ',4.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x0000001C,32.,I2C0_I2C_INT_ENABLE,'I2C Interrupt Enable Register(I2C_INT_ENABLE)',,,,rw
,,,I2C_CALL_IE,'I2C general call interrupt enable',0.,0.,,rw
,,,I2C_TX_OVF_IE,'I2C TX overun interrupt enable',1.,1.,,rw
,,,I2C_ERROR_ABORT_IE,'I2C Error abort interrupt enable',2.,2.,,rw
,,,I2C_ACTIVITY_DET_IE,'I2C activity detect interrupt enable',3.,3.,,rw
,,,I2C_STOP_DET_IE,'I2C stop detect interrupt enable',4.,4.,,rw
,,,I2C_START_DET_IE,'I2C start detect interrupt enable',5.,5.,,rw
,,,RSVD_21_6,'reserve',6.,21.,,rw
,,,SLAVE_RD_REQ_IE,'slave read request interrupt enable',22.,22.,,rw
,,,RX_DONE_IE,'RX done interrupt enable',23.,23.,,rw
,,,RX_UNDER_IE,'RX under interrupt enable',24.,24.,,rw
,,,RX_OVF_IE,'RX overun interrupt enable',25.,25.,,rw
,,,RESTART_DET_IE,'restart detect interrupt enable',26.,26.,,rw
,,,SCL_STUCK_AT_LOW_IE,'SCL stuck at low interrupt enable',27.,27.,,rw
,,,RSVD_29_28,'reserve',28.,29.,,rw
,,,RX_FULL_IE,'RXFIFO interrupt enable',30.,30.,,rw
,,,TX_EMPTY_IE,'TXFIFO interrupt enable',31.,31.,,rw
,0x00000020,32.,I2C0_I2C_COMMAND_DATA,'I2C Rx/Tx Data Buffer and Command Register(I2C_COMMAND_DATA)',,,,rw
,,,DATA,'data',0.,7.,,rw
,,,CMD_MASTER_DIRECTION,'command direction',8.,8.,,rw
,,,CMD_STOP,'command stop',9.,9.,,rw
,,,CMD_RESTART,'command restart',10.,10.,,rw
,,,RSVD_31_11,'reserve',11.,31.,,rw
,0x00000024,32.,I2C0_I2C_DEST_ADDR,'I2C Target Address Register(I2C_DEST_ADDR)',,,,rw
,,,DEST_ADDR,'destination addresss',0.,9.,,rw
,,,MASTER_CMD_SEL,'master command select',10.,11.,,rw
,,,RSVD_31_12,'reserve',12.,31.,,rw
,0x00000028,32.,I2C0_I2C_SLAVE_ADDR,'I2C Slave Address Register(I2C_SLAVE_ADDR)',,,,rw
,,,SLV_ADDR,'slave address',0.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x0000002C,32.,I2C0_I2C_STD_SCL_HCNT,' Standard Speed I2C SCL High Count register(I2C_STD_SCL_HCNT)',,,,rw
,,,STD_SCL_HCNT,'standard SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000030,32.,I2C0_I2C_STD_SCL_LCNT,' Standard Speed  I2C SCL Low Count Register(I2C_STD_SCL_LCNT)',,,,rw
,,,STD_SCL_LCNT,'standard SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000034,32.,I2C0_I2C_FST_SCL_HCNT,'Fast Mode I2C SCL High Count Register(I2C_FST_SCL_HCNT)',,,,rw
,,,FST_SCL_HCNT,'Fast SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000038,32.,I2C0_I2C_FST_SCL_LCNT,'Fast Mode  I2C SCL Low Count Register(I2C_FST_SCL_LCNT)',,,,rw
,,,FST_SCL_LCNT,'Fast SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x0000003C,32.,I2C0_I2C_HS_SCL_HCNT,'High Speed  I2C SCL High Count Register(2C_HS_SCL_HCNT)',,,,rw
,,,HS_SCL_HCNT,'High speed SCL high counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000040,32.,I2C0_I2C_HS_SCL_LCNT,'High Speed  I2C SCL Low Count Register(I2C_HS_SCL_LCNT)',,,,rw
,,,HS_SCL_LCNT,'High speed SCL low counter value',0.,15.,,rw
,,,RSVD_31_16,'reserve',16.,31.,,rw
,0x00000044,32.,I2C0_I2C_RXFIFO_WATER_MARK,'I2C Receive FIFO Water Mark Register(I2C_RXFIFO_WATER_MARK)',,,,rw
,,,RXFIFO_WATER_MARK,'RX FIFO water mark',0.,1.,,rw
,,,RSVD_31_2,'reserve',2.,31.,,rw
,0x00000048,32.,I2C0_I2C_TXFIFO_WATER_MARK,'I2C Transmit FIFO Water Mark Register(I2C_TXFIFO_WATER_MARK)',,,,rw
,,,TXFIFO_WATER_MARK,'TX FIFO water mark',0.,1.,,rw
,,,RSVD_31_2,'reserve',2.,31.,,rw
,0x0000004C,32.,I2C0_I2C_TX_FIFO_CNT,'I2C Transmit FIFO Valid Entry Counter Register(I2C_TX_FIFO_CNT)',,,,rw
,,,TX_FIFO_CNT,'TX FIFO valid entries',0.,2.,,rw
,,,RSVD_31_3,'reserve',3.,31.,,rw
,0x00000050,32.,I2C0_I2C_RX_FIFO_CNT,'I2C Receive FIFO Valid Entry Counter Register(I2C_RX_FIFO_CNT)',,,,rw
,,,RX_FIFO_CNT,'RX FIFO valid entries',0.,2.,,rw
,,,RSVD_31_3,'reserve',3.,31.,,rw
,0x00000054,32.,I2C0_I2C_FSTD_SPKCNT,'I2C Fast and Standard Spike Suppression Limit Register(I2C_FSTD_SPKCNT)',,,,rw
,,,FSTD_SPKLEN,'fast and standard spike counter length',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x00000058,32.,I2C0_I2C_HS_SPKCNT,'I2C High Speed Spike Suppression Limit Register(I2C_HS_SPKCNT)',,,,rw
,,,HS_SPKLEN,'High speed spike counter',0.,7.,,rw
,,,RSVD_31_8,'reserve',8.,31.,,rw
,0x0000005C,32.,I2C0_I2C_STATUS0,'I2C Interrupt Status Register(I2C_STATUS0)',,,,rw
,,,GENERAL_CALL,'general call flag',0.,0.,,rw
,,,TXFIFO_OVERUN,'TXFIFO overrun flag',1.,1.,,rw
,,,ERROR_ABORT,'transfer abort flag',2.,2.,,rw
,,,ACTIVITY,'I2C activity flag',3.,3.,,rw
,,,STOP_DETECT,'stop detect flag',4.,4.,,rw
,,,START_DETECT,'start detect flag',5.,5.,,rw
,,,RSVD_21_6,'reserve',6.,21.,,rw
,,,SLAVE_READ_REQ,'RXFIFO slave read request flag',22.,22.,,rw
,,,RXFIFO_DONE,'RX FIFO done flag',23.,23.,,rw
,,,RXFIFO_UNDERUN,'RXFIFO underun flag',24.,24.,,rw
,,,RXFIFO_OVERUN,'RXFIFO overun flag',25.,25.,,rw
,,,RESTART_DET,'restart detect flag',26.,26.,,rw
,,,SCL_STUCK_AT_LOW,'SCL stuck at low flag',27.,27.,,rw
,,,RSVD_29_28,'reserve',28.,29.,,rw
,,,RXFIFO_FULL,'RXFIFO full flag',30.,30.,,rw
,,,TXFIFO_EMPTY,'TXFIFO empty flag',31.,31.,,rw
,0x00000060,32.,I2C0_I2C_STATUS1,'I2C Status Register(I2C_STATUS1)',,,,rw
,,,MASTER_IS_ACTIVE,'master is active flag',0.,0.,,rw
,,,SLAVE_IS_ACTIVE,'slave is active flag',1.,1.,,rw
,,,TXFIFO_EMPTY_MASTER_HOLD,'master hold bus when TXFIFO empty',2.,2.,,rw
,,,TXFIFO_EMPTY_SLAVE_HOLD,'slave hold bus when TXFIFO empty',3.,3.,,rw
,,,RXFIFO_FULL_MASTER_HOLD,'master RXFIFO hold bus when RXFIFO full',4.,4.,,rw
,,,RXFIFO_FULL_SLAVE_HOLD,'slave RXFIFO hold bus when RXFIFO full',5.,5.,,rw
,,,TXFIO_IS_NOT_FULL,'TXFIFO is not full flag.',6.,6.,,rw
,,,TXFIFO_IS_EMPTY,'TXFIFO is empty flag.',7.,7.,,rw
,,,RXFIFO_IS_NOT_EMPTY,'RXFIFO is not empty flag.',8.,8.,,rw
,,,RXFIO_IS_FULL,'RXFIFO full flag',9.,9.,,rw
,,,SDA_ERR_RECOVER_STUCK_LOW,'SDA error recover from stucking at low flag.',10.,10.,,rw
,,,SLAVE_IS_DISABLED_UNDER_ACT,'slave disabled under active ',11.,11.,,rw
,,,SLAVE_RX_DATA_DISCARD,'slave receive data discard flag.',12.,12.,,rw
,,,I2C_IS_ENABLE,'I2C is enabled flag',13.,13.,,rw
,,,RSVD_31_14,'reserve',14.,31.,,rw
,0x00000064,32.,I2C0_I2C_ERROR_STATUS,'I2C Error Status Register(I2C_ERROR_STATUS)',,,,rw
,,,ERR_GEN_CALL_NO_ACK,'error flag of no ack from general call',0.,0.,,rw
,,,ERR_GEN_CALL_READ,'error flag of reading from general call',1.,1.,,rw
,,,ERR_START_BYTE_ACK_DET,'error flag of ack from start byte',2.,2.,,rw
,,,ERR_SBYTE_NORSTRT,'error flag of sending start byte under restart_en=0',3.,3.,,rw
,,,ERR_H_NO_RSTRT,'error flag of high speed under restart_en=0',4.,4.,,rw
,,,ERR_H_MCODE_ACK_DET,'error flag of high speed master code ack',5.,5.,,rw
,,,ERR_7BIT_ADDR_NO_ACK,'error flag of 7bit address no ack',6.,6.,,rw
,,,ERR_10BIT_ADDR1_NO_ACK,'error flag of 10bit first address no ack ',7.,7.,,rw
,,,ERR_10BIT_ADDR2_NO_ACK,'error flag of 10bit second address no ack ',8.,8.,,rw
,,,ERR_10BIT_READ_NO_RSTRT,'error flag of 10bit read under restart_en=0',9.,9.,,rw
,,,ERR_DATA_NO_ACK,'error flag of master data no_ack',10.,10.,,rw
,,,ERR_MASTER_ABRT,'error flag of master abort',11.,11.,,rw
,,,ERR_MASTER_DIS,'error flag of master disable',12.,12.,,rw
,,,ERR_SLAVE_ARBLOST,'error flag of slave lost',13.,13.,,rw
,,,ERR_MASTER_LOST,'error flag of master lost',14.,14.,,rw
,,,ERR_SLAVE_READ_REQ,'error flag of slave read request',15.,15.,,rw
,,,ERR_SLAVE_FLUSH_TXFIFO,'error flag of slave flush TXFIFO',16.,16.,,rw
,,,ERR_SDA_LOW_TIMEOUT,'error flag of SDA stuck low timeout',17.,17.,,rw
,,,ERR_TXFIFO_FLUSH_CNT,'error counter of TXFIFO flush',18.,20.,,rw
,,,RSVD_31_21,'reserve',21.,31.,,rw
,0x00000068,32.,I2C0_I2C_SCL_LOW_TIMEOUT,'I2C SCL Stuck at Low Timeout Register(I2C_SCL_LOW_TIMEOUT)',,,,rw
,,,SCL_LOW_TIMEOUT,'SCL stuck at low timeout',0.,31.,,rw
,0x0000006C,32.,I2C0_I2C_SDA_LOW_TIMEOUT,'I2C SDA Stuck at Low Timeout Register(I2C_SDA_LOW_TIMEOUT)',,,,rw
,,,SDA_LOW_TIMEOUT,'SDA stuck at low timeout',0.,31.,,rw
,0x00000070,32.,I2C0_I2C_RD_CLR_ERR_STATUS,'I2C Read Clear Error Status Register(I2C_RD_CLR_ERR_STATUS)',,,,rw
,,,CLR_ERR,'read clear I2C_ERROR_STATUS flags.',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
tree.end
base ad:0x4006A000
tree "UART0"
,0x00000000,32.,UART0_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART0_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART0_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART0_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART0_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART0_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART0_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART0_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART0_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART0_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART0_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART0_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART0_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART0_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART0_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART0_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART0_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART0_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART0_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART0_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART0_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART0_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART0_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART0_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART0_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART0_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART0_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART0_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x4006B000
tree "UART1"
,0x00000000,32.,UART1_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART1_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART1_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART1_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART1_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART1_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART1_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART1_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART1_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART1_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART1_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART1_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART1_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART1_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART1_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART1_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART1_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART1_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART1_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART1_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART1_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART1_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART1_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART1_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART1_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART1_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART1_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART1_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x4006C000
tree "UART2"
,0x00000000,32.,UART2_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART2_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART2_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART2_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART2_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART2_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART2_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART2_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART2_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART2_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART2_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART2_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART2_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART2_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART2_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART2_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART2_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART2_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART2_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART2_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART2_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART2_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART2_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART2_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART2_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART2_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART2_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART2_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x40070000
tree "UART3"
,0x00000000,32.,UART3_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART3_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART3_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART3_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART3_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART3_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART3_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART3_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART3_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART3_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART3_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART3_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART3_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART3_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART3_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART3_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART3_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART3_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART3_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART3_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART3_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART3_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART3_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART3_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART3_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART3_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART3_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART3_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x40071000
tree "UART4"
,0x00000000,32.,UART4_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART4_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART4_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART4_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART4_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART4_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART4_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART4_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART4_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART4_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART4_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART4_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART4_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART4_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART4_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART4_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART4_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART4_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART4_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART4_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART4_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART4_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART4_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART4_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART4_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART4_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART4_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART4_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x40072000
tree "UART5"
,0x00000000,32.,UART5_UART_RBR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,RBR_LSB,'low 8bits of rbr',0.,7.,,rd
,,,RBR_MSB,' 9th bit of rbr',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART5_UART_THR,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,THR_LSB,'low 8bits of thr',0.,7.,,rd
,,,THR_MSB,'the 9bit of Data to be transmitted',8.,8.,,rd
,,,RSVD_31_9,'Reserved',9.,31.,,rd
,0x00000000,32.,UART5_UART_DLL,'Receive Buffer Register(LIN_RBR)',,,,rd
,,,DL_L,'low 8bits of divisor register ',0.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000004,32.,UART5_UART_DLH,'Divisor Latch High(LIN_DLH)',,,,rw
,,,DL_H,'high 8 bits of divisor register ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000004,32.,UART5_UART_IER,'Divisor Latch High(LIN_DLH)',,,,rw
,,,ERBFI,'Enable Received Data Available Interrupt',0.,0.,,rw
,,,ETBEI,'Enable Transmit Holding Register Empty Interrupt',1.,1.,,rw
,,,ELSI,'Enable Receiver Line Status Interrupt.',2.,2.,,rw
,,,EDSSI,'Enable Modem Status Interrupt',3.,3.,,rw
,,,RSVD_6_4,'Reserved',4.,6.,,rw
,,,PTIME,'Programmable THRE Interrupt Mode Enable',7.,7.,,rw
,,,HEADER_DONE_INT_EN,'header operation done interrupt enable',8.,8.,,rw
,,,RSP_DONE_INT_EN,'response operation done interrupt enable ',9.,9.,,rw
,,,ASYNC_INT_EN,'Async interrupt enable',10.,10.,,rw
,,,RSVD_31_11,'Reserved',11.,31.,,rw
,0x00000008,32.,UART5_UART_IIR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,IID,'Interrupt ID',0.,3.,,rd
,,,RSVD_5_4,'Reserved',4.,5.,,rd
,,,FIFOSE,'FIFOs Enabled',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x00000008,32.,UART5_UART_FCR,'Interrupt Identity Register(LIN_IIR)',,,,rd
,,,FIFOE,'FIFO Enable',0.,0.,,rd
,,,RFIFOR,'RCVR FIFO Reset',1.,1.,,rd
,,,XFIFOR,'XMIT FIFO Reset',2.,2.,,rd
,,,DMAM,'DMA Mode',3.,3.,,rd
,,,TET,'transmit empty threshold ',4.,5.,,rd
,,,RCVR,'receiver interrupt trigger',6.,7.,,rd
,,,RSVD_31_8,'Reserved',8.,31.,,rd
,0x0000000C,32.,UART5_UART_LCR,'LIN Control Register(LIN_LCR)',,,,rw
,,,DLS,'Data Length Select',0.,1.,,rw
,,,STOP,'Number of stop bits.',2.,2.,,rw
,,,PEN,'Parity Enable.',3.,3.,,rw
,,,EPS,'Even Parity Select',4.,4.,,rw
,,,STP,'Stick Parity',5.,5.,,rw
,,,BC,'Break Control Bit',6.,6.,,rw
,,,DLAB,'Divisor Latch Access Bit',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LBKM,'the length of break in LIN mode',9.,13.,,rw
,,,IDLE_DET_LENGTH,'idle detect lendth',14.,16.,,rw
,,,IDLE_DET_EN,'idle detect enable',17.,17.,,rw
,,,AUTO_SYNC_EN,'LIN baudrate auto sync enable',18.,18.,,rw
,,,DEBUG_EN,'debug enable',19.,19.,,rw
,,,RSVD_31_20,'Reserved',20.,31.,,rw
,0x00000010,32.,UART5_UART_AFCR,'Autoflow Control Register(LIN_AFCR)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,RTS,'Request to Send',1.,1.,,rw
,,,RSVD_2,'Reserved',2.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,LB,'LoopBack Bit',4.,4.,,rw
,,,AFCE,' Auto Flow Control Enable',5.,5.,,rw
,,,SIRE,'SIR Mode Enable',6.,6.,,rw
,,,RSVD_31_7,'Reserved',7.,31.,,rw
,0x00000014,32.,UART5_UART_LSR,'Line Status Register(LIN_LSR)',,,,rd
,,,DR,'Data Ready bit',0.,0.,,rd
,,,OE,'Overrun error bit',1.,1.,,rd
,,,PE,' Parity Error bit.',2.,2.,,rd
,,,FE,'Framing Error bit.',3.,3.,,rd
,,,BI,'Break Interrupt bit',4.,4.,,rd
,,,THRE,'Transmit Holding Register Empty bit',5.,5.,,rd
,,,TEMT,' Transmitter Empty bit.',6.,6.,,rd
,,,RFE,'Receiver FIFO Error bit',7.,7.,,rd
,,,ADDR_RCVD,'Address Received bit ',8.,8.,,rd
,,,ASYNC_INT,'Async interrupt flag ',9.,9.,,rd
,,,SYNC_FIELD_ERROR,'sync field error ',10.,10.,,rd
,,,PID_ERR,'PID error ',11.,11.,,rd
,,,CHECKSUM_ERROR,'checksum error flag ',12.,12.,,rd
,,,TO_ERROR,'timeout error',13.,13.,,rd
,,,HEADER_OP_DONE,'header operation done flag ',14.,14.,,rd
,,,RSP_OP_DONE,'response operation done flag',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x00000018,32.,UART5_UART_MSR,'Modem Status Register(LIN_MSR)',,,,rd
,,,RSVD_3_0,'Reserved',0.,3.,,rd
,,,CTS,'clear to send ',4.,4.,,rd
,,,RSVD_31_5,'Reserved',5.,31.,,rd
,0x0000007C,32.,UART5_UART_USR,'UART Status Register(LIN_USR)',,,,rd
,,,BUSY,'UART Busy.',0.,0.,,rd
,,,RSVD_31_1,'Reserved',1.,31.,,rd
,0x000000A8,32.,UART5_UART_DMA_SA,'DMA Software Acknowledge(LIN_DMA_SA)',,,,wr
,,,DMA_SA,'Reserved',0.,0.,,wr
,,,RSVD_31_1,'Reserved',1.,31.,,wr
,0x000000C0,32.,UART5_UART_FD,'fraction divisor register(LIN_FD)',,,,rw
,,,FD,'Fractional divisor.',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x000000C4,32.,UART5_UART_RAR,'Receive Address Register (LIN_RAR)',,,,rw
,,,RAR,'address matching ',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000C8,32.,UART5_UART_TAR,'Transmit Address Register(LIN_TAR)',,,,rw
,,,TAR,'address matching register during transmit mode',0.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x000000CC,32.,UART5_UART_LCR_EXT,'Line Extended Control Register(LIN_LCR_EXT)',,,,rw
,,,DLS_E,'Extension for DLS',0.,0.,,rw
,,,ADDR_MATCH,'Address Match Mode. ',1.,1.,,rw
,,,SEND_ADDR,'Send address control bit',2.,2.,,rw
,,,TRANSMIST_MODE,'Transmit mode control bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000100,32.,UART5_LIN_CTL,'LIN mode control register(LIN_CTL)',,,,rw
,,,LIN_MODE,'LIN mode enable',0.,0.,,rw
,,,MASTER_MODE,'master mode.',1.,1.,,rw
,,,HEADER_OP_START,'header operation start trigger',2.,2.,,rw
,,,RSP_OP_START,'response operation start trigger',3.,3.,,rw
,,,RSP_DIR,'response operation direction',4.,4.,,rw
,,,RSVD_31_5,'Reserved',5.,31.,,rw
,0x00000104,32.,UART5_UART_LIN_RSP_LENGTH,'LIN response length register(LIN_RSP_LENGTH)',,,,rw
,,,RSP_LENGTH,'LIN response length register',0.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x00000108,32.,UART5_UART_LIN_PID_VALUE,'LIN PID register(LIN_PID_VALUE)',,,,rw
,,,PID,'LIN PID register',0.,5.,,rw
,,,RSVD_31_6,'Reserved',6.,31.,,rw
,0x0000010C,32.,UART5_UART_LIN_CHECKSUM,'LIN checksum register(LIN_CHECKSUM)',,,,rw
,,,CHECKSUM_TYPE,'LIN checksum type',0.,0.,,rw
,,,RSVD_7_1,'Reserved',1.,7.,,rw
,,,RSVD_31_8,'Reserved',8.,31.,,rw
,0x00000110,32.,UART5_UART_LIN_DEL_LENGTH,'LIN delimiter field length(LIN_DEL_LENGTH)',,,,rw
,,,LIN_DEL_LENGTH,'LIN delimiter field length',0.,2.,,rw
,,,RSVD_31_3,'Reserved',3.,31.,,rw
,0x00000114,32.,UART5_UART_LIN_PID_FILTER_0,'LIN PID filter 0(LIN_PID_FILTER_0)',,,,rw
,,,FID0,'filter PID0',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID1,'filter PID1',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID2,'filter PID2',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID3,'filter PID3',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000118,32.,UART5_UART_LIN_PID_FILTER_1,'LIN PID filter 1(LIN_PID_FILTER_1)',,,,rw
,,,FID4,'filter PID4',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID5,'filter PID5',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID6,'filter PID6',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID7,'filter PID7',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x0000011C,32.,UART5_UART_LIN_PID_FILTER_2,'LIN PID filter 2(LIN_PID_FILTER_2)',,,,rw
,,,FID8,'filter PID8',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID9,'filter PID9',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID10,'filter PID10',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID11,'filter PID11',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000120,32.,UART5_UART_LIN_PID_FILTER_3,'LIN PID filter 3(LIN_PID_FILTER_3)',,,,rw
,,,FID12,'filter PID12',0.,5.,,rw
,,,RSVD_7_6,'Reserved',6.,7.,,rw
,,,FID13,'filter PID13',8.,13.,,rw
,,,RSVD_15_14,'Reserved',14.,15.,,rw
,,,FID14,'filter PID14',16.,21.,,rw
,,,RSVD_23_22,'Reserved',22.,23.,,rw
,,,FID15,'filter PID15',24.,29.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000124,32.,UART5_UART_LIN_PID_FILTER_VAGUE,'LIN PID filter vague(LIN_PID_FILTER_VAGUE)',,,,rw
,,,FID_VAGUE,'vague filter PID ',0.,5.,,rw
,,,RSVD_31_30,'Reserved',30.,31.,,rw
,0x00000128,32.,UART5_UART_LIN_PID_FILTER_CTRL,'LIN PID filter ctrl register(LIN_PID_FILTER_CTRL)',,,,rw
,,,FID_MASK,'the enable bit of the filter id 0-15',0.,16.,,rw
,,,FID_VAGUE_MASK,'he enable bit of the filter vague id ',17.,22.,,rw
,,,LIN_FILTER_EN,'the enable bit of the filter',23.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
tree.end
base ad:0x40073000
tree "CMP"
,0x00000000,32.,CMP_VERID,'Version ID register(CMP_VERID)',,,,rd
,,,VERID,'CMP version number',0.,31.,,rd
,0x00000004,32.,CMP_PARAM,'Parameter register',,,,rd
,,,DAC_RES,'DAC resolution',0.,3.,,rd
,,,RSVD_31_4,'Reserved',4.,31.,,rd
,0x00000008,32.,CMP_CCR0,'Comparator control register0(CMP_CCR0)',,,,rw
,,,CMP_SEL,'Low speed/high speed comparator select ',0.,0.,,rw
,,,CMP_EN,'comparator enable',1.,1.,,rw
,,,SOC_TRG_EN,'SOC trigger enable',2.,2.,,rw
,,,STOP_EN,'stop enable bit',3.,3.,,rw
,,,RSVD_31_4,'Reserved',4.,31.,,rw
,0x0000000C,32.,CMP_CCR1,'Comparator control register1(CMP_CCR1)',,,,rw
,,,WINDOW_EN,'Window mode enable',0.,0.,,rw
,,,SAMPLE_EN,'sample mode enable',1.,1.,,rw
,,,DMA_EN,'DMA enbale',2.,2.,,rw
,,,COUT_INV,'Comparator invert',3.,3.,,rw
,,,COUT_SEL,'Cout select',4.,4.,,rw
,,,COUT_PEN,'Cout output to pad ',5.,5.,,rw
,,,COUT_OWE,'COUT level when window is closed, enbale bit',6.,6.,,rw
,,,COUT_OW,'COUT level when window is closed',7.,7.,,rw
,,,RSVD_15_8,'Reserved',8.,15.,,rw
,,,FILT_CNT,'Filer sample count',16.,18.,,rw
,,,RSVD_23_19,'Reserved',19.,23.,,rw
,,,FILT_PER,'Filter sample period',24.,31.,,rw
,0x00000010,32.,CMP_CCR2,'Comparator control register2(CMP_CCR2)',,,,rw
,,,HS_HSTCTR,'High-speed cmp hyst select',0.,1.,,rw
,,,RSVD_3_2,'Reserved',2.,3.,,rw
,,,LS_HSTCTR,'low-speed cmp hyst select',4.,5.,,rw
,,,RSVD_15_6,'Reserved',6.,15.,,rw
,,,HS_PSEL,'High speed CMP PMUX select',16.,19.,,rw
,,,HS_MSEL,'High speed CMP NMUX select',20.,23.,,rw
,,,LS_PSEL,'low speed CMP PMUX select',24.,27.,,rw
,,,LS_MSEL,'low speed CMP NMUX select',28.,31.,,rw
,0x00000014,32.,CMP_DCR,'DAC control register(CMP_DCR)',,,,rw
,,,DAC_EN,'DAC enable',0.,0.,,rw
,,,DAC_BUFF_EN,'Reserved',1.,1.,,rw
,,,RSVD_7_2,'Reserved',2.,7.,,rw
,,,VREF_SEL,'DAC reference select',8.,8.,,rw
,,,RSVD_15_9,'Reserved',9.,15.,,rw
,,,DAC_SEL,'DAC output Voltage select',16.,23.,,rw
,,,RSVD_31_24,'Reserved',24.,31.,,rw
,0x00000018,32.,CMP_IER,'Interrupt enable register(CMP_IER)',,,,rw
,,,CFR_IE,'Comparator flag raising interrupt enable',0.,0.,,rw
,,,CFF_IE,'Comparator flag falling interrupt enable',1.,1.,,rw
,,,RSVD_31_2,'Reserved',2.,31.,,rw
,0x0000001C,32.,CMP_CSR,'Comparator status register(CMP_CSR)',,,,rw
,,,CFR,'Comparator output raising edge',0.,0.,,rw
,,,CFF,'Comparator output falling edge ',1.,1.,,rw
,,,RSVD_7_2,'Reserved',2.,7.,,rw
,,,COUT,'Analog comparator output  ',8.,8.,,rw
,,,RSVD_31_9,'Reserved',9.,31.,,rw
tree.end
base ad:0x40079000
tree "RTC"
,0x00000000,32.,RTC_CSR,'RTC control and status register (RTC_CSR)',,,,rw
,,,CRYSTAL_EN,'internal 32K crystal enable',0.,0.,,rw
,,,CNT_CLK_SEL,'RTC one second counter clock source select bit',1.,1.,,rw
,,,CLKOUT_SEL,'RTC output clock to pin output enable',2.,2.,,rw
,,,CLKOUT_PIN_EN,'RTC output clock to pin output enable',3.,3.,,rw
,,,SUP_EN,'supervisor mode enable',4.,4.,,rw
,,,SW_RST,'software reset',5.,5.,,rw
,,,COUNT_EN,'RTC timer counter enable',6.,6.,,rw
,,,OVF,'RTC overflow flag',7.,7.,,rw
,,,ALARM_MATCHF,'RTC alarm match flag',8.,8.,,rw
,,,OSC_RDY,'OSC32K ready ',9.,9.,,rw
,,,EXTAL_32K_EN,'extal 32K enable bit',10.,10.,,rw
,,,SECONDS_INT_FLAG,'seconds interrupt flag',11.,11.,,rw
,,,PERIODIC_CNT_EN,'RTC periodic counter enable ',12.,12.,,rw
,,,PERIODIC_MATCH_FLG,'RTC perriodic counter match flag',13.,13.,,rw
,,,RSVD_31_14,'reserved',14.,31.,,rw
,0x00000004,32.,RTC_IER,'RTC interrupt enable register(RTC_IER)',,,,rw
,,,SECOND_INT_MUX_SEL,'seconds interrupt mux selection',0.,2.,,rw
,,,OVFLOW_IE,'RTC overflow interrupt enable',3.,3.,,rw
,,,ALARM_IE,'RTC timer alarm match interrupt enable',4.,4.,,rw
,,,SECONDS_IE,'seconds interrut enable',5.,5.,,rw
,,,PERIODIC_IE,'RTC periodic timer interrupt enable ',6.,6.,,rw
,,,RSVD_31_7,'reserved',7.,31.,,rw
,0x00000008,32.,RTC_ALARM_CNTR,'RTC  alarm counter register(RTC_ALARM_CNTR)',,,,rw
,,,ALARM_CNT,'alarm counter value',0.,31.,,rw
,0x0000000C,32.,RTC_ONE_SECOND_CNTR,'RTC one second counter register',,,,rw
,,,ONE_SECOND_CNT,'one seconds counter value',0.,15.,,rw
,,,RSVD_31_16,'reserved',16.,31.,,rw
,0x00000010,32.,RTC_MATCH_CNTR,'RTC match counter register(RTC_MATCH_CNTR)',,,,rw
,,,MATCH_CNT,'Reserved',0.,31.,,rw
,0x00000014,32.,RTC_COMPENSATIONR,'RTC compensation register(RTC_COMPENSATIONR)',,,,rw
,,,COMP_CNT,'compensation counter value.',0.,6.,,rw
,,,COMP_DIRECTION,'frequency compensation direction',7.,7.,,rw
,,,DLY,'compensation delay value',8.,15.,,rw
,,,CCOMP_CNT,'current compensation counter value',16.,23.,,rw
,,,CDLY,'current compensation delay value',24.,31.,,rw
,0x00000018,32.,RTC_LOCKR,'RTC lock register (RTC_LOCKR)',,,,rw
,,,RSVD_30_0,'reserved',0.,30.,,rw
,,,LOCK,'lock bit',31.,31.,,rw
,0x0000001C,32.,RTC_VERID,'RTC version ID(RTC_VERID)',,,,rw
,,,VERID,'version ID',0.,31.,,rw
,0x00000020,32.,RTC_PERIODIC_TMR_CNT,'RTC periodic timer counter',,,,rw
,,,PERIODIC_TMR_CNT,'periodic timer counter ',0.,31.,,rw
,0x00000024,32.,RTC_PERIODIC_TMR_MATCH_CNT,'RTC periodic timer match counter',,,,rw
,,,PERIODIC_MATCH_CNT,'periodic timer match counter ',0.,31.,,rw
tree.end
base ad:0x4007C000
tree "REGFILE"
,0x00000000,32.,REGFILE_REGn0,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000004,32.,REGFILE_REGn1,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000008,32.,REGFILE_REGn2,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000000C,32.,REGFILE_REGn3,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000010,32.,REGFILE_REGn4,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000014,32.,REGFILE_REGn5,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000018,32.,REGFILE_REGn6,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000001C,32.,REGFILE_REGn7,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000020,32.,REGFILE_REGn8,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000024,32.,REGFILE_REGn9,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000028,32.,REGFILE_REGn10,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000002C,32.,REGFILE_REGn11,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000030,32.,REGFILE_REGn12,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000034,32.,REGFILE_REGn13,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000038,32.,REGFILE_REGn14,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000003C,32.,REGFILE_REGn15,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000040,32.,REGFILE_REGn16,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000044,32.,REGFILE_REGn17,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000048,32.,REGFILE_REGn18,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000004C,32.,REGFILE_REGn19,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000050,32.,REGFILE_REGn20,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000054,32.,REGFILE_REGn21,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000058,32.,REGFILE_REGn22,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000005C,32.,REGFILE_REGn23,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000060,32.,REGFILE_REGn24,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000064,32.,REGFILE_REGn25,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000068,32.,REGFILE_REGn26,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000006C,32.,REGFILE_REGn27,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000070,32.,REGFILE_REGn28,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000074,32.,REGFILE_REGn29,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x00000078,32.,REGFILE_REGn30,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
,0x0000007C,32.,REGFILE_REGn31,'register file register',,,,rw
,,,DATA,'DATA field',0.,31.,,rw
tree.end
base ad:0x4007D000
tree "PMU"
,0x00000000,32.,PMU_LOCK,'PMU lock protection register(PMU_LOCK_USER)',,,,rw
,,,RSVD_30_0,'reserve',0.,30.,,rw
,,,LOCK,'PMU LOCK protection bit.',31.,31.,,rw
,0x00000004,32.,PMU_LPO_32K_CFG,'PMU LPO32K control register(PMU_LPO32K_CFG)',,,,rw
,,,LPO_CLK_DIS,'LPO clock disable bit',0.,0.,,rw
,,,LPO_CLK_SEL,'LPO clock select bit.',1.,1.,,rw
,,,LPO_CLK_READY,'LPO raw clock ready flag.',2.,2.,,rw
,,,RSVD_31_3,'reserve',3.,31.,,rw
,0x00000008,32.,PMU_LPO_32K_TRIM,'PMU LPO32K trim reigster(PMU_LPO32K_TRIM)',,,,rw
,,,LPO_32K_TRIM,'LPO32K trim',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x0000000C,32.,PMU_ISO_CLR,'PMU isolation clear register(PMU_ISO_CLR)',,,,rw
,,,ISO_CLR,'isolation w1c clear bit.',0.,0.,,rw
,,,RSVD_31_1,'reserve',1.,31.,,rw
,0x00000010,32.,PMU_CSR,'PMU control and status register(PMU_CSR)',,,,rw
,,,VDD_LVD_LP_EN,'VDD5v LVD detect control bit under low power mode',0.,0.,,rw
,,,VDD_LVD_ACT_EN,'VDD5v LVD detect control bit under active mode',1.,1.,,rw
,,,VDD_LVD_IE,'VDD5v LVD interrupt enable control',2.,2.,,rw
,,,VDD_LVD_RE,'VDD5v LVD reset enable control bit',3.,3.,,rw
,,,VDD_LVW_EN,'VDD5v LVW detect control bit.',4.,4.,,rw
,,,VDD_LVW_IE,'VDD5v LVW interrupt enable',5.,5.,,rw
,,,LVWF_VDD,'VDD5v LVW detect flag',6.,6.,,rw
,,,LVDF_VDD,'VDD5v LVD flag',7.,7.,,rw
,,,REF_BUF_1V_EN,'Reference 1V output enable with buf control',8.,8.,,rw
,,,HS_LDO_TRIM_SEL,'high speed trim select bit',9.,9.,,rw
,,,VOLTAGE_TRIM_DONE,'voltage trim done flag',10.,10.,,rw
,,,IREF_EN,'iref1uA enable bit',11.,11.,,rw
,,,RSVD_31_12,'reserve',12.,31.,,rw
,0x00000014,32.,PMU_LDO_EN_CFG,'PMU  LDO enable configure register(PMU_LDO_EN_CFG)',,,,rw
,,,LDO_CORE_EN,'LDO-core regulator enable control',0.,0.,,rw
,,,LDO_CLOCK_EN,'LDO-clock regulator enable control',1.,1.,,rw
,,,LDO_FLASH_EN,'LDO-flash regulator enable control',2.,2.,,rw
,,,RSVD_3,'reserve',3.,3.,,rw
,,,LDO_CORE_LPEN,'LDO-core  low drive strength enable uner stop mode',4.,4.,,rw
,,,LDO_CLOCK_LPEN,'LDO-clock low drive strength mode enable under stop mode',5.,5.,,rw
,,,LDO_FLASH_LPEN,'LDO-flash low drive strength mode enable under stop mode ',6.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x00000018,32.,PMU_LDO_LVD_STATUS,'PMU LDO LVD status register(PMU_LDO_LVD_STATUS)',,,,rw
,,,LVD_CORE_FLAG,'LDO core LVD flag',0.,0.,,rw
,,,LVD_CLOCK_FLAG,'LDO clock LVD flag',1.,1.,,rw
,,,LVD_FLASH_FLAG,'LDO flash  LVD flag',2.,2.,,rw
,,,RSVD_3,'reserve',3.,3.,,rw
,,,LVD_AOA_FLAG,'always-on analog LDO LVD flag',4.,4.,,rw
,,,RSVD_31_5,'reserve',5.,31.,,rw
,0x0000001C,32.,PMU_LDO_LVD_CFG,'PMU LDO LVD configure register(PMU_LDO_LVD_CFG)',,,,rw
,,,LVD_CORE_RE,'PMU LDO-core LVD reset enable control',0.,0.,,rw
,,,LVD_CLOCK_RE,'PMU LDO-clock LVD reset enable control',1.,1.,,rw
,,,LVD_FLASH_RE,'PMU LDO-flash LVD reset enable control',2.,2.,,rw
,,,RSVD_3,'reserve',3.,3.,,rw
,,,LVD_AOA_RE,'PMU LDO-aoa LVD reset enable control',4.,4.,,rw
,,,ACT_CORE_LVDE,'PMU LDO-core LVD detect control under active mode',5.,5.,,rw
,,,ACT_CLOCK_LVDE,'PMU LDO-clock LVD detect control under active mode',6.,6.,,rw
,,,RSVD_8_7,'reserve',7.,8.,,rw
,,,ACT_AOA_LVDE,'PMU LDO-aoa LVD detect control under active mode',9.,9.,,rw
,,,LP_CORE_LVDE,'PMU LDO-core LVD detect control under low power mode',10.,10.,,rw
,,,LP_CLOCK_LVDE,'PMU LDO-clock LVD detect control under low power mode',11.,11.,,rw
,,,RSVD_13_12,'reserve',12.,13.,,rw
,,,LP_AOA_LVDE,'PMU always-on LDO-aoa LVD detect control under low power mode',14.,14.,,rw
,,,RSVD_31_15,'reserve',15.,31.,,rw
,0x00000020,32.,PMU_LDO_LVD_HYST_DLY,'PMU LDO LVD delay configure register(PMU_LVD_HYST_DLY)',,,,rw
,,,CORE_LVD_HYST_DLY_SEL,'core-lvd_hyst select',0.,0.,,rw
,,,CLK_LVD_HYST_DLY_SEL,'clk-lvd_hyst select',1.,1.,,rw
,,,FLASH_LVD_HYST_DLY_SEL,'flash-lvd_hyst select',2.,2.,,rw
,,,AOA_LVD_HYST_DLY_SEL,'aoa-lvd_hyst select',3.,3.,,rw
,,,RSVD_31_4,'reserve',4.,31.,,rw
,0x00000024,32.,PMU_HS_TRIM_DLY_CNT,'PMU reserve1 register  (PMU_RESERVE1)',,,,rw
,,,HS_TRIM_DLY_CNT,'delay counter for switch between hsrun and run',0.,12.,,rw
,,,RSVD_31_13,'reserve',13.,31.,,rw
,0x00000028,32.,PMU_RESERVE2,'PMU reserve2 register (PMU_RESERVE2)',,,,rw
,,,RSVD_31_0,'reserve',0.,31.,,rw
,0x0000002C,32.,PMU_LOCK_TEST,'reserve for user , doest not suggest user write this regsiter though no hardfault during write acces..',,,,rw
,,,RSVD_30_0,'reserve',0.,30.,,rw
,,,LOCK_TEST,'PMU LOCK test protection bit',31.,31.,,rw
,0x00000030,32.,PMU_TEST_REQPIN_CFG,'PMU request pin observe register(PMU_TEST_REQPIN)',,,,rw
,,,OE,'Request pin output enable',0.,0.,,rw
,,,POLARITY,'Request pin polarity control',1.,1.,,rw
,,,OVERIDE,'Request pin override enable',2.,3.,,rw
,,,REQ_MUX_OUT_EN,'Request pin mux output',4.,28.,,rw
,,,REQ_PORT_EN,'Request pin port enable control',29.,29.,,rw
,,,RSVD_31_30,'reserve',30.,31.,,rw
,0x00000034,32.,PMU_TEST_BG_TRIM,'PMU test bangap trim register(PMU_TEST_BG_TRIM)',,,,rw
,,,BG_TC_TRIM,'Bandgap temperature trim',0.,6.,,rw
,,,RSVD_7,'reserve',7.,7.,,rw
,,,BG_ITRIM,'BandGap current reference trim',8.,12.,,rw
,,,RSVD_31_13,'reserve',13.,31.,,rw
,0x00000038,32.,PMU_TEST_LVW_VDD5V_TRIM,'PMU test LVW VDD5V trim register(PMU_TEST_LVW_VDD5V_TRIM)',,,,rw
,,,LVW_VDD5V_TRIM,'VDD5v LVW trim bits',0.,1.,,rw
,,,RSVD_31_2,'reserve',2.,31.,,rw
,0x0000003C,32.,PMU_TEST_CORE_TRIM,'PMU test CORE trim register(PMU_TEST_CORE_TRIM)',,,,rw
,,,LDO_CORE_TRIM,'LDO CORE trim bits',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x00000040,32.,PMU_TEST_AOD_TRIM,'PMU test AOD trim register(PMU_TEST_AOD_TRIM)',,,,rw
,,,LDO_AOD_TRIM,'LDO-aod trim bits',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x00000044,32.,PMU_TEST_AOA_TRIM,'PMU test AOA trim register(PMU_TEST_AOA_TRIM)',,,,rw
,,,LDO_AOA_TRIM,'LDO-aoa trim bits',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x00000048,32.,PMU_TEST_FLASH_TRIM,'PMU test FLASH trim register(PMU_TEST_FLASH_TRIM)',,,,rw
,,,LDO_FLASH_TRIM,'LDO-flash trim bits',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x0000004C,32.,PMU_TEST_CLOCK_TRIM,'PMU test CLOCK trim register(PMU_TEST_CLOCK_TRIM)',,,,rw
,,,LDO_CLOCK_TRIM,'LDO-clock trim bits',0.,6.,,rw
,,,RSVD_31_7,'reserve',7.,31.,,rw
,0x00000050,32.,PMU_TEST_REF1V_TRIM,'PMU test REF1V trim regsiter(PMU_TEST_REF1V_TRIM)',,,,rw
,,,REF1V_TRIM,'Bandgap reference 1v trim bits',0.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x00000054,32.,PMU_TEST_REF1V_AOA_TRIM,'PMU test AOA REF1V trim register(PMU_TEST_REF1V_AOA_TRIM)',,,,rw
,,,REF1V_AOA_TRIM,'LDO-aoa reference 1V trim',0.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x00000058,32.,PMU_TEST_REF1V_CORE_TRIM,'PMU test CORE REF1V trim register(PMU_TEST_REF1V_CORE_TRIM)',,,,rw
,,,REF1V_CORE_TRIM,'LDO-core reference 1V trim',0.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x0000005C,32.,PMU_TEST_REF1V_FLASH_TRIM,'PMU test FLASH REF1V trim register(PMU_TEST_REF1V_FLASH_TRIM)',,,,rw
,,,REFV1_FLASH_TRIM,'LDO-flash reference 1V trim',0.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x00000060,32.,PMU_TEST_REF1V_CLOCK_TRIM,'PMU test CLOCK REF1V trim register(PMU_TEST_REF1V_CLOCK_TRIM)',,,,rw
,,,REF1V_CLOCK_TRIM,'LDO-clock reference 1V trim',0.,5.,,rw
,,,RSVD_31_6,'reserve',6.,31.,,rw
,0x00000064,32.,PMU_TEST_HV_CFG,'PMU test high voltage configure register(PMU_TEST_HV_CFG)',,,,rw
,,,CORE_1P5X_SEL,'ldo-core 1p5x select',0.,0.,,rw
,,,CORE_2X_SEL,'ldo-core 2x select',1.,1.,,rw
,,,CLK_1P5X_SEL,'ldo-clock 1p5x select',2.,2.,,rw
,,,CLK_2X_SEL,'ldo-clock 2x select',3.,3.,,rw
,,,FLASH_1P5X_SEL,'ldo-flash 1p5x select',4.,4.,,rw
,,,FLASH_2X_SEL,'ldo-flash 2x select',5.,5.,,rw
,,,AOD_1P5X_SEL,'ldo-aod 1p5x select',6.,6.,,rw
,,,AOD_2X_SEL,'ldo-aod 2x select',7.,7.,,rw
,,,AOA_1P5X_SEL,'ldo-aoa 1p5x select',8.,8.,,rw
,,,AOA_2X_SEL,'ldo-aoa 2x select',9.,9.,,rw
,,,RSVD_31_10,'reserve',10.,31.,,rw
,0x00000068,32.,PMU_LDO_CLAMP_CFG,'PMU LDO clamp configure register(PMU_LDO_CLAMP_CFG)',,,,rw
,,,LDO_CORE_CLAMP_EN,'ldo-core clamp enable',0.,0.,,rw
,,,LDO_CLOCK_CLAMP_EN,'ldo-clock clamp enable',1.,1.,,rw
,,,LDO_FLASH_CLAMP_EN,'ldo-flash clamp enable',2.,2.,,rw
,,,LDO_AOD_CLAMP_EN,'ldo-aod clamp enable',3.,3.,,rw
,,,LDO_AOA_CLAMP_EN,'ldo-aoa clamp enable',4.,4.,,rw
,,,RSVD_31_5,'reserve',5.,31.,,rw
tree.end
base ad:0x4007E000
tree "SRMC"
,0x00000000,32.,SRMC_VERID,'Version ID Register (SRMC_VERID)',,,,rd
,,,FEATURE,'Feature Number',0.,15.,,rd
,,,MINOR,'Minor Version Number',16.,23.,,rd
,,,MAJOR,'Major Version Number',24.,31.,,rd
,0x00000004,32.,SRMC_PARAM,'Parameter Register (SRMC_PARAM)',,,,rd
,,,EWAKEUP,'Existence of SRS[WAKEUP] status indication feature',0.,0.,,rd
,,,ELVD,'Existence of SRS[LVD] status indication feature',1.,1.,,rd
,,,ELOC,'Existence of SRS[LOC] status indication feature',2.,2.,,rd
,,,ELOL,'Existence of SRS[LOL] status indication feature',3.,3.,,rd
,,,RSVD_4,'Reserved',4.,4.,,rd
,,,EWDOG,'Existence of SRS[EWOG] status indication feature',5.,5.,,rd
,,,EPIN,'Existence of SRS[EPIN] status indication feature',6.,6.,,rd
,,,EPOR,'Existence of SRS[POR] status indication feature',7.,7.,,rd
,,,RSVD_8,'Reserved',8.,8.,,rd
,,,ELOCKUP,'Existence of SRS[LOCKUP] status indication feature',9.,9.,,rd
,,,ESW,'Existence of SRS[SW] status indication feature',10.,10.,,rd
,,,EMDM_AP,'Existence of SRS[MDM_AP] status indication feature',11.,11.,,rd
,,,RSVD_12,'Reserved',12.,12.,,rd
,,,ESACKERR,'Existence of SRS[SACKERR] status indication feature',13.,13.,,rd
,,,RSVD_15_14,'Reserved',14.,15.,,rd
,,,EPDOWN,'Existence of PDOWN feature',16.,16.,,rd
,,,RSVD_31_17,'Reserved',17.,31.,,rd
,0x00000008,32.,SRMC_SRS,'System Reset Status Register (SRMC_SRS)',,,,rw
,,,RSVD_0,'Reserved',0.,0.,,rw
,,,LVD,'Low Voltage Reset',1.,1.,,rw
,,,LOC,'Loss Of Clock Reset',2.,2.,,rw
,,,RSVD_4_3,'Reserved',3.,4.,,rw
,,,WDOG,'WDOG Reset',5.,5.,,rw
,,,PIN,'External Pin Reset',6.,6.,,rw
,,,POR,'Power-On Reset',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LOCKUP,'LOCKUP Reset',9.,9.,,rw
,,,SW,'Software Reset',10.,10.,,rw
,,,MDM_AP,'MDM-AP System Reset Request',11.,11.,,rw
,,,SERU_COLD,'SERU Cold Reset Request',12.,12.,,rw
,,,SERU_SYS,'SERU System Reset Request',13.,13.,,rw
,,,RSVD_14,'Reserved',14.,14.,,rw
,,,SACKERR,'Stop Acknowledge Error',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x0000000C,32.,SRMC_CTRL,'Reset Control register (SRMC_CTRL)',,,,rw
,,,RSTFLTSRW,'Reset Pin Filter Select in Run and Wait Modes',0.,1.,,rw
,,,RSTFLTSS,'Reset Pin Filter Select in Stop Mode',2.,2.,,rw
,,,RSVD_7_3,'Reserved',3.,7.,,rw
,,,RSTFLTSEL,'Reset Pin Filter Bus Clock Select',8.,12.,,rw
,,,RSVD_30_16,'Reserved',16.,30.,,rw
,,,LOCKUP_RST_EN,'Core Lockup Reset enable',31.,31.,,rw
,0x00000010,32.,SRMC_MR,'Reserved',,,,rd
,,,RSVD_31_0,'Reserved',0.,31.,,rd
,0x00000014,32.,SRMC_FM,'Reserved',,,,rd
,,,RSVD_31_0,'Reserved',0.,31.,,rd
,0x00000018,32.,SRMC_SSRS,'Sticky System Reset Status Register (SRMC_SSRS)',,,,rd
,,,RSVD_0,'Reserved',0.,0.,,rd
,,,SLVD,'Sticky low voltage reset',1.,1.,,rd
,,,SLOC,'Sticky loss of external clock.',2.,2.,,rd
,,,RSVD_4_3,'Reserved',3.,4.,,rd
,,,SWDOG,'Sticky watchdog timer timing out (WDOG)',5.,5.,,rd
,,,SPIN,'Sticky external RESET pin Reset',6.,6.,,rd
,,,SPOR,'Sticky Power-On Reset',7.,7.,,rd
,,,RSVD_8,'Reserved',8.,8.,,rd
,,,SLOCKUP,'Sticky Core Lock Up',9.,9.,,rd
,,,SSW,'Sticky Software Reset',10.,10.,,rd
,,,SMDM_AP,'Sticky MDM-AP System Reset Request',11.,11.,,rd
,,,SSERU_COLD,'Sticky SERU Cold Reset Request',12.,12.,,rd
,,,SSERU_SYS,'Sticky SERU System Reset Request',13.,13.,,rd
,,,RSVD_14_12,'Reserved',12.,14.,,rd
,,,SSACKERR,'Sticky Stop Acknowledge Error',15.,15.,,rd
,,,RSVD_31_16,'Reserved',16.,31.,,rd
,0x0000001C,32.,SRMC_SRIE,'System Reset Interrupt Enable Register (SRMC_SRIE)',,,,rw
,,,DELAY,'Maximum reset delay time',0.,1.,,rw
,,,LOC,'Loss-of-Clock Interrupt Enable',2.,2.,,rw
,,,RSVD_4_3,'Reserved',3.,4.,,rw
,,,WDOG,'Watchdog Interrupt Enable',5.,5.,,rw
,,,PIN,'External Reset Pin Interrupt Enable',6.,6.,,rw
,,,GIE,'Global Interrupt Enable',7.,7.,,rw
,,,RSVD_8,'Reserved',8.,8.,,rw
,,,LOCKUP,'Core Lockup Interrupt',9.,9.,,rw
,,,SW,'Software Reset Interrupt Enable',10.,10.,,rw
,,,RSVD_11,'Reserved',11.,11.,,rw
,,,SERU_COLD,'SERU Cold Reset Request',12.,12.,,rw
,,,SERU_SYS,'SERU System Reset Request',13.,13.,,rw
,,,RSVD_14,'Reserved',14.,14.,,rw
,,,SACKERR,'Stop Acknowledge Error Interrupt',15.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000020,32.,SRMC_PMPORT,'Power Mode Protection register (SRMC_PMPROT)',,,,rw
,,,APD,'Allow Power down mode',0.,0.,,rw
,,,RSVD_31_1,'Reserved',1.,31.,,rw
,0x00000024,32.,SRMC_PMCTRL,'Power Mode Control register (SRMC_PMCTRL)',,,,rw
,,,DSMC,'Deep Sleep Mode Configuration',0.,1.,,rw
,,,RSVD_7_2,'Reserved',2.,7.,,rw
,,,DSMACKTMO,'Deep Sleep Mode Acknowledge Time Out',8.,15.,,rw
,,,RSVD_31_16,'Reserved',16.,31.,,rw
,0x00000028,32.,SRMC_PMSTAT,'Power Mode Status register (SRMC_PMSTAT)',,,,rd
,,,PMSTAT,'PMSTAT Power Mode Status',0.,3.,,rd
,,,RSVD_7_4,'Reserved',4.,7.,,rd
,,,DSMABORT,'Deep Sleep Mode Aborted',8.,8.,,rd
,,,RSVD_31_7,'Reserved',7.,31.,,rd
,0x0000002C,32.,SRMC_DSMWUPC1,'DSM Wakeup Control Register (SRMC_DSMWUPC)',,,,rw
,,,WUPSRC_EN2_0,'Wakeup Source Enable',0.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,WUPSRC_EN15_4,'Wakeup Source Enable',4.,15.,,rw
,,,WUPSRC_PL2_0,'Wakeup Source Polarity',16.,18.,,rw
,,,RSVD_19,'Reserved',19.,19.,,rw
,,,WUPSRC_PL14_4,'Wakeup Source Polarity',20.,30.,,rw
,,,RSVD_31,'Reserved',31.,31.,,rw
,0x00000030,32.,SRMC_DSMWUPC2,'DSM Wakeup Control Register (SRMC_DSMWUPC)',,,,rw
,,,WUPSRC_EN16,'Wakeup Source Enable',0.,0.,,rw
,,,RSVD_15_1,'Reserved',1.,15.,,rw
,,,RSVD_16,'Reserved',16.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
,0x00000034,32.,SRMC_DSMWUPS,'DSM Wakeup Status Register (SRMC_DSMWUPS)',,,,rw
,,,WUPS_2_0,'Wakeup Status',0.,2.,,rw
,,,RSVD_3,'Reserved',3.,3.,,rw
,,,WUPS_16_4,'Wakeup Status',4.,16.,,rw
,,,RSVD_31_17,'Reserved',17.,31.,,rw
tree.end
base ad:0x4007F000
tree "SERU"
,0x00000000,32.,SERU_VERSION,'Reserved',,,,rd
,,,VERSION,'version',0.,31.,,rd
,0x00000004,32.,SERU_PARAM,'Reserved',,,,rd
,,,PARAM,'parameter',0.,31.,,rd
,0x00000008,32.,SERU_CSR,'Reserved',,,,rw
,,,CRPAR_INT_EN,'register parity error int enable',0.,0.,,rw
,,,RSVD_3_1,'This field is reserved',1.,3.,,rw
,,,EOUT_PS,'EOUT Polarity Selection',4.,4.,,rw
,,,EOUT0_IO_EN,'EOUT0 to external pin',5.,5.,,rw
,,,EOUT1_IO_EN,'EOUT1 to external pin',6.,6.,,rw
,,,FFI_EN,'fake fault injection enable',7.,7.,,rw
,,,CFG_MODE,'configure mode',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000000C,32.,SERU_INTF,'Reserved',,,,rw
,,,S_CRPAR_ERR,'register parity error flag',0.,0.,,rw
,,,RSVD_31_1,'This field is reserved',1.,31.,,rw
,0x00000010,32.,SERU_CFG_KEY,'Reserved',,,,rw
,,,KEY,'configure mode key',0.,31.,,rw
,0x00000014,32.,SERU_CH_FFI,'Reserved',,,,rw
,,,CH_FFI,'Fake fault injection',0.,31.,,rw
,0x00000018,32.,SERU_SWERR_GNT,'Reserved',,,,rw
,,,SWERR_CH0,'software error generate',0.,0.,,rw
,,,SWERR_CH1,'software error generate',1.,1.,,rw
,,,SWERR_CH2,'software error generate',2.,2.,,rw
,,,RSVD_31_3,'This field is reserved',3.,31.,,rw
,0x0000001C,32.,SERU_CH_FLAG,'Reserved',,,,rw
,,,CH_FLAG,'channel error flag',0.,31.,,rw
,0x00000020,32.,SERU_CFG_CHn0,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000024,32.,SERU_CFG_CHn1,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000028,32.,SERU_CFG_CHn2,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000002C,32.,SERU_CFG_CHn3,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000030,32.,SERU_CFG_CHn4,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000034,32.,SERU_CFG_CHn5,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000038,32.,SERU_CFG_CHn6,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000003C,32.,SERU_CFG_CHn7,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000040,32.,SERU_CFG_CHn8,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000044,32.,SERU_CFG_CHn9,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000048,32.,SERU_CFG_CHn10,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000004C,32.,SERU_CFG_CHn11,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000050,32.,SERU_CFG_CHn12,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000054,32.,SERU_CFG_CHn13,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000058,32.,SERU_CFG_CHn14,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000005C,32.,SERU_CFG_CHn15,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000060,32.,SERU_CFG_CHn16,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000064,32.,SERU_CFG_CHn17,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000068,32.,SERU_CFG_CHn18,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000006C,32.,SERU_CFG_CHn19,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000070,32.,SERU_CFG_CHn20,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000074,32.,SERU_CFG_CHn21,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000078,32.,SERU_CFG_CHn22,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000007C,32.,SERU_CFG_CHn23,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000080,32.,SERU_CFG_CHn24,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000084,32.,SERU_CFG_CHn25,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000088,32.,SERU_CFG_CHn26,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000008C,32.,SERU_CFG_CHn27,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000090,32.,SERU_CFG_CHn28,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000094,32.,SERU_CFG_CHn29,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x00000098,32.,SERU_CFG_CHn30,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
,0x0000009C,32.,SERU_CFG_CHn31,'Reserved',,,,rw
,,,CH_EN,'enable channel',0.,0.,,rw
,,,CH_INT_CFG,'enable INT generation',1.,1.,,rw
,,,CH_INT_TYP,'enable INT type',2.,2.,,rw
,,,CH_EOUT_CFG,'enable EOUT report',3.,3.,,rw
,,,CH_RESET_CFG,'enable RESET generation',4.,4.,,rw
,,,CH_RESET_TYP,'select RESET type',5.,5.,,rw
,,,CH_RESET_DLY,'reset generation delay',6.,7.,,rw
,,,CH_FLAG,'channel error flag',8.,8.,,rw
,,,RSVD_31_9,'This field is reserved',9.,31.,,rw
tree.end
base ad:0x400FF000
tree "GPIO"
,0x00000000,32.,GPIOA_PDOR,'Port Data Output Register(GPIOA_PDOR)',,,,rw
,,,PDO,'Port Data Output',0.,31.,,rw
,0x00000004,32.,GPIOA_PSOR,'Port Set Output Register(GPIOA_PSOR)',,,,wr
,,,PSO,'Port Set Output',0.,31.,,wr
,0x00000008,32.,GPIOA_PCOR,'Port Clear Output Register(GPIOA_PCOR)',,,,wr
,,,PCO,'Port Clear Output',0.,31.,,wr
,0x0000000C,32.,GPIOA_PTOR,'Port Toggle Output Register(GPIOA_PTOR)',,,,wr
,,,PTO,'Port Toggle Output',0.,31.,,wr
,0x00000010,32.,GPIOA_PDIR,'Port Data Input Register(GPIOA_PDIR)',,,,rd
,,,PDI,'Port Data Input',0.,31.,,rd
,0x00000014,32.,GPIOA_PDDR,'Port Data Direction Register(GPIOA_PDDR)',,,,rw
,,,PDD,'Port Data Direction',0.,31.,,rw
,0x00000018,32.,GPIOA_PIDR,'Port Input Disable Register(GPIOA_PIDR)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00000040,32.,GPIOB_PDOR,'Port Data Output Register(GPIOB_PDOR)',,,,rw
,,,PDO,'Port Data Output',0.,31.,,rw
,0x00000044,32.,GPIOB_PSOR,'Port Set Output Register(GPIOB_PSOR)',,,,wr
,,,PSO,'Port Set Output',0.,31.,,wr
,0x00000048,32.,GPIOB_PCOR,'Port Clear Output Register(GPIOB_PCOR)',,,,wr
,,,PCO,'Port Clear Output',0.,31.,,wr
,0x0000004C,32.,GPIOB_PTOR,'Port Toggle Output Register(GPIOB_PTOR)',,,,wr
,,,PTO,'Port Toggle Output',0.,31.,,wr
,0x00000050,32.,GPIOB_PDIR,'Port Data Input Register(GPIOB_PDIR)',,,,rd
,,,PDI,'Port Data Input',0.,31.,,rd
,0x00000054,32.,GPIOB_PDDR,'Port Data Direction Register(GPIOB_PDDR)',,,,rw
,,,PDD,'Port Data Direction',0.,31.,,rw
,0x00000058,32.,GPIOB_PIDR,'Port Input Disable Register(GPIOB_PIDR)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00000080,32.,GPIOC_PDOR,'Port Data Output Register(GPIOC_PDOR)',,,,rw
,,,PDO,'Port Data Output',0.,31.,,rw
,0x00000084,32.,GPIOC_PSOR,'Port Set Output Register(GPIOC_PSOR)',,,,wr
,,,PSO,'Port Set Output',0.,31.,,wr
,0x00000088,32.,GPIOC_PCOR,'Port Clear Output Register(GPIOC_PCOR)',,,,wr
,,,PCO,'Port Clear Output',0.,31.,,wr
,0x0000008C,32.,GPIOC_PTOR,'Port Toggle Output Register(GPIOC_PTOR)',,,,wr
,,,PTO,'Port Toggle Output',0.,31.,,wr
,0x00000090,32.,GPIOC_PDIR,'Port Data Input Register(GPIOC_PDIR)',,,,rd
,,,PDI,'Port Data Input',0.,31.,,rd
,0x00000094,32.,GPIOC_PDDR,'Port Data Direction Register(GPIOC_PDDR)',,,,rw
,,,PDD,'Port Data Direction',0.,31.,,rw
,0x00000098,32.,GPIOC_PIDR,'Port Input Disable Register(GPIOC_PIDR)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x000000C0,32.,GPIOD_PDOR,'Port Data Output Register(GPIOD_PDOR)',,,,rw
,,,PDO,'Port Data Output',0.,31.,,rw
,0x000000C4,32.,GPIOD_PSOR,'Port Set Output Register(GPIOD_PSOR)',,,,wr
,,,PSO,'Port Set Output',0.,31.,,wr
,0x000000C8,32.,GPIOD_PCOR,'Port Clear Output Register(GPIOD_PCOR)',,,,wr
,,,PCO,'Port Clear Output',0.,31.,,wr
,0x000000CC,32.,GPIOD_PTOR,'Port Toggle Output Register(GPIOD_PTOR)',,,,wr
,,,PTO,'Port Toggle Output',0.,31.,,wr
,0x000000D0,32.,GPIOD_PDIR,'Port Data Input Register(GPIOD_PDIR)',,,,rd
,,,PDI,'Port Data Input',0.,31.,,rd
,0x000000D4,32.,GPIOD_PDDR,'Port Data Direction Register(GPIOD_PDDR)',,,,rw
,,,PDD,'Port Data Direction',0.,31.,,rw
,0x000000D8,32.,GPIOD_PIDR,'Port Input Disable Register(GPIOD_PIDR)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
,0x00000100,32.,GPIOE_PDOR,'Port Data Output Register(GPIOE_PDOR)',,,,rw
,,,PDO,'Port Data Output',0.,31.,,rw
,0x00000104,32.,GPIOE_PSOR,'Port Set Output Register(GPIOE_PSOR)',,,,wr
,,,PSO,'Port Set Output',0.,31.,,wr
,0x00000108,32.,GPIOE_PCOR,'Port Clear Output Register(GPIOE_PCOR)',,,,wr
,,,PCO,'Port Clear Output',0.,31.,,wr
,0x0000010C,32.,GPIOE_PTOR,'Port Toggle Output Register(GPIOE_PTOR)',,,,wr
,,,PTO,'Port Toggle Output',0.,31.,,wr
,0x00000110,32.,GPIOE_PDIR,'Port Data Input Register(GPIOE_PDIR)',,,,rd
,,,PDI,'Port Data Input',0.,31.,,rd
,0x00000114,32.,GPIOE_PDDR,'Port Data Direction Register(GPIOE_PDDR)',,,,rw
,,,PDD,'Port Data Direction',0.,31.,,rw
,0x00000118,32.,GPIOE_PIDR,'Port Input Disable Register(GPIOE_PIDR)',,,,rd
,,,RSVD_31_0,'This field is reserved',0.,31.,,rd
tree.end

