Classic Timing Analyzer report for prj1
Thu Feb 13 22:17:28 2025
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'CPU_SCK'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                 ;
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From      ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 6.500 ns                         ; CPU_SDI   ; SimTxEnReg ; --         ; CPU_SCK  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 24.000 ns                        ; RxCnt[4]  ; CPU_SDO    ; CPU_SCK    ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 16.700 ns                        ; FLASH_SDO ; CPU_SDO    ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.600 ns                         ; CPU_SDI   ; SimTxEn    ; --         ; CPU_SCK  ; 0            ;
; Clock Setup: 'CPU_SCK'       ; N/A   ; None          ; 72.46 MHz ( period = 13.800 ns ) ; RxCnt[5]  ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;           ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EPM3032ATC44-10    ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CPU_SCK         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 6           ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-6 processors         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CPU_SCK'                                                                                                                                                         ;
+-------+----------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From       ; To         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 72.46 MHz ( period = 13.800 ns ) ; RxCnt[0]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 9.500 ns                ;
; N/A   ; 72.46 MHz ( period = 13.800 ns ) ; RxCnt[1]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 9.500 ns                ;
; N/A   ; 72.46 MHz ( period = 13.800 ns ) ; RxCnt[6]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 9.500 ns                ;
; N/A   ; 72.46 MHz ( period = 13.800 ns ) ; RxCnt[5]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 9.500 ns                ;
; N/A   ; 78.13 MHz ( period = 12.800 ns ) ; RxCnt[7]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 8.500 ns                ;
; N/A   ; 78.13 MHz ( period = 12.800 ns ) ; RxCnt[3]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 8.500 ns                ;
; N/A   ; 78.13 MHz ( period = 12.800 ns ) ; RxCnt[2]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 8.500 ns                ;
; N/A   ; 78.13 MHz ( period = 12.800 ns ) ; RxCnt[4]   ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 8.500 ns                ;
; N/A   ; 85.47 MHz ( period = 11.700 ns ) ; SimTxEnReg ; SimTxEnReg ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 7.400 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[7]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[3]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[6]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[5]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[4]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[0]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[7]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[3]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[2]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 92.59 MHz ( period = 10.800 ns ) ; RxCnt[1]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[0]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[7]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[3]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[2]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[1]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[6]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[5]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; RxCnt[4]   ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[0]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[7]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[3]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[2]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[1]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[6]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[5]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 102.04 MHz ( period = 9.800 ns ) ; RxCnt[4]   ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; 103.09 MHz ( period = 9.700 ns ) ; SimTxEnReg ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.400 ns                ;
; N/A   ; 103.09 MHz ( period = 9.700 ns ) ; SimTxEn    ; SimTxEn    ; CPU_SCK    ; CPU_SCK  ; None                        ; None                      ; 5.400 ns                ;
+-------+----------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tsu                                                                 ;
+-------+--------------+------------+---------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To         ; To Clock ;
+-------+--------------+------------+---------+------------+----------+
; N/A   ; None         ; 6.500 ns   ; CPU_SDI ; SimTxEnReg ; CPU_SCK  ;
; N/A   ; None         ; 3.500 ns   ; CPU_SDI ; SimTxEn    ; CPU_SCK  ;
+-------+--------------+------------+---------+------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To      ; From Clock ;
+-------+--------------+------------+----------+---------+------------+
; N/A   ; None         ; 24.000 ns  ; RxCnt[0] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[3] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[2] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[1] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[6] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[5] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 24.000 ns  ; RxCnt[4] ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 23.900 ns  ; SimTxEn  ; CPU_SDO ; CPU_SCK    ;
; N/A   ; None         ; 23.000 ns  ; RxCnt[7] ; CPU_SDO ; CPU_SCK    ;
+-------+--------------+------------+----------+---------+------------+


+-------------------------------------------------------------------+
; tpd                                                               ;
+-------+-------------------+-----------------+-----------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To      ;
+-------+-------------------+-----------------+-----------+---------+
; N/A   ; None              ; 16.700 ns       ; FLASH_SDO ; CPU_SDO ;
+-------+-------------------+-----------------+-----------+---------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+---------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To         ; To Clock ;
+---------------+-------------+-----------+---------+------------+----------+
; N/A           ; None        ; 0.600 ns  ; CPU_SDI ; SimTxEnReg ; CPU_SCK  ;
; N/A           ; None        ; 0.600 ns  ; CPU_SDI ; SimTxEn    ; CPU_SCK  ;
+---------------+-------------+-----------+---------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
    Info: Processing started: Thu Feb 13 22:17:28 2025
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off prj1 -c prj1
Info: Parallel compilation is enabled and will use 6 of the 6 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CPU_SCK" is an undefined clock
Info: Clock "CPU_SCK" has Internal fmax of 72.46 MHz between source register "RxCnt[0]" and destination register "SimTxEnReg" (period= 13.8 ns)
    Info: + Longest register to register delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 40; REG Node = 'RxCnt[0]'
        Info: 2: + IC(2.200 ns) + CELL(4.000 ns) = 6.200 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'SimTxEnReg~11'
        Info: 3: + IC(0.000 ns) + CELL(3.300 ns) = 9.500 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
        Info: Total cell delay = 7.300 ns ( 76.84 % )
        Info: Total interconnect delay = 2.200 ns ( 23.16 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CPU_SCK" to destination register is 6.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 10; CLK Node = 'CPU_SCK'
            Info: 2: + IC(1.600 ns) + CELL(2.500 ns) = 6.200 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
            Info: Total cell delay = 4.600 ns ( 74.19 % )
            Info: Total interconnect delay = 1.600 ns ( 25.81 % )
        Info: - Longest clock path from clock "CPU_SCK" to source register is 6.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 10; CLK Node = 'CPU_SCK'
            Info: 2: + IC(1.600 ns) + CELL(2.500 ns) = 6.200 ns; Loc. = LC9; Fanout = 40; REG Node = 'RxCnt[0]'
            Info: Total cell delay = 4.600 ns ( 74.19 % )
            Info: Total interconnect delay = 1.600 ns ( 25.81 % )
    Info: + Micro clock to output delay of source is 1.500 ns
    Info: + Micro setup delay of destination is 2.800 ns
Info: tsu for register "SimTxEnReg" (data pin = "CPU_SDI", clock pin = "CPU_SCK") is 6.500 ns
    Info: + Longest pin to register delay is 9.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_33; Fanout = 17; PIN Node = 'CPU_SDI'
        Info: 2: + IC(2.100 ns) + CELL(1.200 ns) = 4.800 ns; Loc. = LC3; Fanout = 1; COMB Node = 'SimTxEnReg~32'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 5.800 ns; Loc. = LC4; Fanout = 1; COMB Node = 'SimTxEnReg~18'
        Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 6.800 ns; Loc. = LC5; Fanout = 1; COMB Node = 'SimTxEnReg~22'
        Info: 5: + IC(0.000 ns) + CELL(3.100 ns) = 9.900 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
        Info: Total cell delay = 7.800 ns ( 78.79 % )
        Info: Total interconnect delay = 2.100 ns ( 21.21 % )
    Info: + Micro setup delay of destination is 2.800 ns
    Info: - Shortest clock path from clock "CPU_SCK" to destination register is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 10; CLK Node = 'CPU_SCK'
        Info: 2: + IC(1.600 ns) + CELL(2.500 ns) = 6.200 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
        Info: Total cell delay = 4.600 ns ( 74.19 % )
        Info: Total interconnect delay = 1.600 ns ( 25.81 % )
Info: tco from clock "CPU_SCK" to destination pin "CPU_SDO" through register "RxCnt[0]" is 24.000 ns
    Info: + Longest clock path from clock "CPU_SCK" to source register is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 10; CLK Node = 'CPU_SCK'
        Info: 2: + IC(1.600 ns) + CELL(2.500 ns) = 6.200 ns; Loc. = LC9; Fanout = 40; REG Node = 'RxCnt[0]'
        Info: Total cell delay = 4.600 ns ( 74.19 % )
        Info: Total interconnect delay = 1.600 ns ( 25.81 % )
    Info: + Micro clock to output delay of source is 1.500 ns
    Info: + Longest register to pin delay is 16.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 40; REG Node = 'RxCnt[0]'
        Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC12; Fanout = 1; COMB Node = 'CPU_SDO~70'
        Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 7.800 ns; Loc. = LC13; Fanout = 1; COMB Node = 'CPU_SDO~60'
        Info: 4: + IC(2.100 ns) + CELL(4.600 ns) = 14.500 ns; Loc. = LC18; Fanout = 1; COMB Node = 'CPU_SDO~61'
        Info: 5: + IC(0.000 ns) + CELL(1.800 ns) = 16.300 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'CPU_SDO'
        Info: Total cell delay = 12.000 ns ( 73.62 % )
        Info: Total interconnect delay = 4.300 ns ( 26.38 % )
Info: Longest tpd from source pin "FLASH_SDO" to destination pin "CPU_SDO" is 16.700 ns
    Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_35; Fanout = 1; PIN Node = 'FLASH_SDO'
    Info: 2: + IC(2.100 ns) + CELL(4.600 ns) = 8.200 ns; Loc. = LC13; Fanout = 1; COMB Node = 'CPU_SDO~60'
    Info: 3: + IC(2.100 ns) + CELL(4.600 ns) = 14.900 ns; Loc. = LC18; Fanout = 1; COMB Node = 'CPU_SDO~61'
    Info: 4: + IC(0.000 ns) + CELL(1.800 ns) = 16.700 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'CPU_SDO'
    Info: Total cell delay = 12.500 ns ( 74.85 % )
    Info: Total interconnect delay = 4.200 ns ( 25.15 % )
Info: th for register "SimTxEnReg" (data pin = "CPU_SDI", clock pin = "CPU_SCK") is 0.600 ns
    Info: + Longest clock path from clock "CPU_SCK" to destination register is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 10; CLK Node = 'CPU_SCK'
        Info: 2: + IC(1.600 ns) + CELL(2.500 ns) = 6.200 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
        Info: Total cell delay = 4.600 ns ( 74.19 % )
        Info: Total interconnect delay = 1.600 ns ( 25.81 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_33; Fanout = 17; PIN Node = 'CPU_SDI'
        Info: 2: + IC(2.100 ns) + CELL(3.300 ns) = 6.900 ns; Loc. = LC6; Fanout = 3; REG Node = 'SimTxEnReg'
        Info: Total cell delay = 4.800 ns ( 69.57 % )
        Info: Total interconnect delay = 2.100 ns ( 30.43 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 182 megabytes
    Info: Processing ended: Thu Feb 13 22:17:28 2025
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


