module dac_ctrl#(
parameter DAC_7811_NUM = 40,
parameter DAC_5444_NUM = 8
)(
input wire clk,spi_clk,reset,


input wire     [7:0]   config_chn,

input  wire              config_data_wr,
input  wire      [7:0]   config_item,
input  wire      [15:0]  config_data,

input wire             config_ramwr,
input wire     [15:0]  config_ramaddr,
input wire     [15:0]  config_ramdata,




input wire [31:0]   config_cycle,
input wire config_update,
output wire [DAC_7811_NUM+DAC_5444_NUM-1:0] sdin,sync,sclk,
output wire spi_clk_div,
input wire qt_clr_i,

input wire ext_trig_en,

input wire ext_trig_in
);


localparam DAC_7811 = 0;
localparam DAC_5444 = 1;

//localparam TRIG_NUM = 5;//
localparam TRIG_NUM = 3;//

wire w_frm_updt = (ext_trig_en==1'b0)?ext_trig_in :w_inner_trig;


reg r_frame_en;
always @(posedge clk or posedge reset) begin
  if(reset) 
  	r_frame_en <=  1'b1;
  else if(config_update)
    r_frame_en   <= 1'b1;
end


//------------处理控制逻辑
//帧同步处理
/*
reg r_d1,r_d2;

always@(posedge clk or posedge reset) begin
  if(reset) begin
    r_d1    <= 0;
    r_d2    <= 0;
  end
  else begin
    r_d1    <=  w_frm_updt;
    r_d2    <=  r_d1;
  end
end
*/
reg [15:0] r_dly;

always@(posedge clk or posedge reset) begin
  if(reset) 
    r_dly    <= 0;
  else 
    r_dly    <=  {r_dly[14:0],w_frm_updt};
end


wire w_frame_r = ~r_dly[4]&r_dly[0];
wire w_frame_f = ~r_dly[0]&r_dly[4];
wire w_frame_sig = ~r_dly[3]&r_dly[4];

reg [3:0] r_trig_cnt;
always@(posedge clk or posedge reset) begin
  if(reset) 
    r_trig_cnt    <= 0;
  else if(w_frame_sig) begin
  	if(r_trig_cnt==TRIG_NUM-1)
      r_trig_cnt    <= 0;
    else
      r_trig_cnt    <=  r_trig_cnt+1'b1;
  end
end



//wire w_trig_en = (r_trig_cnt==0)?1'b1:1'b0;

//wire w_frame_trig = (r_trig_cnt==0)?w_frame_r:1'b0; 
wire w_frame_trig = w_frame_f;


reg r_spi_clk;
always @(posedge spi_clk or posedge reset) begin
  if(reset) 
  	r_spi_clk <=  1'b0;
  else 
   r_spi_clk   <= !r_spi_clk;
end
assign spi_clk_div = spi_clk;//r_spi_clk;


wire w_inner_trig;
frame_config frm_cfg_inst
(
  .clk(clk),.reset(reset),
  .config_cycle(config_cycle),.config_en(r_frame_en),.config_update(config_update),
  .frame_update(w_inner_trig)
);




/*
micro_oled_spi_ctrl dac_spi_inst(
					.clk (clk),  .reset  (reset),
					  //dac
					.spi_clk(spi_clk),
					.sdin(sdin[0]), .sclk (sclk[0]), .sync (sync[0]),
					  //配置RAM
					.chn_num (0), .config_chn (config_chn), 
					.config_ramaddr (config_ramaddr), .config_ramdata (config_ramdata), .config_ramwr (config_ramwr), 
					//配置波形信息
					//开始地址  
					.config_item (config_item), .config_data (config_data), .config_data_wr (config_data_wr), 
					  //数据帧信号
					.single_done_o(),
					.frame_update(w_frm_updt),.qt_clr(qt_clr_i), .adc_type(DAC_7811)
			);	
	

*/

/*
ext_trig_gen #(.TRIG_PRD(83325*2),.TRIG_WID(694*2)
)trig_gen_inst(
  .clk(spi_clk),.reset(reset),
  .ext_trig_en(ext_trig_in),
  .ext_trig_o(w_inner_trigg)
);
*/

localparam TIRG_PRD = 166650;//+50;
localparam TRIG_WID = 694;
//注意100M时钟，25M SPI ,因此这个值必须是4的倍数
localparam TIRG_DIV = 2;

/*
ext_trig_gen #(.TRIG_PRD(TIRG_PRD*TIRG_DIV),.TRIG_WID(TRIG_WID*TIRG_DIV)
)trig_gen_inst(
  .clk(clk),.reset(reset),
  .ext_trig_en(ext_trig_in),
  .ext_trig_o(w_inner_trigg)
);

ext_trig_frame #(.TRIG_TIME(1388),.TRIG_WID(100),.TRIG_IGNO(5)
	 )trig_cfg_inst(
					  .clk(clk),.reset(reset),
					  .ext_trig_in(w_inner_trigg),
					  .frame_update(w_frm_updt)
					);

*/
generate
	genvar i;

	  //for (i = 0; i < DAC_7811_NUM; i = i + 1)begin: dac_7811
	  for (i = 0; i < 15; i = i + 1)begin: dac_7811
	    //dac5444_50m inst_dac5444_0 (
	    micro_oled_spi_ctrl dac_spi_inst(
					.clk (clk),  .reset  (reset),
					  //dac
					.spi_clk(spi_clk),
					.sdin(sdin[i]), .sclk (sclk[i]), .sync (sync[i]),
					  //配置RAM
					.chn_num (i), .config_chn (config_chn), 
					.config_ramaddr (config_ramaddr), .config_ramdata (config_ramdata), .config_ramwr (config_ramwr), 
					//配置波形信息
					//开始地址  
					.config_item (config_item), .config_data (config_data), .config_data_wr (config_data_wr), 
					  //数据帧信号
					.single_done_o(),.ram_rd_upd(config_update),
					.frame_update(w_frame_f),.trig_update(w_frame_f),
					.qt_clr(qt_clr_i), .adc_type(DAC_7811)
			);						
									
									
	  end
	  
	  for (i = DAC_7811_NUM; i < DAC_7811_NUM+DAC_5444_NUM; i = i + 1)begin: dac_5444
	    //dac5444_50m inst_dac5444_0 (
	    micro_oled_spi_ctrl dac_spi_inst(
					.clk (clk),  .reset  (reset),
					  //dac
					.spi_clk(spi_clk),
					.sdin(sdin[i]), .sclk (sclk[i]), .sync (sync[i]),
					  //配置RAM
					.chn_num (i), .config_chn (config_chn), 
					.config_ramaddr (config_ramaddr), .config_ramdata (config_ramdata), .config_ramwr (config_ramwr), 
					//配置波形信息
					//开始地址  
					.config_item (config_item), .config_data (config_data), .config_data_wr (config_data_wr), 
					  //数据帧信号
					.single_done_o(),.ram_rd_upd(config_update),
					.frame_update(w_frame_f),.trig_update(w_frame_f),.qt_clr(qt_clr_i), .adc_type(DAC_5444)
			);						
									
									
	  end
	  

endgenerate





endmodule