Xilinx Xilinx Zync7000 XC7Z007S 1.0 Zync 7000 Xilinx 8 32 OCM-DDR OCM-DDR OCM-DDR OCM-DDR 0x00000000 0 0x00040000 registers DDR-SCU DDR-SCU DDR-SCU DDR-SCU 0x00040000 0 0x00040000 registers DDR-1 DDR-1 DDR-1 DDR-1 0x00080000 0 0x00080000 registers DDR-2 DDR-2 DDR-2 DDR-2 0x00100000 0 0x3FF00000 registers PL-0 PL-0 PL-0 PL-0 0x40000000 0 0x40000000 registers PL-1 PL-1 PL-1 PL-1 0x80000000 0 0x40000000 registers IOP IOP IOP IOP 0xE0000000 0 0x00300000 registers UART0 UART Controllers 0 IOP UART 0xE0000000 0 0x00001000 registers UART1 UART Controllers 1 IOP UART 0xE0001000 0 0x00001000 registers USB0 USB Controllers 0 IOP USB 0xE0002000 0 0x00001000 registers USB1 USB Controllers 1 IOP USB 0xE0003000 0 0x00001000 registers I2C0 I2C Controllers 0 IOP I2C 0xE0004000 0 0x00001000 registers I2C1 I2C Controllers 1 IOP I2C 0xE0005000 0 0x00001000 registers SPI0 SPI Controllers 0 IOP SPI 0xE0006000 0 0x00001000 registers SPI1 SPI Controllers 1 IOP SPI 0xE0007000 0 0x00001000 registers CAN0 CAN Controllers 0 IOP CAN 0xE0008000 0 0x00001000 registers CAN1 CAN Controllers 1 IOP CAN 0xE0009000 0 0x00001000 registers GPIO GPIO Controllers IOP GPIO 0xE000A000 0 0x00001000 registers ETH0 ETH Controllers 0 IOP ETH 0xE000B000 0 0x00001000 registers ETH1 ETH Controllers 0 IOP ETH 0xE000C000 0 0x00001000 registers Quad-SPI Quad-SPI Controllers IOP SPI 0xE000D000 0 0x00001000 registers SMC Static Memory Controller (SMC) IOP SMC 0xE000E000 0 0x00001000 registers SDIO0 SDIO Controller 0 IOP SDIO 0xE0100000 0 0x00001000 registers SDIO1 SDIO Controller 1 IOP SDIO 0xE0101000 0 0x00001000 registers SDIO0 SD/SDIO Controller 0 SDIO SDIO0_ 0xE0100000 0 0xFF registers DS_ADDR System DMA Address Register 0 32 read-write 0 0xFFFFFFFF DS_ADDR no description available 0 32 read-write BLK_ATT Block Attributes 0x4 32 read-write 0 0xFFFFFFFF BLKSIZE Number of bytes to be transferred 0 12 read-write SDMABUFSIZE These bits specify the size of contiguous buffer in the system memory. 12 3 read-write 000 4KB (Detects A11 Carry out) #000 001 8KB (Detects A12 Carry out) #001 010 16KB (Detects A13 Carry out) #010 011 32KB (Detects A14 Carry out) #011 100 64KB (Detects A15 Carry out) #100 101 128KB (Detects A16 Carry out) #101 110 256KB (Detects A17 Carry out) #110 111 512KB (Detects A18 Carry out) #111 BLKCNT Number of blocks to be transferred 16 16 read-write CMD_ARG Command Argument 0x8 32 read-write 0 0xFFFFFFFF CMDARG Command Argument 0 32 read-write CMD_XFR_TYP Command Transfer Type 0xC 32 read-write 0 0xFFFFFFFF DMAEN If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh). 0 1 read-write BCEN This bit is used to enable the Block count register, which is only relevant for multiple block transfers. 1 1 read-write AC12EN When this bit is set to 1, the HC shall issue CMD12 automatically when last block transfer is completed. 2 1 read-write DTDSEL This bit defines the direction of DAT line data transfers. 4 1 read-write MSBSEL This bit enables multiple block DAT line data transfers. 5 1 read-write RSPTYP Response Type Select 16 2 read-write 00 No Response #00 01 Response Length 136 #01 10 Response Length 48 #10 11 Response Length 48, check Busy after response #11 CCCEN Command CRC Check Enable 19 1 read-write 1 Enable #1 0 Disable #0 CICEN Command Index Check Enable 20 1 read-write 1 Enable #1 0 Disable #0 DPSEL Data Present Select 21 1 read-write 1 Data Present #1 0 No Data Present #0 CMDTYP Command Type 22 2 read-write 11 Abort CMD12, CMD52 for writing I/O Abort in CCCR #11 10 Resume CMD52 for writing Function Select in CCCR #10 01 Suspend CMD52 for writing Bus Suspend in CCCR #01 00 Normal Other commands #00 CMDINX Command Index 24 6 read-write CMD_RSP0 Command Response0 0x10 32 read-only 0 0xFFFFFFFF CMDRSP0 Command Response 0 0 32 read-only CMD_RSP1 Command Response1 0x14 32 read-only 0 0xFFFFFFFF CMDRSP1 Command Response 1 0 32 read-only CMD_RSP2 Command Response2 0x18 32 read-only 0 0xFFFFFFFF CMDRSP2 Command Response 2 0 32 read-only CMD_RSP3 Command Response3 0x1C 32 read-only 0 0xFFFFFFFF CMDRSP3 Command Response 3 0 32 read-only BUFF_DATA_PORT Data Buffer Access Port 0x20 32 read-write 0 0xFFFFFFFF DATCONT Data Content 0 32 read-write PRES_STATE Present State 0x24 32 read-only 0x8080 0xFFFFFFFF CIHB Command Inhibit (CMD) 0 1 read-only 1 Cannot issue command #1 0 Can issue command using only CMD line #0 CDIHB Command Inhibit (DATA) 1 1 read-only 1 Cannot issue command which uses the DATA line #1 0 Can issue command which uses the DATA line #0 DLA Data Line Active 2 1 read-only 1 DATA Line Active #1 0 DATA Line Inactive #0 WTA Write Transfer Active 8 1 read-only 1 Transferring data #1 0 No valid data #0 RTA Read Transfer Active 9 1 read-only 1 Transferring data #1 0 No valid data #0 BWEN Buffer Write Enable 10 1 read-only 1 Write enable #1 0 Write disable #0 BREN Buffer Read Enable 11 1 read-only 1 Read enable #1 0 Read disable #0 CINST Card Inserted 16 1 read-only 1 Card Inserted #1 0 Power on Reset or No Card #0 CSS Card State Stable 17 1 read-only 1 No Card or Inserted #1 0 Reset of Debouncing #0 CDPL Card Detect Pin Level 18 1 read-only 1 Card present (CD_B = 0) #1 0 No card present (CD_B = 1) #0 WPSPL Write Protect Switch Pin Level 19 1 read-only 1 Write enabled (WP = 0) #1 0 Write protected (WP = 1) #0 DLSL DATA[3:0] Line Signal Level 20 4 read-only CLSL CMD Line Signal Level 24 1 read-only PROT_CTRL Protocol Control 0x28 32 read-write 0 0xFFFFFFFF LCTL LED Control 0 1 read-write 1 LED on #1 0 LED off #0 DTW Data Transfer Width 1 1 read-write 1 4-bit mode #1 0 1-bit mode #0 HSEN High Speed Enable 2 1 read-write 1 High speed mode #1 0 Normal speed mode #0 DMASEL DMA select 3 2 read-write 11 64-bit Address ADMA2 is selected #11 10 32-bit Address ADMA2 is selected #10 01 32-bit Address ADMA1 is selected #01 00 SDMA is selected #00 EMODE Endian Mode 4 2 read-write 00 Big Endian Mode #00 01 Half Word Big Endian Mode #01 10 Little Endian Mode #10 CDTL Card Detect Test Level 6 1 read-write 1 Card Detect Test Level is 1, card inserted #1 0 Card Detect Test Level is 0, no card inserted #0 CDSS Card Detect Signal Selection 7 1 read-write 1 Card Detection Test Level is selected (for test purpose). #1 0 Card Detection Level is selected (for normal purpose). #0 SDBUSPOW SD Bus Power 8 1 read-write 0 Power off #0 0 Power on #0 SDBUSVSEL SD Bus Voltage select 9 3 read-write 111 3.3 Flattop #111 110 3.0 V(Typ.) #110 101 1.8 V(Typ.) #101 SABGREQ Stop At Block Gap Request 16 1 read-write 1 Stop #1 0 Transfer #0 CREQ Continue Request 17 1 read-write 1 Restart #1 0 No effect #0 RWCTL Read Wait Control 18 1 read-write 1 Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set #1 0 Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set #0 IABG Interrupt At Block Gap 19 1 read-write 1 Enabled #1 0 Disabled #0 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write 1 Enable #1 0 Disable #0 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write 1 Enable #1 0 Disable #0 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write 1 Enable #1 0 Disable #0 SYS_CTRL System Control 0x2C 32 read-write 0 0xFFFFFFFF ICEN Internal clock enable 0 1 read-write 0 Stop #0 1 Oscillate #1 ICSTA Internal clock stable 1 1 read-write 0 Not Ready #0 1 Ready #1 SDCEN SD clock enable 2 1 read-write 0 Disable #0 1 Enable #1 SDCLKFS SDCLK Frequency Select 8 8 read-write 1/256 Base clock divided by 256 0x80 1/128 Base clock divided by 128 0x40 1/64 Base clock divided by 64 0x20 1/32 Base clock divided by 32 0x10 1/16 Base clock divided by 16 0x08 1/8 Base clock divided by 8 0x04 1/4 Base clock divided by 4 0x02 1/2 Base clock divided by 2 0x01 1 Base clock 0x00 DTOCV Data Timeout Counter Value 16 4 read-write 1111 SDCLK x 2 28 #1111 1110 SDCLK x 2 2 7 #1110 0001 SDCLK x 2 14 #0001 0000 SDCLK x 2 1 3 #0000 RSTA Software Reset For ALL 24 1 read-write 1 Reset #1 0 Work #0 RSTC Software Reset For CMD Line 25 1 read-write 1 Reset #1 0 Work #0 RSTD Software Reset For DATA Line 26 1 read-write 1 Reset #1 0 Work #0 INT_STATUS Interrupt Status 0x30 32 read-write 0 0xFFFFFFFF CC Command Complete 0 1 read-write 1 Command complete #1 0 Command not complete #0 TC Transfer Complete 1 1 read-write 1 Transfer complete #1 0 Transfer not complete #0 BGE Block Gap Event 2 1 read-write 1 Transaction stopped at block gap #1 0 No block gap event #0 DINT DMA Interrupt 3 1 read-write 1 DMA Interrupt is generated #1 0 No DMA Interrupt #0 BWR Buffer Write Ready 4 1 read-write 1 Ready to write buffer: #1 0 Not ready to write buffer #0 BRR Buffer Read Ready 5 1 read-write 1 Ready to read buffer #1 0 Not ready to read buffer #0 CINS Card Insertion 6 1 read-write 1 Card inserted #1 0 Card state unstable or removed #0 CRM Card Removal 7 1 read-write 1 Card removed #1 0 Card state unstable or inserted #0 CINT Card Interrupt 8 1 read-write 1 Generate Card Interrupt #1 0 No Card Interrupt #0 BAR Boot ack received 9 1 read-write 1 Boot ack is received #1 0 Boot ack is not received #0 BTI Boot terminate interrupt 10 1 read-write 1 Boot operation is terminated #1 0 Boot operation is not terminated #0 EI Error interrupt 15 1 read-write 1 Error #1 0 No Error #0 CTOE Command Timeout Error 16 1 read-write 1 Time out #1 0 No Error #0 CCE Command CRC Error 17 1 read-write 1 CRC Error Generated. #1 0 No Error #0 CEBE Command End Bit Error 18 1 read-write 1 End Bit Error Generated #1 0 No Error #0 CIE Command Index Error 19 1 read-write 1 Error #1 0 No Error #0 DTOE Data Timeout Error 20 1 read-write 1 Time out #1 0 No Error #0 DCE Data CRC Error 21 1 read-write 1 Error #1 0 No Error #0 DEBE Data End Bit Error 22 1 read-write 1 Error #1 0 No Error #0 CLE Current Limit Error 23 1 read-write 1 Power fail #1 0 No Error #0 AC12E Auto CMD12 Error 24 1 read-write 1 Error #1 0 No Error #0 ADMAE ADMA Error 25 1 read-write 1 Error #1 0 No Error #0 TRE Target Response Error 28 1 read-write 1 Error #1 0 No Error #0 CAES CEATA Error Status 29 1 read-write 1 Error #1 0 No Error #0 INT_STATUS_EN Interrupt Status Enable 0x34 32 read-write 0 0xFFFFFFFF CCSEN Command Complete Status Enable 0 1 read-write 1 Enabled #1 0 Masked #0 TCSEN Transfer Complete Status Enable 1 1 read-write 1 Enabled #1 0 Masked #0 BGESEN Block Gap Event Status Enable 2 1 read-write 1 Enabled #1 0 Masked #0 DINTSEN DMA Interrupt Status Enable 3 1 read-write 1 Enabled #1 0 Masked #0 BWRSEN Buffer Write Ready Status Enable 4 1 read-write 1 Enabled #1 0 Masked #0 BRRSEN Buffer Read Ready Status Enable 5 1 read-write 1 Enabled #1 0 Masked #0 CINSSEN Card Insertion Status Enable 6 1 read-write 1 Enabled #1 0 Masked #0 CRMSEN Card Removal Status Enable 7 1 read-write 1 Enabled #1 0 Masked #0 CINTSEN Card Interrupt Status Enable 8 1 read-write 1 Enabled #1 0 Masked #0 BAEN Boot ACK Receive Enable 9 1 read-write 1 Enabled #1 0 Masked #0 BTIEN Boot Terminate Interrupt Enable 10 1 read-write 1 Enabled #1 0 Masked #0 CTOESEN Command Timeout Error Status Enable 16 1 read-write 1 Enabled #1 0 Masked #0 CCESEN Command CRC Error Status Enable 17 1 read-write 1 Enabled #1 0 Masked #0 CEBESEN Command End Bit Error Status Enable 18 1 read-write 1 Enabled #1 0 Masked #0 CIESEN Command Index Error Status Enable 19 1 read-write 1 Enabled #1 0 Masked #0 DTOESEN Data Timeout Error Status Enable 20 1 read-write 1 Enabled #1 0 Masked #0 DCESEN Data CRC Error Status Enable 21 1 read-write 1 Enabled #1 0 Masked #0 DEBESEN Data End Bit Error Status Enable 22 1 read-write 1 Enabled #1 0 Masked #0 CLESEN Current Limit Error Status Enable 23 1 read-write 1 Enabled #1 0 Masked #0 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write 1 Enabled #1 0 Masked #0 DMAESEN ADMA Error Status Enable 25 1 read-write 1 Enabled #1 0 Masked #0 TRESEN Target Response Error Status Enable 28 1 read-write 1 Enabled #1 0 Masked #0 CAESEN CEATA Error Status Enable 29 1 read-write 1 Enabled #1 0 Masked #0 INT_SIGNAL_EN Interrupt Signal Enable 0x38 32 read-write 0 0xFFFFFFFF CCIEN Command Complete Interrupt Enable 0 1 read-write 1 Enabled #1 0 Masked #0 TCIEN Transfer Complete Interrupt Enable 1 1 read-write 1 Enabled #1 0 Masked #0 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write 1 Enabled #1 0 Masked #0 DINTIEN DMA Interrupt Enable 3 1 read-write 1 Enabled #1 0 Masked #0 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write 1 Enabled #1 0 Masked #0 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write 1 Enabled #1 0 Masked #0 CINSIEN Card Insertion Interrupt Enable 6 1 read-write 1 Enabled #1 0 Masked #0 CRMIEN Card Removal Interrupt Enable 7 1 read-write 1 Enabled #1 0 Masked #0 CINTIEN Card Interrupt Interrupt Enable 8 1 read-write 1 Enabled #1 0 Masked #0 BARIEN Boot ACK Receive Signal Interrupt Enable 9 1 read-write 1 Enabled #1 0 Masked #0 BTIEN Boot terminate Interrupt Enable 10 1 read-write 1 Enabled #1 0 Masked #0 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write 1 Enabled #1 0 Masked #0 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write 1 Enabled #1 0 Masked #0 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write 1 Enabled #1 0 Masked #0 CIEIEN Command Index Error Interrupt Enable 19 1 read-write 1 Enabled #1 0 Masked #0 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write 1 Enabled #1 0 Masked #0 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write 1 Enabled #1 0 Masked #0 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write 1 Enabled #1 0 Masked #0 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write 1 Enabled #1 0 Masked #0 DMAEIEN ADMA Error Interrupt Enable 25 1 read-write 1 Enable #1 0 Masked #0 TREIEN Target Response Error Interrupt Enable 28 1 read-write 1 Enable #1 0 Masked #0 CEIEN CEATA Error Interrupt Enable 29 1 read-write 1 Enable #1 0 Masked #0 AUTOCMD12_ERR_STATUS Auto CMD12 Error Status 0x3C 32 read-write 0 0xFFFFFFFF AC12NE Auto CMD12 Not Executed 0 1 read-only 1 Not executed #1 0 Executed #0 AC12TOE Auto CMD12 / 23 Timeout Error 1 1 read-only 1 Time out #1 0 No error #0 AC12CE Auto CMD12 / 23 CRC Error 2 1 read-only 1 CRC Error Met in Auto CMD12/23 Response #1 0 No CRC error #0 AC12EBE Auto CMD12 / 23 End Bit Error 3 1 read-only 1 End Bit Error Generated #1 0 No error #0 AC12IE Auto CMD12 / 23 Index Error 4 1 read-only 1 Error, the CMD index in response is not CMD12/23 #1 0 No error #0 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only 1 Not Issued #1 0 No error #0 EXECUTE_TUNING Execute Tuning 22 1 read-write SMP_CLK_SEL Sample Clock Select 23 1 read-write 1 Tuned clock is used to sample data #1 0 Fixed clock is used to sample data #0 HOST_CTRL_CAP Host Controller Capabilities 0x40 32 read-only 0x69EC0080 0xFFFFFFFF TIMEOUT_CLOCK_UNIT This bit shows the unit of base clock frequency used to detect Data Timeout Error. 7 1 read-only MHz MHz #1 kHz kHz #0 MBL Max Block Length 16 2 read-only 00 512 bytes #00 01 1024 bytes #01 10 2048 bytes #10 11 4096 bytes #11 EXTMBUS Extended Media Bus Support 18 1 read-only 1 Extended Media Bus Supported #1 0 Extended Media Bus not Supported #0 ADMA2S ADMA2 Support 19 1 read-only 1 Advanced DMA2 Supported #1 0 Advanced DMA2 Not supported #0 HSS High Speed Support 21 1 read-only 1 High Speed Supported #1 0 High Speed Not Supported #0 DMAS SDMA Support 22 1 read-only 1 SDMA Supported #1 0 SDMA not supported #0 SRS Suspend / Resume Support 23 1 read-only 1 Supported #1 0 Not supported #0 VS33 Voltage Support 3.3V 24 1 read-only 1 3.3V supported #1 0 3.3V not supported #0 VS30 Voltage Support 3.0 V 25 1 read-only 1 3.0V supported #1 0 3.0V not supported #0 VS18 Voltage Support 1.8 V 26 1 read-only 1 1.8V supported #1 0 1.8V not supported #0 INTMODE Interrupt mode 27 1 read-only 1 Supported #1 0 Not supported #0 64BITSBS 64-bit System Bus Support 28 1 read-only 1 Supported #1 0 Not supported #0 SPIMODE SPI Mode 29 1 read-only 1 Supported #1 0 Not supported #0 SPIBMODE SPI Block Mode 30 1 read-only 1 Supported #1 0 Not supported #0 MAX_CUR_CAP Maximum current capabilities 0x48 32 read-write 0x00000001 0xFFFFFFFF MC3V3 Maximum Current for 3.3V 0 8 read-only MC3V0 Maximum Current for 3.0V 8 8 read-only MC1V8 Maximum Current for 1.8V 16 8 read-only FORCE_EVENT Force Event 0x50 32 read-write 0 0xFFFFFFFF FEVTAC12NE Force Event Auto Command 12 Not Executed 0 1 write-only FEVTAC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only FEVTAC12CE Force Event Auto Command 12 CRC Error 2 1 write-only FEVTAC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only FEVTAC12IE Force Event Auto Command 12 Index Error 4 1 write-only FEVTCNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only FEVTCTOE Force Event Command Time Out Error 16 1 write-only FEVTCCE Force Event Command CRC Error 17 1 write-only FEVTCEBE Force Event Command End Bit Error 18 1 write-only FEVTCIE Force Event Command Index Error 19 1 write-only FEVTDTOE Force Event Data Time Out Error 20 1 write-only FEVTDCE Force Event Data CRC Error 21 1 write-only FEVTDEBE Force Event Data End Bit Error 22 1 write-only FEVTCLE Force Event Current Limit Error 23 1 write-only FEVTAC12E Force Event Auto Command 12 Error 24 1 write-only FEVTDMAE Force Event ADMA Error 25 1 write-only FEVTTRE Force Target Response Error 28 1 write-only FEVTCAE Force Event for CEATA Error 29 1 write-only FEVTVSES Force Event Vendor Specific Error Status 30 2 write-only ADMA_ERR_STATUS ADMA Error Status Register 0x54 32 read-only 0 0xFFFFFFFF ADMAES ADMA Error State (when ADMA Error is occurred) 0 2 read-only 00 ST_STOP (Stop DMA) Points next of the error descriptor #00 01 ST_FDS (Fetch Descriptor) Points the error descriptor #01 10 Never set this state (Not used) #10 11 ST_TFR (Transfer Data) Points the next of the error descriptor #11 ADMALME ADMA Length Mismatch Error 2 1 read-only 1 Error #1 0 No Error #0 ADMA_SYS_ADDR ADMA System Address 0x58 32 read-write 0 0xFFFFFFFF ADS_ADDR ADMA System Address 0 32 read-write BOOT_TMOUT_CTRL Boot Timeout Control 0x60 32 read-write 0 0xFFFFFFFF BDT_CNT Boot Data Timeout Counter Value 0 32 read-write DBG_SEL Debug selection 0x64 32 write-only 0 0xFFFFFFFF DBG_SEL no description available 0 1 read-only SPI_INT_SUP SPI Interrupt Support 0xF0 32 read-write 0 0xFFFFFFFF SPI_INT_SUP no description available 0 8 read-write HOST_VER Slot Interrupt Status and Host Controller Register 0xFC 32 read-only 0x89010000 0xFFFFFFFF INT_SIG_ALL_SLOTS Interrupt signal for Each Slot 0 8 read-only SPEC_VER_NUM Specification version number 16 8 read-only 00 SD Host Specification version 1.0 #00 01 SD Host Specification version 2.00 including only the feature of the Test Register #01 VEND_VER_NUM Vendor Version Number 24 8 read-only SDIO1 SD/SDIO Controller 1 SDIO SDIO1_ 0xE0101000 0 0xFF registers DS_ADDR System DMA Address Register 0 32 read-write 0 0xFFFFFFFF DS_ADDR no description available 0 32 read-write BLK_ATT Block Attributes 0x4 32 read-write 0 0xFFFFFFFF BLKSIZE Number of bytes to be transferred 0 12 read-write SDMABUFSIZE These bits specify the size of contiguous buffer in the system memory. 12 3 read-write 000 4KB (Detects A11 Carry out) #000 001 8KB (Detects A12 Carry out) #001 010 16KB (Detects A13 Carry out) #010 011 32KB (Detects A14 Carry out) #011 100 64KB (Detects A15 Carry out) #100 101 128KB (Detects A16 Carry out) #101 110 256KB (Detects A17 Carry out) #110 111 512KB (Detects A18 Carry out) #111 BLKCNT Number of blocks to be transferred 16 16 read-write CMD_ARG Command Argument 0x8 32 read-write 0 0xFFFFFFFF CMDARG Command Argument 0 32 read-write CMD_XFR_TYP Command Transfer Type 0xC 32 read-write 0 0xFFFFFFFF DMAEN If this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of Command register (00Fh). 0 1 read-write BCEN This bit is used to enable the Block count register, which is only relevant for multiple block transfers. 1 1 read-write AC12EN When this bit is set to 1, the HC shall issue CMD12 automatically when last block transfer is completed. 2 1 read-write DTDSEL This bit defines the direction of DAT line data transfers. 4 1 read-write MSBSEL This bit enables multiple block DAT line data transfers. 5 1 read-write RSPTYP Response Type Select 16 2 read-write 00 No Response #00 01 Response Length 136 #01 10 Response Length 48 #10 11 Response Length 48, check Busy after response #11 CCCEN Command CRC Check Enable 19 1 read-write 1 Enable #1 0 Disable #0 CICEN Command Index Check Enable 20 1 read-write 1 Enable #1 0 Disable #0 DPSEL Data Present Select 21 1 read-write 1 Data Present #1 0 No Data Present #0 CMDTYP Command Type 22 2 read-write 11 Abort CMD12, CMD52 for writing I/O Abort in CCCR #11 10 Resume CMD52 for writing Function Select in CCCR #10 01 Suspend CMD52 for writing Bus Suspend in CCCR #01 00 Normal Other commands #00 CMDINX Command Index 24 6 read-write CMD_RSP0 Command Response0 0x10 32 read-only 0 0xFFFFFFFF CMDRSP0 Command Response 0 0 32 read-only CMD_RSP1 Command Response1 0x14 32 read-only 0 0xFFFFFFFF CMDRSP1 Command Response 1 0 32 read-only CMD_RSP2 Command Response2 0x18 32 read-only 0 0xFFFFFFFF CMDRSP2 Command Response 2 0 32 read-only CMD_RSP3 Command Response3 0x1C 32 read-only 0 0xFFFFFFFF CMDRSP3 Command Response 3 0 32 read-only BUFF_DATA_PORT Data Buffer Access Port 0x20 32 read-write 0 0xFFFFFFFF DATCONT Data Content 0 32 read-write PRES_STATE Present State 0x24 32 read-only 0x8080 0xFFFFFFFF CIHB Command Inhibit (CMD) 0 1 read-only 1 Cannot issue command #1 0 Can issue command using only CMD line #0 CDIHB Command Inhibit (DATA) 1 1 read-only 1 Cannot issue command which uses the DATA line #1 0 Can issue command which uses the DATA line #0 DLA Data Line Active 2 1 read-only 1 DATA Line Active #1 0 DATA Line Inactive #0 WTA Write Transfer Active 8 1 read-only 1 Transferring data #1 0 No valid data #0 RTA Read Transfer Active 9 1 read-only 1 Transferring data #1 0 No valid data #0 BWEN Buffer Write Enable 10 1 read-only 1 Write enable #1 0 Write disable #0 BREN Buffer Read Enable 11 1 read-only 1 Read enable #1 0 Read disable #0 CINST Card Inserted 16 1 read-only 1 Card Inserted #1 0 Power on Reset or No Card #0 CSS Card State Stable 17 1 read-only 1 No Card or Inserted #1 0 Reset of Debouncing #0 CDPL Card Detect Pin Level 18 1 read-only 1 Card present (CD_B = 0) #1 0 No card present (CD_B = 1) #0 WPSPL Write Protect Switch Pin Level 19 1 read-only 1 Write enabled (WP = 0) #1 0 Write protected (WP = 1) #0 DLSL DATA[3:0] Line Signal Level 20 4 read-only CLSL CMD Line Signal Level 24 1 read-only PROT_CTRL Protocol Control 0x28 32 read-write 0 0xFFFFFFFF LCTL LED Control 0 1 read-write 1 LED on #1 0 LED off #0 DTW Data Transfer Width 1 1 read-write 1 4-bit mode #1 0 1-bit mode #0 HSEN High Speed Enable 2 1 read-write 1 High speed mode #1 0 Normal speed mode #0 DMASEL DMA select 3 2 read-write 11 64-bit Address ADMA2 is selected #11 10 32-bit Address ADMA2 is selected #10 01 32-bit Address ADMA1 is selected #01 00 SDMA is selected #00 CDTL Card Detect Test Level 6 1 read-write 1 Card Detect Test Level is 1, card inserted #1 0 Card Detect Test Level is 0, no card inserted #0 CDSS Card Detect Signal Selection 7 1 read-write 1 Card Detection Test Level is selected (for test purpose). #1 0 Card Detection Level is selected (for normal purpose). #0 SDBUSPOW SD Bus Power 8 1 read-write 0 Power off #0 0 Power on #0 SDBUSVSEL SD Bus Voltage select 9 3 read-write 111 3.3 Flattop #111 110 3.0 V(Typ.) #110 101 1.8 V(Typ.) #101 SABGREQ Stop At Block Gap Request 16 1 read-write 1 Stop #1 0 Transfer #0 CREQ Continue Request 17 1 read-write 1 Restart #1 0 No effect #0 RWCTL Read Wait Control 18 1 read-write 1 Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set #1 0 Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set #0 IABG Interrupt At Block Gap 19 1 read-write 1 Enabled #1 0 Disabled #0 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write 1 Enable #1 0 Disable #0 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write 1 Enable #1 0 Disable #0 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write 1 Enable #1 0 Disable #0 SYS_CTRL System Control 0x2C 32 read-write 0 0xFFFFFFFF ICEN Internal clock enable 0 1 read-write 0 Stop #0 1 Oscillate #1 ICSTA Internal clock stable 1 1 read-write 0 Not Ready #0 1 Ready #1 SDCEN SD clock enable 2 1 read-write 0 Disable #0 1 Enable #1 SDCLKFS SDCLK Frequency Select 8 8 read-write 1/256 Base clock divided by 256 0x80 1/128 Base clock divided by 128 0x40 1/64 Base clock divided by 64 0x20 1/32 Base clock divided by 32 0x10 1/16 Base clock divided by 16 0x08 1/8 Base clock divided by 8 0x04 1/4 Base clock divided by 4 0x02 1/2 Base clock divided by 2 0x01 1 Base clock 0x00 DTOCV Data Timeout Counter Value 16 4 read-write 1111 SDCLK x 2 28 #1111 1110 SDCLK x 2 2 7 #1110 0001 SDCLK x 2 14 #0001 0000 SDCLK x 2 1 3 #0000 RSTA Software Reset For ALL 24 1 read-write 1 Reset #1 0 Work #0 RSTC Software Reset For CMD Line 25 1 read-write 1 Reset #1 0 Work #0 RSTD Software Reset For DATA Line 26 1 read-write 1 Reset #1 0 Work #0 INT_STATUS Interrupt Status 0x30 32 read-write 0 0xFFFFFFFF CC Command Complete 0 1 read-write 1 Command complete #1 0 Command not complete #0 TC Transfer Complete 1 1 read-write 1 Transfer complete #1 0 Transfer not complete #0 BGE Block Gap Event 2 1 read-write 1 Transaction stopped at block gap #1 0 No block gap event #0 DINT DMA Interrupt 3 1 read-write 1 DMA Interrupt is generated #1 0 No DMA Interrupt #0 BWR Buffer Write Ready 4 1 read-write 1 Ready to write buffer: #1 0 Not ready to write buffer #0 BRR Buffer Read Ready 5 1 read-write 1 Ready to read buffer #1 0 Not ready to read buffer #0 CINS Card Insertion 6 1 read-write 1 Card inserted #1 0 Card state unstable or removed #0 CRM Card Removal 7 1 read-write 1 Card removed #1 0 Card state unstable or inserted #0 CINT Card Interrupt 8 1 read-write 1 Generate Card Interrupt #1 0 No Card Interrupt #0 BAR Boot ack received 9 1 read-write 1 Boot ack is received #1 0 Boot ack is not received #0 BTI Boot terminate interrupt 10 1 read-write 1 Boot operation is terminated #1 0 Boot operation is not terminated #0 EI Error interrupt 15 1 read-write 1 Error #1 0 No Error #0 CTOE Command Timeout Error 16 1 read-write 1 Time out #1 0 No Error #0 CCE Command CRC Error 17 1 read-write 1 CRC Error Generated. #1 0 No Error #0 CEBE Command End Bit Error 18 1 read-write 1 End Bit Error Generated #1 0 No Error #0 CIE Command Index Error 19 1 read-write 1 Error #1 0 No Error #0 DTOE Data Timeout Error 20 1 read-write 1 Time out #1 0 No Error #0 DCE Data CRC Error 21 1 read-write 1 Error #1 0 No Error #0 DEBE Data End Bit Error 22 1 read-write 1 Error #1 0 No Error #0 CLE Current Limit Error 23 1 read-write 1 Power fail #1 0 No Error #0 AC12E Auto CMD12 Error 24 1 read-write 1 Error #1 0 No Error #0 ADMAE ADMA Error 25 1 read-write 1 Error #1 0 No Error #0 TRE Target Response Error 28 1 read-write 1 Error #1 0 No Error #0 CAES CEATA Error Status 29 1 read-write 1 Error #1 0 No Error #0 INT_STATUS_EN Interrupt Status Enable 0x34 32 read-write 0 0xFFFFFFFF CCSEN Command Complete Status Enable 0 1 read-write 1 Enabled #1 0 Masked #0 TCSEN Transfer Complete Status Enable 1 1 read-write 1 Enabled #1 0 Masked #0 BGESEN Block Gap Event Status Enable 2 1 read-write 1 Enabled #1 0 Masked #0 DINTSEN DMA Interrupt Status Enable 3 1 read-write 1 Enabled #1 0 Masked #0 BWRSEN Buffer Write Ready Status Enable 4 1 read-write 1 Enabled #1 0 Masked #0 BRRSEN Buffer Read Ready Status Enable 5 1 read-write 1 Enabled #1 0 Masked #0 CINSSEN Card Insertion Status Enable 6 1 read-write 1 Enabled #1 0 Masked #0 CRMSEN Card Removal Status Enable 7 1 read-write 1 Enabled #1 0 Masked #0 CINTSEN Card Interrupt Status Enable 8 1 read-write 1 Enabled #1 0 Masked #0 BAEN Boot ACK Receive Enable 9 1 read-write 1 Enabled #1 0 Masked #0 BTIEN Boot Terminate Interrupt Enable 10 1 read-write 1 Enabled #1 0 Masked #0 CTOESEN Command Timeout Error Status Enable 16 1 read-write 1 Enabled #1 0 Masked #0 CCESEN Command CRC Error Status Enable 17 1 read-write 1 Enabled #1 0 Masked #0 CEBESEN Command End Bit Error Status Enable 18 1 read-write 1 Enabled #1 0 Masked #0 CIESEN Command Index Error Status Enable 19 1 read-write 1 Enabled #1 0 Masked #0 DTOESEN Data Timeout Error Status Enable 20 1 read-write 1 Enabled #1 0 Masked #0 DCESEN Data CRC Error Status Enable 21 1 read-write 1 Enabled #1 0 Masked #0 DEBESEN Data End Bit Error Status Enable 22 1 read-write 1 Enabled #1 0 Masked #0 CLESEN Current Limit Error Status Enable 23 1 read-write 1 Enabled #1 0 Masked #0 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write 1 Enabled #1 0 Masked #0 DMAESEN ADMA Error Status Enable 25 1 read-write 1 Enabled #1 0 Masked #0 TRESEN Target Response Error Status Enable 28 1 read-write 1 Enabled #1 0 Masked #0 CAESEN CEATA Error Status Enable 29 1 read-write 1 Enabled #1 0 Masked #0 INT_SIGNAL_EN Interrupt Signal Enable 0x38 32 read-write 0 0xFFFFFFFF CCIEN Command Complete Interrupt Enable 0 1 read-write 1 Enabled #1 0 Masked #0 TCIEN Transfer Complete Interrupt Enable 1 1 read-write 1 Enabled #1 0 Masked #0 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write 1 Enabled #1 0 Masked #0 DINTIEN DMA Interrupt Enable 3 1 read-write 1 Enabled #1 0 Masked #0 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write 1 Enabled #1 0 Masked #0 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write 1 Enabled #1 0 Masked #0 CINSIEN Card Insertion Interrupt Enable 6 1 read-write 1 Enabled #1 0 Masked #0 CRMIEN Card Removal Interrupt Enable 7 1 read-write 1 Enabled #1 0 Masked #0 CINTIEN Card Interrupt Interrupt Enable 8 1 read-write 1 Enabled #1 0 Masked #0 BARIEN Boot ACK Receive Signal Interrupt Enable 9 1 read-write 1 Enabled #1 0 Masked #0 BTIEN Boot terminate Interrupt Enable 10 1 read-write 1 Enabled #1 0 Masked #0 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write 1 Enabled #1 0 Masked #0 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write 1 Enabled #1 0 Masked #0 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write 1 Enabled #1 0 Masked #0 CIEIEN Command Index Error Interrupt Enable 19 1 read-write 1 Enabled #1 0 Masked #0 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write 1 Enabled #1 0 Masked #0 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write 1 Enabled #1 0 Masked #0 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write 1 Enabled #1 0 Masked #0 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write 1 Enabled #1 0 Masked #0 DMAEIEN ADMA Error Interrupt Enable 25 1 read-write 1 Enable #1 0 Masked #0 TREIEN Target Response Error Interrupt Enable 28 1 read-write 1 Enable #1 0 Masked #0 CEIEN CEATA Error Interrupt Enable 29 1 read-write 1 Enable #1 0 Masked #0 AUTOCMD12_ERR_STATUS Auto CMD12 Error Status 0x3C 32 read-write 0 0xFFFFFFFF AC12NE Auto CMD12 Not Executed 0 1 read-only 1 Not executed #1 0 Executed #0 AC12TOE Auto CMD12 / 23 Timeout Error 1 1 read-only 1 Time out #1 0 No error #0 AC12CE Auto CMD12 / 23 CRC Error 2 1 read-only 1 CRC Error Met in Auto CMD12/23 Response #1 0 No CRC error #0 AC12EBE Auto CMD12 / 23 End Bit Error 3 1 read-only 1 End Bit Error Generated #1 0 No error #0 AC12IE Auto CMD12 / 23 Index Error 4 1 read-only 1 Error, the CMD index in response is not CMD12/23 #1 0 No error #0 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only 1 Not Issued #1 0 No error #0 EXECUTE_TUNING Execute Tuning 22 1 read-write SMP_CLK_SEL Sample Clock Select 23 1 read-write 1 Tuned clock is used to sample data #1 0 Fixed clock is used to sample data #0 HOST_CTRL_CAP Host Controller Capabilities 0x40 32 read-only 0x69EC0080 0xFFFFFFFF TIMEOUT_CLOCK_UNIT This bit shows the unit of base clock frequency used to detect Data Timeout Error. 7 1 read-only MHz MHz #1 kHz kHz #0 MBL Max Block Length 16 2 read-only 00 512 bytes #00 01 1024 bytes #01 10 2048 bytes #10 11 4096 bytes #11 EXTMBUS Extended Media Bus Support 18 1 read-only 1 Extended Media Bus Supported #1 0 Extended Media Bus not Supported #0 ADMA2S ADMA2 Support 19 1 read-only 1 Advanced DMA2 Supported #1 0 Advanced DMA2 Not supported #0 HSS High Speed Support 21 1 read-only 1 High Speed Supported #1 0 High Speed Not Supported #0 DMAS SDMA Support 22 1 read-only 1 SDMA Supported #1 0 SDMA not supported #0 SRS Suspend / Resume Support 23 1 read-only 1 Supported #1 0 Not supported #0 VS33 Voltage Support 3.3V 24 1 read-only 1 3.3V supported #1 0 3.3V not supported #0 VS30 Voltage Support 3.0 V 25 1 read-only 1 3.0V supported #1 0 3.0V not supported #0 VS18 Voltage Support 1.8 V 26 1 read-only 1 1.8V supported #1 0 1.8V not supported #0 INTMODE Interrupt mode 27 1 read-only 1 Supported #1 0 Not supported #0 64BITSBS 64-bit System Bus Support 28 1 read-only 1 Supported #1 0 Not supported #0 SPIMODE SPI Mode 29 1 read-only 1 Supported #1 0 Not supported #0 SPIBMODE SPI Block Mode 30 1 read-only 1 Supported #1 0 Not supported #0 MAX_CUR_CAP Maximum current capabilities 0x48 32 read-write 0x00000001 0xFFFFFFFF MC3V3 Maximum Current for 3.3V 0 8 read-only MC3V0 Maximum Current for 3.0V 8 8 read-only MC1V8 Maximum Current for 1.8V 16 8 read-only FORCE_EVENT Force Event 0x50 32 read-write 0 0xFFFFFFFF FEVTAC12NE Force Event Auto Command 12 Not Executed 0 1 write-only FEVTAC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only FEVTAC12CE Force Event Auto Command 12 CRC Error 2 1 write-only FEVTAC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only FEVTAC12IE Force Event Auto Command 12 Index Error 4 1 write-only FEVTCNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only FEVTCTOE Force Event Command Time Out Error 16 1 write-only FEVTCCE Force Event Command CRC Error 17 1 write-only FEVTCEBE Force Event Command End Bit Error 18 1 write-only FEVTCIE Force Event Command Index Error 19 1 write-only FEVTDTOE Force Event Data Time Out Error 20 1 write-only FEVTDCE Force Event Data CRC Error 21 1 write-only FEVTDEBE Force Event Data End Bit Error 22 1 write-only FEVTCLE Force Event Current Limit Error 23 1 write-only FEVTAC12E Force Event Auto Command 12 Error 24 1 write-only FEVTDMAE Force Event ADMA Error 25 1 write-only FEVTTRE Force Target Response Error 28 1 write-only FEVTCAE Force Event for CEATA Error 29 1 write-only FEVTVSES Force Event Vendor Specific Error Status 30 2 write-only ADMA_ERR_STATUS ADMA Error Status Register 0x54 32 read-only 0 0xFFFFFFFF ADMAES ADMA Error State (when ADMA Error is occurred) 0 2 read-only 00 ST_STOP (Stop DMA) Points next of the error descriptor #00 01 ST_FDS (Fetch Descriptor) Points the error descriptor #01 10 Never set this state (Not used) #10 11 ST_TFR (Transfer Data) Points the next of the error descriptor #11 ADMALME ADMA Length Mismatch Error 2 1 read-only 1 Error #1 0 No Error #0 ADMA_SYS_ADDR ADMA System Address 0x58 32 read-write 0 0xFFFFFFFF ADS_ADDR ADMA System Address 0 32 read-write BOOT_TMOUT_CTRL Boot Timeout Control 0x60 32 read-write 0 0xFFFFFFFF BDT_CNT Boot Data Timeout Counter Value 0 32 read-write DBG_SEL Debug selection 0x64 32 write-only 0 0xFFFFFFFF DBG_SEL no description available 0 1 read-only SPI_INT_SUP SPI Interrupt Support 0xF0 32 read-write 0 0xFFFFFFFF SPI_INT_SUP no description available 0 8 read-write HOST_VER Slot Interrupt Status and Host Controller Register 0xFC 32 read-only 0x89010000 0xFFFFFFFF INT_SIG_ALL_SLOTS Interrupt signal for Each Slot 0 8 read-only SPEC_VER_NUM Specification version number 16 8 read-only 00 SD Host Specification version 1.0 #00 01 SD Host Specification version 2.00 including only the feature of the Test Register #01 VEND_VER_NUM Vendor Version Number 24 8 read-only SMC SMC SMC SMC 0xE1000000 0 0x05000000 registers NAND SMC NAND Memory address range SMC NAND_ 0xE1000000 0 0x01000000 registers SRAM_NOR0 SMC SRAM/NOR CS 0 Memory address range SMC SRAM_NOR_ 0xE2000000 0 0x02000000 registers SRAM_NOR1 SMC SRAM/NOR CS 1 Memory address range SMC SRAM_NOR_ 0xE4000000 0 0x02000000 registers SLCR System Level Control Registers SLCR SLCR_ 0xF8000000 0 0xFFF registers SDIO_CLK_CTRL SDIO Ref Clock Control 0x150 32 read-write 0x00001E03 0xFFFFFFFF CLKACT0 SDIO Controller 0 Clock control. 0 1 read-write CLKACT1 SDIO Controller 1 Clock control. 1 1 read-write SRCSEL Select the source used to generate the clock. 4 2 read-write 00 Source for generated clock is IO PLL. #00 01 Source for generated clock is IO PLL. #01 10 Source for generated clock is ARM PLL. #10 11 Source for generated clock is DDR PLL. #11 DIVISOR Provides the divisor used to divide the source clock to generate the required generated clock frequency. 8 6 read-write SDIO_RST_CTRL SDIO Ref Clock Control 0x218 32 read-write 0 0xFFFFFFFF SDIO0_CPU1X_RST SDIO 0 master and slave AMBA interfaces reset. 0 1 read-write 0 - de-assert (no reset) de-assert (no reset) #0 1 - assert (held in reset) assert (held in reset) #1 SDIO1_CPU1X_RST SDIO 1 master and slave AMBA interfaces reset. 1 1 read-write 0 - de-assert (no reset) de-assert (no reset) #0 1 - assert (held in reset) assert (held in reset) #1 SDIO0_REF_RST SDIO 0 reference clock domain reset:. 4 1 read-write 0 - de-assert (no reset) de-assert (no reset) #0 1 - assert (held in reset) assert (held in reset) #1 SDIO1_REF_RST SDIO 1 reference clock domain reset:. 5 1 read-write 0 - de-assert (no reset) de-assert (no reset) #0 1 - assert (held in reset) assert (held in reset) #1 MIO_PIN_09 MIO Pin 9 Control 0x724 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 1 - Quad SPI 1 Flash Memory Clock, Output Quad SPI 1 Flash Memory Clock, Output #1 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 15, Output Trace Port Data Bit 15, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 01 - SRAM/NOR Data Bit 6, Input/Output SRAM/NOR Data Bit 6, Input/Output #01 10 - NAND Flash IO Bit 4, Input/Output NAND Flash IO Bit 4, Input/Output #10 11 - SDIO 1 Power Control, Output SDIO 1 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 9 (bank 0), Input/Output GPIO 9 (bank 0), Input/Output #000 001 - CAN 1 Rx, Input CAN 1 Rx, Input #001 111 - UART 1 RxD, Input UART 1 RxD, Input #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_10 MIO Pin 10 Control 0x728 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 1 - Quad SPI 1 IO Bit 0, Input/Output Quad SPI 1 IO Bit 0, Input/Output #1 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 2, Output Trace Port Data Bit 2, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 01 - SRAM/NOR Data Bit 7, Input/Output SRAM/NOR Data Bit 7, Input/Output #01 10 - NAND Flash IO Bit 5, Input/Output NAND Flash IO Bit 5, Input/Output #10 11 - SDIO 0 Power Control, Output SDIO 0 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 10 (bank 0), Input/Output GPIO 10 (bank 0), Input/Output #000 001 - CAN 0 Rx, Input CAN 0 Rx, Input #001 010 - I2C 0 Serial Clock, Input/Ouput I2C 0 Serial Clock, Input/Ouput #010 011 - PJTAG TDI, Input PJTAG TDI, Input #011 100 - SDIO 1 IO Bit 0, Input/Output SDIO 1 IO Bit 0, Input/Output #100 101 - SPI 1 MOSI, Input/Output SPI 1 MOSI, Input/Output #101 111 - UART 0 RxD, Input UART 0 RxD, Input #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_11 MIO Pin 11 Control 0x72C 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 1 - Quad SPI 1 IO Bit 1, Input/Output Quad SPI 1 IO Bit 1, Input/Output #1 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 3, Output Trace Port Data Bit 3, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 01 - SRAM/NOR Data Bit 4, Input/Output SRAM/NOR Data Bit 4, Input/Output #01 10 - NAND Flash IO Bit 6, Input/Output NAND Flash IO Bit 6, Input/Output #10 11 - SDIO 1 Power Control, Output SDIO 1 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 11 (bank 0), Input/Output GPIO 11 (bank 0), Input/Output #000 001 - CAN 0 Tx, Output CAN 0 Tx, Output #001 010 - I2C 0 Serial Data, Input/Output I2C 0 Serial Data, Input/Output #010 011 - PJTAG TDO, Output PJTAG TDO, Output #011 100 - SDIO 1 Command, Input/Output SDIO 1 Command, Input/Output #100 101 - SPI 1 MISO, Input/Output SPI 1 MISO, Input/Output #101 111 - UART 0 TxD, Output UART 0 TxD, Output #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_12 MIO Pin12 Control 0x730 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 1 - Quad SPI 1 IO Bit 1, Input/Output Quad SPI 1 IO Bit 1, Input/Output #1 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 3, Output Trace Port Data Bit 3, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 01 - SRAM/NOR Data Bit 4, Input/Output SRAM/NOR Data Bit 4, Input/Output #01 10 - NAND Flash IO Bit 6, Input/Output NAND Flash IO Bit 6, Input/Output #10 11 - SDIO 1 SDIO 1 #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 11 (bank 0), Input/Output GPIO 11 (bank 0), Input/Output #000 001 - CAN 0 Tx, Output CAN 0 Tx, Output #001 010 - I2C 0 Serial Data, Input/Output I2C 0 Serial Data, Input/Output #010 011 - PJTAG TDO, Output PJTAG TDO, Output #011 100 - SDIO 1 Command, Input/Output SDIO 1 Command, Input/Output #100 101 - SPI 1 MISO, Input/Output SPI 1 MISO, Input/Output #101 111 - UART 0 TxD, Output UART 0 TxD, Output #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_13 MIO Pin 13 Control 0x734 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 1 - Quad SPI 1 IO Bit 3, Input/Output Quad SPI 1 IO Bit 3, Input/Output #1 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Control Signal, Output Trace Port Control Signal, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 01 - SRAM/NOR Data Bit 5, Input/Output SRAM/NOR Data Bit 5, Input/Output #01 10 - NAND Flash IO Bit 3, Input/Output NAND Flash IO Bit 3, Input/Output #10 11 - SDIO 1 Power Control, Output SDIO 1 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 13 (bank 0), Input/Output GPIO 13 (bank 0), Input/Output #000 001 - CAN 1 Rx, Input CAN 1 Rx, Input #001 010 - I2C 1 Serial Data, Input/Output I2C 1 Serial Data, Input/Output #010 011 - PJTAG TMS, Input PJTAG TMS, Input #011 100 - SDIO 1 IO Bit 1, Input/Output SDIO 1 IO Bit 1, Input/Output #100 101 - SPI 1 Slave Select 0, Input/Output SPI 1 Slave Select 0, Input/Output #101 111 - UART 1 RxD, Input UART 1 RxD, Input #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_14 MIO Pin 14 Control 0x738 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 0, Output Trace Port Data Bit 0, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 10 - NAND Flash Busy, Input/Output NAND Flash Busy, Input #10 11 - SDIO 0 Power Control, Output SDIO 0 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 14 (bank 0), Input/Output GPIO 14 (bank 0), Input/Output #000 001 - CAN 0 Rx, Input CAN 0 Rx, Input #001 010 - I2C 0 Serial Clock, Input/Ouput I2C 0 Serial Clock, Input/Ouput #010 011 - SWDT Clock, Input SWDT Clock, Input #011 100 - SDIO 1 IO Bit 2, Input/Output SDIO 1 IO Bit 2, Input/Output #100 101 - SPI 1 slave select 1, Output SPI 1 slave select 1, Output #101 111 - UART 0 RxD, Input UART 0 RxD, Input #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write MIO_PIN_15 MIO Pin 15 Control 0x73C 32 read-write 0x00001601 0xFFFFFFFF TRI_ENABLE Tri-state enable, active high. 0 1 read-write L0_SEL Level 0 Mux Select 1 1 read-write 0 - Level 1 Mux Level 1 Mux #0 L1_SEL Level 1 Mux Select 2 1 read-write 0 - Level 2 Mux Level 2 Mux #0 1 - Trace Port Data Bit 1, Output Trace Port Data Bit 1, Output #1 L2_SEL Level 2 Mux Select 3 2 read-write 00 - Level 3 Mux Level 3 Mux #00 10 - SRAM/NOR Address Bit 0, Output SRAM/NOR Address Bit 0, Output #10 11 - SDIO 1 Power Control, Output SDIO 1 Power Control, Output #11 L3_SEL Level 3 Mux Select 5 3 read-write 000 - GPIO 15 (bank 0), Input/Output GPIO 15 (bank 0), Input/Output #000 001 - CAN 0 Tx, Output CAN 0 Tx, Output #001 010 - I2C 0 Serial Data, Input/Output I2C 0 Serial Data, Input/Output #010 011 - SWDT Reset, Output SWDT Reset, Output #011 100 - SDIO 1 IO Bit 3, Input/Output SDIO 1 IO Bit 3, Input/Output #100 101 - SPI 1 Slave Select 2, Output SPI 1 Slave Select 2, Output #101 111 - UART 0 TxD, Output UART 0 TxD, Output #111 SPEED Select IO Buffer Edge Rate 8 1 read-write 0 - Slow CMOS edge Slow CMOS edge #0 1 - Fast CMOS edge Fast CMOS edge #1 IO_TYPE Select the IO Buffer Type 9 3 read-write 001 - LVCMOS18 LVCMOS18 #001 010 - LVCMOS25 LVCMOS25 #010 011 - LVCMOS33 LVCMOS33 #011 100 - HSTL HSTL #100 PULLUP Enables Pullup on IO Buffer pin 12 1 read-write DIS_RCVR Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 13 1 read-write SD0_WP_CD_SEL SDIO 0 WP CD select 0x830 32 read-write 0 0xFFFFFFFF SDIO0_WP_SEL SDIO 0 WP Select. 0 6 read-write SDIO0_CD_SEL SDIO 0 CD Select. 16 6 read-write SD1_WP_CD_SEL SDIO 1 WP CD select 0x834 32 read-write 0 0xFFFFFFFF SDIO1_WP_SEL SDIO 1 WP Select. 0 6 read-write SDIO1_CD_SEL SDIO 1 CD Select. 16 6 read-write SLCR_W SLCR write protection lock and security SLCR SLCR_W_ 0xF8000000 0 0x00000100 registers SCL Secure Configuration Lock 0x00 32 read-write 0x00000000 value read-write [31:0] locked all writes to secure configuration registers are ignored. 1 unlocked Secure writes to secure configuration registers are enabled. 0 SLCR_LOCK SLCR Write Protection Lock 0x04 32 write-only 0x00000000 LOCK_KEY Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. read-write [31:0] SLCR_UNLOCK SLCR Write Protection Unlock 0x08 32 write-only 0x00000000 value read-write [31:0] SLCR_LOCKSTA SLCR Write Protection Status 0x0C 32 read-only 0x00000001 value read-write [31:0] locked Registers are not writeable. Any attempt to write to an slcr register is ignored, but reads will return valid register values. 1 unlocked Registers are writeable. Use the slcr.SLCR_LOCK register to lock the slcr registers. 0 CCTRS Clock control and status See Clocks SLCR CCTRS_ 0xF8000100 0 0x00000100 registers 3 4 ARM,DDR,IO %s_PLL_CTRL PLL Control 0x00 32 read-write 0x0001A008 reserved [31:19] read-write 0x0 Reserved. Writes are ignored, read data is zero. PLL_FDIV [18:12] read-write 0x1A Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. reserved [11:5] read-write 0x0 Reserved. Writes are ignored, read data is zero. PLL_BYPASS_FORCE [4] read-write 0x0 Arm PLL Bypass override control: 0 enabled PLL_BYPASS_QUAL = 0:not bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1 bypassed PLL_BYPASS_QUAL = 0:not bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 1: PLL bypassed regardless of the pin strapping. PLL_BYPASS_QUAL [3] read-write 0x1 Select the source for the Arm PLL Bypass Control: 0 controlled by the PLL_BYPASS_FORCE bit, bit4. 1 controlled by the value of the sampled BOOT_MODE pin strapping resistor PLL_BYPASS. This can be read using the BOOT_MODE[4] bit. reserved [2] read-write 0x0 Reserved. Writes are ignored, read data is zero. PLL_PWRDWN [1] read-write 0x0 PLL Power-down control: 0 PLL powered up 1 PLL powered down PLL_RESET [0] read-write 0x0 PLL reset control: de-assert (PLL operating) 0 assert (PLL held in reset) 1 PLL_STATUS PLL Status 0x0C 32 read-only 0x0000003F reserved [31:6] read-only Reserved. Writes are ignored, read data is zero. IO_PLL_STABLE [5:5] read-only IO PLL clock stable status: 0 not locked and not in bypass 1 locked or bypassed DDR_PLL_STABLE [4:4] read-only DDR PLL clock stable status: 0 not locked and not in bypass 1 locked or bypassed ARM_PLL_STABLE [3:3] read-only Arm PLL clock stable status: 0 not locked and not in bypass 1 locked or bypassed IO_PLL_LOCK [2:2] read-only IO PLL lock status: 0 not locked 1 locked DDR_PLL_LOCK [1:1] read-only DDR PLL lock status: 0 not locked 1 locked ARM_PLL_LOCK [0:0] read-only Arm PLL lock status: 0 not locked 1 locked 3 3 ARM,DDR,IO, %s_PLL_CFG PLL Configuration 0x10 32 read-write 0x00177EA0 value read-write [31:0] reserved [31:22] read-write Reserved. Writes are ignored, read data is zero. LOCK_CNT [21:12] read-write Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. PLL_CP [11:8] read-write Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. PLL_RES [7:4] read-write Drive the PLL_RES[3:0] input of the PLL to setthe PLL loop filter resistor control. reserved [3:0] read-write 0x0 Reserved. Writes are ignored, read data is zero. ARM_CLK_CTRL CPU Clock Control 0x20 32 read-write 0x1F000400 reserved [31:29] read-write 0x0 Reserved. Writes are ignored, read data is zero. CPU_PERI_CLKACT [28:28] read-write 0x1 Clock active: 0: Clock is disabled 1:Clock is enabled CPU_1XCLKACT [27:27] read-write 0x1 CPU_1x Clock control: 0 disable locked 1 enable CPU_2XCLKACT [26:26] read-write 0x1 CPU_2x Clock control: 0 disable locked 1 enable CPU_3OR2XCLKACT [25:25] read-write 0x1 CPU_3x2x Clock control: 0 disable locked 1 enable CPU_6OR4XCLKACT [24] read-write 0x1 CPU_6x4x Clock control: 0 disable locked 1 enable reserved [23:14] read-write 0x0 Reserved. Writes are ignored, read data iszero. DIVISOR [13:8] read-write 0x4 Frequency divisor for the CPU clock source. 0 do not use. 1 do not use. 2 divide by 2. 3 divide by 3. 3 3Fh: divide by 63. reserved [7:6] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [5:4] read-write 0x0 Select the source used to generate the CPU clock: 0x0 0x: Arm PLL 10 DDR PLL 11 IO PLL This field is reset by POR only. reserved [3:0] read-write 0x0 Reserved. Writes are ignored, read data is zero. DDR_CLK_CTRL DDR Clock Control 0x24 32 read-write 0x18400003 DDR_2XCLK_DIVISOR [31:26 ] read-write 0x6 Frequency divisor for the ddr_2x clock DDR_3XCLK_DIVISOR [25:20 ] read-write 0x4 Frequency divisor for the ddr_3x clock. (Only even divisors are allowed) reserved [19:2 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DDR_2XCLKACT [1 ] read-write 0x1 DDR_2x Clock control: 0 disable locked 1 enable DDR_3XCLKACT [0 ] read-write 0x1 DDR_3x Clock control: 0 disable locked 1 enable DCI_CLK_CTRL DCI clock control 0x28 32 read-write 0x01E03201 reserved [31:26] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 [25:20] read-write 0x1E Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. reserved [19:14] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR0 [13:8] read-write 0x32 Provides the divisor used to divide the source clock to generate the required generated clock frequency. reserved [7:1] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [0] read-write 0x1 DCI clock control 0 disable locked 1 enable APER_CLK_CTRL AMBA Peripheral Clock Control 0x2C 32 read-write 0x01FFCCCD reserved [31:25] read-write 0x0 Reserved. Writes are ignored, read data is zero. SMC_CPU_1XCLKACT [ 24 ] read-write 0x1 SMC AMBA Clock control 0 disable locked 1 enable LQSPI_CPU_1XCLKACT [ 23 ] read-write 0x1 Quad SPI AMBA Clock control 0 disable locked 1 enable GPIO_CPU_1XCLKACT [ 22 ] read-write 0x1 GPIO AMBA Clock control 0 disable locked 1 enable UART1_CPU_1XCLKACT [ 21 ] read-write 0x1 UART 1 AMBA Clock control 0 disable locked 1 enable UART0_CPU_1XCLKACT [ 20 ] read-write 0x1 UART 0 AMBA Clock control 0 disable locked 1 enable I2C1_CPU_1XCLKACT [ 19 ] read-write 0x1 I2C 1 AMBA Clock control 0 disable locked 1 enable I2C0_CPU_1XCLKACT [ 18 ] read-write 0x1 I2C 0 AMBA Clock control 0 disable locked 1 enable CAN1_CPU_1XCLKACT [ 17 ] read-write 0x1 CAN 1 AMBA Clock control 0 disable locked 1 enable CAN0_CPU_1XCLKACT [ 16 ] read-write 0x1 CAN 0 AMBA Clock control 0 disable locked 1 enable SPI1_CPU_1XCLKACT [ 15 ] read-write 0x1 SPI 1 AMBA Clock control 0 disable locked 1 enable SPI0_CPU_1XCLKACT [ 14 ] read-write 0x1 SPI 0 AMBA Clock control 0 disable locked 1 enable reserved [ 13 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 12 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SDI1_CPU_1XCLKACT [ 11 ] read-write 0x1 SDIO controller 1 AMBA Clock control 0 disable locked 1 enable SDI0_CPU_1XCLKACT [ 10 ] read-write 0x1 SDIO controller 0 AMBA Clock 0 disable locked 1 enable reserved [ 9 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 8 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. GEM1_CPU_1XCLKACT [ 7 ] read-write 0x1 Gigabit Ethernet 1 AMBA Clock control 0 disable locked 1 enable GEM0_CPU_1XCLKACT [ 6 ] read-write 0x1 Gigabit Ethernet 0 AMBA Clock control 0 disable locked 1 enable reserved [ 5 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 4 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. USB1_CPU_1XCLKACT [ 3 ] read-write 0x1 USB controller 1 AMBA Clock control 0 disable locked 1 enable USB0_CPU_1XCLKACT [ 2 ] read-write 0x1 USB controller 0 AMBA Clock control 0 disable locked 1 enable reserved [ 1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DMA_CPU_2XCLKACT [ 0 ] read-write 0x1 DMA controller AMBA Clock control 0 disable locked 1 enable USB0_CLK_CTRL USB 0 ULPI Clock Control 0x30 32 read-write 0x00101941 reserved [ 31:26 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 25:20 ] read-write 0x1 Reserved. Do not modify. reserved [ 19:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 13:8 ] read-write 0x19 Reserved. Do not modify. reserved [ 7 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 6:4 ] read-write 0x4 Select the source to generate USB controller 0 ULPI clock:1xx: USB 0 MIO ULPI clock (top level MIO ULPI clock is an input) reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 0 ] read-write 0x1 Reserved. Do not modify. USB1_CLK_CTRL USB 1 ULPI Clock Control 0x34 32 read-write 0x00101941 reserved [ 31:26 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 25:20 ] read-write 0x1 Reserved. Do not modify. reserved [ 19:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 13:8 ] read-write 0x19 Reserved. Do not modify. reserved [ 7 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 6:4 ] read-write 0x4 Select the source to generate USB controller 1 ULPI clock:1xx: USB 1 MIO ULPI clock (top level MIO ULPI clock is an input) reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 0 ] read-write 0x1 Reserved. Do not modify. GEM0_RCLK_CTRL GigE 0 Rx Clock and Rx Signals Select 0x38 32 read-write 0x00000001 reserved [ 31:5 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 4 ] read-write 0x0 Select the source of the Rx clock, control and data signals: 0 MIO 1 EMIO reserved [ 3:1] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 Ethernet Controler 0 Rx Clock control 0 disable locked 1 enable GEM1_RCLK_CTRL GigE 1 Rx Clock and Rx Signals Select 0x3C 32 read-write 0x00000001 reserved [ 31:5 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 4 ] read-write 0x0 Select the source of the Rx clock, control and data signals: 0 MIO 1 EMIO reserved [ 3:1] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 Ethernet Controler 0 Rx Clock control 0 disable locked 1 enable GEM0_CLK_CTRL GigE 0 Ref Clock Control 0x40 32 read-write 0x00003C01 reserved [ 31:26 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 [ 25:20 ] read-write 0x0 Second divisor for Ethernet controller 0 source clock. reserved [ 19:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x3C First divisor for Ethernet controller 0 source clock. reserved [ 7 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 6:4 ] read-write 0x0 Selects the source to generate the reference clock 00x IO PLL. 010 Arm PLL. 011 DDR PLL 1xx Ethernet controller 0 EMIO clock reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 Ethernet Controller 0 Reference Clock control 0 disable locked 1 enable GEM1_CLK_CTRL GigE 1 Ref Clock Control 0x44 32 read-write 0x00003C01 reserved [ 31:26 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 [ 25:20 ] read-write 0x0 Second divisor for Ethernet controller 0 source clock. reserved [ 19:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x3C First divisor for Ethernet controller 0 source clock. reserved [ 7 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 6:4 ] read-write 0x0 Selects the source to generate the reference clock 00x IO PLL. 010 Arm PLL. 011 DDR PLL 1xx Ethernet controller 0 EMIO clock reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 Ethernet Controller 0 Reference Clock control 0 disable locked 1 enable SMC_CLK_CTRL SMC Ref Clock Control 0x48 32 read-write 0x00003C21 reserved [ 31:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x3C Divisor for SMC source clock. reserved [ 7:6 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 5:4 ] read-write 0x2 Select clock source generate SMC clock: 0x0 IO PLL 10 Arm PLL 11 DDR PLL reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 SMC Reference Clock control 0 disable 1 enable LQSPI_CLK_CTRL Quad SPI Ref Clock Control 0x4C 32 read-write 0x00002821 reserved [ 31:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x28 Divisor for Quad SPI Controller source clock. reserved [ 7:6 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 5:4 ] read-write 0x2 Select clock source generate Quad SPI clock: 0x0 IO PLL 10 Arm PLL 11 DDR PLL reserved [ 3:1 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT [ 0 ] read-write 0x1 Quad SPI Controller Reference Clock control 0 disable 1 enable SDIO_CLK_CTRL SDIO Ref Clock Control 0x50 32 read-write 0x00001E03 reserved [ 31:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x1E Provides the divisor used to divide the source clock to generate the required generated clock frequency. reserved [ 7:6 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 5:4 ] read-write 0x0 Select the source used to generate the clock. 0x0 Source for generated clock is IO PLL. 11 Source for generated clock is Arm PLL. 11 Source for generated clock is DDR PLL. reserved [ 3:2 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT1 [ 1 ] read-write 0x1 SDIO Controller 1 Clock control. 0 disable 1 enable CLKACT0 [ 0 ] read-write 0x1 SDIO Controller 0 Clock control. 0 disable 1 enable UART_CLK_CTRL UART Ref Clock Control 0x54 32 read-write 0x00003F03 reserved [ 31:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR [ 13:8 ] read-write 0x3F Divisor for UART Controller source clock. reserved [ 7:6 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 5:4 ] read-write 0x0 Selects the PLL source to generate the clock. 0x IO PLL 10 Arm PLL 11 DDR PLL reserved [ 3:2 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. CLKACT1 [ 1 ] read-write 0x1 UART 1 reference clock active: 0 Clock is disabled 1 Clock is enabled CLKACT0 [ 0 ] read-write 0x1 UART 0 Reference clock control. 0 disable 1 enable SPI_CLK_CTRL SPI Ref Clock Control 0x58 32 read-write 0x00003F03 value read-write [31:0] CAN_CLK_CTRL CAN Ref Clock Control 0x5C 32 read-write 0x00501903 value read-write [31:0] CAN_MIOCLK_CTRL CAN MIO Clock Control 0x60 32 read-write 0x00000000 DBG_CLK_CTRL SoC Debug Clock Control 0x64 32 read-write 0x00000F03 value read-write [31:0] PCAP_CLK_CTRL PCAP Clock Control 0x68 32 read-write 0x00000F01 value read-write [31:0] TOPSW_CLK_CTRL Central Interconnect Clock Control 0x6C 32 read-write 0x00000000 value read-write [31:0] 4 0x10 FPGA0,FPGA1,FPGA2,FPGA3 %s_CLK_CTRL PL Clock 0 Output control 0x70 32 read-write 0x00101800 value [31:0] read-write reserved [ 31:26 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 [ 25:20 ] read-write 0x1 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide reserved [ 19:14 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR0 [ 13:8 ] read-write 0x18 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. reserved [ 7:6 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL [ 5:4 ] read-write 0x0 Select the source used to generate the clock: 0 0x Source for generated clock is IO PLL. 2 10 Source for generated clock is Arm PLL. 3 11 Source for generated clock is DDR PLL. reserved [ 3:0 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. 4 0x10 FPGA0,FPGA1,FPGA2,FPGA3 %s_THR_CTRL PL Clock 0 Throttle control 0x74 32 read-write 0x00000000 value [31:0] read-write reserved [ 31:4 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 3 ] read-write 0x0 Must be set to 1'b0 to use this feature reserved [ 2 ] read-write 0x0 Must be set to 1'b1 to use this feature CNT_RST [ 1 ] read-write 0x0 Reset clock throttle counter when in halt state: 0 0x No effect 1 10 Causes counter to be reset once HALT state is entered. CPU_START [ 0 ] read-write 0x0 Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.) 0 0x No effect 1 10 Start count or restart count if previous value was 0 4 0x10 FPGA0,FPGA1,FPGA2,FPGA3 %s_THR_CNT PL Clock 0 Throttle Count control 0x78 32 read-write 0x00000000 value [31:0] read-write PL Clock 0 Throttle Count control reserved [ 31:20 ] read-write 0x0 Reserved. Writes are ignored, read data is zero. reserved [ 19:16 ] read-write 0x0 Reserved. Do not modify. LAST_CNT [ 15:0 ] read-write 0x0 Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic. 4 0x10 FPGA0,FPGA1,FPGA2,FPGA3 %s_THR_STA PL Clock 0 Throttle Status read 0x7C 32 read-only 0x00010000 value [31:0] read-write PL Clock 0 Throttle Status read reserved [ 31:17 ] read-only 0x0 Reserved. Writes are ignored, read data is zero. RUNNING [ 16 ] read-only 0x1 Current running status of FPGA clock output: 0 0x Clock is stopped or in normal mode (OK to change configuration). 1 10 Clock is running in debug mode (Keep configuration static). CURR_VAL [ 15:0 ] read-only 0x0 Current clock throttle counter value, which indicates the number of clock pulses output so far (only accurate when halted). CLK_621_TRUE CPU Clock Ratio Mode select 0xC4 32 read-write 0x00000001 value read-write [31:0] RCTRS Reset control and status See Reset System SLCR RCTRS_ 0xF8000200 0 0x00000100 registers APU APU control See Application Processing Unit SLCR APU_ 0xF8000300 0 0x00000100 registers TrustZone TrustZone control See UG1019, Programming Arm TrustZone Architecture on the Xilinx Zynq-7000 SoC SLCR TrustZone_ 0xF8000400 0 0x00000100 registers SoC_TD CoreSight SoC debug control See System Test and Debug SLCR SoC_TD_ 0xF8000500 0 0x00000100 registers DRAM DDR DRAM controller See DDR Memory Controller SLCR DRAM_ 0xF8000600 0 0x00000100 registers MIO_C MIO pin configuration See Signals, Interfaces, and Pins SLCR MIO_C_ 0xF8000700 0 0x00000100 registers 54 4 00-53 MIO_PIN_%s MIO Pin Control 0x0 32 read-write 0x00000000 0xFFFFFFFF value read-write [31:0] MIO_P MIO parallel access See Signals, Interfaces, and Pins SLCR PMIO_P_ 0xF8000800 0 0x00000100 registers OCM_M Miscellaneous control See On-Chip Memory (OCM) SLCR OCM_ 0xF8000900 0 0x00000100 registers OCM On-chip memory (OCM) control See On-Chip Memory (OCM) SLCR OCM_ 0xF8000A00 0 0x00000100 registers GPIOB I/O buffers for MIO pins (GPIOB) and DDR pins (DDRIOB) See Signals, Interfaces, and Pins SLCR GPIOB_ 0xF8000B00 0 0x00000100 registers PS PS System registers PS PS 0xF8001000 0 0x00603000 registers TTC0 Triple timer counter 0 (TTC 0) ttc. PS TTC 0xF8001000 0 0x00001000 registers TTC1 Triple timer counter 1 (TTC 1) ttc. PS TTC 0xF8002000 0 0x00001000 registers DMAC_S DMAC when secure (DMAC S) dmac PS DMAC 0xF8003000 0 0x00001000 registers DMAC_NS DMAC when secure (DMAC NS) dmac PS DMAC 0xF8004000 0 0x00001000 registers SWDT System watchdog timer (SWDT) swdt PS SWDT 0xF8005000 0 0x00001000 registers DDRC DDR memory controller ddrc. PS DDRC 0xF8006000 0 0x00001000 registers DevC Device configuration interface (DevC) devcfg. PS DevC 0xF8007000 0 0x00001000 registers AXI_HP0 AXI_HP 0 high performance AXI interface w/ FIFO afi. PS AXI_HP 0xF8008000 0 0x00001000 registers AXI_HP1 AXI_HP 1 high performance AXI interface w/ FIFO afi. PS AXI_HP 0xF8009000 0 0x00001000 registers AXI_HP2 AXI_HP 2 high performance AXI interface w/ FIFO afi. PS AXI_HP 0xF800A000 0 0x00001000 registers AXI_HP3 AXI_HP 3 high performance AXI interface w/ FIFO afi. PS AXI_HP 0xF800B000 0 0x00001000 registers OCM On-chip memory (OCM) ocm. PS OCM 0xF800C000 0 0x00001000 registers eFuse eFuse PS eFuse 0xF800D000 0 0x00001000 registers eFuse eFuse PS eFuse 0xF800F000 0 0x00001000 registers CDCC CoreSight debug control cti. PS CDCC 0xF8800000 0 0x00001000 registers CPU CPU Private registers CPU CPU 0xF8900000 0 0x00602FFF registers GPV Top-level interconnect configuration and Global Programmers View (GPV) CPU GPV_ 0xF8900000 0 0x00100000 registers SCU SCU control and status CPU SCU_ 0xF8F00000 0 0x0000100 registers INT_CTL Interrupt controller CPU CPU INT_CTL_ 0xF8F00100 0 0x0000100 registers G_TIM Global timer CPU G_TIM_ 0xF8F00200 0 0x0000100 registers P_TIM Private timers and private watchdog timers CPU P_TIM_ 0xF8F00600 0 0x0000100 registers INT_CD Interrupt controller distributor CPU INT_CD_ 0xF8F01000 0 0x0001000 registers L2_CTL L2-cache controller CPU L2_CTL_ 0xF8F02000 0 0x0001000 registers Quad-SPI Quad-SPI linear address for linear mode Quad-SPI Quad-SPI 0xFC000000 0 0x02000000 registers OCM OCM is mapped high OCM OCM 0xFFFC0000 0 0x00040000 registers