Microchip https://packs.download.microchip.com/ SAMV71_DFP Microchip SAMV71 Series Device Support Removed SDRAM references due to errata 2.14 Added configuration data required for XC32. - Headers minor version increased to v2.1.0. - Changed integer constant literal macros from _Ux_ to _UNITxx_ (where xx is 32, 16 or 8) (MISRA C2012:R12.2). Deprecated revision A devices. Fixed MPLABX debug scripts. Updated startup code. Updated header files. Updated XC32 content. Added security bit programming for MPLAB X. Added instance headers. Fix DMA trigger information for DACn. Added read device ID. Updated MPLABX debug scripts. Setup prerequisite for MPLAB v5.40 or newer. Fix reading/writing configbits. Updated MPLAB X debug scripts. Updated XC32 content. Updated MPLAB X debug scripts. Improvements to the flash programming algorithm. Rename SVCall_Handler to SVC_Handler. Update modes for USART. Improvements to the flash programming algorithm: Improve programming speed. Resolve a possible flash programming issue. Removed legacy headers. Corrections to XML and header-files. Core modules descriptions in ATDF and SVD changed for rev. B devices. Core IRQ and interrupt handler names changed to alligne with CMSIS names. Old names mapped as aliases to new names. Several errors in SVD files corrected. Missing TC1 and TC2 to instance definitions added to header files. TC, USART and USBHS module changed (for revB devices) to reflect the modes according to the datasheet. Added ARMCC support files. Added Keil support files. Added python programming and debugging scripts for MPLAB X. Succeeds Atmel.SAMV71_DFP 2.3.136. Microchip Device Family Package Microchip Device Support SAMV71 // Debug Access Variables __var TracePCK3 = 0x00000000; // Trace Clock Source Selection and Prescaler __var traceSWO = (__traceout & 0x1) != 0; // SWO Trace Selected? __var traceTPIU = (__traceout & 0x2) != 0; // TPIU Trace Selected? Sequence("EnableTraceSWO"); // Call SWO Trace Setup Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup Write32(0x400E06E4, 0x504D4300); // Disable PMC write protection Write32(0x400E064C, TracePCK3); // Select clock source and prescaler for PCK3 Write32(0x400E0600, (1 << 11)); // Enable PCK3 __var width = (__traceout & 0x003F0000) >> 16; // TPIU Port Width __var val = 0; // 1-Bit TPIU Trace Setup val = 0x00000010; // TRACED[0] // 2-Bit TPIU Trace Setup val = 0x00000030; // TRACED[0..1] // 4-Bit TPIU Trace Setup val = 0x000000F0; // TRACED[0..3] // Write Trace Configuration to Target Write32(0x400E06E4, 0x504D4300); // Disable PMC write protection Write32(0x400E064C, TracePCK3); // Select clock source and prescaler for PCK3 Write32(0x400E0600, (1 << 11)); // Enable PCK3 Write32(0x400E0610, (1 << 16)); // Enable PIOD clock Write32(0x400E14E4, 0x50494F00); // Disable PIOD write protection Write32(0x400E1404, (val | 0x00000100)); // Disable PIOD PD[4..8] Write32(0x400E1470, ((Read32(0x400E1470) & ~val) | 0x00000100)); // Set Peripheral Select registers Write32(0x400E1474, ((Read32(0x400E1474) | val) | 0x00000100)); // TRACED[0..3] to alternate peripheral C and TRACECLK to alternate peripheral D 2021-06-28 2021-06-28 2021-06-28 2021-06-28 2021-06-28 2021-06-28 2021-06-28 2021-06-28 2021-06-28 Headers and startup code for Microchip ATSAMV71J19B Headers and startup code for Microchip ATSAMV71J20B Headers and startup code for Microchip ATSAMV71J21B Headers and startup code for Microchip ATSAMV71N19B Headers and startup code for Microchip ATSAMV71N20B Headers and startup code for Microchip ATSAMV71N21B Headers and startup code for Microchip ATSAMV71Q19B Headers and startup code for Microchip ATSAMV71Q20B Headers and startup code for Microchip ATSAMV71Q21B