Microchip https://packs.download.microchip.com/ PIC32CM-LS_DFP Microchip PIC32CM-LS Series Device Support - Removed 256K flash devices. - Improved memory area naming. - Initial release. Microchip Device Family Package Microchip Device Support PIC32CM-LS // Debugger Setup __var CE_Select = 0x00000002; __var CE0_Keyword0 = 0xFFFFFFFF; __var CE0_Keyword1 = 0xFFFFFFFF; __var CE0_Keyword2 = 0xFFFFFFFF; __var CE0_Keyword3 = 0xFFFFFFFF; __var CE1_Keyword0 = 0xFFFFFFFF; __var CE1_Keyword1 = 0xFFFFFFFF; __var CE1_Keyword2 = 0xFFFFFFFF; __var CE1_Keyword3 = 0xFFFFFFFF; __var CE2_Keyword0 = 0xFFFFFFFF; __var CE2_Keyword1 = 0xFFFFFFFF; __var CE2_Keyword2 = 0xFFFFFFFF; __var CE2_Keyword3 = 0xFFFFFFFF; // Device Setup __var ProgramDebugAccessLevel = 0x00000002; __var UROW_Program = 0x00000000; __var BOCOR_Program = 0x00000000; // UROW Configuration __var UROW_Config0 = 0xB000433F; __var UROW_Config1 = 0x000010BB; __var UROW_Config2 = 0x700007FF; __var UROW_Config3 = 0x000005FF; __var UROW_NONSECA = 0x00000000; __var UROW_NONSECB = 0x00000000; __var UROW_NONSECC = 0x00000000; __var UROW_CDIROFFSET = 0x00000000; // BOCOR Configuration __var BOCOR_Config0 = 0xA0000000; __var BOCOR_Config1 = 0x00030000; __var BOCOR_ROMVersion = 0x0000003A; __var BOCOR_CE0_Keyword0 = 0xFFFFFFFF; __var BOCOR_CE0_Keyword1 = 0xFFFFFFFF; __var BOCOR_CE0_Keyword2 = 0xFFFFFFFF; __var BOCOR_CE0_Keyword3 = 0xFFFFFFFF; __var BOCOR_CE1_Keyword0 = 0xFFFFFFFF; __var BOCOR_CE1_Keyword1 = 0xFFFFFFFF; __var BOCOR_CE1_Keyword2 = 0xFFFFFFFF; __var BOCOR_CE1_Keyword3 = 0xFFFFFFFF; __var BOCOR_CE2_Keyword0 = 0xFFFFFFFF; __var BOCOR_CE2_Keyword1 = 0xFFFFFFFF; __var BOCOR_CE2_Keyword2 = 0xFFFFFFFF; __var BOCOR_CE2_Keyword3 = 0xFFFFFFFF; __var BOCOR_CRC_Keyword0 = 0xFFFFFFFF; __var BOCOR_CRC_Keyword1 = 0xFFFFFFFF; __var BOCOR_CRC_Keyword2 = 0xFFFFFFFF; __var BOCOR_CRC_Keyword3 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword0 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword1 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword2 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword3 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword4 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword5 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword6 = 0xFFFFFFFF; __var BOCOR_BOOT_Keyword7 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword0 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword1 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword2 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword3 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword4 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword5 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword6 = 0xFFFFFFFF; __var BOCOR_UDS_Keyword7 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword0 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword1 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword2 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword3 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword4 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword5 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword6 = 0xFFFFFFFF; __var BOCOR_IOPROTKEY_Keyword7 = 0xFFFFFFFF; __var nReset = 0x80; // De-assert nRESET line to activate the hardware reset DAP_SWJ_Pins(0, nReset, 0); Sequence("ColdPlugin"); __var nReset = 0x80; __var SWCLK_TCK = 0x01; __var canReadPins = 0; // Assert nRESET line and check if nRESET is readable canReadPins = (DAP_SWJ_Pins(nReset, nReset, 0) != 0xFFFFFFFF); DAP_Delay(100000); __var SWCLK_TCK = 0x01; DAP_SWJ_Pins(SWCLK_TCK, SWCLK_TCK, 0); // Make sure that SWCLK/TCK is HIGH for hot-plugin Sequence("ResetHardwareDeassertDefault"); // Typical Boot Timings for PIC32CMLS // - BOOTOPT=0 : 2.30 ms // - BOOTOPT=1, BS=0x40: 207 ms // - BOOTOPT=1, BS=0x80: 409 ms // - BOOTOPT=2, BS=0x40: 209 ms // - BOOTOPT=2, BS=0x80: 411 ms DAP_Delay(420000); // Time for bootloader : Longest period + a few extra ms // Possible Enhancement: Read out Boot options to optimize __var isSWJ = ((__protocol & 0x00010000) != 0); __var protType = __protocol & 0x0000FFFF; // Ensure current debug interface is in reset state DAP_SWJ_Sequence(51, 0x0007FFFFFFFFFFFF); // Execute SWJ-DP Switch Sequence SWD to JTAG (0xE73C) // Change if SWJ-DP uses deprecated switch code (0xAEAE) DAP_SWJ_Sequence(16, 0xE73C); // Ensure JTAG interface is reset DAP_SWJ_Sequence(6, 0x3F); // JTAG "Soft" Reset DAP_JTAG_Sequence(6, 1, 0x3F); DAP_JTAG_Sequence(1, 0, 0x01); // Ensure current debug interface is in reset state DAP_SWJ_Sequence(51, 0x0007FFFFFFFFFFFF); // Execute SWJ-DP Switch Sequence JTAG to SWD (0xE79E) // Change if SWJ-DP uses deprecated switch code (0xEDB6) DAP_SWJ_Sequence(16, 0xE79E); // Enter SWD Line Reset State DAP_SWJ_Sequence(51, 0x0007FFFFFFFFFFFF); // > 50 cycles SWDIO/TMS High DAP_SWJ_Sequence(3, 0x00); // At least 2 idle cycles (SWDIO/TMS Low) // Enter SWD Line Reset State DAP_SWJ_Sequence(51, 0x0007FFFFFFFFFFFF); // > 50 cycles SWDIO/TMS High DAP_SWJ_Sequence(3, 0x00); // At least 2 idle cycles (SWDIO/TMS Low) // Read DPIDR to enable SWD interface (SW-DPv1 and SW-DPv2) ReadDP(0x0); __var SW_DP_ABORT = 0x0; __var DP_CTRL_STAT = 0x4; __var DP_SELECT = 0x8; __var powered_down = 0; // Switch to DP Register Bank 0 WriteDP(DP_SELECT, 0x00000000); // Read DP CTRL/STAT Register and check if CSYSPWRUPACK and CDBGPWRUPACK bits are set powered_down = ((ReadDP(DP_CTRL_STAT) & 0xA0000000) != 0xA0000000); // Request Debug/System Power-Up WriteDP(DP_CTRL_STAT, 0x50000000); // Init AP Transfer Mode, Transaction Counter, and Lane Mask (Normal Transfer Mode, Include all Byte Lanes) // Additionally clear STICKYORUN, STICKYCMP, and STICKYERR bits by writing '1' WriteDP(DP_CTRL_STAT, 0x50000F32); // Init AP Transfer Mode, Transaction Counter, and Lane Mask (Normal Transfer Mode, Include all Byte Lanes) WriteDP(DP_CTRL_STAT, 0x50000F00); // Clear WDATAERR, STICKYORUN, STICKYCMP, and STICKYERR bits of CTRL/STAT Register by write to ABORT register WriteDP(SW_DP_ABORT, 0x0000001E); DAP_SWJ_Pins(0x00, 0x01, 0); // Pull down SWCLK/TCK for cold-plugin Sequence("ResetHardwareDeassertDefault"); __var DSU_BCC1_Addr = 0x41002124; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Val = 0; __var msgType = 0; DSU_BCC1_Val = Read32(DSU_BCC1_Addr); msgType = 1; msgType = 2; msgType = 1; msgType = 2; msgType = 1; Sequence("ResetPulse"); // Bring device (and boot ROM) back into defined state Message(msgType, "Boot ROM error - 0x%08X", DSU_BCC1_Val); __var DSU_BCC1_Addr = 0x41002124; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Val = 0; __var ChecksumErr = 0; DSU_BCC1_Val = Read32(DSU_BCC1_Addr); ChecksumErr = (DSU_BCC1_Val == 0xEC000011) || (DSU_BCC1_Val == 0xEC000013) || (DSU_BCC1_Val == 0xEC000041) || (DSU_BCC1_Val == 0xEC000041); Query(0, "Checksum/hash error!\nErase and reprogram chip under reset.", 1); Message(2, "Checksum/hash error (0x%08X)! Erase and reprogram chip under reset.", DSU_BCC1_Val); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) Write32(DSU_Ctrl_Stat_Addr, 0x00001C00); // Clear Error Flags in DSU.STATA (PERR, FAIL, BERR) Write32(DSU_Ctrl_Stat_Addr, 0x00000200); // Clear CPU Reset Extension in DSU.STATA DAP_Delay(5000); // Wait 5 ms after CPU Release Sequence("Bootrom_CheckError"); // Check Boot ROM Status __var DSU_BCC0_Addr = 0x41002120; // Access DSU External Address Range (for all DALs) Write32(DSU_BCC0_Addr, 0x44424755); // Write CMD_INIT Sequence("Bootrom_CheckError"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DSU_BCC0_Addr = 0x41002120; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Addr = 0x41002124; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Val = 0; __var CE_Keyword0 = CE2_Keyword0; // CE2_Keyword0 by default __var CE_Keyword1 = CE2_Keyword1; // CE2_Keyword1 by default __var CE_Keyword2 = CE2_Keyword2; // CE2_Keyword2 by default __var CE_Keyword3 = CE2_Keyword3; // CE2_Keyword3 by default __var CE_CMD = 0x444247E2; // CMD_CE2 by default Message(0, "Execute Chip Erase (CE%u)...", CE_Select); CE_CMD = 0x444247E0; // Use CE0 CE_Keyword0 = CE0_Keyword0; // Use CE0_Keyword0 CE_Keyword1 = CE0_Keyword1; // Use CE0_Keyword1 CE_Keyword2 = CE0_Keyword2; // Use CE0_Keyword2 CE_Keyword3 = CE0_Keyword3; // Use CE0_Keyword3 CE_CMD = 0x444247E1; // Use CE1 CE_Keyword0 = CE1_Keyword0; // Use CE1_Keyword0 CE_Keyword1 = CE1_Keyword1; // Use CE1_Keyword1 CE_Keyword2 = CE1_Keyword2; // Use CE1_Keyword2 CE_Keyword3 = CE1_Keyword3; // Use CE1_Keyword3 Write32(DSU_BCC0_Addr, CE_CMD); // Write CMD_CE1 Sequence("Bootrom_CheckError"); Write32(DSU_BCC0_Addr, CE_Keyword0); // Write CE_Keyword0 Write32(DSU_BCC0_Addr, CE_Keyword1); // Write CE_Keyword1 Write32(DSU_BCC0_Addr, CE_Keyword2); // Write CE_Keyword2 Write32(DSU_BCC0_Addr, CE_Keyword3); // Write CE_Keyword3 Sequence("Bootrom_CheckError"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DSU_BCC0_Addr = 0x41002120; // Access DSU External Address Range (for all DALs) Write32(DSU_Ctrl_Stat_Addr, 0x00002000); // Boot Rom Phase Extension in DSU.STATA to return to app after CMD_EXIT Write32(DSU_BCC0_Addr, 0x444247AA); // Write CMD_EXIT Sequence("Bootrom_CheckError"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DSU_BCC0_Addr = 0x41002120; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Addr = 0x41002124; // Access DSU External Address Range (for all DALs) __var DSU_BCC1_Val = 0; Write32(DSU_BCC0_Addr, 0x444247AA); // Write CMD_EXIT Sequence("Bootrom_CheckError"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DSU_BCC0_Addr = 0x41002120; // Access DSU External Address Range (for all DALs) Message(0, "Execute Bootrom Reset..."); __errorcontrol = 1; // Ignore errors Write32(DSU_BCC0_Addr, 0x44424752); // Write CMD_RESET __errorcontrol = 0; // Check errors Sequence("DebugPortSetup"); Sequence("DebugPortStart"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var PAC_WRCTRL_Addr = 0x40000000; __var NVMCTRL_CTRLA_Addr = 0x41004000; __var DebugAccessLevel = 0; Message(0, "Set Debug Access Level 1..."); DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level PAC_WRCTRL_Addr += 0x0200; // Use secure alias NVMCTRL_CTRLA_Addr += 0x1000; // Use secure alias Write32(PAC_WRCTRL_Addr, (( 1 << 16) | (34 << 0))); // Disable NVMCTRL Write Protection Write32(NVMCTRL_CTRLA_Addr, 0xA54C); // Set Debug Access Level 1 (Non-Volatile until next Chip Erase or Set DAL 0) __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var PAC_WRCTRL_Addr = 0x40000000; __var NVMCTRL_CTRLA_Addr = 0x41004000; __var DebugAccessLevel = 0; Message(0, "Set Debug Access Level 0..."); DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level PAC_WRCTRL_Addr += 0x0200; // Use secure alias NVMCTRL_CTRLA_Addr += 0x1000; // Use secure alias Write32(PAC_WRCTRL_Addr, (( 1 << 16) | (34 << 0))); // Disable NVMCTRL Write Protection Write32(NVMCTRL_CTRLA_Addr, 0xA54B); // Set Debug Access Level 0 (Non-Volatile until next Chip Erase) __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DHCSR_Addr = 0xE000EDF0; __var DCRSR_Addr = 0xE000EDF4; __var DCRDR_Addr = 0xE000EDF8; __var DebugAccessLevel = 0; DAP_Delay(5000); // Workaround for MDK issue to be fixed Write32(DHCSR_Addr,0xA05F0003); // halt core in any case Write32(DCRDR_Addr, 0x01000000); Write32(DCRSR_Addr, 0x00010010); // update xPSR register (TODO: why?) __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DSU_Ctrl_Stat_Val = 0; __var DebugAccessLevel = 0; __var QueryResult = 0; DSU_Ctrl_Stat_Val = Read32(DSU_Ctrl_Stat_Addr); Sequence("CheckForChecksumError"); Sequence("Bootrom_Connect"); Sequence("Bootrom_CMD_EXIT_ToApp"); Sequence("BootDelay"); Sequence("ForceCoreHalt"); Sequence("Bootrom_Connect"); Sequence("Bootrom_CMD_INIT"); Sequence("Bootrom_CMD_CEx"); Sequence("ResetHardware"); Sequence("ForceCoreHalt"); __var AIRCR_Addr = 0xE000ED0C; __var DHCSR_Addr = 0xE000EDF0; __errorcontrol = 1; // ignore errors Write32(AIRCR_Addr, 0x05FA0004); // Execute SYSRESETREQ via AIRCR __errorcontrol = 0; // check errors Sequence("BootDelay"); Sequence("ForceCoreHalt"); // halt the core __var nReset = 0x80; __var SWCLK_TCK = 0x01; __var canReadPins = 0; canReadPins = (DAP_SWJ_Pins(0x00, nReset, 0) != 0xFFFFFFFF); // Deassert nRESET line DAP_Delay(50000); DAP_SWJ_Pins(SWCLK_TCK, SWCLK_TCK, 0); // Make sure that SWCLK/TCK is HIGH for PIC32CMLS hot-plugin DAP_SWJ_Pins(nReset, nReset, 0); // Assert nRESET line DAP_Delay(100000); // Wait 100ms for recovery if nRESET not readable Sequence("ResetPulse"); Sequence("BootDelay"); Sequence("DebugPortSetup"); Sequence("DebugPortStart"); __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DHCSR_Addr = 0xE000EDF0; __var DEMCR_Addr = 0xE000EDFC; __var FP_CTRL_Addr = 0xE0002000; __var FP_COMP0_Addr = 0xE0002008; __var FPB_KEY = 0x00000002; __var FPB_ENABLE = 0x00000001; __var DWT_COMP0_Addr = 0xE0001020; __var DWT_FUNCTION0_Addr = 0xE0001028; __var DWT_COMP1_Addr = 0xE0001030; __var DWT_FUNCTION1_Addr = 0xE0001038; __var DebugAccessLevel = 0; __var value = 0; __var resetVect = 0x00000000; DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level value = Read32(DEMCR_Addr); Write32(DEMCR_Addr, (value & ~0x00000001)); // Disable Reset Vector Catch resetVect = Read32(0x00000004); // Read Reset Vector Write32(FP_COMP0_Addr, (resetVect | FPB_ENABLE)); // Set BP0 to Reset Vector (ARMv8M) Write32(FP_CTRL_Addr, (FPB_KEY | FPB_ENABLE)); // Enable FPB Write32(DWT_FUNCTION0_Addr, 0x00000412); // DWT_FUNCTION0: DATAVSIZE - 2, ACTION - Debug Event, MATCH - Instrucion Address Write32(DWT_COMP0_Addr, 0x00000000); // DWT_COMP0: Start of available code flash Write32(DWT_COMP1_Addr, 0x00400000); // DWT_COMP1: Start of available data flash Write32(DWT_FUNCTION1_Addr, 0x00000403); // DWT_FUNCTION1: DATAVSIZE - 2, ACTION - Trigger only, MATCH - Instrucion Address Limit value = Read32(DEMCR_Addr); // Read DEMCR value &= ~0x00000001; // Disable Reset Vector Catch value |= 0x01000000; // Ensure TRCENA is set Write32(DEMCR_Addr, value); // Write back DEMCR Read32(DHCSR_Addr); // Read DHCSR to clear potentially set DHCSR.S_RESET_ST bit __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var FP_CTRL_Addr = 0xE0002000; __var FP_COMP0_Addr = 0xE0002008; __var FPB_KEY = 0x00000002; __var DWT_COMP0_Addr = 0xE0001020; __var DWT_FUNCTION0_Addr = 0xE0001028; __var DWT_COMP1_Addr = 0xE0001030; __var DWT_FUNCTION1_Addr = 0xE0001038; __var DebugAccessLevel = 0; DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level Write32(FP_COMP0_Addr, 0x00000000); // Clear BP0 Write32(FP_CTRL_Addr, FPB_KEY ); // Disable FPB Write32(DWT_FUNCTION0_Addr, 0x00000000); // Clear DWT_FUNCTION0 Write32(DWT_FUNCTION1_Addr, 0x00000000); // Clear DWT_FUNCTION1 Write32(DWT_COMP0_Addr, 0x00000000); // Clear DWT_COMP0 Write32(DWT_COMP1_Addr, 0x00000000); // Clear DWT_COMP1 __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var PageBufferDirty = 0; __var DebugAccessLevel = 0; DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level NVMCTRL_Base_Addr += 0x1000; // Use secure alias PageBufferDirty = Read8(NVMCTRL_Base_Addr + 0x18) & 0x02; // NVMCTRL.STATUS: Check if LOAD bit set (page buffer not empty) Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x44 << 0))); // NVMCTRL.CTRLA: Clear page buffer command __Result = -1; // Clear page buffer finished with errors __var PAC_WRCTRL_Addr = 0x40000000; __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for all DALs) __var DebugAccessLevel = 0; __Result = 0; // Initialize __Result to OK DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level PAC_WRCTRL_Addr += 0x0200; // Use secure alias NVMCTRL_Base_Addr += 0x1000; // Use secure alias Write32(PAC_WRCTRL_Addr, (( 1 << 16) | (34 << 0))); // PAC.WRCTRL: disable NVMCTRL Write Protection via Secure alias Write32(NVMCTRL_Base_Addr + 0x04, (( 1 << 18) | (15 << 1))); // NVMCTRL.CTRLB: cache disabled, read wait states = 15 Write8 (NVMCTRL_Base_Addr + 0x08, (( 1 << 0) )); // NVMCTRL.CTRLC: manual write Sequence("PrepareFlashOperation"); Sequence("ClearFlashPageBuffer"); __Result = 0; __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var IndirectAddressing = 0; __var DebugAccessLevel = 0; __var SectorAddr = 0x00804000; Message(0, "Erase UROW..."); __Result = 0; // Initialize __Result to OK DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level IndirectAddressing = (DebugAccessLevel < 2); // DAL1 and Code/Data Flash NVMCTRL_Base_Addr += 0x1000; // Use secure alias Sequence("PrepareFlashOperation"); Sequence("ClearFlashPageBuffer"); Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Sequence("ClearFlashPageBuffer"); Write32(SectorAddr, 0xFFFFFFFF); // Indirect setting of NVMCTRL.ADDR: Cannot be directly written at DAL1 Write32(NVMCTRL_Base_Addr + 0x1C, SectorAddr); // NVMCTRL.ADDR: 0..15 offset, 22..23 array (0 = Flash, 1 = DataFlsh, 2= AuxFlash) Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x02 << 0))); // NVMCTRL.CTRLA: Erase row command __Result = -1; // Erase row finished with errors __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var IndirectAddressing = 0; __var DebugAccessLevel = 0; __var SectorAddr = 0x0080C000; Message(0, "Erase BOCOR..."); __Result = 0; // Initialize __Result to OK DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level IndirectAddressing = (DebugAccessLevel < 2); // DAL1 and Code/Data Flash NVMCTRL_Base_Addr += 0x1000; // Use secure alias Sequence("PrepareFlashOperation"); Sequence("ClearFlashPageBuffer"); Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Sequence("ClearFlashPageBuffer"); Write32(SectorAddr, 0xFFFFFFFF); // Indirect setting of NVMCTRL.ADDR: Cannot be directly written at DAL1 Write32(NVMCTRL_Base_Addr + 0x1C, SectorAddr); // NVMCTRL.ADDR: 0..15 offset, 22..23 array (0 = Flash, 1 = DataFlsh, 2= AuxFlash) Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x02 << 0))); // NVMCTRL.CTRLA: Erase row command __Result = -1; // Erase row finished with errors SectorAddr += 0x20; __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var IndirectAddressing = 0; __var DebugAccessLevel = 0; __var SectorAddr = 0x00000000; __var SectorSize = 0x100; __var BS_HashAddr = 0x00000000; __var BS_Length = 0; __var BNSC_Length = 0; __var BS_Setup = 0; Message(0, "Erase Row for Boot Image hashsum..."); __Result = 0; // Initialize __Result to OK DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level IndirectAddressing = (DebugAccessLevel < 2); // DAL1 and Code/Data Flash BS_Setup = Read32(0x0080C000); BNSC_Length = (BS_Setup & 0x3FF80000) >> 19; BNSC_Length *= 0x20; BS_Setup = Read32(0x0080C004); BS_Length = (BS_Setup & 0x000FFF00) >> 8; BS_Length *= 0x100; BS_HashAddr = BS_Length - BNSC_Length - 0x20; SectorAddr = BS_HashAddr & ~(SectorSize - 1); NVMCTRL_Base_Addr += 0x1000; // Use secure alias Sequence("PrepareFlashOperation"); Sequence("ClearFlashPageBuffer"); Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Sequence("ClearFlashPageBuffer"); Write32(SectorAddr, 0xFFFFFFFF); // Indirect setting of NVMCTRL.ADDR: Cannot be directly written at DAL1 Write32(NVMCTRL_Base_Addr + 0x1C, SectorAddr); // NVMCTRL.ADDR: 0..15 offset, 22..23 array (0 = Flash, 1 = DataFlsh, 2= AuxFlash) Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x02 << 0))); // NVMCTRL.CTRLA: Erase row command __Result = -1; // Erase row finished with errors __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var IndirectAddressing = 0; __var DebugAccessLevel = 0; // Message(0, "Erase Row: 0x%08X...", __FlashAddr); __Result = 0; // Initialize __Result to OK DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level IndirectAddressing = (DebugAccessLevel < 2); // DAL1 and Code/Data Flash NVMCTRL_Base_Addr += 0x1000; // Use secure alias Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Sequence("ClearFlashPageBuffer"); Write32(__FlashAddr, 0xFFFFFFFF); // Indirect setting of NVMCTRL.ADDR: Cannot be directly written at DAL1 Write32(NVMCTRL_Base_Addr + 0x1C, __FlashAddr); // NVMCTRL.ADDR: 0..15 offset, 22..23 array (0 = Flash, 1 = DataFlsh, 2= AuxFlash) Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x02 << 0))); // NVMCTRL.CTRLA: Erase row command __Result = -1; // Erase row finished with errors __var NVMCTRL_Base_Addr = 0x41004000; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var DebugAccessLevel = 0; DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level NVMCTRL_Base_Addr += 0x1000; // Use secure alias Write8 (NVMCTRL_Base_Addr + 0x14, 0x1F); // NVMCTRL.INTFLAG: Clear all errors and DONE flag Write16(NVMCTRL_Base_Addr, ((0xA5 << 8) | (0x04 << 0))); // NVMCTRL.CTRLA: Write page command __Result = -1; // Write page finished with errors __var write_size = __FlashLen; // Message(0, "Program Page: 0x%08X...", __FlashAddr); __Result = 0; // Initialize __Result to OK write_size = (__FlashLen + 3) & ~3; // Adjust size to word FlashWriteBuffer (__FlashAddr, 0, write_size, (32 | 1) ); // Write Page Buffer Sequence("ExecPageWrite"); // Execute the page write __var value = 0; // Prepare UROW Content Buffer BufferSet(0, 0x00, 0x24, 1, 0xFF); // Read BOD12 setup from target (must not be changed, calibrated in factory) value = (Read32(0x00804000) & 0x01FF0000); value |= UROW_Config0 & 0xFE00FFFF; // Set UROW contents for programming BufferSet(0, 0x00, 0x01, 4, value); BufferSet(0, 0x04, 0x01, 4, UROW_Config1); BufferSet(0, 0x08, 0x01, 4, UROW_Config2); BufferSet(0, 0x0C, 0x01, 4, UROW_Config3); BufferSet(0, 0x10, 0x01, 4, UROW_NONSECA); BufferSet(0, 0x14, 0x01, 4, UROW_NONSECB); BufferSet(0, 0x18, 0x01, 4, UROW_NONSECC); BufferSet(0, 0x1C, 0x01, 4, UROW_CDIROFFSET); // Generate UROW Checksum Message (0, "Generate UROW checksum..."); BufferStreamOut(0, 0x08, 0x18, "$P/UROW_contents.bin", 0, 0); RunApplication("$S/PIC32CM-LS00/keil/utilities/GenerateCRC.exe", "\"$P/UROW_contents.bin\" -o \"$P/UROW_crc32.bin\"", "$P", 10000000); BufferStreamIn(0, 0x20, 0x4, "$P/UROW_crc32.bin", 0, 0); // Erase UROW Sequence("EraseUROW"); // Program UROW Message (0, "Program UROW..."); Sequence("PrepareFlashOperation"); Sequence("ClearFlashPageBuffer"); BufferWrite(0, 0, 0x00804000, 0x24, 32|1); Sequence("ExecPageWrite"); __var PageOffset = 0x00000000; __var BOCOR_Addr = 0x0080C000; __var BS_BootOpt = 0; // Prepare BOCOR Content Buffer BufferSet(0, 0x00, 0x100, 1, 0xFF); // Set BOCOR contents for programming - Part 1 BufferSet(0, 0x00, 0x01, 4, BOCOR_Config0); BufferSet(0, 0x04, 0x01, 4, BOCOR_Config1); // Generate BOCOR Checksum Message (0, "Generate BOCOR checksum..."); BufferStreamOut(0, 0, 0x08, "$P/BOCOR_contents_crc32.bin", 0, 0); RunApplication("$S/PIC32CM-LS00/keil/utilities/GenerateCRC.exe", "\"$P/BOCOR_contents_crc32.bin\" -o \"$P/BOCOR_crc32.bin\"", "$P", 10000000); BufferStreamIn(0, 0x08, 0x04, "$P/BOCOR_crc32.bin", 0, 0); // Set BOCOR contents for programming - Part 2 BufferSet(0, 0x0C, 0x01, 4, BOCOR_ROMVersion); BufferSet(0, 0x10, 0x01, 4, BOCOR_CE0_Keyword0); BufferSet(0, 0x14, 0x01, 4, BOCOR_CE0_Keyword1); BufferSet(0, 0x18, 0x01, 4, BOCOR_CE0_Keyword2); BufferSet(0, 0x1C, 0x01, 4, BOCOR_CE0_Keyword3); BufferSet(0, 0x20, 0x01, 4, BOCOR_CE1_Keyword0); BufferSet(0, 0x24, 0x01, 4, BOCOR_CE1_Keyword1); BufferSet(0, 0x28, 0x01, 4, BOCOR_CE1_Keyword2); BufferSet(0, 0x2C, 0x01, 4, BOCOR_CE1_Keyword3); BufferSet(0, 0x30, 0x01, 4, BOCOR_CE2_Keyword0); BufferSet(0, 0x34, 0x01, 4, BOCOR_CE2_Keyword1); BufferSet(0, 0x38, 0x01, 4, BOCOR_CE2_Keyword2); BufferSet(0, 0x3C, 0x01, 4, BOCOR_CE2_Keyword3); BufferSet(0, 0x40, 0x01, 4, BOCOR_CRC_Keyword0); BufferSet(0, 0x44, 0x01, 4, BOCOR_CRC_Keyword1); BufferSet(0, 0x48, 0x01, 4, BOCOR_CRC_Keyword2); BufferSet(0, 0x4C, 0x01, 4, BOCOR_CRC_Keyword3); BufferSet(0, 0x50, 0x01, 4, BOCOR_BOOT_Keyword0); BufferSet(0, 0x54, 0x01, 4, BOCOR_BOOT_Keyword1); BufferSet(0, 0x58, 0x01, 4, BOCOR_BOOT_Keyword2); BufferSet(0, 0x5C, 0x01, 4, BOCOR_BOOT_Keyword3); BufferSet(0, 0x60, 0x01, 4, BOCOR_BOOT_Keyword4); BufferSet(0, 0x64, 0x01, 4, BOCOR_BOOT_Keyword5); BufferSet(0, 0x68, 0x01, 4, BOCOR_BOOT_Keyword6); BufferSet(0, 0x6C, 0x01, 4, BOCOR_BOOT_Keyword7); BufferSet(0, 0x70, 0x01, 4, BOCOR_UDS_Keyword0); BufferSet(0, 0x74, 0x01, 4, BOCOR_UDS_Keyword1); BufferSet(0, 0x78, 0x01, 4, BOCOR_UDS_Keyword2); BufferSet(0, 0x7C, 0x01, 4, BOCOR_UDS_Keyword3); BufferSet(0, 0x80, 0x01, 4, BOCOR_UDS_Keyword4); BufferSet(0, 0x84, 0x01, 4, BOCOR_UDS_Keyword5); BufferSet(0, 0x88, 0x01, 4, BOCOR_UDS_Keyword6); BufferSet(0, 0x8C, 0x01, 4, BOCOR_UDS_Keyword7); BufferSet(0, 0x90, 0x01, 4, BOCOR_IOPROTKEY_Keyword0); BufferSet(0, 0x94, 0x01, 4, BOCOR_IOPROTKEY_Keyword1); BufferSet(0, 0x98, 0x01, 4, BOCOR_IOPROTKEY_Keyword2); BufferSet(0, 0x9C, 0x01, 4, BOCOR_IOPROTKEY_Keyword3); BufferSet(0, 0xA0, 0x01, 4, BOCOR_IOPROTKEY_Keyword4); BufferSet(0, 0xA4, 0x01, 4, BOCOR_IOPROTKEY_Keyword5); BufferSet(0, 0xA8, 0x01, 4, BOCOR_IOPROTKEY_Keyword6); BufferSet(0, 0xAC, 0x01, 4, BOCOR_IOPROTKEY_Keyword7); // Determine BOOTOPT setting for hashsum BS_BootOpt = (BOCOR_Config1 & 0xFF); Message (0, "Generate BOCOR hashsum..."); // Write hashsum input BufferStreamOut(0, 0, 0xE0, "$P/BOCOR_contents.bin", 0x00, 0); // Write BOCOR contents // Write hashsum input (including 2*BOOTKEY) BufferStreamOut(0, 0x50, 0x20, "$P/BOCOR_contents.bin", 0x00, 0); // Write BOOTKEY: First Time BufferStreamOut(0, 0x50, 0x20, "$P/BOCOR_contents.bin", 0x10, 0); // Append BOOTKEY: Second Time BufferStreamOut(0, 0x00, 0xE0, "$P/BOCOR_contents.bin", 0x10, 0); // Append BOCOR contents // Generate hashsum RunApplication("$S/PIC32CM-LS00/keil/utilities/GenerateSHA.exe", "\"$P/BOCOR_contents.bin\" -o \"$P/BOCOR_sha256.bin\"", "$P", 10000000); BufferStreamIn(0, 0xE0, 0x20, "$P/BOCOR_sha256.bin", 0, 0); // Erase BOCOR Sequence("EraseBOCOR"); // Prepare BOCOR programming Message (0, "Program BOCOR..."); Sequence("PrepareFlashOperation"); // Program BOCOR pages Sequence("ClearFlashPageBuffer"); BufferWrite(0, PageOffset, BOCOR_Addr + PageOffset, 0x20, 32|1); Sequence("ExecPageWrite"); PageOffset += 0x20; __var BS_Address = 0x00000000; __var BS_HashAddr = 0x00000000; __var BS_Length = 0; __var BNSC_Length = 0; __var BS_Setup = 0; __var BS_BootOpt = 0; __var SectorSize = 0x100; __var SectorAddr = 0x00000000; __var PageAddr = 0x00000000; BS_Setup = Read32(0x0080C000); BNSC_Length = (BS_Setup & 0x3FF80000) >> 19; BNSC_Length *= 0x20; BS_Setup = Read32(0x0080C004); BS_BootOpt = (BS_Setup & 0xFF); BS_Length = (BS_Setup & 0x000FFF00) >> 8; BS_Length *= 0x100; BS_HashAddr = BS_Length - BNSC_Length - 0x20; SectorAddr = BS_HashAddr & ~(SectorSize - 1); Message (0, "Generate Boot Image hashsum..."); // Read Boot Secure and Non-Secure Callable Code from target BufferRead(0, 0, BS_Address, BS_Length, 32|1); // Write hashsum input BufferStreamOut(0, 0, BS_HashAddr, "$P/Boot_contents.bin", 0x00, 0); // Boot Secure Code: Write to file BufferRead(1, 0, 0x0080C050, 0x20, 32|1); // Read BOOTKEY from target BufferStreamOut(1, 0, 0x20, "$P/Boot_contents.bin", 0x00, 0); // Write BOOTKEY: First Time BufferStreamOut(1, 0, 0x20, "$P/Boot_contents.bin", 0x10, 0); // Append BOOTKEY: Second Time BufferStreamOut(0, 0, BS_HashAddr, "$P/Boot_contents.bin", 0x10, 0); // Append Boot Secure Code BufferStreamOut(0, BS_Length - BNSC_Length, BNSC_Length, "$P/Boot_contents.bin", 0x10, 0); // Append Boot Non-Secure Callable Code RunApplication("$S/PIC32CM-LS00/keil/utilities/GenerateSHA.exe", "\"$P/Boot_contents.bin\" -o \"$P/Boot_sha256.bin\"", "$P", 10000000); BufferStreamIn(0, BS_HashAddr, 0x20, "$P/Boot_sha256.bin", 0, 0); // Erase Sequence("EraseBSHashRow"); // Prepare hashsum programming (entire row) Message (0, "Program Boot Image hashsum..."); PageAddr = SectorAddr; Sequence("PrepareFlashOperation"); // Program row pages for hashsum Sequence("ClearFlashPageBuffer"); BufferWrite(0, PageAddr, PageAddr, 0x20, 32|1); Sequence("ExecPageWrite"); PageAddr += 0x20; __var DSU_Ctrl_Stat_Addr = 0x41002100; // Access DSU External Address Range (for DALs) __var DebugAccessLevel = 0; // Program Configuration Rows and Boot Image Hashsum Sequence("ProgramUROW"); Sequence("ProgramBOCOR"); Sequence("ProgramBootImageHash"); DebugAccessLevel = (Read32(DSU_Ctrl_Stat_Addr) & 0x00030000) >> 16; // Read Debug Access Level Sequence("NVMCTRL_SetDAL1"); Sequence("NVMCTRL_SetDAL0"); Headers and startup code for Microchip PIC32CM2532LS00048 Headers and startup code for Microchip PIC32CM2532LS00064 Headers and startup code for Microchip PIC32CM2532LS00100 Headers and startup code for Microchip PIC32CM5164LS00048 Headers and startup code for Microchip PIC32CM5164LS00064 Headers and startup code for Microchip PIC32CM5164LS00100 Headers and startup code for Microchip PIC32CM5164LS60048 Headers and startup code for Microchip PIC32CM5164LS60064 Headers and startup code for Microchip PIC32CM5164LS60100