ARM http://www.keil.com/pack/ Musca_B1_BSP Musca B1 Board Support PACK for CoreLink SSE-200 based - TrustZone enabled subsystem for embedded. TFM Pack is required. Adds SSE-200 System Information and System Control block to the SVD file. Adds iCache, PWM and watchdog drivers. Runs code in eFlash, adds NVIC reset for platform reset and various other improvements. Musca B1 SoC Support Pack for CoreLink SSE-200 - TrustZone enabled subsystem including device definition. This BSP pack has mandatory requiremant for the TFM pack. The flag __DOMAIN_NS is used in the internal files to distinguish between secure and non-secure application. Please, use the flag as follow: -> secure application uses -D__DOMAIN_NS=0 -> non-secure application uses -D__DOMAIN_NS=1 ARM Device Support Device Family Package ARM CMSDK Board Support Package for Musca B1 SSE-200 Musca B1 Musca B1 SoC (TrustZone enabled subsystem). The flag DOMAIN_NS is used in the internal files to distinguish between secure and non-secure application. Please, use the flag as follow: -> secure application uses -DDOMAIN_NS=0 -> non-secure application uses -DDOMAIN_NS=1 // Debug Authentication Variables __var DAuthFixed = 0x1; // 1 - Use fixed authentication, 0 - Ask for user input __var DAuthConfig = 0xF; // Authentication Value (Security Control Block) // Bit 0 - Invasive Debug (Hardwired to 1) // Bit 1 - Non-Invasive Debug (Hardwired to 1) // Bit 2 - Invasive Secure Debug // Bit 3 - Non-Invasive Secure Debug __var DAuthUserInput = 0; __var DAUTHSTATUS_Val = 0; __var DHCSR_Val = 0; __var SecureDebugEna = 0; __var SecureDebugAvail = 0; __var DAuthVal = 0; __var SECDBGSTAT_Val = 0; __var SECDBGSET_Val = 0; __var SECDBGCLR_Val = 0; __var RESET_MASK = 0; DAUTHSTATUS_Val = Read32(0xE000EE04); // struct CoreDebug_Type of v8m/cm33 DHCSR_Val = Read32(0xE000EDF0); // struct CoreDebug_Type of v8m/cm33 SecureDebugAvail = (DAUTHSTATUS_Val & 0x00000020) ? 1 : 0; // SID: Secure Invasive Debug Implemented RESET_MASK = Read32(0x50021104); // SSE-200 System Control Element - System Control register block - RESET_MASK register RESET_MASK |= (1 << 4) | (1 << 6); // RESET_MASK: Enable SYSRESETREQ0_EN and LOCKUP0_EN Write32(0x50021104, RESET_MASK); SecureDebugEna = ((DHCSR_Val & 0x00100000) || ((DAUTHSTATUS_Val & 0x00000030) == 0x00000030)) ? 1 : 0; // Debug Authentication as per Debug Configuration File DAuthVal = DAuthConfig; DAuthUserInput = Query(1, "Enable Secure Debug?", 3); // Enable Secure Debug DAuthVal = 0xF; // Disable Secure Debug DAuthVal = 0x3; // Read Secure Debug Authentication Status SECDBGSTAT_Val = Read32(0x50021000); // SSE-200 System Control Element - System Control register block - SECDBGSTAT register // Assemble SECDBGSET and SECDBGCLR Values SECDBGSET_Val = 0x000000AA; // Use internal signals: // DBGEN_SEL_SET - 1, // NIDEN_SEL_SET - 1, // SPIDEN_SEL_SET - 1, // SPNIDEN_SEL_SET - 1 SECDBGSET_Val |= DAuthVal & 0x1; // DBGEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x2) << 1; // NIDEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x4) << 2; // SPIDEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x8) << 3; // SPNIDEN_I_SET SECDBGCLR_Val |= (DAuthVal ^ 0x1) & 0x1; // DBGEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x2) & 0x2) << 1); // NIDEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x4) & 0x4) << 2); // SPIDEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x8) & 0x8) << 3); // SPNIDEN_I_SET // Write Secure Debug Authentication Set Register Write32(0x50021004, SECDBGSET_Val); // Write Secure Debug Authentication Clear Register Write32(0x50021008, SECDBGCLR_Val); Query(0, "Cannot configure Debug Authentication, secure debug disabled! Please reboot Board!", 1); ARM Musca B1 CMSIS Core ARM Musca B1 Core Device Musca B1 SoC Device Common Secure Musca B1 SoC Device Non-Secure Musca B1 SoC Device Musca B1 Native MPC Device Musca B1 Native PPC Device Musca B1 Native USART Device Musca B1 Native EFlash Device Musca B1 Native QSPI Flash Device Musca B1 QSPI Flash Device Musca B1 Memory map Secure System and Startup for Musca B1 SoC device Non-Secure System and Startup for Musca B1 SoC device MPC (Memory Protection Controller) driver for Musca B1 PPC (Preipheral Protection Controller) driver for Musca B1 UART driver for Musca B1 Embedded Flash driver for Musca B1 QSPI Flash driver for Musca B1 Flash driver emulated in SRAM for Musca B1 Native MPC driver used by CMSIS Drivers for Musca B1 Native MPC driver used by CMSIS Drivers for Musca B1 Native GPIO driver for Musca B1 Native SCC driver for Musca B1 Native CMSDK Timer driver for Musca B1 Native CMSDK DualTimer driver for Musca B1 Native MHU driver for Musca B1 Native UART driver for Musca B1 Native QSPI Flash Controller for Musca B1 MT25QL Flash Memory Library for Musca B1 Board Native GFC100 EFlash driver for Musca B1 Native SPI driver for Musca B1 SSE200 iCache driver for Musca B1 Native PWM driver for Musca B1 Native watchdog driver for Musca B1 ARM Musca B1 SoC IoT Board