ARM http://www.keil.com/pack/ Musca-S1_DFP https://github.com/ARM-software/CMSIS-Musca-S1/issues Musca-S1 (with on-chip eMRAM and CryptoCell) device and board support pack. https://github.com/ARM-software/CMSIS-Musca-S1.git Fixed MDK Blinky example projects. Added TF-M platform components. Refactored TrustZone setup. Added MPC LUT Init debug sequence. Updated orderForm tag in board element Updated supportContact Fixed partition header file with missing FPU settings. Added support contact and board documentation information. Updated BM_low_power example CMSIS-Driver included: - Flash eMRAM 1.1.0 UART driver updated: - Added support for FIFO handling and ARM_USART_EVENT_RX_TIMEOUT signal event Removed dangling slash character from the device header file CMSIS-Driver included: - I2C: initial version 1.0.0. Example projects cleaned. Initial public release of this pack. CMSIS Startup: for Arm Compiler 6. CMSIS-Driver included: - SPI: initial version 1.0.0. - USART: initial version 1.0.0. CMSIS-Zone resource file: Device/Zone/Musca-S1.rzone. Musca-S1 DFP Musca-S1 is an Arm Cortex-M33 based dual-core device with TrustZone, CryptoCell, and eMRAM. // Debug Authentication Variables __var DAuthFixed = 0x1; // 1 - Use fixed authentication, 0 - Ask for user input __var DAuthConfig = 0xF; // Authentication Value (Security Control Block) // Bit 0 - Invasive Debug (Hardwired to 1) // Bit 1 - Non-Invasive Debug (Hardwired to 1) // Bit 2 - Invasive Secure Debug // Bit 3 - Non-Invasive Secure Debug __var MPC_SRAM0_LUTInit = 0x1; __var MPC_SRAM1_LUTInit = 0x1; __var MPC_SRAM2_LUTInit = 0x1; __var MPC_SRAM3_LUTInit = 0x1; __var MPC_eMRAM_LUTInit = 0x1; __var MPC_CSRAM_LUTInit = 0x1; __var MPC_QSPI_LUTInit = 0x1; // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M. __var SCS_Addr = 0xE000E000; __var AIRCR_Addr = SCS_Addr + 0xD0C; __var DHCSR_Addr = SCS_Addr + 0xDF0; // Execute SYSRESETREQ via AIRCR Write32(AIRCR_Addr, 0x05FA0004); Sequence("MPC_LUT_Init"); __var DAuthUserInput = 0; __var DAUTHSTATUS_Val = 0; __var DHCSR_Val = 0; __var SecureDebugEna = 0; __var SecureDebugAvail = 0; __var DAuthVal = 0; __var SECDBGSTAT_Val = 0; __var SECDBGSET_Val = 0; __var SECDBGCLR_Val = 0; __var RESET_MASK = 0; DAUTHSTATUS_Val = Read32(0xE000EE04); // struct CoreDebug_Type of v8m/cm33 DHCSR_Val = Read32(0xE000EDF0); // struct CoreDebug_Type of v8m/cm33 SecureDebugAvail = (DAUTHSTATUS_Val & 0x00000020) ? 1 : 0; // SID: Secure Invasive Debug Implemented RESET_MASK = Read32(0x50021104); // SSE-200 System Control Element - System Control register block - RESET_MASK register RESET_MASK |= (1 << 4) | (1 << 5); // RESET_MASK: Enable SYSRESETREQ0_EN and SYSRSTREQ1_EN Write32(0x50021104, RESET_MASK); SecureDebugEna = ((DHCSR_Val & 0x00100000) || ((DAUTHSTATUS_Val & 0x00000030) == 0x00000030)) ? 1 : 0; // Debug Authentication as per Debug Configuration File DAuthVal = DAuthConfig; DAuthUserInput = Query(1, "Enable Secure Debug?", 3); // Enable Secure Debug DAuthVal = 0xF; // Disable Secure Debug DAuthVal = 0x3; // Read Secure Debug Authentication Status SECDBGSTAT_Val = Read32(0x50021000); // SSE-200 System Control Element - System Control register block - SECDBGSTAT register // Assemble SECDBGSET and SECDBGCLR Values SECDBGSET_Val = 0x000000AA; // Use internal signals: // DBGEN_SEL_SET - 1, // NIDEN_SEL_SET - 1, // SPIDEN_SEL_SET - 1, // SPNIDEN_SEL_SET - 1 SECDBGSET_Val |= DAuthVal & 0x1; // DBGEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x2) << 1; // NIDEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x4) << 2; // SPIDEN_I_SET SECDBGSET_Val |= (DAuthVal & 0x8) << 3; // SPNIDEN_I_SET SECDBGCLR_Val |= (DAuthVal ^ 0x1) & 0x1; // DBGEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x2) & 0x2) << 1); // NIDEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x4) & 0x4) << 2); // SPIDEN_I_SET SECDBGCLR_Val |= (((DAuthVal ^ 0x8) & 0x8) << 3); // SPNIDEN_I_SET // Write Secure Debug Authentication Set Register Write32(0x50021004, SECDBGSET_Val); // Write Secure Debug Authentication Clear Register Write32(0x50021008, SECDBGCLR_Val); Query(0, "Cannot configure Debug Authentication, secure debug disabled! Please reboot Board!", 1); // MPC address (TRM Arm CoreLink SSE-200 Subsystem for Embedded Revision: r2p0) __var MPC_SRAM0 = 0x50083000; __var MPC_SRAM1 = 0x50084000; __var MPC_SRAM2 = 0x50085000; __var MPC_SRAM3 = 0x50086000; __var MPC_eMRAM = 0x50140000; __var MPC_CSRAM = 0x50130000; __var MPC_QSPI = 0x50120000; __var MPC_CTRL = 0x000; __var MPC_BLK_MAX = 0x010; __var MPC_BLK_IDX = 0x018; __var MPC_BLK_LUT = 0x01C; __var mpc_adr = 0; __var ctrl = 0; __var blk_max = 0; __var blk_idx = 0; __var mpc_val = 0; __var error_ctrl = 0; mpc_adr = MPC_SRAM0; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_SRAM1; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_SRAM2; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_SRAM3; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_eMRAM; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_CSRAM; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; mpc_adr = MPC_QSPI; Write32(mpc_adr + MPC_CTRL, (Read32(mpc_adr + MPC_CTRL) | (1 << 8 )) ); // MPC_CTRL: Set LUT index Auto-increment. Write32(mpc_adr + MPC_BLK_IDX, 0x0); // MPC_BLK_IDX: Set LUT index to 0. blk_max = Read32(mpc_adr + MPC_BLK_MAX); // MPC_BLK_MAX: read block maximum value blk_idx = 0; Write32(mpc_adr + MPC_BLK_LUT, 0x0); // MPC_BLK_LUT: Set all blocks to secure. blk_idx = blk_idx + 1; TrustZone (Secure) Musca-S1 device and CMSIS-Core TF-M Platform for Musca-S1 TF-M Platform SPM HAL for Musca-S1 TF-M Platform System for Musca-S1 TF-M Platform Test for Musca-S1 System and Startup (C-Variant) for ARM Musca-S1 device USART Driver for Musca-S1 Device #define RTE_Drivers_USART SPI Driver for Musca-S1 Device #define RTE_Drivers_SPI I2C Driver for Musca-S1 Device #define RTE_Drivers_I2C eMRAM Flash Driver for Musca-S1 Device #define RTE_Drivers_Flash ARM V2M-Musca-S1 Board Support https://developer.arm.com/tools-and-software/development-boards/iot-test-chips-and-boards/musca-s1-test-chip-board LED driver for ARM V2M-Musca-S1 Board TF-M Platform Memory Map for ST Musca-S1 #define RTE_TFM_IF_PLATFORM_MEMORY_MAP /* TF-M Platform Memory Map */ TF-M Platform SPM HAL for ST Musca-S1 #define RTE_TFM_IF_PLATFORM_SPM_HAL /* TF-M Platform SPM HAL */ TF-M Platform System Template for ST Musca-S1 #define RTE_TFM_PLATFORM_SYSTEM /* TF-M Platform System */ TF-M Platform Test for ST Musca-S1 #define RTE_TFM_PLATFORM_TEST /* TF-M Platform Test */ TF-M Platform Boot HAL for ST Musca-S1 #define RTE_TFM_PLATFORM_BOOT_HAL /* TF-M Platform Boot HAL */ V2M-Musca-S1 SoC IoT Board CMSIS-RTOS2 (Keil RTX5) based Blinky example Getting Started CMSIS-RTX CMSIS-RTOS2 (Keil RTX5) based Blinky example (Tick-less Low-Power) Getting Started CMSIS-RTX Ultra-low power bare-metal blinky example Getting Started TF-M Project Template TF-M TF-M Regression Test - SFN (Secure Functions aka Library Mode) TF-M TF-M Regression Test - IPC Mode, Isolation Level 1 TF-M TF-M Regression Test - IPC Mode, Isolation Level 2 TF-M