/****************************************Copyright (c)**************************************************** ** Guangzhou ZHIYUAN electronics Co.,LTD. ** ** http://www.embedtools.com ** **--------------File Info--------------------------------------------------------------------------------- ** File name: targetinit.c ** Latest modified Date: 2009-03-24 ** Latest Version: 1.0 ** Descriptions: 目标板部分初始化相关代码 ** **-------------------------------------------------------------------------------------------------------- ** Created by: Chenmingji ** Created date: 2009-03-24 ** Version: 1.0 ** Descriptions: The original version ** **-------------------------------------------------------------------------------------------------------- ** Modified by: ** Modified date: ** Version: ** Descriptions: ** *********************************************************************************************************/ #include "firmware\firmware.h" /********************************************************************************************************* 宏定义，用于配置总线 *********************************************************************************************************/ #define WAITWEN0 0x07 /* 配置EMCStaticWaitWen1 */ #define WAITOEN0 0x07 /* 配置EMCStaticWaitOen1 */ #define WAITRD0 0x1f /* 配置EMCStaticWaitRd1 */ #define WAITPAGE0 0x00 /* 配置EMCStaticWaitPage1 */ #define WAITWR0 0x1f /* 配置EMCStaticWaitWr1 */ #define WAITTURN0 0x0f /* 配置EMCStaticWaitTurn1 */ #define WAITWEN1 0x00 /* 配置EMCStaticWaitWen1 */ #define WAITOEN1 0x00 /* 配置EMCStaticWaitOen1 */ #define WAITRD1 0x02 /* 配置EMCStaticWaitRd1 */ #define WAITPAGE1 0x00 /* 配置EMCStaticWaitPage1 */ #define WAITWR1 0x04 /* 配置EMCStaticWaitWr1 */ #define WAITTURN1 0x00 /* 配置EMCStaticWaitTurn1 */ #define WAITWEN2 0x0F /* 配置EMCStaticWaitWen2 */ #define WAITOEN2 0x0F /* 配置EMCStaticWaitOen2 */ #define WAITRD2 0x0F /* 配置EMCStaticWaitRd2 */ #define WAITPAGE2 0x1F /* 配置EMCStaticWaitPage2 */ #define WAITWR2 0x0F /* 配置EMCStaticWaitWr2 */ #define WAITTURN2 0x0F /* 配置EMCStaticWaitTurn2 */ #define WAITWEN3 0x0F /* 配置EMCStaticWaitWen3 */ #define WAITOEN3 0x0F /* 配置EMCStaticWaitOen3 */ #define WAITRD3 0x0F /* 配置EMCStaticWaitRd3 */ #define WAITPAGE3 0x1F /* 配置EMCStaticWaitPage3 */ #define WAITWR3 0x0F /* 配置EMCStaticWaitWr3 */ #define WAITTURN3 0x0F /* 配置EMCStaticWaitTurn3 */ #define BCFG_08DEF 0x00000000 /* 8Bit Bus */ #define BCFG_16DEF 0x00000001 /* 16Bit Bus */ #define BCFG_32DEF 0x00000002 /* 32Bit Bus */ /********************************************************************************************************* SRAM总线配置设置 | 页模式 | 片选极性 |字节定位状态| 延长等待 | 写缓冲区 | 写保护 | | PM | PC | PB | EW | B | P | |0:禁能1:使能| 0:低 1:高 | |0:禁能1:使能|0:禁能1:使能|0:禁能1:使能| *********************************************************************************************************/ #define BCFG0 ( (0x00<<03) | (0x00<<06) | (0x01<<07) | (0x00<<8) | (0x00<<19) | (0x00<<20) ) #define BCFG1 ( (0x00<<03) | (0x00<<06) | (0x01<<07) | (0x00<<8) | (0x00<<19) | (0x00<<20) ) #define BCFG2 ( (0x00<<03) | (0x00<<06) | (0x01<<07) | (0x00<<8) | (0x00<<19) | (0x00<<20) ) #define BCFG3 ( (0x00<<03) | (0x00<<06) | (0x01<<07) | (0x00<<8) | (0x00<<19) | (0x00<<20) ) #define STATICCFG0 ( BCFG_16DEF | BCFG0 ) /* BANK0 */ #define STATICCFG1 ( BCFG_16DEF | BCFG1 ) /* BANK1 */ #define STATICCFG2 ( BCFG_16DEF | BCFG2 ) /* BANK2 */ #define STATICCFG3 ( BCFG_16DEF | BCFG3 ) /* BANK3 */ #ifndef __DEBUG_SDRAM /********************************************************************************************************* ** Function name: emcInit ** Descriptions: 初始化SDRAM ** input parameters: none ** Returned value: none ** Used global variables: none ** Created by: chenmingji ** Created Date: 2009-03-24 **------------------------------------------------------------------------------------------------------- ** Modified by: ** Modified date: **------------------------------------------------------------------------------------------------------- *********************************************************************************************************/ static void emcInit (void) { unsigned int ulTmp; int i; EMCControl = 0x01; /* 使能外部EMC */ EMCConfig = 0x00; /* * SRAM总线Bank0设置 */ EMCStaticConfig0 = STATICCFG0; EMCStaticWaitWen0 = WAITWEN0; EMCStaticWaitOen0 = WAITOEN0; EMCStaticWaitRd0 = WAITRD0; EMCStaticWaitPage0 = WAITPAGE0; EMCStaticWaitWr0 = WAITWR0; EMCStaticWaitTurn0 = WAITTURN0; /* * SRAM总线Bank1设置 */ EMCStaticConfig1 = STATICCFG1; EMCStaticWaitWen1 = WAITWEN1; EMCStaticWaitOen1 = WAITOEN1; EMCStaticWaitRd1 = WAITRD1; EMCStaticWaitPage1 = WAITPAGE1; EMCStaticWaitWr1 = WAITWR1; EMCStaticWaitTurn1 = WAITTURN1; /* * SRAM总线Bank2设置 */ EMCStaticConfig2 = STATICCFG2; EMCStaticWaitWen2 = WAITWEN2; EMCStaticWaitOen2 = WAITOEN2; EMCStaticWaitRd2 = WAITRD2; EMCStaticWaitPage2 = WAITPAGE2; EMCStaticWaitWr2 = WAITWR2; EMCStaticWaitTurn2 = WAITTURN2; /* * SRAM总线Bank3设置 */ EMCStaticConfig3 = STATICCFG3; EMCStaticWaitWen3 = WAITWEN3; EMCStaticWaitOen3 = WAITOEN3; EMCStaticWaitRd3 = WAITRD3; EMCStaticWaitPage3 = WAITPAGE3; EMCStaticWaitWr3 = WAITWR3; EMCStaticWaitTurn3 = WAITTURN3; /* * 关闭LCD控制器，禁止LCD的DMA传输 */ LCD_CTRL = 0x00; LCDCLK_CTRL = 0x00; #if 1 /* * 以下是初始化SDRAM访问的参数设置代码 */ SDRAMCLK_CTRL = 0x0001c000; EMCDynamicRP = 0x00000001; EMCDynamicRAS = 0x00000003; EMCDynamicSREX = 0x00000001; EMCDynamicWR = 0x00000002; EMCDynamicRC = 0x00000003; EMCDynamicRFC = 0x00000003; EMCDynamicXSR = 0x00000005; EMCDynamicRRD = 0x00000001; EMCDynamicMRD = 0x00000002; EMCDynamicCDLR = 0x00000006; EMCDynamicReadConfig = 0x00000011; /* * Default setting, * RAS latency 3 CCLKs, * CAS latenty 3 CCLKs. */ EMCDynamicRasCas0 = 0x00000303; /* * 512Mb, 16Mx32, * 4 banks, row=13, * column=9 */ EMCDynamicConfig0 = 0x00004680; /* Command delayed strategy */ for (i = 0; i < 0x80; i++) { } /* * Mem clock enable, * CLKOUT runs, send command: * NOP */ EMCDynamicControl = 0x00000183; for (i = 0; i < 0x80; i++) { } /* * Send command: * PRECHARGE-ALL, * shortest possible refresh period */ EMCDynamicControl = 0x00000103; for (i = 0; i < 0x80; i++) { } /* * set 32 CCLKs * between SDRAM refresh * cycles */ EMCDynamicRefresh = 0x00000002; for (i = 0; i < 0x80; i++) { /* wait 128 AHB clock cycles */ } /* * set 28 x 16CCLKs=448CCLK=7us * between SDRAM refresh * cycles */ EMCDynamicRefresh = 28; /* * To set mode register in SDRAM, * enter mode by issue MODE command, after finishing, * bailout and back to NORMAL mode. * Mem clock enable, CLKOUT runs, send command: MODE */ EMCDynamicControl = 0x00000083; ulTmp = *((volatile int *)(0x80060000)); EMCDynamicControl = 0x00000000; /* Send command: NORMAL */ for (i = 0; i < 0x80; i++) { } #endif /* 0 */ } #endif /********************************************************************************************************* ** Function name: targetResetInit ** Descriptions: 目标板最基础的初始化代码 ** input parameters: none ** Returned value: none ** Used global variables: none ** Created by: LinEnqiang ** Created Date: 2008-12-12 **------------------------------------------------------------------------------------------------------ ** Modified by: ** Modified date: **------------------------------------------------------------------------------------------------------ ********************************************************************************************************/ extern void reset(void); void targetResetInit (void) { #ifndef __IN_RAM INT8U i; INT32U *cp1,*cp2; cp1 = (INT32U*)reset; #ifdef __OUT_CHIP cp1 ++; #endif cp2 = (INT32U*)0x08000000; for(i=0;i<16;i++) { *cp2++ = *cp1++; } #endif #ifndef __DEBUG_SDRAM emcInit(); #endif BOOT_MAP = 0x01; /* * AHB 总线时钟配置 */ EMCAHBControl0 = 0x00000001; EMCAHBTimeout0 = 0x00000190; EMCAHBControl2 = 0x00000001; EMCAHBTimeout2 = 0x00000190; EMCAHBControl3 = 0x00000001; EMCAHBTimeout3 = 0x00000190; EMCAHBControl4 = 0x00000001; EMCAHBTimeout4 = 0x00000190; /* * 使能CPU工作在直接运行模式，不使用HCLK_PLL */ PWR_CTRL = 0x0012; #if USE_PLL397 == 1 PLL397_CTRL = 0x00; OSC_CTRL = 0x00; SYSCLK_CTRL = (0x50 << 2) | (0x01 << 1) ; while (0 == (PLL397_CTRL & 0x01) ) { if(0 != (PLL397_CTRL & (0x01 << 10))) { break; } } OSC_CTRL = 0x03; #else SYSCLK_CTRL = (0x50 << 2) | (0x00 << 0) ; OSC_CTRL = 0x00; #endif /* USE_PLL397 */ #if (Fcco / Fcclk) == 1 HCLKPLL_CTRL = ((1 << 16) | /* PLL 在操作模式 */ (0 << 15) | /* 正常PLL 操作 */ (1 << 14) | /* 旁路后置分频器 */ (1 << 13) | /* 后置分频器输出反馈 */ (0 << 11) | /* P(无效) */ (0 << 9) | /* N */ (((Fcclk / Fosc) - 1) << 1)); /* M */ #endif /* (Fcco / Fcclk) */ #if (Fcco / Fcclk) == 2 HCLKPLL_CTRL = ((1 << 16) | /* PLL 在操作模式 */ (0 << 15) | /* 正常PLL 操作 */ (0 << 14) | /* 使用后置分频器 */ (1 << 13) | /* 后置分频器输出反馈 */ (0 << 11) | /* P(有效) */ (0 << 9) | /* N */ (((Fcclk / Fosc) - 1) << 1)); /* M */ #endif /* (Fcco / Fcclk) */ #if (Fcco / Fcclk) == 4 HCLKPLL_CTRL = ((1 << 16) | /* PLL 在操作模式 */ (0 << 15) | /* 正常PLL 操作 */ (0 << 14) | /* 使用后置分频器 */ (1 << 13) | /* 后置分频器输出反馈 */ (1 << 11) | /* P(有效) */ (0 << 9) | /* N */ (((Fcclk / Fosc) - 1) << 1)); /* M */ #endif /* (Fcco / Fcclk) */ #if (Fcco / Fcclk) == 8 HCLKPLL_CTRL = ((1 << 16) | /* PLL 在操作模式 */ (0 << 15) | /* 正常PLL 操作 */ (0 << 14) | /* 使用后置分频器 */ (1 << 13) | /* 后置分频器输出反馈 */ (2 << 11) | /* P(有效) */ (0 << 9) | /* N */ (((Fcclk / Fosc) - 1) << 1)); /* M */ #endif /* (Fcco / Fcclk) */ #if (Fcco / Fcclk) == 16 HCLKPLL_CTRL = ((1 << 16) | /* PLL 在操作模式 */ (0 << 15) | /* 正常PLL 操作 */ (0 << 14) | /* 使用后置分频器 */ (1 << 13) | /* 后置分频器输出反馈 */ (3 << 11) | /* P(有效) */ (0 << 9) | /* N */ (((Fcclk / Fosc) - 1) << 1)); /* M */ #endif /* (Fcco / Fcclk) */ while (!(HCLKPLL_CTRL & 0x01)) { ; } #if (Fdclk != 0) HCLKDIV_CTRL = (((Fcclk / Fdclk) & 0x03) << 7) | ((((Fcclk / Fpclk) - 1) & 0x1F) << 2)| (((Fcclk / Fhclk / 2) & 0x03) << 0); #else HCLKDIV_CTRL = ((((Fcclk / Fpclk) - 1) & 0x1F) << 2)| (((Fcclk / Fhclk / 2) & 0x03) << 0); #endif /* Fdclk */ PWR_CTRL |= ( 1 << 2 ); /* 正常RUN 模式。ARM, HCLK 由 */ /* PLL输出提供时钟源 */ return; } /********************************************************************************************************* END FILE *********************************************************************************************************/