; --------------------------------------------------------------------------------
; @Title: Peripherial description for TUNDSA TSI108
; @Props: 
; @Author: -
; @Description:
;north bridge (i.e. SDRAM, Ethernet controller etc...)
;used for PowerPC host processors (MPC74XX)
; @Changelog:
; @Manufacturer:
; @Doc:
; @Core:
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pertsi108.per 5901 2015-01-09 12:29:12Z askoncej $
config 16. 8.
width 24.
;base address (may be changed by application)
base ANC:0xC0000000
tree "HLP Interface"
config 16. 8.
width 24.
config 16. 8.
width 24.
group (0x0000+0x00+0x00)++3
line.long  0. "HLP_B0_ADDR,HLP_B0_ADDR Register"
group (0x0000+0x00+0x04)++3
line.long  0. "HLP_B0_MASK,HLP_B0_MASK Register"
group (0x0000+0x00+0x08)++3
line.long  0. "HLP_B0_CTRL0,HLP_B0_CTRL0 Register"
group (0x0000+0x00+0x0C)++3
line.long  0. "HLP_B0_CTRL1,HLP_B0_CTRL1 Register"
TEXTLINE ""
config 16. 8.
width 24.
group (0x0000+0x10+0x00)++3
line.long  0. "HLP_B1_ADDR,HLP_B1_ADDR Register"
group (0x0000+0x10+0x04)++3
line.long  0. "HLP_B1_MASK,HLP_B1_MASK Register"
group (0x0000+0x10+0x08)++3
line.long  0. "HLP_B1_CTRL0,HLP_B1_CTRL0 Register"
group (0x0000+0x10+0x0C)++3
line.long  0. "HLP_B1_CTRL1,HLP_B1_CTRL1 Register"
TEXTLINE ""
config 16. 8.
width 24.
group (0x0000+0x20+0x00)++3
line.long  0. "HLP_B2_ADDR,HLP_B2_ADDR Register"
group (0x0000+0x20+0x04)++3
line.long  0. "HLP_B2_MASK,HLP_B2_MASK Register"
group (0x0000+0x20+0x08)++3
line.long  0. "HLP_B2_CTRL0,HLP_B2_CTRL0 Register"
group (0x0000+0x20+0x0C)++3
line.long  0. "HLP_B2_CTRL1,HLP_B2_CTRL1 Register"
TEXTLINE ""
config 16. 8.
width 24.
group (0x0000+0x30+0x00)++3
line.long  0. "HLP_B3_ADDR,HLP_B3_ADDR Register"
group (0x0000+0x30+0x04)++3
line.long  0. "HLP_B3_MASK,HLP_B3_MASK Register"
group (0x0000+0x30+0x08)++3
line.long  0. "HLP_B3_CTRL0,HLP_B3_CTRL0 Register"
group (0x0000+0x30+0x0C)++3
line.long  0. "HLP_B3_CTRL1,HLP_B3_CTRL1 Register"
TEXTLINE ""
group (0x0000+0x40)++3
line.long  0. "HLP_DATA_SWAP_CTRL,HLP Data Swap Control Register"
bitfld.long 0. 0.--1.      "DATA_SWAP  , HLP data swap control" "off,byte,word,byte+word"
group (0x0000+0x44)++3
line.long  0. "HLP_ERR,HLP Error Register"
hexmask.long.byte 0. 08.--15. 1. "ERR_MSG"
bitfld.long 0. 1.        "INT_EN     , Interrupt enable" "0,1"
bitfld.long 0. 0.      "  TEA        , Indicates an error occurred in the access" "0,1"

tree.end
tree "PCI/X Interface"
config 16. 8.
width 24.
tree "PCI registers"
group (0x1000)++3
line.long  0x0 "PE_ID,PCI ID Register"
group (0x1000+0x04)++3
line.long  0x0 "PE_CSR,PCI Control and Status Register"
group (0x1000+0x08)++3
line.long  0x0 "PE_CLASS,PCI Class Register"
group (0x1000+0x0c)++3
line.long  0x0 "PE_MISC0,PCI Miscellaneous 0 Register"
group (0x1000+0x10)++3
line.long  0x0 "P2O_BAR0,PCI Base Address Register 0"
group (0x1000+0x14)++3
line.long  0x0 "P2O_BAR0_UPPER,PCI Base Address Register 0 Upper"
group (0x1000+0x18)++3
line.long  0x0 "P2O_BAR2,PCI Base Address Register 2"
group (0x1000+0x1c)++3
line.long  0x0 "P2O_BAR2_UPPER,PCI Base Address Register 2 Upper"
group (0x1000+0x20)++3
line.long  0x0 "P2O_BAR3,PCI Base Address Register 3"
group (0x1000+0x24)++3
line.long  0x0 "P2O_BAR3_UPPER,PCI Base Address Register 3 Upper"
group (0x1000+0x2c)++3
line.long  0x0 "PE_SID,PCI Subsystem ID Register"
group (0x1000+0x30)++3
line.long  0x0 "PE_EROM,PCI Expansion ROM Register"
group (0x1000+0x34)++3
line.long  0x0 "PE_CAP,PCI Capability Pointer Register"
group (0x1000+0x3c)++3
line.long  0x0 "PE_MISC2,PCI Miscellaneous 2 Register"
tree.end
tree "PCI Device-specific registers"
group (0x1000+0x40)++3
line.long  0x0 "MISC_CSR,Miscellaneous Control and Status Register"
group (0x1000+0x44)++3
line.long  0x0 "SERR_DIS,PCI SERRn Disable Register"
group (0x1000+0x48)++3
line.long  0x0 "SERR_STAT,PCI SERRn Status Register"
group (0x1000+0x4c)++3
line.long  0x0 "P2O_PAGE_SIZES,PCI Page Size Register"
group (0x1000+0x50)++3
line.long  0x0 "P_VPD_CSR,PCI VPD Control and Status Register"
tree.end
tree "PCI Capability list registers"
group (0x1000+0xc8)++3
line.long  0x0 "P_SLOT_ID,PCI Slot Identification Capabilities Register"
group (0x1000+0xcc)++3
line.long  0x0 "P_PMC,PCI Power Management Capabilities Register"
group (0x1000+0xd0)++3
line.long  0x0 "P_PMCS,PCI Power Management Control and Status Register"
group (0x1000+0xd4)++3
line.long  0x0 "P_HS_CSR,PCI Compact PCI Hot Swap Control and Status Register"
group (0x1000+0xd8)++3
line.long  0x0 "P_VPDC,PCI Vital Product Data Capability Register"
group (0x1000+0xdc)++3
line.long  0x0 "P_VPDD,PCI Vital Product Data Register"
group (0x1000+0xe0)++3
line.long  0x0 "P_MSIC,PCI Message Signaled Interrupt Control Capability Register"
group (0x1000+0xe4)++3
line.long  0x0 "P_MSIA,PCI Message Signaled Interrupt Address Register"
group (0x1000+0xe8)++3
line.long  0x0 "P_MSIA_UPPER,PCI Message Signaled Interrupt Address Upper Register"
group (0x1000+0xec)++3
line.long  0x0 "P_MSID,PCI Message Signaled Interrupt Data Register"
group (0x1000+0xf0)++3
line.long  0x0 "P_PCI/X_C,PCI-X Capability Register"
group (0x1000+0xf4)++3
line.long  0x0 "P_PCI/X_S,PCI-X Status Register"
tree.end
tree "PCI Miscellaneous registers"
group (0x1000+0x10C)++3
line.long  0x0 "ARB_CTRL,PCI Arbiter Control and Status Register"
TEXTLINE ""    
group (0x1000+0x180)++3
line.long  0x0 "IRP_CFG_CTL,Interrupt Control Register"
group (0x1000+0x184)++3
line.long  0x0 "IRP_STAT,Interrupt Status Register"
group (0x1000+0x188)++3
line.long  0x0 "IRP_ENABLE,Interrupt Enable Register"
group (0x1000+0x18C)++3
line.long  0x0 "IRP_INTAD,PCI Interrupt CSR"
group (0x1000+0x19C)++3
TEXTLINE ""    
line.long  0x0 "P_VID_OVERRIDE,PCI Vendor ID Override Register"
group (0x1000+0x1A0)++3
line.long  0x0 "P_CLASS_OVERRIDE,PCI Class Override Register"
group (0x1000+0x1A4)++3
line.long  0x0 "PE_SID_OVERRIDE,PCI SID Override Register"
group (0x1000+0x1A8)++3
line.long  0x0 "P_SLOT_ID_OVERRIDE,PCI Slot ID Override Register"
tree.end
tree "Switch Fabric registers"
group (0x1000+0x200)++3
line.long  0x0 "PFAB_CSR,PFAB Control and Status Register"
group (0x1000+0x204)++3
line.long  0x0 "PFAB_BAR0,PFAB_BAR0 Register"
group (0x1000+0x208)++3
line.long  0x0 "PFAB_BAR0_UPPER,PFAB_BAR0_UPPER Register"
group (0x1000+0x20C)++3
line.long  0x0 "PFAB_IO,PFAB_IO Base Address Register"
group (0x1000+0x210)++3
line.long  0x0 "PFAB_IO_UPPER,PFAB_IO_UPPER Register"
group (0x1000+0x214)++3
line.long  0x0 "PFAB_MEM32,PFAB_MEM32 Base Address Register"
group (0x1000+0x218)++3
line.long  0x0 "PFAB_MEM32_REMAP,PFAB_MEM32_REMAP Register"
group (0x1000+0x21C)++3
line.long  0x0 "PFAB_MEM32_MASK,PFAB_MEM32_MASK Register"
TEXTLINE ""    
group (0x1000+0x220)++3
line.long  0x0 "PFAB_PFM3,PFAB_PFM3 Base Address Register"
group (0x1000+0x224)++3
line.long  0x0 "PFAB_PFM3_REMAP_UPPER,PFAB_PFM3_REMAP_UPPER Register"
group (0x1000+0x228)++3
line.long  0x0 "PFAB_PFM3_REMAP_LOWER,PFAB_PFM3_REMAP_LOWER Register"
group (0x1000+0x22C)++3
line.long  0x0 "PFAB_PFM3_MASK,PFAB_PFM3_MASK Register"
TEXTLINE ""    
group (0x1000+0x230)++3
line.long  0x0 "PFAB_PFM4,PFAB_PFM4 Base Address Register"
group (0x1000+0x234)++3
line.long  0x0 "PFAB_PFM4_REMAP_UPPER,PFAB_PFM4_REMAP_UPPER Register"
group (0x1000+0x238)++3
line.long  0x0 "PFAB_PFM4_REMAP_LOWER,PFAB_PFM4_REMAP_LOWER Register"
group (0x1000+0x23C)++3
line.long  0x0 "PFAB_PFM4_MASK,PFAB_PFM4_MASK Register"
TEXTLINE ""    
group (0x1000+0x240)++3
line.long  0x0 "PFAB_SYNC_BAR,PFAB_SYNC_BAR Register"
group (0x1000+0x244)++3
line.long  0x0 "PFAB_SYNC_BAR_UPPER,PFAB_SYNC_BAR_UPPER Register"
TEXTLINE ""    
group (0x1000+0x2FC)++3
line.long  0x0 "EROM_MAP,Expansion ROM Map Register"
tree.end
tree "PCI BAR2 Lookup Table"
config 16. 8.
width 24.
group (0x500)++7
line.long  0x0 "P2O_BAR2_LUT00,P2O_BAR2_LUT00 Register"
line.long  0x4 "P2O_BAR2_LUT00_U,P2O_BAR2_LUT00 Upper Register"
config 16. 8.
width 24.
group (0x508)++7
line.long  0x0 "P2O_BAR2_LUT01,P2O_BAR2_LUT01 Register"
line.long  0x4 "P2O_BAR2_LUT01_U,P2O_BAR2_LUT01 Upper Register"
config 16. 8.
width 24.
group (0x510)++7
line.long  0x0 "P2O_BAR2_LUT02,P2O_BAR2_LUT02 Register"
line.long  0x4 "P2O_BAR2_LUT02_U,P2O_BAR2_LUT02 Upper Register"
config 16. 8.
width 24.
group (0x518)++7
line.long  0x0 "P2O_BAR2_LUT03,P2O_BAR2_LUT03 Register"
line.long  0x4 "P2O_BAR2_LUT03_U,P2O_BAR2_LUT03 Upper Register"
config 16. 8.
width 24.
group (0x520)++7
line.long  0x0 "P2O_BAR2_LUT04,P2O_BAR2_LUT04 Register"
line.long  0x4 "P2O_BAR2_LUT04_U,P2O_BAR2_LUT04 Upper Register"
config 16. 8.
width 24.
group (0x528)++7
line.long  0x0 "P2O_BAR2_LUT05,P2O_BAR2_LUT05 Register"
line.long  0x4 "P2O_BAR2_LUT05_U,P2O_BAR2_LUT05 Upper Register"
config 16. 8.
width 24.
group (0x530)++7
line.long  0x0 "P2O_BAR2_LUT06,P2O_BAR2_LUT06 Register"
line.long  0x4 "P2O_BAR2_LUT06_U,P2O_BAR2_LUT06 Upper Register"
config 16. 8.
width 24.
group (0x538)++7
line.long  0x0 "P2O_BAR2_LUT07,P2O_BAR2_LUT07 Register"
line.long  0x4 "P2O_BAR2_LUT07_U,P2O_BAR2_LUT07 Upper Register"
config 16. 8.
width 24.
group (0x540)++7
line.long  0x0 "P2O_BAR2_LUT08,P2O_BAR2_LUT08 Register"
line.long  0x4 "P2O_BAR2_LUT08_U,P2O_BAR2_LUT08 Upper Register"
config 16. 8.
width 24.
group (0x548)++7
line.long  0x0 "P2O_BAR2_LUT09,P2O_BAR2_LUT09 Register"
line.long  0x4 "P2O_BAR2_LUT09_U,P2O_BAR2_LUT09 Upper Register"
config 16. 8.
width 24.
group (0x550)++7
line.long  0x0 "P2O_BAR2_LUT10,P2O_BAR2_LUT10 Register"
line.long  0x4 "P2O_BAR2_LUT10_U,P2O_BAR2_LUT10 Upper Register"
config 16. 8.
width 24.
group (0x558)++7
line.long  0x0 "P2O_BAR2_LUT11,P2O_BAR2_LUT11 Register"
line.long  0x4 "P2O_BAR2_LUT11_U,P2O_BAR2_LUT11 Upper Register"
config 16. 8.
width 24.
group (0x560)++7
line.long  0x0 "P2O_BAR2_LUT12,P2O_BAR2_LUT12 Register"
line.long  0x4 "P2O_BAR2_LUT12_U,P2O_BAR2_LUT12 Upper Register"
config 16. 8.
width 24.
group (0x568)++7
line.long  0x0 "P2O_BAR2_LUT13,P2O_BAR2_LUT13 Register"
line.long  0x4 "P2O_BAR2_LUT13_U,P2O_BAR2_LUT13 Upper Register"
config 16. 8.
width 24.
group (0x570)++7
line.long  0x0 "P2O_BAR2_LUT14,P2O_BAR2_LUT14 Register"
line.long  0x4 "P2O_BAR2_LUT14_U,P2O_BAR2_LUT14 Upper Register"
config 16. 8.
width 24.
group (0x578)++7
line.long  0x0 "P2O_BAR2_LUT15,P2O_BAR2_LUT15 Register"
line.long  0x4 "P2O_BAR2_LUT15_U,P2O_BAR2_LUT15 Upper Register"
config 16. 8.
width 24.
group (0x580)++7
line.long  0x0 "P2O_BAR2_LUT16,P2O_BAR2_LUT16 Register"
line.long  0x4 "P2O_BAR2_LUT16_U,P2O_BAR2_LUT16 Upper Register"
config 16. 8.
width 24.
group (0x588)++7
line.long  0x0 "P2O_BAR2_LUT17,P2O_BAR2_LUT17 Register"
line.long  0x4 "P2O_BAR2_LUT17_U,P2O_BAR2_LUT17 Upper Register"
config 16. 8.
width 24.
group (0x590)++7
line.long  0x0 "P2O_BAR2_LUT18,P2O_BAR2_LUT18 Register"
line.long  0x4 "P2O_BAR2_LUT18_U,P2O_BAR2_LUT18 Upper Register"
config 16. 8.
width 24.
group (0x598)++7
line.long  0x0 "P2O_BAR2_LUT19,P2O_BAR2_LUT19 Register"
line.long  0x4 "P2O_BAR2_LUT19_U,P2O_BAR2_LUT19 Upper Register"
config 16. 8.
width 24.
group (0x5a0)++7
line.long  0x0 "P2O_BAR2_LUT20,P2O_BAR2_LUT20 Register"
line.long  0x4 "P2O_BAR2_LUT20_U,P2O_BAR2_LUT20 Upper Register"
config 16. 8.
width 24.
group (0x5a8)++7
line.long  0x0 "P2O_BAR2_LUT21,P2O_BAR2_LUT21 Register"
line.long  0x4 "P2O_BAR2_LUT21_U,P2O_BAR2_LUT21 Upper Register"
config 16. 8.
width 24.
group (0x5b0)++7
line.long  0x0 "P2O_BAR2_LUT22,P2O_BAR2_LUT22 Register"
line.long  0x4 "P2O_BAR2_LUT22_U,P2O_BAR2_LUT22 Upper Register"
config 16. 8.
width 24.
group (0x5b8)++7
line.long  0x0 "P2O_BAR2_LUT23,P2O_BAR2_LUT23 Register"
line.long  0x4 "P2O_BAR2_LUT23_U,P2O_BAR2_LUT23 Upper Register"
config 16. 8.
width 24.
group (0x5c0)++7
line.long  0x0 "P2O_BAR2_LUT24,P2O_BAR2_LUT24 Register"
line.long  0x4 "P2O_BAR2_LUT24_U,P2O_BAR2_LUT24 Upper Register"
config 16. 8.
width 24.
group (0x5c8)++7
line.long  0x0 "P2O_BAR2_LUT25,P2O_BAR2_LUT25 Register"
line.long  0x4 "P2O_BAR2_LUT25_U,P2O_BAR2_LUT25 Upper Register"
config 16. 8.
width 24.
group (0x5d0)++7
line.long  0x0 "P2O_BAR2_LUT26,P2O_BAR2_LUT26 Register"
line.long  0x4 "P2O_BAR2_LUT26_U,P2O_BAR2_LUT26 Upper Register"
config 16. 8.
width 24.
group (0x5d8)++7
line.long  0x0 "P2O_BAR2_LUT27,P2O_BAR2_LUT27 Register"
line.long  0x4 "P2O_BAR2_LUT27_U,P2O_BAR2_LUT27 Upper Register"
config 16. 8.
width 24.
group (0x5e0)++7
line.long  0x0 "P2O_BAR2_LUT28,P2O_BAR2_LUT28 Register"
line.long  0x4 "P2O_BAR2_LUT28_U,P2O_BAR2_LUT28 Upper Register"
config 16. 8.
width 24.
group (0x5e8)++7
line.long  0x0 "P2O_BAR2_LUT29,P2O_BAR2_LUT29 Register"
line.long  0x4 "P2O_BAR2_LUT29_U,P2O_BAR2_LUT29 Upper Register"
config 16. 8.
width 24.
group (0x5f0)++7
line.long  0x0 "P2O_BAR2_LUT30,P2O_BAR2_LUT30 Register"
line.long  0x4 "P2O_BAR2_LUT30_U,P2O_BAR2_LUT30 Upper Register"
config 16. 8.
width 24.
group (0x5f8)++7
line.long  0x0 "P2O_BAR2_LUT31,P2O_BAR2_LUT31 Register"
line.long  0x4 "P2O_BAR2_LUT31_U,P2O_BAR2_LUT31 Upper Register"
tree.end
tree "PCI BAR3 Lookup Table"
config 16. 8.
width 24.
group (0x600)++7
line.long  0x0 "P2O_BAR3_LUT00,P2O_BAR3_LUT00 Register"
line.long  0x4 "P2O_BAR3_LUT00_U,P2O_BAR3_LUT00 Upper Register"
config 16. 8.
width 24.
group (0x608)++7
line.long  0x0 "P2O_BAR3_LUT01,P2O_BAR3_LUT01 Register"
line.long  0x4 "P2O_BAR3_LUT01_U,P2O_BAR3_LUT01 Upper Register"
config 16. 8.
width 24.
group (0x610)++7
line.long  0x0 "P2O_BAR3_LUT02,P2O_BAR3_LUT02 Register"
line.long  0x4 "P2O_BAR3_LUT02_U,P2O_BAR3_LUT02 Upper Register"
config 16. 8.
width 24.
group (0x618)++7
line.long  0x0 "P2O_BAR3_LUT03,P2O_BAR3_LUT03 Register"
line.long  0x4 "P2O_BAR3_LUT03_U,P2O_BAR3_LUT03 Upper Register"
config 16. 8.
width 24.
group (0x620)++7
line.long  0x0 "P2O_BAR3_LUT04,P2O_BAR3_LUT04 Register"
line.long  0x4 "P2O_BAR3_LUT04_U,P2O_BAR3_LUT04 Upper Register"
config 16. 8.
width 24.
group (0x628)++7
line.long  0x0 "P2O_BAR3_LUT05,P2O_BAR3_LUT05 Register"
line.long  0x4 "P2O_BAR3_LUT05_U,P2O_BAR3_LUT05 Upper Register"
config 16. 8.
width 24.
group (0x630)++7
line.long  0x0 "P2O_BAR3_LUT06,P2O_BAR3_LUT06 Register"
line.long  0x4 "P2O_BAR3_LUT06_U,P2O_BAR3_LUT06 Upper Register"
config 16. 8.
width 24.
group (0x638)++7
line.long  0x0 "P2O_BAR3_LUT07,P2O_BAR3_LUT07 Register"
line.long  0x4 "P2O_BAR3_LUT07_U,P2O_BAR3_LUT07 Upper Register"
config 16. 8.
width 24.
group (0x640)++7
line.long  0x0 "P2O_BAR3_LUT08,P2O_BAR3_LUT08 Register"
line.long  0x4 "P2O_BAR3_LUT08_U,P2O_BAR3_LUT08 Upper Register"
config 16. 8.
width 24.
group (0x648)++7
line.long  0x0 "P2O_BAR3_LUT09,P2O_BAR3_LUT09 Register"
line.long  0x4 "P2O_BAR3_LUT09_U,P2O_BAR3_LUT09 Upper Register"
config 16. 8.
width 24.
group (0x650)++7
line.long  0x0 "P2O_BAR3_LUT10,P2O_BAR3_LUT10 Register"
line.long  0x4 "P2O_BAR3_LUT10_U,P2O_BAR3_LUT10 Upper Register"
config 16. 8.
width 24.
group (0x658)++7
line.long  0x0 "P2O_BAR3_LUT11,P2O_BAR3_LUT11 Register"
line.long  0x4 "P2O_BAR3_LUT11_U,P2O_BAR3_LUT11 Upper Register"
config 16. 8.
width 24.
group (0x660)++7
line.long  0x0 "P2O_BAR3_LUT12,P2O_BAR3_LUT12 Register"
line.long  0x4 "P2O_BAR3_LUT12_U,P2O_BAR3_LUT12 Upper Register"
config 16. 8.
width 24.
group (0x668)++7
line.long  0x0 "P2O_BAR3_LUT13,P2O_BAR3_LUT13 Register"
line.long  0x4 "P2O_BAR3_LUT13_U,P2O_BAR3_LUT13 Upper Register"
config 16. 8.
width 24.
group (0x670)++7
line.long  0x0 "P2O_BAR3_LUT14,P2O_BAR3_LUT14 Register"
line.long  0x4 "P2O_BAR3_LUT14_U,P2O_BAR3_LUT14 Upper Register"
config 16. 8.
width 24.
group (0x678)++7
line.long  0x0 "P2O_BAR3_LUT15,P2O_BAR3_LUT15 Register"
line.long  0x4 "P2O_BAR3_LUT15_U,P2O_BAR3_LUT15 Upper Register"
config 16. 8.
width 24.
group (0x680)++7
line.long  0x0 "P2O_BAR3_LUT16,P2O_BAR3_LUT16 Register"
line.long  0x4 "P2O_BAR3_LUT16_U,P2O_BAR3_LUT16 Upper Register"
config 16. 8.
width 24.
group (0x688)++7
line.long  0x0 "P2O_BAR3_LUT17,P2O_BAR3_LUT17 Register"
line.long  0x4 "P2O_BAR3_LUT17_U,P2O_BAR3_LUT17 Upper Register"
config 16. 8.
width 24.
group (0x690)++7
line.long  0x0 "P2O_BAR3_LUT18,P2O_BAR3_LUT18 Register"
line.long  0x4 "P2O_BAR3_LUT18_U,P2O_BAR3_LUT18 Upper Register"
config 16. 8.
width 24.
group (0x698)++7
line.long  0x0 "P2O_BAR3_LUT19,P2O_BAR3_LUT19 Register"
line.long  0x4 "P2O_BAR3_LUT19_U,P2O_BAR3_LUT19 Upper Register"
config 16. 8.
width 24.
group (0x6a0)++7
line.long  0x0 "P2O_BAR3_LUT20,P2O_BAR3_LUT20 Register"
line.long  0x4 "P2O_BAR3_LUT20_U,P2O_BAR3_LUT20 Upper Register"
config 16. 8.
width 24.
group (0x6a8)++7
line.long  0x0 "P2O_BAR3_LUT21,P2O_BAR3_LUT21 Register"
line.long  0x4 "P2O_BAR3_LUT21_U,P2O_BAR3_LUT21 Upper Register"
config 16. 8.
width 24.
group (0x6b0)++7
line.long  0x0 "P2O_BAR3_LUT22,P2O_BAR3_LUT22 Register"
line.long  0x4 "P2O_BAR3_LUT22_U,P2O_BAR3_LUT22 Upper Register"
config 16. 8.
width 24.
group (0x6b8)++7
line.long  0x0 "P2O_BAR3_LUT23,P2O_BAR3_LUT23 Register"
line.long  0x4 "P2O_BAR3_LUT23_U,P2O_BAR3_LUT23 Upper Register"
config 16. 8.
width 24.
group (0x6c0)++7
line.long  0x0 "P2O_BAR3_LUT24,P2O_BAR3_LUT24 Register"
line.long  0x4 "P2O_BAR3_LUT24_U,P2O_BAR3_LUT24 Upper Register"
config 16. 8.
width 24.
group (0x6c8)++7
line.long  0x0 "P2O_BAR3_LUT25,P2O_BAR3_LUT25 Register"
line.long  0x4 "P2O_BAR3_LUT25_U,P2O_BAR3_LUT25 Upper Register"
config 16. 8.
width 24.
group (0x6d0)++7
line.long  0x0 "P2O_BAR3_LUT26,P2O_BAR3_LUT26 Register"
line.long  0x4 "P2O_BAR3_LUT26_U,P2O_BAR3_LUT26 Upper Register"
config 16. 8.
width 24.
group (0x6d8)++7
line.long  0x0 "P2O_BAR3_LUT27,P2O_BAR3_LUT27 Register"
line.long  0x4 "P2O_BAR3_LUT27_U,P2O_BAR3_LUT27 Upper Register"
config 16. 8.
width 24.
group (0x6e0)++7
line.long  0x0 "P2O_BAR3_LUT28,P2O_BAR3_LUT28 Register"
line.long  0x4 "P2O_BAR3_LUT28_U,P2O_BAR3_LUT28 Upper Register"
config 16. 8.
width 24.
group (0x6e8)++7
line.long  0x0 "P2O_BAR3_LUT29,P2O_BAR3_LUT29 Register"
line.long  0x4 "P2O_BAR3_LUT29_U,P2O_BAR3_LUT29 Upper Register"
config 16. 8.
width 24.
group (0x6f0)++7
line.long  0x0 "P2O_BAR3_LUT30,P2O_BAR3_LUT30 Register"
line.long  0x4 "P2O_BAR3_LUT30_U,P2O_BAR3_LUT30 Upper Register"
config 16. 8.
width 24.
group (0x6f8)++7
line.long  0x0 "P2O_BAR3_LUT31,P2O_BAR3_LUT31 Register"
line.long  0x4 "P2O_BAR3_LUT31_U,P2O_BAR3_LUT31 Upper Register"
tree.end
tree.end
tree "Clock Generator"
config 16. 8.
width 24.
group (0x2000+0x200)++3
line.long  0x0 "CG_INT_STATUS,Clock Generator Interrupt Status Register"
group (0x2000+0x204)++3
line.long  0x0 "CG_INT_SET,Clock Generator Interrupt Set Register"
group (0x2000+0x208)++3
line.long  0x0 "CG_INT_CTRL,Clock Generator Interrupt Control Register"
group (0x2000+0x20c)++3
line.long  0x0 "CG_CLK_CTRL,Clock Generator Clock Control Register"
group (0x2000+0x210)++3
line.long  0x0 "CG_PLL0_CTRL0,Clock Generator PLL0 Control Register 0"
group (0x2000+0x214)++3
line.long  0x0 "CG_PLL0_CTRL1,Clock Generator PLL0 Control Register 1"
group (0x2000+0x220)++3
line.long  0x0 "CG_PLL1_CTRL0,Clock Generator PLL1 Control Register 0"
group (0x2000+0x224)++3
line.long  0x0 "CG_PLL1_CTRL1,Clock Generator PLL1 Control Register 1"
group (0x2000+0x230)++3
line.long  0x0 "CG_IO_CTRL,Clock Generator Output Control Register"
group (0x2000+0x234)++3
line.long  0x0 "CG_PWRUP_STATUS,Clock Generator Power-up Option Status Register"
group (0x2000+0x240)++3
line.long  0x0 "CG_PVT_CTRL,Clock Generator PVT Control Register"

tree.end
tree "Processor Interface"
config 16. 8.
width 24.
group (0x3000)++3
line.long  0x0 "PB_ID,PB Identification Register"
group (0x3000+0x04)++3
line.long  0x0 "PB_RSR,PB Reset Control and Status Register"
group (0x3000+0x8)++3
line.long  0x0 "PB_BUS_MS_SELECT,PB Bus Master Select Register"
group (0x3000+0xc)++3
line.long  0x0 "PB_ISR,PB Interrupt Status Register"
group (0x3000+0x10)++3
line.long  0x0 "PB_IER,PB Interrupt Enable Register"
group (0x3000+0x14)++3
line.long  0x0 "PB_INT_SET,PB Interrupt Set Register"
group (0x3000+0x18)++3
line.long  0x0 "PB_ARB_CTRL,PB Arbiter Control Register"
group (0x3000+0x1c)++3
line.long  0x0 "PB_PWR_CTRL,PB Power Management Control Register"
group (0x3000+0x20)++3
line.long  0x0 "PB_SCRATCH_PAD,PB Scratch Pad Register"
group (0x3000+0x30)++3
line.long  0x0 "PB_PVT_CTRL1,PB PVT Control 1 Register"
group (0x3000+0x34)++3
line.long  0x0 "PB_PVT_CTRL2,PB PVT Control 2 Register"
group (0x3000+0x38)++3
line.long  0x0 "PB_PVT_S,PB PVT Status Register"
TEXTLINE ""  
group (0x3000+0x400)++3
line.long  0x0 "PB_SCR,PB Slave Configuration Register"
group (0x3000+0x404)++3
line.long  0x0 "PB_ERRCS,PB Error Log Register"
group (0x3000+0x408)++3
line.long  0x0 "PB_AERR,PB Address Error Log"
group (0x3000+0x410)++3
line.long  0x0 "PB_REG_BAR,PB Register Base Address Register"
group (0x3000+0x414)++3
line.long  0x0 "PB_OCN_BAR1,PB Switch Fabric Base Address Register 1"
group (0x3000+0x418)++3
line.long  0x0 "PB_OCN_BAR2,PB Switch Fabric Base Address Register 2"
group (0x3000+0x41c)++3
line.long  0x0 "PB_SDRAM_BAR1,PB SDRAM Base Address Register 1"
group (0x3000+0x420)++3
line.long  0x0 "PB_SDRAM_BAR2,PB SDRAM Base Address Register 2"
group (0x3000+0x424)++3
line.long  0x0 "PB_OCN_SYNC_DATA,PB Slave Switch Fabric Sync Packet Data Register"
group (0x3000+0x428)++3
line.long  0x0 "PB_OCN_SYNC_GEN,PB Slave Switch Fabric Sync Packet Generation Register"
TEXTLINE ""  
group (0x3000+0xc00)++3
line.long  0x0 "PB_MCR,PB Master Configuration Register"
group (0x3000+0xc04)++3
line.long  0x0 "PB_MCMD,PB Master Command Register"
TEXTLINE ""  
tree "Fabric BAR 1 Lookup Table Registers"
config 16. 8.
width 24.
group (0x800)++7
line.long  0x0 "PB_BAR1_LUT_ADDR00,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR00_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x808)++7
line.long  0x0 "PB_BAR1_LUT_ADDR01,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR01_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x810)++7
line.long  0x0 "PB_BAR1_LUT_ADDR02,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR02_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x818)++7
line.long  0x0 "PB_BAR1_LUT_ADDR03,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR03_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x820)++7
line.long  0x0 "PB_BAR1_LUT_ADDR04,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR04_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x828)++7
line.long  0x0 "PB_BAR1_LUT_ADDR05,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR05_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x830)++7
line.long  0x0 "PB_BAR1_LUT_ADDR06,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR06_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x838)++7
line.long  0x0 "PB_BAR1_LUT_ADDR07,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR07_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x840)++7
line.long  0x0 "PB_BAR1_LUT_ADDR08,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR08_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x848)++7
line.long  0x0 "PB_BAR1_LUT_ADDR09,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR09_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x850)++7
line.long  0x0 "PB_BAR1_LUT_ADDR10,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR10_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x858)++7
line.long  0x0 "PB_BAR1_LUT_ADDR11,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR11_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x860)++7
line.long  0x0 "PB_BAR1_LUT_ADDR12,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR12_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x868)++7
line.long  0x0 "PB_BAR1_LUT_ADDR13,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR13_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x870)++7
line.long  0x0 "PB_BAR1_LUT_ADDR14,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR14_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x878)++7
line.long  0x0 "PB_BAR1_LUT_ADDR15,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR15_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x880)++7
line.long  0x0 "PB_BAR1_LUT_ADDR16,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR16_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x888)++7
line.long  0x0 "PB_BAR1_LUT_ADDR17,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR17_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x890)++7
line.long  0x0 "PB_BAR1_LUT_ADDR18,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR18_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x898)++7
line.long  0x0 "PB_BAR1_LUT_ADDR19,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR19_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8a0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR20,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR20_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8a8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR21,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR21_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8b0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR22,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR22_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8b8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR23,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR23_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8c0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR24,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR24_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8c8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR25,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR25_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8d0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR26,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR26_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8d8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR27,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR27_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8e0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR28,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR28_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8e8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR29,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR29_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8f0)++7
line.long  0x0 "PB_BAR1_LUT_ADDR30,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR30_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x8f8)++7
line.long  0x0 "PB_BAR1_LUT_ADDR31,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR1_LUT_ADDR31_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
tree.end
tree "Fabric BAR 2 Lookup Table Registers"
config 16. 8.
width 24.
group (0x900)++7
line.long  0x0 "PB_BAR2_LUT_ADDR00,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR00_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x908)++7
line.long  0x0 "PB_BAR2_LUT_ADDR01,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR01_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x910)++7
line.long  0x0 "PB_BAR2_LUT_ADDR02,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR02_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x918)++7
line.long  0x0 "PB_BAR2_LUT_ADDR03,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR03_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x920)++7
line.long  0x0 "PB_BAR2_LUT_ADDR04,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR04_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x928)++7
line.long  0x0 "PB_BAR2_LUT_ADDR05,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR05_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x930)++7
line.long  0x0 "PB_BAR2_LUT_ADDR06,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR06_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x938)++7
line.long  0x0 "PB_BAR2_LUT_ADDR07,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR07_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x940)++7
line.long  0x0 "PB_BAR2_LUT_ADDR08,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR08_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x948)++7
line.long  0x0 "PB_BAR2_LUT_ADDR09,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR09_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x950)++7
line.long  0x0 "PB_BAR2_LUT_ADDR10,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR10_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x958)++7
line.long  0x0 "PB_BAR2_LUT_ADDR11,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR11_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x960)++7
line.long  0x0 "PB_BAR2_LUT_ADDR12,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR12_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x968)++7
line.long  0x0 "PB_BAR2_LUT_ADDR13,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR13_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x970)++7
line.long  0x0 "PB_BAR2_LUT_ADDR14,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR14_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x978)++7
line.long  0x0 "PB_BAR2_LUT_ADDR15,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR15_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x980)++7
line.long  0x0 "PB_BAR2_LUT_ADDR16,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR16_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x988)++7
line.long  0x0 "PB_BAR2_LUT_ADDR17,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR17_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x990)++7
line.long  0x0 "PB_BAR2_LUT_ADDR18,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR18_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x998)++7
line.long  0x0 "PB_BAR2_LUT_ADDR19,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR19_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9a0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR20,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR20_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9a8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR21,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR21_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9b0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR22,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR22_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9b8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR23,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR23_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9c0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR24,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR24_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9c8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR25,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR25_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9d0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR26,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR26_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9d8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR27,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR27_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9e0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR28,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR28_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9e8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR29,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR29_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9f0)++7
line.long  0x0 "PB_BAR2_LUT_ADDR30,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR30_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
config 16. 8.
width 24.
group (0x9f8)++7
line.long  0x0 "PB_BAR2_LUT_ADDR31,PB Switch Fabric BAR Lower Lookup Table Address Register"
line.long  0x4 "PB_BAR2_LUT_ADDR31_U,PB Switch Fabric BAR Lower Lookup Table Upper Address Register"
tree.end

tree.end
tree "Memory Controller"
config 16. 8.
width 24.
group (0x4000)++3
line.long  0x0 "SD_CTRL,SDRAM Control Register"
group (0x4000+0x04)++3
line.long  0x0 "SD_STATUS,SDRAM Status Register"
group (0x4000+0x8)++3
line.long  0x0 "SD_TIMING,SDRAM Memory Timing Control Register"
group (0x4000+0xc)++3
line.long  0x0 "SD_REFRESH,SDRAM Refresh Interval Register"
group (0x4000+0x10)++3
line.long  0x0 "SD_INT_STATUS,SDRAM Interrupt Status Register"
group (0x4000+0x14)++3
line.long  0x0 "SD_INT_ENABLE,SDRAM Interrupt Enable Register"
group (0x4000+0x18)++3
line.long  0x0 "SD_INT_SET,SDRAM Interrupt Set Register"
group (0x4000+0x20)++3
line.long  0x0 "SD_D0_CTRL,SDRAM DIMM Control Register"
group (0x4000+0x24)++3
line.long  0x0 "SD_D1_CTRL,SDRAM DIMM Control Register"
group (0x4000+0x28)++3
line.long  0x0 "SD_D0_BAR,SDRAM Memory DIMM Base Address Register"
group (0x4000+0x2c)++3
line.long  0x0 "SD_D1_BAR,SDRAM Memory DIMM Base Address Register"
group (0x4000+0x40)++3
line.long  0x0 "SD_ECC_CTRL,SDRAM ECC Control Register"
group (0x4000+0x44)++3
line.long  0x0 "SD_ECC_STATUS,SDRAM ECC Status Register"
group (0x4000+0x48)++3
line.long  0x0 "SD_ECC_ADDR_LO,SDRAM ECC Address of Error Low Register"
group (0x4000+0x4C)++3
line.long  0x0 "SD_ECC_ADDR_HI,SDRAM ECC Address of Error High Register"
group (0x4000+0x50)++3
line.long  0x0 "SD_PB_ADDR_ERR_LO,SDRAM Address Error Low, Processor Bus Register"
group (0x4000+0x54)++3
line.long  0x0 "SD_PB_ADDR_ERR_HI,SDRAM Address Error High, Processor Bus Register"
group (0x4000+0x58)++3
line.long  0x0 "SD_OCN_ADDR_ERR_LO,SDRAM ECC Address of Error Low Register"
group (0x4000+0x5C)++3
line.long  0x0 "SD_OCN_ADDR_ERR_HI,SDRAM Address Error High, Switch Fabric Register"
TEXTLINE ""
group (0x4000+0x80)++3
line.long  0x0 "SD_ODT_CFG,SDRAM ODT Configuration Register"
group (0x4000+0x90)++3
line.long  0x0 "SD_ODT_WRITE_PATTERN,SDRAM ODT Write Pattern Register"
group (0x4000+0x98)++3
line.long  0x0 "SD_ODT_READ_PATTERN,SDRAM ODT Read Pattern Register"
group (0x4000+0xA0)++3
line.long  0x0 "SD_ODC_IA_CTRL,SDRAM OCD Impedance Adjust Control Register"
group (0x4000+0xA4)++3
line.long  0x0 "SD_ODC_IA_STATUS,SDRAM OCD Impedance Adjust Status Register"
group (0x4000+0x10c)++3
line.long  0x0 "SD_SINT_STATUS,SDRAM Shadow Interrupt Status Register"
group (0x4000+0x144)++3
line.long  0x0 "SD_SECC_STATUS,SDRAM Shadow ECC Status Register"
group (0x4000+0x148)++3
line.long  0x0 "SD_SECC_ADDR_LO,SDRAM Shadow ECC Address of Error Low Register"
group (0x4000+0x14C)++3
line.long  0x0 "SD_SECC_ADDR_HI,SDRAM Shadow ECC Address of Error High Register"
group (0x4000+0x248)++3
line.long  0x0 "SD_FB_DELAY,SDRAM Feedback Strobe Delay Register"
group (0x4000+0x24c)++3
line.long  0x0 "SD_ADV_CLK_DELAY,SDRAM Advanced Clock Delay Register"
group (0x4000+0x250)++3
line.long  0x0 "SD_DLL_STATUS,SDRAM DLL Status Register"
tree "DQS delay registers"
config 16. 8.
width 24.
group (0x200)++0x03
line.long  0x0 "SD_DQS00_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x204)++0x03
line.long  0x0 "SD_DQS01_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x208)++0x03
line.long  0x0 "SD_DQS02_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x20C)++0x03
line.long  0x0 "SD_DQS03_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x210)++0x03
line.long  0x0 "SD_DQS04_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x214)++0x03
line.long  0x0 "SD_DQS05_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x218)++0x03
line.long  0x0 "SD_DQS06_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x21C)++0x03
line.long  0x0 "SD_DQS07_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x220)++0x03
line.long  0x0 "SD_DQS08_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x224)++0x03
line.long  0x0 "SD_DQS09_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x228)++0x03
line.long  0x0 "SD_DQS10_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x22C)++0x03
line.long  0x0 "SD_DQS11_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x230)++0x03
line.long  0x0 "SD_DQS12_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x234)++0x03
line.long  0x0 "SD_DQS13_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x238)++0x03
line.long  0x0 "SD_DQS14_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x23C)++0x03
line.long  0x0 "SD_DQS15_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x240)++0x03
line.long  0x0 "SD_DQS16_DELAY,SDRAM DQS Delay Register"
config 16. 8.
width 24.
group (0x244)++0x03
line.long  0x0 "SD_DQS17_DELAY,SDRAM DQS Delay Register"
tree.end

tree.end
tree "DMA Controller"
config 16. 8.
width 16.
tree "Channel 0"
group (0x5000)++3
line.long  0x0 "SRC_ADDR_M,Channel Source Address Register (Most significant)"
group (0x5000+0x04)++3
line.long  0x0 "SRC_ADDR_L,Channel Source Address Register (Least significant)"
group (0x5000+0x8)++3
line.long  0x0 "DST_ADDR_M,Channel Destination Address Register (Most significant)"
group (0x5000+0xc)++3
line.long  0x0 "DST_ADDR_L,Channel Destination Address Register (Least significant)"
group (0x5000+0x10)++3
line.long  0x0 "TCR1,Channel Transfer Control Register 1"
group (0x5000+0x14)++3
line.long  0x0 "TCR2,Channel Transfer Control Register 2"
group (0x5000+0x18)++3
line.long  0x0 "ND_ADDR_M,Channel Next Descriptor Address Register (Most significant)"
group (0x5000+0x1c)++3
line.long  0x0 "ND_ADDR_L,Channel Next Descriptor Address Register (Least significant)"
group (0x5000+0x20)++3
line.long  0x0 "ND_TCR,Channel Next Descriptor Control Register"
group (0x5000+0x24)++3
line.long  0x0 "GCSR,Channel General Control and Status Register"
group (0x5000+0x28)++3
line.long  0x0 "CRC_ADDR_M,Channel CRC Address Register (Most significant)"
group (0x5000+0x2c)++3
line.long  0x0 "CRC_ADDR_L,Channel CRC Address Register (Least significant)"
group (0x5000+0x30)++3
line.long  0x0 "CRC,Channel CRC Value Register"
tree "Source address registers"
group (0x5000+0x040)++0x0F
line.long  0x0 "SRC01_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC01_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x048)++0x0F
line.long  0x0 "SRC02_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC02_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x050)++0x0F
line.long  0x0 "SRC03_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC03_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x058)++0x0F
line.long  0x0 "SRC04_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC04_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x060)++0x0F
line.long  0x0 "SRC05_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC05_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x068)++0x0F
line.long  0x0 "SRC06_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC06_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x070)++0x0F
line.long  0x0 "SRC07_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC07_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x078)++0x0F
line.long  0x0 "SRC08_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC08_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x080)++0x0F
line.long  0x0 "SRC09_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC09_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x088)++0x0F
line.long  0x0 "SRC10_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC10_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x090)++0x0F
line.long  0x0 "SRC11_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC11_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x098)++0x0F
line.long  0x0 "SRC12_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC12_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x0a0)++0x0F
line.long  0x0 "SRC13_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC13_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x0a8)++0x0F
line.long  0x0 "SRC14_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC14_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5000+0x0b0)++0x0F
line.long  0x0 "SRC15_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC15_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
tree.end
tree.end
config 16. 8.
width 16.
tree "Channel 1"
group (0x5100)++3
line.long  0x0 "SRC_ADDR_M,Channel Source Address Register (Most significant)"
group (0x5100+0x04)++3
line.long  0x0 "SRC_ADDR_L,Channel Source Address Register (Least significant)"
group (0x5100+0x8)++3
line.long  0x0 "DST_ADDR_M,Channel Destination Address Register (Most significant)"
group (0x5100+0xc)++3
line.long  0x0 "DST_ADDR_L,Channel Destination Address Register (Least significant)"
group (0x5100+0x10)++3
line.long  0x0 "TCR1,Channel Transfer Control Register 1"
group (0x5100+0x14)++3
line.long  0x0 "TCR2,Channel Transfer Control Register 2"
group (0x5100+0x18)++3
line.long  0x0 "ND_ADDR_M,Channel Next Descriptor Address Register (Most significant)"
group (0x5100+0x1c)++3
line.long  0x0 "ND_ADDR_L,Channel Next Descriptor Address Register (Least significant)"
group (0x5100+0x20)++3
line.long  0x0 "ND_TCR,Channel Next Descriptor Control Register"
group (0x5100+0x24)++3
line.long  0x0 "GCSR,Channel General Control and Status Register"
group (0x5100+0x28)++3
line.long  0x0 "CRC_ADDR_M,Channel CRC Address Register (Most significant)"
group (0x5100+0x2c)++3
line.long  0x0 "CRC_ADDR_L,Channel CRC Address Register (Least significant)"
group (0x5100+0x30)++3
line.long  0x0 "CRC,Channel CRC Value Register"
tree "Source address registers"
group (0x5100+0x040)++0x0F
line.long  0x0 "SRC01_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC01_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x048)++0x0F
line.long  0x0 "SRC02_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC02_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x050)++0x0F
line.long  0x0 "SRC03_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC03_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x058)++0x0F
line.long  0x0 "SRC04_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC04_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x060)++0x0F
line.long  0x0 "SRC05_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC05_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x068)++0x0F
line.long  0x0 "SRC06_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC06_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x070)++0x0F
line.long  0x0 "SRC07_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC07_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x078)++0x0F
line.long  0x0 "SRC08_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC08_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x080)++0x0F
line.long  0x0 "SRC09_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC09_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x088)++0x0F
line.long  0x0 "SRC10_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC10_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x090)++0x0F
line.long  0x0 "SRC11_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC11_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x098)++0x0F
line.long  0x0 "SRC12_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC12_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x0a0)++0x0F
line.long  0x0 "SRC13_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC13_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x0a8)++0x0F
line.long  0x0 "SRC14_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC14_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5100+0x0b0)++0x0F
line.long  0x0 "SRC15_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC15_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
tree.end
tree.end
config 16. 8.
width 16.
tree "Channel 2"
group (0x5200)++3
line.long  0x0 "SRC_ADDR_M,Channel Source Address Register (Most significant)"
group (0x5200+0x04)++3
line.long  0x0 "SRC_ADDR_L,Channel Source Address Register (Least significant)"
group (0x5200+0x8)++3
line.long  0x0 "DST_ADDR_M,Channel Destination Address Register (Most significant)"
group (0x5200+0xc)++3
line.long  0x0 "DST_ADDR_L,Channel Destination Address Register (Least significant)"
group (0x5200+0x10)++3
line.long  0x0 "TCR1,Channel Transfer Control Register 1"
group (0x5200+0x14)++3
line.long  0x0 "TCR2,Channel Transfer Control Register 2"
group (0x5200+0x18)++3
line.long  0x0 "ND_ADDR_M,Channel Next Descriptor Address Register (Most significant)"
group (0x5200+0x1c)++3
line.long  0x0 "ND_ADDR_L,Channel Next Descriptor Address Register (Least significant)"
group (0x5200+0x20)++3
line.long  0x0 "ND_TCR,Channel Next Descriptor Control Register"
group (0x5200+0x24)++3
line.long  0x0 "GCSR,Channel General Control and Status Register"
group (0x5200+0x28)++3
line.long  0x0 "CRC_ADDR_M,Channel CRC Address Register (Most significant)"
group (0x5200+0x2c)++3
line.long  0x0 "CRC_ADDR_L,Channel CRC Address Register (Least significant)"
group (0x5200+0x30)++3
line.long  0x0 "CRC,Channel CRC Value Register"
tree "Source address registers"
group (0x5200+0x040)++0x0F
line.long  0x0 "SRC01_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC01_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x048)++0x0F
line.long  0x0 "SRC02_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC02_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x050)++0x0F
line.long  0x0 "SRC03_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC03_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x058)++0x0F
line.long  0x0 "SRC04_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC04_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x060)++0x0F
line.long  0x0 "SRC05_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC05_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x068)++0x0F
line.long  0x0 "SRC06_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC06_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x070)++0x0F
line.long  0x0 "SRC07_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC07_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x078)++0x0F
line.long  0x0 "SRC08_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC08_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x080)++0x0F
line.long  0x0 "SRC09_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC09_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x088)++0x0F
line.long  0x0 "SRC10_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC10_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x090)++0x0F
line.long  0x0 "SRC11_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC11_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x098)++0x0F
line.long  0x0 "SRC12_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC12_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x0a0)++0x0F
line.long  0x0 "SRC13_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC13_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x0a8)++0x0F
line.long  0x0 "SRC14_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC14_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5200+0x0b0)++0x0F
line.long  0x0 "SRC15_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC15_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
tree.end
tree.end
config 16. 8.
width 16.
tree "Channel 3"
group (0x5300)++3
line.long  0x0 "SRC_ADDR_M,Channel Source Address Register (Most significant)"
group (0x5300+0x04)++3
line.long  0x0 "SRC_ADDR_L,Channel Source Address Register (Least significant)"
group (0x5300+0x8)++3
line.long  0x0 "DST_ADDR_M,Channel Destination Address Register (Most significant)"
group (0x5300+0xc)++3
line.long  0x0 "DST_ADDR_L,Channel Destination Address Register (Least significant)"
group (0x5300+0x10)++3
line.long  0x0 "TCR1,Channel Transfer Control Register 1"
group (0x5300+0x14)++3
line.long  0x0 "TCR2,Channel Transfer Control Register 2"
group (0x5300+0x18)++3
line.long  0x0 "ND_ADDR_M,Channel Next Descriptor Address Register (Most significant)"
group (0x5300+0x1c)++3
line.long  0x0 "ND_ADDR_L,Channel Next Descriptor Address Register (Least significant)"
group (0x5300+0x20)++3
line.long  0x0 "ND_TCR,Channel Next Descriptor Control Register"
group (0x5300+0x24)++3
line.long  0x0 "GCSR,Channel General Control and Status Register"
group (0x5300+0x28)++3
line.long  0x0 "CRC_ADDR_M,Channel CRC Address Register (Most significant)"
group (0x5300+0x2c)++3
line.long  0x0 "CRC_ADDR_L,Channel CRC Address Register (Least significant)"
group (0x5300+0x30)++3
line.long  0x0 "CRC,Channel CRC Value Register"
tree "Source address registers"
group (0x5300+0x040)++0x0F
line.long  0x0 "SRC01_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC01_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x048)++0x0F
line.long  0x0 "SRC02_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC02_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x050)++0x0F
line.long  0x0 "SRC03_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC03_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x058)++0x0F
line.long  0x0 "SRC04_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC04_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x060)++0x0F
line.long  0x0 "SRC05_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC05_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x068)++0x0F
line.long  0x0 "SRC06_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC06_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x070)++0x0F
line.long  0x0 "SRC07_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC07_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x078)++0x0F
line.long  0x0 "SRC08_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC08_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x080)++0x0F
line.long  0x0 "SRC09_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC09_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x088)++0x0F
line.long  0x0 "SRC10_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC10_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x090)++0x0F
line.long  0x0 "SRC11_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC11_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x098)++0x0F
line.long  0x0 "SRC12_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC12_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x0a0)++0x0F
line.long  0x0 "SRC13_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC13_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x0a8)++0x0F
line.long  0x0 "SRC14_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC14_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
group (0x5300+0x0b0)++0x0F
line.long  0x0 "SRC15_ADDR_M,Source Address Register (Most significant)"
line.long  0x4 "SRC15_ADDR_L,Source Address Register (Least significant)"
TEXTLINE ""
tree.end
tree.end
tree.end
tree "Ethernet Controllers"
config 16. 8.
width 16.
tree "Ethernet Port 0"
tree "Port 0 MAC Registers"
group (0x6000+0x000)++3
line.long  0x0 "MAC_CONF1,MAC CONFIGURATION2"
group (0x6000+0x004)++3
line.long  0x0 "MAC_CONF2,MAC CONFIGURATION2"
group (0x6000+0x008)++3
line.long  0x0 "IPG_IFG,IPG_IFG"
group (0x6000+0x00C)++3
line.long  0x0 "H_DPLX,HALF_DUPLEX"
group (0x6000+0x010)++3
line.long  0x0 "MAXFRLEN,MAXIMUM FRAME LENGTH"
group (0x6000+0x01c)++3
line.long  0x0 "TEST,TEST_REGISTER"
TEXTLINE ""
group (0x6000+0x020)++3
line.long  0x0 "MII_MGMTCNF,MII MGMT CONFIGURATION"
group (0x6000+0x024)++3
line.long  0x0 "MII_MGMTCMD,MII MGMT COMMAND"
group (0x6000+0x028)++3
line.long  0x0 "MII_MGMTADR,MII MGMT ADDRESS"
group (0x6000+0x02c)++3
line.long  0x0 "MII_MGMTCTL,MII MGMT CONTROL"
group (0x6000+0x030)++3
line.long  0x0 "MII_MGMTSTAT,MII MGMT STATUS"
group (0x6000+0x034)++3
line.long  0x0 "MII_MGMTIND,MII MGMT INDICATORS"
TEXTLINE ""
group (0x6000+0x03c)++3
line.long  0x0 "I_STAT,INTERFACE_STATUS"
group (0x6000+0x040)++3
line.long  0x0 "ST_ADR1,STATION_ADDRESS1"
group (0x6000+0x044)++3
line.long  0x0 "ST_ADR2,STATION_ADDRESS2"
tree.end
tree "Port 0 STAT Registers"
group (0x6000+0x050)++3
line.long  0x0 "TR64,Transmit and Receive 64-Byte Frame Counter Register"
group (0x6000+0x054)++3
line.long  0x0 "TR127,Transmit and Receive 65-to-127 Byte Frame Counter Register"
group (0x6000+0x058)++3
line.long  0x0 "TR255,Transmit and Receive 128-to-255 Byte Frame Counter Register"
group (0x6000+0x05c)++3
line.long  0x0 "TR511,Transmit and Receive 256-to-511 Byte Frame Counter Register"
group (0x6000+0x060)++3
line.long  0x0 "TR1K,Transmit and Receive 512-to-1023 Byte Frame Counter Register"
group (0x6000+0x064)++3
line.long  0x0 "TRMAX,Transmit and Receive 1024-to-1518 Byte Frame Counter Register"
group (0x6000+0x068)++3
line.long  0x0 "TRMGV,Transmit and Receive 1519-to-1522 Byte VLAN Frame Counter"
TEXTLINE ""
group (0x6000+0x06c)++3
line.long  0x0 "RBYT,Receive Byte Counter Register"
group (0x6000+0x070)++3
line.long  0x0 "RPKT,Receive Packet Counter Register"
group (0x6000+0x074)++3
line.long  0x0 "RFCS,Receive FCS Error Counter Register"
group (0x6000+0x078)++3
line.long  0x0 "RMCA,Receive Multicast Packet Counter Register"
group (0x6000+0x07c)++3
line.long  0x0 "RBCA,Receive Broadcast Packet Counter Register"
group (0x6000+0x080)++3
line.long  0x0 "RXCF,Receive Control Frame Packet Counter Register"
group (0x6000+0x084)++3
line.long  0x0 "RXPF,Receive PAUSE Frame Packet Counter Register"
group (0x6000+0x088)++3
line.long  0x0 "RXUO,Receive Unknown OPCode Packet Counter Register"
group (0x6000+0x08c)++3
line.long  0x0 "RALN,Receive Alignment Error Counter Register"
group (0x6000+0x090)++3
line.long  0x0 "RFLR,Receive Frame Length Error Counter Register"
group (0x6000+0x094)++3
line.long  0x0 "RCDE,Receive Code Error Counter Register"
group (0x6000+0x098)++3
line.long  0x0 "RCSE,Receive Carrier Sense Error Counter Register"
group (0x6000+0x09c)++3
line.long  0x0 "RUND,Receive Undersize Packet Counter Register"
group (0x6000+0x0a0)++3
line.long  0x0 "ROVR,Receive Oversize Packet Counter Register"
group (0x6000+0x0a4)++3
line.long  0x0 "RFRG,Receive Fragments Counter Register"
group (0x6000+0x0a8)++3
line.long  0x0 "RJBR,Receive Jabber Counter Register"
group (0x6000+0x0ac)++3
line.long  0x0 "RDRP,Receive Dropped Packet Counter Register"
TEXTLINE ""
group (0x6000+0x0b0)++3
line.long  0x0 "TBYT,Transmit Byte Counter Register"
group (0x6000+0x0b4)++3
line.long  0x0 "TPKT,Transmit Packet Counter Register"
group (0x6000+0x0b8)++3
line.long  0x0 "TMCA,Transmit Multicast Packet Counter Register"
group (0x6000+0x0bc)++3
line.long  0x0 "TBCA,Transmit Broadcast Packet Counter Register"
group (0x6000+0x0c0)++3
line.long  0x0 "TXPF,Transmit PAUSE Control Frame Counter Register"
group (0x6000+0x0c4)++3
line.long  0x0 "TDFR,Transmit Deferral Packet Counter Register"
group (0x6000+0x0c8)++3
line.long  0x0 "TEDF,Transmit Excessive Deferral Packet Counter Control Register"
group (0x6000+0x0cc)++3
line.long  0x0 "TSCL,Transmit Single Collision Packet Counter Register"
group (0x6000+0x0d0)++3
line.long  0x0 "TMCL,Transmit Multiple Collision Packet Counter Register"
group (0x6000+0x0d4)++3
line.long  0x0 "TLCL,Transmit Late Collision Packet Counter Register"
group (0x6000+0x0d8)++3
line.long  0x0 "TXCL,Transmit Excessive Collision Packet Counter Register"
group (0x6000+0x0dc)++3
line.long  0x0 "TNCL,Transmit Total Collision Counter Register"
group (0x6000+0x0e0)++3
line.long  0x0 "TPFH,Transmit PAUSE Frames Honored Counter Register"
group (0x6000+0x0e4)++3
line.long  0x0 "TDRP,Transmit Drop Frame Counter Register"
group (0x6000+0x0e8)++3
line.long  0x0 "TJBR,Transmit Jabber Frame Counter Register"
group (0x6000+0x0ec)++3
line.long  0x0 "TFCS,Transmit FCS Error Counter Register"
group (0x6000+0x0f0)++3
line.long  0x0 "TXCF,Transmit PAUSE Control Frame Counter Register"
group (0x6000+0x0f4)++3
line.long  0x0 "TOVR,Transmit Oversize Frame Counter Register"
group (0x6000+0x0f8)++3
line.long  0x0 "TUND,Transmit Undersize Frame Counter Register"
group (0x6000+0x0fc)++3
line.long  0x0 "TFRG,Transmit Fragment Counter Register"
TEXTLINE ""  
group (0x6000+0x100)++3
line.long  0x0 "CAR1,Carry Register 1"
group (0x6000+0x104)++3
line.long  0x0 "CAR2,Carry Register 2"
group (0x6000+0x108)++3
line.long  0x0 "CAM1,Carry Mask Register 1"
group (0x6000+0x10c)++3
line.long  0x0 "CAM2,Carry Mask Register 2"
tree.end
tree  "Port 0 Control Registers"
group (0x6000+0x200)++3
line.long  0x0 "PCTRL,Port Control Register"
bitfld.long  0. 31.                  "SRT ,Status Reset" "0,1"
bitfld.long  0. 30.                  "  CLR ,Clear Statistics" "0,1"
bitfld.long  0. 29.                  "  ZOR ,Zero On Read" "0,1"
bitfld.long  0. 28.                  "  STE ,Statistics Enable" "0,1"
bitfld.long  0. 23.                  "  TBI ,Ten Bit interface select" "0,1"
bitfld.long  0. 22.                  "  DIS ,Disable TX Code Group Outputs" "0,1"
bitfld.long  0. 21.                  "  PRB ,PRBS Enable" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RBC ,RBC Mode" "half,full"
bitfld.long  0. 18.                  "  SPD ,Speed" "1000Mbit,10/100 mode"
bitfld.long  0. 16.                  "  BPT ,Back Pressure Type" "Full duplex,Half duplex"
bitfld.long  0. 0.                   "  PRI ,Port Priority" "lowest,highest"
TEXTLINE ""
group (0x6000+0x204)++3
line.long  0x0 "PISTAT,Port Int Status"
bitfld.long  0. 31.                    "INT     ,PORT_INTERRUPT" "0,1"
TEXTLINE "                       "
bitfld.long  0. 30.                  "  OCN_ERR ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 29.                  "  RX_IDLE ,RX Idle interrupt" "0,1"
bitfld.long  0. 28.                  "  RX_ABT  ,RX Abort interrupt" "0,1"
bitfld.long  0. 27.                  "  RX_ERR  ,RX Error interrupt" "0,1"
bitfld.long  0. 26.                  "  RX_OVR  ,RX Overrun interrupt" "0,1"
bitfld.long  0. 25.                  "  RX_THR  ,RX Threshold interrupt" "0,1"
bitfld.long  0. 24.                  "  RX_WAIT ,RX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RX_QUE3 ,RX Queue interrupts," "0,1"
bitfld.long  0. 18.                  "  RX_QUE2 ,RX Queue interrupts," "0,1"
bitfld.long  0. 17.                  "  RX_QUE1 ,RX Queue interrupts," "0,1"
bitfld.long  0. 16.                  "  RX_QUE0 ,RX Queue interrupts," "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                  "  STC     ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 13.                  "  TX_IDLE ,TX Idle interrupt" "0,1"
bitfld.long  0. 12.                  "  TX_ABT  ,TX Abort interrupt" "0,1"
bitfld.long  0. 11.                  "  TX_ERR  ,TX Error interrupt" "0,1"
bitfld.long  0. 10.                  "  TX_UNR  ,TX Underrun interrupt" "0,1"
bitfld.long  0. 09.                  "  TX_THR  ,TX Threshold interrupt" "0,1"
bitfld.long  0. 08.                  "  TX_WAIT ,TX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 03.                  "  TX_QUE3 ,TX Queue interrupts" "0,1"
bitfld.long  0. 02.                  "  TX_QUE2 ,TX Queue interrupts" "0,1"
bitfld.long  0. 01.                  "  TX_QUE1 ,TX Queue interrupts" "0,1"
bitfld.long  0. 00.                  "  TX_QUE0 ,TX Queue interrupts" "0,1"
TEXTLINE ""
group (0x6000+0x208)++3
line.long  0x0 "PIMASK,Port Int Mask"
bitfld.long  0. 30.                    "OCN_ERR ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 29.                  "  RX_IDLE ,RX Idle interrupt" "0,1"
bitfld.long  0. 28.                  "  RX_ABT  ,RX Abort interrupt" "0,1"
bitfld.long  0. 27.                  "  RX_ERR  ,RX Error interrupt" "0,1"
bitfld.long  0. 26.                  "  RX_OVR  ,RX Overrun interrupt" "0,1"
bitfld.long  0. 25.                  "  RX_THR  ,RX Threshold interrupt" "0,1"
bitfld.long  0. 24.                  "  RX_WAIT ,RX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RX_QUE3 ,RX Queue interrupts," "0,1"
bitfld.long  0. 18.                  "  RX_QUE2 ,RX Queue interrupts," "0,1"
bitfld.long  0. 17.                  "  RX_QUE1 ,RX Queue interrupts," "0,1"
bitfld.long  0. 16.                  "  RX_QUE0 ,RX Queue interrupts," "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                  "  STC     ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 13.                  "  TX_IDLE ,TX Idle interrupt" "0,1"
bitfld.long  0. 12.                  "  TX_ABT  ,TX Abort interrupt" "0,1"
bitfld.long  0. 11.                  "  TX_ERR  ,TX Error interrupt" "0,1"
bitfld.long  0. 10.                  "  TX_UNR  ,TX Underrun interrupt" "0,1"
bitfld.long  0. 09.                  "  TX_THR  ,TX Threshold interrupt" "0,1"
bitfld.long  0. 08.                  "  TX_WAIT ,TX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 03.                  "  TX_QUE3 ,TX Queue interrupts" "0,1"
bitfld.long  0. 02.                  "  TX_QUE2 ,TX Queue interrupts" "0,1"
bitfld.long  0. 01.                  "  TX_QUE1 ,TX Queue interrupts" "0,1"
bitfld.long  0. 00.                  "  TX_QUE0 ,TX Queue interrupts" "0,1"
TEXTLINE ""
group (0x6000+0x20c)++3
line.long  0x0 "SFS,Switch Fabric Status"
hexmask.byte 0. 00.--07. 1. 0.    "OCN_ERROR_COUNT ,OCN_ERROR_COUNT"
hexmask.long 0. 00.--23. 1. 0.  "  OCN_RESPONSE_HEADER[87:64] ,OCN_RESPONSE_HEADER[87:64]"
TEXTLINE ""
tree "TX Registers"
group (0x6000+0x220)++3
line.long  0x0 "TXCNF,TX Configuration"
bitfld.long  0. 31.                      "RST ,Reset" "0,1"
bitfld.long  0. 23.                    "  CHP ,Change Priority" "0,1"
bitfld.long  0. 22.                    "  EHP ,Enable Higher Priority" "0,1"
bitfld.long  0. 00.--01.               "  START_Q ,Start Queue Number" "0,1,2,3"
TEXTLINE ""
group (0x6000+0x224)++3
line.long  0x0 "TXCTRL,TX Control"
bitfld.long  0. 31.                      "EII  ,Enable Idle Interrupt" "0,1"
bitfld.long  0. 30.                    "  ABT  ,Abort" "0,1"
bitfld.long  0. 29.                    "  EAI  ,Enable Abort Interrupt" "0,1"
bitfld.long  0. 24.                    "  MP   ,Manual Pause" "0,1"
bitfld.long  0. 15.                    "  GO   ,Set to 1 to enable frame transmissions" "0,1"
bitfld.long  0. 03.                    "  QEN3 ,Queue Enable" "0,1"
bitfld.long  0. 02.                    "  QEN2 ,Queue Enable" "0,1"
bitfld.long  0. 01.                    "  QEN1 ,Queue Enable" "0,1"
bitfld.long  0. 00.                    "  QEN0 ,Queue Enable" "0,1"
TEXTLINE ""
group (0x6000+0x228)++3
line.long  0x0 "TXSTAT,TX Status"
bitfld.long  0. 27.                      "EOQ_PEN3   ,End of Queue Pending" "0,1"
bitfld.long  0. 26.                    "  EOQ_PEN2   ,End of Queue Pending" "0,1"
bitfld.long  0. 25.                    "  EOQ_PEN1   ,End of Queue Pending" "0,1"
bitfld.long  0. 24.                    "  EOQ_PEN0   ,End of Queue Pending" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  Q_IDLE3    ,queue idle" "0,1"
bitfld.long  0. 18.                    "  Q_IDLE2    ,queue idle" "0,1"
bitfld.long  0. 17.                    "  Q_IDLE1    ,queue idle" "0,1"
bitfld.long  0. 16.                    "  Q_IDLE0    ,queue idle" "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                    "  ACT        ,TX is active" "0,1"
bitfld.long  0. 08.--09.               "  CURR_Q     ,Current Queue Number" "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 03.                    "  Q_USABLE3  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 02.                    "  Q_USABLE2  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 01.                    "  Q_USABLE1  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 00.                    "  Q_USABLE0  ,queue is enabled and has a valid descriptor." "0,1"
TEXTLINE ""
group (0x6000+0x22c)++3
line.long  0x0 "TXEXSTAT,TX Extended Status"
bitfld.long  0. 27.                      "ERR_FLG3 ,error flag" "0,1"
bitfld.long  0. 26.                    "  ERR_FLG2 ,error flag" "0,1"
bitfld.long  0. 25.                    "  ERR_FLG1 ,error flag" "0,1"
bitfld.long  0. 24.                    "  ERR_FLG0 ,error flag" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  DSCICND3 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 18.                    "  DSCICND2 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 17.                    "  DSCICND1 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 16.                    "  DSCICND0 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOFRCND3 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOFRCND2 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOFRCND1 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOFRCND0 ,END_OF_FRAME_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOQUCND3 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOQUCND2 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOQUCND1 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1"
TEXTLINE ""
group (0x6000+0x230)++3
line.long  0x0 "TSTHRES,TX Thresholds"
hexmask.byte 1. 00.--07. 1. 0.      "STOP_FILLING_THRESHOLD  ,"
hexmask.byte 3. 00.--07. 1. 0.    "  START_SENDING_THRESHOLD ,"
group (0x6000+0x234)++3
line.long  0x0 "TXPRITH,TX Priority Thresholds"
bitfld.long  0. 24.--31.          "EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1,?..."
TEXTLINE ""
group (0x6000+0x240)++3
line.long  0x0 "TXQPM,TX Queue Priority Map"
bitfld.long  0. 28.--31.             "FRAME_LIMIT_QUEUE_3 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 27.                "  REVERT_AFTER_3      " "0,1"
bitfld.long  0. 24.--25.           "  NEXT_QUEUE_AFTER_3  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 20.--23.           "  FRAME_LIMIT_QUEUE_2 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 19.                "  REVERT_AFTER_2      " "0,1"
bitfld.long  0. 16.--17.           "  NEXT_QUEUE_AFTER_2  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 12.--15.           "  FRAME_LIMIT_QUEUE_1 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 11.                "  REVERT_AFTER_1      " "0,1"
bitfld.long  0. 09.--10.           "  NEXT_QUEUE_AFTER_1  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 04.--07.           "  FRAME_LIMIT_QUEUE_0 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 03.                "  REVERT_AFTER_0      " "0,1"
bitfld.long  0. 00.--01.           "  NEXT_QUEUE_AFTER_0  " "0,1,2,3"
TEXTLINE ""
group (0x6000+0x248)++3
line.long  0x0 "TXPENCOM,TX Pending Completion"
hexmask.byte 0. 24.--29. 1. 0.    "PENDING_QUEUE_3  "
hexmask.byte 0. 16.--21. 1. 0.    "  PENDING_QUEUE_2  "
hexmask.byte 0. 08.--13. 1. 0.    "  PENDING_QUEUE_1  "
hexmask.byte 0. 00.--05. 1. 0.    "  PENDING_QUEUE_0  "
TEXTLINE ""
group (0x6000+0x250)++3
line.long  0x0 "TXPSCNTL,TX Pause Count"
group (0x6000+0x254)++3
line.long  0x0 "TXGVLANT,TX Global VLAN Tag"
group (0x6000+0x278)++3
line.long  0x0 "TXERR,TX Error Status"
bitfld.long  0. 31.                  "DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 30.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 29.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 28.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 24.--27.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 23.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 22.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 21.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 20.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 16.--19.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 15.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 14.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 13.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 12.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 08.--11.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 07.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 06.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 05.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 04.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 00.--03.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
tree "TX Diagnostic Indirect Access Registers"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000000
line.long 0x00 "TXCurDesc0,TX Cur Descriptor 0"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000001
line.long 0x00 "TXCurDesc1,TX Cur Descriptor 1"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000002
line.long 0x00 "TXCurDesc2,TX Cur Descriptor 2"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000003
line.long 0x00 "TXCurDesc3,TX Cur Descriptor 3"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000004
line.long 0x00 "TXCurDesc4,TX Cur Descriptor 4"
group (0x6000+0x274)++3
saveout (0x6000+0x270) %L 0x0x40000005
line.long 0x00 "TXCurDesc5,TX Cur Descriptor 5"
;group (0x6000+0x270)++3
;  line.long  0x0 "TXDIA,TX Diagnostic Indirect Access"
;group (0x6000+0x274)++3
;  line.long  0x0 "TXDID,TX Diagnostic Indirect Data"
;TEXTLINE ""
tree.end
tree "TX Queue Registers"
group (0x280+0x0)++3
line.long  0x0 "TXQ0CONF,TXQ0 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x280+0x4)++3
line.long  0x0 "TXQ0BCNF,TXQ0 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x280+0x8)++3
line.long  0x0 "TXQ0PL,TXQ0 Pointer Low"
group (0x280+0xc)++3
line.long  0x0 "TXQ0PH,TXQ0 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x290+0x0)++3
line.long  0x0 "TXQ1CONF,TXQ1 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x290+0x4)++3
line.long  0x0 "TXQ1BCNF,TXQ1 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x290+0x8)++3
line.long  0x0 "TXQ1PL,TXQ1 Pointer Low"
group (0x290+0xc)++3
line.long  0x0 "TXQ1PH,TXQ1 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x2A0+0x0)++3
line.long  0x0 "TXQ2CONF,TXQ2 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2A0+0x4)++3
line.long  0x0 "TXQ2BCNF,TXQ2 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2A0+0x8)++3
line.long  0x0 "TXQ2PL,TXQ2 Pointer Low"
group (0x2A0+0xc)++3
line.long  0x0 "TXQ2PH,TXQ2 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x2B0+0x0)++3
line.long  0x0 "TXQ3CONF,TXQ3 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2B0+0x4)++3
line.long  0x0 "TXQ3BCNF,TXQ3 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2B0+0x8)++3
line.long  0x0 "TXQ3PL,TXQ3 Pointer Low"
group (0x2B0+0xc)++3
line.long  0x0 "TXQ3PH,TXQ3 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
tree.end
tree.end
tree "RX Registers"
group (0x6000+0x320)++3
line.long  0x0 "RXCONF,RX Configuration"
bitfld.long  0. 31.                      "RST ,Reset" "0,1"
bitfld.long  0. 23.                    "  CHP ,Change Priority" "0,1"
bitfld.long  0. 22.                    "  APE ,Auto Pause Enable" "0,1"
bitfld.long  0. 21.                    "  ABF ,Allow Bad Frames" "0,1"
TEXTLINE "                       "
bitfld.long  0. 13.                    "  SE  ,Station Enable" "0,1"
bitfld.long  0. 12.                    "  UFE ,Unicast Frame Enable" "0,1"
bitfld.long  0. 11.                    "  MFE ,Multicast Frame Enable" "0,1"
bitfld.long  0. 10.                    "  BFE ,Broadcast Frame Enable" "0,1"
bitfld.long  0. 09.                    "  EUF ,Enable Unicast Hash Filter" "0,1"
bitfld.long  0. 08.                    "  EMF ,Enable Multicast Hash Filter" "0,1"
bitfld.long  0. 00.--01.               "  DEF_Q ,Default Queue Number" "0,1,2,3"
TEXTLINE ""
group (0x6000+0x324)++3
line.long  0x0 "RXCTRL,RX Control"
bitfld.long  0. 31.                      "EII  ,Enable Idle Interrupt" "0,1"
bitfld.long  0. 30.                    "  ABT  ,Abort" "0,1"
bitfld.long  0. 29.                    "  EAI  ,Enable Abort Interrupt" "0,1"
bitfld.long  0. 15.                    "  GO   ,Set to 1 to enable frame receptions." "0,1"
bitfld.long  0. 03.                    "  QEN3 ,Queue Enable" "0,1"
bitfld.long  0. 02.                    "  QEN2 ,Queue Enable" "0,1"
bitfld.long  0. 01.                    "  QEN1 ,Queue Enable" "0,1"
bitfld.long  0. 00.                    "  QEN0 ,Queue Enable" "0,1"
TEXTLINE ""
group (0x6000+0x328)++3
line.long  0x0 "RXSTAT,RX Status"
bitfld.long  0. 19.                    "Q_IDLE3    ,queue idle" "0,1"
bitfld.long  0. 18.                    "  Q_IDLE2    ,queue idle" "0,1"
bitfld.long  0. 17.                    "  Q_IDLE1    ,queue idle" "0,1"
bitfld.long  0. 16.                    "  Q_IDLE0    ,queue idle" "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                    "  ACT        ,TX is active" "0,1"
bitfld.long  0. 14.                    "  PRB        ,Pseudo Random Bit Stream" "0,1"
bitfld.long  0. 08.--09.               "  CURR_Q     ,Current Queue Number" "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 03.                    "  Q_USABLE3  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 02.                    "  Q_USABLE2  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 01.                    "  Q_USABLE1  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 00.                    "  Q_USABLE0  ,queue is enabled and has a valid descriptor." "0,1"
TEXTLINE ""
group (0x6000+0x32c)++3
line.long  0x0 "RXEXSTAT,RX Extended Status"
bitfld.long  0. 27.                      "ERR_FLG3 ,error flag" "0,1"
bitfld.long  0. 26.                    "  ERR_FLG2 ,error flag" "0,1"
bitfld.long  0. 25.                    "  ERR_FLG1 ,error flag" "0,1"
bitfld.long  0. 24.                    "  ERR_FLG0 ,error flag" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  DSCICND3 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 18.                    "  DSCICND2 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 17.                    "  DSCICND1 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 16.                    "  DSCICND0 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOFRCND3 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOFRCND2 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOFRCND1 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOFRCND0 ,END_OF_FRAME_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOQUCND3 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOQUCND2 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOQUCND1 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1"
TEXTLINE ""
group (0x6000+0x330)++3
line.long  0x0 "RXPTH,RX Pause Thresholds"
hexmask.word 0. 00.--08. 1. 0.      "PAUSE_THRESHOLD   "
hexmask.word 2. 00.--08. 1. 0.    "  UNPAUSE_THRESHOLD "
group (0x6000+0x334)++3
line.long  0x0 "TXTHRES,RX Thresholds"
hexmask.word 2. 00.--08. 1. 0.    "OVERRUN_WARNING_THRESHOLD "
group (0x6000+0x340)++3
line.long  0x0 "RXVLANT,RX VLAN Tag Map"
bitfld.long  0. 28.--29.          "QFTAG7 ,Queue # for Tag 7" "0,1,2,3"
bitfld.long  0. 24.--25.          "  QFTAG6 ,Queue # for Tag 6" "0,1,2,3"
bitfld.long  0. 20.--21.          "  QFTAG5 ,Queue # for Tag 5" "0,1,2,3"
bitfld.long  0. 16.--17.          "  QFTAG4 ,Queue # for Tag 4" "0,1,2,3"
bitfld.long  0. 12.--13.          "  QFTAG3 ,Queue # for Tag 3" "0,1,2,3"
bitfld.long  0. 08.--09.          "  QFTAG2 ,Queue # for Tag 2" "0,1,2,3"
bitfld.long  0. 04.--05.          "  QFTAG1 ,Queue # for Tag 1" "0,1,2,3"
bitfld.long  0. 00.--01.          "  QFTAG0 ,Queue # for Tag 0" "0,1,2,3"
group (0x6000+0x378)++3
line.long  0x0 "RXERR,RX Error Status"
bitfld.long  0. 31.                  "DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 30.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 29.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 28.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 24.--27.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 23.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 22.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 21.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 20.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 16.--19.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 15.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 14.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 13.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 12.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 08.--11.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 07.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 06.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 05.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 04.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 00.--03.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
tree "RX Hash Table Indirect Access Registers"
tree "Unicast Hash Table"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0
line.long 0x00 "UCHASH00,UCHASH00"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1
line.long 0x00 "UCHASH01,UCHASH01"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|2
line.long 0x00 "UCHASH02,UCHASH02"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|3
line.long 0x00 "UCHASH03,UCHASH03"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|4
line.long 0x00 "UCHASH04,UCHASH04"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|5
line.long 0x00 "UCHASH05,UCHASH05"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|6
line.long 0x00 "UCHASH06,UCHASH06"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|7
line.long 0x00 "UCHASH07,UCHASH07"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|8
line.long 0x00 "UCHASH08,UCHASH08"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|9
line.long 0x00 "UCHASH09,UCHASH09"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0a
line.long 0x00 "UCHASH10,UCHASH10"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0b
line.long 0x00 "UCHASH11,UCHASH11"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0c
line.long 0x00 "UCHASH12,UCHASH12"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0d
line.long 0x00 "UCHASH13,UCHASH13"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0e
line.long 0x00 "UCHASH14,UCHASH14"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|0f
line.long 0x00 "UCHASH15,UCHASH15"
tree.end
tree "Multicast Hash Table"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|10
line.long 0x00 "MCHASH00,MCHASH00"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|11
line.long 0x00 "MCHASH01,MCHASH01"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|12
line.long 0x00 "MCHASH02,MCHASH02"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|13
line.long 0x00 "MCHASH03,MCHASH03"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|14
line.long 0x00 "MCHASH04,MCHASH04"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|15
line.long 0x00 "MCHASH05,MCHASH05"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|16
line.long 0x00 "MCHASH06,MCHASH06"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|17
line.long 0x00 "MCHASH07,MCHASH07"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|18
line.long 0x00 "MCHASH08,MCHASH08"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|19
line.long 0x00 "MCHASH09,MCHASH09"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1a
line.long 0x00 "MCHASH10,MCHASH10"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1b
line.long 0x00 "MCHASH11,MCHASH11"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1c
line.long 0x00 "MCHASH12,MCHASH12"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1d
line.long 0x00 "MCHASH13,MCHASH13"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1e
line.long 0x00 "MCHASH14,MCHASH14"
group (0x6000+0x364)++3
saveout (0x6000+0x360) %L 0x0x40000000|1f
line.long 0x00 "MCHASH15,MCHASH15"
tree.end
;group (0x6000+0x360)++3
;  line.long  0x0 "RXHASHIA,RX Hash Table Indirect Access"
;group (0x6000+0x364)++3
;  line.long  0x0 "RXHASHID,RX Hash Table Indirect Data"
tree.end
tree "RX Diagnostic Indirect Access Registers"
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000000
line.long 0x00 "RXCurDesc0,RX Cur Descriptor 0"
hexmask.long 0. 00.--31. 1. 0.      "BUFFER_START_ADDRESS_LOW  "
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000001
line.long 0x00 "RXCurDesc1,RX Cur Descriptor 1"
hexmask.word 2. 00.--11. 1. 0.      "BUFFER_START_ADDRESS_HIGH "
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000002
line.long 0x00 "RXCurDesc2,RX Cur Descriptor 2"
hexmask.long 0. 00.--31. 1. 0.      "NEXT_DESCRIPTOR_ADDRESS_LOW   "
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000003
line.long 0x00 "RXCurDesc3,RX Cur Descriptor 3"
bitfld.long  0. 31.                  "LAST ,If 1, signals end of the queue - equivalent to a null descriptor" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  NEXT_DESCRIPTOR_ADDRESS_HIGH  "
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000004
line.long 0x00 "RXCurDesc4,RX Cur Descriptor 4"
hexmask.word 0. 00.--15. 1. 0.      "VLAN_TAG ,VLAN tag extracted from received frame if the vtf bit is set in the status"
hexmask.word 2. 00.--15. 1. 0.      "  RECEIVED_BYTE_COUNT ,Number of bytes actually filled in buffer"
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000005
line.long 0x00 "RXCurDesc5,RX Cur Descriptor 5"
hexmask.word 0. 00.--15. 1. 0.      "BUFFER_BYTE_COUNT ,Total buffer size. Number of bytes available in buffer to received data"
TEXTLINE "                       "
bitfld.long  0. 15.                 "  Owner ,0=System 1=User" "SYS,USR"
bitfld.long  0. 13.                 "  DSC_INT ,If set to 1, a descriptor interrupt will be triggered when the processing on this descriptor is finished" "0,1"
bitfld.long  0. 12.                 "  CRC_ERR ,CRC mismatched" "0,1"
bitfld.long  0. 11.                 "  MAX_FRAME_LENGTH ,Frame truncated due to maximum length or frame length check status received from MAC." "0,1"
bitfld.long  0. 09.                 "  OVERRUN ,Overrun on RX FIFO, frame aborted" "0,1"
bitfld.long  0. 08.                 "  BAD_FRAME ,OK status not received, indicating CRC error or coding error, or Overrun condition" "0,1"
TEXTLINE "                       "
bitfld.long  0. 07.                 "  HASH_TABLE_MATCH ,a hash table match was found based on the destination address in the frame." "0,1"
bitfld.long  0. 04.                 "  SHORT_FRAME ,this was a short frame" "0,1"
bitfld.long  0. 03.                 "  FRAME_IS_TYPE ,The Length/Type field in the frame was a type, >=1536 decimal." ">=1536.,<1536"
bitfld.long  0. 02.                 "  VLAN_TAG_IN_FRAME ,the VLAN TAG field existed in the frame and the 16 LSBs have been placed in the VLAN TAG field of this descriptor." "0,1"
bitfld.long  0. 01.                 "  START_OF_FRAME ,this descriptor marks the start of a frame." "0,1"
bitfld.long  0. 00.                 "  END_OF_FRAME ,this descriptor marks the end of a frame" "0,1"
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000008
line.long 0x00 "RXSTF0,RX Start Frame 0"
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x40000009
line.long 0x00 "RXSTF1,RX Start Frame 1"
bitfld.long  0. 31.                  "USR " "0,1"
bitfld.long  0. 29.                  "  INT " "0,1"
bitfld.long  0. 28.                  "  CRC " "0,1"
bitfld.long  0. 27.                  "  MFL " "0,1"
bitfld.long  0. 25.                  "  OR  " "0,1"
bitfld.long  0. 24.                  "  BAD " "0,1"
TEXTLINE "                       "
bitfld.long  0. 23.                  "  HTM " "0,1"
bitfld.long  0. 20.                  "  SF  " "0,1"
bitfld.long  0. 19.                  "  FT  " "0,1"
bitfld.long  0. 18.                  "  VTF " "0,1"
bitfld.long  0. 17.                  "  SOF " "0,1"
bitfld.long  0. 16.                  "  EOF " "0,1"
bitfld.long  0. 15.                  "  LAS " "0,1"
hexmask.word 2. 00.--11. 1. 0.      "  SOF_DESCRIPTOR_ADDRESS_BITS_43_32 "
group (0x6000+0x374)++3
saveout (0x6000+0x370) %L 0x0x4000000A
line.long 0x00 "RXSTF2,RX Start Frame 2"
hexmask.word 0. 00.--15. 1. 0.    "VLAN_TCI "
hexmask.word 2. 00.--15. 1. 0.    "  RECEIVED_BYTE_COUNT_BYTES_IN_THIS_BUFFER "
tree.end
tree "RX Queue Registers"
group (0x380+0x0)++3
line.long  0x0 "RXQ0CONF,RXQ0 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x380+0x4)++3
line.long  0x0 "RXQ0BCNF,RXQ0 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x380+0x8)++3
line.long  0x0 "RXQ0PL,RXQ0 Pointer Low"
group (0x380+0xc)++3
line.long  0x0 "RXQ0PH,RXQ0 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x390+0x0)++3
line.long  0x0 "RXQ1CONF,RXQ1 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x390+0x4)++3
line.long  0x0 "RXQ1BCNF,RXQ1 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x390+0x8)++3
line.long  0x0 "RXQ1PL,RXQ1 Pointer Low"
group (0x390+0xc)++3
line.long  0x0 "RXQ1PH,RXQ1 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x3A0+0x0)++3
line.long  0x0 "RXQ2CONF,RXQ2 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3A0+0x4)++3
line.long  0x0 "RXQ2BCNF,RXQ2 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3A0+0x8)++3
line.long  0x0 "RXQ2PL,RXQ2 Pointer Low"
group (0x3A0+0xc)++3
line.long  0x0 "RXQ2PH,RXQ2 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x3B0+0x0)++3
line.long  0x0 "RXQ3CONF,RXQ3 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3B0+0x4)++3
line.long  0x0 "RXQ3BCNF,RXQ3 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3B0+0x8)++3
line.long  0x0 "RXQ3PL,RXQ3 Pointer Low"
group (0x3B0+0xc)++3
line.long  0x0 "RXQ3PH,RXQ3 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
tree.end
tree.end
tree.end
tree.end
config 16. 8.
width 16.
tree "Ethernet Port 1"
tree "Port 1 MAC Registers"
group (0x6400+0x000)++3
line.long  0x0 "MAC_CONF1,MAC CONFIGURATION2"
group (0x6400+0x004)++3
line.long  0x0 "MAC_CONF2,MAC CONFIGURATION2"
group (0x6400+0x008)++3
line.long  0x0 "IPG_IFG,IPG_IFG"
group (0x6400+0x00C)++3
line.long  0x0 "H_DPLX,HALF_DUPLEX"
group (0x6400+0x010)++3
line.long  0x0 "MAXFRLEN,MAXIMUM FRAME LENGTH"
group (0x6400+0x01c)++3
line.long  0x0 "TEST,TEST_REGISTER"
TEXTLINE ""
group (0x6400+0x020)++3
line.long  0x0 "MII_MGMTCNF,MII MGMT CONFIGURATION"
group (0x6400+0x024)++3
line.long  0x0 "MII_MGMTCMD,MII MGMT COMMAND"
group (0x6400+0x028)++3
line.long  0x0 "MII_MGMTADR,MII MGMT ADDRESS"
group (0x6400+0x02c)++3
line.long  0x0 "MII_MGMTCTL,MII MGMT CONTROL"
group (0x6400+0x030)++3
line.long  0x0 "MII_MGMTSTAT,MII MGMT STATUS"
group (0x6400+0x034)++3
line.long  0x0 "MII_MGMTIND,MII MGMT INDICATORS"
TEXTLINE ""
group (0x6400+0x03c)++3
line.long  0x0 "I_STAT,INTERFACE_STATUS"
group (0x6400+0x040)++3
line.long  0x0 "ST_ADR1,STATION_ADDRESS1"
group (0x6400+0x044)++3
line.long  0x0 "ST_ADR2,STATION_ADDRESS2"
tree.end
tree "Port 1 STAT Registers"
group (0x6400+0x050)++3
line.long  0x0 "TR64,Transmit and Receive 64-Byte Frame Counter Register"
group (0x6400+0x054)++3
line.long  0x0 "TR127,Transmit and Receive 65-to-127 Byte Frame Counter Register"
group (0x6400+0x058)++3
line.long  0x0 "TR255,Transmit and Receive 128-to-255 Byte Frame Counter Register"
group (0x6400+0x05c)++3
line.long  0x0 "TR511,Transmit and Receive 256-to-511 Byte Frame Counter Register"
group (0x6400+0x060)++3
line.long  0x0 "TR1K,Transmit and Receive 512-to-1023 Byte Frame Counter Register"
group (0x6400+0x064)++3
line.long  0x0 "TRMAX,Transmit and Receive 1024-to-1518 Byte Frame Counter Register"
group (0x6400+0x068)++3
line.long  0x0 "TRMGV,Transmit and Receive 1519-to-1522 Byte VLAN Frame Counter"
TEXTLINE ""
group (0x6400+0x06c)++3
line.long  0x0 "RBYT,Receive Byte Counter Register"
group (0x6400+0x070)++3
line.long  0x0 "RPKT,Receive Packet Counter Register"
group (0x6400+0x074)++3
line.long  0x0 "RFCS,Receive FCS Error Counter Register"
group (0x6400+0x078)++3
line.long  0x0 "RMCA,Receive Multicast Packet Counter Register"
group (0x6400+0x07c)++3
line.long  0x0 "RBCA,Receive Broadcast Packet Counter Register"
group (0x6400+0x080)++3
line.long  0x0 "RXCF,Receive Control Frame Packet Counter Register"
group (0x6400+0x084)++3
line.long  0x0 "RXPF,Receive PAUSE Frame Packet Counter Register"
group (0x6400+0x088)++3
line.long  0x0 "RXUO,Receive Unknown OPCode Packet Counter Register"
group (0x6400+0x08c)++3
line.long  0x0 "RALN,Receive Alignment Error Counter Register"
group (0x6400+0x090)++3
line.long  0x0 "RFLR,Receive Frame Length Error Counter Register"
group (0x6400+0x094)++3
line.long  0x0 "RCDE,Receive Code Error Counter Register"
group (0x6400+0x098)++3
line.long  0x0 "RCSE,Receive Carrier Sense Error Counter Register"
group (0x6400+0x09c)++3
line.long  0x0 "RUND,Receive Undersize Packet Counter Register"
group (0x6400+0x0a0)++3
line.long  0x0 "ROVR,Receive Oversize Packet Counter Register"
group (0x6400+0x0a4)++3
line.long  0x0 "RFRG,Receive Fragments Counter Register"
group (0x6400+0x0a8)++3
line.long  0x0 "RJBR,Receive Jabber Counter Register"
group (0x6400+0x0ac)++3
line.long  0x0 "RDRP,Receive Dropped Packet Counter Register"
TEXTLINE ""
group (0x6400+0x0b0)++3
line.long  0x0 "TBYT,Transmit Byte Counter Register"
group (0x6400+0x0b4)++3
line.long  0x0 "TPKT,Transmit Packet Counter Register"
group (0x6400+0x0b8)++3
line.long  0x0 "TMCA,Transmit Multicast Packet Counter Register"
group (0x6400+0x0bc)++3
line.long  0x0 "TBCA,Transmit Broadcast Packet Counter Register"
group (0x6400+0x0c0)++3
line.long  0x0 "TXPF,Transmit PAUSE Control Frame Counter Register"
group (0x6400+0x0c4)++3
line.long  0x0 "TDFR,Transmit Deferral Packet Counter Register"
group (0x6400+0x0c8)++3
line.long  0x0 "TEDF,Transmit Excessive Deferral Packet Counter Control Register"
group (0x6400+0x0cc)++3
line.long  0x0 "TSCL,Transmit Single Collision Packet Counter Register"
group (0x6400+0x0d0)++3
line.long  0x0 "TMCL,Transmit Multiple Collision Packet Counter Register"
group (0x6400+0x0d4)++3
line.long  0x0 "TLCL,Transmit Late Collision Packet Counter Register"
group (0x6400+0x0d8)++3
line.long  0x0 "TXCL,Transmit Excessive Collision Packet Counter Register"
group (0x6400+0x0dc)++3
line.long  0x0 "TNCL,Transmit Total Collision Counter Register"
group (0x6400+0x0e0)++3
line.long  0x0 "TPFH,Transmit PAUSE Frames Honored Counter Register"
group (0x6400+0x0e4)++3
line.long  0x0 "TDRP,Transmit Drop Frame Counter Register"
group (0x6400+0x0e8)++3
line.long  0x0 "TJBR,Transmit Jabber Frame Counter Register"
group (0x6400+0x0ec)++3
line.long  0x0 "TFCS,Transmit FCS Error Counter Register"
group (0x6400+0x0f0)++3
line.long  0x0 "TXCF,Transmit PAUSE Control Frame Counter Register"
group (0x6400+0x0f4)++3
line.long  0x0 "TOVR,Transmit Oversize Frame Counter Register"
group (0x6400+0x0f8)++3
line.long  0x0 "TUND,Transmit Undersize Frame Counter Register"
group (0x6400+0x0fc)++3
line.long  0x0 "TFRG,Transmit Fragment Counter Register"
TEXTLINE ""  
group (0x6400+0x100)++3
line.long  0x0 "CAR1,Carry Register 1"
group (0x6400+0x104)++3
line.long  0x0 "CAR2,Carry Register 2"
group (0x6400+0x108)++3
line.long  0x0 "CAM1,Carry Mask Register 1"
group (0x6400+0x10c)++3
line.long  0x0 "CAM2,Carry Mask Register 2"
tree.end
tree  "Port 1 Control Registers"
group (0x6400+0x200)++3
line.long  0x0 "PCTRL,Port Control Register"
bitfld.long  0. 31.                  "SRT ,Status Reset" "0,1"
bitfld.long  0. 30.                  "  CLR ,Clear Statistics" "0,1"
bitfld.long  0. 29.                  "  ZOR ,Zero On Read" "0,1"
bitfld.long  0. 28.                  "  STE ,Statistics Enable" "0,1"
bitfld.long  0. 23.                  "  TBI ,Ten Bit interface select" "0,1"
bitfld.long  0. 22.                  "  DIS ,Disable TX Code Group Outputs" "0,1"
bitfld.long  0. 21.                  "  PRB ,PRBS Enable" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RBC ,RBC Mode" "half,full"
bitfld.long  0. 18.                  "  SPD ,Speed" "1000Mbit,10/100 mode"
bitfld.long  0. 16.                  "  BPT ,Back Pressure Type" "Full duplex,Half duplex"
bitfld.long  0. 0.                   "  PRI ,Port Priority" "lowest,highest"
TEXTLINE ""
group (0x6400+0x204)++3
line.long  0x0 "PISTAT,Port Int Status"
bitfld.long  0. 31.                    "INT     ,PORT_INTERRUPT" "0,1"
TEXTLINE "                       "
bitfld.long  0. 30.                  "  OCN_ERR ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 29.                  "  RX_IDLE ,RX Idle interrupt" "0,1"
bitfld.long  0. 28.                  "  RX_ABT  ,RX Abort interrupt" "0,1"
bitfld.long  0. 27.                  "  RX_ERR  ,RX Error interrupt" "0,1"
bitfld.long  0. 26.                  "  RX_OVR  ,RX Overrun interrupt" "0,1"
bitfld.long  0. 25.                  "  RX_THR  ,RX Threshold interrupt" "0,1"
bitfld.long  0. 24.                  "  RX_WAIT ,RX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RX_QUE3 ,RX Queue interrupts," "0,1"
bitfld.long  0. 18.                  "  RX_QUE2 ,RX Queue interrupts," "0,1"
bitfld.long  0. 17.                  "  RX_QUE1 ,RX Queue interrupts," "0,1"
bitfld.long  0. 16.                  "  RX_QUE0 ,RX Queue interrupts," "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                  "  STC     ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 13.                  "  TX_IDLE ,TX Idle interrupt" "0,1"
bitfld.long  0. 12.                  "  TX_ABT  ,TX Abort interrupt" "0,1"
bitfld.long  0. 11.                  "  TX_ERR  ,TX Error interrupt" "0,1"
bitfld.long  0. 10.                  "  TX_UNR  ,TX Underrun interrupt" "0,1"
bitfld.long  0. 09.                  "  TX_THR  ,TX Threshold interrupt" "0,1"
bitfld.long  0. 08.                  "  TX_WAIT ,TX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 03.                  "  TX_QUE3 ,TX Queue interrupts" "0,1"
bitfld.long  0. 02.                  "  TX_QUE2 ,TX Queue interrupts" "0,1"
bitfld.long  0. 01.                  "  TX_QUE1 ,TX Queue interrupts" "0,1"
bitfld.long  0. 00.                  "  TX_QUE0 ,TX Queue interrupts" "0,1"
TEXTLINE ""
group (0x6400+0x208)++3
line.long  0x0 "PIMASK,Port Int Mask"
bitfld.long  0. 30.                    "OCN_ERR ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 29.                  "  RX_IDLE ,RX Idle interrupt" "0,1"
bitfld.long  0. 28.                  "  RX_ABT  ,RX Abort interrupt" "0,1"
bitfld.long  0. 27.                  "  RX_ERR  ,RX Error interrupt" "0,1"
bitfld.long  0. 26.                  "  RX_OVR  ,RX Overrun interrupt" "0,1"
bitfld.long  0. 25.                  "  RX_THR  ,RX Threshold interrupt" "0,1"
bitfld.long  0. 24.                  "  RX_WAIT ,RX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                  "  RX_QUE3 ,RX Queue interrupts," "0,1"
bitfld.long  0. 18.                  "  RX_QUE2 ,RX Queue interrupts," "0,1"
bitfld.long  0. 17.                  "  RX_QUE1 ,RX Queue interrupts," "0,1"
bitfld.long  0. 16.                  "  RX_QUE0 ,RX Queue interrupts," "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                  "  STC     ,Switch Fabric Error Interrupt" "0,1"
bitfld.long  0. 13.                  "  TX_IDLE ,TX Idle interrupt" "0,1"
bitfld.long  0. 12.                  "  TX_ABT  ,TX Abort interrupt" "0,1"
bitfld.long  0. 11.                  "  TX_ERR  ,TX Error interrupt" "0,1"
bitfld.long  0. 10.                  "  TX_UNR  ,TX Underrun interrupt" "0,1"
bitfld.long  0. 09.                  "  TX_THR  ,TX Threshold interrupt" "0,1"
bitfld.long  0. 08.                  "  TX_WAIT ,TX Wait interrupt" "0,1"
TEXTLINE "                       "
bitfld.long  0. 03.                  "  TX_QUE3 ,TX Queue interrupts" "0,1"
bitfld.long  0. 02.                  "  TX_QUE2 ,TX Queue interrupts" "0,1"
bitfld.long  0. 01.                  "  TX_QUE1 ,TX Queue interrupts" "0,1"
bitfld.long  0. 00.                  "  TX_QUE0 ,TX Queue interrupts" "0,1"
TEXTLINE ""
group (0x6400+0x20c)++3
line.long  0x0 "SFS,Switch Fabric Status"
hexmask.byte 0. 00.--07. 1. 0.    "OCN_ERROR_COUNT ,OCN_ERROR_COUNT"
hexmask.long 0. 00.--23. 1. 0.  "  OCN_RESPONSE_HEADER[87:64] ,OCN_RESPONSE_HEADER[87:64]"
TEXTLINE ""
tree "TX Registers"
group (0x6400+0x220)++3
line.long  0x0 "TXCNF,TX Configuration"
bitfld.long  0. 31.                      "RST ,Reset" "0,1"
bitfld.long  0. 23.                    "  CHP ,Change Priority" "0,1"
bitfld.long  0. 22.                    "  EHP ,Enable Higher Priority" "0,1"
bitfld.long  0. 00.--01.               "  START_Q ,Start Queue Number" "0,1,2,3"
TEXTLINE ""
group (0x6400+0x224)++3
line.long  0x0 "TXCTRL,TX Control"
bitfld.long  0. 31.                      "EII  ,Enable Idle Interrupt" "0,1"
bitfld.long  0. 30.                    "  ABT  ,Abort" "0,1"
bitfld.long  0. 29.                    "  EAI  ,Enable Abort Interrupt" "0,1"
bitfld.long  0. 24.                    "  MP   ,Manual Pause" "0,1"
bitfld.long  0. 15.                    "  GO   ,Set to 1 to enable frame transmissions" "0,1"
bitfld.long  0. 03.                    "  QEN3 ,Queue Enable" "0,1"
bitfld.long  0. 02.                    "  QEN2 ,Queue Enable" "0,1"
bitfld.long  0. 01.                    "  QEN1 ,Queue Enable" "0,1"
bitfld.long  0. 00.                    "  QEN0 ,Queue Enable" "0,1"
TEXTLINE ""
group (0x6400+0x228)++3
line.long  0x0 "TXSTAT,TX Status"
bitfld.long  0. 27.                      "EOQ_PEN3   ,End of Queue Pending" "0,1"
bitfld.long  0. 26.                    "  EOQ_PEN2   ,End of Queue Pending" "0,1"
bitfld.long  0. 25.                    "  EOQ_PEN1   ,End of Queue Pending" "0,1"
bitfld.long  0. 24.                    "  EOQ_PEN0   ,End of Queue Pending" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  Q_IDLE3    ,queue idle" "0,1"
bitfld.long  0. 18.                    "  Q_IDLE2    ,queue idle" "0,1"
bitfld.long  0. 17.                    "  Q_IDLE1    ,queue idle" "0,1"
bitfld.long  0. 16.                    "  Q_IDLE0    ,queue idle" "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                    "  ACT        ,TX is active" "0,1"
bitfld.long  0. 08.--09.               "  CURR_Q     ,Current Queue Number" "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 03.                    "  Q_USABLE3  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 02.                    "  Q_USABLE2  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 01.                    "  Q_USABLE1  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 00.                    "  Q_USABLE0  ,queue is enabled and has a valid descriptor." "0,1"
TEXTLINE ""
group (0x6400+0x22c)++3
line.long  0x0 "TXEXSTAT,TX Extended Status"
bitfld.long  0. 27.                      "ERR_FLG3 ,error flag" "0,1"
bitfld.long  0. 26.                    "  ERR_FLG2 ,error flag" "0,1"
bitfld.long  0. 25.                    "  ERR_FLG1 ,error flag" "0,1"
bitfld.long  0. 24.                    "  ERR_FLG0 ,error flag" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  DSCICND3 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 18.                    "  DSCICND2 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 17.                    "  DSCICND1 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 16.                    "  DSCICND0 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOFRCND3 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOFRCND2 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOFRCND1 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOFRCND0 ,END_OF_FRAME_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOQUCND3 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOQUCND2 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOQUCND1 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1"
TEXTLINE ""
group (0x6400+0x230)++3
line.long  0x0 "TSTHRES,TX Thresholds"
hexmask.byte 1. 00.--07. 1. 0.      "STOP_FILLING_THRESHOLD  ,"
hexmask.byte 3. 00.--07. 1. 0.    "  START_SENDING_THRESHOLD ,"
group (0x6400+0x234)++3
line.long  0x0 "TXPRITH,TX Priority Thresholds"
bitfld.long  0. 24.--31.          "EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1,?..."
TEXTLINE ""
group (0x6400+0x240)++3
line.long  0x0 "TXQPM,TX Queue Priority Map"
bitfld.long  0. 28.--31.             "FRAME_LIMIT_QUEUE_3 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 27.                "  REVERT_AFTER_3      " "0,1"
bitfld.long  0. 24.--25.           "  NEXT_QUEUE_AFTER_3  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 20.--23.           "  FRAME_LIMIT_QUEUE_2 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 19.                "  REVERT_AFTER_2      " "0,1"
bitfld.long  0. 16.--17.           "  NEXT_QUEUE_AFTER_2  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 12.--15.           "  FRAME_LIMIT_QUEUE_1 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 11.                "  REVERT_AFTER_1      " "0,1"
bitfld.long  0. 09.--10.           "  NEXT_QUEUE_AFTER_1  " "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 04.--07.           "  FRAME_LIMIT_QUEUE_0 " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long  0. 03.                "  REVERT_AFTER_0      " "0,1"
bitfld.long  0. 00.--01.           "  NEXT_QUEUE_AFTER_0  " "0,1,2,3"
TEXTLINE ""
group (0x6400+0x248)++3
line.long  0x0 "TXPENCOM,TX Pending Completion"
hexmask.byte 0. 24.--29. 1. 0.    "PENDING_QUEUE_3  "
hexmask.byte 0. 16.--21. 1. 0.    "  PENDING_QUEUE_2  "
hexmask.byte 0. 08.--13. 1. 0.    "  PENDING_QUEUE_1  "
hexmask.byte 0. 00.--05. 1. 0.    "  PENDING_QUEUE_0  "
TEXTLINE ""
group (0x6400+0x250)++3
line.long  0x0 "TXPSCNTL,TX Pause Count"
group (0x6400+0x254)++3
line.long  0x0 "TXGVLANT,TX Global VLAN Tag"
group (0x6400+0x278)++3
line.long  0x0 "TXERR,TX Error Status"
bitfld.long  0. 31.                  "DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 30.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 29.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 28.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 24.--27.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 23.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 22.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 21.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 20.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 16.--19.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 15.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 14.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 13.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 12.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 08.--11.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 07.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 06.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 05.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 04.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 00.--03.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
tree "TX Diagnostic Indirect Access Registers"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000000
line.long 0x00 "TXCurDesc0,TX Cur Descriptor 0"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000001
line.long 0x00 "TXCurDesc1,TX Cur Descriptor 1"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000002
line.long 0x00 "TXCurDesc2,TX Cur Descriptor 2"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000003
line.long 0x00 "TXCurDesc3,TX Cur Descriptor 3"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000004
line.long 0x00 "TXCurDesc4,TX Cur Descriptor 4"
group (0x6400+0x274)++3
saveout (0x6400+0x270) %L 0x0x40000005
line.long 0x00 "TXCurDesc5,TX Cur Descriptor 5"
;group (0x6400+0x270)++3
;  line.long  0x0 "TXDIA,TX Diagnostic Indirect Access"
;group (0x6400+0x274)++3
;  line.long  0x0 "TXDID,TX Diagnostic Indirect Data"
;TEXTLINE ""
tree.end
tree "TX Queue Registers"
group (0x280+0x0)++3
line.long  0x0 "TXQ0CONF,TXQ0 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x280+0x4)++3
line.long  0x0 "TXQ0BCNF,TXQ0 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x280+0x8)++3
line.long  0x0 "TXQ0PL,TXQ0 Pointer Low"
group (0x280+0xc)++3
line.long  0x0 "TXQ0PH,TXQ0 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x290+0x0)++3
line.long  0x0 "TXQ1CONF,TXQ1 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x290+0x4)++3
line.long  0x0 "TXQ1BCNF,TXQ1 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x290+0x8)++3
line.long  0x0 "TXQ1PL,TXQ1 Pointer Low"
group (0x290+0xc)++3
line.long  0x0 "TXQ1PH,TXQ1 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x2A0+0x0)++3
line.long  0x0 "TXQ2CONF,TXQ2 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2A0+0x4)++3
line.long  0x0 "TXQ2BCNF,TXQ2 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2A0+0x8)++3
line.long  0x0 "TXQ2PL,TXQ2 Pointer Low"
group (0x2A0+0xc)++3
line.long  0x0 "TXQ2PH,TXQ2 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x2B0+0x0)++3
line.long  0x0 "TXQ3CONF,TXQ3 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2B0+0x4)++3
line.long  0x0 "TXQ3BCNF,TXQ3 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x2B0+0x8)++3
line.long  0x0 "TXQ3PL,TXQ3 Pointer Low"
group (0x2B0+0xc)++3
line.long  0x0 "TXQ3PH,TXQ3 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
tree.end
tree.end
tree "RX Registers"
group (0x6400+0x320)++3
line.long  0x0 "RXCONF,RX Configuration"
bitfld.long  0. 31.                      "RST ,Reset" "0,1"
bitfld.long  0. 23.                    "  CHP ,Change Priority" "0,1"
bitfld.long  0. 22.                    "  APE ,Auto Pause Enable" "0,1"
bitfld.long  0. 21.                    "  ABF ,Allow Bad Frames" "0,1"
TEXTLINE "                       "
bitfld.long  0. 13.                    "  SE  ,Station Enable" "0,1"
bitfld.long  0. 12.                    "  UFE ,Unicast Frame Enable" "0,1"
bitfld.long  0. 11.                    "  MFE ,Multicast Frame Enable" "0,1"
bitfld.long  0. 10.                    "  BFE ,Broadcast Frame Enable" "0,1"
bitfld.long  0. 09.                    "  EUF ,Enable Unicast Hash Filter" "0,1"
bitfld.long  0. 08.                    "  EMF ,Enable Multicast Hash Filter" "0,1"
bitfld.long  0. 00.--01.               "  DEF_Q ,Default Queue Number" "0,1,2,3"
TEXTLINE ""
group (0x6400+0x324)++3
line.long  0x0 "RXCTRL,RX Control"
bitfld.long  0. 31.                      "EII  ,Enable Idle Interrupt" "0,1"
bitfld.long  0. 30.                    "  ABT  ,Abort" "0,1"
bitfld.long  0. 29.                    "  EAI  ,Enable Abort Interrupt" "0,1"
bitfld.long  0. 15.                    "  GO   ,Set to 1 to enable frame receptions." "0,1"
bitfld.long  0. 03.                    "  QEN3 ,Queue Enable" "0,1"
bitfld.long  0. 02.                    "  QEN2 ,Queue Enable" "0,1"
bitfld.long  0. 01.                    "  QEN1 ,Queue Enable" "0,1"
bitfld.long  0. 00.                    "  QEN0 ,Queue Enable" "0,1"
TEXTLINE ""
group (0x6400+0x328)++3
line.long  0x0 "RXSTAT,RX Status"
bitfld.long  0. 19.                    "Q_IDLE3    ,queue idle" "0,1"
bitfld.long  0. 18.                    "  Q_IDLE2    ,queue idle" "0,1"
bitfld.long  0. 17.                    "  Q_IDLE1    ,queue idle" "0,1"
bitfld.long  0. 16.                    "  Q_IDLE0    ,queue idle" "0,1"
TEXTLINE "                       "
bitfld.long  0. 15.                    "  ACT        ,TX is active" "0,1"
bitfld.long  0. 14.                    "  PRB        ,Pseudo Random Bit Stream" "0,1"
bitfld.long  0. 08.--09.               "  CURR_Q     ,Current Queue Number" "0,1,2,3"
TEXTLINE "                       "
bitfld.long  0. 03.                    "  Q_USABLE3  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 02.                    "  Q_USABLE2  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 01.                    "  Q_USABLE1  ,queue is enabled and has a valid descriptor." "0,1"
bitfld.long  0. 00.                    "  Q_USABLE0  ,queue is enabled and has a valid descriptor." "0,1"
TEXTLINE ""
group (0x6400+0x32c)++3
line.long  0x0 "RXEXSTAT,RX Extended Status"
bitfld.long  0. 27.                      "ERR_FLG3 ,error flag" "0,1"
bitfld.long  0. 26.                    "  ERR_FLG2 ,error flag" "0,1"
bitfld.long  0. 25.                    "  ERR_FLG1 ,error flag" "0,1"
bitfld.long  0. 24.                    "  ERR_FLG0 ,error flag" "0,1"
TEXTLINE "                       "
bitfld.long  0. 19.                    "  DSCICND3 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 18.                    "  DSCICND2 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 17.                    "  DSCICND1 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
bitfld.long  0. 16.                    "  DSCICND0 ,DESCRIPTOR_INTERRUPT_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOFRCND3 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOFRCND2 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOFRCND1 ,END_OF_FRAME_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOFRCND0 ,END_OF_FRAME_CONDITION" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                    "  EOQUCND3 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 10.                    "  EOQUCND2 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 09.                    "  EOQUCND1 ,END_OF_QUEUE_CONDITION" "0,1"
bitfld.long  0. 08.                    "  EOQUCND0 ,END_OF_QUEUE_CONDITION" "0,1"
TEXTLINE ""
group (0x6400+0x330)++3
line.long  0x0 "RXPTH,RX Pause Thresholds"
hexmask.word 0. 00.--08. 1. 0.      "PAUSE_THRESHOLD   "
hexmask.word 2. 00.--08. 1. 0.    "  UNPAUSE_THRESHOLD "
group (0x6400+0x334)++3
line.long  0x0 "TXTHRES,RX Thresholds"
hexmask.word 2. 00.--08. 1. 0.    "OVERRUN_WARNING_THRESHOLD "
group (0x6400+0x340)++3
line.long  0x0 "RXVLANT,RX VLAN Tag Map"
bitfld.long  0. 28.--29.          "QFTAG7 ,Queue # for Tag 7" "0,1,2,3"
bitfld.long  0. 24.--25.          "  QFTAG6 ,Queue # for Tag 6" "0,1,2,3"
bitfld.long  0. 20.--21.          "  QFTAG5 ,Queue # for Tag 5" "0,1,2,3"
bitfld.long  0. 16.--17.          "  QFTAG4 ,Queue # for Tag 4" "0,1,2,3"
bitfld.long  0. 12.--13.          "  QFTAG3 ,Queue # for Tag 3" "0,1,2,3"
bitfld.long  0. 08.--09.          "  QFTAG2 ,Queue # for Tag 2" "0,1,2,3"
bitfld.long  0. 04.--05.          "  QFTAG1 ,Queue # for Tag 1" "0,1,2,3"
bitfld.long  0. 00.--01.          "  QFTAG0 ,Queue # for Tag 0" "0,1,2,3"
group (0x6400+0x378)++3
line.long  0x0 "RXERR,RX Error Status"
bitfld.long  0. 31.                  "DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 30.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 29.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 28.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 24.--27.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 23.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 22.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 21.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 20.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 16.--19.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 15.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 14.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 13.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 12.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 08.--11.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
TEXTLINE "                       "
bitfld.long  0. 07.                "  DER_Q3 ,Descriptor Error" "0,1"
bitfld.long  0. 06.                "  TER_Q3 ,Read Timeout" "0,1"
bitfld.long  0. 05.                "  RER_Q3 ,Read Error" "0,1"
bitfld.long  0. 04.                "  TEA_Q3 ,Transaction Error Acknowledge" "0,1"
bitfld.long  0. 00.--03.           "  Q3_ERES ,Target error response" "0,unsupported req,Invalid SYNC packet destination fields,3,Address error,5,6,7,8,9,10,11,12,13,14,15"
tree "RX Hash Table Indirect Access Registers"
tree "Unicast Hash Table"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0
line.long 0x00 "UCHASH00,UCHASH00"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1
line.long 0x00 "UCHASH01,UCHASH01"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|2
line.long 0x00 "UCHASH02,UCHASH02"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|3
line.long 0x00 "UCHASH03,UCHASH03"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|4
line.long 0x00 "UCHASH04,UCHASH04"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|5
line.long 0x00 "UCHASH05,UCHASH05"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|6
line.long 0x00 "UCHASH06,UCHASH06"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|7
line.long 0x00 "UCHASH07,UCHASH07"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|8
line.long 0x00 "UCHASH08,UCHASH08"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|9
line.long 0x00 "UCHASH09,UCHASH09"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0a
line.long 0x00 "UCHASH10,UCHASH10"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0b
line.long 0x00 "UCHASH11,UCHASH11"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0c
line.long 0x00 "UCHASH12,UCHASH12"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0d
line.long 0x00 "UCHASH13,UCHASH13"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0e
line.long 0x00 "UCHASH14,UCHASH14"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|0f
line.long 0x00 "UCHASH15,UCHASH15"
tree.end
tree "Multicast Hash Table"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|10
line.long 0x00 "MCHASH00,MCHASH00"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|11
line.long 0x00 "MCHASH01,MCHASH01"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|12
line.long 0x00 "MCHASH02,MCHASH02"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|13
line.long 0x00 "MCHASH03,MCHASH03"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|14
line.long 0x00 "MCHASH04,MCHASH04"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|15
line.long 0x00 "MCHASH05,MCHASH05"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|16
line.long 0x00 "MCHASH06,MCHASH06"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|17
line.long 0x00 "MCHASH07,MCHASH07"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|18
line.long 0x00 "MCHASH08,MCHASH08"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|19
line.long 0x00 "MCHASH09,MCHASH09"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1a
line.long 0x00 "MCHASH10,MCHASH10"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1b
line.long 0x00 "MCHASH11,MCHASH11"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1c
line.long 0x00 "MCHASH12,MCHASH12"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1d
line.long 0x00 "MCHASH13,MCHASH13"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1e
line.long 0x00 "MCHASH14,MCHASH14"
group (0x6400+0x364)++3
saveout (0x6400+0x360) %L 0x0x40000000|1f
line.long 0x00 "MCHASH15,MCHASH15"
tree.end
;group (0x6400+0x360)++3
;  line.long  0x0 "RXHASHIA,RX Hash Table Indirect Access"
;group (0x6400+0x364)++3
;  line.long  0x0 "RXHASHID,RX Hash Table Indirect Data"
tree.end
tree "RX Diagnostic Indirect Access Registers"
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000000
line.long 0x00 "RXCurDesc0,RX Cur Descriptor 0"
hexmask.long 0. 00.--31. 1. 0.      "BUFFER_START_ADDRESS_LOW  "
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000001
line.long 0x00 "RXCurDesc1,RX Cur Descriptor 1"
hexmask.word 2. 00.--11. 1. 0.      "BUFFER_START_ADDRESS_HIGH "
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000002
line.long 0x00 "RXCurDesc2,RX Cur Descriptor 2"
hexmask.long 0. 00.--31. 1. 0.      "NEXT_DESCRIPTOR_ADDRESS_LOW   "
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000003
line.long 0x00 "RXCurDesc3,RX Cur Descriptor 3"
bitfld.long  0. 31.                  "LAST ,If 1, signals end of the queue - equivalent to a null descriptor" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  NEXT_DESCRIPTOR_ADDRESS_HIGH  "
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000004
line.long 0x00 "RXCurDesc4,RX Cur Descriptor 4"
hexmask.word 0. 00.--15. 1. 0.      "VLAN_TAG ,VLAN tag extracted from received frame if the vtf bit is set in the status"
hexmask.word 2. 00.--15. 1. 0.      "  RECEIVED_BYTE_COUNT ,Number of bytes actually filled in buffer"
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000005
line.long 0x00 "RXCurDesc5,RX Cur Descriptor 5"
hexmask.word 0. 00.--15. 1. 0.      "BUFFER_BYTE_COUNT ,Total buffer size. Number of bytes available in buffer to received data"
TEXTLINE "                       "
bitfld.long  0. 15.                 "  Owner ,0=System 1=User" "SYS,USR"
bitfld.long  0. 13.                 "  DSC_INT ,If set to 1, a descriptor interrupt will be triggered when the processing on this descriptor is finished" "0,1"
bitfld.long  0. 12.                 "  CRC_ERR ,CRC mismatched" "0,1"
bitfld.long  0. 11.                 "  MAX_FRAME_LENGTH ,Frame truncated due to maximum length or frame length check status received from MAC." "0,1"
bitfld.long  0. 09.                 "  OVERRUN ,Overrun on RX FIFO, frame aborted" "0,1"
bitfld.long  0. 08.                 "  BAD_FRAME ,OK status not received, indicating CRC error or coding error, or Overrun condition" "0,1"
TEXTLINE "                       "
bitfld.long  0. 07.                 "  HASH_TABLE_MATCH ,a hash table match was found based on the destination address in the frame." "0,1"
bitfld.long  0. 04.                 "  SHORT_FRAME ,this was a short frame" "0,1"
bitfld.long  0. 03.                 "  FRAME_IS_TYPE ,The Length/Type field in the frame was a type, >=1536 decimal." ">=1536.,<1536"
bitfld.long  0. 02.                 "  VLAN_TAG_IN_FRAME ,the VLAN TAG field existed in the frame and the 16 LSBs have been placed in the VLAN TAG field of this descriptor." "0,1"
bitfld.long  0. 01.                 "  START_OF_FRAME ,this descriptor marks the start of a frame." "0,1"
bitfld.long  0. 00.                 "  END_OF_FRAME ,this descriptor marks the end of a frame" "0,1"
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000008
line.long 0x00 "RXSTF0,RX Start Frame 0"
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x40000009
line.long 0x00 "RXSTF1,RX Start Frame 1"
bitfld.long  0. 31.                  "USR " "0,1"
bitfld.long  0. 29.                  "  INT " "0,1"
bitfld.long  0. 28.                  "  CRC " "0,1"
bitfld.long  0. 27.                  "  MFL " "0,1"
bitfld.long  0. 25.                  "  OR  " "0,1"
bitfld.long  0. 24.                  "  BAD " "0,1"
TEXTLINE "                       "
bitfld.long  0. 23.                  "  HTM " "0,1"
bitfld.long  0. 20.                  "  SF  " "0,1"
bitfld.long  0. 19.                  "  FT  " "0,1"
bitfld.long  0. 18.                  "  VTF " "0,1"
bitfld.long  0. 17.                  "  SOF " "0,1"
bitfld.long  0. 16.                  "  EOF " "0,1"
bitfld.long  0. 15.                  "  LAS " "0,1"
hexmask.word 2. 00.--11. 1. 0.      "  SOF_DESCRIPTOR_ADDRESS_BITS_43_32 "
group (0x6400+0x374)++3
saveout (0x6400+0x370) %L 0x0x4000000A
line.long 0x00 "RXSTF2,RX Start Frame 2"
hexmask.word 0. 00.--15. 1. 0.    "VLAN_TCI "
hexmask.word 2. 00.--15. 1. 0.    "  RECEIVED_BYTE_COUNT_BYTES_IN_THIS_BUFFER "
tree.end
tree "RX Queue Registers"
group (0x380+0x0)++3
line.long  0x0 "RXQ0CONF,RXQ0 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x380+0x4)++3
line.long  0x0 "RXQ0BCNF,RXQ0 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x380+0x8)++3
line.long  0x0 "RXQ0PL,RXQ0 Pointer Low"
group (0x380+0xc)++3
line.long  0x0 "RXQ0PH,RXQ0 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x390+0x0)++3
line.long  0x0 "RXQ1CONF,RXQ1 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x390+0x4)++3
line.long  0x0 "RXQ1BCNF,RXQ1 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x390+0x8)++3
line.long  0x0 "RXQ1PL,RXQ1 Pointer Low"
group (0x390+0xc)++3
line.long  0x0 "RXQ1PH,RXQ1 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x3A0+0x0)++3
line.long  0x0 "RXQ2CONF,RXQ2 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3A0+0x4)++3
line.long  0x0 "RXQ2BCNF,RXQ2 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3A0+0x8)++3
line.long  0x0 "RXQ2PL,RXQ2 Pointer Low"
group (0x3A0+0xc)++3
line.long  0x0 "RXQ2PH,RXQ2 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
group (0x3B0+0x0)++3
line.long  0x0 "RXQ3CONF,RXQ3 Configuration"
bitfld.long  0. 20.                    "EDI  ,Enable Descriptor Interrupt" "0,1"
bitfld.long  0. 19.                  "  ESI  ,Enable EOQ Interrupt on Owner = System" "0,1"
bitfld.long  0. 18.                  "  ENI  ,Enable EOQ Interrupt on Null Pointer" "0,1"
bitfld.long  0. 17.                  "  ELI  ,Enable EOQ Interrupt on Last Bit Set" "0,1"
bitfld.long  0. 16.                  "  EEI  ,Enable Interrupt on EOF" "0,1"
bitfld.long  0. 15.                  "  GVI  ,GLOBAL VLAN Insert" "0,1"
bitfld.long  0. 14.                  "  AM   ,Auto Mode" "0,1"
TEXTLINE "                       "
bitfld.long  0. 11.                  "  WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3B0+0x4)++3
line.long  0x0 "RXQ3BCNF,RXQ3 Buffer Configuration"
bitfld.long  0. 11.                  "WSWP ,Enable Word swapping mode" "0,1"
bitfld.long  0. 10.                  "  BSWP ,Enable Byte swapping mode" "0,1"
bitfld.long  0. 08.--09.             "  BURST ,Burst Size" "8 bytes,32 bytes,128 bytes,256 bytes"
hexmask.byte 3. 00.--05. 1. 0.       "  OCN_PORT  ,Switch Fabric port for descriptors in this queue."
group (0x3B0+0x8)++3
line.long  0x0 "RXQ3PL,RXQ3 Pointer Low"
group (0x3B0+0xc)++3
line.long  0x0 "RXQ3PH,RXQ3 Pointer High"
bitfld.long  0. 31.                    "VALID ,Valid" "0,1"
hexmask.word 2. 00.--11. 1. 0.       "  DESCRIPTOR_ADDRESS  ,Target address of next descriptor in this queue"
TEXTLINE ""
tree.end
tree.end
tree.end
tree.end
tree.end
tree "I2C Interface"
config 16. 8.
width 24.
group (0x7000)++3
line.long  0x0 "I2C_CNTRL1,I2C Control 1 Register"
group (0x7000+0x04)++3
line.long  0x0 "I2C_CNTRL2,I2C Control 2 Register"
group (0x7000+0x08)++3
line.long  0x0 "I2C_RD_DATA,I2C Read Data Register"
group (0x7000+0x0c)++3
line.long  0x0 "I2C_TX_DATA,I2C Transmit Data Register"

tree.end
tree "Interrupt Controller"
config 16. 8.
width 24.
tree "Global registers"
group (0x7400+0x400)++3
line.long  0x0 "INT_FRR,Feature Reporting Register"
group (0x7400+0x404)++3
line.long  0x0 "INT_GCR,Global Configuration Register"
group (0x7400+0x408)++3
line.long  0x0 "INT_ICR,Interrupt Configuration Register"
group (0x7400+0x40c)++3
line.long  0x0 "INT_MVI,Vendor Identification Register"
group (0x7400+0x410)++3
line.long  0x0 "INT_SVR,Spurious Vector Register"
group (0x7400+0x414)++3
line.long  0x0 "INT_TFRR,Timer Frequency Reporting Register"
tree.end
tree "Software registers"
group (0x7400+0x420)++3
line.long  0x0 "INT_SOFT_SET,Interrupt Software Override Set Register"
group (0x7400+0x424)++3
line.long  0x0 "INT_SOFT_ENABLE,Interrupt Software Override Enable Register"
tree.end
tree "Timer registers"
config 16. 8.
width 24.
group (0x430)++0x0f
line.long  0x0 "INT_GTCCR0,Global Timer Current Count Register 0"
line.long  0x4 "INT_GTBCR0,Global Timer Base Count Register 0"
line.long  0x8 "INT_GTVPR0,Global Timer Vector/Priority Register 0"
line.long  0xc "INT_GTDR0,Global Timer Destination Register 0"
TEXTLINE ""
config 16. 8.
width 24.
group (0x440)++0x0f
line.long  0x0 "INT_GTCCR1,Global Timer Current Count Register 1"
line.long  0x4 "INT_GTBCR1,Global Timer Base Count Register 1"
line.long  0x8 "INT_GTVPR1,Global Timer Vector/Priority Register 1"
line.long  0xc "INT_GTDR1,Global Timer Destination Register 1"
TEXTLINE ""
config 16. 8.
width 24.
group (0x450)++0x0f
line.long  0x0 "INT_GTCCR2,Global Timer Current Count Register 2"
line.long  0x4 "INT_GTBCR2,Global Timer Base Count Register 2"
line.long  0x8 "INT_GTVPR2,Global Timer Vector/Priority Register 2"
line.long  0xc "INT_GTDR2,Global Timer Destination Register 2"
TEXTLINE ""
config 16. 8.
width 24.
group (0x460)++0x0f
line.long  0x0 "INT_GTCCR3,Global Timer Current Count Register 3"
line.long  0x4 "INT_GTBCR3,Global Timer Base Count Register 3"
line.long  0x8 "INT_GTVPR3,Global Timer Vector/Priority Register 3"
line.long  0xc "INT_GTDR3,Global Timer Destination Register 3"
TEXTLINE ""
tree.end
tree "Local registers per input pin"
config 16. 8.
width 24.
group (0x500)++0x07
line.long  0x0 "INT_IVPR00,IRQ Vector/Priority Register 00"
line.long  0x4 "INT_IDR00,IRQ Destination Register 00"
config 16. 8.
width 24.
group (0x508)++0x07
line.long  0x0 "INT_IVPR01,IRQ Vector/Priority Register 01"
line.long  0x4 "INT_IDR01,IRQ Destination Register 01"
config 16. 8.
width 24.
group (0x510)++0x07
line.long  0x0 "INT_IVPR02,IRQ Vector/Priority Register 02"
line.long  0x4 "INT_IDR02,IRQ Destination Register 02"
config 16. 8.
width 24.
group (0x518)++0x07
line.long  0x0 "INT_IVPR03,IRQ Vector/Priority Register 03"
line.long  0x4 "INT_IDR03,IRQ Destination Register 03"
TEXTLINE ""
config 16. 8.
width 24.
group (0x520)++0x07
line.long  0x0 "INT_IVPR04,IRQ Vector/Priority Register 04"
line.long  0x4 "INT_IDR04,IRQ Destination Register 04"
config 16. 8.
width 24.
group (0x528)++0x07
line.long  0x0 "INT_IVPR05,IRQ Vector/Priority Register 05"
line.long  0x4 "INT_IDR05,IRQ Destination Register 05"
config 16. 8.
width 24.
group (0x530)++0x07
line.long  0x0 "INT_IVPR06,IRQ Vector/Priority Register 06"
line.long  0x4 "INT_IDR06,IRQ Destination Register 06"
config 16. 8.
width 24.
group (0x538)++0x07
line.long  0x0 "INT_IVPR07,IRQ Vector/Priority Register 07"
line.long  0x4 "INT_IDR07,IRQ Destination Register 07"
TEXTLINE ""
config 16. 8.
width 24.
group (0x540)++0x07
line.long  0x0 "INT_IVPR08,IRQ Vector/Priority Register 08"
line.long  0x4 "INT_IDR08,IRQ Destination Register 08"
config 16. 8.
width 24.
group (0x548)++0x07
line.long  0x0 "INT_IVPR09,IRQ Vector/Priority Register 09"
line.long  0x4 "INT_IDR09,IRQ Destination Register 09"
config 16. 8.
width 24.
group (0x550)++0x07
line.long  0x0 "INT_IVPR10,IRQ Vector/Priority Register 10"
line.long  0x4 "INT_IDR10,IRQ Destination Register 10"
config 16. 8.
width 24.
group (0x558)++0x07
line.long  0x0 "INT_IVPR11,IRQ Vector/Priority Register 11"
line.long  0x4 "INT_IDR11,IRQ Destination Register 11"
TEXTLINE ""
config 16. 8.
width 24.
group (0x560)++0x07
line.long  0x0 "INT_IVPR12,IRQ Vector/Priority Register 12"
line.long  0x4 "INT_IDR12,IRQ Destination Register 12"
config 16. 8.
width 24.
group (0x568)++0x07
line.long  0x0 "INT_IVPR13,IRQ Vector/Priority Register 13"
line.long  0x4 "INT_IDR13,IRQ Destination Register 13"
config 16. 8.
width 24.
group (0x570)++0x07
line.long  0x0 "INT_IVPR14,IRQ Vector/Priority Register 14"
line.long  0x4 "INT_IDR14,IRQ Destination Register 14"
config 16. 8.
width 24.
group (0x578)++0x07
line.long  0x0 "INT_IVPR15,IRQ Vector/Priority Register 15"
line.long  0x4 "INT_IDR15,IRQ Destination Register 15"
TEXTLINE ""
config 16. 8.
width 24.
group (0x580)++0x07
line.long  0x0 "INT_IVPR16,IRQ Vector/Priority Register 16"
line.long  0x4 "INT_IDR16,IRQ Destination Register 16"
config 16. 8.
width 24.
group (0x588)++0x07
line.long  0x0 "INT_IVPR17,IRQ Vector/Priority Register 17"
line.long  0x4 "INT_IDR17,IRQ Destination Register 17"
config 16. 8.
width 24.
group (0x590)++0x07
line.long  0x0 "INT_IVPR18,IRQ Vector/Priority Register 18"
line.long  0x4 "INT_IDR18,IRQ Destination Register 18"
config 16. 8.
width 24.
group (0x598)++0x07
line.long  0x0 "INT_IVPR19,IRQ Vector/Priority Register 19"
line.long  0x4 "INT_IDR19,IRQ Destination Register 19"
TEXTLINE ""
config 16. 8.
width 24.
group (0x5a0)++0x07
line.long  0x0 "INT_IVPR20,IRQ Vector/Priority Register 20"
line.long  0x4 "INT_IDR20,IRQ Destination Register 20"
config 16. 8.
width 24.
group (0x5a8)++0x07
line.long  0x0 "INT_IVPR21,IRQ Vector/Priority Register 21"
line.long  0x4 "INT_IDR21,IRQ Destination Register 21"
config 16. 8.
width 24.
group (0x5b0)++0x07
line.long  0x0 "INT_IVPR22,IRQ Vector/Priority Register 22"
line.long  0x4 "INT_IDR22,IRQ Destination Register 22"
config 16. 8.
width 24.
group (0x5b8)++0x07
line.long  0x0 "INT_IVPR23,IRQ Vector/Priority Register 23"
line.long  0x4 "INT_IDR23,IRQ Destination Register 23"
tree.end
tree "Doorbell registers"
group (0x7400+0x600)++3
line.long  0x0 "INT_DAR,Doorbell Activate Register"
config 16. 8.
width 24.
group (0x604)++0x0b
line.long  0x0 "INT_DVPR0,Doorbell Vector/Priority Register 0"
line.long  0x4 "INT_DDR0,Doorbell Destination Register 0"
line.long  0x8 "INT_DMR0,Doorbell Messaging Register 0"
TEXTLINE ""
config 16. 8.
width 24.
group (0x610)++0x0b
line.long  0x0 "INT_DVPR1,Doorbell Vector/Priority Register 1"
line.long  0x4 "INT_DDR1,Doorbell Destination Register 1"
line.long  0x8 "INT_DMR1,Doorbell Messaging Register 1"
TEXTLINE ""
config 16. 8.
width 24.
group (0x61C)++0x0b
line.long  0x0 "INT_DVPR2,Doorbell Vector/Priority Register 2"
line.long  0x4 "INT_DDR2,Doorbell Destination Register 2"
line.long  0x8 "INT_DMR2,Doorbell Messaging Register 2"
TEXTLINE ""
config 16. 8.
width 24.
group (0x628)++0x0b
line.long  0x0 "INT_DVPR3,Doorbell Vector/Priority Register 3"
line.long  0x4 "INT_DDR3,Doorbell Destination Register 3"
line.long  0x8 "INT_DMR3,Doorbell Messaging Register 3"
TEXTLINE ""
tree.end
tree "Mailbox registers"
config 16. 8.
width 24.
group (0x680)++0x0b
line.long  0x0 "INT_MBR0,Mailbox Register 0"
line.long  0x4 "INT_MBVPR0,Mailbox Vector/Priority Register 0"
line.long  0x8 "INT_MBDR0,Mailbox Destination Register 0"
TEXTLINE ""
config 16. 8.
width 24.
group (0x690)++0x0b
line.long  0x0 "INT_MBR1,Mailbox Register 1"
line.long  0x4 "INT_MBVPR1,Mailbox Vector/Priority Register 1"
line.long  0x8 "INT_MBDR1,Mailbox Destination Register 1"
TEXTLINE ""
config 16. 8.
width 24.
group (0x6a0)++0x0b
line.long  0x0 "INT_MBR2,Mailbox Register 2"
line.long  0x4 "INT_MBVPR2,Mailbox Vector/Priority Register 2"
line.long  0x8 "INT_MBDR2,Mailbox Destination Register 2"
TEXTLINE ""
config 16. 8.
width 24.
group (0x6b0)++0x0b
line.long  0x0 "INT_MBR3,Mailbox Register 3"
line.long  0x4 "INT_MBVPR3,Mailbox Vector/Priority Register 3"
line.long  0x8 "INT_MBDR3,Mailbox Destination Register 3"
TEXTLINE ""
tree.end
tree "Local registers per output pin"
config 16. 8.
width 24.
group (0x700)++0x0F
line.long  0x0 "INT_TASKP0,Processor Current Task Priority Register 0"
line.long  0x4 "INT_VECTOR0,CPU Interrupt Acknowledge Register 0"
line.long  0x8 "INT_EOI0,CPU End of Interrupt 0"
line.long  0xC "INT_CSR0,CPU Sensitivity Register 0"
TEXTLINE ""
config 16. 8.
width 24.
group (0x740)++0x0F
line.long  0x0 "INT_TASKP1,Processor Current Task Priority Register 1"
line.long  0x4 "INT_VECTOR1,CPU Interrupt Acknowledge Register 1"
line.long  0x8 "INT_EOI1,CPU End of Interrupt 1"
line.long  0xC "INT_CSR1,CPU Sensitivity Register 1"
TEXTLINE ""
config 16. 8.
width 24.
group (0x780)++0x0F
line.long  0x0 "INT_TASKP2,Processor Current Task Priority Register 2"
line.long  0x4 "INT_VECTOR2,CPU Interrupt Acknowledge Register 2"
line.long  0x8 "INT_EOI2,CPU End of Interrupt 2"
line.long  0xC "INT_CSR2,CPU Sensitivity Register 2"
TEXTLINE ""
config 16. 8.
width 24.
group (0x7C0)++0x0F
line.long  0x0 "INT_TASKP3,Processor Current Task Priority Register 3"
line.long  0x4 "INT_VECTOR3,CPU Interrupt Acknowledge Register 3"
line.long  0x8 "INT_EOI3,CPU End of Interrupt 3"
line.long  0xC "INT_CSR3,CPU Sensitivity Register 3"
TEXTLINE ""
tree.end
tree.end
tree "UART Interfaces"
config 16. 8.
width 24.
tree "UART 0"
group (0x7800)++3
line.long  0x0 "UART0_LOWER_LE,UART0_LOWER_LE Register"
group (0x7800+0x04)++3
line.long  0x0 "UART0_UPPER_LE,UART0_UPPER_LE Register"
group (0x7800+0x08)++3
line.long  0x0 "UART0_LOWER_BE,UART0_LOWER_BE Register"
group (0x7800+0x0c)++3
line.long  0x0 "UART0_UPPER_BE,UART0_UPPER_BE Register"
tree.end
config 16. 8.
width 24.
tree "UART 1"
group (0x7C00)++3
line.long  0x0 "UART1_LOWER_LE,UART1_LOWER_LE Register"
group (0x7C00+0x04)++3
line.long  0x0 "UART1_UPPER_LE,UART1_UPPER_LE Register"
group (0x7C00+0x08)++3
line.long  0x0 "UART1_LOWER_BE,UART1_LOWER_BE Register"
group (0x7C00+0x0c)++3
line.long  0x0 "UART1_UPPER_BE,UART1_UPPER_BE Register"
tree.end
tree.end
tree "GPIO Interface"
config 16. 8.
width 24.
group (1+0xa0)++3
line.long  0x0 "GPIO_DATA,GPIO Data Register"
group (1+0xa4)++3
line.long  0x0 "GPIO_CNTRL,GPIO Control Register"
group (1+0xa8)++3
line.long  0x0 "GPIO_EDGE_CNTRL,GPIO Edge Control Register"
group (1+0xac)++3
line.long  0x0 "GPIO_INT_STATUS,GPIO Interrupt Status Register"
tree.end