; --------------------------------------------------------------------------------
; @Title: P3xxx On-Chip Peripherals
; @Props: Released
; @Author: STR
; @Changelog: 2014-03-28 STR
; @Manufacturer: NXP
; @Doc: P3041RM_Rev0.pdf
; @Core: PowerPC
; @Chip: P3*
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perp3xxx_rcw.per 7231 2016-09-07 16:44:50Z kjmal $
config 16. 8.
endian.be
width 12.
group.long (edbg:0x01000000+0x00)++0x00 "PLL configuration" 
line.long 0x00 "PLL_1,PLL_1" 
bitfld.long 0x00 30.--31. " SYS_PLL_CFG ,System PLL Configuration Platform frequency/system PLL)" ">= 667 MHz,< 667 MHz,,"
bitfld.long 0x00 25.--29. "  SYS_PLL_RAT ,System PLL multiplier/ratio" ",,,,4:1,5:1,6:1,7:1,8:1,9:1,10:1,11:1,12:1,?..."    
bitfld.long 0x00 22.--23. "        MEM_PLL_CFG ,Memory Controller Complex PLL Configuration" "Lower freq.,Higher freq.,,"
bitfld.long 0x00 17.--21. "  MEM_PLL_RAT ,Memory Controller Complex PLL multiplier/ratio" ",1:1 sync.,,,,5:1 async.,6:1 async.,,8:1 async.,9:1 async.,10:1 async.,,12:1 async.,13:1 async.,,,16:1 async.,,18:1 async.,19:1 async.,20:1 async.,,,,24:1 async.,,,,,,,"    
group.long (edbg:0x01000000+0x02)++0x00 
line.long 0x00 "PLL_2,PLL_2"
bitfld.long 0x00 30.--31. " CC1_PLL_CFG ,Core cluster PLL 1 configuration" ">= 1 GHz,< 1 GHz,,"
bitfld.long 0x00 25.--29. "    CC1_PLL_RAT ,Core cluster PLL 1 multiplier/ratio" ",,,,,,,,8:1 async.,9:1 async.,10:1 async.,11:1 async.,12:1 async.,13:1 async.,14:1 async.,15:1 async.,16:1 async.,,18:1 async.,,20:1 async.,,22:1 async.,,,,,,,,,"    
bitfld.long 0x00 22.--23. " CC2_PLL_CFG ,Core cluster PLL 2 configuration" ">= 1 GHz,< 1 GHz,,"    
bitfld.long 0x00 17.--21. "      CC2_PLL_RAT ,Core cluster PLL 2 multiplier/ratio" ",,,,,,,,8:1 async.,9:1 async.,10:1 async.,11:1 async.,12:1 async.,13:1 async.,14:1 async.,15:1 async.,16:1 async.,,18:1 async.,,20:1 async.,,22:1 async.,,,,,,,,,"
group.long (edbg:0x01000000+0x03)++0x00 
line.long 0x00 "PLL_3,PLL_3" 
bitfld.long 0x00 28.--31. " C0_PLL_SEL  ,Core complex 0 PLL select" "CC1 PLL/1,CC1 PLL/2,CC1 PLL/4,,CC2 PLL/1,CC2 PLL/2,CC2 PLL/4,,,,,,,,,"
bitfld.long 0x00 24.--27. "   C1_PLL_SEL  ,Core complex 1 PLL select" "CC1 PLL/1,CC1 PLL/2,CC1 PLL/4,,CC2 PLL/1,CC2 PLL/2,CC2 PLL/4,,,,,,,,,"
bitfld.long 0x00 20.--23. "   C2_PLL_SEL  ,Core complex 2 PLL select" "CC1 PLL/1,CC1 PLL/2,CC1 PLL/4,,CC2 PLL/1,CC2 PLL/2,CC2 PLL/4,,,,,,,,,"
textline "                     "
group.long (edbg:0x01000000+0x04)++0x00 "SerDes PLL and Protocol Configuration"
line.long 0x00 "SERDES_1,SERDES_1"
bitfld.long 0x00 26.--31. " SRDS_PRTCL    ,SerDes protocol select" ",,2h,,4h,,,,,,,Bh,,,,,10h,11h,,13h,14h,15h,16h,17h,18h,,,1Bh,,1Dh,,,20h,21h,22h,23h,24h,,,,28h,29h,2Ah,2Bh,,,,2Fh,,31h,,33h,34h,35h,36h,37h,,,,,,,,"
bitfld.long 0x00 25. "     SRDS_RIO_SPD    ,SerDes RapidIO speed" "2.5/5 Gbps,3.125 Gbps"
textline "                     "
bitfld.long 0x00 21.--23. " SRDS_RATIO_B1 ,SerDes PLL ratio - bank 1" ",,25:1,40:1,50:1,,,"
bitfld.long 0x00 20. "    SRDS_DIV_B1_A/B ,SerDes PLL dividers - bank 1 Lanes A/B" "/1,/2"
bitfld.long 0x00 19. "    SRDS_DIV_B1_C/D ,SerDes PLL dividers - bank 1 Lanes C/D" "/1,/2"
bitfld.long 0x00 18. "  SRDS_DIV_B1_E/F ,SerDes PLL dividers - bank 1 Lanes E/F" "/1,/2"
bitfld.long 0x00 17. "  SRDS_DIV_B1_G/H ,SerDes PLL dividers - bank 1 Lanes G/H" "/1,/2"
bitfld.long 0x00 16. "  SRDS_DIV_B1_I/J ,SerDes PLL dividers - bank 1 Lanes I/J" "/1,/2"
textline "                     "
bitfld.long 0x00 13.--15. " SRDS_RATIO_B2 ,SerDes PLL ratio - bank 2" ",20:1,25:1,40:1,50:1,24:1,30:1,"
bitfld.long 0x00 12. "    SRDS_DIV_B2     ,SerDes PLL divider - bank 2 Lanes A/D" "/1,/2"
textline "                     "
bitfld.long 0x00 9.--11. " SRDS_RATIO_B3 ,SerDes PLL ratio - bank 3" ",20:1,25:1,40:1,50:1,24:1,30:1,"
textline "                     "
bitfld.long 0x00 8. " SRDS_DIV_B3   ,SerDes PLL divider - bank 3 Lanes A/D" "/1,/2"
textline "                     "
bitfld.long 0x00 7. " SRDS_LPD_B1_A ,SerDes lane power down - bank 1 Lane A" "Not powered down,Powered down"
bitfld.long 0x00 6. "  SRDS_LPD_B1_B ,SerDes lane power down - bank 1 Lane B" "Not powered down,Powered down"
textline "                     "
bitfld.long 0x00 5. " SRDS_LPD_B1_C ,SerDes lane power down - bank 1 Lane C" "Not powered down,Powered down"
bitfld.long 0x00 4. "  SRDS_LPD_B1_D ,SerDes lane power down - bank 1 Lane D" "Not powered down,Powered down"
bitfld.long 0x00 3. "  SRDS_LPD_B1_E ,SerDes lane power down - bank 1 Lane E" "Not powered down,Powered down"
bitfld.long 0x00 2. "  SRDS_LPD_B1_F ,SerDes lane power down - bank 1 Lane F" "Not powered down,Powered down"
textline "                     "
bitfld.long 0x00 1. " SRDS_LPD_B1_G ,SerDes lane power down - bank 1 Lane G" "Not powered down,Powered down"
bitfld.long 0x00 0. "  SRDS_LPD_B1_H ,SerDes lane power down - bank 1 Lane H" "Not powered down,Powered down"
group.long (edbg:0x01000000+0x05)++0x00 
line.byte 0x00 "SERDES_2,SERDES_2"
bitfld.long 0x00 29. "     SRDS_LPD_B1_I ,SerDes lane power down - bank 1 Lane I" "Not powered down,Powered down"
bitfld.long 0x00 28. "  SRDS_LPD_B1_J ,SerDes lane power down - bank 1 Lane J" "Not powered down,Powered down"
textline "                     "
bitfld.long 0x00 29. " SRDS_LPD_B2_A ,SerDes lane power down - bank 2 Lane A" "Not powered down,Powered down"
bitfld.long 0x00 28. "  SRDS_LPD_B2_B ,SerDes lane power down - bank 2 Lane B" "Not powered down,Powered down"
bitfld.long 0x00 27. "  SRDS_LPD_B2_C ,SerDes lane power down - bank 2 Lane C" "Not powered down,Powered down"
bitfld.long 0x00 26. "  SRDS_LPD_B2_D ,SerDes lane power down - bank 2 Lane D" "Not powered down,Powered down"
textline "                     "
bitfld.long 0x00 25. " SRDS_LPD_B3_A ,SerDes lane power down - bank 3 Lane A" "Not powered down,Powered down"
bitfld.long 0x00 24. "  SRDS_LPD_B3_B ,SerDes lane power down - bank 3 Lane B" "Not powered down,Powered down"
bitfld.long 0x00 23. "  SRDS_LPD_B3_C ,SerDes lane power down - bank 3 Lane C" "Not powered down,Powered down"
bitfld.long 0x00 22. "  SRDS_LPD_B3_D ,SerDes lane power down - bank 3 Lane D" "Not powered down,Powered down"
textline "                     "
bitfld.long 0x00 13. " SRDS_EN       ,SerDes enable" "Disabled,Enabled"
textline "                     "
group.long (edbg:0x01000000+0x05)++0x00 "Miscellaneous PLL-Related Configuration"
line.byte 0x00 "MISC_PLL,MISC_PLL" 
bitfld.long 0x00 7. "     DDR_SYNC ,DDR synchronous mode" "Asynchronous,Synchronous"
textline "                     "
group.long (edbg:0x01000000+0x06)++0x00 "Boot Configuration"
line.long 0x00 "BOOT_CONF,BOOT_CONF"
bitfld.long 0x00 28.--31. " PBI_SRC    ,Pre-boot initialization source" "I2C1 normal addressing,I2C1 extended addressing,,,SPI 16-bit addressing,SPI 24-bit addressing,eSDHC,,eLBC FCM 8-bit small page NAND,eLBC FCM 8-bit large page NAND,,,eLBC GPCM 8-bit NOR,eLBC GPCM 16-bit NOR,eLBC GPCM 32-bit NOR,Disabled"
bitfld.long 0x00 23.--27. "  BOOT_LOC ,Boot location" "PCIe1,PCIe2,PCIe3,PCIe4,,,,,sRIO1,sRIO2,,,,,,,Memory complex 1,,,,,,,,eLBC FCM 8-bit small page NAND,eLBC FCM 8-bit large page NAND,,,eLBC GPCM 8-bit NOR,eLBC GPCM 16-bit NOR,eLBC GPCM 32-bit NOR,"
textline "                     "
bitfld.long 0x00 22. " BOOT_HO    ,Boot holdoff mode" "All cores except core 0,All cores"
bitfld.long 0x00 21. "         SB_EN    ,Secure boot enable" "Disabled,Enabled"
textline "                     "
group.long (edbg:0x01000000+0x07)++0x00 "Clocking Configuration"
line.long 0x00 "CLK_CONF,CLK_CONF"
bitfld.long 0x00 30. " FM_CLK_SEL ,Frame manager clock select" "Platform clock /2,Core cluster PLL 2 /2 or /4"
bitfld.long 0x00 26. "  HWA_ASYNC_DIV ,Hardware accelerator async divider" "Core cluster PLL 2 /2,Core cluster PLL 2 /4"
textline "                     "
bitfld.long 0x00 24.--25. " DRAM_LAT ,DDR latency" "6-6-6/7-7-7,8-8-8/9-9-9/10-10-10/11-11-11,,5-5-5"
bitfld.long 0x00 23. "  DDR_RATE ,DDR data rate" "0,1"
bitfld.long 0x00 22. "    MCK_TO_PLAT_RAT ,MCK to platform (freq) ratio" "Ratio of 1,Ratio of 1/2"
textline "                     "
group.long (edbg:0x01000000+0x08)++0x00 "Memory and High-Speed I/O Configuration"
line.long 0x00 "MHSIO_CONF,MHSIO_CONF" 
bitfld.long 0x00 25.--27. " RIO_DEVICE_ID ,RapidIO device ID" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "  RIO_SYS_SIZE ,RapidIO system size" "256 devices,65536 devices"
textline "                     "
bitfld.long 0x00 21.--23. " HOST_AGT_B1 ,Host/agent bank 1" "All host,All agent,1st two agent,1st and 3rd agent,1st and 4th agent,2nd and 3rd agent,2nd and 4th agent,3rd and 4th agent"
bitfld.long 0x00 20. "  HOST_AGT_B2 ,Host/agent bank 2" "Host (RC),Agent (EP)"
bitfld.long 0x00 19. "  HOST_AGT_B3 ,Host/agent bank 3" "Host (RC),Agent (EP)"
textline "                     "
group.long (edbg:0x01000000+0x09)++0x00 "General Purpose Information (no affect)"
line.long 0x00 "GP_INFO,GP_INFO" 
textline "                     "
width 12.
group.long (edbg:0x01000000+0x0B)++0x00 "Pin Multiplexing Configuration"
line.long 0x00 "GROUP_A,GROUP_A"
bitfld.long 0x00 31. " GPIO_1588[0] ,GPIO or 1588 functionality [GPIO[31],TSEC_1588_PULSE_OUT2]" "1588,GPIO"
bitfld.long 0x00 30. "  GPIO_1588[1] ,GPIO or 1588 functionality [GPIO[30],TSEC_1588_ALARM_OUT2]" "1588,GPIO"
textline "                     "
bitfld.long 0x00 26.--28. " I2C  ,I2C3 and I2C4 pin functionality" "IIC{3/4}_[SCL/SDA],IIC3[SCL/SDA]|/EVT[5:6],GPIO[16:17]|IIC4_[SCL/SDA],GPIO[16:17]|/EVT[5:6],/SDHC_CD|SDHC_WP|IIC4_[SCL/SDA],/SDHC_CD|SDHC_WP|/EVT[5:6],,"
textline "                     "
bitfld.long 0x00 22.--23. " EC1  ,Functionality assigned to the EC1 parallel mode pins" "FM MAC4 RGMII,1588 & ext. timestamp,,No parallel Ethernet"
bitfld.long 0x00 19.--20. " EC2 ,Functionality assigned to the EC2 parallel mode pins" "FM MAC5 RGMII,,,No parallel Ethernet"
bitfld.long 0x00 18. "  GPIO ,Functionality of GPIO[4:7] pins" "GPIO[4:7],USB1_[DRVVBUS/PWRFAULT]|USB2_[DRVVBUS/PWRFAULT]"
textline "                     "
bitfld.long 0x00 15.--17. " UART ,Functionality of the UART pins (UART1_[SOUT/SIN/!RTS/!CTS],UART2_[SOUT/SIN/!RTS/!CTS])" "GPIO[8/10/12/14/9/11/13/15],,,UART1_[SOUT/SIN]|GPIO[12/14/9/11/13/15],UART1_[SOUT/SIN/!RTS/!CTS]|GPIO[9/11/13/15],UART1_[SOUT/SIN]|GPIO[12/14]|UART2_[SOUT/SIN]|GPIO[13/15],UART1_[SOUT/SIN/!RTS/!CTS]|UART2_[SOUT/SIN/!RTS/!CTS],UART1_[SOUT/SIN]|UART2_[SOUT/SIN]|UART3_[SOUT/SIN]|UART4_[SOUT/SIN]"
textline "                     "
bitfld.long 0x00 13. " SPI  ,Functionality of the SPI_CS[0:3] pins" "SPI_CS[0:3],SDHC_DAT[4:7]"
textline "                     "
bitfld.long 0x00 11. " IRQ[3]  ,IRQ[3] pin configuration (corresponding GPIO[21])" "IRQ,GPIO"
bitfld.long 0x00 10. "  IRQ[4] ,IRQ[4] pin configuration (corresponding GPIO[22])" "IRQ,GPIO"
bitfld.long 0x00 9. "  IRQ[5] ,IRQ[5] pin configuration (corresponding GPIO[23])" "IRQ,GPIO"
bitfld.long 0x00 7. "  IRQ[6] ,IRQ[6] pin configuration (corresponding GPIO[24])" "IRQ,GPIO"
bitfld.long 0x00 6. "  IRQ[7] ,IRQ[7] pin configuration (corresponding GPIO[25])" "IRQ,GPIO"
bitfld.long 0x00 5. "  IRQ[8] ,IRQ[8] pin configuration (corresponding GPIO[26])" "IRQ,GPIO"
bitfld.long 0x00 3. "  IRQ[9] ,IRQ[9] pin configuration (corresponding GPIO[27])" "IRQ,GPIO"
bitfld.long 0x00 2. "  IRQ[10] ,IRQ[10] pin configuration (corresponding GPIO[28])" "IRQ,GPIO"
bitfld.long 0x00 1. "  IRQ[11] ,IRQ[11] pin configuration (corresponding GPIO[29])" "IRQ,GPIO"
textline "                     "
bitfld.long 0x00 0. " IRQ_OUT ,Functionality of the IRQ_OUT pin" "/IRQ_OUT,/EVT[9]"
group.long (edbg:0x01000000+0x0C)++0x00
line.long 0x00 "GROUP_B,GROUP_B" 
bitfld.long 0x00 31. " DMA1    ,Functionality of the DMA1 pins" "/DMA1_D[REQ/ACK/DONE]0,GPIO[18:19]"
bitfld.long 0x00 28.--29. "  DMA2 ,Functionality of the DMA1 pins" "/DMA2_D[REQ/ACK/DONE]0,LB_{DVAL/SRCID[0:1]},GPIO[20]/EVT[7:8],"
bitfld.long 0x00 27. "  GTX_CLK125_SEL ,Selects unique/dedicated GTX_CLK125 reference clock sources" "Unique,Dedicated"
width 0xb
textline ""