; -------------------------------------------------------------------------------- ; @Title: OMAP4470 On-Chip Peripherals ; @Props: Released ; @Author: KAM ; @Changelog: ; 2011-10-05 KAM ; 2011-12-13 KAM ; @Manufacturer: TI - Texas Instruments ; @Doc: XML GENERATED ; @Core: ARM968E ; @Chip: OMAP4470 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peromap4470_arm9.per 7592 2017-02-18 13:54:14Z askoncej $ config 16. 8. ; ; WARNING: EXPORT NOTICE ; ; Recipient agrees to not knowingly export or re-export, directly or ; indirectly, any product or technical data (as defined by the U.S., EU, and ; other Export Administration Regulations) including software, or any ; controlled product restricted by other applicable national regulations, ; received from Disclosing party under this Agreement, or any direct ; product of such technology, to any destination to which such export or ; re-export is restricted or prohibited by U.S. or other applicable laws, ; without obtaining prior authorisation from U.S. Department of Commerce ; and other competent Government authorities to the extent required by ; those laws. This provision shall survive termination or expiration of this ; Agreement. ; ; According to our best knowledge of the state and end-use of this ; product or technology, and in compliance with the export control ; regulations of dual-use goods in force in the origin and exporting ; countries, this technology is classified as follows: ; ; US ECCN: 3E991 ; EU ECCN: EAR99 ; ; And may require export or re-export license for shipping it in compliance ; with the applicable regulations of certain countries. ; ; base ad:0x00000000 tree "Core Registers" width 8. tree "ID Registers" rgroup c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" tree.end tree "System Configuration and Control" width 8. group c15:0x1--0x1 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction SRAM Enable" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" bitfld.long 0x0 3. " W ,Write Buffer" "Disable,Enable" bitfld.long 0x0 2. " D ,Data SRAM Enable" "Disable,Enable" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,1" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end tree.end tree.open "IVA_HD_Overview" tree "SYSCTRL_iCONT" base ad:0xDA400 width 26. rgroup.long 0x0++0x3 line.long 0x00 "IVAHD_REVISION,IP revision identifier (X.Y.R). Used by software to track features, bugs, and compatibility" hexmask.long 0x00 0.--31. 1. " REVISION ,IP revision" rgroup.long 0x4++0x3 line.long 0x00 "IVAHD_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x00 14. " ECD3 ,ECD3 available0: ECD3 not present 1: ECD3 present" "0,1" bitfld.long 0x00 13. " MC3 ,MC3 available0: MC3 not present 1: MC3 present" "0,1" bitfld.long 0x00 12. " IPE3 ,iPE3 available0: iPE3 not present 1: iPE3 present" "0,1" textline " " bitfld.long 0x00 11. " CALC3 ,CALC3 available0: CALC3 not present 1: CALC3 present" "0,1" bitfld.long 0x00 10. " IME3 ,iME3 available0: iME3 not present 1: iME3 present" "0,1" bitfld.long 0x00 9. " ILF3 ,iLF3 available0: iLF3 not present 1: iLF3 present" "0,1" textline " " bitfld.long 0x00 8. " VDMA ,vDMA available0: vDMA not present 1: vDMA present" "0,1" bitfld.long 0x00 7. " ICONT2 ,iCONT2 available0: iCONT2 not present 1: iCONT2 present" "0,1" bitfld.long 0x00 6. " ICONT1 ,iCONT1 available0: iCONT1 not present 1: iCONT1 present" "0,1" textline " " bitfld.long 0x00 4.--5. " SL2BANK ,- . - . - . - ." "1bank,2bank,4bank,8bank" bitfld.long 0x00 0.--3. " SL2SIZE ,Size of SL2 memory - . - . - . - . - . - . - . - . - . - . - . - . - . - ." "0,16kB,32kB,48kB,64kB,96kB,128kB,160kB,192kB,224kB,256kB,320kB,384kB,448kB,512kB,15" group.long 0x10++0x3 line.long 0x00 "IVAHD_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode.By definition, initiator may generate read/write transaction as long as it is out of STANDBY state.0x0 and 0x3: Reserved. - . - . - ." "0,no,smart,3" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode.By definition, target can handle read/write transaction as long as it is out of IDLE state.0x0 and 0x3: Reserved. - . - . - ." "0,no,smart,3" group.long 0x24++0x3 line.long 0x00 "IVAHD_IRQSTATUS_RAW,Per-event raw interrupt status vector.Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Settable raw status for Clock Programming Error event - . - . - . - ." "noaction_/_noevent,set_/_pending" group.long 0x28++0x3 line.long 0x00 "IVAHD_IRQSTATUS,Per-event 'enabled' interrupt status vector, line 0.Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clearable, enabled status for Clock Programming Error event - . - . - . - ." "noaction_/_noevent,clear_/_pending" group.long 0x2C++0x3 line.long 0x00 "IVAHD_IRQENABLE_SET,Per-event interrupt enable bit vector.Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clock Programing Error - . - . - . - ." "noaction_/_disabled,enable_/_enabled" group.long 0x30++0x3 line.long 0x00 "IVAHD_IRQENABLE_CLR,Per-event interrupt enable bit vector.Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x00 0. " SYSCTRL_CLKERR ,Clock Programing Error - . - . - . - ." "noaction_/_disabled,disable_/_enabled" group.long 0x34++0x3 line.long 0x00 "IVAHD_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector.Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Settable raw status for SYNC INPUT event. For each bit of the bit field: Read 0: No event pending Read 1: Event pending Write 0: No action Write 1: Set event (debug)" group.long 0x38++0x3 line.long 0x00 "IVAHD_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector, line 0.Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Clearable, enabled status for SYNC INPUT event. For each bit of the bit field: Read 0: No (enabled) event pending Read 1: Event pending Write 0: No action Write 1: Clear (raw) event" group.long 0x3C++0x3 line.long 0x00 "IVAHD_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector.Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Enable for interrupt event. For each bit of the bit field: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Enable interrupt" group.long 0x40++0x3 line.long 0x00 "IVAHD_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector.Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." hexmask.long.byte 0x00 0.--7. 1. " SYNC_INPUT7_0 ,Enable for interrupt event. For each bit of the bitfiled: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Disable interrupt" group.long 0x50++0x3 line.long 0x00 "IVAHD_CLKCTRL,IVA-HD clock control register" bitfld.long 0x00 10. " SMSET ,Clock control of SMSET 0: Exit idle state and start SMSET clock 1: Request SMSET to go to idle state and stop SMSET clockNote: Shutting down SMSET clock may hang system if software performs software instrumentation and/or access to its configuration port." "0,1" bitfld.long 0x00 9. " MSGIF ,Clock control of MSGIF 0: Exit idle state and start MSGIF clock 1: Request MSGIF to go to idle state and stop MSGIF clock" "0,1" bitfld.long 0x00 8. " ECD3 ,Clock control of ECD3 0: Exit idle state and start ECD3 clock 1: Request ECD3 to go to idle state and stop ECD3 clock" "0,1" textline " " bitfld.long 0x00 7. " MC3 ,Clock control of MC3 0: Exit idle state and start MC3 clock 1: Request MC3 to go to idle state and stop MC3 clock" "0,1" bitfld.long 0x00 6. " IPE3 ,Clock control of iPE3 0: Exit idle state and start iPE3 clock 1: Request iME3 to go to idle state and stop iPE3 clock" "0,1" bitfld.long 0x00 5. " CALC3 ,Clock control of CALC3 0: Exit idle state and start CALC3 clock 1: Request CALC3 to go to idle state and stop CALC3 clock" "0,1" textline " " bitfld.long 0x00 4. " ILF3 ,Clock control of iLF3 0: Exit idle state and start iLF3 clock 1: Request iLF3 to go to idle state and stop iLF3 clock" "0,1" bitfld.long 0x00 3. " IME3 ,Clock control of iME3 0: Exit idle state and start iME3 clock 1: Request iME3 to go to idle state and stop iME3 clock" "0,1" bitfld.long 0x00 2. " VDMA ,Clock control of vDMA 0: Exit idle state and start vDMA clock 1: Request vDMA to go to idle state and stop vDMA clock" "0,1" textline " " bitfld.long 0x00 1. " ICONT2 ,Clock control of iCONT2 0: Exit idle state and start iCONT2 clock 1: Request iCONT2 to go to idle state and stop iCONT2 clock" "0,1" bitfld.long 0x00 0. " ICONT1 ,Clock control of iCONT1 0: Exit idle state and start iCONT1 clock 1: Request iCONT1 to go to idle state and stop iCONT1 clock" "0,1" rgroup.long 0x54++0x3 line.long 0x00 "IVAHD_CLKST,IVA-HD clock status register" bitfld.long 0x00 10. " SMSET ,Clock status of SMSET 1: SMSET clock is active 0: SMSET clock is idled" "0,1" bitfld.long 0x00 9. " MSGIF ,Clock status of MSGIF 1: MSGIF clock is active 0: MSGIF clock is idled" "0,1" bitfld.long 0x00 8. " ECD3 ,Clock status of ECD3 1: ECD3 clock is active 0: ECD3 clock is idled" "0,1" textline " " bitfld.long 0x00 7. " MC3 ,Clock status of MC3 1: MC3 clock is active 0: MC3 clock is idled" "0,1" bitfld.long 0x00 6. " IPE3 ,Clock status of iPE3 1: iPE3 clock is active 0: iPE3 clock is idled" "0,1" bitfld.long 0x00 5. " CALC3 ,Clock status of CALC3 1: CALC3 clock is active 0: CALC3 clock is idled" "0,1" textline " " bitfld.long 0x00 4. " ILF3 ,Clock status of iLF3 1: iLF3 clock is active 0: iLF3 clock is idled" "0,1" bitfld.long 0x00 3. " IME3 ,Clock status of iME3 1: iME3 clock is active 0: iME3 clock is idled" "0,1" bitfld.long 0x00 2. " VDMA ,Clock status of vDMA 1: vDMA clock is active 0: vDMA clock is idled" "0,1" textline " " bitfld.long 0x00 1. " ICONT2 ,Clock status of iCONT2 1: iCONT2 clock is active 0: iCONT2 clock is idled" "0,1" bitfld.long 0x00 0. " ICONT1 ,Clock status of iCONT1 1: iCONT1 clock is active 0: iCONT1 clock is idled" "0,1" rgroup.long 0x58++0x3 line.long 0x00 "IVAHD_STDBYST,IVA-HD STANDBY status" bitfld.long 0x00 2. " vDMA ,vDMA Standby status 0: module is not in Standby 1: module is in Standby" "0,1" bitfld.long 0x00 1. " ICONT2 ,iCONT2 Standby status 0: module is not in Standby 1: module is in Standby" "0,1" bitfld.long 0x00 0. " ICONT1 ,iCONT1 Standby status 0: module is not in Standby 1: module is in Standby" "0,1" tree.end tree.end tree.open "Mailbox" tree "IVAHD_Mailbox_ICONT" base ad:0x8DA800 tree "Channel_0" width 27. rgroup.long 0x80++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x10C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x108++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x104++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x100++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x40++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_1" width 27. rgroup.long 0x84++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x11C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x118++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x114++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x110++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x44++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" width 27. rgroup.long 0x88++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x12C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x128++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x124++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x120++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x48++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xC8++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" width 27. rgroup.long 0x8C++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x13C++0x3 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x138++0x3 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x00 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x134++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x130++0x3 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x00 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7 - . - . - . - ." "No_action,1" bitfld.long 0x00 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7 - . - . - . - ." "0,1" bitfld.long 0x00 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6 - . - . - . - ." "0,1" bitfld.long 0x00 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" bitfld.long 0x00 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4 - . - . - . - ." "0,1" bitfld.long 0x00 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3 - . - . - . - ." "0,1" bitfld.long 0x00 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" bitfld.long 0x00 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1 - . - . - . - ." "0,1" bitfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" textline " " bitfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0 - . - . - . - ." "0,1" group.long 0x4C++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xCC++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_4" width 24. rgroup.long 0x90++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x50++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD0++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end tree "Channel_5" width 24. rgroup.long 0x94++0x3 line.long 0x00 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox - . - ." "0,1" group.long 0x54++0x3 line.long 0x00 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x00 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" rgroup.long 0xD4++0x3 line.long 0x00 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x00 0.--2. " NBOFMSGMBM ,Number of unread messages in MailboxNote: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" tree.end textline "" width 19. rgroup.long 0x0++0x3 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x00 0.--31. 1. " REVISION ,IP Revision" group.long 0x10++0x3 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle Mode - . - . - . - ." "b00,b01,b10,b11" bitfld.long 0x00 0. " SOFTRESET ,Softreset - . - . - . - ." "b0,b1" tree.end tree.end textline ""