; -------------------------------------------------------------------------------- ; @Title: tbd. ; @Description: tbd. ; @Author: - ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permpct4xxxm.per 6473 2015-10-28 11:40:58Z mbussjaeger $ width 16. config 16. 8. tree.open "Memory Management Registers" group spr:1012.++0x0 line.quad 0x0 " MMUCSR0,MMU Control and Status Register" bitfld.quad 0x0 2. "L2TLB0_FL ,TLB0 flush invalidate" "0,1" bitfld.quad 0x0 1. " L2TLB1_FL ,TLB1 flush invalidate" "0,1" rgroup spr:1015.++0x0 line.quad 0x0 " MMUCFG,MMU Configuration Register (r/o)" hexmask.quad.byte 0x0 24.--27. 0x1 "LPIDSIZE , The number of LPID bits implemented (0b0110 indicates LPIDR is 6 bits)" hexmask.quad.byte 0x0 17.--23. 0x1 " RASIZE , Real address size supported by the implementation. (0b0100100 indicates 36 PA bits)" hexmask.quad.byte 0x0 11.--14. 0x1 " NPIDS ,Number of PID Registers" hexmask.quad.byte 0x0 6.--10. 0x1 " PIDSIZE ,PID Register Size" hexmask.quad.byte 0x0 2.--3. 0x1 " NTLBS ,Number of TLBs" hexmask.quad.byte 0x0 0.--1. 0x1 " MAVN ,MMU Architecture Version Number" TEXTLINE "Process ID Registers" group spr:48.++0 line.quad 0x0 " PID0,Process ID 0 Register" hexmask.quad.byte 0x0 0.--7. 0x1 "PID0 ,Process ID 0" TEXTLINE "TLB Configuration Registers" rgroup spr:688.++0x0 line.quad 0x0 " TLB0CFG,TLB 0 Configuration Register (r/o)" hexmask.quad.byte 0x0 24.--31. 0x1 "ASSOC ,Associativity of TLB0" bitfld.quad 0x0 20.--23. " MINSIZE ,Minimum Page Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" bitfld.quad 0x0 16.--19. " MAXSIZE ,Maximum Page Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" bitfld.quad 0x0 15. " IPROT ,Invalidate protect supported" "0,1" bitfld.quad 0x0 1. " LAVAIL ,Variable Page Size Availability of TLB" "0,1" hexmask.quad.word 0x0 0.--11. 0x1 " NENTRY ,Number of Entries in TLB" rgroup spr:689.++0x0 line.quad 0x0 " TLB1CFG,TLB 1 Configuration Register (r/o)" hexmask.quad.byte 0x0 24.--31. 0x1 "ASSOC ,Associativity of TLB0" bitfld.quad 0x0 20.--23. " MINSIZE ,Minimum Page Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" bitfld.quad 0x0 16.--19. " MAXSIZE ,Maximum Page Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" bitfld.quad 0x0 15. " IPROT ,Invalidate protect supported" "0,1" bitfld.quad 0x0 1. " LAVAIL ,Variable Page Size Availability of TLB" "0,1" hexmask.quad.word 0x0 0.--11. 0x1 " NENTRY ,Number of Entries in TLB" TEXTLINE "MMU Assist Registers" group spr:624.++0x0 line.quad 0x0 " MAS0,MMU Assist Register 0" bitfld.quad 0x0 28. "TLBSEL ,Selects TLB for Access" "TLB 0,TLB 1" hexmask.quad.byte 0x0 16.--21. 0x1 " ESEL ,Entry Select" hexmask.quad.byte 0x0 0.--1. 0x1 " NV ,Next Victim" group spr:625.++0x0 line.quad 0x0 " MAS1,MMU Assist Register 1" bitfld.quad 0x0 31. "V ,TLB Valid Bit" "0,1" bitfld.quad 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.quad.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.quad 0x0 12. " TS ,Translation Space" "0,1" bitfld.quad 0x0 8.--11. " TSIZE ,Translation Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" group spr:626.++0x0 line.quad 0x0 " MAS2,MMU Assist Register 2" hexmask.quad 0x0 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x0 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x0 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x0 4. " W ,Write-Through" "0,1" bitfld.quad 0x0 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x0 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x0 1. " G ,Guarded" "0,1" bitfld.quad 0x0 0. " E ,Endianness" "big,little" group spr:627.++0x0 line.quad 0x0 " MAS3,MMU Assist Register 3" hexmask.quad 0x0 12.--31. 0x1 "RPN ,Real Page Number" bitfld.quad 0x0 9. " U0 ,User Bit 0" "0,1" bitfld.quad 0x0 8. " U1 ,User Bit 1" "0,1" bitfld.quad 0x0 7. " U2 ,User Bit 2" "0,1" bitfld.quad 0x0 6. " U3 ,User Bit 3" "0,1" bitfld.quad 0x0 5. " UX ,UX Permission Bit" "0,1" bitfld.quad 0x0 4. " SX ,SX Permission Bit" "0,1" bitfld.quad 0x0 3. " UW ,UW Permission Bit" "0,1" bitfld.quad 0x0 2. " SW ,SW Permission Bit" "0,1" bitfld.quad 0x0 1. " UR ,UR Permission Bit" "0,1" bitfld.quad 0x0 0. " SR ,SR Permission Bit" "0,1" group spr:628.++0x0 line.quad 0x0 " MAS4,MMU Assist Register 4" bitfld.quad 0x0 28. "TLBSELD , Default TLB for Access" "TLB 0,TLB 1" bitfld.quad 0x0 8.--11. " TSIZE ,Translation Size" "1 KB,4 KB,16 KB,64 KB,256 KB,1 MB,4 MB,16 MB,64 MB,256 MB,1 GB,4 GB,16 GB,64 GB,256 GB,1 TB" bitfld.quad 0x0 6. " X0D ,Default X0 Value" "0,1" bitfld.quad 0x0 5. " X1D ,Default X1 Value" "0,1" bitfld.quad 0x0 4. " WD ,Default W Value" "0,1" bitfld.quad 0x0 3. " ID ,Default I Value" "0,1" bitfld.quad 0x0 2. " MD ,Default M Value" "0,1" bitfld.quad 0x0 1. " GD ,Default G Value" "0,1" bitfld.quad 0x0 0. " ED ,Default E Value" "0,1" group spr:339.++0x0 line.quad 0x0 " MAS5,MMU Assist Register 5" bitfld.quad 0x0 31. "SGS ,Guest/Supervisor Value for Search" "0,1" hexmask.quad.byte 0x0 0.--5. 0x1 " SLPID ,Search LPID" group spr:630.++0x0 line.quad 0x0 " MAS6,MMU Assist Register 6" hexmask.quad.byte 0x0 16.--23. 0x1 "SPID ,Search PID" bitfld.quad 0x0 0. " SAS ,Address Space Value for Search" "0,1" group spr:944.++0x0 line.quad 0x0 " MAS7,MMU Assist Register 7" hexmask.quad.byte 0x0 0.--7. 0x1 "RPN_HIGH ,Real page number, 8 high-order bits" group spr:341.++0x0 line.quad 0x0 " MAS8,MMU Assist Register 8" bitfld.quad 0x0 31. "TGS ,Translation guest space" "0,1" bitfld.quad 0x0 30. " VF ,Virtualization fault" "0,1" hexmask.quad.byte 0x0 0.--5. 0x1 " TLPID ,Translation logical partition ID" tree.end tree "TLB1 Array" group tlb:0x0++0x1f line.long 0x0 " TLB1[0]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[0]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[0]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[0]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[0]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x20++0x1f line.long 0x0 " TLB1[1]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[1]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[1]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[1]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[1]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x40++0x1f line.long 0x0 " TLB1[2]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[2]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[2]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[2]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[2]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x60++0x1f line.long 0x0 " TLB1[3]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[3]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[3]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[3]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[3]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x80++0x1f line.long 0x0 " TLB1[4]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[4]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[4]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[4]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[4]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0xA0++0x1f line.long 0x0 " TLB1[5]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[5]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[5]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[5]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[5]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0xC0++0x1f line.long 0x0 " TLB1[6]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[6]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[6]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[6]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[6]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0xE0++0x1f line.long 0x0 " TLB1[7]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[7]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[7]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[7]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[7]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x100++0x1f line.long 0x0 " TLB1[8]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[8]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[8]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[8]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[8]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x120++0x1f line.long 0x0 " TLB1[9]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[9]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[9]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[9]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[9]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x140++0x1f line.long 0x0 " TLB1[10]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[10]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[10]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[10]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[10]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x160++0x1f line.long 0x0 " TLB1[11]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[11]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[11]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[11]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[11]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x180++0x1f line.long 0x0 " TLB1[12]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[12]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[12]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[12]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[12]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x1A0++0x1f line.long 0x0 " TLB1[13]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[13]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[13]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[13]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[13]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x1C0++0x1f line.long 0x0 " TLB1[14]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[14]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[14]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[14]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[14]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x1E0++0x1f line.long 0x0 " TLB1[15]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[15]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[15]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[15]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[15]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x200++0x1f line.long 0x0 " TLB1[16]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[16]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[16]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[16]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[16]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x220++0x1f line.long 0x0 " TLB1[17]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[17]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[17]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[17]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[17]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x240++0x1f line.long 0x0 " TLB1[18]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[18]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[18]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[18]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[18]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x260++0x1f line.long 0x0 " TLB1[19]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[19]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[19]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[19]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[19]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x280++0x1f line.long 0x0 " TLB1[20]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[20]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[20]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[20]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[20]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x2A0++0x1f line.long 0x0 " TLB1[21]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[21]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[21]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[21]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[21]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x2C0++0x1f line.long 0x0 " TLB1[22]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[22]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[22]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[22]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[22]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x2E0++0x1f line.long 0x0 " TLB1[23]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[23]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[23]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[23]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[23]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x300++0x1f line.long 0x0 " TLB1[24]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[24]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[24]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[24]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[24]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x320++0x1f line.long 0x0 " TLB1[25]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[25]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[25]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[25]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[25]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x340++0x1f line.long 0x0 " TLB1[26]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[26]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[26]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[26]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[26]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x360++0x1f line.long 0x0 " TLB1[27]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[27]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[27]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[27]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[27]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x380++0x1f line.long 0x0 " TLB1[28]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[28]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[28]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[28]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[28]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x3A0++0x1f line.long 0x0 " TLB1[29]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[29]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[29]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[29]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[29]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x3C0++0x1f line.long 0x0 " TLB1[30]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[30]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[30]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[30]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[30]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x3E0++0x1f line.long 0x0 " TLB1[31]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[31]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[31]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[31]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[31]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x400++0x1f line.long 0x0 " TLB1[32]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[32]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[32]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[32]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[32]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x420++0x1f line.long 0x0 " TLB1[33]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[33]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[33]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[33]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[33]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x440++0x1f line.long 0x0 " TLB1[34]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[34]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[34]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[34]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[34]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x460++0x1f line.long 0x0 " TLB1[35]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[35]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[35]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[35]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[35]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x480++0x1f line.long 0x0 " TLB1[36]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[36]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[36]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[36]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[36]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x4A0++0x1f line.long 0x0 " TLB1[37]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[37]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[37]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[37]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[37]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x4C0++0x1f line.long 0x0 " TLB1[38]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[38]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[38]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[38]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[38]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x4E0++0x1f line.long 0x0 " TLB1[39]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[39]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[39]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[39]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[39]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x500++0x1f line.long 0x0 " TLB1[40]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[40]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[40]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[40]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[40]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x520++0x1f line.long 0x0 " TLB1[41]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[41]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[41]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[41]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[41]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x540++0x1f line.long 0x0 " TLB1[42]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[42]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[42]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[42]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[42]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x560++0x1f line.long 0x0 " TLB1[43]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[43]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[43]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[43]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[43]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x580++0x1f line.long 0x0 " TLB1[44]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[44]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[44]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[44]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[44]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x5A0++0x1f line.long 0x0 " TLB1[45]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[45]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[45]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[45]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[45]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x5C0++0x1f line.long 0x0 " TLB1[46]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[46]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[46]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[46]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[46]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x5E0++0x1f line.long 0x0 " TLB1[47]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[47]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[47]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[47]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[47]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x600++0x1f line.long 0x0 " TLB1[48]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[48]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[48]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[48]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[48]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x620++0x1f line.long 0x0 " TLB1[49]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[49]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[49]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[49]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[49]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x640++0x1f line.long 0x0 " TLB1[50]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[50]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[50]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[50]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[50]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x660++0x1f line.long 0x0 " TLB1[51]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[51]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[51]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[51]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[51]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x680++0x1f line.long 0x0 " TLB1[52]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[52]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[52]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[52]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[52]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x6A0++0x1f line.long 0x0 " TLB1[53]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[53]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[53]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[53]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[53]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x6C0++0x1f line.long 0x0 " TLB1[54]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[54]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[54]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[54]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[54]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x6E0++0x1f line.long 0x0 " TLB1[55]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[55]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[55]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[55]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[55]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x700++0x1f line.long 0x0 " TLB1[56]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[56]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[56]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[56]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[56]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x720++0x1f line.long 0x0 " TLB1[57]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[57]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[57]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[57]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[57]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x740++0x1f line.long 0x0 " TLB1[58]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[58]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[58]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[58]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[58]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x760++0x1f line.long 0x0 " TLB1[59]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[59]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[59]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[59]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[59]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x780++0x1f line.long 0x0 " TLB1[60]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[60]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[60]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[60]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[60]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x7A0++0x1f line.long 0x0 " TLB1[61]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[61]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[61]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[61]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[61]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x7C0++0x1f line.long 0x0 " TLB1[62]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[62]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[62]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[62]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[62]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" group tlb:0x7E0++0x1f line.long 0x0 " TLB1[63]a,MMU Assist Register 1" bitfld.long 0x0 31. " V ,TLB Valid Bit" "0,1" bitfld.long 0x0 30. " IPROT ,Invalidate Protect" "0,1" hexmask.long.byte 0x0 16.--23. 0x1 " TID ,Translation Identity" bitfld.long 0x0 12. " TS ,Translation Space" "0,1" bitfld.long 0x0 7.--11. " TSIZE ,Translation Size" "res.,res.,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,128 GB,256 GB,512 GB,1 TB,res." line.quad 0x4 " TLB1[63]b,MMU Assist Register 2" hexmask.quad 0x4 12.--63. 0x1 "EPN ,Effective Page Number" bitfld.quad 0x4 6. " X0 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 5. " X1 ,Implementation-dependent Page Attribute" "0,1" bitfld.quad 0x4 4. " W ,Write-Through" "0,1" bitfld.quad 0x4 3. " I ,Caching Inhibited" "0,1" bitfld.quad 0x4 2. " M ,Memory Coherence Required" "0,1" bitfld.quad 0x4 1. " G ,Guarded" "0,1" bitfld.quad 0x4 0. " E ,Endianness" "big,little" line.long 0xc " TLB1[63]c,MMU Assist Register 3" hexmask.long 0xc 12.--31. 0x1 " RPN ,Real Page Number" bitfld.long 0xc 9. " U0 ,User Bit 0" "0,1" bitfld.long 0xc 8. " U1 ,User Bit 1" "0,1" bitfld.long 0xc 7. " U2 ,User Bit 2" "0,1" bitfld.long 0xc 6. " U3 ,User Bit 3" "0,1" bitfld.long 0xc 5. " UX ,UX Permission Bit" "0,1" bitfld.long 0xc 3. " UW ,UW Permission Bit" "0,1" bitfld.long 0xc 1. " UR ,UR Permission Bit" "0,1" bitfld.long 0xc 4. " SX ,SX Permission Bit" "0,1" bitfld.long 0xc 2. " SW ,SW Permission Bit" "0,1" bitfld.long 0xc 0. " SR ,SR Permission Bit" "0,1" line.long 0x10 " TLB1[63]d,MMU Assist Register 7" hexmask.long.byte 0x10 00.--03. 0x1 " RPN ,Real Page Number (4 high order bits)" line.long 0x14 " TLB1[63]e,MMU Assist Register 8" bitfld.long 0x14 31. " TGS ,Translation guest space" "0,1" bitfld.long 0x14 30. " VF ,Virtualization fault" "0,1" hexmask.long.byte 0x14 00.--04. 0x1 " TLPID ,Translation logical partition ID (compared with the LPIDR to select a TLB entry)" Textline "" tree.end