; --------------------------------------------------------------------------------
; @Title: tbd.
; @Description: tbd.
; @Author: -
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permpct4xxxc.per 6151 2015-05-07 10:45:12Z askoncej $
width 13.
tree.open "L1 Configuration Registers"
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.QUAD 0. "L1CSR0,L1 Cache Configuration & Status Register"
bitfld.quad  0. 18.--19. "CEA     ,Data cache error action" "machine check interrupt,res.,res.,res."
bitfld.quad  0. 16.      "  DCPE   ,Cache error checking enable" "0,1"
bitfld.quad  0. 15.      "  DCPI   ,Cache error injection enable" "0,1"
Textline "                            "
bitfld.quad  0. 12.--13. "  CEDT    ,Data cache error detection/correction type" "Tag&data parity errors ,res.,res.,res."
bitfld.quad  0. 11.      "  DCSLC  ,Cache Snoop Lock Clear" "0,1"
bitfld.quad  0. 10.      "  DCUL   ,Cache Unable to Lock" "0,1"
Textline "                            "
bitfld.quad  0.  9.      "  DCLO    ,Cache Lock Overflow" "0,1"
bitfld.quad  0.  8.      "  DCLFC  ,Cache Lock Bits Flush Clear" "0,1"
bitfld.quad  0.  5.--6.  "  CEIT  ,Cache error injection type" "single-bit data&tag error,res.,res.,res."
Textline "                            "
bitfld.quad  0.  3.      "  DCBZ32  ," "0,1"
bitfld.quad  0.  2.      "  CABT   ,Cache Operation Aborted" "0,1"
bitfld.quad  0.  1.      "  DCFI  ,Cache Flush Invalidate" "0,1"
bitfld.quad  0.  0.      "  DCE  ,Cache Enable" "0,1"
Textline ""
group spr:1011.--1011. "L1CSR1, L1 Cache Configuration & Status Register 1"
LINE.QUAD 0. "L1CSR1,L1 Cache Configuration & Status Register 1"
bitfld.quad  0. 18.--19.   "ICEA    ,Instruction cache error action" "machine check,res.,res.,res."
Textline "                            "
bitfld.quad  0. 16.      "  ICECE   ,Instruction error checking enable" "0,1"
bitfld.quad  0. 15.      "  ICEI    ,Instruction cache error injection enable" "0,1"
bitfld.quad  0. 12.--13. "  ICEDT   ,Instruction cache error detection type" "parity,res.,res.,res."
Textline "                            "
bitfld.quad  0. 11.      "  ICSLC   ,Instruction cache snoop lock clear" "0,1"
bitfld.quad  0. 10.      "  ICUL    ,Instruction cache unable to lock" "0,1"
bitfld.quad  0.  9.      "  ICLO    ,Instruction cache lock overflow" "0,1"
bitfld.quad  0.  8.      "  ICLFC   ,Instruction cache lock bits flash clear" "0,1"
Textline "                            "
bitfld.quad  0.  1.      "  ICFI    ,Instruction cache flash invalidate" "0,1"
bitfld.quad  0.  0.      "  ICE     ,Instruction cache enable" "0,1"
Textline ""
group spr:606.--606. "L1CSR2,L1 Cache Control and Status Register 2"
LINE.QUAD 0. "L1CSR2,L1 Cache Control and Status Register 2"
bitfld.quad  0.  30.       "DCWS    ,Data cache write shadow" "0,1"
hexmask.quad.byte 0. 00.--07. 1. "  DCSTASHID ,Data cache stash ID"
Textline ""
group spr:515.--515. "L1CFG0, L1 Cache Configuration Register 0 (r/o)"
LINE.QUAD  0. "L1CFG0,L1 Cache Configuration Register 0"
bitfld.quad  0.  30.--31.   "CARCH   ,Cache Architecture" "harvard,unified,res (10),res (11)"
Textline "                            "
bitfld.quad  0.  29.      "  DCWPA   ,Cache Way Partitioning Available" "0,1"
bitfld.quad  0.  28.      "  DCFAHA  ,Cache Flush All by Hardware Available" "0,1"
bitfld.quad  0.  27.      "  DCFISWA ,Cache flush/inval by Set and Way Available" "0,1"
bitfld.quad   0. 23.--24. "  DCBSIZE ,Cache Line Size" "32 bytes,64 bytes, res(10),res(11)"
Textline "                            "
bitfld.quad   0. 21.--22. "  DCREPL  ,Cache Replacement Policy" "true LRU,pseudo LRU,pseudo round-robin,res(11)"
Textline "                            "
bitfld.quad   0. 20.      "  DCLA    ,Cache Lockung APU Available" "0,1"
bitfld.quad   0. 19.      "  DCPA    ,Cache Parity Available" "0,1"
bitfld.quad   0. 11.--13. "  DCNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.quad   0. 04.--06. "  DCSIZE  , Cache Size" "8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB "
Textline ""
group spr:516.--516. "L1CFG1, L1 Cache Configuration Register 1"
LINE.QUAD  0. "L1CFG1,L1 Cache Configuration Register 1 (r/o)"
bitfld.quad   0. 27.        "ICFISWA ,Direct cache flush available" "0,1"
bitfld.quad   0. 23.--24. "  ICBSIZE ,Cache Line Size" "32 Bytes,64 Bytes, res(10),res(11)"
Textline "                            "
bitfld.quad   0. 21.--22. "  ICREPL  ,Cache Replacement Policy" "true LRU,pseudo LRU,pseudo round-robin,res(11)"
Textline "                            "
bitfld.quad   0. 20.      "  ICLA    ,Cache Lockung APU Available" "0,1"
bitfld.quad   0. 19.      "  ICPA    ,Cache Parity Available" "0,1"
bitfld.quad   0. 11.--13. "  ICNWAY  ,Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.quad   0. 04.--06. "  ICSIZE  ,Cache Size" "8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB "
Textline "       "
tree.end
base 0
tree.open "L2 Cache Configuration Registers"
group 0.--0. "Access to the cluster associated shared backside L2 cache is given in the peripheral file"
Textline ""
Textline "Open peripheral file: "
button "L2-Cache" "PER.view , ""L2-Cache"""
tree.end
Textline "                            "