; --------------------------------------------------------------------------------
; @Title: tbd.
; @Props: 
; @Author: -
; @Changelog: 
; @Manufacturer: 
; @Doc: 
; @Core: 
; @Chip: 
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permpcp4xxxc.per 5900 2015-01-09 11:57:07Z askoncej $
width 13.
tree.open "L1 Configuration Registers"
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register"
bitfld.long  0. 16.        "DCPE    ,Cache Parity Enable" "0,1"
bitfld.long  0. 15.      "  DCPI    ," "0,1"
Textline "                    "
bitfld.long  0. 11.      "  DCSLC   ,Cache Snoop Lock Clear" "0,1"
bitfld.long  0. 10.      "  DCUL    ,Cache Unable to Lock" "0,1"
bitfld.long  0.  9.      "  DCLO    ,Cache Lock Overflow" "0,1"
bitfld.long  0.  8.      "  DCLFC   ,Cache Lock Bits Flush Clear" "0,1"
Textline "                    "
bitfld.long  0.  3.      "  DCBZ32  ," "0,1"
bitfld.long  0.  2.      "  CABT    ,Cache Operation Aborted" "0,1"
bitfld.long  0.  1.      "  DCFI    ,Cache Flush Invalidate" "0,1"
bitfld.long  0.  0.      "  DCE     ,Cache Enable" "0,1"
Textline ""
group spr:1011.--1011. "L1CSR1, L1 Cache Configuration & Status Register 1"
LINE.LONG 0. "L1CSR1,L1 Cache Configuration & Status Register 1"
bitfld.long  0. 18.--19.   "ICEA    ,Instruction cache error action" "machine check,res.,res.,res."
Textline "                    "
bitfld.long  0. 16.      "  ICECE   ,Instruction error checking enable" "0,1"
bitfld.long  0. 15.      "  ICEI    ,Instruction cache error injection enable" "0,1"
bitfld.long  0. 12.--13. "  ICEDT   ,Instruction cache error detection type" "parity,res.,res.,res."
Textline "                    "
bitfld.long  0. 11.      "  ICSLC   ,Instruction cache snoop lock clear" "0,1"
bitfld.long  0. 10.      "  ICUL    ,Instruction cache unable to lock" "0,1"
bitfld.long  0.  9.      "  ICLO    ,Instruction cache lock overflow" "0,1"
bitfld.long  0.  8.      "  ICLFC   ,Instruction cache lock bits flash clear" "0,1"
Textline "                    "
bitfld.long  0.  1.      "  ICFI    ,Instruction cache flash invalidate" "0,1"
bitfld.long  0.  0.      "  ICE     ,Instruction cache enable" "0,1"
Textline ""
group spr:606.--606. "L1CSR2,L1 Cache Control and Status Register 2"
LINE.LONG 0. "L1CSR2,L1 Cache Control and Status Register 2"
bitfld.long  0.  30.       "DCWS    ,Data cache write shadow" "0,1"
hexmask.long.byte 0. 00.--07. 1. "  DCSTASHID ,Data cache stash ID"
Textline ""
group spr:515.--515. "L1CFG0, L1 Cache Configuration Register 0 (r/o)"
LINE.Long  0. "L1CFG0,L1 Cache Configuration Register 0"
bitfld.long  0.  30.--31.   "CARCH   ,Cache Architecture" "harvard,unified,res (10),res (11)"
Textline "                    "
bitfld.long  0.  29.      "  DCWPA   ,Cache Way Partitioning Available" "0,1"
bitfld.long  0.  28.      "  DCFAHA  ,Cache Flush All by Hardware Available" "0,1"
bitfld.long  0.  27.      "  DCFISWA ,Cache flush/inval by Set and Way Available" "0,1"
bitfld.long   0. 23.--24. "  DCBSIZE ,Cache Line Size" "32 bytes,64 bytes, res(10),res(11)"
Textline "                    "
bitfld.long   0. 21.--22. "  DCREPL  ,Cache Replacement Policy" "true LRU,pseudo LRU,pseudo round-robin,res(11)"
Textline "                    "
bitfld.long   0. 20.      "  DCLA    ,Cache Lockung APU Available" "0,1"
bitfld.long   0. 19.      "  DCPA    ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  DCNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.long   0. 04.--05. "  DCSIZE  , Cache Size" "8 KB,16 KB,32 KB,64 KB "
Textline ""
group spr:516.--516. "L1CFG1, L1 Cache Configuration Register 1"
LINE.Long  0. "L1CFG1,L1 Cache Configuration Register 1 (r/o)"
bitfld.long   0. 27.        "ICFISWA ,Direct cache flush available" "0,1"
bitfld.long   0. 23.--24. "  ICBSIZE ,Cache Line Size" "32 Bytes,64 Bytes, res(10),res(11)"
Textline "                    "
bitfld.long   0. 21.--22. "  ICREPL  ,Cache Replacement Policy" "true LRU,pseudo LRU,pseudo round-robin,res(11)"
Textline "                    "
bitfld.long   0. 20.      "  ICLA    ,Cache Lockung APU Available" "0,1"
bitfld.long   0. 19.      "  ICPA    ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  ICNWAY  ,Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.long   0. 04.--05. "  ICSIZE  ,Cache Size" "8 KB,16 KB,32 KB,64 KB "
tree.end
tree.open "L2 Cache Configuration Registers"
group spr:1017.++0 "L2CSR0,L2 Cache Control and Status Register 0"
LINE.LONG 0. "L2CSR0,L2 Cache Control and Status Register 0"
bitfld.long 0. 31.        "L2E     ,L2 cache enable" "0,1"
bitfld.long 0. 30.      "  L2PE    ,L2 data parity generation and checking enable" "0,1"
bitfld.long 0. 26.--28. "  L2WP    ,L2 instruction/data way partitioning" "unpartitioned,1 instr - 7 data,2 instr - 6 data,3 instr - 5 data,4 instr - 4 data,5 instr - 3 data,6 instr - 2 data,7 instr - 1 data"
Textline "                    "
bitfld.long 0. 21.      "  L2FI    ,L2 cache flash invalidate" "0,1"
bitfld.long 0. 20.      "  L2IO    ,L2 cache instruction only" "0,1"
bitfld.long 0. 16.      "  L2DO    ,L2 cache data only" "0,1"
bitfld.long 0. 12.--13. "  L2REP   ,L2 line replacement algorithm" "SPLRU,res.,SPLPU,PLRU"
Textline "                    "
bitfld.long 0. 11.      "  L2FL    ,L2 cache flush" "0,1"
bitfld.long 0. 10.      "  L2LFC   ,L2 cache lock flash clear" "0,1"
bitfld.long 0. 07.      "  L2LOA   ,L2 cache lock overflow allocate" "0,1"
bitfld.long 0. 05.      "  L2LO    ,L2 cache lock overflow" "0,1"
Textline ""
group spr:1018.++0 "L2CSR1,L2 Cache Control and Status Register 1"
LINE.LONG 0. "L2CSR1,L2 Cache Control and Status Register 1"
bitfld.long 0. 31.                 "L2INSTLOSSLIMITDIS  ,L2 Instruction Loss Limit Disable" "0,1"
bitfld.long 0. 28.--29.          "  L2INSTLOSSLIMIT     ,specifies how many consecutive cycles instruction fetches can lose backside L2 arbitration before raising its priority" "8,4,8,16"
Textline "                    "
bitfld.long 0. 27.               "  L2SNPWINLIMITDIS    ,L2 Snoop Win Limit Disable" "0,1"
bitfld.long 0. 24.--26.          "  L2SNPWINLIMIT       ,specifies how many consecutive snoops can win arbitration before allowing another unit to win" "8,2,4,8,16,32,64,128"
Textline "                    "
hexmask.long.byte 0. 00.--07. 1. "  L2STASHID          ,L2 cache stash ID"
Textline ""
group spr:519.++0 "L2CFG0,L2 Configuration Register"
LINE.LONG 0. "L2CFG0,L2 Configuration Register"
bitfld.long  0. 29.--30.     "L2CTEHA  ,L2 cache tags error handling available" "res.,parity,res.,res.    "
bitfld.long  0. 27.--28.   "  L2CDEHA  ,L2 cache data error handling available" "res.,res.,res.,par+ecc "
bitfld.long  0. 26.        "      L2CIDPA  ,Cache instruction and data partitioning available" "0,1       "
Textline "                    "
bitfld.long  0. 23.--25.   "  L2CBSIZE ,Cache line size" "32 bytes,64 bytes,res.,res.,res.,res.,res.,res."
bitfld.long  0. 21.--22.   "  L2CREPL  ,Cache default replacement policy" "res.,pseudo-lru,res.,res."
Textline "                    "
bitfld.long  0. 20.        "  L2CLA    ,Cache line locking available" "0,1"
Textline "                    "
bitfld.long  0. 14.--18.   "  L2CNWAY  ,Number of cache ways minus 1" "1 way,2 ways,3 ways,4 ways,5 ways,6 ways,7 ways,8 ways,?..."
bitfld.long  0. 00.--13.   "  L2CSIZE  ,Cache size as a multiple of 64 Kbytes" "64KB,128KB,res.,256KB,?..."
TEXTLINE "              "
group spr:725.++0 "L2ERRDIS,L2 Cache Error Disable Register"
LINE.LONG 0. "L2ERRDIS,L2 Cache Error Disable Register"
bitfld.long  0. 7.             "TMHITDIS ,Tag multi-way hit error disable" "0,1"
bitfld.long  0. 4.           "  TPARDIS ,Tag parity error disable" "0,1"
bitfld.long  0. 3.            "  MBECCDIS ,Data Multiple-bit ECC error disable" "0,1"
Textline "                      "
bitfld.long  0. 2.           "SBECCDIS ,Data ECC error disable" "0,1"
bitfld.long  0. 1.           "  PARDIS  ,Data parity error disable" "0,1"
bitfld.long  0. 0.            "  L2CFGDIS ,L2 Cache config disable" "0,1"
Textline "                    "
group spr:991.++0 "L2ERRDET,L2 Cache Error Detect Register"
LINE.LONG 0. "L2ERRDET,L2 Cache Error Detect Register"
bitfld.long  0. 31.             "MULL2ERR ,Multiple L2 errors" "0,1"
bitfld.long  0. 7.           "  TMHIT    ,Tag multi-way hit detected" "0,1"
bitfld.long  0. 4.            "  TPARERR ,Tag parity error detected" "0,1"
Textline "                      "
bitfld.long  0. 3.           "MBECCERR ,Data Multiple-bit ECC error detected" "0,1"
bitfld.long  0. 2.           "  SBECCERR ,Data ECC error detected" "0,1"
bitfld.long  0. 1.            "  PARERR  ,Data parity error detected" "0,1"
Textline "                    "
group spr:720.++0 "L2ERRINTEN,L2 Cache Error Interrupt Enable Register"
LINE.LONG 0. "L2ERRINTEN,L2 Cache Error Interrupt Enable Register"
bitfld.long  0. 7.             "TMHITINTEN ,Tag multi-way hit interrupt reporting enable" "0,1"
bitfld.long  0. 4.           "  TPARINTEN ,Tag parity error interrupt reporting enable" "0,1"
bitfld.long  0. 3.            "  MBECCINTEN ,Data Multiple-bit ECC error interrupt reporting enable" "0,1"
Textline "                      "
bitfld.long  0. 2.           "SBECCINTEN ,Data ECC error interrupt reporting enable" "0,1"
bitfld.long  0. 1.           "  PARINTEN  ,Data parity error interrupt reporting enable" "0,1"
Textline "                    "
group spr:724.++0 "L2ERRCTL,L2 Cache Error Control Register"
LINE.LONG 0. "L2ERRCTL,L2 Cache Error Control Register"
hexmask.long.byte  0. 16.--23. 1. "L2CTHRESH ,L2 cache threshold"
Textline "                      "
hexmask.long.byte  0. 0.--7. 1.       "L2CCOUNT  ,L2 data ECC single-bit error count"
Textline "                    "
group spr:722.++0 "L2ERRADDR,L2 Cache Error Address Capture Register"
LINE.LONG 0. "L2ERRADDR,L2 Cache Error Address Capture Register"
Textline "                    "
group spr:723.++0 "L2ERREADDR,L2 Cache Error Effective Address Capture Register"
LINE.LONG 0. "L2ERREADDR,L2 Cache Error Effective Address Capture Register"
Textline "                    "
group spr:988.++0 "L2CAPTDATAHI,L2 Cache Error Capture Data Register Higher"
LINE.LONG 0. "L2CAPTDATAHI,L2 Cache Error Capture Data Register Higher"
Textline "                    "
group spr:989.++0 "L2CAPTDATALO,L2 Cache Error Capture Data Register Lower"
LINE.LONG 0. "L2CAPTDATALO,L2 Cache Error Capture Data Register Lower"
Textline "                    "
group spr:990.++0 "L2CAPTECC,L2 Cache Capture ECC Syndrome Register"
LINE.LONG 0. "L2CAPTECC,L2 Cache Capture ECC Syndrome Register"
Textline "                    "
group spr:721.++0 "L2ERRATTR,L2 Cache Error Attribute Register"
LINE.LONG 0. "L2ERRATTR,L2 Cache Error Attribute Register"
bitfld.long  0. 28.--30.      "DWNUM     ,Double-word number of the detected data ECC error" "0,1,2,3,4,5,6,7"
bitfld.long  0. 16.--20.       "      TRANSSRC ,Transaction source for detected error" "External (snoop),res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,Internal (instruction),10001 Internal (data),res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res.,res."
Textline "                      "
bitfld.long  0. 12.--13.       "TRANSTYPE ,Transaction type for detected error" "Snoop,Write,Read,res."
bitfld.long  0. 0.           "  VALINFO  ,L2 capture registers valid" "0,1"
Textline "                    "
group spr:987.++0 "L2ERRINJCTL,L2 Cache Error Injection Control Register"
LINE.LONG 0. "L2ERRINJCTL,L2 Cache Error Injection Control Register"
bitfld.long  0. 16.      "TERRIEN ,L2 tag array error injection" "0,1"
bitfld.long  0. 9.       "  ECCMB     ,ECC/Parity mirror byte enable" "0,1"
Textline "                      "
bitfld.long  0. 8.           "DERRIEN ,L2 data array error injection" "0,1"
hexmask.long.byte  0. 0.--7. 1.    "  ECCERRIM ,Error injection mask for the ECC/parity bits"
Textline "                    "
group spr:985.++0 "L2ERRINJHI,L2 Cache Error Injection Mask Register Higher"
LINE.LONG 0. "L2ERRINJHI,L2 Cache Error Injection Mask Register Higher"
Textline "                    "
group spr:986.++0 "L2ERRINJLO,L2 Cache Error Injection Mask Register Lower"
LINE.LONG 0. "L2ERRINJLO,L2 Cache Error Injection Mask Register Lower"
Textline "                    "
tree.end
Textline "             "