; --------------------------------------------------------------------------------
; @Title: tbd.
; @Props: 
; @Author: -
; @Changelog: 
; @Manufacturer: 
; @Doc: 
; @Core: 
; @Chip: 
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permpc86xxcc.per 6090 2015-03-24 10:27:53Z askoncej $
WIDTH 9. 9.
GROUP spr:0x3f0--0x3f0 "Cache Management Register"
LINE.long 0. "HID0, Hardware Implementation-Dependent Register 0"
BITFLD.long 0. 15. "ICE ,Instruction cache enable" "0,1"
BITFLD.long 0. 14. "  DCE  ,Data cache enable" "0,1"
BITFLD.long 0. 13. "  ILOCK ,Instruction cache LOCK" "0,1"
BITFLD.long 0. 12. "  DLOCK ,Data cache LOCK" "0,1"
BITFLD.long 0. 11. "  ICFI ,Instruction cache flash invalidate" "0,1"
BITFLD.long 0. 10. "   DCFI ,Data cache flash invalidate" "0,1"
TEXTLINE "                  "
BITFLD.long 0. 09. "SPD ,Speculative cache access disable" "0,1"
BITFLD.long 0. 08. "  IFEM ,Enable M bit on bus for instruction fetches" "0,1"
BITFLD.long 0. 07. "  SGE   ,Store gathering enable" "0,1"
BITFLD.long 0. 06. "  DCFA  ,Data cache flash assist" "0,1"
BITFLD.long 0. 05. "  BTIC ,BTIC disable" "0,1"
BITFLD.long 0. 02. "   BHT  ,Branch history table enable" "0,1"
BITFLD.long 0. 00. " NOOPTI ,No-op the data cache touch instructions" "0,1"
GROUP spr:1016.--1016. "LDSTCR Register"
LINE.long 0x00 "LDSTCR, LDSTCR Register"
HEXMASK.LONG 0x00 00.--07. 1. 0. "  DCWL ,Data cache way lock"

GROUP spr:1011.--1011. "Instruction Cache and Interrupt Register"
LINE.long 0x00 "ICTRL,Instruction Cache and Interrupt Register"
BITFLD.long  0x00 31.            "  CIRQ  ,CPU interrupt request" "0,1"
BITFLD.long  0x00 27.            "  EIEC  ,Instruction cache parity error enable" "0,1"
BITFLD.long  0x00 26.            "  EDCE  ,Data cache parity error enable" "0,1"
BITFLD.long  0x00 08.            "  EICP  ,Enable instruction cache parity enable" "0,1"
HEXMASK.LONG 0x00 00.--07. 1. 0. "  ICWL  ,Instruction cache way lock"

GROUP spr:0x3F9--0x3F9 "L2 Cache Control Register"
LINE.long 0x00 "L2CR, L2 Cache Control Register"
BITFLD.long 0x00 31. " L2E   ,L2 enable" "0,1"
BITFLD.long 0x00 30. "  L2PE  ,L2 data parity generation and checking enable" "0,1"
BITFLD.long 0x00 21. "  L2I   ,L2 global invalidate" "0,1"
BITFLD.long 0x00 20. "  L2IO  ,L2 instruction-only mode" "0,1"
BITFLD.long 0x00 16. "  L2DO  ,L2 data-only" "0,1"
BITFLD.long 0x00 12. "  L2REP ,L2 replacement algorithm" "0,1"
BITFLD.long 0x00 11. "  L2HWF ,L2 hardware flush" "0,1"
WIDTH 12. 12.
tree "L2 Error Injection Registers"
group SPR:985.--985.
line.long 0x0 "L2ERRINJHI,L2 Error Injection Mask High Register"
group SPR:986.--986.
line.long 0x0 "L2ERRINJLO,L2 Error Injection Mask Low Register"
TEXTLINE ""
group SPR:987.--987.
line.long 0x0 "L2ERRINJCTL,L2 Error Injection Mask Control Register"
BITFLD.long  0x00 16. "TERRIEN  ,L2 tag array error injection enable" "0,1"
BITFLD.long  0x00 09. "   ECCMB  ,ECC mirror byte enable" "0,1"
BITFLD.long  0x00 09. "  DERRIEN  ,L2 data array error injection enable" "0,1"
hexmask.byte 0x03 00.--07. 1. "  ECCERRIM  ,Error injection mask for the ECC bits" 
TEXTLINE ""
group SPR:988.--988.
line.long 0x0 "L2CAPTDATAHI,L2 Error Capture Data High Register"
group SPR:989.--989.
line.long 0x0 "L2CAPTDATALO,L2 Error Capture Data Low Register"
TEXTLINE ""
group SPR:990.--990.
line.long 0x0 "L2CAPTECC,L2 Error Capture Data Low Register"
hexmask.byte 0x00 00.--07. 1. "ECCSYND  ,The calculated ECC syndrome of the failing double word (read only)"
hexmask.byte 0x03 00.--07. 1. "  ECCCHKSUM  ,The datapath ECC of the failing double word (read only)"
TEXTLINE ""
group SPR:991.--991.
line.long 0x0 "L2ERRDET,L2 Error Detect Register"
BITFLD.long  0x00 31. "MULL2ER  ,Multiple L2 errors" "0,1"
BITFLD.long  0x00 04. "   TPARERR    ,Tag parity error" "0,1"
BITFLD.long  0x00 03. "  MBECCERR    ,Multiple-bit ECC error" "0,1"
BITFLD.long  0x00 02. "  SBECCERR    ,Single-bit ECC error" "0,1"
group SPR:992.--992.
line.long 0x0 "L2ERRDIS,L2 Error Disable Register"
BITFLD.long  0x00 04. "             TPARDIS    ,Tag parity error" "0,1"
BITFLD.long  0x00 03. "  MBECCDIS    ,Multiple-bit ECC error" "0,1"
BITFLD.long  0x00 02. "  SBECCDIS    ,Single-bit ECC error" "0,1"
group SPR:993.--993.
line.long 0x0 "L2ERRINTEN,L2 Error Interrupt Register"
BITFLD.long  0x00 04. "             TPARINTEN  ,Tag parity error" "0,1"
BITFLD.long  0x00 03. "  MBECCINTEN  ,Multiple-bit ECC error" "0,1"
BITFLD.long  0x00 02. "  SBECCINTEN  ,Single-bit ECC error" "0,1"
TEXTLINE ""
group SPR:994.--994.
line.long 0x0 "L2ERRATTR,L2 Error Attributes Capture Register"
BITFLD.long 0x00 28.--29. "DWNUM    ,Double-word number of the detected error" "0,1,2,3"
BITFLD.long 0x00 23.--26. "   TRANSSIZ  ,Transaction size for detected error" "8 bytes,res.,1 byte,16 bytes,2 bytes,32 bytes,3 bytes,res.,4 bytes,res.,5 bytes,res.,6 bytes,res.,7 bytes,res."
BITFLD.long  0x00 23. "           BURST       ,Burst transaction for detected error" "0,1"
TEXTLINE "                   "
BITFLD.long  0x00 20. "  TRSRC    ,Transaction source for detected error" "ext,proc "
BITFLD.long  0x00 16. ",Transaction source for detected error" "instr,data"
BITFLD.long  0x00 12.--13. "        TRTYPE  ,Transaction type for detected error" "snoop,write,read,res."
BITFLD.long  0x00 0. "  VALINFO     ,L2 capture registers valid" "0,1"
TEXTLINE ""
group SPR:995.--995.
line.long 0x0 "L2ERRADDR,L2 Error Address Error Capture Register"
group SPR:996.--996.
line.long 0x0 "L2ERREADDR,L2 Error Extended Address Error Capture Register"
TEXTLINE ""
group SPR:997.--997.
line.long 0x0 "L2ERRCTL,L2 Error Control Register"
hexmask.byte 0x01 00.--07. 1. "L2CTHRESH  ,L2 cache threshold"
hexmask.byte 0x02 00.--07. 1. "  L2CCOUNT  ,L2 count"
tree.end
WIDTH 9. 9.
TEXTLINE ""

TEXTLINE ""