; --------------------------------------------------------------------------------
; @Title: Peripherals PPC7451
; @Props: 
; @Author: -
; @Changelog: 
; @Manufacturer: 
; @Doc: 
; @Core: 
; @Chiplist: MPC7400, MPC7410, MPC7441, MPC7445, MPC7447, MPC7447A, MPC7448, 
;   MPC7450, MPC7451, MPC7455, MPC7457, MPC74XX
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permpc74xx.per 7991 2017-06-29 15:55:30Z rweiss $
config 16. 8.
width 9. 9.
munging.le
base d:iobase()
tree "Configuration Registers"
GROUP spr:0x11F--0x11F "Processor Version Register"
LINE.LONG 0x00 "PVR ,Processor Version Register"
HEXMASK.WORD 0x00 00.--15. 1. 0. "VER ,Version"
HEXMASK.WORD 0x02 00.--15. 1. 0. "  REV ,Revision"
GROUP spr:0x3FF--0x3FF "Processor ID Register"
LINE.LONG 0x00 "PIR ,The Processor ID register is used to differentiate between processors in a multiprocessor system."
sif ((CPU()=="MPC7400")||(CPU()=="MPC7410"))
GROUP spr:0x3f0--0x3f0 "HID0-Register"
LINE.LONG 0x00 "HID0 , Hardware Implementation Register"
TEXTLINE "EMCP  EBA  EBD  BCLK ECLK PAR  DOZE NAP  SLEEP DPM  RISEG NHR"
TEXTLINE " "
BITFLD.long 0x00 31. ", EMCP: Enable machine check pin" "0,1"
BITFLD.long 0x00 29. "    ,EBA: Enable bus address parity checking" "0,1"
BITFLD.long 0x00 28. "    ,EBD: Enable bus data parity checking" "0,1"
BITFLD.long 0x00 27. "    ,BCLK: Select bus clock for test clock pin" "0,1"
BITFLD.long 0x00 25. "    ,ECLK: Enable external test clock pin" "0,1"
BITFLD.long 0x00 24. "    ,PAR: Disable precharge of  !ARTRY  and shared signals" "0,1"
BITFLD.long 0x00 23. "    ,DOZE: Doze mode; PLL, time base, and snooping active" "0,1"
BITFLD.long 0x00 22. "    ,NAP: Nap mode; PLL and time base active" "0,1"
BITFLD.long 0x00 21. "    ,SLEEP: Sleep mode; no external clock required" "0,1"
BITFLD.long 0x00 20. "     ,DPM: Enable dynamic power management" "0,1"
BITFLD.long 0x00 19. "    ,RISEG: Read ISEG (by mfsr)" "0,1"
BITFLD.long 0x00 16. "     , NHR: Not hard reset (software use only)", "0,1"
TEXTLINE ""
TEXTLINE "ICE  DCE ILOCK DLOCK ICFI DCFI SPD IFTT SGE DCFA BTIC FBIOB BHT NOPDST NOPTI"
TEXTLINE " "
BITFLD.long 0x00 15. ",ICE: Instruction cache enable" "0,1"
BITFLD.long 0x00 14. "   ,DCE: Data cache enable" "0,1"
BITFLD.long 0x00 13. "   ,ILOCK: Instruction cache LOCK" "0,1"
BITFLD.long 0x00 12. "     ,DLOCK: Data cache LOCK" "0,1"
BITFLD.long 0x00 11. "     ,ICFI: Instruction cache flash invalidate" "0,1"
BITFLD.long 0x00 10. "    ,DCFI: Data cache flash invalidate" "0,1"
BITFLD.long 0x00 09. "    ,SPD: Speculative cache access disable" "0,1"
BITFLD.long 0x00 08. "   ,IFTT: I-Fetch TTx encoding differentiation" "0,1"
BITFLD.long 0x00 07. "    ,SGE: Store gathering enable" "0,1"
BITFLD.long 0x00 06. "   ,DCFA: Data cache flash assist" "0,1"
BITFLD.long 0x00 05. "    ,Branch target instruction cache enable" "0,1"
BITFLD.long 0x00 04. "    , Force branch inirect on bus" "0,1"
BITFLD.long 0x00 02. "     ,BHT: Branch history table enable" "0,1"
BITFLD.long 0x00 01. "   ,NOPDST: No-op dst, dstt, dstst, and dststt instructions" "0,1"
BITFLD.long 0x00  0. "      ,NOPTI: No-op the data cache touch instructions" "0,1"
endif
sif ((CPU()=="MPC7450")||(CPU()=="MPC7451")||(CPU()=="MPC7441"))
GROUP spr:0x3f0--0x3f0 "HID0-Register"
LINE.LONG 0x00 "HID0, Hardware Implementation Register"
BITFLD.long 0x00 25. " TBEN   ,TBEN: Time base enable" "0,1"
BITFLD.long 0x00 23. "  STEN   ,STEN: Software table search enable" "0,1"
BITFLD.long 0x00 22. "  NAP    ,NAP: Nap mode; PLL and time base active" "0,1"
BITFLD.long 0x00 21. "  SLEEP  ,SLEEP: Sleep mode; no external clock required" "0,1"
BITFLD.long 0x00 20. "  DPM    ,DPM: Enable dynamic power management" "0,1"
BITFLD.long 0x00 19. "  RISEG  ,RISEG: Read ISEG (by mfsr)" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 18. "  BHTCLR ,Clear branch history table" "0,1"
BITFLD.long 0x00 17. "  XAEN   ,Extended addressing enabled" "0,1"
BITFLD.long 0x00 16. "  NHR    , NHR: Not hard reset (software use only)", "0,1"
BITFLD.long 0x00 15. "  ICE    ,ICE: Instruction cache enable" "0,1"
BITFLD.long 0x00 14. "  DCE    ,DCE: Data cache enable" "0,1"
BITFLD.long 0x00 13. "  ILOCK  ,ILOCK: Instruction cache LOCK" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 12. "  DLOCK  ,DLOCK: Data cache LOCK" "0,1"
BITFLD.long 0x00 11. "  ICFI   ,ICFI: Instruction cache flash invalidate" "0,1"
BITFLD.long 0x00 10. "  DCFI   ,DCFI: Data cache flash invalidate" "0,1"
BITFLD.long 0x00 09. "  SPD    ,SPD: Speculative cache access disable" "0,1"
BITFLD.long 0x00 07. "  SGE    ,SGE: Store gathering enable" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 05. "  BTIC   ,Branch target instruction cache enable" "0,1"
BITFLD.long 0x00 04. "  LRSTK  ,LRSTK: Link register stack enable" "0,1"
BITFLD.long 0x00 03. "  FOLD   ,FOLD: Branch folding enable" "0,1"
BITFLD.long 0x00 02. "  BHT    ,BHT: Branch history table enable" "0,1"
BITFLD.long 0x00 01. "  NOPDST ,NOPDST: No-op dst, dstt, dstst, and dststt instructions" "0,1"
BITFLD.long 0x00 00. "  NOPTI  ,NOPTI: No-op the data cache touch instructions" "0,1"
endif
sif ((CPU()=="MPC7455")||(CPU()=="MPC7445")||(CPU()=="MPC7457")||(CPU()=="MPC7447")||(CPU()=="MPC7447A")||(CPU()=="MPC7448"))
GROUP spr:0x3f0--0x3f0 "HID0-Register"
LINE.LONG 0x00 "HID0, Hardware Implementation Register"
BITFLD.long 0x00 26. " TBEN   ,TBEN: Time base enable" "0,1"
BITFLD.long 0x00 24. "  STEN   ,STEN: Software table search enable" "0,1"
BITFLD.long 0x00 23. "  HBATEN ,HIGH_BAT_EN: Additional BATs enabled" "0,1"
BITFLD.long 0x00 22. "  NAP    ,NAP: Nap mode; PLL and time base active" "0,1"
BITFLD.long 0x00 21. "  SLEEP  ,SLEEP: Sleep mode; no external clock required" "0,1"
BITFLD.long 0x00 20. "  DPM    ,DPM: Enable dynamic power management" "0,1"
BITFLD.long 0x00 19. "  RISEG  ,RISEG: Read ISEG (by mfsr)" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 18. "  BHTCLR ,Clear branch history table" "0,1"
BITFLD.long 0x00 17. "  XAEN   ,Extended addressing enabled" "0,1"
BITFLD.long 0x00 16. "  NHR    , NHR: Not hard reset (software use only)", "0,1"
BITFLD.long 0x00 15. "  ICE    ,ICE: Instruction cache enable" "0,1"
BITFLD.long 0x00 14. "  DCE    ,DCE: Data cache enable" "0,1"
BITFLD.long 0x00 13. "  ILOCK  ,ILOCK: Instruction cache LOCK" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 12. "  DLOCK  ,DLOCK: Data cache LOCK" "0,1"
BITFLD.long 0x00 11. "  ICFI   ,ICFI: Instruction cache flash invalidate" "0,1"
BITFLD.long 0x00 10. "  DCFI   ,DCFI: Data cache flash invalidate" "0,1"
BITFLD.long 0x00 09. "  SPD    ,SPD: Speculative cache access disable" "0,1"
BITFLD.long 0x00 08. "  XBSEN  ,XBSEN: Extended BAT block size enable" "0,1"
BITFLD.long 0x00 07. "  SGE    ,SGE: Store gathering enable" "0,1"
TEXTLINE "                 "
BITFLD.long 0x00 05. "  BTIC   ,BTIC: Branch target instruction cache enable" "0,1"
BITFLD.long 0x00 04. "  LRSTK  ,LRSTK: Link register stack enable" "0,1"
BITFLD.long 0x00 03. "  FOLD   ,FOLD: Branch folding enable" "0,1"
BITFLD.long 0x00 02. "  BHT    ,BHT: Branch history table enable" "0,1"
BITFLD.long 0x00 01. "  NOPDST ,NOPDST: No-op dst, dstt, dstst, and dststt instructions" "0,1"
BITFLD.long 0x00 00. "  NOPTI  ,NOPTI: No-op the data cache touch instructions" "0,1"
endif
;sif ((CPU()=="MPC7400")||(CPU()=="MPC7410"))
;  %include ph/HID1.ph
;endif
sif ((CPU()=="MPC7450")||(CPU()=="MPC7451")||(CPU()=="MPC7441")||(CPU()=="MPC7455")||(CPU()=="MPC7445")||(CPU()=="MPC7457")||(CPU()=="MPC7447"))
GROUP spr:0x3f1--0x3f1 "HID1-Register"
LINE.long 0x00 "HID1, Hardware Implementation Register"
BITFLD.long 0x00 31. " EMCP   , Machine check signal enable" "0,1"
BITFLD.long 0x00 29. " EBA    , Enable 60X/MPX bus address bus parity checking" "0,1"
BITFLD.long 0x00 28. " EBD    , Enable 60X/MPX bus data bus parity checking" "0,1"
BITFLD.long 0x00 27. " BCLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 25. " ECLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 24. " PAR    , Disable precharge for !ARTRY, !SHD0, and !SHD1 pins" "0,1"
TEXTLINE "                  "
BITFLD.long 0x00 16. " PC0    , PLL configuration bit0 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 15. " PC1    , PLL configuration bit1 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 14. " PC2    , PLL configuration bit2 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 13. " PC3    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 12. " PC4    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 11. " SYNCBE , Address broadcast enable for sync, eieio" "0,1"
BITFLD.long 0x00 10. " ABE    , Address broadcast enable for dcbf, dcbst, dcbi, icbi, tlbie, and tlbsync" "0,1"
TEXTLINE "                   Note: PC* not accessible via JTAG"
endif
sif (CPU()=="MPC7447A")
GROUP spr:0x3f1--0x3f1 "HID1-Register"
LINE.long 0x00 "HID1, Hardware Implementation Register"
BITFLD.long 0x00 31. " EMCP   , Machine check signal enable" "0,1"
BITFLD.long 0x00 29. " EBA    , Enable 60X/MPX bus address bus parity checking" "0,1"
BITFLD.long 0x00 28. " EBD    , Enable 60X/MPX bus data bus parity checking" "0,1"
BITFLD.long 0x00 27. " BCLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 25. " ECLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 24. " PAR    , Disable precharge for !ARTRY, !SHD0, and !SHD1 pins" "0,1"
BITFLD.long 0x00 22. " DFS2   , Dynamic frequency switching - div-by-two mode" "0,1"
TEXTLINE "                  "
BITFLD.long 0x00 16. " PC0    , PLL configuration bit0 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 15. " PC1    , PLL configuration bit1 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 14. " PC2    , PLL configuration bit2 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 13. " PC3    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 12. " PC4    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 11. " SYNCBE , Address broadcast enable for sync, eieio" "0,1"
BITFLD.long 0x00 10. " ABE    , Address broadcast enable for dcbf, dcbst, dcbi, icbi, tlbie, and tlbsync" "0,1"
TEXTLINE "                   Note: PC* not accessible via JTAG"
endif
sif (CPU()=="MPC7448")
GROUP spr:0x3f1--0x3f1 "HID1-Register"
LINE.long 0x00 "HID1, Hardware Implementation Register"
BITFLD.long 0x00 31. " EMCP   , Machine check signal enable" "0,1"
BITFLD.long 0x00 29. " EBA    , Enable 60X/MPX bus address bus parity checking" "0,1"
BITFLD.long 0x00 28. " EBD    , Enable 60X/MPX bus data bus parity checking" "0,1"
BITFLD.long 0x00 27. " BCLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 25. " ECLK   , CLK_OUT output enable and clock type selection" "0,1"
BITFLD.long 0x00 24. " PAR    , Disable precharge for !ARTRY, !SHD0, and !SHD1 pins" "0,1"
BITFLD.long 0x00 23. " DFS4   , Dynamic frequency switching - div-by-four mode" "0,1"
BITFLD.long 0x00 22. " DFS2   , Dynamic frequency switching - div-by-two mode" "0,1"
TEXTLINE "                  "
BITFLD.long 0x00 17. " PC5    , PLL configuration bit5 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 16. " PC0    , PLL configuration bit0 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 15. " PC1    , PLL configuration bit1 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 14. " PC2    , PLL configuration bit2 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 13. " PC3    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 12. " PC4    , PLL configuration bit3 (not accessible through the debugger)" "0,1"
BITFLD.long 0x00 11. " SYNCBE , Address broadcast enable for sync, eieio" "0,1"
BITFLD.long 0x00 10. " ABE    , Address broadcast enable for dcbf, dcbst, dcbi, icbi, tlbie, and tlbsync" "0,1"
TEXTLINE "                   Note: PC* not accessible via JTAG"
endif
tree.end
tree "Exception Handling Registers"
GROUP spr:0x013--0x013 "Data Addres Register"
LINE.LONG 0x00 "DAR ,Data Addres Register" 
GROUP spr:0x012--0x012 "DSISR Register"
LINE.LONG  0x00 "DSISR , Data Storage Interrupt Status Register"
GROUP spr:0x01A--0x01B "SRR Register"
LINE.LONG  0x00 "SRR0 , SRR0 holds EA for resuming program execution"
LINE.LONG  0x04 "SRR1 , SRR1 Exception-specific information and MSR bit values"
TEXTLINE "         SRR1 Machine Check Interrupt flags:"
TEXTLINE "                 "
BITFLD.LONG 0x04 30.   "SRR1[1]  L1ICERR            ,L1 instruction cache error (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 29. "  SRR1[2]  L1DCERR            ,L1 data cache error (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 20. "  SRR1[11] MSSERR             ,MSS error. Set for an L2 cache tag parity or L2 data parity error (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 19. "  SRR1[12] MCP                ,Set when /mcp signal is asserted (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 13. "  SRR1[13] TEA                ,Set when /tea signal is asserted (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 12. "  SRR1[14] DP                 ,Set when a data bus parity error is detected on the MPX bus (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 11. "  SRR1[15] AP                 ,Set when a address bus parity error is detected on the MPX bus (e600 specific flag)" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 01. "  SRR1[30] RI                 ,Set in case of a recoverable interrupt" "0,1"
TEXTLINE "         SRR1 ISI Interrupt flags:"
TEXTLINE "                 "
BITFLD.LONG 0x04 30.   "SRR1[1]  PAGE_FAULT         ,translation neither found in HTEG nor IBAT" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 29. "  SRR1[2]  DSTORE/NX/G_ACC_IR ,access to a direct-store segment,no-execute segment or to guarded memory when MSR[IR] = 1" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 27. "  SRR1[4]  ACCESS_NOT_PERM    ,access not permitted by the page or IBAT protection" "0,1"
TEXTLINE "         SRR1 External Interrupt flags:"
TEXTLINE "                 "
BITFLD.LONG 0x04 30.   "SRR1[1]  CIRQ               ,Set when an external interrupt is caused by the ICTRL[CIRQ] bit (e600 specific flag)" "0,1"
TEXTLINE "                 "
BITFLD.LONG 0x04 21.   "SRR1[10]  INT               ,Set when an external interrupt is caused by /int assertion (e600 specific flag)" "0,1"
TEXTLINE "         SRR1 Program Interrupt flags:"
TEXTLINE "                 "
BITFLD.LONG 0x04 20.   "SRR1[11] FPENA              ,Set for an IEEE floating-point enabled program exception" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 19. "  SRR1[12] ILLINST            ,Set for an illegal instruction program exception" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 18. "  SRR1[13] PRIVINST           ,Set for a privileged instruction program exception" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 17. "  SRR1[14] TRAP               ,Set for a trap program exception" "0,1"
TEXTLINE "               "
BITFLD.LONG 0x04 16. "  SRR1[15] SUBS               ,Set if SRR0 contains the address of a subsequent instruction - Cleared if SRR0 contains the address of the instruction causing the exception" "0,1"
sif ((CPU()=="MPC7400")||(CPU()=="MPC7410")||(CPU()=="MPC7450")||(CPU()=="MPC7451")||(CPU()=="MPC7441"))
GROUP spr:0x110--0x113 "SPRG Register"
LINE.LONG  0x00 "SPRG0 , SPRG0 Memory address reseved for use by the first-level exception handler"
LINE.LONG  0x04 "SPRG1 , SPRG1 Scratch register for a GPR register. Used by the first-level exception handler"
LINE.LONG  0x08 "SPRG2 , SPRG2 Register"
LINE.LONG  0x0C "SPRG3 , SPRG3 Register"
endif
sif ((CPU()=="MPC7455")||(CPU()=="MPC7445")||(CPU()=="MPC7457")||(CPU()=="MPC7447")||(CPU()=="MPC7447A")||(CPU()=="MPC7448"))
GROUP spr:0x110--0x117 "SPRG Register"
LINE.LONG 0x00 "SPRG0 , SPRG0 Memory address reseved for use by the first-level exception handler"
LINE.LONG 0x04 "SPRG1 , SPRG1 Scratch register for a GPR register. Used by the first-level exception handler"
LINE.LONG 0x08 "SPRG2 , SPRG2 Register"
LINE.LONG 0x0C "SPRG3 , SPRG3 Register"
LINE.LONG 0x10 "SPRG4 , SPRG4 Register"
LINE.LONG 0x14 "SPRG5 , SPRG5 Register"
LINE.LONG 0x18 "SPRG6 , SPRG6 Register"
LINE.LONG 0x1C "SPRG7 , SPRG7 Register"
endif
tree.end
tree "Performance Monitor Registers"
GROUP spr:0x3B8--0x3B8 "Monitor Control Registers"
LINE.LONG 0x00 "MMCR0 ,Monitor Mode Control Register 0"
BITFLD.LONG 0x00 31. "FC     ,Freeze counters" "0,1"
BITFLD.LONG 0x00 30. "   FCS    ,Freeze counters in supervisor mode" "0,1"
BITFLD.LONG 0x00 29. "        FCP     ,Freeze counters in user mode" "0,1"
BITFLD.LONG 0x00 28. "  FCM1      ,Disables counting while MSR[PMM] is 1" "0,1"
BITFLD.LONG 0x00 27. "         FCM0 ,Disables counting while MSR[PMM] is 0" "0,1"
BITFLD.LONG 0x00 26. "      PMXE ,Performance monitor exception enable" "0,1"
TEXTLINE "         "
BITFLD.LONG 0x00 25. "         FCECE  ,Freeze counters on enabled condition or event" "0,1"
BITFLD.LONG 0x00 23.--24. "   TBSEL  ,Time Base Bit Selector" "TBL[31],TBL[23],TBL[19],TBL[15]"
BITFLD.LONG 0x00 22. "  TBEE    ,Time base event enable" "0,1"
HEXMASK.LONG 0x00 16.--21. 1. 0. "  THRESHOLD ,Threshold value"
TEXTLINE "         "
BITFLD.LONG 0x00 15. "         PMC1CE ,PMC1 condition enable. Controls whether counter negative conditions due to a negative value in PMC1 are enabled." "0,1"
BITFLD.LONG 0x00 14. "   PMCjCE ,PMCj condition enable. Controls whether counter negative conditions due to a negative value in any PMC2-4 are enabled." "0,1"
BITFLD.LONG 0x00 13. "        TRIGGER ,Can be used to trigger counting of PMC2-PMC4 after PMC1 has overflowed or after a performance monitor interrupt is signaled" "0,1"
TEXTLINE "        "
HEXMASK.LONG 0x00 6.--12. 1. 0. "          PMC1SELECT ,PMC1 input selector"
HEXMASK.LONG 0x00 0.--5. 1. 0.  "        PMC2SELECT ,PMC2 input selector"
TEXTLINE "            "
GROUP spr:0x3BC--0x3BC
LINE.LONG 0x00 "MMCR1 ,Monitor Mode Control Register 1"
HEXMASK.LONG 0x00 27.--31. 1. 0. "PMC3SELECT ,PMC3 input selector"
HEXMASK.LONG 0x00 22.--26. 1. 0. "        PMC4SELECT ,PMC4 input selector"
GROUP spr:0x3B0--0x3B0
LINE.LONG 0x00 "MMCR2 ,Monitor Mode Control Register 2"
BITFLD.LONG 0x00 31. "THRESHMULT ,PMC1 condition enable. Threshold multiplier Used to extend the range of the THRESHOLD field, MMCR0[10-15]." "x2,x32"
BITFLD.LONG 0x00 30. "             SMCNTEN    ,SMCNTEN is used to mask the request from a peripheral performance monitor." "0,1"
BITFLD.LONG 0x00 29. "         SMINTEN ,SMINTEN is used to mask the performance monitor exception request from a peripheral performance monitor." "0,1"

sif ((CPU()=="MPC7400")||(CPU()=="MPC7410"))
GROUP spr:0x3B9--0x3B9 "Performance Counters"
LINE.LONG 0x00 "PMC1 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BA--0x3BA
LINE.LONG 0x00 "PMC2 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BD--0x3BD
LINE.LONG 0x00 "PMC3 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BE--0x3BE
LINE.LONG 0x00 "PMC4 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
endif
sif ((CPU()!="MPC7400")&&(CPU()!="MPC7410"))
GROUP spr:0x3B9--0x3B9 "Performance Counters"
LINE.LONG 0x00 "PMC1 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BA--0x3BA
LINE.LONG 0x00 "PMC2 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BD--0x3BD
LINE.LONG 0x00 "PMC3 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3BE--0x3BE
LINE.LONG 0x00 "PMC4 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3B1--0x3B1
LINE.LONG 0x00 "PMC5 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
GROUP spr:0x3B2--0x3B2
LINE.LONG 0x00 "PMC6 ,Performance Counter Register"
BITFLD.LONG 0x00 31. "OV ,Overflow" "0,1"
HEXMASK.LONG 0x00 0.--30. 1. 0. "  Counter-Value , Counter-Value"
endif
GROUP spr:0x3BB--0x3BB "Sampled Instruction Address Register"
LINE.LONG 0x00 "SIA ,The SIA holds the EA of an instruction executing at or around the time the processor signals the performance monitor interrupt condition."

GROUP spr:0x3B7--0x3B7 "Breakpoint Address Mask Register"
LINE.LONG 0x00 "BAMR, Breakpoint Address Mask Register"

tree.end
tree "Power/Thermal Management Registers"
sif ((CPU()=="MPC7400")||(CPU()=="MPC7410"))
GROUP spr:0x3FC--0x3FC
LINE.LONG 0x00 "THRM1 ,Thermal Management Register 1"
BITFLD.LONG 0x00 31. "TIN ,Thermal management interrupt bit (READ ONLY)" "0,1"
BITFLD.LONG 0x00 30. "  TIV ,Thermal management interrupt valid" "0,1"
HEXMASK.LONG 0x00 23.--29. 1. 0. "  THRESHOLD ,Threshold that the thermal sensor output is compared to"
BITFLD.LONG 0x00 0. "  TID ,Thermal management interrupt direction bit" "0,1"
BITFLD.LONG 0x00 0. "  TIE ,Thermal management interrupt enable" "0,1"
BITFLD.LONG 0x00 0. "  V ,SPR valid bit" "0,1"
GROUP spr:0x3FD--0x3FD
LINE.LONG 0x00 "THRM2 ,Thermal Management Register 2"
BITFLD.LONG 0x00 31. "TIN ,Thermal management interrupt bit (READ ONLY)" "0,1"
BITFLD.LONG 0x00 30. "  TIV ,Thermal management interrupt valid" "0,1"
HEXMASK.LONG 0x00 23.--29. 1. 0. "  THRESHOLD ,Threshold that the thermal sensor output is compared to"
BITFLD.LONG 0x00 0. "  TID ,Thermal management interrupt direction bit" "0,1"
BITFLD.LONG 0x00 0. "  TIE ,Thermal management interrupt enable" "0,1"
BITFLD.LONG 0x00 0. "  V ,SPR valid bit" "0,1"
GROUP spr:0x3FE--0x3FE
LINE.LONG 0x00 "THRM3 ,Thermal Management Register 3"
HEXMASK.LONG 0x00 1.--13. 1. 0. "SITV ,Sample interval timer value"
BITFLD.LONG 0x00 0. "  E ,Enables the thermal sensor compare operation if either THRM1[V] or THRM2[v] is set" "0,1"
TEXTLINE ""
endif
GROUP spr:0x3FB--0x3FB "Instruction Cache Throttling Control Register"
LINE.LONG 0x00 "ICTC ,Instruction Cache Throttling Control Register"
HEXMASK.LONG 0x00 1.--8. 1. 0. "FI ,Instruction forwarding interval expressed in processor clocks"
BITFLD.LONG 0x00 0. "    E ,Enable instruction throttling" "0,1"
tree.end
tree "Memory Subsystem Registers"
sif ((CPU()=="MPC7400")||(CPU()=="MPC7410"))
GROUP spr:1014.--1014. "Memory Subsystem Control Register"
LINE.long 0x00 "MSSCR0, Memory Subsystem Control Register"
BITFLD.long 0x00 31. "SHDEN   ,Shared-state enable" "0,1"
BITFLD.long 0x00 30. "  SHDPEN3  ,L2 data parity generation and checking enable" "0,1"
HEXMASK.long.byte 0x00 27.--29. 1. 0. "  L1_INTVEN , L1 data cache !HIT intervention enable"
HEXMASK.long.byte 0x00 24.--26. 1. 0. "  L2_INTVEN , L2 data cache !HIT intervention enable"
TEXTLINE "                "
BITFLD.long 0x00 23. "  DL1HWF  ,L1 data cache hardware flush" "0,1"
BITFLD.long 0x00 21. "  EMODE    ,MPX bus mode (read-only)" "0,1"
BITFLD.long 0x00 20. "  ABD       ,Address bus driven (read-only)" "0,1"
endif
sif ((CPU()=="MPC7400"))
GROUP spr:1015.--1015. "Memory Subsystem Debug Register"
LINE.long 0x00 "MSSCR1, Memory Subsystem Debug Register"
TEXTLINE "       "
endif
sif ((CPU()!="MPC7400")&&(CPU()!="MPC7410"))
GROUP spr:1014.--1014. "Memory Subsystem Control Register"
LINE.long 0x00 "MSSCR0,Memory Subsystem Control Register"
BITFLD.long  0x00 26.--28.       " DTQ    ,Maximum number of outstandind bus transactions the MPC7451 can support" "8,16,2,3,4,5,6,7"
BITFLD.long  0x00 24.            "    EIDIS  ,Disable external intervention in MPX bus mode" "0,1"
BITFLD.long  0x00 19.            "  L3TCEN ,L3 turnaround clock enable" "0,1"
BITFLD.long  0x00 17.--18.       "  L3TC  ,L3 turnaround clock count" "2 L2CKn,3 L2CKn,4 L2CKn,5 L2CKn"
TEXTLINE "                 "
BITFLD.long  0x00 14.--15.       "  BMODE  ,Bus mode (BMODE bits are not accessable for the debugger)" "60x,res.,MPX,res."
BITFLD.long  0x00 05.            "  ID     ,Processor identification" "0,1"
BITFLD.long  0x00 00.--01.       "  L2PFE  ,L2 prefetching enabled" "dis.,1,2,3"
TEXTLINE "                   Note: BMODE not accessible via JTAG"

GROUP spr:1015.--1015. "Memory Subsystem Status Register"
LINE.long 0x00 "MSSSR0, Memory Subsystem Status Register"
BITFLD.long 0x00 18.             "   L2TAG  ,L2 tag parity error" "0,1"
BITFLD.long 0x00 17.             "   L2DAT  ,L2 data parity error" "0,1"
BITFLD.long 0x00 16.             "   L3TAG  ,L3 tag parity error" "0,1"
BITFLD.long 0x00 15.             "   L3DAT  ,L3 data parity error" "0,1"
TEXTLINE "                  "
BITFLD.long 0x00 14.             "   APE    ,Address bus parity error" "0,1"
BITFLD.long 0x00 13.             "   DPE    ,Data bus parity error" "0,1"
BITFLD.long 0x00 12.             "   TEA    ,Bus transfer error acknoledge" "0,1"
endif
tree.end
tree "External Access Register"
GROUP spr:0x11A--0x11A "External Access Register"
LINE.LONG 0x00 "EAR ,External Access Register"
BITFLD.LONG 0x00 31. "E ,Enable bit" "0,1"
HEXMASK.LONG 0x00 0.--5. 1. 0. "  RID ,Resource ID"
tree.end
tree "Breakpoint Registers"
GROUP spr:3f2--3f2 "Instruction Address Breakpoint Register (used by debugger)"
LINE.long 0x00 "IABR"
HEXMASK.long 0x00 2.--31. 0x4 0. "CEA , Word address to be compared"
BITFLD.long 0x00 1. " BE  , Breakpoint enable" "0,1"
BITFLD.long 0x00 0. " TE  , Translation enable" "0,1"
GROUP spr:3F5--3F5 "Data Address Breakpoint Register (used by debugger)"
LINE.long 0x00 "DABR"
HEXMASK.long 0x00 3.--31. 0x8 0. "DAB , Data address breakpoint"
BITFLD.long 0x00 2. " BT  , Breakpoint translation enable" "0,1"
BITFLD.long 0x00 1. " DW  , Data write enable" "0,1"
BITFLD.long 0x00 0. " DR  , Data read enable" "0,1"
tree.end
TEXTLINE ""