; -------------------------------------------------------------------------------- ; @Title: MPC5200 On-Chip Peripherals ; @Props: Released ; @Author: KAM ; @Changelog: 2006-01-03 KAM ; @Manufacturer: NXP ; @Doc: MPC5200B_UG.pdf; MPC5200UM_rev3.0.pdf; MPC5200UM_rev0.8.pdf ; MPC5200UM_rev0.4.pdf ; @Core: 603e, G2_LE ; @Chip: MPC5200 ; @Chiplist: MPC5200 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permpc5200.per 7231 2016-09-07 16:44:50Z kjmal $ config 16. 8. width 0xb ;Default MBAR Address base anc:iobase() tree "Core Specific Registers" width 8. tree "Version Registers" RGROUP spr:0x11F--0x11F "Processor Version Register" LINE.LONG 0. "PVR ,Processor Version Register" HEXMASK.LONG.WORD 0. 16.--31. 1. 0. " VER ,Version" HEXMASK.LONG.WORD 0. 00.--15. 1. 0. " REV ,Revision" RGROUP spr:0200++3 "JTAG ID Number" LINE.LONG 0. "JTAGID,CDM Register 0x00 = JTAG ID Number (JTAGID): 01C5301D hex (read only)" tree.end tree "Time Base Registers" group SPR:284.++0 line.long 0x00 "TBL,Time Base Low Register" group SPR:285.++0 line.long 0x00 "TBU,Time Base High Register" TEXTLINE "" group SPR:22.++0 line.long 0x00 "DEC,Decrementer Register" tree.end tree "Hardware Implementation Registers" GROUP spr:0x3f0--0x3f0 "HID0-Register" LINE.LONG 0. "HID0 , Hardware Implementation Register 0" BITFLD.long 0. 31. " EMCP ,Enable machine check pin" "0,1" BITFLD.long 0. 29. " EBA ,Enable bus address parity checking" "0,1" BITFLD.long 0. 28. " EBD ,Enable bus data parity checking" "0,1" BITFLD.long 0. 27. " SBCLK ,Select Bus Clock for test clock pin" "0,1" textline " " BITFLD.long 0. 25. " ECLK ,enable external test clock pin" "0,1" BITFLD.long 0. 24. " PAR ,Disable precharge of !ARTRY and shared signals" "0,1" BITFLD.long 0. 23. " DOZE ,Doze mode; PLL, time base, and snooping active" "0,1" BITFLD.long 0. 22. " NAP ,Nap mode; PLL and time base active" "0,1" textline " " BITFLD.long 0. 21. " SLEEP ,Sleep mode; no external clock required" "0,1" BITFLD.long 0. 20. " DPM ,Enable dynamic power management" "0,1" BITFLD.long 0. 19. " ERISEG ,Read I SEG (For test only)" "0,1" BITFLD.long 0. 16. " NHR ,Not hard reset" "0,1" textline " " BITFLD.long 0. 15. " ICE ,Instruction cache enable" "0,1" BITFLD.long 0. 14. " DCE ,Data cache enable" "0,1" BITFLD.long 0. 13. " ILOCK ,Instruction cache LOCK" "0,1" BITFLD.long 0. 12. " DLOCK ,Data cache LOCK" "0,1" textline " " BITFLD.long 0. 11. " ICFI ,Instruction cache flash invalidate" "0,1" BITFLD.long 0. 10. " DCFI ,Data cache flash invalidate" "0,1" BITFLD.long 0. 7. " IFEM ,Instruction fetch enable M" "0,1" BITFLD.long 0. 4. " FBIOB ,Force branch inirect on bus" "0,1" textline " " BITFLD.long 0. 3. " ABE ,Address broadcast enable" "0,1" BITFLD.long 0. 0. " NOOPTI ,No-op touch instructions" "0,1" RGROUP spr:0x3f1--0x3f1 "HID1-Register" LINE.long 0. "HID1, Hardware Implementation Register 1" BITFLD.long 0. 31. " PC0 ,PLL configuration bit0 (read only)" "0,1" BITFLD.long 0. 30. " PC1 ,PLL configuration bit1 (read only)" "0,1" BITFLD.long 0. 29. " PC2 ,PLL configuration bit2 (read only)" "0,1" BITFLD.long 0. 28. " PC3 ,PLL configuration bit3 (read only)" "0,1" textline " " BITFLD.long 0. 27. " PC4 ,PLL configuration bit4 (read only)" "0,1" BITFLD.long 0. 00. " FPD ,Floating Point Disabled" "0,1" GROUP spr:0x3f3--0x3f3 "HID2-Register" LINE.long 0. "HID2, Hardware Implementation Register 2" BITFLD.long 0. 27. " LET ,Little endian type. 0 = classic PowerPC LE 1 = true LE" "0,1" BITFLD.long 0. 18. " HiBatEN ,Enable IBAT 4-7 and DBAT 4-7. Abbreviated name for this bit is: HID2[13]HBE" "0,1" BITFLD.long 0. 16. " SFP ,Speed for low power" "0,1" BITFLD.long 0. 13.--15. " IWLCK ,Instruction cache way lock" "No Way,Reserved,Reserved,Reserved,Way 0,Reserved,Way 0/1,Way 0/1/2" BITFLD.long 0. 5.--7. " DWLCK ,Data cache way lock" "No Way,Reserved,Reserved,Reserved,Way 0,Reserved,Way 0/1,Way 0/1/2" tree.end tree "Debug Registers" group SPR:1010.++0 line.long 0x00 "IABR,Instruction Address Breakpoint Register (used by debugger)" hexmask.long 0x00 02.--31. 0x4 " CEA ,Compare effective address." bitfld.long 0x00 01. " BE ,Breakpoint enable" "0,1" group SPR:1018.++0 line.long 0x00 "IABR2,Instruction Address Breakpoint Register 2 (used by debugger)" hexmask.long 0x00 02.--31. 0x4 " CEA ,Compare effective address." bitfld.long 0x00 01. " BE ,Breakpoint enable" "0,1" TEXTLINE "" group SPR:1013.++0 line.long 0x00 "DABR,Data Address Breakpoint Register (used by debugger)" hexmask.long 0x00 03.--31. 0x8 " CEA ,Compare effective address." bitfld.long 0x00 02. " BT ,Breakpoint translation enable" "0,1" bitfld.long 0x00 01. " WBE ,Data write enable" "0,1" bitfld.long 0x00 00. " RBE ,Data read enable" "0,1" group SPR:317.++0 line.long 0x00 "DABR2,Data Address Breakpoint Register 2 (used by debugger)" hexmask.long 0x00 03.--31. 0x8 " CEA ,Compare effective address." bitfld.long 0x00 02. " BT ,Breakpoint translation enable" "0,1" bitfld.long 0x00 01. " WBE ,Data write enable" "0,1" bitfld.long 0x00 00. " RBE ,Data read enable" "0,1" TEXTLINE "" group SPR:309.++0 line.long 0x00 "IBCR,Instruction Address Breakpoint Control Register (used by debugger)" bitfld.long 0x00 22.--23. " CMP ,IABR breakpoint compare type" "IEA==IABR ,res,IEA=IABR " bitfld.long 0x00 20.--21. " CMP2 ,IABR2 breakpoint compare type" "IEA==IABR2,res,IEA=IABR2" bitfld.long 0x00 17. " SIG_TYPE ,Combinational signal type" "OR,AND" bitfld.long 0x00 16. " DNS ,Do not signal" "0,1" group SPR:310.++0 line.long 0x00 "DBCR,Data Address Breakpoint Control Register (used by debugger)" bitfld.long 0x00 22.--23. " CMP ,DABR breakpoint compare type" "DEA==DABR ,res,DEA=DABR " bitfld.long 0x00 20.--21. " CMP2 ,DABR2 breakpoint compare type" "DEA==DABR2,res,DEA=DABR2" bitfld.long 0x00 17. " SIG_TYPE ,Combinational signal type" "OR,AND" bitfld.long 0x00 16. " DNS ,Do not signal" "0,1" tree.end width 0xb tree.end tree "Memory Map Space Registers (MBAR + 0x0000)" width 10. group 0x00000++0x67 line.long 0x00 "MBAR,Module Address Base Register" hexmask.long 0x00 00.--15. 0x10000 " MBAR ,Module Address Base Register" line.long 0x04 "CS0STR ,CS0 Start Address Register" hexmask.long 0x04 00.--15. 0x10000 " CS0STR ," bitfld.word 0x54 00. " CS0_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x04))*0x10000)--(((d.l(anc:(iobase()+0x08))+1)*0x10000)-1) /dialog" line.long 0x08 "CS0STP ,CS0 Stop Address Register" hexmask.long 0x08 00.--15. 0x10000 0xffff " CS0STP ," line.long 0x0c "CS1STR ,CS1 Start Address Register" hexmask.long 0x0c 00.--15. 0x10000 " CS1STR ," bitfld.word 0x54 01. " CS1_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x0c))*0x10000)--(((d.l(anc:(iobase()+0x10))+1)*0x10000)-1) /dialog" line.long 0x10 "CS1STP ,CS1 Stop Address Register" hexmask.long 0x10 00.--15. 0x10000 0xffff " CS1STP ," line.long 0x14 "CS2STR ,CS2 Start Address Register" hexmask.long 0x14 00.--15. 0x10000 " CS2STR ," bitfld.word 0x54 02. " CS2_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x14))*0x10000)--(((d.l(anc:(iobase()+0x18))+1)*0x10000)-1) /dialog" line.long 0x18 "CS2STP ,CS2 Stop Address Register" hexmask.long 0x18 00.--15. 0x10000 0xffff " CS2STP ," line.long 0x1c "CS3STR ,CS3 Start Address Register" hexmask.long 0x1c 00.--15. 0x10000 " CS3STR ," bitfld.word 0x54 03. " CS3_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x1c))*0x10000)--(((d.l(anc:(iobase()+0x20))+1)*0x10000)-1) /dialog" line.long 0x20 "CS3STP ,CS3 Stop Address Register" hexmask.long 0x20 00.--15. 0x10000 0xffff " CS3STP ," line.long 0x24 "CS4STR ,CS4 Start Address Register" hexmask.long 0x24 00.--15. 0x10000 " CS4STR ," bitfld.word 0x54 04. " CS4_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x24))*0x10000)--(((d.l(anc:(iobase()+0x28))+1)*0x10000)-1) /dialog" line.long 0x28 "CS4STP ,CS4 Stop Address Register" hexmask.long 0x28 00.--15. 0x10000 0xffff " CS4STP ," line.long 0x2c "CS5STR ,CS5 Start Address Register" hexmask.long 0x2c 00.--15. 0x10000 " CS5STR ," bitfld.word 0x54 05. " CS5_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x2c))*0x10000)--(((d.l(anc:(iobase()+0x30))+1)*0x10000)-1) /dialog" line.long 0x30 "CS5STP ,CS5 Stop Address Register" hexmask.long 0x30 00.--15. 0x10000 0xffff " CS5STP ," line.long 0x58 "CS6STR ,CS6 Start Address Register" hexmask.long 0x58 00.--15. 0x10000 " CS6STR ," bitfld.word 0x54 10. " CS6_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x58))*0x10000)--(((d.l(anc:(iobase()+0x5c))+1)*0x10000)-1) /dialog" line.long 0x5c "CS6STP ,CS6 Stop Address Register" hexmask.long 0x5c 00.--15. 0x10000 0xffff " CS6STP ," line.long 0x60 "CS7STR ,CS7 Start Address Register" hexmask.long 0x60 00.--15. 0x10000 " CS7STR ," bitfld.word 0x54 11. " CS7_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x60))*0x10000)--(((d.l(anc:(iobase()+0x64))+1)*0x10000)-1) /dialog" line.long 0x64 "CS7STP ,CS7 Stop Address Register" hexmask.long 0x64 00.--15. 0x10000 0xffff " CS7STP ," line.long 0x4c "BOOTSTR ,Boot start address" hexmask.long 0x4c 00.--15. 0x10000 " BOOTSTR ," bitfld.word 0x54 09. " Boot_en ,Address space" "Disabled,Enabled" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x4c))*0x10000)--(((d.l(anc:(iobase()+0x50))+1)*0x10000)-1) /dialog" line.long 0x50 "BOOTSTP ,Boot stop address" hexmask.long 0x50 00.--15. 0x10000 0xffff " BOOTSTP ," Textline "" line.word 0x56 "WSER , Wait State Enable Register" bitfld.word 0x56 00. " WSE ,Wait State Enable bit" "Disabled,Enabled" line.word 0x54 "IPBICR ,IPBI Control Register" bitfld.word 0x54 11. " CS7_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 10. " CS6_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 09. " Boot_en ,Boot Address space" "Disabled,Enabled" Textline " " bitfld.word 0x54 05. " CS5_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 04. " CS4_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 03. " CS3_en ,Address space" "Disabled,Enabled" Textline " " bitfld.word 0x54 02. " CS2_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 01. " CS1_en ,Address space" "Disabled,Enabled" bitfld.word 0x54 00. " CS0_en ,Address space" "Disabled,Enabled" group 0x34--0x3b "SDRAM Chip Select Configuration Registers" line.long 0x00 "SDRAMCS0 ,Contains the Base Addresses and configurations for SDRAMs connected to the SDRAM controller." hexmask.long 0x00 20.--31. 0x100000 " SDRAMSTR ,Start address for memory" bitfld.long 0x00 00.--04. " SDRAM_Size ," "Disabled,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x34))&0xFFF80000)++((0x01<<(((d.l(anc:(iobase()+0x34)))&0x001f)+0x01))-0x01) /dialog" line.long 0x04 "SDRAMCS1 ,Contains the Base Addresses and configurations for SDRAMs connected to the SDRAM controller." hexmask.long 0x04 20.--31. 0x100000 " SDRAMSTR ," bitfld.long 0x04 00.--04. " SDRAM_Size ," "Disabled,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" textfld " " button "Dump" "d A:(d.l(anc:(iobase()+0x38))&0xFFF80000)++((0x01<<(((d.l(anc:(iobase()+0x38)))&0x001f)+0x01))-0x01) /dialog" width 0xb tree.end tree "ATA Registers (MBAR + 0x3A00)" width 14. group 0x3a00++0x3 "ATA Host Registers" line.long 0x0 "HCFG,Host Configuration" bitfld.long 0x0 31. " SMR ,State Machine Reset" "No reset,Reset" bitfld.long 0x0 30. " FR ,FIFO Reset" "No reset,Reset" textline " " bitfld.long 0x0 25. " IE ,Drive interrupt to pass to CPU in PIO modes" "Disabled,Enabled" bitfld.long 0x0 24. " IORDY ,IORDY support" "Not supported,Supported" group 0x3a04++0x3 line.long 0x0 "HSR,Host Status" bitfld.long 0x0 31. " TIP ,Transaction in Progress indicator" "Not pending,Pending" bitfld.long 0x0 30. " UREP ,UDMA Read Extended Pause" "No effect,Paused" textline " " bitfld.long 0x0 25. " RERR ,Read Error. An un-implemented register read" "No error,Error" bitfld.long 0x0 24. " WERR ,Write Error. An un-implemented register write" "No error,Error" group 0x3a08++0x3 line.long 0x0 "PIO1,PIO Timing 1" hexmask.long.byte 0x0 24.--31. 1. " PIO_t0 ,PIO cycle time" hexmask.long.byte 0x0 16.--23. 1. " PIO_t2_8 ,PIO read/write pulse width for 8-bit transfers" textline " " hexmask.long.byte 0x0 8.--15. 1. " PIO_t2_16 ,PIO read/write pulse width for 16-bit transfers" group 0x3a0c++0x3 line.long 0x0 "PIO2,PIO Timing 2" hexmask.long.byte 0x0 24.--31. 1. " PIO_t4 ,PIO write (DIOW) data hold time" hexmask.long.byte 0x0 16.--23. 1. " PIO_t1 ,Address valid to DIOR/DIOW setup" textline " " hexmask.long.byte 0x0 8.--15. 1. " PIO_ta ,IORDY setup time" group 0x3a10++0x3 line.long 0x0 "DMA1,Multiword DMA Timing 1" hexmask.long.byte 0x0 24.--31. 1. " DMA_t0 ,Multiword DMA cycle time" hexmask.long.byte 0x0 16.--23. 1. " DMA_td ,Multiword DMA read/write (DIOR/DIOW) asserted pulse width" textline " " hexmask.long.byte 0x0 8.--15. 1. " DMA_tk ,Multiword DMA read/write (DIOR/DIOW) negated pulse width" hexmask.long.byte 0x0 0.--7. 1. " DMA_tm ,/CS[0], /CS[1] valid to DIOR/DIOW" group 0x3a14++0x3 line.long 0x0 "DMA2,Multiword DMA Timing 2" hexmask.long.byte 0x0 24.--31. 1. " DMA_th ,Multiword DMA write (DIOW) data hold time" hexmask.long.byte 0x0 16.--23. 1. " DMA_tj ,Multiword DMA read/write (DIOR/DIOW) asserted pulse width" textline " " hexmask.long.byte 0x0 8.--15. 1. " DMA_tn ,/CS[0], /CS[1] hold" group 0x3a18++0x3 line.long 0x0 "UDMA1,Ultra DMA Timing 1" hexmask.long.byte 0x0 24.--31. 1. " UDMA_t2cyc ,Ultra DMA sustained average two cycle time" hexmask.long.byte 0x0 16.--23. 1. " UDMA_tcyc ,Ultra DMA strobe edge to strobe edge cycle time" textline " " hexmask.long.byte 0x0 8.--15. 1. " UDMA_tds ,Ultra DMA read data setup time" hexmask.long.byte 0x0 0.--7. 1. " UDMA_tdh ,Ultra DMA read data hold time" group 0x3a1c++0x3 line.long 0x0 "UDMA2,Ultra DMA Timing 2" hexmask.long.byte 0x0 24.--31. 1. " UDMA_tdvs ,Ultra DMA write data setup time" hexmask.long.byte 0x0 16.--23. 1. " UDMA_tdvh ,Ultra DMA write data hold time" textline " " hexmask.long.byte 0x0 8.--15. 1. " UDMA_tfs ,First strobe time during the initiation of ultra DMA data transfer" hexmask.long.byte 0x0 0.--7. 1. " UDMA_tli ,Limited interlock time with a defined maximum" group 0x3a20++0x3 line.long 0x0 "UDMA3,Ultra DMA Timing 3" hexmask.long.byte 0x0 24.--31. 1. " UDMA_tmli ,Limited interlock time with a defined minimum" hexmask.long.byte 0x0 16.--23. 1. " UDMA_taz ,Maximum time allowed for output drivers to release from being driven" textline " " hexmask.long.byte 0x0 8.--15. 1. " UDMA_tenv ,Envelope time from DMACK to STOP and HDMARDY during data-out burst initiation" hexmask.long.byte 0x0 0.--7. 1. " UDMA_tsr ,Strobe to DMARDY time" group 0x3a24++0x3 line.long 0x0 "UDMA4,Ultra DMA Timing 4" hexmask.long.byte 0x0 24.--31. 1. " UDMA_tss ,Time from strobe edge to negation of DMARQ (when drive terminates burst) or assertion of STOP (when host terminates burst)" hexmask.long.byte 0x0 16.--23. 1. " UDMA_trfs ,Ready-to-final-strobe time" textline " " hexmask.long.byte 0x0 8.--15. 1. " UDMA_trp ,Ready-to-pause time" hexmask.long.byte 0x0 0.--7. 1. " UDMA_tack ,Setup and hold times for DMACK before negation or assertion" group 0x3a28++0x3 line.long 0x0 "UDMA5,Ultra DMA Timing 5" hexmask.long.byte 0x0 24.--31. 1. " UDMA_tzah ,Minimum delay time required for output drivers to assert or negate from release state" group 0x3a2c++0x3 line.long 0x0 "ATA_SHRE_CNT, ATA Share Count Register" hexmask.long.byte 0x0 16.--31. 1. " ATA_share_cnt ,Length of the time slot assigned to ATA transactions" group 0x3a3c++0x3 "ATA FIFO Registers" line.long 0x0 "RTFDWR,Rx/Tx FIFO Data Word" hexmask.long.byte 0x0 0.--31. 1. " FIFO_Data_Word ,The FIFO data port" group 0x3a40++0x3 line.long 0x0 "RTFSR,Rx/Tx FIFO Status" eventfld.long 0x0 22. " Err ,Error - flag bit is essentially the logical OR of other flag bits" "No error,Error" eventfld.long 0x0 21. " UF ,UnderFlow - flag indicates read pointer has surpassed the write pointer" "No underflow,Underflow" textline " " eventfld.long 0x0 20. " OF ,OverFlow - flag indicates write pointer surpassed read pointer" "No overflow,Overflow" bitfld.long 0x0 19. " Full ,FIFO full - this is NOT a sticky bit or error condition" "No error,FIFO full" textline " " bitfld.long 0x0 18. " HI ,High - FIFO requests attention because high level alarm is asserted" "Not asserted,Asserted" bitfld.long 0x0 17. " LO ,Low - FIFO requests attention because low level alarm is asserted" "Not asserted,Asserted" textline " " bitfld.long 0x0 16. " Empty ,FIFO empty" "No error,FIFO empty" group 0x3a44++0x3 line.long 0x0 "RTFCR,Rx/Tx FIFO Control" bitfld.long 0x0 29. " WFR ,Write End of Frame (EOF)" "No error,EOF" bitfld.long 0x0 24.--26. " GR ,Granularity bits" "FIFO waiting,FIFO stopped data request,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x3a48++0x3 line.long 0x0 "RTFAR,Rx/Tx Alarm" hexmask.long.word 0x0 0.--11. 1. " Alarm ,Alarm" group 0x3a4c++0x3 line.long 0x0 "RTFRPR,Rx/Tx FIFO Read Pointer" hexmask.long.word 0x0 0.--11. 1. " ReadPtr ,Read address presented to the FIFO RAM" group 0x3a50++0x3 line.long 0x0 "RTFWPR,Rx/Tx FIFO Write Pointer" hexmask.long.word 0x0 0.--11. 1. " WritePTR ,Write address presented to the FIFO RAM" group 0x3a5c++0x3 "ATA Drive Registers" line.long 0x0 "DASR,Drive Alternate Status (read) / Device Control (write)" bitfld.long 0x0 31. " BSY ,Drive Busy (read)" "Idle,Busy" bitfld.long 0x0 30. " DRDY ,Drive Ready (read)" "Not ready,Ready" textline " " bitfld.long 0x0 27. " DRQ ,Transfer a word of data (read)" "Not ready,Ready" bitfld.long 0x0 26. " SRST ,Software Reset (write)" "No reset,Reset" textline " " bitfld.long 0x0 25. " nIEN ,Interrupt Enable (write)" "Disabled,Enabled" bitfld.long 0x0 24. " ERR ,Error during the execution of the previous command (read)" "No error,Error" group 0x3a60++0x3 line.long 0x0 "DDR,Drive Data" hexmask.long.byte 0x0 24.--31. 1. " Data , Upper byte of drive data" hexmask.long.byte 0x0 16.--23. 1. " Data , Lower byte of drive data" ;wgroup 0x3a64++0x3 ; line.long 0x0 "DFR,Drive Features (write)" ; hexmask.long.byte 0x0 24.--31. 1. " Data , Command parameters when the ATA drive command register is written" group 0x3a64++0x3 line.long 0x0 "DER,Drive Error (read)" hexmask.long.byte 0x0 27.--31. 1. " Data ,Command parameters when the ATA drive command register is written" bitfld.long 0x0 26. " ABRT ,Requested command aborted" ",Aborted" textline " " hexmask.long.byte 0x0 24.--25. 1. " Data ,Command parameters when the ATA drive command register is written" group 0x3a68++0x3 line.long 0x0 "DSCR,Drive Sector Count" hexmask.long.byte 0x0 24.--31. 1. " Data ,Total number of sectors requested for transfer" group 0x3a6c++0x3 line.long 0x0 "DSNR,Drive Sector Number" hexmask.long.byte 0x0 24.--31. 1. " Data ,Data transfer starting sector number (CHS), Part of the LBA address (LBA)" group 0x3a70++0x3 line.long 0x0 "DCLR,Drive Cylinder Low" hexmask.long.byte 0x0 24.--31. 1. " Data ,Data transfer starting sector number (CHS), Part of the LBA address (LBA)" group 0x3a74++0x3 line.long 0x0 "DCHR,Drive Cylinder High" hexmask.long.byte 0x0 24.--31. 1. " Data ,Data transfer starting sector number (CHS), Part of the LBA address (LBA)" group 0x3a78++0x3 line.long 0x0 "DDHR,Drive Device/Head" bitfld.long 0x0 30. " Data ,LBA addressing for data transfer" "Disabled,Enabled" hexmask.long.byte 0x0 24.--27. 1. " Data ,Data transfer starting sector number (CHS), Part of the LBA address (LBA)" group 0x3a7c++0x3 line.long 0x0 "DCR/DSR,Drive Device Command/Status" bitfld.long 0x0 31. " Data_0/BSY ,Data 0 / Drive busy" "0/Not Busy,1/Busy" bitfld.long 0x0 30. " Data_1/DRDY ,Data 1 / Drive ready" "0/Not ready,1/Ready" textline " " bitfld.long 0x0 28.--29. " Data_23 ,Data 2/3" "0,1,2,3" bitfld.long 0x0 27. " Data_4/DRQ ,Data 4 / Drive ready to transfer" "0/Not ready,1/Ready" textline " " bitfld.long 0x0 25.--26. " Data_56 ,Data 5/6" "0,1,2,3" bitfld.long 0x0 24. " Data_7/ERR ,Data 7 / ATA drive error" "0/No error,1/Error" textline " " bitfld.long 0x0 22. " HUT ,Host UDMA burst Terminate" "Disabled,Enabled" bitfld.long 0x0 21. " FR ,FIFO Reset" "No reset,Reset" textline " " bitfld.long 0x0 20. " FE ,FIFO flush in Rx mode" "Disabled,Enabled" bitfld.long 0x0 19. " IE ,Drive interrupt to pass to CPU in DMA/UDMA modes" "Disabled,Enabled" textline " " bitfld.long 0x0 18. " UDMA ,UDMA/DMA" "DMA,UDMA" bitfld.long 0x0 17. " READ ,READ DMA" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " WRITE ,WRITE DMA" "Disabled,Enabled" width 0xb tree.end tree "J1850 (BDLC Registers) (MBAR + 0x1300)" width 5. group 0x1300++0x0 line.byte 0x0 "CR1,BDLC Control 1" bitfld.byte 0x0 7. " IMSG ,Ignore Message Bit" "Disabled,Enabled" bitfld.byte 0x0 6. " CLKS ,Clock Select Bit" "1.048576 MHz,1 MHz" textline " " bitfld.byte 0x0 1. " IE ,Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x0 0. " WCM ,Wait Clock Mode" "BDLC_STOP,BDLC_WAIT" group 0x1301++0x0 line.byte 0x0 "VR,BDLC State Vector" bitfld.byte 0x0 2.--5. " I ,Interrupt State Vector (read)" "No Interrupts Pending,Received EOF,Received IFR byte,Rx data register full,Tx data register empty,Loss of arbitration,CRC error,Symbol invalid or out of range,Wakeup,?..." group 0x1304++0x0 line.byte 0x0 "CR2,BDLC Control 2" bitfld.byte 0x0 7. " SMRST ,State Machine Reset" "No reset,Reset" bitfld.byte 0x0 6. " DLOOP ,Digital Loopback Mode" "Disabled,Enabled" bitfld.byte 0x0 5. " 4XE ,4X Mode Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 4. " NBFS ,Normalization Bit Format Select" "Without CRC,With CRC" bitfld.byte 0x0 3. " TEOD ,Transmit End of Data" "No EOD,EOD" bitfld.byte 0x0 2. " TSIFR ,Transmit Single Byte IFR with no CRC" "Error,No error" textline " " bitfld.byte 0x0 1. " TMIFR1 ,Transmit Multiple Byte IFR with CRC" "Error,No error" bitfld.byte 0x0 0. " TMIFR0 ,Transmit Multiple Byte IFR with no CRC" "Error,No error" group 0x1305++0x0 line.byte 0x0 "DR, BDLC Data Register" hexmask.byte 0x0 0.--7. 1. " D7_D0 ,Receive/Transmit Data" group 0x1308++0x0 line.byte 0x0 "ARD,BDLC Analog Round Trip Delay" bitfld.byte 0x0 6. " RXPOL ,Receive Pin Polarity" "Inverted,Normal" bitfld.byte 0x0 0.--4. " BO4_BO0 ,BDLC Analog Roundtrip Delay Offset Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group 0x1309++0x0 line.byte 0x0 "RS,BDLC Rate Select" hexmask.byte 0x0 0.--7. 1. " R7_R0 ,Rate Select" group 0x130c++0x0 line.byte 0x0 "CR,BDLC Control" bitfld.byte 0x0 4. " BDLCE ,BDLC Enable" "Disabled,Enabled" bitfld.byte 0x0 0. " BREAK ,BREAK signal" "No BREAK,BREAK" rgroup 0x130d++0x0 line.byte 0x0 "ST,BDLC Status" bitfld.byte 0x0 0. " IDLE ,IDLE bit" "Not idle,Idle" width 0xb tree.end tree.open "MSCAN Registers (MBAR + 0x0900/0x0980)" tree "MSCAN 1 (MBAR + 0x0900)" base anc:iobase()+900 width 8. group 0x00++0x0 line.byte 0x0 "CTL0,Control Register 0" bitfld.byte 0x0 7. " RXFRM ,Received Frame" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 5. " CSWAI ,CAN Stops in Wait Mode" "Enabled,Disabled" bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Disabled,Enabled" group 0x01++0x0 line.byte 0x0 "CTL1,Control Register 1" bitfld.byte 0x0 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x0 6. " CLKSRC ,MSCAN Clock Source" "IP bus,Oscillator" textline " " bitfld.byte 0x0 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x0 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x0 2. " WUPM ,WakeUp Mode" "Disabled,Enabled" bitfld.byte 0x0 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" textline " " bitfld.byte 0x0 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group 0x04++0x0 line.byte 0x0 "BTR0,Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW ,Synchronization Jump Width" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles" bitfld.byte 0x0 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" group 0x05++0x0 line.byte 0x0 "BTR1,Bus Timing Register 1" bitfld.byte 0x0 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x0 4.--6. " TSEG[22:20] ,Time Segment 2" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles,5 Tq clock cycles,6 Tq clock cycles,7 Tq clock cycles,8 Tq clock cycles" textline " " bitfld.byte 0x0 0.--3. " TSEG[13:10] ,Time Segment 1" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles,5 Tq clock cycles,6 Tq clock cycles,7 Tq clock cycles,8 Tq clock cycles,9 Tq clock cycles,10 Tq clock cycles,11 Tq clock cycles,12 Tq clock cycles,13 Tq clock cycles,14 Tq clock cycles,15 Tq clock cycles,16 Tq clock cycles" group 0x08++0x0 line.byte 0x0 "RFLG,Rx Flag" bitfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" bitfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " bitfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "Pending,Overrun" bitfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" group 0x09++0x0 line.byte 0x0 "RIER,Rx Interrupt Enable" bitfld.byte 0x0 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x0 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x0 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x0 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x0 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x0 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group 0x0c++0x0 line.byte 0x0 "TFLG,Tx Flag" bitfld.byte 0x0 0.--2. " TXE[2:0] ,Transmitter Buffer Empty" "Buffer full,Buffer empty,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x0d++0x0 line.byte 0x0 "TIER,Tx Interrupt Enable" bitfld.byte 0x0 0.--2. " TXEIE[2:0] ,Transmitter Empty Interrupt Enable" "Disabled,Enabled,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x10++0x0 line.byte 0x0 "TARQ,Tx Message Abort Request" bitfld.byte 0x0 0.--2. " ABTRQ[2:0] ,Abort Request" "Not aborted,Aborted,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x11++0x0 line.byte 0x0 "TAAK,Tx Message Abort Ack" bitfld.byte 0x0 0.--2. " ABTAK[2:0] ,Abort Acknowledge" "Not aborted,Aborted,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x14++0x0 line.byte 0x0 "BSEL,Tx Buffer Select" bitfld.byte 0x0 0.--2. " TX[2:0] ,Transmit Buffer Select" "Deselected,Selected,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x15++0x0 line.byte 0x0 "IDAC,ID Acceptance Control" bitfld.byte 0x0 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x0 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" rgroup 0x1c++0x0 line.byte 0x0 "RXERR,Rx Error" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN receive error counter." rgroup 0x1d++0x0 line.byte 0x0 "TXERR,Tx Error" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN transmit error counter." group 0x20++0x0 line.byte 0x0 "IDAR0,ID Acceptance 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x21++0x0 line.byte 0x0 "IDAR1,ID Acceptance 1" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x24++0x0 line.byte 0x0 "IDAR2,ID Acceptance 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x25++0x0 line.byte 0x0 "IDAR3,ID Acceptance 3" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x30++0x0 line.byte 0x0 "IDAR4,ID Acceptance 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x31++0x0 line.byte 0x0 "IDAR5,ID Acceptance 5" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x34++0x0 line.byte 0x0 "IDAR6,ID Acceptance 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x35++0x0 line.byte 0x0 "IDAR7,ID Acceptance 7" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x28++0x0 line.byte 0x0 "IDMR0,ID Mask 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x29++0x0 line.byte 0x0 "IDMR1,ID Mask 1" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x2c++0x0 line.byte 0x0 "IDMR2,ID Mask 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x2d++0x0 line.byte 0x0 "IDMR3,ID Mask 3" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x38++0x0 line.byte 0x0 "IDMR4,ID Mask 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x39++0x0 line.byte 0x0 "IDMR5,ID Mask 5" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x3c++0x0 line.byte 0x0 "IDMR6,ID Mask 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x3d++0x0 line.byte 0x0 "IDMR7,ID Mask 7" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" width 8. if (((d.b(anc:(iobase()+900+0x41)))&0x8)==0x8) group 0x40++0x0 "Foreground Receive Buffer" line.byte 0x0 "RXIDR0,Rx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" group 0x41++0x0 line.byte 0x0 "RXIDR1,Rx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " SRR ,Substitute Remote Request" "Not requested,Requested" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" textline " " bitfld.byte 0x0 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group 0x44++0x0 line.byte 0x0 "RXIDR2,Rx ID Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" group 0x45++0x0 line.byte 0x0 "RXIDR3,Rx ID Register 3" hexmask.byte 0x0 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x0 0. " RTR ,Remote Transmission Request" "Data,Remote" else group 0x40++0x0 "Foreground Receive Buffer" line.byte 0x0 "RXIDR0,Rx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Extended format identifier" group 0x41++0x0 line.byte 0x0 "RXIDR1,Rx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[2:0] ,Standard format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" hgroup 0x44++0x0 hide.byte 0x0 "RXIDR2,Rx ID Register 2" hgroup 0x45++0x0 hide.byte 0x0 "RXIDR3,Rx ID Register 3" endif group 0x48++0x0 line.byte 0x0 "RXDSR0,Rx Data Segment 0" group 0x49++0x0 line.byte 0x0 "RXDSR1,Rx Data Segment 1" group 0x4c++0x0 line.byte 0x0 "RXDSR2,Rx Data Segment 2" group 0x4d++0x0 line.byte 0x0 "RXDSR3,Rx Data Segment 3" group 0x50++0x0 line.byte 0x0 "RXDSR4,Rx Data Segment 4" group 0x51++0x0 line.byte 0x0 "RXDSR5,Rx Data Segment 5" group 0x54++0x0 line.byte 0x0 "RXDSR6,Rx Data Segment 6" group 0x55++0x0 line.byte 0x0 "RXDSR7,Rx Data Segment 7" group 0x58++0x0 line.byte 0x0 "TXDLR,Rx Data Length" hexmask.byte 0x0 0.--3. 1. " DLR ,Data Length Code" group 0x5c++0x0 line.byte 0x0 "RXTIMH,Rx Time Stamp High" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time Stamp High Register" group 0x5d++0x0 line.byte 0x0 "RXTIML,Rx Time Stamp Low" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time Stamp Low Register" width 8. if (((d.b(anc:(iobase()+900+0x61)))&0x8)==0x8) group 0x60++0x0 "Foreground Transmit Buffer" line.byte 0x0 "TXIDR0,Tx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" group 0x61++0x0 line.byte 0x0 "TXIDR1,Tx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " SRR ,Substitute Remote Request" "Not requested,Requested" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" textline " " bitfld.byte 0x0 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group 0x64++0x0 line.byte 0x0 "TXIDR2,Tx ID Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" group 0x65++0x0 line.byte 0x0 "TXIDR3,Tx ID Register 3" hexmask.byte 0x0 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x0 0. " RTR ,Remote Transmission Request" "Data,Remote" else group 0x60++0x0 "Foreground Transmit Buffer" line.byte 0x0 "TXIDR0,Tx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Extended format identifier" group 0x61++0x0 line.byte 0x0 "TXIDR1,Tx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[2:0] ,Standard format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" hgroup 0x64++0x0 hide.byte 0x0 "TXIDR2,Tx ID Register 2" hgroup 0x65++0x0 hide.byte 0x0 "TXIDR3,Tx ID Register 3" endif group 0x68++0x0 line.byte 0x0 "TXDSR0,Tx Data Segment 0" group 0x69++0x0 line.byte 0x0 "TXDSR1,Tx Data Segment 1" group 0x6c++0x0 line.byte 0x0 "TXDSR2,Tx Data Segment 2" group 0x6d++0x0 line.byte 0x0 "TXDSR3,Tx Data Segment 3" group 0x70++0x0 line.byte 0x0 "TXDSR4,Tx Data Segment 4" group 0x71++0x0 line.byte 0x0 "TXDSR5,Tx Data Segment 5" group 0x74++0x0 line.byte 0x0 "TXDSR6,Tx Data Segment 6" group 0x75++0x0 line.byte 0x0 "TXDSR7,Tx Data Segment 7" group 0x78++0x0 line.byte 0x0 "TXDLR,Tx Data Length" hexmask.byte 0x0 0.--3. 1. " DLC ,Data Length Code" group 0x79++0x0 line.byte 0x0 "TXTBPR,Tx Buffer Priority" hexmask.byte 0x0 0.--7. 1. " PRIO[7:0] ,Priority of associated message buffer" rgroup 0x7c++0x0 line.byte 0x0 "TXTIMH,Tx Time Stamp High" hexmask.byte 0x0 0.--7. 1. " TSR[15:8] ,Time stamp" rgroup 0x7d++0x0 line.byte 0x0 "TXTIML,Tx Time Stamp Low" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time stamp" width 0xb tree.end tree "MSCAN 2 (MBAR + 0x0980)" base anc:iobase()+980 width 8. group 0x00++0x0 line.byte 0x0 "CTL0,Control Register 0" bitfld.byte 0x0 7. " RXFRM ,Received Frame" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 5. " CSWAI ,CAN Stops in Wait Mode" "Enabled,Disabled" bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Disabled,Enabled" group 0x01++0x0 line.byte 0x0 "CTL1,Control Register 1" bitfld.byte 0x0 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x0 6. " CLKSRC ,MSCAN Clock Source" "IP bus,Oscillator" textline " " bitfld.byte 0x0 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x0 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x0 2. " WUPM ,WakeUp Mode" "Disabled,Enabled" bitfld.byte 0x0 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" textline " " bitfld.byte 0x0 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group 0x04++0x0 line.byte 0x0 "BTR0,Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW ,Synchronization Jump Width" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles" bitfld.byte 0x0 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" group 0x05++0x0 line.byte 0x0 "BTR1,Bus Timing Register 1" bitfld.byte 0x0 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x0 4.--6. " TSEG[22:20] ,Time Segment 2" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles,5 Tq clock cycles,6 Tq clock cycles,7 Tq clock cycles,8 Tq clock cycles" textline " " bitfld.byte 0x0 0.--3. " TSEG[13:10] ,Time Segment 1" "1 Tq clock cycle,2 Tq clock cycles,3 Tq clock cycles,4 Tq clock cycles,5 Tq clock cycles,6 Tq clock cycles,7 Tq clock cycles,8 Tq clock cycles,9 Tq clock cycles,10 Tq clock cycles,11 Tq clock cycles,12 Tq clock cycles,13 Tq clock cycles,14 Tq clock cycles,15 Tq clock cycles,16 Tq clock cycles" group 0x08++0x0 line.byte 0x0 "RFLG,Rx Flag" bitfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" bitfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " bitfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "Pending,Overrun" bitfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" group 0x09++0x0 line.byte 0x0 "RIER,Rx Interrupt Enable" bitfld.byte 0x0 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x0 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x0 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x0 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x0 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x0 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group 0x0c++0x0 line.byte 0x0 "TFLG,Tx Flag" bitfld.byte 0x0 0.--2. " TXE[2:0] ,Transmitter Buffer Empty" "Buffer full,Buffer empty,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x0d++0x0 line.byte 0x0 "TIER,Tx Interrupt Enable" bitfld.byte 0x0 0.--2. " TXEIE[2:0] ,Transmitter Empty Interrupt Enable" "Disabled,Enabled,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x10++0x0 line.byte 0x0 "TARQ,Tx Message Abort Request" bitfld.byte 0x0 0.--2. " ABTRQ[2:0] ,Abort Request" "Not aborted,Aborted,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x11++0x0 line.byte 0x0 "TAAK,Tx Message Abort Ack" bitfld.byte 0x0 0.--2. " ABTAK[2:0] ,Abort Acknowledge" "Not aborted,Aborted,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x14++0x0 line.byte 0x0 "BSEL,Tx Buffer Select" bitfld.byte 0x0 0.--2. " TX[2:0] ,Transmit Buffer Select" "Deselected,Selected,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group 0x15++0x0 line.byte 0x0 "IDAC,ID Acceptance Control" bitfld.byte 0x0 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x0 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" rgroup 0x1c++0x0 line.byte 0x0 "RXERR,Rx Error" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN receive error counter." rgroup 0x1d++0x0 line.byte 0x0 "TXERR,Tx Error" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN transmit error counter." group 0x20++0x0 line.byte 0x0 "IDAR0,ID Acceptance 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x21++0x0 line.byte 0x0 "IDAR1,ID Acceptance 1" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x24++0x0 line.byte 0x0 "IDAR2,ID Acceptance 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x25++0x0 line.byte 0x0 "IDAR3,ID Acceptance 3" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x30++0x0 line.byte 0x0 "IDAR4,ID Acceptance 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x31++0x0 line.byte 0x0 "IDAR5,ID Acceptance 5" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x34++0x0 line.byte 0x0 "IDAR6,ID Acceptance 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x35++0x0 line.byte 0x0 "IDAR7,ID Acceptance 7" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" group 0x28++0x0 line.byte 0x0 "IDMR0,ID Mask 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x29++0x0 line.byte 0x0 "IDMR1,ID Mask 1" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x2c++0x0 line.byte 0x0 "IDMR2,ID Mask 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x2d++0x0 line.byte 0x0 "IDMR3,ID Mask 3" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x38++0x0 line.byte 0x0 "IDMR4,ID Mask 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x39++0x0 line.byte 0x0 "IDMR5,ID Mask 5" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x3c++0x0 line.byte 0x0 "IDMR6,ID Mask 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group 0x3d++0x0 line.byte 0x0 "IDMR7,ID Mask 7" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" width 8. if (((d.b(anc:(iobase()+980+0x41)))&0x8)==0x8) group 0x40++0x0 "Foreground Receive Buffer" line.byte 0x0 "RXIDR0,Rx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" group 0x41++0x0 line.byte 0x0 "RXIDR1,Rx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " SRR ,Substitute Remote Request" "Not requested,Requested" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" textline " " bitfld.byte 0x0 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group 0x44++0x0 line.byte 0x0 "RXIDR2,Rx ID Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" group 0x45++0x0 line.byte 0x0 "RXIDR3,Rx ID Register 3" hexmask.byte 0x0 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x0 0. " RTR ,Remote Transmission Request" "Data,Remote" else group 0x40++0x0 "Foreground Receive Buffer" line.byte 0x0 "RXIDR0,Rx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Extended format identifier" group 0x41++0x0 line.byte 0x0 "RXIDR1,Rx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[2:0] ,Standard format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" hgroup 0x44++0x0 hide.byte 0x0 "RXIDR2,Rx ID Register 2" hgroup 0x45++0x0 hide.byte 0x0 "RXIDR3,Rx ID Register 3" endif group 0x48++0x0 line.byte 0x0 "RXDSR0,Rx Data Segment 0" group 0x49++0x0 line.byte 0x0 "RXDSR1,Rx Data Segment 1" group 0x4c++0x0 line.byte 0x0 "RXDSR2,Rx Data Segment 2" group 0x4d++0x0 line.byte 0x0 "RXDSR3,Rx Data Segment 3" group 0x50++0x0 line.byte 0x0 "RXDSR4,Rx Data Segment 4" group 0x51++0x0 line.byte 0x0 "RXDSR5,Rx Data Segment 5" group 0x54++0x0 line.byte 0x0 "RXDSR6,Rx Data Segment 6" group 0x55++0x0 line.byte 0x0 "RXDSR7,Rx Data Segment 7" group 0x58++0x0 line.byte 0x0 "TXDLR,Rx Data Length" hexmask.byte 0x0 0.--3. 1. " DLR ,Data Length Code" group 0x5c++0x0 line.byte 0x0 "RXTIMH,Rx Time Stamp High" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time Stamp High Register" group 0x5d++0x0 line.byte 0x0 "RXTIML,Rx Time Stamp Low" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time Stamp Low Register" width 8. if (((d.b(anc:(iobase()+980+0x61)))&0x8)==0x8) group 0x60++0x0 "Foreground Transmit Buffer" line.byte 0x0 "TXIDR0,Tx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" group 0x61++0x0 line.byte 0x0 "TXIDR1,Tx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " SRR ,Substitute Remote Request" "Not requested,Requested" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" textline " " bitfld.byte 0x0 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group 0x64++0x0 line.byte 0x0 "TXIDR2,Tx ID Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" group 0x65++0x0 line.byte 0x0 "TXIDR3,Tx ID Register 3" hexmask.byte 0x0 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x0 0. " RTR ,Remote Transmission Request" "Data,Remote" else group 0x60++0x0 "Foreground Transmit Buffer" line.byte 0x0 "TXIDR0,Tx Standard/Extended ID Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Extended format identifier" group 0x61++0x0 line.byte 0x0 "TXIDR1,Tx Standard/Extended ID Register 1" bitfld.byte 0x0 5.--7. " ID[2:0] ,Standard format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.byte 0x0 3. " IDE ,ID Extended" "Standard,Extended" hgroup 0x64++0x0 hide.byte 0x0 "TXIDR2,Tx ID Register 2" hgroup 0x65++0x0 hide.byte 0x0 "TXIDR3,Tx ID Register 3" endif group 0x68++0x0 line.byte 0x0 "TXDSR0,Tx Data Segment 0" group 0x69++0x0 line.byte 0x0 "TXDSR1,Tx Data Segment 1" group 0x6c++0x0 line.byte 0x0 "TXDSR2,Tx Data Segment 2" group 0x6d++0x0 line.byte 0x0 "TXDSR3,Tx Data Segment 3" group 0x70++0x0 line.byte 0x0 "TXDSR4,Tx Data Segment 4" group 0x71++0x0 line.byte 0x0 "TXDSR5,Tx Data Segment 5" group 0x74++0x0 line.byte 0x0 "TXDSR6,Tx Data Segment 6" group 0x75++0x0 line.byte 0x0 "TXDSR7,Tx Data Segment 7" group 0x78++0x0 line.byte 0x0 "TXDLR,Tx Data Length" hexmask.byte 0x0 0.--3. 1. " DLC ,Data Length Code" group 0x79++0x0 line.byte 0x0 "TXTBPR,Tx Buffer Priority" hexmask.byte 0x0 0.--7. 1. " PRIO[7:0] ,Priority of associated message buffer" rgroup 0x7c++0x0 line.byte 0x0 "TXTIMH,Tx Time Stamp High" hexmask.byte 0x0 0.--7. 1. " TSR[15:8] ,Time stamp" rgroup 0x7d++0x0 line.byte 0x0 "TXTIML,Tx Time Stamp Low" hexmask.byte 0x0 0.--7. 1. " TSR[7:0] ,Time stamp" width 0xb tree.end tree.end ;Default MBAR Address base anc:iobase() tree "CDM Registers (MBAR + 0x0200)" width 8. rgroup 0x200++0x3 line.long 0x0 "JTAGID,CDM JTAG ID Number" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B rgroup 0x204++0x3 line.long 0x0 "PORCFG,CDM Power ON Reset Configuration" bitfld.long 0x0 16. " sys_pll_bypass ,System PLL bypass mode" "Normal,SYS OSC clock" bitfld.long 0x0 15. " boot_rom_lf ,Large Flash mode is selected" "Deselected,Selected" textline " " bitfld.long 0x0 14. " boot_rom_type ,Latched pin value at reset" "Non-muxed,Muxed" bitfld.long 0x0 13. " boot_rom_size ,Latched pin value at reset (Non-muxed/Muxed)" "8bit/16bit,16bit/32bit" textline " " bitfld.long 0x0 12. " boot_rom_swap ,Latched pin value at reset" "No byte lane,Byte lane" bitfld.long 0x0 11. " boot_rom_wait ,Latched pin value at reset" "4 PCI locks,48 PCI clocks" textline " " bitfld.long 0x0 10. " ppc_msrip ,Latched pin value at reset." "0000_0100,FFF0_0100" bitfld.long 0x0 8. " boot_rom_mg ,Most/Graphic Mode is selected as BOOT mode" "Deselected,Selected" textline " " bitfld.long 0x0 7. " sys_pll_cfg_1 ,Latched pin value at reset" "No operation,Doubled" bitfld.long 0x0 6. " sys_pll_cfg_0 ,Latched pin value at reset" "16x,12x" textline " " bitfld.long 0x0 5. " xlb_clk_sel ,Latched pin value at reset" "fvco_sys/4,fvco_sys/8" hexmask.long.byte 0x0 0.--4. 1. " ppc_pll_cfg_[0:4] ,603e G2_LE Core PLL config pin" else group 0x204++0x3 line.long 0x0 "PORCFG,CDM Power ON Reset Configuration" hexmask.long.byte 0x0 24.--28. 1. " tap_select[0:4] ,Delay of the internal sdram controller read clock" bitfld.long 0x0 16. " sys_pll_bypass ,System PLL bypass mode" "Normal,SYS OSC clock" textline " " bitfld.long 0x0 15. " boot_rom_lf ,Large Flash mode is selected" "Deselected,Selected" bitfld.long 0x0 14. " boot_rom_type ,Latched pin value at reset" "Non-muxed,Muxed" textline " " bitfld.long 0x0 13. " boot_rom_size ,Latched pin value at reset (Non-muxed/Muxed)" "8bit/16bit,16bit/32bit" bitfld.long 0x0 12. " boot_rom_swap ,Latched pin value at reset" "No byte lane,Byte lane" textline " " bitfld.long 0x0 11. " boot_rom_wait ,Latched pin value at reset" "4 PCI locks,48 PCI clocks" bitfld.long 0x0 10. " ppc_msrip ,Latched pin value at reset." "0000_0100,FFF0_0100" textline " " bitfld.long 0x0 8. " boot_rom_mg ,Most/Graphic Mode is selected as BOOT mode" "Deselected,Selected" bitfld.long 0x0 7. " sys_pll_cfg_1 ,Latched pin value at reset" "No operation,Doubled" textline " " bitfld.long 0x0 6. " sys_pll_cfg_0 ,Latched pin value at reset" "16x,12x" bitfld.long 0x0 5. " xlb_clk_sel ,Latched pin value at reset" "fvco_sys/4,fvco_sys/8" textline " " hexmask.long.byte 0x0 0.--4. 1. " ppc_pll_cfg_[0:4] ,603e G2_LE Core PLL config pin" endif elif (cpu()=="MGT5100") group 0x204++0x3 line.long 0x0 "PORCFG,CDM Power ON Reset Configuration" hexmask.long.byte 0x0 24.--28. 1. " tap_select[0:4] ,Delay of the internal sdram controller read clock" bitfld.long 0x0 16. " sys_pll_bypass ,System PLL bypass mode" "Normal,SYS OSC clock" textline " " bitfld.long 0x0 15. " boot_rom_lf ,Large Flash mode is selected" "Deselected,Selected" bitfld.long 0x0 14. " boot_rom_type ,Latched pin value at reset" "Non-muxed,Muxed" textline " " bitfld.long 0x0 13. " boot_rom_size ,Latched pin value at reset (Non-muxed/Muxed)" "8bit/16bit,16bit/32bit" bitfld.long 0x0 12. " boot_rom_swap ,Latched pin value at reset" "No byte lane,Byte lane" textline " " bitfld.long 0x0 11. " boot_rom_wait ,Latched pin value at reset" "4 PCI locks,48 PCI clocks" bitfld.long 0x0 10. " ppc_msrip ,Latched pin value at reset." "0000_0100,FFF0_0100" textline " " bitfld.long 0x0 8. " boot_rom_mg ,Most/Graphic Mode is selected as BOOT mode" "Deselected,Selected" bitfld.long 0x0 7. " sys_pll_cfg_1 ,Latched pin value at reset" "No operation,Doubled" textline " " bitfld.long 0x0 6. " sys_pll_cfg_0 ,Latched pin value at reset" "16x,12x" bitfld.long 0x0 5. " xlb_clk_sel ,Latched pin value at reset" "fvco_sys/4,fvco_sys/8" textline " " hexmask.long.byte 0x0 0.--4. 1. " ppc_pll_cfg_[0:4] ,603e G2_LE Core PLL config pin" endif group 0x208++0x3 line.long 0x0 "BC,CDM Bread Crumb" group 0x20c++0x3 line.long 0x0 "CFG,CDM Configuration" bitfld.long 0x0 24. " ddr_mode ,SDRAM Controller DDR memory mode, read-only." "SDR,DDR" bitfld.long 0x0 16. " xlb_clk_sel ,XLB Clock Frequency, read-only." "CDM_SYS_PLL_FVCO/4,CDM_SYS_PLL_FVCO/8" textline " " bitfld.long 0x0 8. " ipb_clk_sel ,IPB Clock Select" "XLB_CLK,XLB_CLK/2" bitfld.long 0x0 0.--1. " pci_clk_sel ,PCI Clock Select" "IPB_CLK,IPB_CLK/2,XLB_CLK/4,Reserved" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x210++0x3 line.long 0x0 "FDCFG,CDM 48 MHz Fractional Divider Configuration" bitfld.long 0x0 26. " ext_usb_48MHz_en ,Enable synchronization logic which synchronize the external ext_usb_48Mhz" "Not synchronized,Synchronized" textline " " bitfld.long 0x0 25. " ext_usb_48MHz_en ,USB External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 24. " ext_irda_48MHz_en ,IrDA External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 16. " fd_en ,CDM 48MHz Fractional Divider Enable" "Disabled,Enabled" bitfld.long 0x0 12.--14. " cgfd_p3_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 8.--10. " cgfd_p2_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" bitfld.long 0x0 4.--6. " cgfd_p1_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 0.--2. " cgfd_p0_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" else group 0x210++0x3 line.long 0x0 "FDCFG,CDM 48 MHz Fractional Divider Configuration" bitfld.long 0x0 25. " ext_usb_48MHz_en ,USB External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 24. " ext_irda_48MHz_en ,IrDA External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 16. " fd_en ,CDM 48MHz Fractional Divider Enable" "Disabled,Enabled" bitfld.long 0x0 12.--14. " cgfd_p3_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 8.--10. " cgfd_p2_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" bitfld.long 0x0 4.--6. " cgfd_p1_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 0.--2. " cgfd_p0_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" endif elif (cpu()=="MGT5100") group 0x210++0x3 line.long 0x0 "FDCFG,CDM 48 MHz Fractional Divider Configuration" bitfld.long 0x0 25. " ext_usb_48MHz_en ,USB External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 24. " ext_irda_48MHz_en ,IrDA External 48MHz Clock Select" "CMD Fractional Divider,GPIO" textline " " bitfld.long 0x0 16. " fd_en ,CDM 48MHz Fractional Divider Enable" "Disabled,Enabled" bitfld.long 0x0 12.--14. " cgfd_p3_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 8.--10. " cgfd_p2_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" bitfld.long 0x0 4.--6. " cgfd_p1_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" textline " " bitfld.long 0x0 0.--2. " cgfd_p0_cnt[2:0] ,4 phase divide ratios used by the fractional divider." "fvco_clk/8,fvco_clk/9,fvco_clk/10,fvco_clk/11,fvco_clk/11,fvco_clk/11,fvco_clk/6,fvco_clk/7" endif group 0x214++0x3 line.long 0x0 "CLKEN,CDM Clock Enable" bitfld.long 0x0 19. " mem_clk_en ,Memory Clock Enable" "Disabled,Enabled" bitfld.long 0x0 18. " pci_clk_en ,PCI Bus Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " lpc_clk_en ,Local Plus Bus Clock Enable" "Disabled,Enabled" bitfld.long 0x0 16. " slt_clk_en ,Slice Timer Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " scom_clk_en ,Smart Comm Clock Enable" "Disabled,Enabled" bitfld.long 0x0 14. " ata_clk_en ,ATA Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " eth_clk_en ,Ethernet Clock Enable" "Disabled,Enabled" bitfld.long 0x0 12. " usb_clk_en ,Universal Serial Bus Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " spi_clk_en ,SPI Clock Enable" "Disabled,Enabled" bitfld.long 0x0 10. " pli_clk_en ,PLI Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 9. " irrx_clk_en ,Infrared Receive Clock Enable" "Disabled,Enabled" bitfld.long 0x0 8. " irtx_clk_en ,Infrared Transmit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " psc3_clk_en ,PCI #3,4,5 Clock Enable" "Disabled,Enabled" bitfld.long 0x0 6. " psc2_clk_en ,PCI #2 Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " psc1_clk_en ,PCI #1 Clock Enable" "Disabled,Enabled" bitfld.long 0x0 4. " irda_clk_en ,IRDA Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " mscan_clk_en ,MSCAN Clock Enable" "Disabled,Enabled" bitfld.long 0x0 2. " i2c_clk_en ,I2C Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " timer_clk_en ,Timer Clock Enable" "Disabled,Enabled" bitfld.long 0x0 0. " gpio_clk_en ,GPIO Clock Enable" "Disabled,Enabled" group 0x218++0x3 line.long 0x0 "OSCCFG,CDM System Oscillator Configuration" bitfld.long 0x0 24. " sys_osc_disable ,CDM System Oscillator Disable" "Enabled,Disabled" group 0x21c++0x3 line.long 0x0 "CCSCFG,CDM Clock Control Sequencer Configuration" bitfld.long 0x0 24. " ccs_sleep_en ,CCS Module Enable" "Disabled,Enabled" bitfld.long 0x0 16. " ccs_osc_sleep_en ,CCS System Oscillator Disable Control" "Active,Sleep mode" textline " " bitfld.long 0x0 0. " ccs_qreq_test ,CCS Test bitG2" "Active,602e G2_LE Core" group 0x220++0x3 line.long 0x0 "SFTRST,CDM Soft Reset" bitfld.long 0x0 24. " cdm_soft_reset ,CDM Soft Reset bit." "Reset,No reset" bitfld.long 0x0 16. " cdm_no_ckstp_reset ,CDM No checkstop on reset." "Reset,No reset" group 0x224++0x3 line.long 0x0 "PLLSTA,SCDM ystem PLL Status" bitfld.long 0x0 24. " pll_lock ,CDM System PLL Lock Detect" "Detected,Not detected" bitfld.long 0x0 16. " pll_lost_lock ,CDM System PLL Lock Lost" "Not detected,Detected" textline " " bitfld.long 0x0 8. " pll_small_lock_window ,PLL Small Lock Window" "4 fvco_sys,2 f_vco_sys" group 0x228++0x3 line.long 0x0 "PSC1CC,PSC1 Clock Config" bitfld.long 0x0 15. " MClockEnable ,PSC1 Mclock enable." "Disabled,Enabled" hexmask.long.word 0x0 0.--8. 1. " MclkDiv[8:0] ,The value in which to divide the MCLK frequency to get the bit clock rate" group 0x22c++0x3 line.long 0x0 "PSC2CC,PSC2 Clock Config" bitfld.long 0x0 15. " MClockEnable ,PSC2 Mclock enable." "Disabled,Enabled" hexmask.long.word 0x0 0.--8. 1. " MclkDiv[8:0] ,The value in which to divide the MCLK frequency to get the bit clock rate" group 0x230++0x3 line.long 0x0 "PSC3CC,PSC3 Clock Config" bitfld.long 0x0 15. " MClockEnable ,PSC3 Mclock enable." "Disabled,Enabled" hexmask.long.word 0x0 0.--8. 1. " MclkDiv[8:0] ,The value in which to divide the MCLK frequency to get the bit clock rate" group 0x234++0x3 line.long 0x0 "PSC6CC,PSC6 Clock Config" bitfld.long 0x0 15. " MClockEnable ,PSC6 Mclock enable." "Disabled,Enabled" hexmask.long.word 0x0 0.--8. 1. " MclkDiv[8:0] ,The value in which to divide the MCLK frequency to get the bit clock rate" width 0xb tree.end tree.open "Fast Ethernet Controller Registers (MBAR + 0x3000)" tree "Control/Status Registers" width 15. group 0x3000++0x3 line.long 0x0 "FEC_ID,FEC ID" hexmask.long.word 0x0 16.--31. 1. " FEC_ID ,Value identifying the FEC" bitfld.long 0x0 10. " DMA ,DMA function is included in the FEC" "Not included,Included" textline " " bitfld.long 0x0 9. " FIFO ,FIFO function included in the FEC" "Not included,Included" hexmask.long.byte 0x0 0.--7. 1. " FEC_REV ,Value identifies the FEC revision" group 0x3004++0x3 line.long 0x0 "IEVENT,FEC Interrupt Event" bitfld.long 0x0 31. " HBERR ,Heartbeat Error" "No error,Error" bitfld.long 0x0 30. " BABR ,Babbling Receive Error" "No error,Error" textline " " bitfld.long 0x0 29. " BABT ,Babbling Transmit Error" "No error,Error" bitfld.long 0x0 28. " GRA ,Graceful Stop Complete" "Pending,Paused" textline " " bitfld.long 0x0 27. " TFINT ,Transmit frame interrupt" "Disabled,Enabled" bitfld.long 0x0 23. " MII ,MII Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 21. " LATE_COL ,Collision occurred" "Not occurred,Occurred" bitfld.long 0x0 20. " COL_RETRY_LIM ,Collision Retry Limit" "Not occurred,Occurred" textline " " bitfld.long 0x0 19. " XFIFO_UN ,Transmit FIFO Underrun Error" "No error,Error" bitfld.long 0x0 18. " XFIFO_ERROR ,Transmit FIFO Error" "No error,Error" textline " " bitfld.long 0x0 17. " RFIFO_ERROR ,Receive FIFO Error" "No error,Error" rgroup 0x3008++0x3 line.long 0x0 "IMASK,FEC Interrupt Enable" bitfld.long 0x0 31. " HBEEN ,Heartbeat Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 30. " BREN ,Babbling Receiver Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " BTEN ,Babbling Transmitter Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 28. " GRAEN ,Graceful Stop Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " TFINTEN ,Transmit Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 23. " MIIEN ,MII Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 21. " LCEN ,Late Collision Enable" "Disabled,Enabled" bitfld.long 0x0 20. " CRLEN ,Late Collision Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " XFUNEN ,Transmit FIFO Underrun Enable" "Disabled,Enabled" bitfld.long 0x0 18. " XFERREN ,Transmit FIFO Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " RFERREN ,Receive FIFO Error Enable" "Disabled,Enabled" group 0x3010++0x03 line.long 0x0 "R_DES_ACTIVE, Receive Ring Update Flag" bitfld.long 0x0 24. " R_DES_ACTIVE ,Rx Descriptor Active" "Inactive,Active" group 0x3014++0x03 line.long 0x0 "X_DES_ACTIVE, Transmit Ring Update Flag" bitfld.long 0x0 24. " X_DES_ACTIVE ,Tx Descriptor Active" "Inactive,Active" group 0x3024++0x3 line.long 0x0 "ECNTRL,FEC Ethernet Control" hexmask.long.byte 0x0 28.--31. 1. " TAG[0:3] ,Programming and reading the TBUS tag bits" bitfld.long 0x0 26. " TESTMD ,Test Mode used for manufacturing test only" "Normal,Test mode" textline " " bitfld.long 0x0 2. " FEC_OE ,FEC Output Enable" "Disabled,Enabled" bitfld.long 0x0 1. " ETHER_EN ,Ethernet Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Ethernet Controller Reset" "No reset,Reset" group 0x3040++0x3 line.long 0x0 "MII_DATA,FEC MII Management Frame" bitfld.long 0x0 30.--31. " ST ,Start of Frame Delimiter" "Not valid,Valid,Not valid,Not valid" bitfld.long 0x0 28.--29. " OP ,Operation Code" "00,01,10,11" textline " " hexmask.long 0x0 23.--27. 1. " PA ,PHY Address" hexmask.long.byte 0x0 18.--22. 1. " RA ,Register Address" textline " " bitfld.long 0x0 16.--17. " TA ,TurnAround" "Not valid,Not valid,Valid,Not valid" hexmask.long.word 0x0 0.--15. 1. " DATA ,Management Frame Data" group 0x3044++0x3 line.long 0x0 "MII_SPEED,FEC MII Speed Control" bitfld.long 0x0 7. " DIS_PREAMBLE ,Preamble (32 1s) not prepended to the MII management frame." "False,True" hexmask.long.byte 0x0 1.--6. 1. " MII_SPEED ,Frequency of the MII management interface clock" group 0x3064++0x3 line.long 0x0 "MIB_CONTROL,FEC MIB Control" bitfld.long 0x0 31. " MIB_DISABLE ,A read/write control bit" "Enabled,Disabled" bitfld.long 0x0 30. " MIB_IDLE ,A read-only status bit" "Busy,Idle" group 0x3084++0x3 line.long 0x0 "R_CNTRL,FEC Receive Control" hexmask.long.word 0x0 16.--26. 1. " MAX_FL ,Maximum Frame Length" bitfld.long 0x0 5. " FCE ,Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x0 3. " PROM ,Promiscuous mode" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " MII_MODE ,Selects external interface mode" "7 wire,MII" bitfld.long 0x0 1. " DRT ,Disable Receive on Transmit" "Enabled,Disabled" textline " " bitfld.long 0x0 0. " LOOP ,Internal Loopback" "Disabled,Enabled" rgroup 0x3088++0x3 line.long 0x0 "R_HASH,FEC Hash" bitfld.long 0x0 31. " FCE_DC ,Read-only view of the R_CNTRL register FCE bit" "Disabled,Enabled" bitfld.long 0x0 30. " MULTICAST ,Current Rx frame contained a multi-cast destination address" "Other,Multicast" textline " " hexmask.long.byte 0x0 24.--29. 1. " HASH ,Corresponds to hash value of current Rx frame's destination address" ;rgroup 0x309c++0x3 ; line.long 0x0 "R_DA_LOW,FEC Rx Destination Address Low" ; hexmask.long.long 0x0 0.--31. 1. " R_DA_LOW ,First 4Bytes of the receive frame" ;group 0x30a0++0x3 ; line.long 0x0 "R_DA_HIGH,FEC Rx Destination Address High" ; hexmask.long.word 0x0 16.--31. 1. " R_DA_HIGH ,Last 2Bytes of the receive frame" group 0x30c4++0x3 line.long 0x0 "X_CNTRL,FEC Tx Control" bitfld.long 0x0 4. " RFC_PAUSE ,Full duplex flow control pause frame is received" "Pending,Paused" bitfld.long 0x0 3. " TFC_PAUSE ,Transmit a PAUSE frame." "Pending,Paused" textline " " bitfld.long 0x0 2. " FDEN ,Full Duplex Enable." "Disabled,Enabled" bitfld.long 0x0 1. " HBC ,Heartbeat Control" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " GTS ,Graceful Transmit Stop" "Disabled,Enabled" ;rgroup 0x30d0++0x3 ; line.long 0x0 "XMIT.X_STATUS,FEC Tx Status" ; bitfld.long 0x0 25. " DEF ,Defer" "Not defered,Defered" ; bitfld.long 0x0 24. " HB ,Heartbeat Error" "No error,Error" ; bitfld.long 0x0 23. " LC ,Late Collision" "Not occurred,Occurred" ; textline " " ; bitfld.long 0x0 22. " RL ,Retry Limit" "No collision,No meaning" ; hexmask.long.byte 0x0 18.--21. 1. " RC ,Retry Count" ; bitfld.long 0x0 17. " UN ,Underrun" "Not occurred,Occurred" ; textline " " ; bitfld.long 0x0 16. " CSL ,Carrier Sense Lost" "Not occurred,Occurred" group 0x30e4++0x3 line.long 0x0 "PADDR1,FEC Physical Address Low" hexmask.long.long 0x0 0.--31. 1. " PADDR1 ,First 4Bytes of the 6-byte individual address in PAUSE frames" group 0x30e8++0x3 line.long 0x0 "PADDR2,FEC Physical Address High" hexmask.long.word 0x0 16.--31. 1. " PADDR2 ,Last 2Bytes of the 6-byte individual address in PAUSE frames" hexmask.long.word 0x0 0.--16. 1. " TYPE ,16bit constant value, hex 8808" group 0x30ec++0x3 line.long 0x0 "OP_PAUSE,FEC Opcode / Pause Duration" hexmask.long.word 0x0 16.--31. 1. " OPCODE ,Opcode field used in PAUSE frames" hexmask.long.word 0x0 0.--16. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames" group 0x3118++0x3 line.long 0x0 "IADDR1,FEC Descriptor Individual Address 1" hexmask.long.long 0x0 0.--31. 1. " IADDR1 ,The upper 32bits of the 64-bit hash table" group 0x311c++0x3 line.long 0x0 "IADDR2,FEC Descriptor Individual Address 2" hexmask.long.long 0x0 0.--31. 1. " IADDR2 ,The lower 32bits of the 64-bit hash table" group 0x3120++0x3 line.long 0x0 "GADDR1,FEC Descriptor Group Address 1" hexmask.long.long 0x0 0.--31. 1. " GADDR1 ,The upper 32bits of the 64-bit hash table" group 0x3124++0x3 line.long 0x0 "GADDR2,FEC Descriptor Group Address 2" hexmask.long.long 0x0 0.--31. 1. " GADDR2 ,The lower 32bits of the 64-bit hash table" group 0x3144++0x3 line.long 0x0 "X_WMRK,FEC Tx FIFO Watermark" bitfld.long 0x0 0.--3. " X_WMRK ,Transmit FIFO Watermark" "64 Bytes,128 Bytes,192 Bytes,256 Bytes,320 Bytes,384 Bytes,448 Bytes,512 Bytes,576 Bytes,640 Bytes,704 Bytes,768 Bytes,832 Bytes,896 Bytes,960 Bytes,1024 Bytes" hgroup 0x3184++0x3 hide.long 0x0 "RFDATA,FEC Rx FIFO Data" in rgroup 0x3188++0x3 line.long 0x0 "RFSTAT,FEC Rx FIFO Status" bitfld.long 0x0 27. " Frame[0] ,Frame Indicator" "Not occurred,Occurred" bitfld.long 0x0 26. " Frame[1] ,Frame Indicator" "Not occurred,Occurred" textline " " bitfld.long 0x0 25. " Frame[2] ,Frame Indicator" "Not occurred,Occurred" bitfld.long 0x0 24. " Frame[3] ,Frame Indicator" "Not occurred,Occurred" textline " " eventfld.long 0x0 22. " Error ,FIFO Error" "No error,Error" eventfld.long 0x0 21. " UF ,FIFO Underflow" "No underflow,Underflow" textline " " eventfld.long 0x0 20. " OF ,FIFO Overflow" "No overflow,Overflow" bitfld.long 0x0 19. " FR ,Frame Ready. Read Only" "Not ready,Ready" textline " " bitfld.long 0x0 18. " Full ,Full Alarm. Read Only" "No alarm,Alarm" bitfld.long 0x0 17. " Alarm ,FIFO Alarm. Read Only" "No alarm,Alarm" textline " " bitfld.long 0x0 16. " Empty ,Empty. Read Only" "Not empty,Empty" group 0x318c++0x3 line.long 0x0 "RFCNTL,FEC Rx FIFO Control" bitfld.long 0x0 29.--30. " WFR[1:0] ,Write Frame" "Reserved,Next to last write,Status,Reserved" bitfld.long 0x0 28. " COMP ,COMP Re-enable Requests on Frame Transmission Completion" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " FRAME ,Frame Mode Enable." "Disabled,Enabled" bitfld.long 0x0 24.--26. " GR ,Last Transfer Granularity." "0,1,2,3,4,5,6,7" group 0x3190++0x3 line.long 0x0 "RFLRFPTR,FEC Rx FIFO Last Read Frame PTR" hexmask.long.word 0x0 0.--9. 1. " LRFP[9:0] ,LRFP Last Read Frame Pointer" group 0x3194++0x3 line.long 0x0 "RFLWFPTR,FEC Rx FIFO Last Write Frame PTR" hexmask.long.word 0x0 0.--9. 1. " LWFP[9:0] ,LRFP Last Write Frame Pointer" group 0x3198++0x3 line.long 0x0 "RFALARM,FEC Rx FIFO Alarm Pointer" hexmask.long.word 0x0 0.--9. 1. " Alarm[9:0] ,Alarm Pointer" group 0x319c++0x3 line.long 0x0 "RFRPTR,FEC Rx FIFO Read Pointer" hexmask.long.word 0x0 0.--9. 1. " READ[9:0] ,Read Pointer" group 0x31a0++0x3 line.long 0x0 "RFWPTR,FEC Rx FIFO Write Pointer" hexmask.long.word 0x0 0.--9. 1. " WRITE[9:0] ,Write Pointer" hgroup 0x31a4++0x3 hide.long 0x0 "TFDATA,FEC Tx FIFO Data" in group 0x31a8++0x3 line.long 0x0 "TFSTAT,FEC Tx FIFO Status" bitfld.long 0x0 27. " Frame[0] ,Frame Indicator" "Not occurred,Occurred" bitfld.long 0x0 26. " Frame[1] ,Frame Indicator" "Not occurred,Occurred" textline " " bitfld.long 0x0 25. " Frame[2] ,Frame Indicator" "Not occurred,Occurred" bitfld.long 0x0 24. " Frame[3] ,Frame Indicator" "Not occurred,Occurred" textline " " eventfld.long 0x0 22. " Error ,FIFO Error" "No error,Error" eventfld.long 0x0 21. " UF ,FIFO Underflow" "No underflow,Underflow" textline " " eventfld.long 0x0 20. " OF ,FIFO Overflow" "No overflow,Overflow" bitfld.long 0x0 19. " FR ,Frame Ready. Read Only" "Not ready,Ready" textline " " bitfld.long 0x0 18. " Full ,Full Alarm. Read Only" "No alarm,Alarm" bitfld.long 0x0 17. " Alarm ,FIFO Alarm. Read Only" "No alarm,Alarm" textline " " bitfld.long 0x0 16. " Empty ,Empty. Read Only" "Not empty,Empty" group 0x31ac++0x3 line.long 0x0 "TFCNTL,FEC Tx FIFO Control" bitfld.long 0x0 29.--30. " WFR[1:0] ,Write Frame" "Reserved,Next to last write,Status,Reserved" bitfld.long 0x0 28. " COMP ,COMP Re-enable Requests on Frame Transmission Completion" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " FRAME ,Frame Mode Enable." "Disabled,Enabled" bitfld.long 0x0 24.--26. " GR ,Last Transfer Granularity." "0,1,2,3,4,5,6,7" group 0x31b0++0x3 line.long 0x0 "TFLRFPTR,FEC Tx FIFO Last Read Frame PTR" hexmask.long.word 0x0 0.--9. 1. " LRFP[9:0] ,LRFP Last Read Frame Pointer" group 0x31b4++0x3 line.long 0x0 "TFLWFPTR,FEC Tx FIFO Last Write Frame PTR" hexmask.long.word 0x0 0.--9. 1. " LWFP[9:0] ,LRFP Last Write Frame Pointer" group 0x31b8++0x3 line.long 0x0 "TFALARM,FEC Tx FIFO Alarm Pointer" hexmask.long.word 0x0 0.--9. 1. " Alarm[9:0] ,Alarm Pointer" group 0x31bc++0x3 line.long 0x0 "TFRPTR,FEC Tx FIFO Read Pointer" hexmask.long.word 0x0 0.--9. 1. " READ[9:0] ,Read Pointer" group 0x31c0++0x3 line.long 0x0 "TFWPTR,FEC Tx FIFO Write Pointer" hexmask.long.word 0x0 0.--9. 1. " WRITE[9:0] ,Write Pointer" group 0x31c4++0x3 line.long 0x0 "RCNTL,FEC Reset Control Register" bitfld.long 0x0 25. " RCTL[1] ,Reset FIFO controllers" "No reset,Reset" bitfld.long 0x0 24. " RCTL[0] ,fec_enable as a reset to FIFO controllers" "Disabled,Enabled" group 0x31c8++0x3 line.long 0x0 "TFSM,FEC Transmit FSM Register" bitfld.long 0x0 25. " XFSM[1] ,Append CRC" "Not appended,Appended" bitfld.long 0x0 24. " XFSM[0] ,Enable CRC FSM" "Disabled,Enabled" width 0xb tree.end tree "MIB Block Counters" width 20. group 0x3200++0x3 line.long 0x0 "RMON_T_DROP, Count of Frames Not Correctly Counted" group 0x3204++0x3 line.long 0x0 "RMON_T_PACKETS, RMON Tx Packet Count" group 0x3208++0x3 line.long 0x0 "RMON_T_BC_PKT, RMON Tx Broadcast Packets" group 0x320c++0x3 line.long 0x0 "RMON_T_MC_PKT, RMON Tx Multicast Packets" group 0x3210++0x3 line.long 0x0 "RMON_T_CRC_ALIGN, RMON Tx Packets with CRC/Align error" group 0x3214++0x3 line.long 0x0 "RMON_T_UNDERSIZE, RMON Tx Packets less than 64bytes, good CRC" group 0x3218++0x3 line.long 0x0 "RMON_T_OVERSIZE, RMON Tx Packets greater than MAX_FL bytes, good CRC" group 0x321c++0x3 line.long 0x0 "RMON_T_FRAG, RMON Tx Packets less than 64bytes, bad CRC" group 0x3220++0x3 line.long 0x0 "RMON_T_JAB, RMONTxPackets greater than MAX_FL bytes, bad CRC" group 0x3224++0x3 line.long 0x0 "RMON_T_COL, RMON Tx collision count" group 0x3228++0x3 line.long 0x0 "RMON_T_P64, RMON Tx 64Byte packets" group 0x322c++0x3 line.long 0x0 "RMON_T_P65TO127, RMON Tx 65 to 127Byte packets" group 0x3230++0x3 line.long 0x0 "RMON_T_P128TO255, RMON Tx 128 to 255Byte packets" group 0x3234++0x3 line.long 0x0 "RMON_T_P256TO511, RMON Tx 256 to 511Byte packets" group 0x3238++0x3 line.long 0x0 "RMON_T_P512TO1023, RMON Tx 512 to 1023Byte packets" group 0x323c++0x3 line.long 0x0 "RMON_T_P1024TO2047, RMON Tx 1024 to 2047Byte packets" group 0x3240++0x3 line.long 0x0 "RMON_T_P_GTE2048, RMON Tx packets with greater than 2048Bytes" group 0x3244++0x3 line.long 0x0 "RMON_T_OCTETS, RMON Tx Octets" group 0x3248++0x3 line.long 0x0 "IEEE_T_DROP, Count of Frames Not Counted Correctly" group 0x324c++0x3 line.long 0x0 "IEEE_T_FRAME_OK, Frames Transmitted OK" group 0x3250++0x3 line.long 0x0 "IEEE_T_1COL, Frames Transmitted with Single Collision" group 0x3254++0x3 line.long 0x0 "IEEE_T_MCOL, Frames Transmitted with Multiple Collisions" group 0x3258++0x3 line.long 0x0 "IEEE_T_DEF, Frames Transmitted after Deferral Delay" group 0x325c++0x3 line.long 0x0 "IEEE_T_LCOL, Frames Transmitted with Late Collision" group 0x3260++0x3 line.long 0x0 "IEEE_T_EXCOL, Frames Transmitted with Excessive Collisions" group 0x3264++0x3 line.long 0x0 "IEEE_T_MACERR, Frames Transmitted with Tx FIFO Underrun" group 0x3268++0x3 line.long 0x0 "IEEE_T_CSERR, Frames Transmitted with Carrier Sense Error" group 0x326c++0x3 line.long 0x0 "IEEE_T_SQE, Frames Transmitted with SQE Error" group 0x3270++0x3 line.long 0x0 "T_FDXFC, Flow Control Pause Frames Transmitted" group 0x3274++0x3 line.long 0x0 "IEEE_T_OCTETS_OK, Octet Count for Frames Transmitted w/o Error" group 0x3280++0x3 line.long 0x0 "RMON_R_DROP, Count of frames Not Counted Correctly" group 0x3284++0x3 line.long 0x0 "RMON_R_PACKETS, RMON Rx Packet Count" group 0x3288++0x3 line.long 0x0 "RMON_R_BC_PKT, RMON Rx Broadcast Packets" group 0x328c++0x3 line.long 0x0 "RMON_R_MC_PKT, RMON Rx Multicast Packets" group 0x3290++0x3 line.long 0x0 "RMON_R_CRC_ALIGN, RMON Rx Packets with CRC/Align error" group 0x3294++0x3 line.long 0x0 "RMON_R_UNDERSIZE, RMON Rx Packets less than 64Bytes, good CRC" group 0x3298++0x3 line.long 0x0 "RMON_R_OVERSIZE, RMON Rx Packets greater than MAX_FL bytes, good CRC" group 0x329c++0x3 line.long 0x0 "RMON_R_FRAG, RMON Rx Packets less than 64Bytes, bad CRC" group 0x32a0++0x3 line.long 0x0 "RMON_R_JAB, RMONRxPackets greater than MAX_FL bytes, bad CRC" group 0x32a8++0x3 line.long 0x0 "RMON_R_P64, RMON Rx 64Byte packets" group 0x32ac++0x3 line.long 0x0 "RMON_R_P65TO127, RMON Rx 65 to 127Byte packets" group 0x32b0++0x3 line.long 0x0 "RMON_R_P128TO255, RMON Rx 128 to 255Byte packets" group 0x32b4++0x3 line.long 0x0 "RMON_R_P256TO511, RMON Rx 256 to 511Byte packets" group 0x32b8++0x3 line.long 0x0 "RMON_R_P512TO1023, RMON Rx 512 to 1023Byte packets" group 0x32bc++0x3 line.long 0x0 "RMON_R_P1024TO2047, RMON Rx 1024 to 2047Byte packets" group 0x32c0++0x3 line.long 0x0 "RMON_R_P_GTE2048, RMON Rx packets with greater than 2048Bytes" group 0x32c4++0x3 line.long 0x0 "RMON_R_OCTETS, RMON Rx Octets" group 0x32c8++0x3 line.long 0x0 "IEEE_R_DROP, Count of frames not counted correctly" group 0x32cc++0x3 line.long 0x0 "IEEE_R_FRAME_OK, Frames received OK" group 0x32d0++0x3 line.long 0x0 "IEEE_R_CRC, Frames received with CRC error" group 0x32d4++0x3 line.long 0x0 "IEEE_R_ALIGN, Frames received with alignment error" group 0x32d8++0x3 line.long 0x0 "IEEE_R_MACERR, Rx FIFO overflow count" group 0x32dc++0x3 line.long 0x0 "R_FDXFC, Flow Control Pause frames received" group 0x32e0++0x3 line.long 0x0 "IEEE_R_OCTETS_OK, Octet count for frames received without error" tree.end tree.end tree "GPIO Standard/WakeUp Registers (MBAR + 0x0B00/0x0C00)" width 10. sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0xb00++0x3 "GPIO Registers (MBAR + 0B00)" line.long 0x0 "GPIOPCR,Port Configuration Register" bitfld.long 0x0 31. " CS1 ,Memory Chip Select bit" "GPIO_wkup_6,MEM_cs1" textline " " bitfld.long 0x0 30. " LPTZ ,LocalPlus non-muxed TSIZ bit" "GPIO_wkup_7 and test_sel_1,TSIZ 1 (gpio_wkup_7)/TSIZ 2 (test_sel_1)" textline " " bitfld.long 0x0 28.--29. " ALTs ,Alternatives" "None,CAN,SPI,CAN&SPI" bitfld.long 0x0 27. " CS7 ," "GPIO Interrupted,CS7" textline " " bitfld.long 0x0 26. " CS6 ," "GPIO Interrupted,CS6" bitfld.long 0x0 24.--25. " ATA ,Advanced Technology Attachment" "No ATA chip selects,ATA cs0/1 on csb_4/5,ATA cs0/1 on i2c2 clk/io,ATA cs0/1 on Tmr0/1" textline " " bitfld.long 0x0 23. " IR_USB_CLK ,Infrared USB Clock" "48MHz,External" bitfld.long 0x0 20.--22. " IRDA ,Infrared Data Association" "All GPIO,Reserved,Reserved,Reserved,Reserved,UART(without CD)/IrDA,Reserved,CODEC(without MCLK)/IrDA" textline " " bitfld.long 0x0 16.--19. " Ether ,Ethernet" "All GPIO,USB2,Eth 10MBit(7-wire),Eth (7-wire) & USB2,Eth 100MBit w/o MD,Eth. 100MBit w MD,Reserved,Reserved,Eth 7-wire/UARTe/J1850,Eth 7-wire/J1850,Two UARTes/J1850,One UARTe/J1850,J1850,Reserved,Reserved,Reserved" bitfld.long 0x0 15. " PCI_DIS ,PCI controller disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 14. " USB_SE ,USB Single Ended mode" "Differential,Single ended" bitfld.long 0x0 12.--13. " USB ,USB" "All GPIO,USB,two UARTs,Reserved" textline " " bitfld.long 0x0 8.--11. " PSC3 ,Programmable Serial Controller 3" "All GPIO,USB2,Reserved,Reserved,UART w/o CD,UART w CD,CODEC3 w/o MCLK,CODEC3 w MCLK,SPI,SPI,Reserved,Reserved,SPI w UART3,SPI w UART3e,SPI w CODEC3,SPI w CODEC3" bitfld.long 0x0 4.--6. " PSC2 ,Programmable Serial Controller 2" "All GPIO,CAN1&2,AC97,AC97,UART w/o CD,UART w CD,CODEC2 w/o MCLK,CODEC2 w MCLK" textline " " bitfld.long 0x0 0.--2. " PSC1 ,Programmable Serial Controller 1" "All GPIO,All GPIO,AC97,AC97,UART w/o CD,UARTe w CD,CODEC1 w/o MCLK,CODEC1 w MCLK" else group 0xb00++0x3 "GPIO Registers (MBAR + 0B00)" line.long 0x0 "GPIOPCR,Port Configuration Register" bitfld.long 0x0 31. " CS1 ,Memory Chip Select bit" "GPIO_wkup_6,MEM_cs1" textline " " bitfld.long 0x0 28.--29. " ALTs ,Alternatives" "None,CAN,SPI,CAN&SPI" bitfld.long 0x0 27. " CS7 ," "GPIO Interrupted,CS7" textline " " bitfld.long 0x0 26. " CS6 ," "GPIO Interrupted,CS6" bitfld.long 0x0 24.--25. " ATA ,Advanced Technology Attachment" "No ATA chip selects,ATA cs0/1 on csb_4/5,ATA cs0/1 on i2c2 clk/io,ATA cs0/1 on Tmr0/1" textline " " bitfld.long 0x0 23. " IR_USB_CLK ,Infrared USB Clock" "48MHz,External" bitfld.long 0x0 20.--22. " IRDA ,Infrared Data Association" "All GPIO,Reserved,Reserved,Reserved,Reserved,UART(without CD)/IrDA,Reserved,CODEC(without MCLK)/IrDA" textline " " bitfld.long 0x0 16.--19. " Ether ,Ethernet" "All GPIO,USB2,Eth 10MBit(7-wire),Eth (7-wire) & USB2,Eth 100MBit w/o MD,Eth. 100MBit w MD,Reserved,Reserved,Eth 7-wire/UARTe/J1850,Eth 7-wire/J1850,Two UARTes/J1850,One UARTe/J1850,J1850,Reserved,Reserved,Reserved" bitfld.long 0x0 15. " PCI_DIS ,PCI controller disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 14. " USB_SE ,USB Single Ended mode" "Differential,Single ended" bitfld.long 0x0 12.--13. " USB ,USB" "All GPIO,USB,two UARTs,Reserved" textline " " bitfld.long 0x0 8.--11. " PSC3 ,Programmable Serial Controller 3" "All GPIO,USB2,Reserved,Reserved,UART w/o CD,UART w CD,CODEC3 w/o MCLK,CODEC3 w MCLK,SPI,SPI,Reserved,Reserved,SPI w UART3,SPI w UART3e,SPI w CODEC3,SPI w CODEC3" bitfld.long 0x0 4.--6. " PSC2 ,Programmable Serial Controller 2" "All GPIO,CAN1&2,AC97,AC97,UART w/o CD,UART w CD,CODEC2 w/o MCLK,CODEC2 w MCLK" textline " " bitfld.long 0x0 0.--2. " PSC1 ,Programmable Serial Controller 1" "All GPIO,All GPIO,AC97,AC97,UART w/o CD,UARTe w CD,CODEC1 w/o MCLK,CODEC1 w MCLK" endif elif (cpu()=="MGT5100") group 0xb00++0x3 "GPIO Registers (MBAR + 0B00)" line.long 0x0 "GPIOPCR,Port Configuration Register" bitfld.long 0x0 31. " CS1 ,Memory Chip Select bit" "GPIO_wkup_6,MEM_cs1" textline " " bitfld.long 0x0 28.--29. " ALTs ,Alternatives" "None,CAN,SPI,CAN&SPI" bitfld.long 0x0 27. " CS7 ," "GPIO Interrupted,CS7" textline " " bitfld.long 0x0 26. " CS6 ," "GPIO Interrupted,CS6" bitfld.long 0x0 24.--25. " ATA ,Advanced Technology Attachment" "No ATA chip selects,ATA cs0/1 on csb_4/5,ATA cs0/1 on i2c2 clk/io,ATA cs0/1 on Tmr0/1" textline " " bitfld.long 0x0 23. " IR_USB_CLK ,Infrared USB Clock" "48MHz,External" bitfld.long 0x0 20.--22. " IRDA ,Infrared Data Association" "All GPIO,Reserved,Reserved,Reserved,Reserved,UART(without CD)/IrDA,Reserved,CODEC(without MCLK)/IrDA" textline " " bitfld.long 0x0 16.--19. " Ether ,Ethernet" "All GPIO,USB2,Eth 10MBit(7-wire),Eth (7-wire) & USB2,Eth 100MBit w/o MD,Eth. 100MBit w MD,Reserved,Reserved,Eth 7-wire/UARTe/J1850,Eth 7-wire/J1850,Two UARTes/J1850,One UARTe/J1850,J1850,Reserved,Reserved,Reserved" bitfld.long 0x0 15. " PCI_DIS ,PCI controller disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 14. " USB_SE ,USB Single Ended mode" "Differential,Single ended" bitfld.long 0x0 12.--13. " USB ,USB" "All GPIO,USB,two UARTs,Reserved" textline " " bitfld.long 0x0 8.--11. " PSC3 ,Programmable Serial Controller 3" "All GPIO,USB2,Reserved,Reserved,UART w/o CD,UART w CD,CODEC3 w/o MCLK,CODEC3 w MCLK,SPI,SPI,Reserved,Reserved,SPI w UART3,SPI w UART3e,SPI w CODEC3,SPI w CODEC3" bitfld.long 0x0 4.--6. " PSC2 ,Programmable Serial Controller 2" "All GPIO,CAN1&2,AC97,AC97,UART w/o CD,UART w CD,CODEC2 w/o MCLK,CODEC2 w MCLK" textline " " bitfld.long 0x0 0.--2. " PSC1 ,Programmable Serial Controller 1" "All GPIO,All GPIO,AC97,AC97,UART w/o CD,UARTe w CD,CODEC1 w/o MCLK,CODEC1 w MCLK" endif group 0xb04++0x3 line.long 0x0 "GPIOSEN,Simple GPIO Enables" bitfld.long 0x0 29. " IRDA[1] ,Simple GPIO on IRDA_1 port" "Disabled,Enabled" bitfld.long 0x0 28. " IRDA[0] ,Simple GPIO on IRDA_0 port" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " ETHR[3] ,Simple GPIO on ETHR_3 port" "Disabled,Enabled" bitfld.long 0x0 26. " ETHR[2] ,Simple GPIO on ETHR_2 port" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " ETHR[1] ,Simple GPIO on ETHR_1 port" "Disabled,Enabled" bitfld.long 0x0 24. " ETHR[0] ,Simple GPIO on ETHR_0 port" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " USB[3] ,Simple GPIO on USB_3 port" "Disabled,Enabled" bitfld.long 0x0 18. " USB[2] ,Simple GPIO on USB_2 port" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " USB[1] ,Simple GPIO on USB_1 port" "Disabled,Enabled" bitfld.long 0x0 16. " USB[0] ,Simple GPIO on USB_0 port" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " PSC3[5] ,Simple GPIO on PSC3_5 port" "Disabled,Enabled" bitfld.long 0x0 12. " PSC3[4] ,Simple GPIO on PSC3_4 port" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " PSC3[3] ,Simple GPIO on PSC3_3 port" "Disabled,Enabled" bitfld.long 0x0 10. " PSC3[2] ,Simple GPIO on PSC3_2 port" "Disabled,Enabled" textline " " bitfld.long 0x0 9. " PSC3[1] ,Simple GPIO on PSC3_1 port" "Disabled,Enabled" bitfld.long 0x0 8. " PSC3[0] ,Simple GPIO on PSC3_0 port" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " PSC2[3] ,Simple GPIO on PSC2_3 port" "Disabled,Enabled" bitfld.long 0x0 6. " PSC2[2] ,Simple GPIO on PSC2_2 port" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " PSC2[1] ,Simple GPIO on PSC2_1 port" "Disabled,Enabled" bitfld.long 0x0 4. " PSC2[0] ,Simple GPIO on PSC2_0 port" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PSC1[3] ,Simple GPIO on PSC1_3 port" "Disabled,Enabled" bitfld.long 0x0 2. " PSC1[2] ,Simple GPIO on PSC1_2 port" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " PSC1[1] ,Simple GPIO on PSC1_1 port" "Disabled,Enabled" bitfld.long 0x0 0. " PSC1[0] ,Simple GPIO on PSC1_0 port" "Disabled,Enabled" group 0xb08++0x3 line.long 0x0 "GPIOSOD,Simple GPIO Open Drain Type" bitfld.long 0x0 29. " IRDA[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 28. " IRDA[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 27. " ETHR[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 26. " ETHR[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 25. " ETHR[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 24. " ETHR[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 19. " USB[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 18. " USB[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 17. " USB[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 16. " USB[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 13. " PSC3[5] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 12. " PSC3[4] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 11. " PSC3[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 10. " PSC3[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 9. " PSC3[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 8. " PSC3[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 7. " PSC2[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 6. " PSC2[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 5. " PSC2[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 4. " PSC2[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 3. " PSC1[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 2. " PSC1[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 1. " PSC1[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 0. " PSC1[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" group 0xb0c++0x3 line.long 0x0 "GPIOSDD,Simple GPIO Data Direction" bitfld.long 0x0 29. " IRDA[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 28. " IRDA[0] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 27. " ETHR[3] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 26. " ETHR[2] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 25. " ETHR[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 24. " ETHR[0] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 19. " USB[3] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 18. " USB[2] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 17. " USB[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 16. " USB[0] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 13. " PSC3[5] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 12. " PSC3[4] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 11. " PSC3[3] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 10. " PSC3[2] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 9. " PSC3[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 8. " PSC3[0] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 7. " PSC2[3] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 6. " PSC2[2] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 5. " PSC2[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 4. " PSC2[0] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 3. " PSC1[3] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 2. " PSC1[2] ,Control directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 1. " PSC1[1] ,Control directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 0. " PSC1[0] ,Control directionality of the pin as GPIO" "Input,Output" group 0xb10++0x3 line.long 0x0 "GPIOSDO,Simple GPIO Data Output Values" bitfld.long 0x0 29. " IRDA[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 28. " IRDA[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " ETHR[3] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 26. " ETHR[2] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " ETHR[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 24. " ETHR[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 19. " USB[3] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 18. " USB[2] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 17. " USB[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 16. " USB[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 13. " PSC3[5] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 12. " PSC3[4] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 11. " PSC3[3] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 10. " PSC3[2] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 9. " PSC3[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 8. " PSC3[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 7. " PSC2[3] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 6. " PSC2[2] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 5. " PSC2[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 4. " PSC2[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 3. " PSC1[3] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 2. " PSC1[2] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 1. " PSC1[1] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 0. " PSC1[0] ,Control the state of pins configured as GPIO output" "Drive 0,Drive 1" rgroup 0xb14++0x3 line.long 0x0 "GPIOSDI,Simple GPIO Data Input Values" bitfld.long 0x0 29. " IRDA[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 28. " IRDA[0] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 27. " ETHR[3] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 26. " ETHR[2] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 25. " ETHR[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 24. " ETHR[0] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 19. " USB[3] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 18. " USB[2] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 17. " USB[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 16. " USB[0] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 13. " PSC3[5] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 12. " PSC3[4] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 11. " PSC3[3] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 10. " PSC3[2] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 9. " PSC3[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 8. " PSC3[0] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 7. " PSC2[3] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 6. " PSC2[2] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 5. " PSC2[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 4. " PSC2[0] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 3. " PSC1[3] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 2. " PSC1[2] ,State of corresponding GPIO pins" "Low,High" textline " " bitfld.long 0x0 1. " PSC1[1] ,State of corresponding GPIO pins" "Low,High" bitfld.long 0x0 0. " PSC1[0] ,State of corresponding GPIO pins" "Low,High" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0xb18++0x3 line.long 0x0 "GPIOOE,Output-Only Enables" bitfld.long 0x0 31. " ETHR[7] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 30. " ETHR[6] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " ETHR[5] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 28. " ETHR[4] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " ETHR[3] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 26. " ETHR[2] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " ETHR[1] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 24. " ETHR[0] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " I2C2_CLK ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 18. " I2C2_IO ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " I2C1_CLK ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 16. " I2C1_IO ,Enable Output Only GPIO pin" "Disabled,Enabled" else group 0xb18++0x3 line.long 0x0 "GPIOOE,Output-Only Enables" bitfld.long 0x0 31. " ETHR[7] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 30. " ETHR[6] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " ETHR[5] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 28. " ETHR[4] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " ETHR[3] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 26. " ETHR[2] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " ETHR[1] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 24. " ETHR[0] ,Enable Output Only GPIO pin" "Disabled,Enabled" endif elif (cpu()=="MGT5100") group 0xb18++0x3 line.long 0x0 "GPIOOE,Output-Only Enables" bitfld.long 0x0 31. " ETHR[7] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 30. " ETHR[6] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " ETHR[5] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 28. " ETHR[4] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " ETHR[3] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 26. " ETHR[2] ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " ETHR[1] ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 24. " ETHR[0] ,Enable Output Only GPIO pin" "Disabled,Enabled" endif sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0xb1c++0x3 line.long 0x0 "GPIOODO,Output-Only Data Value Out" bitfld.long 0x0 31. " ETHR[7] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 30. " ETHR[6] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 29. " ETHR[5] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 28. " ETHR[4] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " ETHR[3] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 26. " ETHR[2] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " ETHR[1] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 24. " ETHR[0] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 19. " I2C2_CLK ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 18. " I2C2_IO ,Enable Output Only GPIO pin" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " I2C1_CLK ,Enable Output Only GPIO pin" "Disabled,Enabled" bitfld.long 0x0 16. " I2C1_IO ,Enable Output Only GPIO pin" "Disabled,Enabled" else group 0xb1c++0x3 line.long 0x0 "GPIOODO,Output-Only Data Value Out" bitfld.long 0x0 31. " ETHR[7] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 30. " ETHR[6] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 29. " ETHR[5] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 28. " ETHR[4] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " ETHR[3] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 26. " ETHR[2] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " ETHR[1] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 24. " ETHR[0] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" endif elif (cpu()=="MGT5100") group 0xb1c++0x3 line.long 0x0 "GPIOODO,Output-Only Data Value Out" bitfld.long 0x0 31. " ETHR[7] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 30. " ETHR[6] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 29. " ETHR[5] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 28. " ETHR[4] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " ETHR[3] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 26. " ETHR[2] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " ETHR[1] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" bitfld.long 0x0 24. " ETHR[0] ,Control the state of enabled Output Only GPIO pins" "Drive 0,Drive 1" endif group 0xb20++0x3 line.long 0x0 "GPIOSIE,Simple Interrupt Enables" bitfld.long 0x0 31. " SIGPIOE[7] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" bitfld.long 0x0 30. " SIGPIOE[6] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " SIGPIOE[5] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" bitfld.long 0x0 28. " SIGPIOE[4] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " SIGPIOE[3] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" bitfld.long 0x0 26. " SIGPIOE[2] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " SIGPIOE[1] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" bitfld.long 0x0 24. " SIGPIOE[0] ,Enable each Interrupt GPIO pin (pins are scattered)" "Disabled,Enabled" group 0xb24++0x3 line.long 0x0 "GPIOSIOD,Simple Interrupt Open-Drain Emulation" bitfld.long 0x0 31. " SIODe[7] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 30. " SIODe[6] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 29. " SIODe[5] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 28. " SIODe[4] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 27. " SIODe[3] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 26. " SIODe[2] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" textline " " bitfld.long 0x0 25. " SIODe[1] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" bitfld.long 0x0 24. " SIODe[0] ,Open drain emulation for pins configured as GPIO output" "Normal,Open drain" group 0xb28++0x3 line.long 0x0 "GPIOSIDD,Simple Interrupt Data Direction" bitfld.long 0x0 31. " SIDDR[7] ,Control direction of the pin as GPIO" "Input,Output" bitfld.long 0x0 30. " SIDDR[6] ,Control direction of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 29. " SIDDR[5] ,Control direction of the pin as GPIO" "Input,Output" bitfld.long 0x0 28. " SIDDR[4] ,Control direction of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 27. " SIDDR[3] ,Control direction of the pin as GPIO" "Input,Output" bitfld.long 0x0 26. " SIDDR[2] ,Control direction of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 25. " SIDDR[1] ,Control direction of the pin as GPIO" "Input,Output" bitfld.long 0x0 24. " SIDDR[0] ,Control direction of the pin as GPIO" "Input,Output" group 0xb2c++0x3 line.long 0x0 "GPIOSIDO,Simple Interrupt Data Value Out" bitfld.long 0x0 31. " SIDVO[7] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 30. " SIDVO[6] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 29. " SIDVO[5] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 28. " SIDVO[4] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " SIDVO[3] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 26. " SIDVO[2] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " SIDVO[1] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 24. " SIDVO[0] ,State of pins configured as GPIO output" "Drive 0,Drive 1" group 0xb30++0x3 line.long 0x0 "GPIOSIIE,Simple Interrupt Interrupt Enable" bitfld.long 0x0 31. " SIINTEN[7] ,Interrupt generation for each GPIO pin configured as an Input" "No interrupt,Interrupt" bitfld.long 0x0 30. " SIINTEN[6] ,Interrupt generation for each GPIO pin configured as an Input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 29. " SIINTEN[5] ,Interrupt generation for each GPIO pin configured as an Input" "No interrupt,Interrupt" bitfld.long 0x0 28. " SIINTEN[4] ,Interrupt generation for each GPIO pin configured as an Input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 27. " SIINTEN[3] ,Interrupt generation for each GPIO pin configured as an Input" "No interupt,Interupt" bitfld.long 0x0 26. " SIINTEN[2] ,Interrupt generation for each GPIO pin configured as an Input" "No interupt,Interupt" textline " " bitfld.long 0x0 25. " SIINTEN[1] ,Interrupt generation for each GPIO pin configured as an Input" "No interupt,Interupt" bitfld.long 0x0 24. " SIINTEN[0] ,Interrupt generation for each GPIO pin configured as an Input" "No interupt,Interupt" group 0xb34++0x3 line.long 0x0 "GPIOSIIT,Simple Interrupt Interrupt Types" bitfld.long 0x0 30.--31. " ITYP7 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 7" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 28.--29. " ITYP6 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 6" "Transition,Rising,Falling,Pulse" textline " " bitfld.long 0x0 26.--27. " ITYP5 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 5" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 24.--25. " ITYP4 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 4" "Transition,Rising,Falling,Pulse" textline " " bitfld.long 0x0 22.--23. " ITYP3 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 3" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 20.--21. " ITYP2 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 2" "Transition,Rising,Falling,Pulse" textline " " bitfld.long 0x0 18.--19. " ITYP1 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 1" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 16.--17. " ITYP0 ,GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 0" "Transition,Rising,Falling,Pulse" group 0xb38++0x3 line.long 0x0 "GPIOSIME,Simple Interrupt Master Enable" bitfld.long 0x0 28. " ME ,GPIO Simple Interrupt Master Enable pin" "Disabled,Enabled" group 0xb3c++0x3 line.long 0x0 "GPIOSIST,Simple Interrupt Status" eventfld.long 0x0 31. " ISTAT[7] ,Interrupt Status" "Not occurred,Occurred" eventfld.long 0x0 30. " ISTAT[6] ,Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x0 29. " ISTAT[5] ,Interrupt Status" "Not occurred,Occurred" eventfld.long 0x0 28. " ISTAT[4] ,Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x0 27. " ISTAT[3] ,Interrupt Status" "Not occurred,Occurred" eventfld.long 0x0 26. " ISTAT[2] ,Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x0 25. " ISTAT[1] ,Interrupt Status" "Not occurred,Occurred" eventfld.long 0x0 24. " ISTAT[0] ,Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x0 23. " IVAL[7] ,Input Value" "Low,High" bitfld.long 0x0 22. " IVAL[6] ,Input Value" "Low,High" textline " " bitfld.long 0x0 21. " IVAL[5] ,Input Value" "Low,High" bitfld.long 0x0 20. " IVAL[4] ,Input Value" "Low,High" textline " " bitfld.long 0x0 19. " IVAL[3] ,Input Value" "Low,High" bitfld.long 0x0 18. " IVAL[2] ,Input Value" "Low,High" textline " " bitfld.long 0x0 17. " IVAL[1] ,Input Value" "Low,High" bitfld.long 0x0 16. " IVAL[0] ,Input Value" "Low,High" group 0xc00++0x3 "GPIO Wakeup Registers (MBAR + 0C00)" line.long 0x0 "GPIOWE,WakeUp GPIO Enables" bitfld.long 0x0 31. " WGPIOe[7] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" bitfld.long 0x0 30. " WGPIOe[6] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " WGPIOe[5] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" bitfld.long 0x0 28. " WGPIOe[4] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " WGPIOe[3] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" bitfld.long 0x0 26. " WGPIOe[2] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " WGPIOe[1] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" bitfld.long 0x0 24. " WGPIOe[0] ,Enable the operation of individual WaleUp GPIO pins" "Disabled,Enabled" group 0xc04++0x3 line.long 0x0 "GPIOWOD,WakeUp GPIO Open Drain Emulation" bitfld.long 0x0 31. " WODe[7] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" bitfld.long 0x0 30. " WODe[6] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" textline " " bitfld.long 0x0 29. " WODe[5] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" bitfld.long 0x0 28. " WODe[4] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" textline " " bitfld.long 0x0 27. " WODe[3] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" bitfld.long 0x0 26. " WODe[2] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" textline " " bitfld.long 0x0 25. " WODe[1] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" bitfld.long 0x0 24. " WODe[0] ,Open drain emulation for individual WakeUp GPIO configured as outputs" "Normal,Open drain" group 0xc08++0x3 line.long 0x0 "GPIOWDD,WakeUp GPIO Data Direction" bitfld.long 0x0 31. " WDDR[7] ,Directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 30. " WDDR[6] ,Directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 29. " WDDR[5] ,Directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 28. " WDDR[4] ,Directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 27. " WDDR[3] ,Directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 26. " WDDR[2] ,Directionality of the pin as GPIO" "Input,Output" textline " " bitfld.long 0x0 25. " WDDR[1] ,Directionality of the pin as GPIO" "Input,Output" bitfld.long 0x0 24. " WDDR[0] ,Directionality of the pin as GPIO" "Input,Output" group 0xc0c++0x3 line.long 0x0 "GPIOWDO,WakeUp GPIO Data Value Out" bitfld.long 0x0 31. " WDVO[7] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 30. " WDVO[6] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 29. " WDVO[5] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 28. " WDVO[4] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 27. " WDVO[3] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 26. " WDVO[2] ,State of pins configured as GPIO output" "Drive 0,Drive 1" textline " " bitfld.long 0x0 25. " WDVO[1] ,State of pins configured as GPIO output" "Drive 0,Drive 1" bitfld.long 0x0 24. " WDVO[0] ,State of pins configured as GPIO output" "Drive 0,Drive 1" group 0xc10++0x3 line.long 0x0 "GPIOWUE,WakeUp GPIO Interrupt Enable" bitfld.long 0x0 31. " WUPe[7] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 30. " WUPe[6] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 29. " WUPe[5] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 28. " WUPe[4] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 27. " WUPe[3] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 26. " WUPe[2] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 25. " WUPe[1] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 24. " WUPe[0] ,Generation of WakeUp interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" group 0xc14++0x3 line.long 0x0 "GPIOWSIE,WakeUp GPIO Simple Interrupt Enable" bitfld.long 0x0 31. " WINe[7] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 30. " WINe[6] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 29. " WINe[5] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 28. " WINe[4] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 27. " WINe[3] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 26. " WINe[2] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" textline " " bitfld.long 0x0 25. " WINe[1] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" bitfld.long 0x0 24. " WINe[0] ,Generation of Simple interrupt for WakeUp GPIO configured as input" "No interrupt,Interrupt" group 0xc18++0x3 line.long 0x0 "GPIOWT,WakeUp GPIO Interrupt Types" bitfld.long 0x0 30.--31. " ITYP7 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp GPIO" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 28.--29. " ITYP6 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp GPIO" "Transition,Rising,Falling,Pulse" textline " " bitfld.long 0x0 26.--27. " ITYP5 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp GPIO" "Transition,Rising,Falling,Pulse" bitfld.long 0x0 24.--25. " ITYP4 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp GPIO" "Transition,Rising,Falling,Pulse" textline " " bitfld.long 0x0 22.--23. " ITYP3 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp/Deep Sleep Mode GPIO" "Transition/Not valid,Rising/Level high,Falling/Lewel low,Pulse/Not valid" bitfld.long 0x0 20.--21. " ITYP2 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp/Deep Sleep Mode GPIO" "Transition/Not valid,Rising/Level high,Falling/Lewel low,Pulse/Not valid" textline " " bitfld.long 0x0 18.--19. " ITYP1 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp/Deep Sleep Mode GPIO" "Transition/Not valid,Rising/Level high,Falling/Lewel low,Pulse/Not valid" bitfld.long 0x0 16.--17. " ITYP0 ,GPIO Interrupt Type bits for Simple Interrupt WakeUp/Deep Sleep Mode GPIO" "Transition/Not valid,Rising/Level high,Falling/Lewel low,Pulse/Not valid" group 0xc1c++0x3 line.long 0x0 "GPIOWME,WakeUp GPIO Master Enables" bitfld.long 0x0 24. " ME ,WakeUp GPIO Master Enable pin" "Disabled,Enabled" rgroup 0xc20++0x3 line.long 0x0 "GPIOWI,WakeUp GPIO Data Input Values" bitfld.long 0x0 31. " WIVAL[7] ,Input Value bits for GPIO WakeUp pins" "Low,High" bitfld.long 0x0 30. " WIVAL[6] ,Input Value bits for GPIO WakeUp pins" "Low,High" textline " " bitfld.long 0x0 29. " WIVAL[5] ,Input Value bits for GPIO WakeUp pins" "Low,High" bitfld.long 0x0 28. " WIVAL[4] ,Input Value bits for GPIO WakeUp pins" "Low,High" textline " " bitfld.long 0x0 27. " WIVAL[3] ,Input Value bits for GPIO WakeUp pins" "Low,High" bitfld.long 0x0 26. " WIVAL[2] ,Input Value bits for GPIO WakeUp pins" "Low,High" textline " " bitfld.long 0x0 25. " WIVAL[1] ,Input Value bits for GPIO WakeUp pins" "Low,High" bitfld.long 0x0 24. " WIVAL[0] ,Input Value bits for GPIO WakeUp pins" "Low,High" group 0xc24++0x3 line.long 0x0 "GPIOWS,WakeUp GPIO Status Register" eventfld.long 0x0 31. " Istat[7] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" eventfld.long 0x0 30. " Istat[6] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" textline " " eventfld.long 0x0 29. " Istat[5] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" eventfld.long 0x0 28. " Istat[4] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" textline " " eventfld.long 0x0 27. " Istat[3] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" eventfld.long 0x0 26. " Istat[2] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" textline " " eventfld.long 0x0 25. " Istat[1] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" eventfld.long 0x0 24. " Istat[0] ,Interrupt status bits for GPIO WakeUp pins" "Not occurred,Occurred" width 0xb tree.end tree.open "GPT Registers (MBAR + 0x0600)" tree "GPT 0 (MBAR + 0x0600)" base anc:iobase()+600 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 1 (MBAR + 0x0610)" base anc:iobase()+610 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 2 (MBAR + 0x0620)" base anc:iobase()+620 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 3 (MBAR + 0x0630)" base anc:iobase()+630 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 4 (MBAR + 0x0640)" base anc:iobase()+640 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 5 (MBAR + 0x0650)" base anc:iobase()+650 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 6 (MBAR + 0x0660)" base anc:iobase()+660 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree "GPT 7 (MBAR + 0x0670)" base anc:iobase()+670 width 5. group 0x00++0x3 "GPT 0" line.long 0x0 "EMS,GPT0 Enable and Mode Select" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" bitfld.long 0x0 15. " WDen ,Wachdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" textline " " bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4.--5. " GPIO ,Simple GPIO Mode Type" "Input,Input,Output value=0,Output value=1" bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" group 0x04++0x3 line.long 0x0 "CIN,GPT0 Counter Input" hexmask.long.word 0x0 16.--31. 1. " Prescale ,Prescale amount applied to internal counter" hexmask.long.word 0x0 0.--15. 1. " COUNT ,Number of prescaled counts applied to reference events" group 0x08++0x3 line.long 0x0 "PWM,GPT0 PWM Configuration" hexmask.long.word 0x0 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x0 8. " PWMOP ,Pulse Width Mode Output Polarity" "ON,OFF" textline " " bitfld.long 0x0 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" group 0x0c++0x3 line.long 0x0 "STA,GPT0 Status" hexmask.long.word 0x0 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" hexmask.long.byte 0x0 12.--14. 1. " OVF ,Represents how many times internal counter has rolled over" textline " " bitfld.long 0x0 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" textline " " eventfld.long 0x0 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" eventfld.long 0x0 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" width 0xb tree.end tree.end ;Default MBAR Address base anc:iobase() tree "I2C Interface Registers (MBAR + 0x3D00)" width 4. group 0x3d20++0x3 line.long 0x0 "IC,Interrupt Control Register" bitfld.long 0x0 31. " BNBE2 ,Bus Not Busy Enable 2" "Disabled,Enabled" bitfld.long 0x0 30. " TE2 ,Transmit Enable 2" "Disabled,Enabled" bitfld.long 0x0 29. " RE2 ,Receive Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " IE2 ,Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x0 27. " BNBE1 ,Bus Not Busy Enable 1" "Disabled,Enabled" bitfld.long 0x0 26. " TE1 ,Transmit Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " RE1 ,Receive Enable 1" "Disabled,Enabled" bitfld.long 0x0 24. " IE1 ,Interrupt Enable 1" "Disabled,Enabled" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x3d24++0x3 line.long 0x0 "MIFR,I2C Filter Register" bitfld.long 0x0 24.--27. " FR[7:4] ,Width of glitch" "No filter/Bypass,1 IPBUS clock cycle,2 IPBUS clock cycles,3 IPBUS clock cycles,4 IPBUS clock cycles,5 IPBUS clock cycles,6 IPBUS clock cycles,7 IPBUS clock cycles,8 IPBUS clock cycles,9 IPBUS clock cycles,10 IPBUS clock cycles,11 IPBUS clock cycles,12 IPBUS clock cycles,13 IPBUS clock cycles,14 IPBUS clock cycles,15 IPBUS clock cycles" endif endif group 0x3d00++0x3 "I2C 1" line.long 0x0 "AD,I2C1 Address Register 0" hexmask.long.byte 0x0 25.--31. 1. " ADR ,The address I2C responds to, when addressed as a slave" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x3d04++0x3 line.long 0x0 "FD,I2C1 Frequency Divider Register 1" hexmask.long.byte 0x0 24.--31. 1. " FDR ,Field is used to prescale the clock for bit-rate selection" else group 0x3d04++0x3 line.long 0x0 "FD,I2C1 Frequency Divider Register 1" hexmask.long.byte 0x0 24.--29. 1. " FDR ,Field is used to prescale the clock for bit-rate selection" endif elif (cpu()=="MGT5100") group 0x3d04++0x3 line.long 0x0 "FD,I2C1 Frequency Divider Register 1" hexmask.long.byte 0x0 24.--29. 1. " FDR ,Field is used to prescale the clock for bit-rate selection" endif group 0x3d08++0x3 line.long 0x0 "CT,I2C1 Control Register 2" bitfld.long 0x0 31. " EN ,I2C Enable bit controls software reset of entire I2C module" "Disabled,Enabled" bitfld.long 0x0 30. " IEN ,I2C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 29. " STA ,Master/Slave mode select" "Slave,Master" textline " " bitfld.long 0x0 28. " TX ,Transmit/Receive mode select" "Receive,Transmit" bitfld.long 0x0 27. " TXAK ,Transmit Acknowledge enable" "Disabled,Enabled" bitfld.long 0x0 26. " RSTA ,Repeat Start cycle" "No start,Start" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x3d0c++0x3 line.long 0x0 "ST,I2C1 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" else group 0x3d0c++0x3 line.long 0x0 "ST,I2C1 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" bitfld.long 0x0 27. " AKF ,Acknowledge Cycle Falling Edge when Arbitration Lost" "Rising edge,Falling edge" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" endif elif (cpu()=="MGT5100") group 0x3d0c++0x3 line.long 0x0 "ST,I2C1 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" bitfld.long 0x0 27. " AKF ,Acknowledge Cycle Falling Edge when Arbitration Lost" "Rising edge,Falling edge" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" endif group 0x3d10++0x3 line.long 0x0 "IO,I2C1 Data I / O Register 4" hexmask.long.byte 0x0 24.--31. 1. " D[7:0] ,Data in Master Transmit Mode" group 0x3d40++0x3 "I2C 2" line.long 0x0 "AD,I2C2 Address Register 0" hexmask.long.byte 0x0 25.--31. 1. " ADR ,The address I2C responds to, when addressed as a slave" group 0x3d44++0x3 line.long 0x0 "FD,I2C2 Frequency Divider Register 1" hexmask.long.byte 0x0 24.--29. 1. " FDR ,Field is used to prescale the clock for bit-rate selection" group 0x3d48++0x3 line.long 0x0 "CT,I2C2 Control Register 2" bitfld.long 0x0 31. " EN ,I2C Enable bit controls software reset of entire I2C module" "Disabled,Enabled" bitfld.long 0x0 30. " IEN ,I2C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 29. " STA ,Master/Slave mode select" "Slave,Master" textline " " bitfld.long 0x0 28. " TX ,Transmit/Receive mode select" "Receive,Transmit" bitfld.long 0x0 27. " TXAK ,Transmit Acknowledge enable" "Disabled,Enabled" bitfld.long 0x0 26. " RSTA ,Repeat Start cycle" "No start,Start" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B rgroup 0x3d4c++0x3 line.long 0x0 "ST,I2C2 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" bitfld.long 0x0 27. " AKF ,Acknowledge Cycle Falling Edge when Arbitration Lost" "Rising edge,Falling edge" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" else rgroup 0x3d4c++0x3 line.long 0x0 "ST,I2C2 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" endif elif (cpu()=="MGT5100") rgroup 0x3d4c++0x3 line.long 0x0 "ST,I2C2 Status Register 3" bitfld.long 0x0 31. " CF ,Data transferring" "In progress,Completed" bitfld.long 0x0 30. " AAS ,Addressed As Slave" "Not addressed,Slave" bitfld.long 0x0 29. " BB ,Bus Busy" "Idle,Busy" textline " " bitfld.long 0x0 28. " AL ,Arbitration Lost" "Not lost,Lost" textline " " bitfld.long 0x0 26. " SRW ,Slave Read/Write" "Write,Read" bitfld.long 0x0 25. " IF ,I2C Interrupt" "Stopped,Pending" bitfld.long 0x0 24. " RXAK ,Receive Acknowledge" "Received,Not received" endif group 0x3d50++0x3 line.long 0x0 "IO,I2C2 Data I / O Register 4" hexmask.long.byte 0x0 24.--29. 1. " FDR ,Field is used to prescale the clock for bit-rate selection" width 0xb tree.end tree "Interrupt Controller Registers (MBAR + 0x0500)" width 6. group 0x500++0x3 line.long 0x0 "PIM,Peripheral Interrupt Mask" bitfld.long 0x0 31. " Per_Mask_BC ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 30. " Per_Mask_PSC1 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 29. " Per_Mask_PSC2 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 28. " Per_Mask_PSC3 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 27. " Per_Mask_PSC6 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 26. " Per_Mask_ETH ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 25. " Per_Mask_USB ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 24. " Per_Mask_ATA ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 23. " Per_Mask_PCIC ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 22. " Per_Mask_PCIRX ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 21. " Per_Mask_PCITX ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 20. " Per_Mask_PSC4 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 19. " Per_Mask_PSC5 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 18. " Per_Mask_SPIM ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 17. " Per_Mask_SPIS ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 16. " Per_Mask_I2C1 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 15. " Per_Mask_I2C2 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 14. " Per_Mask_CAN1 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 13. " Per_Mask_CAN2 ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 12. " Per_Mask_IRRX ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 11. " Per_Mask_IRTX ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 10. " Per_Mask_XLBA ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" textline " " bitfld.long 0x0 9. " Per_Mask_BDLC ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" bitfld.long 0x0 8. " Per_Mask_BCLP ,Mask/accept individual peripheral interrupt sources" "Accepted,Ignored" group 0x504++0x3 line.long 0x0 "PPHL1,Peripheral Priority and HI / LO Select 1" hexmask.long.byte 0x0 28.--31. 1. " Per0_pri_BS ,Priority encoding value" hexmask.long.byte 0x0 24.--27. 1. " Per1_pri_PSC1 ,Priority encoding value" textline " " hexmask.long.byte 0x0 20.--23. 1. " Per2_pri_PSC2 ,Priority encoding value" hexmask.long.byte 0x0 16.--19. 1. " Per3_pri_PSC3 ,Priority encoding value" textline " " hexmask.long.byte 0x0 12.--15. 1. " Per4_pri_PSC6 ,Priority encoding value" hexmask.long.byte 0x0 8.--11. 1. " Per5_pri_ETH ,Priority encoding value" textline " " hexmask.long.byte 0x0 4.--7. 1. " Per6_pri_USB ,Priority encoding value" hexmask.long.byte 0x0 0.--3. 1. " Per7_pri_ATA ,Priority encoding value" group 0x508++0x3 line.long 0x0 "PPHL2,Peripheral Priority and HI / LO Select 2" hexmask.long.byte 0x0 28.--31. 1. " Per8_pri_PCIC ,Priority encoding value" hexmask.long.byte 0x0 24.--27. 1. " Per9_pri_PCIRX ,Priority encoding value" textline " " hexmask.long.byte 0x0 20.--23. 1. " Per10_pri_PCITX ,Priority encoding value" hexmask.long.byte 0x0 16.--19. 1. " Per11_pri_PSC4 ,Priority encoding value" textline " " hexmask.long.byte 0x0 12.--15. 1. " Per12_pri_PSC5 ,Priority encoding value" hexmask.long.byte 0x0 8.--11. 1. " Per13_pri_SPIM ,Priority encoding value" textline " " hexmask.long.byte 0x0 4.--7. 1. " Per14_pri_SPIS ,Priority encoding value" hexmask.long.byte 0x0 0.--3. 1. " Per15_pri_I2C1 ,Priority encoding value" group 0x50c++0x3 line.long 0x0 "PPHL3,Peripheral Priority and HI / LO Select 3" hexmask.long.byte 0x0 28.--31. 1. " Per16_pri_I2C2 ,Priority encoding value" hexmask.long.byte 0x0 24.--27. 1. " Per17_pri_CAN1 ,Priority encoding value" textline " " hexmask.long.byte 0x0 20.--23. 1. " Per18_pri_CAN2 ,Priority encoding value" hexmask.long.byte 0x0 16.--19. 1. " Per19_pri_IRRX ,Priority encoding value" textline " " hexmask.long.byte 0x0 12.--15. 1. " Per20_pri_IRTX ,Priority encoding value" hexmask.long.byte 0x0 8.--11. 1. " Per21_pri_XLB ,Priority encoding value" textline " " hexmask.long.byte 0x0 4.--7. 1. " Per22_pri_BDLC ,Priority encoding value" hexmask.long.byte 0x0 0.--3. 1. " Per23_pri_BCLP ,Priority encoding value" group 0x510++0x3 line.long 0x0 "EEET,External Enable and External Types" bitfld.long 0x0 27. " ECLR0 ,Clear external /IRQ[0] interrupt indications" "Not cleared,Cleared" bitfld.long 0x0 26. " ECLR1 ,Clear external /IRQ[1] interrupt indications" "Not cleared,Cleared" textline " " bitfld.long 0x0 25. " ECLR2 ,Clear external /IRQ[2] interrupt indications" "Not cleared,Cleared" bitfld.long 0x0 24. " ECLR3 ,Clear external /IRQ[3] interrupt indications" "Not cleared,Cleared" textline " " bitfld.long 0x0 22.--23. " Etype0 ,Control how the Interrupt Controller interprets the /IRQ[0] input pin" "Level high,Edge rising,Edge falling,Level low" bitfld.long 0x0 20.--21. " Etype1 ,Control how the Interrupt Controller interprets the /IRQ[1] input pin" "Level high,Edge rising,Edge falling,Level low" textline " " bitfld.long 0x0 18.--19. " Etype2 ,Control how the Interrupt Controller interprets the /IRQ[2] input pin" "Level high,Edge rising,Edge falling,Level low" bitfld.long 0x0 16.--17. " Etype3 ,Control how the Interrupt Controller interprets the /IRQ[3] input pin" "Level high,Edge rising,Edge falling,Level low" textline " " bitfld.long 0x0 12. " MEE ,Master External Enable" "Disabled,Enabled" bitfld.long 0x0 11. " EENA0 ,IRQ[0] enable bit" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " EENA1 ,IRQ[1] enable bit" "Disabled,Enabled" bitfld.long 0x0 9. " EENA2 ,IRQ[2] enable bit" "Disabled,Enabled" textline " " bitfld.long 0x0 8. " EENA3 ,IRQ[3] enable bit" "Disabled,Enabled" bitfld.long 0x0 0. " CEb ,Critical Enable" "Disabled,Enabled" group 0x514++0x3 line.long 0x0 "CPMI,Critical Priority and Main Interrupt Mask" hexmask.long.byte 0x0 30.--31. 1. " Crit0_pri ,Priority encoding value for Critical Interrupt 0, /IRQ[0] input pin" hexmask.long.byte 0x0 28.--29. 1. " Crit1_pri ,Priority encoding value for Slice Timer 0 interrupt source" textline " " hexmask.long.byte 0x0 26.--27. 1. " Crit2_pri ,Priority encoding value for HI_int interrupt source" hexmask.long.byte 0x0 24.--25. 1. " Crit3_pri ,Priority encoding value for CCS WakeUp source" textline " " bitfld.long 0x0 16. " Main_Mask0 ,Mask/accept Slice Timer 1 main interrupt source" "Accepted,Ignored" bitfld.long 0x0 15. " Main_Mask1 ,Mask/accept /IRQ[1] main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 14. " Main_Mask2 ,Mask/accept /IRQ[2] main interrupt source" "Accepted,Ignored" bitfld.long 0x0 13. " Main_Mask3 ,Mask/accept /IRQ[3] main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 12. " Main_Mask4 ,Mask/accept LO_int main interrupt source" "Accepted,Ignored" bitfld.long 0x0 11. " Main_Mask5 ,Mask/accept RTC_int main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 10. " Main_Mask6 ,Mask/accept RTC_sint main interrupt source" "Accepted,Ignored" bitfld.long 0x0 9. " Main_Mask7 ,Mask/accept GPIO_std main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 8. " Main_Mask8 ,Mask/accept GPIO_wkup main interrupt source" "Accepted,Ignored" bitfld.long 0x0 7. " Main_Mask9 ,Mask/accept TMR0 main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 6. " Main_Mask10 ,Mask/accept TMR1 main interrupt source" "Accepted,Ignored" bitfld.long 0x0 5. " Main_Mask11 ,Mask/accept TMR2 main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 4. " Main_Mask12 ,Mask/accept TMR3 main interrupt source" "Accepted,Ignored" bitfld.long 0x0 3. " Main_Mask13 ,Mask/accept TMR4 main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 2. " Main_Mask14 ,Mask/accept TMR5 main interrupt source" "Accepted,Ignored" bitfld.long 0x0 1. " Main_Mask15 ,Mask/accept TMR6 main interrupt source" "Accepted,Ignored" textline " " bitfld.long 0x0 0. " Main_Mask16 ,Mask/accept TMR7 main interrupt source" "Accepted,Ignored" group 0x518++0x3 line.long 0x0 "MIP1,Main Interrupt Priority and INT / SMI Select 1" hexmask.long.byte 0x0 28.--31. 1. " Main1_pri ,Main interrupt /IRQ[1] priority encoding value" hexmask.long.byte 0x0 24.--27. 1. " Main2_pri ,Main interrupt /IRQ[1] priority encoding value" textline " " hexmask.long.byte 0x0 20.--23. 1. " Main3_pri ,Main interrupt /IRQ[1] priority encoding value" hexmask.long.byte 0x0 16.--19. 1. " Main4_pri ,Main interrupt LO_int priority encoding value" textline " " hexmask.long.byte 0x0 12.--15. 1. " Main5_pri ,Main interrupt RTC_periodic priority encoding value" hexmask.long.byte 0x0 8.--11. 1. " Main6_pri ,Main interrupt RTC_stopwatch and RTC_alarm priority encoding value" textline " " hexmask.long.byte 0x0 4.--7. 1. " Main7_pri ,Main interrupt GPIO_std priority encoding value" hexmask.long.byte 0x0 0.--3. 1. " Main8_pri ,Main interrupt GPRIO_wkup priority encoding value" group 0x51c++0x3 line.long 0x0 "MIP2,Main Interrupt Priority and INT / SMI Select 2" hexmask.long.byte 0x0 28.--31. 1. " Main9_pri ,Main interrupt TMR0 priority encoding value" hexmask.long.byte 0x0 24.--27. 1. " Main10_pri ,Main interrupt TMR1 priority encoding value" textline " " hexmask.long.byte 0x0 20.--23. 1. " Main11_pri ,Main interrupt TMR2 priority encoding value" hexmask.long.byte 0x0 16.--19. 1. " Main12_pri ,Main interrupt TMR3 priority encoding value" textline " " hexmask.long.byte 0x0 12.--15. 1. " Main13_pri ,Main interrupt TMR4 priority encoding value" hexmask.long.byte 0x0 8.--11. 1. " Main14_pri ,Main interrupt TMR5 priority encoding value" textline " " hexmask.long.byte 0x0 4.--7. 1. " Main15_pri ,Main interrupt TMR6 priority encoding value" hexmask.long.byte 0x0 0.--3. 1. " Main16_pri ,Main interrupt TMR7 priority encoding value" group 0x524++0x3 line.long 0x0 "PMCE,PerStat, MainStat, CritStat Encoded" hexmask.long.byte 0x0 24.--29. 1. " PSe ,Peripheral Status Encoded" hexmask.long.byte 0x0 16.--21. 1. " MSe ,Main Status Encoded" textline " " bitfld.long 0x0 8.--10. " CSe ,Critical Status Encoded" "/IRQ,Slice Timer 0,HI_int,CCS module,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0 0. " CEbSh ,Critical Enable bar Shadow bit" "Disabled,Enabled" group 0x528++0x3 line.long 0x0 "CISA,Critical Interrupt Status All" bitfld.long 0x0 27. " CSa0 ,Critical interrupt status for /IRQ[0] interrupt" "Not active,Active" bitfld.long 0x0 26. " CSa1 ,Critical interrupt status for Slice Timer 0 interrupt" "Not active,Active" textline " " bitfld.long 0x0 25. " CSa2 ,Critical interrupt status for HI_int interrupt" "Not active,Active" bitfld.long 0x0 24. " CSa3 ,Critical interrupt status for WakeUp from deep-sleep mode CCS interrupt" "Not active,Active" group 0x52c++0x3 line.long 0x0 "MISA,Main Interrupt Status All" bitfld.long 0x0 16. " MSa0 ,Main interrupt status for Slice_Timer 1 (SMI interrupt only)" "Not active,Active" bitfld.long 0x0 15. " MSa1 ,Main interrupt status for /IRQ[1] input pin" "Not active,Active" textline " " bitfld.long 0x0 14. " MSa2 ,Main interrupt status for /IRQ[2] input pin" "Not active,Active" bitfld.long 0x0 13. " MSa3 ,Main interrupt status for /IRQ[3] input pin" "Not active,Active" textline " " bitfld.long 0x0 12. " MSa4 ,Main interrupt status for LO_int (some Peripheral source)" "Not active,Active" bitfld.long 0x0 11. " MSa5 ,Main interrupt status for RTC_periodic interrupt" "Not active,Active" textline " " bitfld.long 0x0 10. " MSa6 ,Main interrupt status for RTC_stopwatch interrupt" "Not active,Active" bitfld.long 0x0 9. " MSa7 ,Main interrupt status for GPIO std interrupt" "Not active,Active" textline " " bitfld.long 0x0 8. " MSa8 ,Main interrupt status for GPIO WakeUp interrupt" "Not active,Active" bitfld.long 0x0 7. " MSa9 ,Main interrupt status for TMR0 interrupt" "Not active,Active" textline " " bitfld.long 0x0 6. " MSa10 ,Main interrupt status for TMR1 interrupt" "Not active,Active" bitfld.long 0x0 5. " MSa11 ,Main interrupt status for TMR2 interrupt" "Not active,Active" textline " " bitfld.long 0x0 4. " MSa12 ,Main interrupt status for TMR3 interrupt" "Not active,Active" bitfld.long 0x0 3. " MSa13 ,Main interrupt status for TMR4 interrupt" "Not active,Active" textline " " bitfld.long 0x0 2. " MSa14 ,Main interrupt status for TMR5 interrupt" "Not active,Active" bitfld.long 0x0 1. " MSa15 ,Main interrupt status for TMR6 interrupt" "Not active,Active" textline " " bitfld.long 0x0 0. " MSa16 ,Main interrupt status for TMR7 interrupt" "Not active,Active" group 0x530++0x3 line.long 0x0 "PISA,Peripheral Interrupt Status All" bitfld.long 0x0 23. " PSa23 ,Peripheral interrupt status for BestComm LocalPlus" "Not active,Active" bitfld.long 0x0 22. " PSa22 ,Peripheral interrupt status for BDLC" "Not active,Active" textline " " bitfld.long 0x0 21. " PSa0 ,Peripheral interrupt status for BestComm interrupt source" "Not active,Active" bitfld.long 0x0 20. " PSa1 ,Peripheral interrupt status for PSC1" "Not active,Active" textline " " bitfld.long 0x0 19. " PSa2 ,Peripheral interrupt status for PSC2" "Not active,Active" bitfld.long 0x0 18. " PSa3 ,Peripheral interrupt status for PSC3" "Not active,Active" textline " " bitfld.long 0x0 17. " PSa4 ,Peripheral interrupt status for PSC6" "Not active,Active" bitfld.long 0x0 16. " PSa5 ,Peripheral interrupt status for Ethernet" "Not active,Active" textline " " bitfld.long 0x0 15. " PSa6 ,Peripheral interrupt status for USB" "Not active,Active" bitfld.long 0x0 14. " PSa7 ,Peripheral interrupt status for ATA" "Not active,Active" textline " " bitfld.long 0x0 13. " PSa8 ,Peripheral interrupt status for PCI Control module" "Not active,Active" bitfld.long 0x0 12. " PSa9 ,Peripheral interrupt status for PCI SC Initiator Rx" "Not active,Active" textline " " bitfld.long 0x0 11. " PSa10 ,Peripheral interrupt status for PCI SC Initiator Tx" "Not active,Active" bitfld.long 0x0 10. " PSa11 ,Peripheral interrupt status for PSC4" "Not active,Active" textline " " bitfld.long 0x0 9. " PSa12 ,Peripheral interrupt status for PSC5" "Not active,Active" bitfld.long 0x0 8. " PSa13 ,Peripheral interrupt status for SPI modf" "Not active,Active" textline " " bitfld.long 0x0 7. " PSa14 ,Peripheral interrupt status for SPI spif" "Not active,Active" bitfld.long 0x0 6. " PSa15 ,Peripheral interrupt status for I2C1" "Not active,Active" textline " " bitfld.long 0x0 5. " PSa16 ,Peripheral interrupt status for I2C2" "Not active,Active" bitfld.long 0x0 4. " PSa17 ,Peripheral interrupt status for CAN1" "Not active,Active" textline " " bitfld.long 0x0 3. " PSa18 ,Peripheral interrupt status for CAN2" "Not active,Active" bitfld.long 0x0 0. " PSa21 ,Peripheral interrupt status for XLB Arbiter" "Not active,Active" group 0x538++0x3 line.long 0x0 "BEE,Bus Error Enable Register" bitfld.long 0x0 25. " BE1 ,Bus Error 1 - write attempt to read-only register" "No error,Error" bitfld.long 0x0 24. " BE2 ,Bus Error 0 - access to unimplemented register" "No error,Error" group 0x540++0x3 line.long 0x0 "MIE,Main Interrupt Emulation Register" bitfld.long 0x0 16. " MEa0 ,Main interrupt emulation for Slice_Timer 1 interrupt" "Not active,Active" bitfld.long 0x0 15. " MEa1 ,Main interrupt emulation for /IRQ[1] interrupt" "Not active,Active" textline " " bitfld.long 0x0 14. " MEa2 ,Main interrupt emulation for /IRQ[2] interrupt" "Not active,Active" bitfld.long 0x0 13. " MEa3 ,Main interrupt emulation for /URQ[3] interrupt" "Not active,Active" textline " " bitfld.long 0x0 12. " MEa4 ,Main interrupt emulation for LO_int interrupt" "Not active,Active" bitfld.long 0x0 11. " MEa5 ,Main interrupt emulation for RTC_periodic interrupt" "Not active,Active" textline " " bitfld.long 0x0 10. " MEa6 ,Main interrupt emulation for RTC_stopwatch interrupt" "Not active,Active" bitfld.long 0x0 9. " MEa7 ,Main interrupt emulation for GPIO_std interrupt" "Not active,Active" textline " " bitfld.long 0x0 8. " MEa8 ,Main interrupt emulation for GPIO_wkup interrupt" "Not active,Active" bitfld.long 0x0 7. " MEa9 ,Main interrupt emulation for TMR0 interrupt" "Not active,Active" textline " " bitfld.long 0x0 6. " MEa10 ,Main interrupt emulation for TMR1 interrupt" "Not active,Active" bitfld.long 0x0 5. " MEa11 ,Main interrupt emulation for TMR2 interrupt" "Not active,Active" textline " " bitfld.long 0x0 4. " MEa12 ,Main interrupt emulation for TMR3 interrupt" "Not active,Active" bitfld.long 0x0 3. " MEa13 ,Main interrupt emulation for TMR4 interrupt" "Not active,Active" textline " " bitfld.long 0x0 2. " MEa14 ,Main interrupt emulation for TMR5 interrupt" "Not active,Active" bitfld.long 0x0 1. " MEa15 ,Main interrupt emulation for TMR6 interrupt" "Not active,Active" textline " " bitfld.long 0x0 0. " MEa16 ,Main interrupt emulation for TMR7 interrupt" "Not active,Active" group 0x544++0x3 line.long 0x0 "PIE, Peripheral Interrupt Emulation Register" bitfld.long 0x0 23. " PEa[23] ,Peripheral interrupt mulation for BestComm LocalPlus interrupt" "Not active,Active" bitfld.long 0x0 22. " PEa[22] ,Peripheral interrupt mulation for BDLC interrupt" "Not active,Active" textline " " bitfld.long 0x0 21. " PEa[0] ,Peripheral interrupt mulation for BestComm interrupt" "Not active,Active" bitfld.long 0x0 20. " PEa[1] ,Peripheral interrupt mulation for PSC1 interrupt" "Not active,Active" textline " " bitfld.long 0x0 19. " PEa[2] ,Peripheral interrupt mulation for PSC2 interrupt" "Not active,Active" bitfld.long 0x0 18. " PEa[3] ,Peripheral interrupt mulation for PSC3 interrupt" "Not active,Active" textline " " bitfld.long 0x0 17. " PEa[4] ,Peripheral interrupt mulation for PSC6 interrupt" "Not active,Active" bitfld.long 0x0 16. " PEa[5] ,Peripheral interrupt mulation for Ethernet interrupt" "Not active,Active" textline " " bitfld.long 0x0 15. " PEa[6] ,Peripheral interrupt mulation for USB interrupt" "Not active,Active" bitfld.long 0x0 14. " PEa[7] ,Peripheral interrupt mulation for ATA interrupt" "Not active,Active" textline " " bitfld.long 0x0 13. " PEa[8] ,Peripheral interrupt mulation for PCI Control module interrupt" "Not active,Active" bitfld.long 0x0 12. " PEa[9] ,Peripheral interrupt mulation for PCI SC Initiator Rx interrupt" "Not active,Active" textline " " bitfld.long 0x0 11. " PEa[10] ,Peripheral interrupt mulation for PCI SC Initiator Tx interrupt" "Not active,Active" bitfld.long 0x0 10. " PEa[11] ,Peripheral interrupt mulation for PSC4 interrupt" "Not active,Active" textline " " bitfld.long 0x0 9. " PEa[12] ,Peripheral interrupt mulation for PSC5 interrupt" "Not active,Active" bitfld.long 0x0 8. " PEa[13] ,Peripheral interrupt mulation for SPI_modf interrupt" "Not active,Active" textline " " bitfld.long 0x0 7. " PEa[14] ,Peripheral interrupt mulation for SPI_spif interrupt" "Not active,Active" bitfld.long 0x0 6. " PEa[15] ,Peripheral interrupt mulation for I2C1 interrupt" "Not active,Active" textline " " bitfld.long 0x0 5. " PEa[16] ,Peripheral interrupt mulation for I2C2 interrupt" "Not active,Active" bitfld.long 0x0 4. " PEa[17] ,Peripheral interrupt mulation for CAN1 interrupt" "Not active,Active" textline " " bitfld.long 0x0 3. " PEa[18] ,Peripheral interrupt mulation for CAN2 interrupt" "Not active,Active" bitfld.long 0x0 0. " PEa[21] ,Peripheral interrupt mulation for XLB Arbiter interrupt" "Not active,Active" group 0x548++0x3 line.long 0x0 "IIE,IRQ Interrupt Emulation Register" bitfld.long 0x0 27. " IRQEa0 ,/IRQ[0] input pin emulation" "Not active,Active" bitfld.long 0x0 26. " IRQEa1 ,/IRQ[1] input pin emulation" "Not active,Active" textline " " bitfld.long 0x0 25. " IRQEa2 ,/IRQ[2] input pin emulation" "Not active,Active" bitfld.long 0x0 24. " IRQEa3 ,/IRQ[3] input pin emulation" "Not active,Active" width 0xb tree.end tree "Chip Select / LocalPlus Bus Registers (MBAR + 0x0300)" width 7. group 0x300++0x3 line.long 0x0 "CS0CR,CS0" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x304++0x3 line.long 0x0 "CS1CR,CS1" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x308++0x3 line.long 0x0 "CS2CR,CS2" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x30c++0x3 line.long 0x0 "CS3CR,CS3" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x310++0x3 line.long 0x0 "CS4CR,CS4" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x314++0x3 line.long 0x0 "CS5CR,CS5" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x320++0x3 line.long 0x0 "CS6CR,CS6" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x324++0x3 line.long 0x0 "CS7CR,CS7" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of wait states to insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,Base number of wait states to insert" textline " " bitfld.long 0x0 15. " MX ,Transaction operates as multiplexed or non-multiplexed" "Non-multiplexed,Multiplexed" bitfld.long 0x0 13. " AA ,ACK Active - multiplexed transactions only" "Not active,Active" textline " " bitfld.long 0x0 12. " CE ,An individual Enable bit" "Disabled,Enabled" bitfld.long 0x0 10.--11. " AS ,Address Size field" "8 bits,16 bits,24 bits,>25 bits" textline " " bitfld.long 0x0 8.--9. " DS ,Data Size field" "1 Byte,2 Bytes,3 Bytes,4 Bytes" hexmask.long.byte 0x0 6.--7. 1. " Bank ,Bank bits" textline " " bitfld.long 0x0 4.--5. " WTyp ,WaitX/WaitP state type" "WaitX is applied to read and write cycles (WaitP is ignored),WaitX is applied to Read cycles (WaitP is applied to Write cycles),WaitX is applied to Reads (WaitP/WaitX (16-bit value) is applied to Writes),WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes" textline " " bitfld.long 0x0 3. " WS ,Write Swap bit" "No swap,Swap" bitfld.long 0x0 2. " RS ,Read Swap bit" "No swap,Swap" textline " " bitfld.long 0x0 1. " WO ,Write Only bit" "Read/write,Write" bitfld.long 0x0 0. " RO ,Read Only bit" "Read/write,Write" group 0x318++0x3 line.long 0x0 "CSCR,CS Control Register" bitfld.long 0x0 31. " EBEE ,External Bus Error Enable bit" "Disabled,Enabled" bitfld.long 0x0 28. " IBEE ,Internal Bus Error Enable bit" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " IE ,Interrupt Enable bit" "Disabled,Enabled" bitfld.long 0x0 24. " ME ,Master Enable bit" "Disabled,Enabled" group 0x31c++0x3 line.long 0x0 "CSSR,CS Status Register" bitfld.long 0x0 29. " WOerr ,Write Only error" "No error,Error" bitfld.long 0x0 28. " ROerr ,Read Only error" "No error,Error" textline " " bitfld.long 0x0 24.--26. " CSxerr ,Chip Select error" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7" bitfld.long 0x0 17. " B2 ,Bus Error (type 2)" "No error,Error" textline " " bitfld.long 0x0 16. " B3 ,Bus Error (type 3)" "No error,Error" group 0x328++0x3 line.long 0x0 "CSBCR,CS Burst Control Register" bitfld.long 0x0 31. " CW7 ,Chip Select 7 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 30. " SLB7 ,Chip Select 7 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 29. " BWE7 ,Chip Select 7 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 28. " BRE7 ,Chip Select 7 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " CW6 ,Chip Select 6 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 26. " SLB6 ,Chip Select 6 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 25. " BWE6 ,Chip Select 6 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 24. " BRE6 ,Chip Select 6 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 23. " CW5 ,Chip Select 5 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 22. " SLB5 ,Chip Select 5 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 21. " BWE5 ,Chip Select 5 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 20. " BRE5 ,Chip Select 5 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " CW4 ,Chip Select 4 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 18. " SLB4 ,Chip Select 4 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 17. " BWE4 ,Chip Select 4 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 16. " BRE4 ,Chip Select 4 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " CW3 ,Chip Select 3 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 14. " SLB3 ,Chip Select 3 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 13. " BWE3 ,Chip Select 3 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 12. " BRE3 ,Chip Select 3 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " CW2 ,Chip Select 2 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 10. " SLB2 ,Chip Select 2 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 9. " BWE2 ,Chip Select 2 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 8. " BRE2 ,Chip Select 2 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " CW1 ,Chip Select 1 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 6. " SLB1 ,Chip Select 1 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 5. " BWE1 ,Chip Select 1 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 4. " BRE1 ,Chip Select 1 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " CW0 ,Chip Select 0 Cache Wrap capable" "Not capable,Capable" bitfld.long 0x0 2. " SLB0 ,Chip Select 0 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x0 1. " BWE0 ,Chip Select 0 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x0 0. " BRE0 ,Chip Select 0 Burst Read Enable" "Disabled,Enabled" group 0x32c++0x3 line.long 0x0 "CSDCR,CS Dead Cycle Control Register" bitfld.long 0x0 28.--29. " DC7 ,Deadcycles" "0,1,2,3" bitfld.long 0x0 24.--25. " DC6 ,Deadcycles" "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " DC5 ,Deadcycles" "0,1,2,3" bitfld.long 0x0 16.--17. " DC4 ,Deadcycles" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DC3 ,Deadcycles" "0,1,2,3" bitfld.long 0x0 8.--9. " DC2 ,Deadcycles" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " DC1 ,Deadcycles" "0,1,2,3" bitfld.long 0x0 0.--1. " DC0 ,Deadcycles" "0,1,2,3" width 0xb tree.end tree "PCI Control Registers (MBAR + 0x0D00)" width 9. group 0xd00++0x3 line.long 0x0 "IDR,PCI Device ID / Vendor ID" hexmask.long.word 0x0 16.--31. 1. " Device_ID ,PCI Device Id assigned to MPC5200/MPC5200B" hexmask.long.word 0x0 0.--15. 1. " Vendor_ID ,PCI Vendor Id assigned to MPC5200/MPC5200B" group 0xd04++0x3 line.long 0x0 "SCR,PCI Status / Command" eventfld.long 0x0 31. " PE ,Parity Error Detected" "Not detected,Detected" eventfld.long 0x0 30. " SE ,System Error Signalled" "No error,Error" textline " " eventfld.long 0x0 29. " MA ,Master Abort Received" "Not received,Received" eventfld.long 0x0 28. " TR ,Target Abort Received" "Not received,Received" textline " " eventfld.long 0x0 27. " TS ,Target Abort Signalled" "Not signalled,Signalled" bitfld.long 0x0 25.--26. " DT ,DEVSEL# Timing" "00,01,10,11" textline " " eventfld.long 0x0 24. " DP ,Master Data Parity Error" "No error,Error" ;bitfld.long 0x0 23. " FC ,Fast Back-to-Back Capable" "0,1" bitfld.long 0x0 22. " R ,UDF (User Defined Features) Supported" "Not supported,Supported" textline " " bitfld.long 0x0 21. " 66M ,66 MHz Capable (fixed to 1)" "Other,66MHz" bitfld.long 0x0 20. " C ,Capabilities List" "Implemented,Not implemented" textline " " ;bitfld.long 0x0 9. " F ,Fast Back-to-Back Transfer Enable" "0,1" bitfld.long 0x0 8. " S ,/SERR Enable" "Disabled,Enabled" bitfld.long 0x0 7. " St ,Address and Data Stepping" "Used,Not used" textline " " bitfld.long 0x0 6. " PER ,Parity Error Response" "/PERR not asserted,/PERR asserted" bitfld.long 0x0 5. " V ,VGA Palette Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " MW ,Memory Write and Invalidate Enable" "Disabled,Enabled" bitfld.long 0x0 3. " Sp ,Special Cycle Monitor or Ignore" "Ignored,Not ignored" textline " " bitfld.long 0x0 2. " B ,Bus Master Enable" "Disabled,Enabled" bitfld.long 0x0 1. " M ,Memory Access Control" "Disabled,Enabled" ;bitfld.long 0x0 0. " IO ,IO Access Control" "0,1" rgroup 0xd08++0x3 line.long 0x0 "CCRIR,PCI Class / Code Revision ID" hexmask.long 0x0 8.--31. 1. " Class_Code ,PCI Class Code assigned to MPC5200/MPC5200B" hexmask.long.byte 0x0 0.--7. 1. " Revision_ID ,PCI Revision Id for this version of MPC5200/MPC5200B" group 0xd0c++0x3 line.long 0x0 "CR1,PCI Configuration" hexmask.long.byte 0x0 24.--31. 1. " BIST ,Built In Self Test" hexmask.long.byte 0x0 16.--23. 1. " HT ,Header Type" textline " " hexmask.long.byte 0x0 8.--15. 1. " LT ,Latency Timer" hexmask.long.byte 0x0 0.--3. 1. " CLSize ,Cache Line Size" group 0xd10++0x3 line.long 0x0 "BAR0,PCI Base Address 0" hexmask.long.byte 0x0 18.--31. 1. " BAR0 ,Base Address Register 0" bitfld.long 0x0 3. " PREF ,Prefetchable Address" "Prefetchable,Not prefetchable" textline " " bitfld.long 0x0 1.--2. " RANGE ,Base address 0 is 32 bits wide" "00,01,10,11" bitfld.long 0x0 0. " IO/M# ,IO or Memory Space Fixed to 0" "Memory,I/O" group 0xd14++0x3 line.long 0x0 "BAR1,PCI Base Address 1" hexmask.long.byte 0x0 30.--31. 1. " BAR1 ,Base Address Register 1" bitfld.long 0x0 3. " PREF ,Prefetchable Address" "Prefetchable,Not prefetchable" textline " " bitfld.long 0x0 1.--2. " RANGE ,Base address 0 is 32 bits wide" "00,01,10,11" bitfld.long 0x0 0. " IO/M# ,IO or Memory Space Fixed to 0" "Memory,I/O" group 0xd28++0x3 line.long 0x0 "CCPR,PCI Cardbus CIS Pointer" group 0xd2c++0x3 line.long 0x0 "SID,PCI Subsystem ID/Subsystem Vendor ID" group 0xd30++0x3 line.long 0x0 "ERBAR,PCI Expansion ROM" group 0xd34++0x3 line.long 0x0 "CPR,PCI Capabilities Pointer" group 0xd3c++0x3 line.long 0x0 "CR2,PCI Configuration 2" hexmask.long.byte 0x0 28.--31. 1. " MAX_LAT ,Maximum Latency" hexmask.long.byte 0x0 20.--23. 1. " MIN_GNT ,Minimum Grant" textline " " hexmask.long.byte 0x0 12.--15. 1. " I_PIN ,Interrupt Pin" hexmask.long.byte 0x0 4.--7. 1. " I_LINE ,Interrupt Line" group 0xd60++0x3 line.long 0x0 "GSCR,PCI Global Status/Control" eventfld.long 0x0 30. " BM ,Broken Master Detected" "Not detected,Detected" eventfld.long 0x0 29. " PE ,PERR Detected" "Not detected,Detected" textline " " eventfld.long 0x0 28. " SE ,SERR Detected" "Not detected,Detected" hexmask.long.byte 0x0 24.--26. 1. " XTPD ,XL bus clock to the PCI clock divide ratio" textline " " hexmask.long.byte 0x0 16.--18. 1. " ITPD ,Slave bus clock to the PCI clock divide ratio" bitfld.long 0x0 14. " BME ,Broken Master Interupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " PEE ,Parity Interrupt Error Enable" "Disabled,Enabled" bitfld.long 0x0 12. " SEE ,System Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " PR ,PCI Reset" "Reset,Not reset" group 0xd64++0x3 line.long 0x0 "TBATR0,PCI Target Base Address Translation 0" hexmask.long.word 0x0 18.--31. 1. " BAT0 ,Base Address Translation Register" bitfld.long 0x0 0. " EN0 ,Transaction in BAR0 space enabled" "Disabled,Enabled" group 0xd68++0x3 line.long 0x0 "TBATR1,PCI Target Base Address Translation 1" bitfld.long 0x0 30.--31. " BAT1 ,Base Address Translation Register" "0,1,2,3" bitfld.long 0x0 0. " EN1 ,Transaction in BAR1 space enabled" "Disabled,Enabled" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0xd6c++0x3 line.long 0x0 "TCR,PCI Target Control Register" bitfld.long 0x0 24. " LD ,Latrule Disabled" "Enabled,Disabled" bitfld.long 0x0 16. " P ,Prefetch Reads" "Low,High" textline " " bitfld.long 0x0 8. " WCD ,Write Combine Disabled" "Enabled,Disabled" hexmask.long.byte 0x0 0.--7. 1. " WCT ,Write Combine Timer" else group 0xd6c++0x3 line.long 0x0 "TCR,PCI Target Control Register" bitfld.long 0x0 24. " LD ,Latrule Disabled" "Enabled,Disabled" bitfld.long 0x0 16. " P ,Prefetch Reads" "Low,High" endif elif (cpu()=="MGT5100") group 0xd6c++0x3 line.long 0x0 "TCR,PCI Target Control Register" bitfld.long 0x0 24. " LD ,Latrule Disabled" "Enabled,Disabled" bitfld.long 0x0 16. " P ,Prefetch Reads" "Low,High" endif group 0xd70++0x3 line.long 0x0 "IW0BTAR,PCI Initiator Window 0 Base/Translation Address" hexmask.long.byte 0x0 24.--31. 1. " WBA0 ,Window 0 Base Address" hexmask.long.byte 0x0 16.--23. 1. " WAM0 ,Window 0 Address Mask" textline " " hexmask.long.byte 0x0 8.--15. 1. " WTA0 ,Window 0 Translation Address" group 0xd74++0x3 line.long 0x0 "IW1BTAR,PCI Initiator Window 1 Base/Translation Address" hexmask.long.byte 0x0 24.--31. 1. " WBA1 ,Window 1 Base Address" hexmask.long.byte 0x0 16.--23. 1. " WAM1 ,Window 1 Address Mask" textline " " hexmask.long.byte 0x0 8.--15. 1. " WTA1 ,Window 1 Translation Address" group 0xd78++0x3 line.long 0x0 "IW2BTAR,PCI Initiator Window 2 Base/Translation Address" hexmask.long.byte 0x0 24.--31. 1. " WBA2 ,Window 2 Base Address" hexmask.long.byte 0x0 16.--23. 1. " WAM2 ,Window 2 Address Mask" textline " " hexmask.long.byte 0x0 8.--15. 1. " WTA2 ,Window 2 Translation Address" group 0xd80++0x3 line.long 0x0 "IWCR,PCI Initiator Window Configuration Register" bitfld.long 0x0 27. " W0C3 ,Window 0 Control: IO/M#" "PCI memory,PCI I/O" bitfld.long 0x0 25.--26. " W0C[2:1] ,Window 0 Control: PCI Read Command" "Memory read,Memory read line,Memory read multiple,Reserved" textline " " bitfld.long 0x0 24. " W0C0 ,Window 0 Control: Enable" "Disabled,Enabled" bitfld.long 0x0 19. " W1C3 ,Window 1 Control: IO/M#" "PCI memory,PCI I/O" textline " " bitfld.long 0x0 17.--18. " W1C[2:1] ,Window 1 Control: PCI Read Command" "Memory read,Memory read line,Memory read multiple,Reserved" bitfld.long 0x0 16. " W1C0 ,Window 1 Control: Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " W2C3 ,Window 2 Control: IO/M#" "PCI memory,PCI I/O" bitfld.long 0x0 9.--10. " W2C[2:1] ,Window 2 Control: PCI Read Command" "Memory read,Memory read line,Memory read multiple,Reserved" textline " " bitfld.long 0x0 8. " W2C0 ,Window 2 Control: Enable" "Disabled,Enabled" group 0xd84++0x3 line.long 0x0 "ICR,PCI Initiator Configuration Register" bitfld.long 0x0 26. " REE ,Retry Error Enable" "Disabled,Enabled" bitfld.long 0x0 25. " IAE ,Initiator Abort Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 24. " TAE ,Target Abort Enable" "Disabled,Enabled" hexmask.long.byte 0x0 0.--7. 1. " MRET ,Maximum Retries" group 0xd88++0x3 line.long 0x0 "ISR,PCI Initiator Status Register" eventfld.long 0x0 26. " RE ,Retry Error" "No error,Error" eventfld.long 0x0 25. " IA ,Initiator Abort" "No error,Error" textline " " eventfld.long 0x0 24. " TA ,Target Abort" "No error,Error" group 0xd8c++0x3 line.long 0x0 "ARB,PCI Arbiter Register" bitfld.long 0x0 24. " ASR ,PCI Arbiter Soft Reset" "Released,Reset" group 0xdf8++0x3 line.long 0x0 "CAR,PCI Configuration Address Register" bitfld.long 0x0 31. " E ,Configuration Space Mapping Enable" "Disabled,Enabled" hexmask.long.byte 0x0 16.--23. 1. " BNR ,Bus Number" textline " " hexmask.long.byte 0x0 11.--15. 1. " DNR ,Device Number" hexmask.long.byte 0x0 8.--10. 1. " FNR ,Function Number" textline " " hexmask.long.byte 0x0 2.--7. 1. " dword ,DWORD address offset" width 0xb tree "PCI Communication System Interface Registers (MBAR + 0x3800)" width 7. sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x3800++0x3 line.long 0x0 "TPSR,Tx Packet Size" hexmask.long.long 0x0 0.--31. 1. " Packet_Size ,Number of bytes for transmit controller to send over PCI" else group 0x3800++0x3 line.long 0x0 "TPSR,Tx Packet Size" hexmask.long.word 0x0 16.--31. 1. " Packet_Size ,Number of bytes for transmit controller to send over PCI" endif elif (cpu()=="MGT5100") group 0x3800++0x3 line.long 0x0 "TPSR,Tx Packet Size" hexmask.long.word 0x0 16.--31. 1. " Packet_Size ,Number of bytes for transmit controller to send over PCI" endif group 0x3804++0x3 line.long 0x0 "TSAR,Tx Start Address" hexmask.long 0x0 0.--31. 1. " START_ADD ,PCI address to be presented for the first DWORD (32 bit) of a PCI packet" group 0x3808++0x3 line.long 0x0 "TTCR,Tx Transaction Control Register" hexmask.long.byte 0x0 24.--27. 1. " PCI_cmd ,PCI command to present during the address phase" hexmask.long.byte 0x0 16.--23. 1. " Max_Retries ,Maximum number of retries to permit 'perpacket'" textline " " hexmask.long.byte 0x0 8.--10. 1. " Max_Beats ,Desired number of PCI data beats to attempt" bitfld.long 0x0 4. " W ,Word Transfer" "Enabled,Disabled" textline " " bitfld.long 0x0 0. " DI ,Disabled address incrementing" "Enabled,Disabled" group 0x380c++0x3 line.long 0x0 "TER,Tx Enables" bitfld.long 0x0 31. " RC ,Reset controller" "No reset,Reset" bitfld.long 0x0 30. " RF ,Reset FIFO" "No reset,Reset" textline " " bitfld.long 0x0 28. " CM ,Continous mode" "Not active,Active" bitfld.long 0x0 27. " BE ,Bus error enable" "Disabled,Enabled" textline " " bitfld.long 0x0 24. " ME ,Master enable" "Disabled,Enabled" bitfld.long 0x0 21. " FEE ,FIFO master enable" "Disabled,Enabled" textline " " bitfld.long 0x0 20. " SE ,System error enable" "Disabled,Enabled" bitfld.long 0x0 19. " RE ,Retry abort enable" "Disabled,Enabled" textline " " bitfld.long 0x0 18. " TAE ,Target abort enable" "Disabled,Enabled" bitfld.long 0x0 17. " IAE ,Initiator abort enable" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " NE ,Normal termination enable" "Disabled,Enabled" rgroup 0x3810++0x3 line.long 0x0 "TNAR,Tx Next Address" hexmask.long 0x0 0.--31. 1. " Next_Address ,Next (unwritten) PCI address" rgroup 0x3814++0x3 line.long 0x0 "TLWR,Tx Last Word" hexmask.long 0x0 0.--31. 1. " Last_Word ,Last 32-bit data fetched from the FIFO" rgroup 0x3818++0x3 line.long 0x0 "TDCR,Tx Done Counts" hexmask.long.word 0x0 16.--31. 1. " Bytes_Done ,Number of bytes transmitted since the start of a packet" hexmask.long.word 0x0 0.--15. 1. " Packets_Done ,Number of packets transmitted" group 0x381c++0x3 line.long 0x0 "TSR,Tx Status" eventfld.long 0x0 24. " NT ,Normal termination" "Abnormal,Normal" eventfld.long 0x0 23. " BE3 ,Bus error type 3" "No error,Error" textline " " eventfld.long 0x0 22. " BE2 ,Bus error type 2" "No error,Error" eventfld.long 0x0 21. " BE1 ,Bus error type 1" "No error,Error" textline " " eventfld.long 0x0 20. " BE0 ,Bus error type 0" "No error,Error" eventfld.long 0x0 19. " SE ,System error" "No error,Error" textline " " eventfld.long 0x0 18. " RE ,Retry error" "No error,Error" eventfld.long 0x0 17. " TA ,Target abort" "No error,Error" textline " " eventfld.long 0x0 16. " IA ,Initiator Abort" "No error,Error" group 0x3840++0x3 line.long 0x0 "TFDR,Tx FIFO Data" hexmask.long 0x0 0.--31. 1. " FIFO_Data_Word ,Data port to the FIFO" group 0x3844++0x3 line.long 0x0 "TFSR,Tx FIFO Status" eventfld.long 0x0 22. " RXW ,Receive wait condition" "Not received,Received" eventfld.long 0x0 21. " UF ,UnderFlow" "No underflow,Underflow" textline " " eventfld.long 0x0 20. " OF ,OverFlow" "No overflow,Overflow" bitfld.long 0x0 19. " FR ,Frame raedy" "Not ready,Ready" textline " " bitfld.long 0x0 18. " FULL ,FIFO full" "Not full,Full" bitfld.long 0x0 17. " ALARM ,Alarm" "No alarm,Alarm" textline " " bitfld.long 0x0 16. " EMPTY ,FIFO empty" "Not empty,Empty" group 0x3848++0x3 line.long 0x0 "TFCR,Tx FIFO Conrol" hexmask.long.byte 0x0 24.--26. 1. " GR ,Granularity bits" bitfld.long 0x0 23. " IP_MASK ,Illegal Pointer Mask" "Not masked,Masked" textline " " bitfld.long 0x0 22. " FAE_MASK ,Illegal Pointer Mask" "Not masked,Masked" bitfld.long 0x0 21. " RXW_MASK ,Illegal Pointer Mask" "Not masked,Masked" textline " " bitfld.long 0x0 20. " U_MASK ,Illegal Pointer Mask" "Not masked,Masked" bitfld.long 0x0 19. " OF_MASK ,Illegal Pointer Mask" "Not masked,Masked" group 0x384c++0x3 line.long 0x0 "TFAR,Tx FIFO Alarm" hexmask.long.word 0x0 0.--11. 1. " Alarm ," group 0x3850++0x3 line.long 0x0 "TFRPR,Tx FIFO Read Pointer" hexmask.long.word 0x0 0.--11. 1. " ReadPtr ,Read address presented to the FIFO RAM" group 0x3854++0x3 line.long 0x0 "TFWPR,Tx FIFO Write Pointer" hexmask.long.word 0x0 0.--11. 1. " WritePtr ,Write address presented to the FIFO RAM" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x3880++0x3 line.long 0x0 "RPSR,Rx Packet Size" hexmask.long.long 0x0 0.--31. 1. " Packet_Size ,Number of bytes for receive controller to fetch over PCI" else group 0x3880++0x3 line.long 0x0 "RPSR,Rx Packet Size" hexmask.long.word 0x0 16.--31. 1. " Packet_Size ,Number of bytes for receive controller to fetch over PCI" endif elif (cpu()=="MGT5100") group 0x3880++0x3 line.long 0x0 "RPSR,Rx Packet Size" hexmask.long.word 0x0 16.--31. 1. " Packet_Size ,Number of bytes for receive controller to fetch over PCI" endif group 0x3884++0x3 line.long 0x0 "RSAR,Rx Start Address" hexmask.long 0x0 0.--31. 1. " START_ADD ,Starting Address for the current packet" group 0x3888++0x3 line.long 0x0 "RTCR,Rx Transaction Control Register" hexmask.long.byte 0x0 24.--27. 1. " PCI_cmd ,PCI command to present during the address phase" hexmask.long.byte 0x0 16.--23. 1. " Max_Retries ,Maximum number of retries to permit 'perpacket'" textline " " bitfld.long 0x0 12. " FB ,Full Burst" "Disabled,Enabled" hexmask.long.byte 0x0 8.--10. 1. " Max_Beats ,Desired number of PCI data beats to attempt" textline " " bitfld.long 0x0 4. " W ,Word Transfer" "Enabled,Disabled" bitfld.long 0x0 0. " DI ,Disabled address incrementing" "Enabled,Disabled" group 0x388c++0x3 line.long 0x0 "RER,Rx Enables" bitfld.long 0x0 31. " RC ,Reset controller" "No reset,Reset" bitfld.long 0x0 30. " RF ,Reset FIFO" "No reset,Reset" textline " " bitfld.long 0x0 29. " FE ,Flush enable" "Disabled,Enabled" bitfld.long 0x0 28. " CM ,Continous mode" "Not active,Active" textline " " bitfld.long 0x0 27. " BE ,Bus error enable" "Disabled,Enabled" bitfld.long 0x0 24. " ME ,Master enable" "Disabled,Enabled" textline " " bitfld.long 0x0 21. " FEE ,FIFO master enable" "Disabled,Enabled" bitfld.long 0x0 20. " SE ,System error enable" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " RE ,Retry abort enable" "Disabled,Enabled" bitfld.long 0x0 18. " TAE ,Target abort enable" "Disabled,Enabled" textline " " bitfld.long 0x0 17. " IAE ,Initiator abort enable" "Disabled,Enabled" bitfld.long 0x0 16. " NE ,Normal termination enable" "Disabled,Enabled" rgroup 0x3890++0x3 line.long 0x0 "RNAR,Rx Next Address" hexmask.long 0x0 0.--31. 1. " Next_Address ,Next (unread) PCI address" rgroup 0x3894++0x3 line.long 0x0 "RLWR,Rx Last Word" hexmask.long 0x0 0.--31. 1. " Last_Word ,Last 32-bit data fetched from the FIFO" rgroup 0x3898++0x3 line.long 0x0 "RDCR,Rx Done Counts" hexmask.long.word 0x0 16.--31. 1. " Bytes_Done ,Number of bytes received since the start of a packet" hexmask.long.word 0x0 0.--15. 1. " Packets_Done ,Number of packets received" group 0x389c++0x3 line.long 0x0 "RSR,Rx Status" eventfld.long 0x0 24. " NT ,Normal termination" "Abnormal,Normal" eventfld.long 0x0 23. " BE3 ,Bus error type 3" "No error,Error" textline " " eventfld.long 0x0 22. " BE2 ,Bus error type 2" "No error,Error" eventfld.long 0x0 21. " BE1 ,Bus error type 1" "No error,Error" textline " " eventfld.long 0x0 20. " FE ,FIFO error" "No error,Error" eventfld.long 0x0 19. " SE ,System error" "No error,Error" textline " " eventfld.long 0x0 18. " RE ,Retry error" "No error,Error" eventfld.long 0x0 17. " TA ,Target abort" "No error,Error" textline " " eventfld.long 0x0 16. " IA ,Initiator Abort" "No error,Error" group 0x38c0++0x3 line.long 0x0 "RFDR,Rx FIFO Data" hexmask.long 0x0 0.--31. 1. " FIFO_Data_Word ,Data port from the FIFO" group 0x38c4++0x3 line.long 0x0 "RFSR,Rx FIFO Status" eventfld.long 0x0 22. " RXW ,Receive wait condition" "Not received,Received" eventfld.long 0x0 21. " UF ,UnderFlow" "No underflow,Underflow" textline " " eventfld.long 0x0 20. " OF ,OverFlow" "No overflow,Overflow" bitfld.long 0x0 19. " FR ,Frame raedy" "Not ready,Ready" textline " " bitfld.long 0x0 18. " FULL ,FIFO full" "Not full,Full" bitfld.long 0x0 17. " ALARM ,Alarm" "No alarm,Alarm" textline " " bitfld.long 0x0 16. " EMPTY ,FIFO empty" "Not empty,Empty" group 0x38c8++0x3 line.long 0x0 "RFCR,Rx FIFO Conrol" hexmask.long.byte 0x0 24.--26. 1. " GR ,Granularity bits" bitfld.long 0x0 23. " IP_MASK ,Illegal Pointer Mask" "Not masked,Masked" textline " " bitfld.long 0x0 22. " FAE_MASK ,Illegal Pointer Mask" "Not masked,Masked" bitfld.long 0x0 21. " RXW_MASK ,Illegal Pointer Mask" "Not masked,Masked" textline " " bitfld.long 0x0 20. " U_MASK ,Illegal Pointer Mask" "Not masked,Masked" bitfld.long 0x0 19. " OF_MASK ,Illegal Pointer Mask" "Not masked,Masked" group 0x38cc++0x3 line.long 0x0 "RFAR,Rx FIFO Alarm" hexmask.long.word 0x0 0.--11. 1. " Alarm ," group 0x38d0++0x3 line.long 0x0 "RFRPR,Rx FIFO Read Pointer" hexmask.long.word 0x0 0.--11. 1. " ReadPtr ,Read address presented to the FIFO RAM" group 0x38d4++0x3 line.long 0x0 "RFWPR,Rx FIFO Write Pointer" hexmask.long.word 0x0 0.--11. 1. " WritePtr ,Write address presented to the FIFO RAM" width 0xb tree.end tree.end tree.open "Programmable Serial Controller Registers (MBAR + 0x2X00)" tree "PSC 1 (MBAR + 0x2000)" base anc:iobase()+2000 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree "PSC 2 (MBAR + 0x2200)" base anc:iobase()+2200 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree "PSC 3 (MBAR + 0x2400)" base anc:iobase()+2400 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree "PSC 4 (MBAR + 0x2600)" base anc:iobase()+2600 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree "PSC 5 (MBAR + 0x2800)" base anc:iobase()+2800 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree "PSC 6 (MBAR + 0x2C00)" base anc:iobase()+2C00 width 10. group 0x00++0x0 line.byte 0x0 "MR1/MR2,Mode Register 1/2" group 0x04++0x1 line.word 0x0 "SR/CSR,Status Register/Clock-Select Register" wgroup 0x08++0x0 line.byte 0x0 "CR,Command Register" bitfld.byte 0x0 4.--6. " MISC ,Miscellaneus Command" "No command,Reset mode register pointer,Reset receiver,Reset transmitter,Reset error status,Reset break change interrupt,Start break,Stop break" textline " " bitfld.byte 0x0 2.--3. " TC ,Transmitter Command" "No action taken,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x0 0.--1. " RC ,Receiver Command" "No action taken,Receiver enabled,Receiver disabled,Reserved" hgroup 0x0c++0x3 hide.long 0x0 "RB/TB,Rx Buffer Register/Tx Buffer Register" in width 10. group 0x10++0x0 line.byte 0x0 "IPCR/ACR,Input Port Change Register/Auxiliary Control Register" group 0x14++0x1 line.word 0x0 "ISR/IMR,Interrupt Status Register/Interrupt Mask Register" wgroup 0x18++0x0 line.byte 0x0 "CTUR,Counter Timer Upper Register" hexmask.byte 0x0 0.--7. 1. " CTUR ,Code" wgroup 0x1c++0x0 line.byte 0x0 "CTLR,Counter Timer Lower Register" hexmask.byte 0x0 0.--7. 1. " CTLR ,UART baud rate prescale value" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x20++0x3 line.long 0x0 "CCR,Codec Clock Register" hexmask.long.byte 0x0 24.--31. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.long.byte 0x0 16.--23. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" textline " " hexmask.long.byte 0x0 8.--15. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" group 0x24++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register" hexmask.long.word 0x0 16.--25. 1. " TX_Slots ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_Slots ,Expected Receive Slots" group 0x28++0x3 line.long 0x0 "AC97CMD, AC97 Command Register" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 target control address" textline " " hexmask.long.byte 0x0 16.--23. 1. " AC97_CD ,AC97 Command Data" hexmask.long.byte 0x0 8.--15. 1. " AC97_CD ,AC97 Command Data" rgroup 0x2c++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" else group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif elif (cpu()=="MGT5100") group 0x20++0x1 line.word 0x0 "CCR,Codec Clock Register" hexmask.word.byte 0x0 8.--15. 1. " FrameSyncDiv ,Codec: Frame Sync Divider, Codec/SPI: delay before SCK" hexmask.word.byte 0x0 0.--7. 1. " BitClkDiv ,Codec: Bit Clock Divider, SPI: Baud Rate, MIR/FIR: IrDA Clock" endif ;group 0x30++0x0 ; line.byte 0x0 "IVR,Interrupt Vector Register" rgroup 0x34++0x0 line.byte 0x0 "IP,Input Port" bitfld.byte 0x0 7. " LPWR ,AC97 Low power mode in AC97 mode" "Low power,Normal" bitfld.byte 0x0 6. " TGL ,AC97/Codec Test usage. Toggle by frame sync" "Low,High" textline " " bitfld.byte 0x0 1. " DCD ,Current state of the /DCD input" "Low,High" bitfld.byte 0x0 0. " CTS ,Current state of the /CTS input" "Low,High" wgroup 0x38++0x0 line.byte 0x0 "OP1,Output Port 1 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Asserted" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Asserted" wgroup 0x3c++0x0 line.byte 0x0 "OP0,Output Port 0 Bit Set" bitfld.byte 0x0 1. " RES ,Assert RES output" "No operation,Negated" bitfld.byte 0x0 0. " RTS ,AC97: Reserved, other Modes: Asserts RTS Output" "No operation,Negated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " I2S ,Codec: I2S mode" "No I2S,I2S" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 9. " ESAI ,Codec: Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 8. " EnAC97 ,Codec: Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" textline " " bitfld.long 0x0 2. " Disable_EOF ,Disable EOF generation" "Enabled,Disabled" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 5. " INV_RX ,SIR/MIR/FIR: Invert the RX line" "Not inverted,Inverted" textline " " bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" else group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif elif (cpu()=="MGT5100") group 0x40++0x3 line.long 0x0 "SICR,Serial Interface Control Register" bitfld.long 0x0 23. " ACRB ,AC97: Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 22. " AWR ,AC97: Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 21. " DTS1 ,Codec: Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 20. " SHDIR ,Codec: Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 16.--19. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD ignored,MIR,FIR,Codec: 24-bit,UART: /DCD effective,Codec: 8-bit,Codec: 16-bit,AC97,SIR: /DCD effective,MIR,FIR,Codec: 32-bit" bitfld.long 0x0 15. " GenClk ,Codec,MIR/FIR: Generate Bit Clock and Frame Sync" "External,Internal" textline " " bitfld.long 0x0 14. " MultiWd ,Codec: Multi Word mode" "One data,More data" bitfld.long 0x0 13. " ClkPol ,Codec: Bit Clock Polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x0 12. " SyncPol ,Codec Frame Sync Polarity" "Low,High" bitfld.long 0x0 11. " CellSlave ,Codec: Cell Phone Slave" "Not slave,Slave" textline " " bitfld.long 0x0 10. " Cell2xClk ,Codec Cell Slave 2x Clock Frequency" "Bit clock,2x Bit clock" textline " " bitfld.long 0x0 7. " SPI ,Codec: SPI mode" "Not SPI, SPI" bitfld.long 0x0 6. " MSTR ,Codec: SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 5. " CPOL ,Codec SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 4. " CPHA ,Codec SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 3. " UseEOF ,Codec: Use End-of-Frame" "Up to 4bytes,Multiple" group 0x44++0x0 line.byte 0x0 "IRCR1,Infrared Control 1" bitfld.byte 0x0 2. " FD ,SIR/MIR/FIR Full duplex enable" "Disabled,Enabled" bitfld.byte 0x0 1. " SIPEN ,MIR/FIR Send SIP enable after every frame" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " SPUL ,SIR SIR pulse width" "3/16 bit duration,1.6us" endif group 0x48++0x0 line.byte 0x0 "IRCR2,Infrared Control 2" bitfld.byte 0x0 2. " SIPREQ ,MIR/FIR Request to send SIP" "No operation,Sent" bitfld.byte 0x0 1. " ABORT ,MIR/FIR Abort output" "No abort,Abort" textline " " bitfld.byte 0x0 0. " NXTEOF ,SIR/MIR/FIR Next is the last byte" "Not last,Last" group 0x4c++0x0 line.byte 0x0 "IRSDR,Infrared SIR Divide Register" hexmask.byte 0x0 0.--7. 1. " IRSTIM ,SIR Timer counter value for 1.6us pulse" group 0x50++0x0 line.byte 0x0 "IRMDR,Infrared MIR Divide Register" bitfld.byte 0x0 7. " FREQ ,MIR 0.576 M bps mode" "1.152Mbps,0.576Mbps" hexmask.byte 0x0 0.--6. 1. " M_FDIV ,MIR Clock divide ratio in MIR mode" group 0x54++0x0 line.byte 0x0 "IRFDR,Infrared FIR Divide Register" bitfld.byte 0x0 0.--3. " F_FDIV ,FIR Clock divide ratio in FIR mode" "Reserved,Reserved,Reserved,32MHz,40MHz,48MHz,56MHz,64MHz,72MHz,80MHz,88MHz,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup 0x58++0x1 line.word 0x0 "RFNUM,Rx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" rgroup 0x5c++0x1 line.word 0x0 "TFNUM,Tx FIFO Number of Data" hexmask.word.byte 0x0 0.--8. 1. " COUNT ,Number of data bytes in the Rx FIFO" group 0x60++0x1 line.word 0x0 "RFDATA,Rx FIFO Data" group 0x64++0x1 line.word 0x0 "RFSTAT,Rx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x68++0x0 line.byte 0x0 "RFCNTL,Rx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x6e++0x1 line.word 0x0 "RFALARM,Rx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x72++0x1 line.word 0x0 "RFRPTR,Rx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x76++0x1 line.word 0x0 "RFWPTR,Rx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x7a++0x1 line.word 0x0 "RFLRFPTR,Rx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x7c++0x1 line.word 0x0 "RFLWFPTR,Rx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x80++0x3 line.long 0x0 "TFDATA,Tx FIFO Data" group 0x84++0x1 line.word 0x0 "TFSTAT,Tx FIFO Status" hexmask.word.byte 0x0 8.--11. 1. " Frame[3:0] ,Frame indicator" eventfld.word 0x0 6. " Error ,FIFO error" "No error,Error" textline " " eventfld.word 0x0 5. " UF ,Underflow" "No underflow,Underflow" eventfld.word 0x0 4. " OF ,Overflow" "No overflow,Overflow" textline " " bitfld.word 0x0 3. " FR ,Frame ready" "Not ready,Ready" bitfld.word 0x0 2. " FULL ,FIFO completely full of data" "Not full,Full" textline " " bitfld.word 0x0 1. " ALARM ,FIFO is requesting service from either BestComm or CPU" "No alarm,Alarm" bitfld.word 0x0 0. " EMPTY ,FIFO completely empty" "Not empty,Empty" group 0x88++0x0 line.byte 0x0 "TFCNTL,Tx FIFO Control" bitfld.byte 0x0 5. " WFR ,Write frame" "Low,High" bitfld.byte 0x0 4. " COMP ,Re-enable requests on frame transmission completion" "Disabled,Enabled" textline " " bitfld.byte 0x0 3. " FRAME ,Frame mode enable" "Disabled,Enabled" hexmask.byte 0x0 0.--2. 1. " GR[2:0] ,Last transfer granularity" group 0x8e++0x1 line.word 0x0 "TFALARM,Tx FIFO Alarm" hexmask.word 0x0 0.--11. 1. " ALARM ,'Almost full' threshold level" group 0x92++0x1 line.word 0x0 "TFRPTR,Tx FIFO Read Pointer" hexmask.word 0x0 0.--11. 1. " R_PTR ,Read pointer" group 0x96++0x1 line.word 0x0 "TFWPTR,Tx FIFO Write Pointer" hexmask.word 0x0 0.--11. 1. " W_PTR ,Write pointer" group 0x9a++0x1 line.word 0x0 "TFLRFPTR,Tx FIFO Last Read Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" group 0x9c++0x1 line.word 0x0 "TFLWFPTR,Tx FIFO Last Write Frame PTR" hexmask.word 0x0 0.--11. 1. " LFP ,Last Frame Pointer" width 0xb tree.end tree.end ;Default MBAR Address base anc:iobase() tree "RTC Interface Registers (MBAR + 0x0800)" width 6. group 0x800++0x3 line.long 0x0 "TSET,Time Set" bitfld.long 0x0 25. " set_time ,New time to be programmed into the RTC" "Not set,Set" bitfld.long 0x0 24. " pause_time ,Perform time update" "Normal,Update" textline " " bitfld.long 0x0 21. " SlctHour ,Hour output format" "24-hour,12-hour" bitfld.long 0x0 16.--20. " C24Hour_set ,Hour in 24-hour format written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x0 8.--13. " Minute_set ,Minute written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0 0.--5. " Second_set ,Second written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,Reserved,Reserved,Reserved,Reserved" group 0x804++0x3 line.long 0x0 "DSET,Date Set" bitfld.long 0x0 25. " set_date ,New date to be programmed into the RTC" "Not set,Set" bitfld.long 0x0 24. " pause_date ,Perform date update" "Normal,Update" textline " " bitfld.long 0x0 16.--20. " Month_set ,New month written in RTC" "Reserved,Jan,Febr,Mar,Apr,May,June,July,Aug,Sept,Oct,Nov,Dec,?..." bitfld.long 0x0 8.--10. " Weekday_set ,New weekday written in RTC" "Reserved,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x0 0.--4. " Date_set ,New date written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group 0x808++0x3 line.long 0x0 "NYSW,New Year and Stopwatch" bitfld.long 0x0 24. " write_SW ,Stopwatch minute countdown begin" "Stopped,Started" hexmask.long.byte 0x0 16.--26. 1. " SW_set ,Number of minutes to be written into stopwatch, max is 255" textline " " hexmask.long.word 0x0 8.--11. 1. " Year_set ,New year written in RTC after successful state machine transition by set_date and pause_date bits" group 0x80c++0x3 line.long 0x0 "ALIE,Alarm and Interrupt Enable" bitfld.long 0x0 24. " Alm_enable ,Alarm Enable bit for once-a-day Alarm" "Disabled,Enabled" bitfld.long 0x0 16.--20. " Alm_24Hset ,Hour setting (in 24 hour format)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x0 8.--13. " Alm_Min_set ,Minute setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0 3. " MPEb ,Master Periodic Enable bar" "Enabled,Disabled" textline " " bitfld.long 0x0 2. " IntEn_day ,Enable bit of periodic interrupts at midnight rollover" "Disabled,Enabled" bitfld.long 0x0 1. " IntEn_min ,Enable bit of periodic interrupts at minute rollover" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " IntEn_sec ,Enable bit of periodic interrupts at second rollover" "Disabled,Enabled" rgroup 0x810++0x3 line.long 0x0 "CTIM,Current Time" bitfld.long 0x0 16.--20. " Hour ,Hour format can be either 24-hour or 12-hour with AM/PM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0 8.--13. " Minute ,Shows minutes in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x0 0.--5. " Second ,Shows seconds in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,Reserved,Reserved,Reserved,Reserved" rgroup 0x814++0x3 line.long 0x0 "CDAT,Current Date" bitfld.long 0x0 24.--27. " Month ,Shows current month" "Reserved,Jan,Febr,Mar,Apr,May,June,July,Aug,Sept,Oct,Nov,Dec,?..." bitfld.long 0x0 21.--23. " Weekday ,Indicates day of week" "Reserved,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x0 16.--20. " Day ,Shows current date" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 0.--11. 1. " Year ,Shows current year, max is 4052" group 0x818++0x3 line.long 0x0 "ALSI,Alarm and Stopwatch Interrupt" eventfld.long 0x0 24. " Int_alm ,Enabled once-a-day Alarm has occurred" "Not occurred,Occurred" eventfld.long 0x0 16. " Int_SW ,Stopwatch expiration has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x0 8. " Alm_status ,Once-a-day Alarm has occurred" "Not occurred,Occurred" hexmask.long.byte 0x0 0.--7. 1. " SW_min ,Minutes remaining in stopwatch" group 0x81c++0x3 line.long 0x0 "PIBE,Periodic Interrupt and Bus Error" eventfld.long 0x0 24. " Bus_error_1 ,Internal status register" "No error,Error" eventfld.long 0x0 16. " Int_day ,Periodic interrupt at midnight" "Not occurred,Occurred" textline " " eventfld.long 0x0 8. " Int_min ,Periodic interrupt at each minute rollover" "Not occurred,Occurred" eventfld.long 0x0 0. " Int_sec ,Periodic interrupt at each second rollover" "Not occurred,Occurred" group 0x820++0x3 line.long 0x0 "TEST,Test Register" hexmask.long.byte 0x0 24.--30. 1. " PTERM ,Prescale Termination value" hexmask.long.byte 0x0 16.--23. 1. " ETERM ,External Termination value" width 0xb tree.end tree "BestComm DMA Registers (MBAR + 0x1200)" width 9. group 0x1200++0x3 line.long 0x0 "TaskBar,Task Bar" hexmask.long 0x0 0.--31. 1. " taskBar ,Pointer to the base address of the Task Table" group 0x1204++0x3 line.long 0x0 "CurPtr,Current Pointer" hexmask.long 0x0 0.--31. 1. " currentPointer ,Address of the currently executing DMA descriptor" group 0x1208++0x3 line.long 0x0 "EndPtr,End Pointer" hexmask.long 0x0 0.--31. 1. " endPointer ,Address of the last descriptor in the currently executing SDMA task" group 0x120c++0x3 line.long 0x0 "VPtr,Variable Pointer" hexmask.long 0x0 0.--31. 1. " variablePointer ,Starting address of the variable table for the currently executing task" group 0x1210++0x3 line.long 0x0 "IntV1/2,,Interrupt Vector, PTD Control" bitfld.long 0x0 28.--31. " VectorA ,Interrupt Vector 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--27. " INA ,Interrupt Vector 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " VectorB ,Interrupt Vector 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " INB ,Interrupt Vector 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " T/I ,Task/Initiator Priority" "Initiator,Task" bitfld.long 0x0 14. " TEA ,TEA" "Not ignored,Ignored" textline " " bitfld.long 0x0 13. " HE ,HE" "Disabled,Allowed" bitfld.long 0x0 0. " PE ,PE Prefetch Disable" "Enabled,Disabled" group 0x1214++0x3 line.long 0x0 "IntPend,Interrupt Pending Register" bitfld.long 0x0 31. " DBG ,Debug" "Low,High" bitfld.long 0x0 28. " TEA ,TEA" "Not received,Received" textline " " hexmask.long.byte 0x0 24.--27. 1. " ETN[3:0] ,Error Task Number" hexmask.long.byte 0x0 16.--23. 1. " EU[7:0] ,Execution Unit" textline " " bitfld.long 0x0 15. " TASK[15] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 14. " TASK[14] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 13. " TASK[13] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 12. " TASK[12] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 11. " TASK[11] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 10. " TASK[10] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 9. " TASK[9] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 8. " TASK[8] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 7. " TASK[7] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 6. " TASK[6] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 5. " TASK[5] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 4. " TASK[4] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 3. " TASK[3] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 2. " TASK[2] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" textline " " bitfld.long 0x0 1. " TASK[1] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" bitfld.long 0x0 0. " TASK[0] ,Interrupt source defined by the task number or execution unit" "Not pending,Pending" group 0x1218++0x3 line.long 0x0 "IntMask,Interrupt Mask" bitfld.long 0x0 31. " DBG ,Debug" "Not masked,Masked" bitfld.long 0x0 28. " TEA_MSK ,TEA Mask" "Not masked,Masked" textline " " bitfld.long 0x0 19. " EU[3] ,Execution Unit" "Not masked,Masked" bitfld.long 0x0 15. " TASK[15] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 14. " TASK[14] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 13. " TASK[13] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 12. " TASK[12] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 11. " TASK[11] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 10. " TASK[10] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 9. " TASK[9] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 8. " TASK[8] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 7. " TASK[7] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 6. " TASK[6] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 5. " TASK[5] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 4. " TASK[4] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 3. " TASK[3] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 2. " TASK[2] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" bitfld.long 0x0 1. " TASK[1] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" textline " " bitfld.long 0x0 0. " TASK[0] ,Interrupt source defined by the task number or execution unit" "Not masked,Masked" group 0x121c++0x1 line.word 0x0 "TCR0,Task Control 0" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x121e++0x1 line.word 0x0 "TCR1,Task Control 1" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1220++0x1 line.word 0x0 "TCR2,Task Control 2" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1222++0x1 line.word 0x0 "TCR3,Task Control 3" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1224++0x1 line.word 0x0 "TCR4,Task Control 4" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1226++0x1 line.word 0x0 "TCR5,Task Control 5" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1228++0x1 line.word 0x0 "TCR6,Task Control 6" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x122a++0x1 line.word 0x0 "TCR7,Task Control 7" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x122c++0x1 line.word 0x0 "TCR8,Task Control 8" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x122e++0x1 line.word 0x0 "TCR9,Task Control 9" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1230++0x1 line.word 0x0 "TCRA,Task Control A" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1232++0x1 line.word 0x0 "TCRB,Task Control B" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1234++0x1 line.word 0x0 "TCRC,Task Control C" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1236++0x1 line.word 0x0 "TCRD,Task Control D" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x1238++0x1 line.word 0x0 "TCRE,Task Control E" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x123a++0x1 line.word 0x0 "TCRF,Task Control F" bitfld.word 0x0 15. " EN ,Task Enable" "Disabled,Enabled" bitfld.word 0x0 14. " Val ,Initiator Number is Valid" "Not valid,Valid" textline " " bitfld.word 0x0 13. " Alw ,Decode of the always initiator" "Not used,Used" hexmask.word.byte 0x0 8.--12. 1. " IN[4:0] ,Initiator number from task descriptor" textline " " bitfld.word 0x0 7. " AutoStart ,Task Start" "Not started,Started" bitfld.word 0x0 6. " HighEn ,High Priority Task Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 5. " Hold ,Hold initiator number" "Update,Hold" hexmask.word.byte 0x0 0.--3. 1. " AS[3:0] ,Auto-Start Task Number" group 0x123c++0x1f line.byte 0x0 "IPR0 ,Initiator Priority 0 " bitfld.byte 0x0 7. " IPR_Hold0 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x0 0.--2. 1. " Prior[2:0]0 ,Initiator/Task priority level" line.byte 0x1 "IPR1 ,Initiator Priority 1 " bitfld.byte 0x1 7. " IPR_Hold1 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1 0.--2. 1. " Prior[2:0]1 ,Initiator/Task priority level" line.byte 0x2 "IPR2 ,Initiator Priority 2 " bitfld.byte 0x2 7. " IPR_Hold2 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x2 0.--2. 1. " Prior[2:0]2 ,Initiator/Task priority level" line.byte 0x3 "IPR3 ,Initiator Priority 3 " bitfld.byte 0x3 7. " IPR_Hold3 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x3 0.--2. 1. " Prior[2:0]3 ,Initiator/Task priority level" line.byte 0x4 "IPR4 ,Initiator Priority 4 " bitfld.byte 0x4 7. " IPR_Hold4 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x4 0.--2. 1. " Prior[2:0]4 ,Initiator/Task priority level" line.byte 0x5 "IPR5 ,Initiator Priority 5 " bitfld.byte 0x5 7. " IPR_Hold5 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x5 0.--2. 1. " Prior[2:0]5 ,Initiator/Task priority level" line.byte 0x6 "IPR6 ,Initiator Priority 6 " bitfld.byte 0x6 7. " IPR_Hold6 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x6 0.--2. 1. " Prior[2:0]6 ,Initiator/Task priority level" line.byte 0x7 "IPR7 ,Initiator Priority 7 " bitfld.byte 0x7 7. " IPR_Hold7 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x7 0.--2. 1. " Prior[2:0]7 ,Initiator/Task priority level" line.byte 0x8 "IPR8 ,Initiator Priority 8 " bitfld.byte 0x8 7. " IPR_Hold8 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x8 0.--2. 1. " Prior[2:0]8 ,Initiator/Task priority level" line.byte 0x9 "IPR9 ,Initiator Priority 9 " bitfld.byte 0x9 7. " IPR_Hold9 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x9 0.--2. 1. " Prior[2:0]9 ,Initiator/Task priority level" line.byte 0xA "IPR10,Initiator Priority 10" bitfld.byte 0xA 7. " IPR_Hold10 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xA 0.--2. 1. " Prior[2:0]10 ,Initiator/Task priority level" line.byte 0xB "IPR11,Initiator Priority 11" bitfld.byte 0xB 7. " IPR_Hold11 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xB 0.--2. 1. " Prior[2:0]11 ,Initiator/Task priority level" line.byte 0xC "IPR12,Initiator Priority 12" bitfld.byte 0xC 7. " IPR_Hold12 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xC 0.--2. 1. " Prior[2:0]12 ,Initiator/Task priority level" line.byte 0xD "IPR13,Initiator Priority 13" bitfld.byte 0xD 7. " IPR_Hold13 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xD 0.--2. 1. " Prior[2:0]13 ,Initiator/Task priority level" line.byte 0xE "IPR14,Initiator Priority 14" bitfld.byte 0xE 7. " IPR_Hold14 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xE 0.--2. 1. " Prior[2:0]14 ,Initiator/Task priority level" line.byte 0xF "IPR15,Initiator Priority 15" bitfld.byte 0xF 7. " IPR_Hold15 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0xF 0.--2. 1. " Prior[2:0]15 ,Initiator/Task priority level" line.byte 0x10 "IPR16,Initiator Priority 16" bitfld.byte 0x10 7. " IPR_Hold16 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x10 0.--2. 1. " Prior[2:0]16 ,Initiator/Task priority level" line.byte 0x11 "IPR17,Initiator Priority 17" bitfld.byte 0x11 7. " IPR_Hold17 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x11 0.--2. 1. " Prior[2:0]17 ,Initiator/Task priority level" line.byte 0x12 "IPR18,Initiator Priority 18" bitfld.byte 0x12 7. " IPR_Hold18 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x12 0.--2. 1. " Prior[2:0]18 ,Initiator/Task priority level" line.byte 0x13 "IPR19,Initiator Priority 19" bitfld.byte 0x13 7. " IPR_Hold19 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x13 0.--2. 1. " Prior[2:0]19 ,Initiator/Task priority level" line.byte 0x14 "IPR20,Initiator Priority 20" bitfld.byte 0x14 7. " IPR_Hold20 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x14 0.--2. 1. " Prior[2:0]20 ,Initiator/Task priority level" line.byte 0x15 "IPR21,Initiator Priority 21" bitfld.byte 0x15 7. " IPR_Hold21 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x15 0.--2. 1. " Prior[2:0]21 ,Initiator/Task priority level" line.byte 0x16 "IPR22,Initiator Priority 22" bitfld.byte 0x16 7. " IPR_Hold22 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x16 0.--2. 1. " Prior[2:0]22 ,Initiator/Task priority level" line.byte 0x17 "IPR23,Initiator Priority 23" bitfld.byte 0x17 7. " IPR_Hold23 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x17 0.--2. 1. " Prior[2:0]23 ,Initiator/Task priority level" line.byte 0x18 "IPR24,Initiator Priority 24" bitfld.byte 0x18 7. " IPR_Hold24 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x18 0.--2. 1. " Prior[2:0]24 ,Initiator/Task priority level" line.byte 0x19 "IPR25,Initiator Priority 25" bitfld.byte 0x19 7. " IPR_Hold25 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x19 0.--2. 1. " Prior[2:0]25 ,Initiator/Task priority level" line.byte 0x1A "IPR26,Initiator Priority 26" bitfld.byte 0x1A 7. " IPR_Hold26 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1A 0.--2. 1. " Prior[2:0]26 ,Initiator/Task priority level" line.byte 0x1B "IPR27,Initiator Priority 27" bitfld.byte 0x1B 7. " IPR_Hold27 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1B 0.--2. 1. " Prior[2:0]27 ,Initiator/Task priority level" line.byte 0x1C "IPR28,Initiator Priority 28" bitfld.byte 0x1C 7. " IPR_Hold28 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1C 0.--2. 1. " Prior[2:0]28 ,Initiator/Task priority level" line.byte 0x1D "IPR29,Initiator Priority 29" bitfld.byte 0x1D 7. " IPR_Hold29 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1D 0.--2. 1. " Prior[2:0]29 ,Initiator/Task priority level" line.byte 0x1E "IPR30,Initiator Priority 30" bitfld.byte 0x1E 7. " IPR_Hold30 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1E 0.--2. 1. " Prior[2:0]30 ,Initiator/Task priority level" line.byte 0x1F "IPR31,Initiator Priority 31" bitfld.byte 0x1F 7. " IPR_Hold31 ,Keep current priority of initiator" "Higher,Current" hexmask.byte.byte 0x1F 0.--2. 1. " Prior[2:0]31 ,Initiator/Task priority level" width 9. group 0x125c++0x3 line.long 0x0 "RMC,Requestor Mux Control" bitfld.long 0x0 30.--31. " Req31 ,Requestor" "Requestor,No active requestor,No active requestor,Always requestor 31" bitfld.long 0x0 28.--29. " Req30 ,Requestor" "Requestor,No active requestor,No active requestor,Always requestor 30" textline " " bitfld.long 0x0 26.--27. " Req29 ,Requestor" "Requestor,No active requestor,No active requestor,Always requestor 29" bitfld.long 0x0 24.--25. " Req28 ,Requestor" "Requestor,No active requestor,No active requestor,Always requestor 28" textline " " bitfld.long 0x0 22.--23. " Req27 ,Requestor" "Requestor,No active requestor,No active requestor,Always requestor 27" bitfld.long 0x0 20.--21. " Req26 ,Requestor (IrDA TX)" "Requestor,No active requestor,No active requestor,Always requestor 26" textline " " bitfld.long 0x0 18.--19. " Req25 ,Requestor (IrDA RX)" "Requestor,No active requestor,No active requestor,Always requestor 25" bitfld.long 0x0 16.--17. " Req24 ,Requestor (I2C1 TX)" "Requestor,No active requestor,No active requestor,Always requestor 24" textline " " bitfld.long 0x0 14.--15. " Req23 ,Requestor (I2C1 RX)" "Requestor,No active requestor,No active requestor,Always requestor 23" bitfld.long 0x0 12.--13. " Req22 ,Requestor (I2C2 TX)" "Requestor,No active requestor,No active requestor,Always requestor 22" textline " " bitfld.long 0x0 10.--11. " Req21 ,Requestor (I2C2 RX)" "Requestor,No active requestor,No active requestor,Always requestor 21" bitfld.long 0x0 8.--9. " Req20 ,Requestor (PSC2 TX)" "Requestor,No active requestor,No active requestor,Always requestor 20" textline " " bitfld.long 0x0 6.--7. " Req19 ,Requestor (PSC2 RX)" "Requestor,No active requestor,No active requestor,Always requestor 19" bitfld.long 0x0 4.--5. " Req18 ,Requestor (PSC4 TX)" "Requestor,No active requestor,No active requestor,Always requestor 18" textline " " bitfld.long 0x0 2.--3. " Req17 ,Requestor (PSC4 RX)" "Requestor,No active requestor,No active requestor,Always requestor 17" bitfld.long 0x0 0.--1. " Req16 ,Requestor (LP)" "Requestor,No active requestor,No active requestor,Always requestor 16" width 9. group 0x1260++0x3 line.long 0x0 "TS0,Task Size 0" bitfld.long 0x0 30.--31. " src0Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 28.--29. " dst0Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 26.--27. " src1Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 24.--25. " dst1Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 22.--23. " src2Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 20.--21. " dst2Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 18.--19. " src3Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 16.--17. " dst3Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 14.--15. " src4Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 12.--13. " dst4Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 10.--11. " src5Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 8.--9. " dst5Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 6.--7. " src6Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 4.--5. " dst6Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 2.--3. " src7Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 0.--1. " dst7Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" group 0x1264++0x3 line.long 0x0 "TS1,Task Size 1" bitfld.long 0x0 30.--31. " src8Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 28.--29. " dst8Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 26.--27. " src9Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 24.--25. " dst9Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 22.--23. " src10Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 20.--21. " dst10Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 18.--19. " src11Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 16.--17. " dst11Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 14.--15. " src12Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 12.--13. " dst12Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 10.--11. " src13Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 8.--9. " dst13Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 6.--7. " src14Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 4.--5. " dst14Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" textline " " bitfld.long 0x0 2.--3. " src15Size[1:0] ,Task Source Size" "Word (32bit),Byte,Word,Word" bitfld.long 0x0 0.--1. " dst15Size[1:0] ,Task Destination Size" "Word (32bit),Byte,Word,Word" hgroup 0x1268++0x3 hide.long 0x0 "RES1,Reserved Register 1" hgroup 0x126c++0x3 hide.long 0x0 "RES2,Reserved Register 2" group 0x1270++0x3 line.long 0x0 "DMC1,Debug Module Comparator 1" hexmask.long.long 0x0 0.--31. 1. " Value1 ,Debug Module Comparator 1 Value" group 0x1274++0x3 line.long 0x0 "DMC2,Debug Module Comparator 2" hexmask.long.long 0x0 0.--31. 1. " Value2 ,Debug Module Comparator 2 Value" group 0x1278++0x3 line.long 0x0 "DMCTRL,Debug Modulator Control" bitfld.long 0x0 31. " Block_Tasks[15] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 30. " Block_Tasks[14] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 29. " Block_Tasks[13] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 28. " Block_Tasks[12] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 27. " Block_Tasks[11] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 26. " Block_Tasks[10] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 25. " Block_Tasks[9] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 24. " Block_Tasks[8] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 23. " Block_Tasks[7] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 22. " Block_Tasks[6] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 21. " Block_Tasks[5] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 20. " Block_Tasks[4] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 19. " Block_Tasks[3] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 18. " Block_Tasks[2] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 17. " Block_Tasks[1] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" bitfld.long 0x0 16. " Block_Tasks[0] ,Block that task with detection of a breakpoint" "Not blocked,Blocked" textline " " bitfld.long 0x0 15. " AA ,Triggered bit dbgStatusReg[16] automatically reset to 0" "Disabled,Enabled" bitfld.long 0x0 14. " B ,Breakpoint" "Disabled,Enabled" textline " " bitfld.long 0x0 11.--13. " CompType1 ,Comparator 1 type" "Uninitialized,Write address,Read address,Current pointer,Task #,Reserved,Reserved,Reserved" bitfld.long 0x0 8.--10. " CompType2 ,Comparator 2 type" "Uninitialized,Write address,Read address,Current pointer,Task #,Counter value,Reserved,Reserved" textline " " bitfld.long 0x0 7. " and_or ,AND/OR" "OR,AND" bitfld.long 0x0 6. " EU_breakpoint[3] ,Breakpoint occurred" "Not occurred,Occurred" textline " " bitfld.long 0x0 5. " EU_breakpoint[2] ,Breakpoint occurred" "Not occurred,Occurred" bitfld.long 0x0 4. " EU_breakpoint[1] ,Breakpoint occurred" "Not occurred,Occurred" textline " " bitfld.long 0x0 3. " EU_breakpoint[0] ,Breakpoint occurred" "Not occurred,Occurred" bitfld.long 0x0 2. " E ,Enable interrupt breakpoint" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " I ,Enable internal breakpoint" "Disabled,Enabled" bitfld.long 0x0 0. " EB ,Master External Breakpoint" "Disabled,Enabled" group 0x127c++0x3 line.long 0x0 "DMSR,Debug Module Status" eventfld.long 0x0 18. " I ,Interrupt taken" "No interrupt,Interrupt" eventfld.long 0x0 17. " E ,External Breakpoint" "No breakpoint,Breakpoint" textline " " eventfld.long 0x0 16. " T ,Triggered (dbgStatusReg[16])" "Armed/Normal,Triggered/Debug" bitfld.long 0x0 15. " dbgStaReg[15] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 14. " dbgStaReg[14] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 13. " dbgStaReg[13] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 13. " dbgStaReg[12] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 12. " dbgStaReg[11] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 10. " dbgStaReg[10] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 9. " dbgStaReg[9] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 8. " dbgStaReg[8] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 7. " dbgStaReg[7] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 6. " dbgStaReg[6] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 5. " dbgStaReg[5] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 4. " dbgStaReg[4] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 3. " dbgStaReg[3] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 2. " dbgStaReg[2] ,Debug state of the task number" "Unblocked,Blocked" bitfld.long 0x0 1. " dbgStaReg[1] ,Debug state of the task number" "Unblocked,Blocked" textline " " bitfld.long 0x0 0. " dbgStaReg[0] ,Debug state of the task number" "Unblocked,Blocked" width 0xb tree.end tree "BestComm DMA LocalPlus Registers (MBAR + 0x3C00)" width 6. group 0x3c00++0x3 "BLPC Registers" line.long 0x0 "PSR,Packet Size Register" bitfld.long 0x0 24. " Restart ," "Not restarted, Restarted" hexmask.long 0x0 0.--23. 1. " PacketSize ,Number of bytes SCLPC transact before going idle and waiting for a Restart" group 0x3c04++0x3 line.long 0x0 "SAR,Start Address Register" hexmask.long.long 0x0 0.--31. 1. " Start_address ,Address of the first byte in the packet to send" group 0x3c08++0x3 line.long 0x0 "CTR,Control Register" hexmask.long.byte 0x0 24.--26. 1. " CSX ,Chip Select number associated with each DMA transaction" bitfld.long 0x0 17. " Flush ,Enables the assertion of SCLPC requestor" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " RWb ,Read - Write bar" "Write,Read" bitfld.long 0x0 8. " DAI ,Disable Auto Increment" "Enabled,Disabled" textline " " bitfld.long 0x0 0.--3. " BPT ,Bytes Per Transaction" "Not valid,1 byte,2 bytes,Not valid,4 bytes,Not valid,Not valid,Not valid,8 bytes,Not valid,Not valid,Not valid,Not valid,Not valid,Not valid,Not valid" group 0x3c0c++0x3 line.long 0x0 "ENR,Enable Register" bitfld.long 0x0 24. " RC ,Reset Controller" "No reset,Reset" bitfld.long 0x0 16. " RF ,Reset Fifo" "No reset,Reset" textline " " bitfld.long 0x0 9. " AIE ,Abort Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 8. " NIE ,Normal Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " ME ,Master Enable" "Disabled,Enabled" ;rgroup 0x3c10++0x3 ; line.long 0x0 "NASR,Next Address Status Register" ; hexmask.long.long 0x0 0.--31. 1. " Next_address ,Next Address at which a byte would be sent to the Peripheral" group 0x3c14++0x3 line.long 0x0 "BDSR,Bytes Done Status Register" eventfld.long 0x0 28. " AT ,Abort Termination" "Not aborted,Aborted" eventfld.long 0x0 24. " NT ,Normal Termination" "Not normal,Normal" textline " " hexmask.long 0x0 0.--23. 1. " BytesDone ,Actual number of bytes transmitted at a given point in time" group 0x3c40++0x3 "BLPC FIFO Registers" line.long 0x0 "DWR,Rx/Tx FIFO Data Word Register" hexmask.long.long 0x0 0.--31. 1. " FIFO_Data_Word ,FIFO data port" group 0x3c44++0x3 line.long 0x0 "SR,LPC Rx/Tx FIFO Status Register" eventfld.long 0x0 22. " Err ,Error" "No error,Error" eventfld.long 0x0 21. " UF ,UnderFlow" "Underflow,No underflow" textline " " eventfld.long 0x0 20. " OF ,OverFlow" "Overflow,No overflow" bitfld.long 0x0 19. " Full ,FIFO full" "Not full,Full" textline " " bitfld.long 0x0 18. " HI ,High - FIFO requests attention" "No alarm,Alarm" bitfld.long 0x0 17. " LO ,Low - FIFO requests attention" "No alarm,Alarm" textline " " bitfld.long 0x0 16. " Emty ,FIFO empty" "Not empty,Empty" group 0x3c48++0x3 line.long 0x0 "CTR,LPC Rx/Tx FIFO Control Register" bitfld.long 0x0 29. " WFR ,FIFO Controller assumes next data write is EOF" "No EOF,EOF" bitfld.long 0x0 24.--26. " GR ,Granularity" "FIFO waits,FIFO stopped,?..." group 0x3c4c++0x3 line.long 0x0 "ALR,LPC Rx/Tx FIFO Alarm Register" hexmask.long.word 0x0 0.--11. 1. " Alarm ,User writes these bits to set low level watermark" group 0x3c50++0x3 line.long 0x0 "RPR,Rx/Tx FIFO Read Pointer Register" hexmask.long.word 0x0 0.--11. 1. " ReadPtr ,Read address presented to the FIFO RAM" group 0x3c54++0x3 line.long 0x0 "WPR,Rx/Tx FIFO Write Pointer Register" hexmask.long.word 0x0 0.--11. 1. " WritePtr ,Write address presented to the FIFO RAM" width 0xb tree.end tree "SmartComm Timer Registers (MBAR + 0x0400)" width 6. sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)<0x80822014) ; cpu!=MPC5200B group 0x400++0x3 line.long 0x0 "STAT,BT Status Register" group 0x410++0x3 "Timer 1" line.long 0x0 "PTC,BT 1 Prescale and Termination Count Register" group 0x414++0x3 line.long 0x0 "CTR,BT 1 Control and Enable Register" group 0x418++0x3 line.long 0x0 "STA,BT 1 Force and Status Register" group 0x41c++0x3 line.long 0x0 "INFO,BT 1 Info Register" group 0x420++0x3 "Timer 2" line.long 0x0 "PTC,BT 2 Prescale and Termination Count Register" group 0x424++0x3 line.long 0x0 "CTR,BT 2 Control and Enable Register" group 0x428++0x3 line.long 0x0 "STA,BT 2 Force and Status Register" group 0x42c++0x3 line.long 0x0 "INFO,BT 2 Info Register" group 0x430++0x3 "Timer 3" line.long 0x0 "PTC,BT 3 Prescale and Termination Count Register" group 0x434++0x3 line.long 0x0 "CTR,BT 3 Control and Enable Register" group 0x438++0x3 line.long 0x0 "STA,BT 3 Force and Status Register" group 0x43c++0x3 line.long 0x0 "INFO,BT 3 Info Register" group 0x440++0x3 "Timer 4" line.long 0x0 "PTC,BT 4 Prescale and Termination Count Register" group 0x444++0x3 line.long 0x0 "CTR,BT 4 Control and Enable Register" group 0x448++0x3 line.long 0x0 "STA,BT 4 Force and Status Register" group 0x44c++0x3 line.long 0x0 "INFO,BT 4 Info Register" group 0x450++0x3 "Timer 5" line.long 0x0 "PTC,BT 5 Prescale and Termination Count Register" group 0x454++0x3 line.long 0x0 "CTR,BT 5 Control and Enable Register" group 0x458++0x3 line.long 0x0 "STA,BT 5 Force and Status Register" group 0x45c++0x3 line.long 0x0 "INFO,BT 5 Info Register" group 0x460++0x3 "Timer 6" line.long 0x0 "PTC,BT 6 Prescale and Termination Count Register" group 0x464++0x3 line.long 0x0 "CTR,BT 6 Control and Enable Register" group 0x468++0x3 line.long 0x0 "STA,BT 6 Force and Status Register" group 0x46c++0x3 line.long 0x0 "INFO,BT 6 Info Register" group 0x470++0x3 "Timer 7" line.long 0x0 "PTC,BT 7 Prescale and Termination Count Register" group 0x474++0x3 line.long 0x0 "CTR,BT 7 Control and Enable Register" group 0x478++0x3 line.long 0x0 "STA,BT 7 Force and Status Register" group 0x47c++0x3 line.long 0x0 "INFO,BT 7 Info Register" else hgroup 0x400++0x3 hide.long 0x0 "STAT,BT Status Register" hgroup 0x410++0x3 "Timer 1" hide.long 0x0 "PTC,BT 1 Prescale and Termination Count Register" hgroup 0x414++0x3 hide.long 0x0 "CTR,BT 1 Control and Enable Register" hgroup 0x418++0x3 hide.long 0x0 "STA,BT 1 Force and Status Register" hgroup 0x41c++0x3 hide.long 0x0 "INFO,BT 1 Info Register" hgroup 0x420++0x3 "Timer 2" hide.long 0x0 "PTC,BT 2 Prescale and Termination Count Register" hgroup 0x424++0x3 hide.long 0x0 "CTR,BT 2 Control and Enable Register" hgroup 0x428++0x3 hide.long 0x0 "STA,BT 2 Force and Status Register" hgroup 0x42c++0x3 hide.long 0x0 "INFO,BT 2 Info Register" hgroup 0x430++0x3 "Timer 3" hide.long 0x0 "PTC,BT 3 Prescale and Termination Count Register" hgroup 0x434++0x3 hide.long 0x0 "CTR,BT 3 Control and Enable Register" hgroup 0x438++0x3 hide.long 0x0 "STA,BT 3 Force and Status Register" hgroup 0x43c++0x3 hide.long 0x0 "INFO,BT 3 Info Register" hgroup 0x440++0x3 "Timer 4" hide.long 0x0 "PTC,BT 4 Prescale and Termination Count Register" hgroup 0x444++0x3 hide.long 0x0 "CTR,BT 4 Control and Enable Register" hgroup 0x448++0x3 hide.long 0x0 "STA,BT 4 Force and Status Register" hgroup 0x44c++0x3 hide.long 0x0 "INFO,BT 4 Info Register" hgroup 0x450++0x3 "Timer 5" hide.long 0x0 "PTC,BT 5 Prescale and Termination Count Register" hgroup 0x454++0x3 hide.long 0x0 "CTR,BT 5 Control and Enable Register" hgroup 0x458++0x3 hide.long 0x0 "STA,BT 5 Force and Status Register" hgroup 0x45c++0x3 hide.long 0x0 "INFO,BT 5 Info Register" hgroup 0x460++0x3 "Timer 6" hide.long 0x0 "PTC,BT 6 Prescale and Termination Count Register" hgroup 0x464++0x3 hide.long 0x0 "CTR,BT 6 Control and Enable Register" hgroup 0x468++0x3 hide.long 0x0 "STA,BT 6 Force and Status Register" hgroup 0x46c++0x3 hide.long 0x0 "INFO,BT 6 Info Register" hgroup 0x470++0x3 "Timer 7" hide.long 0x0 "PTC,BT 7 Prescale and Termination Count Register" hgroup 0x474++0x3 hide.long 0x0 "CTR,BT 7 Control and Enable Register" hgroup 0x478++0x3 hide.long 0x0 "STA,BT 7 Force and Status Register" hgroup 0x47c++0x3 hide.long 0x0 "INFO,BT 7 Info Register" endif elif (cpu()=="MGT5100") group 0x400++0x3 line.long 0x0 "STAT,BT Status Register" group 0x410++0x3 "Timer 1" line.long 0x0 "PTC,BT 1 Prescale and Termination Count Register" group 0x414++0x3 line.long 0x0 "CTR,BT 1 Control and Enable Register" group 0x418++0x3 line.long 0x0 "STA,BT 1 Force and Status Register" group 0x41c++0x3 line.long 0x0 "INFO,BT 1 Info Register" group 0x420++0x3 "Timer 2" line.long 0x0 "PTC,BT 2 Prescale and Termination Count Register" group 0x424++0x3 line.long 0x0 "CTR,BT 2 Control and Enable Register" group 0x428++0x3 line.long 0x0 "STA,BT 2 Force and Status Register" group 0x42c++0x3 line.long 0x0 "INFO,BT 2 Info Register" group 0x430++0x3 "Timer 3" line.long 0x0 "PTC,BT 3 Prescale and Termination Count Register" group 0x434++0x3 line.long 0x0 "CTR,BT 3 Control and Enable Register" group 0x438++0x3 line.long 0x0 "STA,BT 3 Force and Status Register" group 0x43c++0x3 line.long 0x0 "INFO,BT 3 Info Register" group 0x440++0x3 "Timer 4" line.long 0x0 "PTC,BT 4 Prescale and Termination Count Register" group 0x444++0x3 line.long 0x0 "CTR,BT 4 Control and Enable Register" group 0x448++0x3 line.long 0x0 "STA,BT 4 Force and Status Register" group 0x44c++0x3 line.long 0x0 "INFO,BT 4 Info Register" group 0x450++0x3 "Timer 5" line.long 0x0 "PTC,BT 5 Prescale and Termination Count Register" group 0x454++0x3 line.long 0x0 "CTR,BT 5 Control and Enable Register" group 0x458++0x3 line.long 0x0 "STA,BT 5 Force and Status Register" group 0x45c++0x3 line.long 0x0 "INFO,BT 5 Info Register" group 0x460++0x3 "Timer 6" line.long 0x0 "PTC,BT 6 Prescale and Termination Count Register" group 0x464++0x3 line.long 0x0 "CTR,BT 6 Control and Enable Register" group 0x468++0x3 line.long 0x0 "STA,BT 6 Force and Status Register" group 0x46c++0x3 line.long 0x0 "INFO,BT 6 Info Register" group 0x470++0x3 "Timer 7" line.long 0x0 "PTC,BT 7 Prescale and Termination Count Register" group 0x474++0x3 line.long 0x0 "CTR,BT 7 Control and Enable Register" group 0x478++0x3 line.long 0x0 "STA,BT 7 Force and Status Register" group 0x47c++0x3 line.long 0x0 "INFO,BT 7 Info Register" endif width 0xb tree.end tree "SDRAM Memory Controller Registers (MBAR + 0x0100)" width 7. wgroup 0x100++0x3 line.long 0x0 "MOD,SDRAM Mode Register" bitfld.long 0x0 30.--31. " MEM_MBA ,Select either the memory device Mode register or the memory device Extended Mode register if present" "0,1,2,3" hexmask.long.word 0x0 18.--29. 1. " MEM_MA ,See SDRAM data sheet" bitfld.long 0x0 0. " cmd ,Generate a (Extended) Mode Register Set memory command" "Not generated,Generated" sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x104++0x3 line.long 0x0 "CTR,SDRAM Control Register" bitfld.long 0x0 31. " mode_en ,Mode register enable" "Disabled,Enabled" bitfld.long 0x0 30. " cke ,MEM_CLK_EN negated or asserted" "Negated,Asserted" bitfld.long 0x0 29. " ddr ,DDR mode enable" "SDR,DDR" textline " " bitfld.long 0x0 28. " ref_en ,Automatic refresh enable" "Disabled,Enabled" bitfld.long 0x0 24. " hi_addr ,Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA bus" "Low,High" textline " " bitfld.long 0x0 22. " drive_rule ," "Tri-state except to write,Drive except to read" textline " " hexmask.long.byte 0x0 16.--21. 1. " ref_interval ,The average periodic interval" textline " " bitfld.long 0x0 13. " mem_ps ,Memory data port size" "32-bit,16-bit" textline " " bitfld.long 0x0 11. " dqs_3e ,Controls one MEM_MDQS output" "Never driven,Can be driven" bitfld.long 0x0 10. " dqs_2e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 9. " dqs_1e ,Controls one MEM_MDQS output" "Not driven,Driven" textline " " bitfld.long 0x0 8. " dqs_0e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 2. " soft_ref ,Generate a non-periodic Auto Refresh command as soon as possible" "No operation,Generated" bitfld.long 0x0 1. " soft_pre ,Generate a Precharge All command as soon as possible" "No operation,Generated" group 0x108++0x3 line.long 0x0 "CFG1,SDRAM Configuration Register 1" bitfld.long 0x0 28.--31. " srd2rwp ,Single Read to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--27. " swt2rwp ,Single Write to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " rd_lat ,Read CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--18. " act2rw ,Active to Read/Write Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " pre2act ,Precharge to Active Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " ref2act ,Refresh to Active Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " wr_lat ,Write Latency" "0,1,2,3,4,5,6,7" else group 0x104++0x3 line.long 0x0 "CTR,SDRAM Control Register" bitfld.long 0x0 31. " mode_en ,Mode register enable" "Disabled,Enabled" bitfld.long 0x0 30. " cke ,MEM_CLK_EN negated or asserted" "Negated,Asserted" bitfld.long 0x0 29. " ddr ,DDR mode enable" "SDR,DDR" textline " " bitfld.long 0x0 28. " ref_en ,Automatic refresh enable" "Disabled,Enabled" bitfld.long 0x0 24. " hi_addr ,Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA bus" "Low,High" textline " " bitfld.long 0x0 22. " drive_rule ," "Tri-state except to write,Drive except to read" textline " " hexmask.long.byte 0x0 16.--21. 1. " ref_interval ,The average periodic interval" textline " " bitfld.long 0x0 11. " dqs_3e ,Controls one MEM_MDQS output" "Never driven,Can be driven" bitfld.long 0x0 10. " dqs_2e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 9. " dqs_1e ,Controls one MEM_MDQS output" "Not driven,Driven" textline " " bitfld.long 0x0 8. " dqs_0e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 2. " soft_ref ,Generate a non-periodic Auto Refresh command as soon as possible" "No operation,Generated" bitfld.long 0x0 1. " soft_pre ,Generate a Precharge All command as soon as possible" "No operation,Generated" group 0x108++0x3 line.long 0x0 "CFG1,SDRAM Configuration Register 1" bitfld.long 0x0 28.--31. " srd2rwp ,Single Read to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--26. " swt2rwp ,Single Write to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20.--23. " rd_lat ,Read CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--18. " act2rw ,Active to Read/Write Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " pre2act ,Precharge to Active Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " ref2act ,Refresh to Active Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " wr_lat ,Write Latency" "0,1,2,3,4,5,6,7" endif elif (cpu()=="MGT5100") group 0x104++0x3 line.long 0x0 "CTR,SDRAM Control Register" bitfld.long 0x0 31. " mode_en ,Mode register enable" "Disabled,Enabled" bitfld.long 0x0 30. " cke ,MEM_CLK_EN negated or asserted" "Negated,Asserted" bitfld.long 0x0 29. " ddr ,DDR mode enable" "SDR,DDR" textline " " bitfld.long 0x0 28. " ref_en ,Automatic refresh enable" "Disabled,Enabled" bitfld.long 0x0 24. " hi_addr ,Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA bus" "Low,High" textline " " bitfld.long 0x0 22. " drive_rule ," "Tri-state except to write,Drive except to read" textline " " hexmask.long.byte 0x0 16.--21. 1. " ref_interval ,The average periodic interval" textline " " bitfld.long 0x0 11. " dqs_3e ,Controls one MEM_MDQS output" "Never driven,Can be driven" bitfld.long 0x0 10. " dqs_2e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 9. " dqs_1e ,Controls one MEM_MDQS output" "Not driven,Driven" textline " " bitfld.long 0x0 8. " dqs_0e ,Controls one MEM_MDQS output" "Not driven,Driven" bitfld.long 0x0 2. " soft_ref ,Generate a non-periodic Auto Refresh command as soon as possible" "No operation,Generated" bitfld.long 0x0 1. " soft_pre ,Generate a Precharge All command as soon as possible" "No operation,Generated" group 0x108++0x3 line.long 0x0 "CFG1,SDRAM Configuration Register 1" bitfld.long 0x0 28.--31. " srd2rwp ,Single Read to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--26. " swt2rwp ,Single Write to Read/Write/Precharge Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20.--23. " rd_lat ,Read CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--18. " act2rw ,Active to Read/Write Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " pre2act ,Precharge to Active Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " ref2act ,Refresh to Active Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " wr_lat ,Write Latency" "0,1,2,3,4,5,6,7" endif group 0x10c++0x3 line.long 0x0 "CFG2,SDRAM Configuration Register 2" hexmask.long.byte 0x0 28.--31. 1. " brd2rp ,Burst Read to Read/Precharge delay" hexmask.long.byte 0x0 24.--27. 1. " bwt2rwp ,Burst Write to Read/Write/Precharge Delay" hexmask.long.byte 0x0 20.--23. 1. " brd2wt ,Burst Read to Read/Write/Precharge Delay" textline " " hexmask.long.byte 0x0 16.--19. 1. " burst_length ,Write 0x07 (Burst Length - 1)" group 0x110++0x3 line.long 0x0 "ADSEL,SDRAM Address Select Register" width 0xb tree.end tree "SLT Registers (MBAR + 0x0700)" width 5. group 0x700++0x3 "SLT 0" line.long 0x0 "TCN,SLT0 Terminal Count" hexmask.long 0x0 0.--23. 1. " Terminal_Count ,Terminal Count value used by the Timer" group 0x704++0x3 line.long 0x0 "CTR,SLT0 Control" bitfld.long 0x0 26. " Run_Wait ," "Wait,Run" bitfld.long 0x0 25. " Interrupt_Enable ," "Disabled,Enabled" textline " " bitfld.long 0x0 24. " Timer_Enable ," "Idle,Normal" rgroup 0x708++0x3 line.long 0x0 "CNT,SLT0 Count" hexmask.long 0x0 0.--23. 1. " TimerCount ,Current state of the Timer counter" rgroup 0x70c++0x3 line.long 0x0 "TST,SLT0 Terminal Status" eventfld.long 0x0 24. " ST ,Timer has reached Terminal Count" "Not reached,Reached" group 0x710++0x3 "SLT 1" line.long 0x0 "TCN,SLT1 Terminal Count" hexmask.long 0x0 0.--23. 1. " Terminal_Count ,Terminal Count value used by the Timer" group 0x714++0x3 line.long 0x0 "CTR,SLT1 Control" bitfld.long 0x0 26. " Run_Wait ," "Wait,Run" bitfld.long 0x0 25. " Interrupt_Enable ," "Disabled,Enabled" textline " " bitfld.long 0x0 24. " Timer_Enable ," "Idle,Normal" rgroup 0x718++0x3 line.long 0x0 "CNT,SLT1 Count" hexmask.long 0x0 0.--23. 1. " TimerCount ,Current state of the Timer counter" group 0x71c++0x3 line.long 0x0 "TST,SLT1 Terminal Status" eventfld.long 0x0 24. " ST ,Timer has reached Terminal Count" "Not reached,Reached" width 0xb tree.end tree "SPI Registers (MBAR + 0x0F00)" width 9. group 0xf00++0x0 line.byte 0x0 "SPICR1,Control Register 1" bitfld.byte 0x0 7. " SPIE ,SPI Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x0 6. " SPE ,SPI System Enable" "Disabled,Enabled" bitfld.byte 0x0 4. " MSTR ,SPI Master/Slave Mode Select" "Slave,Master" textline " " bitfld.byte 0x0 3. " CPOL ,SPI Clock Polarity" "Active-high,Active-low" bitfld.byte 0x0 2. " CPHA ,SPI Clock Phase of the 8-cycle transfer operation" "Half cycle,Normal" bitfld.byte 0x0 1. " SSOE ,Slave Select (/SS) Output Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 0. " LSBFE ,SPI LSB-First Enable" "MSB first,LSB first" group 0xf01++0x0 line.byte 0x0 "SPICR2,Control Register 2" bitfld.byte 0x0 1. " SPISWAI ,SPI Stop in Wait Mode" "Normal,Stopped" bitfld.byte 0x0 0. " SPC0 ,Serial Pin Control Bit 0" "Normal,Bidirectional" group 0xf04++0x0 line.byte 0x0 "SPIBR,Baud Rate Register" hexmask.byte 0x0 4.--6. 1. " SPPR ,SPI Baud Rate Preselection bits" hexmask.byte 0x0 0.--2. 1. " SPR ,SPI Baud Rate Selection bits" group 0xf05++0x0 line.byte 0x0 "SPISR,Status Register" bitfld.byte 0x0 7. " SPIF ,SPI Interrupt flag" "Not occurred,Occurred" bitfld.byte 0x0 6. " WCOL ,Write Collision flag" "Not occurred,Occurred" bitfld.byte 0x0 4. " MODF ,Mode Fault flag" "Not occurred,Occurred" group 0xf09++0x0 line.byte 0x0 "SPIDR,Data Register" hexmask.byte 0x0 0.--7. 1. " D[0:7] ,SPI Port Data" group 0xf0d++0x0 line.byte 0x0 "SPIPORT,Port Data Register" hexmask.byte 0x0 0.--7. 1. " D[0:7] ,SPI Port Data" group 0xf10++0x0 line.byte 0x0 "SPIDDR,Data Direction Register" bitfld.byte 0x0 7. " DDR[0] ,SPI Port Data Direction" "Input,Output" bitfld.byte 0x0 6. " DDR[1] ,SPI Port Data Direction" "Input,Output" bitfld.byte 0x0 5. " DDR[2] ,SPI Port Data Direction" "Input,Output" textline " " bitfld.byte 0x0 4. " DDR[3] ,SPI Port Data Direction" "Input,Output" bitfld.byte 0x0 3. " DDR[4] ,SPI Port Data Direction" "Input,Output" bitfld.byte 0x0 2. " DDR[5] ,SPI Port Data Direction" "Input,Output" textline " " bitfld.byte 0x0 1. " DDR[6] ,SPI Port Data Direction" "Input,Output" bitfld.byte 0x0 0. " DDR[7] ,SPI Port Data Direction" "Input,Output" width 0xb tree.end tree "USB Host Controller Registers (MBAR + 0x1000)" width 20. group 0x1000++0x3 "Control and Status Partition" line.long 0x0 "HcRevision,HC Revision" hexmask.long.byte 0x0 0.--7. 1. " REV ,BCD representation of the HCI specification version implemented by this HC" group 0x1004++0x3 line.long 0x0 "HcControl,HC Control" bitfld.long 0x0 10. " RWE ,Remote Wake Up Enable" "Disabled,Enabled" bitfld.long 0x0 9. " RWC ,Remote Wake Up Connected" "Not connected,Connected" textline " " bitfld.long 0x0 8. " IR ,Interrupt Routing" "Normal host bus,System managment interrupt" textline " " bitfld.long 0x0 6.--7. " HCFS ,Host Controller Functional State" "USBRESET,USBRESUME,USBOPERATIONAL,USBSUSPEND" bitfld.long 0x0 5. " BLE ,Bulk List Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " CLE ,Control List Enable" "Disabled,Enabled" bitfld.long 0x0 3. " IE ,Isochronous Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " PLE ,Periodic List Enable" "Disabled,Enabled" bitfld.long 0x0 0.--1. " CBSR ,Control Bulk Service Ratio" "1:1,2:1,3:1,4:1" group 0x1008++0x3 line.long 0x0 "HcCommandStatus,HC Command Status" bitfld.long 0x0 16.--17. " SOC ,Scheduling Overrun Count" "00,01,10,11" bitfld.long 0x0 3. " OCR ,Ownership Change Request" "Not requested,Requested" textline " " bitfld.long 0x0 2. " BLF ,Bulk List Filled" "Not started,Started" bitfld.long 0x0 1. " CLF ,Control List Filled" "Not started,Started" textline " " bitfld.long 0x0 0. " HCR ,Host Controller Reset" "No reset,Reset" group 0x100c++0x3 line.long 0x0 "HcInterruptStatus,HC Interrupt Status" bitfld.long 0x0 30. " OC ,Ownership Change" "Not occurred,Occurred" bitfld.long 0x0 6. " RHSC ,Root Hub Status Change" "Not changed,Changed" textline " " bitfld.long 0x0 5. " FNO ,Frame Number Overflow" "No overflow,Overflow" bitfld.long 0x0 4. " UE ,Unrecoverable Error" "No error,Error" textline " " bitfld.long 0x0 3. " RD ,Resume Detected" "Not detected,Detected" bitfld.long 0x0 2. " SF ,Start of Frame" "No SOF,SOF" textline " " bitfld.long 0x0 1. " WDH ,Writeback Done Head" "Not occurred,Occurred" bitfld.long 0x0 0. " SO ,Scheduling Overrun" "No overrun,Overrun" group 0x1010++0x3 line.long 0x0 "HcInterruptEnable,HC Interrupt Enable" bitfld.long 0x0 31. " MIE ,Master Interrupt Enable" "Ignored,Enabled" bitfld.long 0x0 30. " OC ,Ownership Change" "Ignored,Enabled" textline " " bitfld.long 0x0 6. " RHSC ,Root Hub Status Change" "Ignored,Enabled" bitfld.long 0x0 5. " FNO ,Frame Number Overfow" "Ignored,Enabled" textline " " bitfld.long 0x0 4. " UE ,Unrecoverable Error" "Ignored,Enabled" bitfld.long 0x0 3. " RD ,Resume Detected" "Ignored,Enabled" textline " " bitfld.long 0x0 2. " SF ,Start of Frame" "Ignored,Enabled" bitfld.long 0x0 1. " WDH ,Writeback Done Head" "Ignored,Enabled" textline " " bitfld.long 0x0 0. " SO ,Scheduling Overrun" "Ignored,Enabled" group 0x1014++0x3 line.long 0x0 "HcInterruptDisable,HC Interrupt Disable" bitfld.long 0x0 31. " MIE ,Master Interrupt Enable" "Ignored,Disabled" bitfld.long 0x0 30. " OC ,Ownership Change" "Ignored,Disabled" textline " " bitfld.long 0x0 6. " RHSC ,Root Hub Status Change" "Ignored,Disabled" bitfld.long 0x0 5. " FNO ,Frame Number Overflow" "Ignored,Disabled" textline " " bitfld.long 0x0 4. " UE ,Unrecoverable Error" "Ignored,Disabled" bitfld.long 0x0 3. " RD ,Resume Detected" "Ignored,Disabled" textline " " bitfld.long 0x0 2. " SF ,Start of Frame" "Ignored,Disabled" bitfld.long 0x0 1. " WDH ,Writeback Done Head" "Ignored,Disabled" textline " " bitfld.long 0x0 0. " SO ,Scheduling Overrun" "Ignored,Disabled" width 20. group 0x1018++0x3 "Memory Pointer Partition" line.long 0x0 "HcHCCA,HC Communication" hexmask.long 0x0 8.--31. 0x100 " HCCA ,Host Controller Communication Area base address" group 0x101c++0x3 line.long 0x0 "HcPeriodCurrentED,HC Period Current ED" hexmask.long.long 0x0 4.--31. 1. " PCED ,Period Current ED" group 0x1020++0x3 line.long 0x0 "HcControlHeadED,HC Control Head ED" hexmask.long.long 0x0 4.--31. 1. " CHED ,Control Head ED" group 0x1024++0x3 line.long 0x0 "HcControlCurrentED,HC Control Current ED" hexmask.long.long 0x0 4.--31. 1. " CCED ,Control Current ED" group 0x1028++0x3 line.long 0x0 "HcBulkHeadED,HC First Bulk Head List ED" hexmask.long.long 0x0 4.--31. 1. " BHED ,Bulk Head ED" group 0x102c++0x3 line.long 0x0 "HcBulkCurrentED,HC Bulk List Current ED" hexmask.long.long 0x0 4.--31. 1. " BHED ,Bulk Current ED" group 0x1030++0x3 line.long 0x0 "HcDoneHead,HC Last Completed Transfer" hexmask.long.long 0x0 4.--31. 1. " DH ,Done Head" width 20. group 0x1034++0x3 "Frame Counter Partition" line.long 0x0 "HcFmInterval,HC Frame Interval" bitfld.long 0x0 31. " FIT ,Frame Interval Toggle" "No effect,New FI" hexmask.long.word 0x0 16.--30. 1. " FSMPS ,FS Largest Data Packet" textline " " hexmask.long.word 0x0 0.--13. 1. " FI ,Frame Interval" group 0x1038++0x3 line.long 0x0 "HcFmRemaining,HC Frame Bit-time Remaining" bitfld.long 0x0 31. " FRT ,FrameRemainingToggle" "No effect,FR=0" hexmask.long.word 0x0 0.--13. 1. " FR ,Frame Remaining" group 0x103c++0x3 line.long 0x0 "HcFmNumber,HC Timing Reference" hexmask.long.word 0x0 0.--15. 1. " FN ,Frame Number" group 0x1040++0x3 line.long 0x0 "HcPeriodicStart,HC Start Processing Periodic List" hexmask.long.word 0x0 0.--13. 1. " PS ,Periodic Start" group 0x1044++0x3 line.long 0x0 "HcLSThreshold,HC Commit Transfer" hexmask.long.word 0x0 0.--11. 1. " LST ,LS Threshold" width 20. group 0x1048++0x3 "Root Hub Partition" line.long 0x0 "HcRhDescriptorA,HC Root Hub Descriptor A" hexmask.long.byte 0x0 24.--31. 1. " POTPGT ,Power On To Power Good Time" bitfld.long 0x0 12. " NOCP ,No OverCurrent Protection" "Overcurrent,No overcurrent" textline " " bitfld.long 0x0 11. " OCPM ,OverCurrent Protection Mode" "For all ports,Per-port" bitfld.long 0x0 10. " DT ,Device Type" "Compound,Not compound" textline " " bitfld.long 0x0 9. " NPS ,No Power Switchinged on" "Switched,Powered on" bitfld.long 0x0 8. " PSM ,Power Switching Mode" "All ports,Individual" textline " " hexmask.long.byte 0x0 0.--7. 1. " NDP ,Number Downstream Ports" group 0x104c++0x3 line.long 0x0 "HcRhDescriptorB,HC Root Hub Descriptor B" bitfld.long 0x0 30. " PPCM[1] ,Port #1 Power Control Mask" "Per-port,Global" bitfld.long 0x0 29. " PPCM[2] ,Port #2 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 28. " PPCM[3] ,Port #3 Power Control Mask" "Per-port,Global" bitfld.long 0x0 27. " PPCM[4] ,Port #4 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 26. " PPCM[5] ,Port #5 Power Control Mask" "Per-port,Global" bitfld.long 0x0 25. " PPCM[6] ,Port #6 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 24. " PPCM[7] ,Port #7 Power Control Mask" "Per-port,Global" bitfld.long 0x0 23. " PPCM[8] ,Port #8 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 22. " PPCM[9] ,Port #9 Power Control Mask" "Per-port,Global" bitfld.long 0x0 21. " PPCM[10] ,Port #10 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 20. " PPCM[11] ,Port #11 Power Control Mask" "Per-port,Global" bitfld.long 0x0 19. " PPCM[12] ,Port #12 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 18. " PPCM[13] ,Port #13 Power Control Mask" "Per-port,Global" bitfld.long 0x0 17. " PPCM[14] ,Port #14 Power Control Mask" "Per-port,Global" textline " " bitfld.long 0x0 16. " PPCM[15] ,Port #15 Power Control Mask" "Per-port,Global" bitfld.long 0x0 15. " DR[0] ,Reserved" "Reserved,Reserved" textline " " bitfld.long 0x0 14. " DR[1] ,NDevice Removable (Port #1)" "Removable,Not removable" bitfld.long 0x0 13. " DR[2] ,NDevice Removable (Port #2)" "Removable,Not removable" textline " " bitfld.long 0x0 12. " DR[3] ,NDevice Removable (Port #3)" "Removable,Not removable" bitfld.long 0x0 11. " DR[4] ,NDevice Removable (Port #4)" "Removable,Not removable" textline " " bitfld.long 0x0 10. " DR[5] ,NDevice Removable (Port #5)" "Removable,Not removable" bitfld.long 0x0 9. " DR[6] ,NDevice Removable (Port #6)" "Removable,Not removable" textline " " bitfld.long 0x0 8. " DR[7] ,NDevice Removable (Port #7)" "Removable,Not removable" bitfld.long 0x0 7. " DR[8] ,NDevice Removable (Port #8)" "Removable,Not removable" textline " " bitfld.long 0x0 6. " DR[9] ,NDevice Removable (Port #9)" "Removable,Not removable" bitfld.long 0x0 5. " DR[10] ,NDevice Removable (Port #10)" "Removable,Not removable" textline " " bitfld.long 0x0 4. " DR[11] ,NDevice Removable (Port #11)" "Removable,Not removable" bitfld.long 0x0 3. " DR[12] ,NDevice Removable (Port #12)" "Removable,Not removable" textline " " bitfld.long 0x0 2. " DR[13] ,NDevice Removable (Port #13)" "Removable,Not removable" bitfld.long 0x0 1. " DR[14] ,NDevice Removable (Port #14)" "Removable,Not removable" textline " " bitfld.long 0x0 0. " DR[15] ,NDevice Removable (Port #15)" "Removable,Not removable" group 0x1050++0x3 line.long 0x0 "HcRhStatus,HC Root Hub Status" bitfld.long 0x0 31. " CRWE ,Clear Remote WakeUp Enable (write)" "No effect,DRWE cleared" eventfld.long 0x0 17. " OCIC ,OverCurrent Indicator Change" "No effect,OCI changed" textline " " bitfld.long 0x0 16. " LPSC ,Local Power Status Change (read) / Set Global Power (write)" "No effect,No effect/Power on" bitfld.long 0x0 15. " DRWE ,Set Remote WakeUp Enable (read) / Device Remote WakeUp Enable (write)" "No effect/Disabled,DRWE set/Enabled" textline " " bitfld.long 0x0 1. " OCI ,OverCurrent Indicator" "Normal,Overcurrent" bitfld.long 0x0 0. " LPS ,Local Power Status" "No effect,Power on" width 20. group 0x1054++0x3 line.long 0x0 "HcRhPort1Status,HC RH Port 1 Status" eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not completed,Completed" textline " " eventfld.long 0x0 19. " OCIC ,Port OverCurrent Indicator Change" "Not changed,Changed" textline " " eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change (Resume)" "Not completed,Completed" textline " " eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed" textline " " eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed" textline " " bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached (read) / Clear Port Power (write)" "Full speed/No effect,Low speed/PPS cleared" textline " " bitfld.long 0x0 8. " PPS ,Port Power Status (read) / Set Port Power (write)" "Off/No effect,On/Set" textline " " bitfld.long 0x0 4. " PRS ,Port Reset Status (read) / Set Port Reset (write)" "Not active/No effect,Active/Set" textline " " bitfld.long 0x0 3. " POCI ,Port OverCurrent Indicator (read) / Clear Suspend Status (write)" "No overcurrent/No effect,Overcurrent/Resume initiated" textline " " bitfld.long 0x0 2. " PSS ,Port Suspend Status (read) / Set Port Suspend (write)" "Not suspended/No effect,Suspended/Set" textline " " bitfld.long 0x0 1. " PES ,Port Enable Status (read) / Set Port Enable (write)" "Disabled/No effect,Enabled/Set" textline " " bitfld.long 0x0 0. " CCS ,Current Connect Status (read) / Clear Port Enable (write)" "No device/No effect,Device/PES cleared" group 0x1058++0x3 line.long 0x0 "HcRhPort2Status,HC RH Port 2 Status" eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not completed,Completed" textline " " eventfld.long 0x0 19. " OCIC ,Port OverCurrent Indicator Change" "Not changed,Changed" textline " " eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change (Resume)" "Not completed,Completed" textline " " eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed" textline " " eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed" textline " " bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached (read) / Clear Port Power (write)" "Full speed/No effect,Low speed/PPS cleared" textline " " bitfld.long 0x0 8. " PPS ,Port Power Status (read) / Set Port Power (write)" "Off/No effect,On/Set" textline " " bitfld.long 0x0 4. " PRS ,Port Reset Status (read) / Set Port Reset (write)" "Not active/No effect,Active/Set" textline " " bitfld.long 0x0 3. " POCI ,Port OverCurrent Indicator (read) / Clear Suspend Status (write)" "No overcurrent/No effect,Overcurrent/Resume initiated" textline " " bitfld.long 0x0 2. " PSS ,Port Suspend Status (read) / Set Port Suspend (write)" "Not suspended/No effect,Suspended/Set" textline " " bitfld.long 0x0 1. " PES ,Port Enable Status (read) / Set Port Enable (write)" "Disabled/No effect,Enabled/Set" textline " " bitfld.long 0x0 0. " CCS ,Current Connect Status (read) / Clear Port Enable (write)" "No device/No effect,Device/PES cleared" width 0xb tree.end tree "XLB Arbiter Registers (MBAR+0x1F00)" width 8. sif (cpu()=="MPC5200") if (((d.l(spr:0x11F))&0xffffffff)>0x80822014) ; cpu=MPC5200B group 0x1f40++0x3 line.long 0x0 "ACFG,Configuration Register" bitfld.long 0x0 16. " BSDIS ,BestComm Snooping Disable" "Enabled,Disabled" textline " " bitfld.long 0x0 31. " PLDIS ,Pipeline Disable" "Enabled,Disabled" bitfld.long 0x0 15. " SE ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " USE_WWF ,Force write-with-flush transfer type (TT) for PCI, SmartComm, and USB interfaces to XLB" "Write-with-kill,Write-with-flush" bitfld.long 0x0 13. " TBEN ,Timebase Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " WS ,Minimum Wait State" "0,1" bitfld.long 0x0 8.--10. " SP[2:0] ,Select Parked Master" "Master 0,Master 1,Master 2,Master 3,Master 4,Master 5,Master 6,Master 7" textline " " bitfld.long 0x0 5.--6. " PM[1:0] ,Parking Mode" "No parking,Reserved,Most recently used,Programmed master" bitfld.long 0x0 3. " BA ,Bus Activity Time-out Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " DT ,Data Tenure Time-out Enable" "Disabled,Enabled" bitfld.long 0x0 1. " AT ,Address Tenure Time-out Enable" "Disabled,Enabled" else group 0x1f40++0x3 line.long 0x0 "ACFG,Configuration Register" bitfld.long 0x0 31. " PLDIS ,Pipeline Disable" "Enabled,Disabled" bitfld.long 0x0 15. " SE ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " USE_WWF ,Force write-with-flush transfer type (TT) for PCI, SmartComm, and USB interfaces to XLB" "Write-with-kill,Write-with-flush" bitfld.long 0x0 13. " TBEN ,Timebase Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " WS ,Minimum Wait State" "0,1" bitfld.long 0x0 8.--10. " SP[2:0] ,Select Parked Master" "Master 0,Master 1,Master 2,Master 3,Master 4,Master 5,Master 6,Master 7" textline " " bitfld.long 0x0 5.--6. " PM[1:0] ,Parking Mode" "No parking,Reserved,Most recently used,Programmed master" bitfld.long 0x0 3. " BA ,Bus Activity Time-out Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " DT ,Data Tenure Time-out Enable" "Disabled,Enabled" bitfld.long 0x0 1. " AT ,Address Tenure Time-out Enable" "Disabled,Enabled" endif elif (cpu()=="MGT5100") group 0x1f40++0x3 line.long 0x0 "ACFG,Configuration Register" bitfld.long 0x0 31. " PLDIS ,Pipeline Disable" "Enabled,Disabled" bitfld.long 0x0 15. " SE ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " USE_WWF ,Force write-with-flush transfer type (TT) for PCI, SmartComm, and USB interfaces to XLB" "Write-with-kill,Write-with-flush" bitfld.long 0x0 13. " TBEN ,Timebase Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " WS ,Minimum Wait State" "0,1" bitfld.long 0x0 8.--10. " SP[2:0] ,Select Parked Master" "Master 0,Master 1,Master 2,Master 3,Master 4,Master 5,Master 6,Master 7" textline " " bitfld.long 0x0 5.--6. " PM[1:0] ,Parking Mode" "No parking,Reserved,Most recently used,Programmed master" bitfld.long 0x0 3. " BA ,Bus Activity Time-out Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " DT ,Data Tenure Time-out Enable" "Disabled,Enabled" bitfld.long 0x0 1. " AT ,Address Tenure Time-out Enable" "Disabled,Enabled" endif group 0x1f44++0x3 line.long 0x0 "VER,Version Register" hexmask.long.long 0x0 0.--31. 1. " VER ,Hardware version ID" group 0x1f48++0x3 line.long 0x0 "STA,Status Register" bitfld.long 0x0 8. " SEA ,Slave Error Acknowledge" "No error,Error" bitfld.long 0x0 7. " MM ,Multiple Masters at Priority 0" "Not occurred,Occurred" textline " " bitfld.long 0x0 6. " TTA ,TT Address Only" "Not occurred,Occurred" bitfld.long 0x0 5. " TTR ,TT Reserved" "Not occurred,Occurred" textline " " bitfld.long 0x0 4. " ECW ,External Control Word Read/Write" "Not occurred,Occurred" bitfld.long 0x0 3. " TTM ,TBST/TSIZ mismatch" "Not occurred,Occurred" textline " " bitfld.long 0x0 2. " BA ,Bus Activity Tenure Time-out" "Not expired,Expired" bitfld.long 0x0 1. " DT ,Data Tenure Time-out" "Not expired,Expired" textline " " bitfld.long 0x0 0. " AT ,Address Tenure Time-out" "Not expired,Expired" group 0x1f4c++0x3 line.long 0x0 "INTEN,Interrupt Enable Register" bitfld.long 0x0 8. " SEAE ,Slave Error Acknowledge interrupt enable" "Disabled,Enabled" bitfld.long 0x0 7. " MME ,Multiple Masters at priority 0 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " TTAE ,TT Address Only interrupt enable" "Disabled,Enabled" bitfld.long 0x0 5. " TTRE ,TT Reserved interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " ECWE ,External Control Word Read/Write interrupt enable" "Disabled,Enabled" bitfld.long 0x0 3. " TTME ,TBST/TSIZ mismatch interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " BAE ,Bus Activity Tenure Time-out interrupt enable" "Disabled,Enabled" bitfld.long 0x0 1. " DTE ,Data Tenure Time-out interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " ATE ,Address Tenure Time-out interrupt enable" "Disabled,Enabled" group 0x1f50++0x3 line.long 0x0 "ADRCAP,Address Capture Register" hexmask.long.long 0x0 0.--31. 1. " ADRCAP ,Address Capture Value" group 0x1f54++0x3 line.long 0x0 "SIGCAP,Bus Signal Capture Register" hexmask.long.byte 0x0 7.--9. 1. " TSIZ ,Captured Value of TSIZ[0:2]" bitfld.long 0x0 6. " GBL ,Captured Value of GBL" "Not captured,Captured" textline " " bitfld.long 0x0 5. " TBST ,Captured Value of TBST" "Not captured,Captured" hexmask.long.byte 0x0 0.--4. 1. " TT ,Captured Value of TT[0:4]" group 0x1f58++0x3 line.long 0x0 "ADRTO,Address Tenure Time-Out Register" hexmask.long.long 0x0 0.--27. 1. " ADRTO ,Address Tenure Time-out" group 0x1f5c++0x3 line.long 0x0 "DATTO,Data Tenure Time-Out Register" hexmask.long.long 0x0 0.--27. 1. " DATTO ,Data Tenure Time-out" group 0x1f60++0x3 line.long 0x0 "BUSTO,Bus Activity Time-Out Register" hexmask.long.long 0x0 0.--31. 1. " BUSTO ,Bus Activity Time-out" group 0x1f64++0x3 line.long 0x0 "PRIEN,Master Priority Enable Register" bitfld.long 0x0 7. " M7 ,Master 7 Priority Register Enable (Unused)" "Disabled,Enabled" bitfld.long 0x0 6. " M6 ,Master 6 Priority Register Enable (Unused)" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " M5 ,Master 5 Priority Register Enable (Unused)" "Disabled,Enabled" bitfld.long 0x0 4. " M4 ,Master 4 Priority Register Enable (Unused)" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " M3 ,Master 3 Priority Register Enable (PCI Target Interface)" "Disabled,Enabled" bitfld.long 0x0 2. " M2 ,Master 2 Priority Register Enable (BestComm)" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " M1 ,Master 1 Priority Register Enable (USB)" "Disabled,Enabled" bitfld.long 0x0 0. " M0 ,Master 0 Priority Register Enable (G2_LE)" "Disabled,Enabled" group 0x1f68++0x3 line.long 0x0 "PRI,Master Priority Register" bitfld.long 0x0 28.--30. " M7P ,Master 7 Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " M6P ,Master 6 Priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20.--22. " M5P ,Master 5 Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. " M4P ,Master 4 Priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " M3P ,Master 3 Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. " M2P ,Master 2 Priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " M1P ,Master 1 Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. " M0P ,Master 0 Priority" "0,1,2,3,4,5,6,7" ; group 0x1f6c++0x3 No effect in MPC5200 implementation ; line.long 0x0 "BAR,Base Address Register" ; bitfld.long 0x0 28.--31. "BAR ,Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" ; bitfld.long 0x0 24.--27. ",Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" ; bitfld.long 0x0 20.--23. ",Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" ; bitfld.long 0x0 16.--19. ",Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" ; bitfld.long 0x0 12.--15. ",Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" ; bitfld.long 0x0 8.--11. ",Base address. Value is 0x00001F. This register has no effect in MGT5200 implementation." "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" group 0x1f70++0x3 line.long 0x0 "SNOOP,Snoop Window Register" hexmask.long 0x0 12.--31. 0x1000 " WINBASE ,Window Base Address" bitfld.long 0x0 7. " DS ,Default Snooping Policy" "Snoop inside window,Snoop outside window" textline " " bitfld.long 0x0 0.--4. " WINSIZE ,Window Size" "Window miss,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,4 kByte,8 kByte,16 kByte,32 kByte,64 kByte,128 kByte,256 kByte,512 kByte,1 MByte,2 MByte,4 MByte,8 MByte,16 MByte,32 MByte,64 MByte,128 MByte,256 MByte,512 MByte,1 GByte,2 GByte,Reserved" hgroup 0x1f00--0x1f3c hide.long 0x0 "RSV0 , Arbiter Reserved Register 0 " hide.long 0x4 "RSV1 , Arbiter Reserved Register 1 " hide.long 0x8 "RSV2 , Arbiter Reserved Register 2 " hide.long 0xC "RSV3 , Arbiter Reserved Register 3 " hide.long 0x10 "RSV4 , Arbiter Reserved Register 4 " hide.long 0x14 "RSV5 , Arbiter Reserved Register 5 " hide.long 0x18 "RSV6 , Arbiter Reserved Register 6 " hide.long 0x1C "RSV7 , Arbiter Reserved Register 7 " hide.long 0x20 "RSV8 , Arbiter Reserved Register 8 " hide.long 0x24 "RSV9 , Arbiter Reserved Register 9 " hide.long 0x28 "RSV10, Arbiter Reserved Register 10" hide.long 0x2C "RSV11, Arbiter Reserved Register 11" hide.long 0x30 "RSV12, Arbiter Reserved Register 12" hide.long 0x34 "RSV13, Arbiter Reserved Register 13" hide.long 0x38 "RSV14, Arbiter Reserved Register 14" hide.long 0x3C "RSV15, Arbiter Reserved Register 15" hgroup 0x1f74--0x1fff hide.long 0x0 "RSV16, Arbiter Reserved Register 16" hide.long 0x4 "RSV17, Arbiter Reserved Register 17" hide.long 0x8 "RSV18, Arbiter Reserved Register 18" hide.long 0xC "RSV19, Arbiter Reserved Register 19" hide.long 0x10 "RSV20, Arbiter Reserved Register 20" hide.long 0x14 "RSV21, Arbiter Reserved Register 21" hide.long 0x18 "RSV22, Arbiter Reserved Register 22" hide.long 0x1C "RSV23, Arbiter Reserved Register 23" hide.long 0x20 "RSV24, Arbiter Reserved Register 24" hide.long 0x24 "RSV25, Arbiter Reserved Register 25" hide.long 0x28 "RSV26, Arbiter Reserved Register 26" hide.long 0x2C "RSV27, Arbiter Reserved Register 27" hide.long 0x30 "RSV28, Arbiter Reserved Register 28" hide.long 0x34 "RSV29, Arbiter Reserved Register 29" hide.long 0x38 "RSV30, Arbiter Reserved Register 30" hide.long 0x3C "RSV31, Arbiter Reserved Register 31" hide.long 0x40 "RSV32, Arbiter Reserved Register 32" hide.long 0x44 "RSV33, Arbiter Reserved Register 33" hide.long 0x48 "RSV34, Arbiter Reserved Register 34" hide.long 0x4C "RSV35, Arbiter Reserved Register 35" hide.long 0x50 "RSV36, Arbiter Reserved Register 36" hide.long 0x54 "RSV37, Arbiter Reserved Register 37" hide.long 0x58 "RSV38, Arbiter Reserved Register 38" hide.long 0x5C "RSV39, Arbiter Reserved Register 39" hide.long 0x60 "RSV40, Arbiter Reserved Register 40" hide.long 0x64 "RSV41, Arbiter Reserved Register 41" hide.long 0x68 "RSV42, Arbiter Reserved Register 42" hide.long 0x6C "RSV43, Arbiter Reserved Register 43" hide.long 0x70 "RSV44, Arbiter Reserved Register 44" hide.long 0x74 "RSV45, Arbiter Reserved Register 45" hide.long 0x78 "RSV46, Arbiter Reserved Register 46" hide.long 0x7C "RSV47, Arbiter Reserved Register 47" hide.long 0x80 "RSV48, Arbiter Reserved Register 48" hide.long 0x84 "RSV49, Arbiter Reserved Register 49" hide.long 0x88 "RSV50, Arbiter Reserved Register 50" wgroup 0x00++0x0 width 0xb tree.end textline ""