; -------------------------------------------------------------------------------- ; @Title: MPC521x On-Chip Peripherals ; @Props: Released ; @Author: MAC, PAW ; @Changelog: ; 2008-01-17 ; 2009-01-13 ; @Manufacturer: NXP ; @Doc: MPC5121e_Rev3_DraftA.pdf (Rev. 2007-08); MPC5121ERM_rev3(2008-10).pdf ; @Core: PowerPC ; @Chiplist: BORNEO, CAYMAN, MPC5121, MPC5123, MPC5125, SUMATRA ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permpc512x.per 7231 2016-09-07 16:44:50Z kjmal $ config 16. 8. width 0xb tree "Core Registers" tree "General Registers" group SPR:286.++0 line.long 0x00 "SVR,System Version Register" group SPR:287.++0 line.long 0x00 "PVR,Processor Version Register" TEXTLINE "" group SPR:311.++0 line.long 0x00 "MBAR,Memory Base Address Register" TEXTLINE "" group.long SPR:0x8000++0 line.long 0x00 "CR,Condition Register" bitfld.long 0x00 31. "CR0: LT ,Negative (LT)" "0,1" bitfld.long 0x00 30. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 29. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 28. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 27. " CR1: LT ,Negative (LT)" "0,1" bitfld.long 0x00 26. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 25. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 24. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 23. " CR2: LT ,Negative (LT)" "0,1" bitfld.long 0x00 22. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 21. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 20. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 19. " CR3: LT ,Negative (LT)" "0,1" bitfld.long 0x00 18. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 17. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 16. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 15. " CR4: LT ,Negative (LT)" "0,1" bitfld.long 0x00 14. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 13. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 12. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 11. " CR5: LT ,Negative (LT)" "0,1" bitfld.long 0x00 10. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 09. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 08. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 07. " CR6: LT ,Negative (LT)" "0,1" bitfld.long 0x00 06. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 05. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 04. " SO ,Summary overflow (SO)" "0,1" TEXTLINE " " bitfld.long 0x00 03. " CR7: LT ,Negative (LT)" "0,1" bitfld.long 0x00 02. " GT ,Positive (GT)" "0,1" bitfld.long 0x00 01. " EQ ,Zero (EQ)" "0,1" bitfld.long 0x00 00. " SO ,Summary overflow (SO)" "0,1" TEXTLINE "" group.long SPR:1.++0 line.long 0x00 "XER,Integer Exception Register" bitfld.long 0x00 31. "SO ,Summary Overflow (per Book E)" "0,1" bitfld.long 0x00 30. " OV ,Overflow (per Book E)" "0,1" bitfld.long 0x00 29. " CA ,Carry (per Book E)" "0,1" hexmask.long.byte 0x00 00.--06. 1. " BYTECOUNT ,This field specifies the number of bytes to be transferred by a lswx or stswx instruction" tree.end tree "Time Base Registers" group SPR:284.++0 line.long 0x00 "TBL,Time Base Low Register" group SPR:285.++0 line.long 0x00 "TBU,Time Base High Register" TEXTLINE "" group SPR:22.++0 line.long 0x00 "DEC,Decrementer Register" tree.end tree "Interrupt Handling Registers" group SPR:19.++0 line.long 0x00 "DAR,Data Address Register" group SPR:18.++0 line.long 0x00 "DSISR,DSI Status Register" bitfld.long 0x00 30. "MISS ,Set if the translation of an attempted access is not found in the primary hash table entry group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT reg" "0,1" bitfld.long 0x00 27. " PROT ,Set if a memory access is not permitted by the page or DBAT protection mechanism" "0,1" bitfld.long 0x00 25. " STOR ,Set for a store operation and cleared for a load operation" "0,1" bitfld.long 0x00 22. " DABR ,Set if a data address breakpoint interrupt occurs" "0,1" TEXTLINE "" GROUP spr:0x01A--0x01B LINE.LONG 0x00 "SRR0 ,SRR0 holds EA for resuming program execution" LINE.LONG 0x04 "SRR1 ,SRR1 Exception-specific information and MSR bit values" TEXTLINE " SRR1 Machine Check Interrupt flags:" TEXTLINE " " BITFLD.LONG 0x04 30. "SRR1[10] ICERR ,instruction cache error (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 29. " SRR1[11] DCERR ,data cache error (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 19. " SRR1[12] MCP ,Set when /mcp signal is asserted (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 13. " SRR1[13] TEA ,Set when /tea signal is asserted (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 12. " SRR1[14] DPE ,Data parity error condition (and signal assertion) caused interrupt (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 11. " SRR1[15] APE ,Address parity error condition (and signal assertion) caused interrupt (e300 specific flag)" "0,1" TEXTLINE " " BITFLD.LONG 0x04 01. " SRR1[30] RI ,Set in case of a recoverable interrupt" "0,1" TEXTLINE " SRR1 ISI Interrupt flags:" TEXTLINE " " BITFLD.LONG 0x04 30. "SRR1[1] PAGE_FAULT ,translation neither found in HTEG nor IBAT" "0,1" TEXTLINE " " BITFLD.LONG 0x04 29. " SRR1[2] DSTORE/NX/G_ACC_IR ,access to a direct-store segment,no-execute segment or to guarded memory when MSR[IR] = 1" "0,1" TEXTLINE " " BITFLD.LONG 0x04 27. " SRR1[4] ACCESS_NOT_PERM ,access not permitted by the page or IBAT protection" "0,1" TEXTLINE " SRR1 Program Interrupt flags:" TEXTLINE " " BITFLD.LONG 0x04 20. "SRR1[11] FPENA ,Set for an IEEE floating-point enabled program exception" "0,1" TEXTLINE " " BITFLD.LONG 0x04 19. " SRR1[12] ILLINST ,Set for an illegal instruction program exception" "0,1" TEXTLINE " " BITFLD.LONG 0x04 18. " SRR1[13] PRIVINST ,Set for a privileged instruction program exception" "0,1" TEXTLINE " " BITFLD.LONG 0x04 17. " SRR1[14] TRAP ,Set for a trap program exception" "0,1" TEXTLINE " " BITFLD.LONG 0x04 16. " SRR1[15] SUBS ,Set if SRR0 contains the address of a subsequent instruction - Cleared if SRR0 contains the address of the instruction causing the exception" "0,1" TEXTLINE " SRR1 Instruction/Data TLB Interrupt flags:" TEXTLINE " " BITFLD.LONG 0x04 19. "SRR1[12] KEY ,Key for TLB miss" "0,1" TEXTLINE " " BITFLD.LONG 0x04 18. " SRR1[13] D/I ,Data or instruction access" "D,I" TEXTLINE " " BITFLD.LONG 0x04 17. " SRR1[14] WAY ,Next TLB set to be replaced" "0,1" TEXTLINE " " BITFLD.LONG 0x04 16. " SRR1[15] S/L ,Store or load data access" "S,L" TEXTLINE " " tree.end tree "Hardware Implementation Registers" group SPR:1008.++0 line.long 0x00 "HID0,Hardware Implementation Register 0" bitfld.long 0x00 31. "EMCP ,enable !MCP" "0,1" bitfld.long 0x00 30. " ECPE ,Enable cache parity errors" "0,1" bitfld.long 0x00 29. " EBA ,Enable ap_in[0:3] and ape for address parity checking" "0,1" bitfld.long 0x00 28. " EBD ,Enable dpe for data parity checking" "0,1" bitfld.long 0x00 27. " SBCLK ,clk_out output enable" "0,1" bitfld.long 0x00 25. " ECLK ,clk_out output enable" "0,1" bitfld.long 0x00 24. " PAR ,Disable precharge of artry_out" "0,1" TEXTLINE " " bitfld.long 0x00 23. " DOZE ,Doze mode enable" "0,1" bitfld.long 0x00 22. " NAP ,Nap mode enable" "0,1" bitfld.long 0x00 21. " SLEEP ,Sleep mode enable" "0,1" bitfld.long 0x00 20. " DPM ,Dynamic power management enable" "0,1" TEXTLINE " " bitfld.long 0x00 15. " ICE ,Instruction cache enable" "0,1" bitfld.long 0x00 14. " DCE ,Data cache enable" "0,1" bitfld.long 0x00 13. " ILOCK ,Instruction cache lock" "0,1" bitfld.long 0x00 12. " DLOCK ,Data cache lock" "0,1" bitfld.long 0x00 11. " ICFI ,Instruction cache flush invalidate" "0,1" bitfld.long 0x00 10. " DCFI ,Data cache flush invalidate" "0,1" TEXTLINE " " bitfld.long 0x00 07. " IFEM ,Enable M bit on bus for instruction fetches" "0,1" bitfld.long 0x00 04. " FBIOB ,Force branch indirect on the bus" "0,1" bitfld.long 0x00 03. " ABE ,Address broadcast enable" "0,1" bitfld.long 0x00 00. " NO0PTI ,No-op the data cache touch instructions" "0,1" TEXTLINE "" rgroup SPR:1009.++0 line.long 0x00 "HID1,Hardware Implementation Register 1" bitfld.long 0x00 31. "PC0 ,PLL configuration bit 0 (read-only)" "0,1" bitfld.long 0x00 30. " PC1 ,PLL configuration bit 1 (read-only)" "0,1" bitfld.long 0x00 29. " PC2 ,PLL configuration bit 2 (read-only)" "0,1" bitfld.long 0x00 28. " PC3 ,PLL configuration bit 3 (read-only)" "0,1" bitfld.long 0x00 27. " PC4 ,PLL configuration bit 4 (read-only)" "0,1" bitfld.long 0x00 26. " PC5 ,PLL configuration bit 5 (read-only)" "0,1" bitfld.long 0x00 25. " PC6 ,PLL configuration bit 6 (read-only)" "0,1" TEXTLINE "" group SPR:1011.++0 line.long 0x00 "HID2,Hardware Implementation Register 2" bitfld.long 0x00 27. "LET ,True little-endian" "0,1" bitfld.long 0x00 26. " IFEB ,Instruction fetch burst extension" "0,1" bitfld.long 0x00 24. " MESISTATE ,MESI state enable" "0,1" TEXTLINE " " bitfld.long 0x00 23. " IFEC ,Instruction fetch cancel extension" "0,1" bitfld.long 0x00 22. " EBQS ,Enable BIU queue sharing" "0,1" bitfld.long 0x00 21. " EBPX ,Enable BIU pipeline extension" "0,1" bitfld.long 0x00 20. " ELRW ,Enable weighted LRU" "0,1" bitfld.long 0x00 19. " NOKS ,NOKS" "0,1" bitfld.long 0x00 18. " HBE ,High BAT enable" "0,1" TEXTLINE " " bitfld.long 0x00 13.--15. " IWLCK ,Instruction cache way-lock" "off,way0,0-1,0-2,0-3,0-4,0-5,0-6" bitfld.long 0x00 12. " ICWP ,Instruction cache way protection" "0,1" bitfld.long 0x00 05.--07. " DWLCK ,Data cache way-lock" "off,way0,0-1,0-2,0-3,0-4,0-5,0-6" tree.end tree "Software Table Search Registers" group SPR:976.++0 line.long 0x00 "DMISS,Data TLB Miss Address Register" group SPR:977.++0 line.long 0x00 "DCMP,Data TLB Compare Registers" bitfld.long 0x00 27. "V ,Valid bit. Set by the processor on a TLB miss interrupt" "0,1" hexmask.long 0x00 07.--24. 1. 0. " VSID ,Virtual segment ID. Copied from VSID field of corresponding segment register" hexmask.byte 0x00 00.--05. 1. 0. " API ,Virtual segment ID. Abbreviated page index. Copied from API of effective address" group SPR:980.++0 line.long 0x00 "IMISS,Instruction TLB Miss Address Register" group SPR:981.++0 line.long 0x00 "ICMP,Instruction TLB Compare Registers" bitfld.long 0x00 27. "V ,Valid bit. Set by the processor on a TLB miss interrupt" "0,1" hexmask.long 0x00 07.--24. 1. 0. " VSID ,Virtual segment ID. Copied from VSID field of corresponding segment register" hexmask.byte 0x00 00.--05. 1. 0. " API ,Virtual segment ID. Abbreviated page index. Copied from API of effective address" group SPR:25.++0 line.long 0x00 "SDR1,SDR1 Register" group SPR:978.++0 line.long 0x00 "HASH1,Primary Hash Address Register" group SPR:979.++0 line.long 0x00 "HASH2,Secondary Hash Address Register" group SPR:982.++0 line.long 0x00 "RPA,Required Physical Address Register" hexmask.long 0x00 12.--31. 1. 0. "RPN ,Physical page number from PTE" bitfld.long 0x00 08. " R ,Referenced bit from PTE" "0,1" bitfld.long 0x00 07. " C ,Changed bit from PTE" "0,1" bitfld.long 0x00 06. " W ,write-through" "0,1" bitfld.long 0x00 05. " I ,caching inhibited" "0,1" bitfld.long 0x00 04. " M ,memory coherency required" "0,1" bitfld.long 0x00 03. " G ,guarded" "0,1" bitfld.long 0x00 00.--01. " PP ,Page protection bits from PTE" "00,01,10,11" tree.end tree "Performance Monitor Registers" GROUP PMR:400.++0. line.LONG 0x0 "PMGC0,Global Control Register 0" bitfld.long 0x00 31. "FAC ,Freeze all counters" "0,1" bitfld.long 0x00 30. " PMIE ,Performance monitor interrupt enable" "0,1" bitfld.long 0x00 29. " FCECE ,Freeze counters on enabled condition or event" "0,1" bitfld.long 0x00 11.--12. " TBSEL ,Time base selector" "TB[63] (TBL[31]),TB[55] (TBL[23]),TB[51] (TBL[19]),TB[47] (TBL[15])" bitfld.long 0x00 08. " TBEE ,Time base transition event exception enable" "0,1" TEXTLINE "" GROUP PMR:144.++0. line.LONG 0x0 "PMLCa0,Local Control A Register 0" bitfld.long 0x00 31. "FC ,Freeze counter" "0,1" bitfld.long 0x00 30. " FCS ,Freeze counter in supervisor state" "0,1" bitfld.long 0x00 29. " FCU ,Freeze counter in user state" "0,1" bitfld.long 0x00 28. " FCM1 ,Freeze counter while mark = 1" "0,1" bitfld.long 0x00 27. " FCM0 ,Freeze counter while mark = 0" "0,1" bitfld.long 0x00 26. " CE ,Condition enable" "0,1" TEXTLINE " " bitfld.long 0x00 16.--22. " EVENT ,Event selector" "Nothing,Processor cycles,Instructions completed,res(3),Instructions fetched,res(5),PM_EVENT transitions,PM_EVENT cycles,Branch instructions completed,Load completed,Store completed,res(11),Branches finished,Taken branches finished,res(14),Branches mispredicted (for anyreason),res(16),res(17),Cycles decode stalled,Cycles issue stalled,res(20),res(21),res(22),res(23),res(24),res(25),res(26),res(27),res(28),res(29),res(30),Cache-inhibited accesses translated,res(32),res(33),res(34),res(35),res(36),res(37),res(38),res(39),res(40),res(41),res(42),res(43),res(44),res(45),res(46),res(47),res(48),res(49),res(50),res(51),res(52),res(53),res(54),res(55),res(56),res(57),res(58),res(59),res(60),Number of instruction fetches that hit,MMU inside miss,res(63),res(64),res(65),res(66),BIU master requests,BIU master instruction-side requests,BIU master data-side requests,res(70),BIU master retries,res(72),res(73),Snoop pushes,res(75),res(76),res(77),res(78),res(79),res(80),res(81),PMC0 overflow,PMC1 overflow,PMC2 overflow,PMC3 overflow,Interrupts taken,External input interrupts taken,Critical input interrupts taken,System call and trap interrupts,Transitions of TBL bit selected by PMGC0[TBSEL],res(91),res(92),res(93),res(94),res(95),i-cache hits,Instructions folded,res(98),res(99),Stalls due to completion buffer,res(101),res(102),res(103),Stalled completion,Stalles due to load,Stalles due to floating-point,res(107),Load and stores to cacheable space,Loads and stores that hit in cache,res(110),res(111),res(112),res(113),res(114),res(115),res(16),res(117),res(118),res(119),res(120),res(121),res(122),res(123),res(124),res(125),res(126),res(127)" GROUP PMR:16.++0. line.LONG 0x0 "PMC0,Performance Monitor Counter Register 0" bitfld.long 0x00 31. "OV ,Overflow" "0,1" hexmask.long 0x00 00.--30. " CNT ,Counter Value" TEXTLINE "" GROUP PMR:145.++0. line.LONG 0x0 "PMLCa1,Local Control A Register 1" bitfld.long 0x00 31. "FC ,Freeze counter" "0,1" bitfld.long 0x00 30. " FCS ,Freeze counter in supervisor state" "0,1" bitfld.long 0x00 29. " FCU ,Freeze counter in user state" "0,1" bitfld.long 0x00 28. " FCM1 ,Freeze counter while mark = 1" "0,1" bitfld.long 0x00 27. " FCM0 ,Freeze counter while mark = 0" "0,1" bitfld.long 0x00 26. " CE ,Condition enable" "0,1" TEXTLINE " " bitfld.long 0x00 16.--22. " EVENT ,Event selector" "Nothing,Processor cycles,Instructions completed,res(3),Instructions fetched,res(5),PM_EVENT transitions,PM_EVENT cycles,Branch instructions completed,Load completed,Store completed,res(11),Branches finished,Taken branches finished,res(14),Branches mispredicted (for anyreason),res(16),res(17),Cycles decode stalled,Cycles issue stalled,res(20),res(21),res(22),res(23),res(24),res(25),res(26),res(27),res(28),res(29),res(30),Cache-inhibited accesses translated,res(32),res(33),res(34),res(35),res(36),res(37),res(38),res(39),res(40),res(41),res(42),res(43),res(44),res(45),res(46),res(47),res(48),res(49),res(50),res(51),res(52),res(53),res(54),res(55),res(56),res(57),res(58),res(59),res(60),Number of instruction fetches that hit,MMU inside miss,res(63),res(64),res(65),res(66),BIU master requests,BIU master instruction-side requests,BIU master data-side requests,res(70),BIU master retries,res(72),res(73),Snoop pushes,res(75),res(76),res(77),res(78),res(79),res(80),res(81),PMC0 overflow,PMC1 overflow,PMC2 overflow,PMC3 overflow,Interrupts taken,External input interrupts taken,Critical input interrupts taken,System call and trap interrupts,Transitions of TBL bit selected by PMGC0[TBSEL],res(91),res(92),res(93),res(94),res(95),i-cache hits,Instructions folded,res(98),res(99),Stalls due to completion buffer,res(101),res(102),res(103),Stalled completion,Stalles due to load,Stalles due to floating-point,res(107),Load and stores to cacheable space,Loads and stores that hit in cache,res(110),res(111),res(112),res(113),res(114),res(115),res(16),res(117),res(118),res(119),res(120),res(121),res(122),res(123),res(124),res(125),res(126),res(127)" GROUP PMR:17.++0. line.LONG 0x0 "PMC1,Performance Monitor Counter Register 1" bitfld.long 0x00 31. "OV ,Overflow" "0,1" hexmask.long 0x00 00.--30. " CNT ,Counter Value" TEXTLINE "" GROUP PMR:146.++0. line.LONG 0x0 "PMLCa2,Local Control A Register 2" bitfld.long 0x00 31. "FC ,Freeze counter" "0,1" bitfld.long 0x00 30. " FCS ,Freeze counter in supervisor state" "0,1" bitfld.long 0x00 29. " FCU ,Freeze counter in user state" "0,1" bitfld.long 0x00 28. " FCM1 ,Freeze counter while mark = 1" "0,1" bitfld.long 0x00 27. " FCM0 ,Freeze counter while mark = 0" "0,1" bitfld.long 0x00 26. " CE ,Condition enable" "0,1" TEXTLINE " " bitfld.long 0x00 16.--22. " EVENT ,Event selector" "Nothing,Processor cycles,Instructions completed,res(3),Instructions fetched,res(5),PM_EVENT transitions,PM_EVENT cycles,Branch instructions completed,Load completed,Store completed,res(11),Branches finished,Taken branches finished,res(14),Branches mispredicted (for anyreason),res(16),res(17),Cycles decode stalled,Cycles issue stalled,res(20),res(21),res(22),res(23),res(24),res(25),res(26),res(27),res(28),res(29),res(30),Cache-inhibited accesses translated,res(32),res(33),res(34),res(35),res(36),res(37),res(38),res(39),res(40),res(41),res(42),res(43),res(44),res(45),res(46),res(47),res(48),res(49),res(50),res(51),res(52),res(53),res(54),res(55),res(56),res(57),res(58),res(59),res(60),Number of instruction fetches that hit,MMU inside miss,res(63),res(64),res(65),res(66),BIU master requests,BIU master instruction-side requests,BIU master data-side requests,res(70),BIU master retries,res(72),res(73),Snoop pushes,res(75),res(76),res(77),res(78),res(79),res(80),res(81),PMC0 overflow,PMC1 overflow,PMC2 overflow,PMC3 overflow,Interrupts taken,External input interrupts taken,Critical input interrupts taken,System call and trap interrupts,Transitions of TBL bit selected by PMGC0[TBSEL],res(91),res(92),res(93),res(94),res(95),i-cache hits,Instructions folded,res(98),res(99),Stalls due to completion buffer,res(101),res(102),res(103),Stalled completion,Stalles due to load,Stalles due to floating-point,res(107),Load and stores to cacheable space,Loads and stores that hit in cache,res(110),res(111),res(112),res(113),res(114),res(115),res(16),res(117),res(118),res(119),res(120),res(121),res(122),res(123),res(124),res(125),res(126),res(127)" GROUP PMR:18.++0. line.LONG 0x0 "PMC2,Performance Monitor Counter Register 2" bitfld.long 0x00 31. "OV ,Overflow" "0,1" hexmask.long 0x00 00.--30. " CNT ,Counter Value" TEXTLINE "" GROUP PMR:147.++0. line.LONG 0x0 "PMLCa3,Local Control A Register 3" bitfld.long 0x00 31. "FC ,Freeze counter" "0,1" bitfld.long 0x00 30. " FCS ,Freeze counter in supervisor state" "0,1" bitfld.long 0x00 29. " FCU ,Freeze counter in user state" "0,1" bitfld.long 0x00 28. " FCM1 ,Freeze counter while mark = 1" "0,1" bitfld.long 0x00 27. " FCM0 ,Freeze counter while mark = 0" "0,1" bitfld.long 0x00 26. " CE ,Condition enable" "0,1" TEXTLINE " " bitfld.long 0x00 16.--22. " EVENT ,Event selector" "Nothing,Processor cycles,Instructions completed,res(3),Instructions fetched,res(5),PM_EVENT transitions,PM_EVENT cycles,Branch instructions completed,Load completed,Store completed,res(11),Branches finished,Taken branches finished,res(14),Branches mispredicted (for anyreason),res(16),res(17),Cycles decode stalled,Cycles issue stalled,res(20),res(21),res(22),res(23),res(24),res(25),res(26),res(27),res(28),res(29),res(30),Cache-inhibited accesses translated,res(32),res(33),res(34),res(35),res(36),res(37),res(38),res(39),res(40),res(41),res(42),res(43),res(44),res(45),res(46),res(47),res(48),res(49),res(50),res(51),res(52),res(53),res(54),res(55),res(56),res(57),res(58),res(59),res(60),Number of instruction fetches that hit,MMU inside miss,res(63),res(64),res(65),res(66),BIU master requests,BIU master instruction-side requests,BIU master data-side requests,res(70),BIU master retries,res(72),res(73),Snoop pushes,res(75),res(76),res(77),res(78),res(79),res(80),res(81),PMC0 overflow,PMC1 overflow,PMC2 overflow,PMC3 overflow,Interrupts taken,External input interrupts taken,Critical input interrupts taken,System call and trap interrupts,Transitions of TBL bit selected by PMGC0[TBSEL],res(91),res(92),res(93),res(94),res(95),i-cache hits,Instructions folded,res(98),res(99),Stalls due to completion buffer,res(101),res(102),res(103),Stalled completion,Stalles due to load,Stalles due to floating-point,res(107),Load and stores to cacheable space,Loads and stores that hit in cache,res(110),res(111),res(112),res(113),res(114),res(115),res(16),res(117),res(118),res(119),res(120),res(121),res(122),res(123),res(124),res(125),res(126),res(127)" GROUP PMR:19.++0. line.LONG 0x0 "PMC3,Performance Monitor Counter Register 3" bitfld.long 0x00 31. "OV ,Overflow" "0,1" hexmask.long 0x00 00.--30. " CNT ,Counter Value" tree.end tree "Debug Registers" group SPR:1010.++0 line.long 0x00 "IABR,Instruction Address Breakpoint Register (used by debugger)" hexmask.long 0x00 02.--31. 0x4 " CEA ,Compare effective address." bitfld.long 0x00 01. " BE ,Breakpoint enable" "0,1" group SPR:1018.++0 line.long 0x00 "IABR2,Instruction Address Breakpoint Register 2 (used by debugger)" hexmask.long 0x00 02.--31. 0x4 " CEA ,Compare effective address." bitfld.long 0x00 01. " BE ,Breakpoint enable" "0,1" TEXTLINE "" group SPR:1013.++0 line.long 0x00 "DABR,Data Address Breakpoint Register (used by debugger)" hexmask.long 0x00 03.--31. 0x8 " CEA ,Compare effective address." bitfld.long 0x00 02. " BT ,Breakpoint translation enable" "0,1" bitfld.long 0x00 01. " WBE ,Data write enable" "0,1" bitfld.long 0x00 00. " RBE ,Data read enable" "0,1" group SPR:317.++0 line.long 0x00 "DABR2,Data Address Breakpoint Register 2 (used by debugger)" hexmask.long 0x00 03.--31. 0x8 " CEA ,Compare effective address." bitfld.long 0x00 02. " BT ,Breakpoint translation enable" "0,1" bitfld.long 0x00 01. " WBE ,Data write enable" "0,1" bitfld.long 0x00 00. " RBE ,Data read enable" "0,1" TEXTLINE "" group SPR:309.++0 line.long 0x00 "IBCR,Instruction Address Breakpoint Control Register (used by debugger)" bitfld.long 0x00 22.--23. " CMP ,IABR breakpoint compare type" "IEA==IABR ,res,IEA=IABR " bitfld.long 0x00 20.--21. " CMP2 ,IABR2 breakpoint compare type" "IEA==IABR2,res,IEA=IABR2" bitfld.long 0x00 17. " SIG_TYPE ,Combinational signal type" "OR,AND" bitfld.long 0x00 16. " DNS ,Do not signal" "0,1" group SPR:310.++0 line.long 0x00 "DBCR,Data Address Breakpoint Control Register (used by debugger)" bitfld.long 0x00 22.--23. " CMP ,DABR breakpoint compare type" "DEA==DABR ,res,DEA=DABR " bitfld.long 0x00 20.--21. " CMP2 ,DABR2 breakpoint compare type" "DEA==DABR2,res,DEA=DABR2" bitfld.long 0x00 17. " SIG_TYPE ,Combinational signal type" "OR,AND" bitfld.long 0x00 16. " DNS ,Do not signal" "0,1" tree.end tree.end ;Default MBAR Address base anc:iobase() tree "Internal Memory Map Register (IMMRBAR)" width 0x9 group.long 0x00++0x03 line.long 0x00 "IMMRBAR,Internal Memory Map Registers Base Address Register" hexmask.long 0x00 20.--31. 0x100000 " BASE_ADDR ,Address Bits of the Internal Memory Window" tree.end tree "System Configuration and Memory Map (IMMRBAR + 0x0000)" width 0xc tree "Local Access Registers" group.long 0x20++0x23 line.long 0x00 "LPBAW,LocalPlus Boot Access Window Registers" hexmask.long.word 0x00 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x00 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x04 "LPCS0AW,CS0 Access Window Register 0" hexmask.long.word 0x04 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x04 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x08 "LPCS1AW,CS1 Access Window Register 1" hexmask.long.word 0x08 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x08 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x0c "LPCS2AW,CS2 Access Window Register 2" hexmask.long.word 0x0c 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x0c 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x10 "LPCS3AW,CS3 Access Window Register 3" hexmask.long.word 0x10 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x10 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x14 "LPCS4AW,CS4 Access Window Register 4" hexmask.long.word 0x14 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x14 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x18 "LPCS5AW,CS5 Access Window Register 5" hexmask.long.word 0x18 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x18 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x1c "LPCS6AW,CS6 Access Window Register 6" hexmask.long.word 0x1c 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x1c 0.--15. 1. " STOP_ADDR ,Stop Adress" line.long 0x20 "LPCS7AW,CS7 Access Window Register 7" hexmask.long.word 0x20 16.--31. 1. " START_ADDR ,Start Adress" hexmask.long.word 0x20 0.--15. 1. " STOP_ADDR ,Stop Adress" group.long 0x60++0x03 line.long 0x00 "PCILAWBAR0,PCI Local Access Window 0 Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " BASE_ADDR ,Base Address of Local Access Window" group.long 0x68++0x03 line.long 0x00 "PCILAWBAR1,PCI Local Access Window 1 Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " BASE_ADDR ,Base Address of Local Access Window" group.long 0x70++0x03 line.long 0x00 "PCILAWBAR2,PCI Local Access Window 2 Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " BASE_ADDR ,Base Address of Local Access Window" group.long 0x64++0x03 line.long 0x00 "PCILAWAR0,PCI Local Access Window 0 Attributes Register" bitfld.long 0x00 31. " EN ,PCI Local Access Window Enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " SIZE ,Size of The Window" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1028 KBytes,2 MBytes,4 MBytes,8 Mbytes,16 MBytes,32 Mbytes,64 Mbytes,128 Mbytes,256 Mbytes,512 Mbytes,1 Gbyte,2 Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0x6c++0x03 line.long 0x00 "PCILAWAR1,PCI Local Access Window 1 Attributes Register" bitfld.long 0x00 31. " EN ,PCI Local Access Window Enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " SIZE ,Size of The Window" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1028 KBytes,2 MBytes,4 MBytes,8 Mbytes,16 MBytes,32 Mbytes,64 Mbytes,128 Mbytes,256 Mbytes,512 Mbytes,1 Gbyte,2 Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0x74++0x03 line.long 0x00 "PCILAWAR2,PCI Local Access Window 2 Attributes Register" bitfld.long 0x00 31. " EN ,PCI Local Access Window Enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " SIZE ,Size of The Window" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1028 KBytes,2 MBytes,4 MBytes,8 Mbytes,16 MBytes,32 Mbytes,64 Mbytes,128 Mbytes,256 Mbytes,512 Mbytes,1 Gbyte,2 Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0xa0++0x07 line.long 0x00 "DDRLAWBAR,DDR Local Access Window Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " BASE_ADDR ,Base Address of the Local Access Window" line.long 0x04 "DDRLAWAR,DDR Local Access Window Attributes Register" bitfld.long 0x04 0.--5. " SIZE ,Size of The Window" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 Mbytes,128 Mbytes,256 Mbytes,512 Mbytes,1 GB,2GB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0xc0++0x10 line.long 0x00 "MBXBAR,MBX Base Address Register" hexmask.long.byte 0x00 24.--31. 0x1 " BASE_ADDR ,Base Address of the MBX Memory Window" line.long 0x04 "SRAMBAR,SRAM Base Address Register" hexmask.long.word 0x04 18.--31. 0x4 " BASE_ADDR ,Base Address of the SRAM Memory Window" line.long 0x08 "NFCBAR,NFC Base Address Register" hexmask.long.word 0x08 20.--31. 0x10 " BASE_ADDR ,Base Address of the NFC Memory Window" tree.end tree "System Configuration Registers" group.long 0x100++0x07 line.long 0x00 "SPRIDR,System Part and Revision ID Register" hexmask.long.word 0x00 16.--31. 1. " PARTID ,Part Identification" hexmask.long.word 0x00 0.--15. 1. " REVID ,Revision Identification" line.long 0x04 "SPCR,System Priority Configuration Register" bitfld.long 0x04 28. " PCIHPE ,PCI Highest Priority Enable" "Disabled,Enabled" bitfld.long 0x04 24.--25. " PCIPR ,PCI Bridge System Bus Request Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x04 22. " TBEN ,PowerPC Core Time Base Unit Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 20.--21. " COREPR ,PowerPC Core System Bus Request Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x04 12.--13. " SAPPR ,SAP and TPR2MG System Bus Request Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x04 10. " MBXBSEN ,MBX Byte Swap Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " TEMPPD ,Temperature Sensor Power Down" "Enabled,Disabled" bitfld.long 0x04 0.--2. " TEMPSEL ,Temperature Sensor Select Trip Point for temp_flt_lo" "105C,95C,85C,75C,65C,55C,45C,35C" tree.end tree.end tree "Reset Module (IMMRBAR + 0x0e00)" width 0xa rgroup.long 0xe00++0x07 line.long 0x00 "RCWLR,Reset Configuration Word Low Register" bitfld.long 0x00 27. " SPMF3 ,System PLL Multiplication Factor" "Low,High" bitfld.long 0x00 26. " SPMF2 ,System PLL Multiplication Factor" "Low,High" bitfld.long 0x00 25. " SPMF1 ,System PLL Multiplication Factor" "Low,High" textline " " bitfld.long 0x00 24. " SPMF0 ,System PLL Multiplication Factor" "Low,High" bitfld.long 0x00 19. " CPMF3 ,Core PLL Configuration" "Low,High" bitfld.long 0x00 18. " CPMF2 ,Core PLL Configuration" "Low,High" textline " " bitfld.long 0x00 17. " CPMF1 ,Core PLL Configuration" "Low,High" bitfld.long 0x00 16. " CPMF0 ,Core PLL Configuration" "Low,High" bitfld.long 0x00 13. " SYSDIV5 ,SYSDIV" "Low,High" textline " " bitfld.long 0x00 12. " SYSDIV4 ,SYSDIV" "Low,High" bitfld.long 0x00 11. " SYSDIV3 ,SYSDIV" "Low,High" bitfld.long 0x00 10. " SYSDIV2 ,SYSDIV" "Low,High" textline " " bitfld.long 0x00 9. " SYSDIV1 ,SYSDIV" "Low,High" bitfld.long 0x00 8. " SYSDIV0 ,SYSDIV" "Low,High" line.long 0x04 "RCWHR,Reset Configuration Word High Register" bitfld.long 0x04 30. " PCI66EN ,PCI 66 Enable" "Low,High" bitfld.long 0x04 29. " PCIARB ,PCI Internal Arbiter Mode" "Low,High" textline " " bitfld.long 0x04 28. " SYSOSCEN ,System oscillator enable" "Disabled,Enabled" bitfld.long 0x04 27. " COREDIS ,Core Disable Mode" "Low,High" textline " " bitfld.long 0x04 26. " BMS ,Boot Memory Space" "Low,High" bitfld.long 0x04 23. " SWEN ,Software Watchdog Enable" "Low,High" textline " " bitfld.long 0x04 22. " ROMLOC1 ,Boot ROM Interface Location 1" "Low,High" bitfld.long 0x04 21. " ROMLOC0 ,Boot ROM Interface Location 0" "Low,High" bitfld.long 0x04 20. " TPR ,TPR Pin Muxing" "Low,High" textline " " bitfld.long 0x04 11. " LPC_MX ,LPC Muxed Mode" "Low,High" bitfld.long 0x04 10. " LPC_WA ,LPC Word/Byte Address" "Low,High" bitfld.long 0x04 9. " LPC_DBW1 ,LPC Data Bus Width 1" "Low,High" textline " " bitfld.long 0x04 8. " LPC_DBW0 ,LPC Data Bus Width 0" "Low,High" bitfld.long 0x04 7. " NFC_PS ,NFC Page Size" "Low,High" bitfld.long 0x04 6. " NFC_DBW ,NFC Data Bus Width" "Low,High" textline " " bitfld.long 0x04 5. " LPC_AX1 ,LPC Extended Address Bus 1" "Low,High" bitfld.long 0x04 4. " LPC_AX0 ,LPC Extended Address Bus 0" "Low,High" bitfld.long 0x04 3. " TLE ,True Little-Endian" "Low,High" textline " " bitfld.long 0x04 2. " CKS_IN ,Checkstop in Pin Muxing" "Low,High" group.long 0xe10++0x0b line.long 0x00 "RSR,Reset Status Register" eventfld.long 0x00 13. " SWSR ,Software Soft Reset" "Not occurred,Occurred" eventfld.long 0x00 12. " SWHR ,Software Hard Reset" "Not occurred,Occurred" textline " " eventfld.long 0x00 9. " JHRS ,JTAG hard reset status" "Not occurred,Occurred" eventfld.long 0x00 8. " JSRS ,JTAG Soft Reset Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " CSHR ,Check Stop Reset Status" "Not occurred,Occurred" eventfld.long 0x00 3. " SWRS ,Software Watchdog Reset Status" "Not occurred,Occurred" eventfld.long 0x00 2. " BMRS ,Bus Monitor Reset Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " SRS ,Soft Reset Status" "Not occurred,Occurred" eventfld.long 0x00 0. " HRS ,Hard Reset Status" "Not occurred,Occurred" line.long 0x04 "RMR,Reset Mode Register" bitfld.long 0x04 0. " CSRE ,Checkstop Reset Enable" "Not generated,Generated" line.long 0x08 "RPR,Reset Protection Register" if (((d.l(anc:(iobase()+0xe00+0x20)))&0x1)==0x1) group.long 0xe1c++0x03 line.long 0x00 "RCR,Reset Control Register" bitfld.long 0x00 1. " SWHR ,Software Hard Reset" "No reset,Reset" bitfld.long 0x00 0. " SWSR ,Software Soft Reset" "No reset,Reset" else hgroup.long 0xe1c++0x03 hide.long 0x00 "RCR,Reset Control Register" endif group.long 0xe20++0x03 line.long 0x00 "RCER,Reset Control Enable Register" eventfld.long 0x00 0. " CRE ,Control Register Enabled" "Disabled,Enabled" tree.end tree "Clock Control Module (IMMRMBAR + 0x0F00)" width 0xa rgroup.long 0xf00++0x03 line.long 0x00 "SPMR,System PLL Mode Register" bitfld.long 0x00 24.--27. " SPMF ,System PLL Multiplication Factor" "68,PLL BYPASS,12,16,20,24,28,32,36,40,44,48,52,56,60,64" bitfld.long 0x00 16.--19. " CMPF ,Core PLL Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xf04++0x13 line.long 0x00 "SCCR1,System Clock Control Register 1" bitfld.long 0x00 31. " CFG_EN ,Access to the Memory Map Configuration Registers for IO_CONTROL and MEMMAP Configuration Enable" "Disabled,Enabled" bitfld.long 0x00 30. " LPC_EN ,lpc_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " NFC_EN ,nfc_clk Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PATA_EN ,pata_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PSC0_EN ,PSC0_clk Enable" "Disabled,Enabled" bitfld.long 0x00 26. " PSC1_EN ,PSC1_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " PSC2_EN ,PSC2_clk Enable" "Disabled,Enabled" bitfld.long 0x00 24. " PSC3_EN ,PSC3_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " PSC4_EN ,PSC4_clk Enable" "Disabled,Enabled" bitfld.long 0x00 22. " PSC5_EN ,PSC5_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PSC6_EN ,PSC6_clk Enable" "Disabled,Enabled" bitfld.long 0x00 20. " PSC7_EN ,PSC7_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PSC8_EN ,PSC8_clk Enable" "Disabled,Enabled" bitfld.long 0x00 18. " PSC9_EN ,PSC9_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PSC10_EN ,PSC10_clk Enable" "Disabled,Enabled" bitfld.long 0x00 16. " PSC11_EN ,PSC11_clk Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SFIFO_EN ,SFIFO Clock Enable" "Disabled,Enabled" bitfld.long 0x00 14. " SATA_EN ,SATA Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FEC_EN ,FEC Clock Enable" "Disabled,Enabled" bitfld.long 0x00 12. " TPR_EN ,TPR Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PCI_EN ,PCI Clock Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DDR_EN ,MDDRC Clock Enable" "Disabled,Enabled" line.long 0x04 "SCCR2,System Clock Control Register 2" bitfld.long 0x04 31. " DIU_EN ,DIU Clock Enable" "Disabled,Enabled" bitfld.long 0x04 30. " AXE_EN ,AXE Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " MEM_EN ,MEM Clock Enable" "Disabled,Enabled" bitfld.long 0x04 28. " USB1_EN ,USB1 Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " USB2_EN ,USB2 Clock Enable" "Disabled,Enabled" bitfld.long 0x04 26. " I2C_EN ,I2C Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " BDLC_EN ,BDLC and MSCAN Clock Enable" "Disabled,Enabled" bitfld.long 0x04 24. " SDHC_EN ,SDHC Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " SPDIF_EN ,SPDIF Clock Enable" "Disabled,Enabled" bitfld.long 0x04 22. " MBX_BUS_EN ,IMBX BUS Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " MBX_EN ,MBX Clock Enable" "Disabled,Enabled" bitfld.long 0x04 20. " MBX_3D_EN ,MBX 3D Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " IIM_EN ,IIM Clock Enable" "Disabled,Enabled" bitfld.long 0x04 18. " VIDEO_IN_EN ,VIDEO_IN Clock Enable" "Disabled,Enabled" line.long 0x08 "SCFR1,System Clock Frequency Register 1" bitfld.long 0x08 23.--25. " IPS_DIV ,IPS Clock Divide Ratio" "Reserved,Reserved,1/2,1/3,1/4,Reserved,1/6,Reserved" bitfld.long 0x08 20.--22. " PCI_DIV ,PCI Clock Divide Ratio" "Reserved,Reserved,1/2,1/3,1/4,Reserved,1/6,Reserved" textline " " bitfld.long 0x08 14.--16. " MBS_GPX_DIV ,MBX 3D Clock Divide Ratio" "Reserved,1/1,1/2,1/3,1/4,Reserved,Reserved,Reserved" bitfld.long 0x08 11.--13. " LPC_DIV ,LPC Clock Divide Ratio" "Reserved,1/1,1/2,1/3,1/4,Reserved,Reserved,Reserved" textline " " bitfld.long 0x08 8.--10. " NFC_DIV ,NFC Divide Ratio" "Reserved,1/1,1/2,1/3,1/4,Reserved,Reserved,Reserved" hexmask.long.byte 0x08 0.--7. 1. " DIU_DIV ,DIU Divide Ratio" line.long 0x0c "SCFR2,System Clock Frequency Register 2" bitfld.long 0x0c 26.--31. " SYS_DIV ,SYS_CLK Divide Ratio" "2,2.5,3,3.5,4,4.5,5,7,6,8,9,11,10,12,13,15,14,16,17,19,18,20,21,23,22,24,25,27,26,28,29,31,30,32,33,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" hexmask.long.byte 0x0c 0.--7. 1. " SDHC_DIV ,SDHC Divide Ratio" line.long 0x10 "SCFR2S,Shadow of System Clock Frequency Register 2" bitfld.long 0x10 26.--31. " SYS_DIV ,SYS_CLK Divide Ratio" "2,2.5,3,3.5,4,4.5,5,7,6,8,9,11,10,12,13,15,14,16,17,19,18,20,21,23,22,24,25,27,26,28,29,31,30,32,33,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" hexmask.long.byte 0x10 0.--7. 1. " SDHC_DIV ,SDHC Divide Ratio" hgroup.long 0xf18++0x03 hide.long 0x00 "BCR,Bread Crumb Register" group.long 0xf1c++0x3b line.long 0x0 "P0CCR,PSC0 Clock Control Register" hexmask.long.word 0x0 17.--31. 1. " PSC0_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x0 16. " MCLK_0_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14.--15. " PSC0_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x0 7. " PSC0_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x4 "P1CCR,PSC1 Clock Control Register" hexmask.long.word 0x4 17.--31. 1. " PSC1_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x4 16. " MCLK_1_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 14.--15. " PSC1_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x4 7. " PSC1_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x8 "P2CCR,PSC2 Clock Control Register" hexmask.long.word 0x8 17.--31. 1. " PSC2_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x8 16. " MCLK_2_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 14.--15. " PSC2_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x8 7. " PSC2_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0xC "P3CCR,PSC3 Clock Control Register" hexmask.long.word 0xC 17.--31. 1. " PSC3_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0xC 16. " MCLK_3_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 14.--15. " PSC3_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0xC 7. " PSC3_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x10 "P4CCR,PSC4 Clock Control Register" hexmask.long.word 0x10 17.--31. 1. " PSC4_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x10 16. " MCLK_4_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x10 14.--15. " PSC4_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x10 7. " PSC4_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x14 "P5CCR,PSC5 Clock Control Register" hexmask.long.word 0x14 17.--31. 1. " PSC5_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x14 16. " MCLK_5_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 14.--15. " PSC5_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x14 7. " PSC5_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x18 "P6CCR,PSC6 Clock Control Register" hexmask.long.word 0x18 17.--31. 1. " PSC6_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x18 16. " MCLK_6_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 14.--15. " PSC6_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x18 7. " PSC6_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x1C "P7CCR,PSC7 Clock Control Register" hexmask.long.word 0x1C 17.--31. 1. " PSC7_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x1C 16. " MCLK_7_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 14.--15. " PSC7_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x1C 7. " PSC7_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x20 "P8CCR,PSC8 Clock Control Register" hexmask.long.word 0x20 17.--31. 1. " PSC8_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x20 16. " MCLK_8_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 14.--15. " PSC8_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x20 7. " PSC8_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x24 "P9CCR,PSC9 Clock Control Register" hexmask.long.word 0x24 17.--31. 1. " PSC9_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x24 16. " MCLK_9_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x24 14.--15. " PSC9_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x24 7. " PSC9_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x28 "P10CCR,PSC10 Clock Control Register" hexmask.long.word 0x28 17.--31. 1. " PSC10_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x28 16. " MCLK_10_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x28 14.--15. " PSC10_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x28 7. " PSC10_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x2C "P11CCR,PSC11 Clock Control Register" hexmask.long.word 0x2C 17.--31. 1. " PSC11_MCLK_DIV ,MCLK_DIV divider Ratio" bitfld.long 0x2C 16. " MCLK_11_EN ,PSC Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 14.--15. " PSC11_MCLK_0_SRC ,PSC Mclk Divider Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x2C 7. " PSC11_MCLK_1_SRC ,PSC MCLK Source" "MCLK_DIV,SPDIF_RX CLOCK" line.long 0x30 "SPCCR,SPDIF Clock Control Register" hexmask.long.word 0x30 17.--31. 1. " SPDIF_MCLK_RATIO ,SPDIF Mclk Divider Ratio" bitfld.long 0x30 16. " DE5 ,SPDIF Mclk Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x30 14.--15. " SPDIF_CLK_SRC ,SPDIF Mclk Divider Source" "XCLK,OSC_CLK,PSC_MCLK_IN,SPDIF_TXCLK" bitfld.long 0x30 7. " SPDIF_TX_SRC ,SPDIF MCLK Source" "SPDIF Clock Divider,Spdif RX Clock" line.long 0x34 "CCCR,CFM Clock Control Register" bitfld.long 0x34 29.--31. " CFM_SRC0 ,CFM Clock 0 Source Selection" "psc0_mclk_out,psc1_mclk_out,psc2_mclk_out,Reserved,psc0_bclk,psc1_bclk,psc2_bclk,Reserved" bitfld.long 0x34 21.--23. " CFM_SRC1 ,CFM Clock 1 Source Selection" "psc3_mclk_out,psc4_mclk_out,psc5_mclk_out,Reserved,psc3_bclk,psc4_bclk,psc5_bclk,Reserved" textline " " bitfld.long 0x34 13.--15. " CFM_SRC2 ,CFM Clock 2 Source Selection" "psc6_mclk_out,psc7_mclk_out,psc8_mclk_out,Reserved,psc6_bclk,psc7_bclk,psc8_bclk,Reserved" bitfld.long 0x34 5.--7. " CFM_SRC3 ,CFM Clock 3 Source Selection" "psc9_mclk_out,psc10_mclk_out,psc11_mclk_out,Reserved,psc9_bclk,psc10_bclk,psc11_bclk,Reserved" line.long 0x38 "DCCR,DIU Clock Config Register" bitfld.long 0x38 30.--31. " DLY_NUM ,Number of DDR_CLK Cycles Delay" "0 cycle,2 cycle,4 cycle,6 cycle" bitfld.long 0x38 24. " CLK_INV ,Pixel Clock Inversion" "Same,Inverted" group.long 0xF58++0x03 line.long 0x00 "M1CCR,MSCAN1Clock Control Register" hexmask.long.word 0x00 17.--31. 1. " MSCAN1_CLK_DIV ,MSCAN1 divider Ratio" bitfld.long 0x00 16. " MSCAN1_EN ,MSCAN1 Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " MSCAN1_CLK_SRC ,MSCAN1 CLK Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" group.long 0xF5C++0x03 line.long 0x00 "M2CCR,MSCAN2Clock Control Register" hexmask.long.word 0x00 17.--31. 1. " MSCAN1_CLK_DIV ,MSCAN1 divider Ratio" bitfld.long 0x00 16. " MSCAN1_EN ,MSCAN1 Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " MSCAN1_CLK_SRC ,MSCAN1 CLK Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" group.long 0xF60++0x03 line.long 0x00 "M3CCR,MSCAN3Clock Control Register" hexmask.long.word 0x00 17.--31. 1. " MSCAN1_CLK_DIV ,MSCAN1 divider Ratio" bitfld.long 0x00 16. " MSCAN1_EN ,MSCAN1 Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " MSCAN1_CLK_SRC ,MSCAN1 CLK Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" group.long 0xF64++0x03 line.long 0x00 "M4CCR,MSCAN4Clock Control Register" hexmask.long.word 0x00 17.--31. 1. " MSCAN1_CLK_DIV ,MSCAN1 divider Ratio" bitfld.long 0x00 16. " MSCAN1_EN ,MSCAN1 Divider Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14.--15. " MSCAN1_CLK_SRC ,MSCAN1 CLK Source" "SYS_CLK,REF_CLK,PSC_MCLK_IN,SPDIF_TXCLK" width 0xb tree.end tree "AXE Processor (IMMRBAR + 0x2000)" width 0xa tree "DMA Operation" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2000++0x0b line.long 0x00 "DMAR,DMA Magenta Address Register" hexmask.long 0x00 2.--31. 0x4 " DMA_MAGENTA_ADDR ,Address The Local DMA for The Next Transfer" line.long 0x04 "DMAMEMAR,DMA MEM Address Register" hexmask.long 0x04 0.--19. 1. " DMA_MEM_ADDR ,Contains the first or next address the DMA uses to address the on-chip SRAM" line.long 0x08 "DMAAR,DMA Attributes Register" bitfld.long 0x08 20. " DMA_DIRECTION ,Dma Write Direction" "SRAM/DDR or IP Bus,DDR or IP Bus/SRAM" bitfld.long 0x08 19. " INT_EN ,Intpend Bit Interrupt" "Not sent,Sent" textline " " bitfld.long 0x08 18. " INT_CLEAR ,Clear Intpend Bit" "No effect,Clear" bitfld.long 0x08 17. " INT_PEND ,Interrupt Pending" "Not completed,Completed" textline " " bitfld.long 0x08 16. " DMA_ON ,DMA on Bit" "Not Armed,Armed/WORD_COUNT=0" hexmask.long.word 0x08 2.--15. 1. " WORD_COUNT[13:0] ,Number of 32-bit Words the DMA Transfers" endif tree.end tree "Instruction Cache and SRAM Operation" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x200c++0x03 line.long 0x00 "ICSAR,Instruction Cache and SRAM Attributes Register" bitfld.long 0x00 25. " SLEEP ,Sleep/Run Mode" "Run/Normal,Sleep/Stopped" bitfld.long 0x00 24. " SRAM2_DUSER_ON ,On-chip SRAM For Data Accesses in User Mode Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SRAM2_DRSUP_ON ,On-chip SRAM For Data Accesses in Supervisor Mode Enabled" "Disabled,Enabled" bitfld.long 0x00 22. " SRAM2_IUSER_ON ,On-chip SRAM For Instructions Accesses in User Mode Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " SRAM2_ISUP_ON ,On-chip SRAM For Instructions Accesses in Supervisor Mode Enabled" "Disabled,Enabled" bitfld.long 0x00 20. " CACHE_ON ,Instruction Cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CACHE_CLEAR ,Instruction Cache Clear" "No effect,Clear" bitfld.long 0x00 18. " IRAM_USER_ON ,Instruction SRAM for Instruction Accesses in User Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IRAM_SUP_ON ,Instruction SRAM for Instruction Accesses in Supervisor Mode Enable" "Disabled,Enabled" bitfld.long 0x00 16. " PROC_RST ,Processor Reset" "Not kept in reset,Kept in reset" endif tree.end tree "Interrupt Controller" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2010++0x1f line.long 0x00 "INTPRI0,INTPRI0 Interrupt Priority Register" bitfld.long 0x00 30. " INT0_ON ,Interrupt 0 Enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--29. 1. " INT0_PRI ,Interrupt 0 Priority Level" textline " " bitfld.long 0x00 22. " INT1_ON ,Interrupt 1 Enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--21. 1. " INT1_PRI ,Interrupt 1 Priority Level" textline " " bitfld.long 0x00 14. " INT2_ON ,Interrupt 2 Enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " INT2_PRI ,Interrupt 2 Priority Level" textline " " bitfld.long 0x00 6. " INT3_ON ,Interrupt 3 Enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--5. 1. " INT3_PRI ,Interrupt 3 Priority Level" line.long 0x04 "INTPRI1,INTPRI1 Interrupt Priority Register" bitfld.long 0x04 30. " INT4_ON ,Interrupt 4 Enable" "Disabled,Enabled" hexmask.long.byte 0x04 24.--29. 1. " INT4_PRI ,Interrupt 4 Priority Level" textline " " bitfld.long 0x04 22. " INT5_ON ,Interrupt 5 Enable" "Disabled,Enabled" hexmask.long.byte 0x04 16.--21. 1. " INT5_PRI ,Interrupt 5 Priority Level" textline " " bitfld.long 0x04 14. " INT6_ON ,Interrupt 6 Enable" "Disabled,Enabled" hexmask.long.byte 0x04 8.--13. 1. " INT6_PRI ,Interrupt 6 Priority Level" textline " " bitfld.long 0x04 6. " INT7_ON ,Interrupt 7 Enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--5. 1. " INT7_PRI ,Interrupt 7 Priority Level" line.long 0x08 "INTPRI2,INTPRI2 Interrupt Priority Register" bitfld.long 0x08 30. " INT8_ON ,Interrupt 8 Enable" "Disabled,Enabled" hexmask.long.byte 0x08 24.--29. 1. " INT8_PRI ,Interrupt 8 Priority Level" textline " " bitfld.long 0x08 22. " INT9_ON ,Interrupt 9 Enable" "Disabled,Enabled" hexmask.long.byte 0x08 16.--21. 1. " INT9_PRI ,Interrupt 9 Priority Level" textline " " bitfld.long 0x08 14. " INT10_ON ,Interrupt 10 Enable" "Disabled,Enabled" hexmask.long.byte 0x08 8.--13. 1. " INT10_PRI ,Interrupt 10 Priority Level" textline " " bitfld.long 0x08 6. " INT11_ON ,Interrupt 11 Enable" "Disabled,Enabled" hexmask.long.byte 0x08 0.--5. 1. " INT11_PRI ,Interrupt 11 Priority Level" line.long 0x0c "INTPRI3,INTPRI3 Interrupt Priority Register" bitfld.long 0x0c 30. " INT12_ON ,Interrupt 12 Enable" "Disabled,Enabled" hexmask.long.byte 0x0c 24.--29. 1. " INT12_PRI ,Interrupt 12 Priority Level" textline " " bitfld.long 0x0c 22. " INT13_ON ,Interrupt 13 Enable" "Disabled,Enabled" hexmask.long.byte 0x0c 16.--21. 1. " INT13_PRI ,Interrupt 13 Priority Level" textline " " bitfld.long 0x0c 14. " INT14_ON ,Interrupt 14 Enable" "Disabled,Enabled" hexmask.long.byte 0x0c 8.--13. 1. " INT14_PRI ,Interrupt 14 Priority Level" textline " " bitfld.long 0x0c 6. " INT15_ON ,Interrupt 15 Enable" "Disabled,Enabled" hexmask.long.byte 0x0c 0.--5. 1. " INT15_PRI ,Interrupt 15 Priority Level" line.long 0x10 "INTPRI4,INTPRI4 Interrupt Priority Register" bitfld.long 0x10 30. " INT16_ON ,Interrupt 61 Enable" "Disabled,Enabled" hexmask.long.byte 0x10 24.--29. 1. " INT16_PRI ,Interrupt 16 Priority Level" textline " " bitfld.long 0x10 22. " INT17_ON ,Interrupt 17 Enable" "Disabled,Enabled" hexmask.long.byte 0x10 16.--21. 1. " INT17_PRI ,Interrupt 17 Priority Level" textline " " bitfld.long 0x10 14. " INT18_ON ,Interrupt 18 Enable" "Disabled,Enabled" hexmask.long.byte 0x10 8.--13. 1. " INT18_PRI ,Interrupt 18 Priority Level" textline " " bitfld.long 0x10 6. " INT19_ON ,Interrupt 19 Enable" "Disabled,Enabled" hexmask.long.byte 0x10 0.--5. 1. " INT19_PRI ,Interrupt 19 Priority Level" line.long 0x14 "INTPRI5,INTPRI5 Interrupt Priority Register" bitfld.long 0x14 30. " INT20_ON ,Interrupt 20 Enable" "Disabled,Enabled" hexmask.long.byte 0x14 24.--29. 1. " INT20_PRI ,Interrupt 20 Priority Level" textline " " bitfld.long 0x14 22. " INT21_ON ,Interrupt 21 Enable" "Disabled,Enabled" hexmask.long.byte 0x14 16.--21. 1. " INT21_PRI ,Interrupt 21 Priority Level" textline " " bitfld.long 0x14 14. " INT22_ON ,Interrupt 22 Enable" "Disabled,Enabled" hexmask.long.byte 0x14 8.--13. 1. " INT22_PRI ,Interrupt 22 Priority Level" textline " " bitfld.long 0x14 6. " INT23_ON ,Interrupt 23 Enable" "Disabled,Enabled" hexmask.long.byte 0x14 0.--5. 1. " INT23_PRI ,Interrupt 23 Priority Level" line.long 0x18 "INTPRI6,INTPRI6 Interrupt Priority Register" bitfld.long 0x18 30. " INT24_ON ,Interrupt 24 Enable" "Disabled,Enabled" hexmask.long.byte 0x18 24.--29. 1. " INT24_PRI ,Interrupt 24 Priority Level" textline " " bitfld.long 0x18 22. " INT25_ON ,Interrupt 25 Enable" "Disabled,Enabled" hexmask.long.byte 0x18 16.--21. 1. " INT25_PRI ,Interrupt 25 Priority Level" textline " " bitfld.long 0x18 14. " INT26_ON ,Interrupt 26 Enable" "Disabled,Enabled" hexmask.long.byte 0x18 8.--13. 1. " INT26_PRI ,Interrupt 26 Priority Level" textline " " bitfld.long 0x18 6. " INT27_ON ,Interrupt 27 Enable" "Disabled,Enabled" hexmask.long.byte 0x18 0.--5. 1. " INT27_PRI ,Interrupt 27 Priority Level" line.long 0x1c "INTPRI7,INTPRI7 Interrupt Priority Register" bitfld.long 0x1c 30. " INT28_ON ,Interrupt 28 Enable" "Disabled,Enabled" hexmask.long.byte 0x1c 24.--29. 1. " INT28_PRI ,Interrupt 28 Priority Level" textline " " bitfld.long 0x1c 22. " INT29_ON ,Interrupt 29 Enable" "Disabled,Enabled" hexmask.long.byte 0x1c 16.--21. 1. " INT29_PRI ,Interrupt 29 Priority Level" textline " " bitfld.long 0x1c 14. " INT30_ON ,Interrupt 30 Enable" "Disabled,Enabled" hexmask.long.byte 0x1c 8.--13. 1. " INT30_PRI ,Interrupt 30 Priority Level" textline " " bitfld.long 0x1c 6. " INT31_ON ,Interrupt 31 Enable" "Disabled,Enabled" hexmask.long.byte 0x1c 0.--5. 1. " INT31_PRI ,Interrupt 31 Priority Level" endif tree.end tree "Instruction Cache Indirect Access" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2030++0x07 line.long 0x00 "ISAR,Instruction SRAM Address Register" hexmask.long.word 0x00 2.--15. 0x4 " INSTR_ADDR ,Address into Instruction RAM" line.long 0x04 "ISDR,Instruction SRAM Data Register" endif tree.end tree "Inter Processor Communication FIFOs" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else hgroup.long 0x203c++0x03 hide.long 0x00 "F1WDR,FIFO1 Write Data Register" in hgroup.long 0x2040++0x03 hide.long 0x00 "F1RDR,FIFO1 Read Data Register" in hgroup.long 0x2044++0x03 hide.long 0x00 "F2WDR,FIFO2 Write Data Register" in hgroup.long 0x2048++0x03 hide.long 0x00 "F2RDR,FIFO2 Read Data Register" in rgroup.long 0x204c++0x03 line.long 0x00 "FFR,FIFO Filling Register" bitfld.long 0x00 24.--26. " FIFO1_FILL ,FIFO 1 filling" "000,001,010,011,100,101,110,111" bitfld.long 0x00 16.--18. " FIFO2_FILL ,FIFO 2 filling" "000,001,010,011,100,101,110,111" wgroup 0x00++0x00 endif tree.end textline " " if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2050++0x07 line.long 0x00 "SNEIER,SNE Interrupt Enable Register" bitfld.long 0x00 31. " SNESOFTINT7 ,SNE Software Interrupt 7" "Disabled,Enabled" bitfld.long 0x00 30. " SNESOFTINT6 ,SNE Software Interrupt 6" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " SNESOFTINT5 ,SNE Software Interrupt 5" "Disabled,Enabled" bitfld.long 0x00 28. " SNESOFTINT4 ,SNE Software Interrupt 4" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SNESOFTINT3 ,SNE Software Interrupt 3" "Disabled,Enabled" bitfld.long 0x00 26. " SNESOFTINT2 ,SNE Software Interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SNESOFTINT1 ,SNE Software Interrupt 1" "Disabled,Enabled" bitfld.long 0x00 24. " SNESOFTINT0 ,SNE Software Interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SF1EE ,SNE FIFO 1 Empty Interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " SF1NEE ,SNE FIFO 1 Not Empty Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " SF1NFE ,SNE FIFO 1 Not Full Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " SF1UE ,SNE FIFO 1 Underflow Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SF1OE ,SNE FIFO 1 Overflow Interrupt" "Disabled,Enabled" bitfld.long 0x00 15. " SF2EE ,SNE FIFO 2 Empty Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " SF2NEE ,SNE FIFO 2 Not Empty Interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " SF2NFE ,SNE FIFO 2 Not Full Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SF2UE ,SNE FIFO 2 Underflow Interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " SF2OE ,SNE FIFO 2 Overflow Interrupt" "Disabled,Enabled" line.long 0x04 "PAIER,Power Architecture Interrupt Enable Register" bitfld.long 0x04 31. " PPCSOFTINT7 ,PPC Software Interrupt 7" "Disabled,Enabled" bitfld.long 0x04 30. " PPCSOFTINT6 ,PPC Software Interrupt 6" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " PPCSOFTINT5 ,PPC Software Interrupt 5" "Disabled,Enabled" bitfld.long 0x04 28. " PPCSOFTINT4 ,PPC Software Interrupt 4" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " PPCSOFTINT3 ,PPC Software Interrupt 3" "Disabled,Enabled" bitfld.long 0x04 26. " PPCSOFTINT2 ,PPC Software Interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " PPCSOFTINT1 ,PPC Software Interrupt 1" "Disabled,Enabled" bitfld.long 0x04 24. " PPCSOFTINT0 ,PPC Software Interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " PF1EE ,PPC FIFO 1 Empty Interrupt" "Disabled,Enabled" bitfld.long 0x04 22. " PF1NEE ,PPC FIFO 1 Not Empty Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " PF1NFE ,PPC FIFO 1 Not Full Interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " PF1UE ,PPC FIFO 1 Underflow Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " PF1OE ,PPC FIFO 1 Overflow Interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " PF2EE ,PPC FIFO 2 Empty Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PF2NEE ,PPC FIFO 2 Not Empty Interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " PF2NFE ,PPC FIFO 2 Not Full Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " PF2UE ,PPC FIFO 2 Underflow Interrupt" "Disabled,Enabled" bitfld.long 0x04 11. " PF2OE ,PPC FIFO 2 Overflow Interrupt" "Disabled,Enabled" rgroup.long 0x205c++0x03 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " SOFTINT7 ,Software Interrupt 7" "Not pending,Pending" bitfld.long 0x00 30. " SOFTINT6 ,Software Interrupt 6" "Not pending,Pending" textline " " bitfld.long 0x00 29. " SOFTINT5 ,Software Interrupt 5" "Not pending,Pending" bitfld.long 0x00 28. " SOFTINT4 ,Software Interrupt 4" "Not pending,Pending" textline " " bitfld.long 0x00 27. " SOFTINT3 ,Software Interrupt 3" "Not pending,Pending" bitfld.long 0x00 26. " SOFTINT2 ,Software Interrupt 2" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SOFTINT1 ,Software Interrupt 1" "Not pending,Pending" bitfld.long 0x00 24. " SOFTINT0 ,Software Interrupt 0" "Not pending,Pending" textline " " bitfld.long 0x00 23. " F1EP ,FIFO 1 Empty Interrupt" "Not pending,Pending" bitfld.long 0x00 22. " F1NEP ,FIFO 1 Not Empty Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 21. " F1NFP ,FIFO 1 Not Full Interrupt" "Not pending,Pending" bitfld.long 0x00 20. " F1UP ,FIFO 1 Underflow Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 19. " F1OP ,FIFO 1 Overflow Interrupt" "Not pending,Pending" bitfld.long 0x00 15. " F2EP ,FIFO 2 Empty Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 14. " F2NEP ,FIFO 2 Not Empty Interrupt" "Not pending,Pending" bitfld.long 0x00 13. " F2NFP ,FIFO 2 Not Full Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 12. " F2UP ,FIFO 2 Underflow Interrupt" "Not pending,Pending" bitfld.long 0x00 11. " F2OP ,FIFO 2 Overflow Interrupt" "Not pending,Pending" wgroup.long 0x2058++0x03 line.long 0x00 "ICSR,IntClearSet Register" bitfld.long 0x00 31. " SOFTINT_SET7 ,Software Interrupt 7 Set" "No effect,Set" bitfld.long 0x00 30. " SOFTINT_SET6 ,Software Interrupt 6 Set" "No effect,Set" textline " " bitfld.long 0x00 29. " SOFTINT_SET5 ,Software Interrupt 5 Set" "No effect,Set" bitfld.long 0x00 28. " SOFTINT_SET4 ,Software Interrupt 4 Set" "No effect,Set" textline " " bitfld.long 0x00 27. " SOFTINT_SET3 ,Software Interrupt 3 Set" "No effect,Set" bitfld.long 0x00 26. " SOFTINT_SET2 ,Software Interrupt 2 Set" "No effect,Set" textline " " bitfld.long 0x00 25. " SOFTINT_SET1 ,Software Interrupt 1 Set" "No effect,Set" bitfld.long 0x00 24. " SOFTINT_SET0 ,Software Interrupt 0 Set" "No effect,Set" textline " " bitfld.long 0x00 23. " SOFTINT_CLEAR7 ,Software Interrupt 7 Clear" "No effect,Clear" bitfld.long 0x00 22. " SOFTINT_CLEAR6 ,Software Interrupt 6 Clear" "No effect,Clear" textline " " bitfld.long 0x00 21. " SOFTINT_CLEAR5 ,Software Interrupt 5 Clear" "No effect,Clear" bitfld.long 0x00 20. " SOFTINT_CLEAR4 ,Software Interrupt 4 Clear" "No effect,Clear" textline " " bitfld.long 0x00 19. " SOFTINT_CLEAR3 ,Software Interrupt 3 Clear" "No effect,Clear" bitfld.long 0x00 18. " SOFTINT_CLEAR2 ,Software Interrupt 2 Clear" "No effect,Clear" textline " " bitfld.long 0x00 17. " SOFTINT_CLEAR1 ,Software Interrupt 1 Clear" "No effect,Clear" bitfld.long 0x00 16. " SOFTINT_CLEAR0 ,Software Interrupt 0 Clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " F1UC ,FIFO1 Under Bit Clear" "No effect,Clear" bitfld.long 0x00 2. " F1OC ,FIFO1 Over Bit Clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " F2UC ,FIFO2 Under Bit Clear" "No effect,Clear" bitfld.long 0x00 0. " F2OC ,FIFO2 Over Bit Clear" "No effect,Clear" endif tree "Instruction Cache Indirect Access" if (data.long(ANC:iobase()+0xf08)&0x40000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2060++0x0B line.long 0x00 "ICSR,Instruction Cache Address Register" hexmask.long.word 0x00 2.--12. 0x4 " ICACHE_ADDR ,Address into instruction cache data array" line.long 0x04 "ICDR,Instruction Cache Data Register" line.long 0x08 "ICTR,Instruction Cache Tag Register" bitfld.long 0x08 20. " V ,Instruction Cache line valid bit" "Invalid,Valid" bitfld.long 0x08 19. " S ,Supervisor bit" "User,Supervisor" hexmask.long 0x08 0.--18. 1. " ADDR ,Address tag" endif tree.end tree.end tree "BLDC (Byte Data Link Controller IMMRBAR + 0x1400)" width 0xa if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte 0x1400++0x00 line.byte 0x00 "DLCBCR1,BDLC Control Register 1" bitfld.byte 0x00 7. " IMSG ,Ignore Message" "Disabled,Enabled" bitfld.byte 0x00 6. " CLKS ,Clock Selection" "1 MHz,1.048576 MHz" textline " " bitfld.byte 0x00 1. " IE ,Interrupt Enable" "Disabled,Enabled" rgroup.byte 0x1401++0x0 line.byte 0x0 "DLCBSVR,BDLC State Vector Register" bitfld.byte 0x0 2.--5. " I ,Interrupt State Vector" "No Interrupts Pending,Received EOF,Received IFR byte,Rx data register full,Tx data register empty,Loss of arbitration,CRC error,Symbol invalid or out of range,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.byte 0x1404++0x1 line.byte 0x0 "DLCBCR2,BDLC Control Register 2" bitfld.byte 0x0 7. " SMRST ,State Machine Reset" "Generated,Armed" bitfld.byte 0x0 6. " DLOOP ,Digital Loopback Mode" "Disabled,Enabled" textline " " bitfld.byte 0x0 5. " 4XE ,4X Mode Enable" "Disabled,Enabled" bitfld.byte 0x0 4. " NBFS ,Normalization Bit Format Select" "1 with CRC/0 without,0 with CRC/1 without" textline " " bitfld.byte 0x0 3. " TEOD ,Transmit End of Data" "No EOD,EOD" bitfld.byte 0x0 2. " TSIFR ,Transmit Single Byte IFR with no CRC" "Error,No error" textline " " bitfld.byte 0x0 1. " TMIFR1 ,Transmit Multiple Byte IFR with CRC" "Error,No error" bitfld.byte 0x0 0. " TMIFR0 ,Transmit Multiple Byte IFR with no CRC" "Error,No error" line.byte 0x1 "DLCBDR,BDLC Data Register" hexmask.byte 0x1 0.--7. 1. " D[7:0] ,Receive/Transmit Data" group.byte 0x1408++0x1 line.byte 0x0 "DLCBARD,BDLC Analog Round Trip Delay Register" bitfld.byte 0x0 6. " RXPOL ,Receive Pin Polarity" "Inverted,Normal" bitfld.byte 0x0 0.--4. " BO[4:0] ,BDLC Analog Roundtrip Delay Offset Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x1 "DLCBRSR,BDLC Rate Select Register" hexmask.byte 0x1 0.--7. 1. " R[7:0] ,Rate Select" group.byte 0x140c++0x0 line.byte 0x0 "DLCSCR,BDLC Control Register" bitfld.byte 0x0 4. " BDLCE ,BDLC Enable" "Disabled,Enabled" bitfld.byte 0x0 0. " BREAK ,BREAK signal" "No BREAK,BREAK" group.byte 0x140d++0x01 line.byte 0x00 "DLCBSTAT,BDLC Status Register" bitfld.byte 0x00 2. " TST_DIVTE_T4 ,The module output Tx pin output" "Normal,MUX IC" bitfld.byte 0x00 1. " TST_CRCV_T4 ,Status of the receive message CRC" "Correct,Incorrect" textline " " bitfld.byte 0x00 0. " IDLE ,This bit indicates when the BDLC module is idle" "No idle,Idle" endif width 0xb tree.end tree "CFM (Clock Frequency Measurement IMMRBAR + 0x2200)" width 0x5 group.long 0x2200++0x03 line.long 0x00 "PCR,PhaseConfig Register" bitfld.long 0x00 3.--5. " CoefSel ,The Gain Value for Measurement Result" "24,16,12,8,6,4,3,3" bitfld.long 0x00 0.--2. " ClkSrc_Sel ,Clock Source Selection " "CLK_IN1,CLK_IN2,CLK_IN3,CLK_IN4,Reserved,Reserved,Reserved,Reserved" rgroup.long 0x2208++0x03 line.long 0x00 "FMR,FreqMeas Register" tree.end tree "CSB Arbiter and Bus Monitor (IMMRBAR + 0xd00)" width 7. group.long 0xd00++0x17 line.long 0x00 "ACR,Arbiter Configuration Register" bitfld.long 0x00 26. " DTO_DIS ,Data Time Out Detection Disable" "Enabled,Disabled" bitfld.long 0x00 25. " ATO_DIS ,Address Time Out Detection Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " COREDIS ,Core disable" "Enabled,Disabled" bitfld.long 0x00 20.--21. " AACKWS ,Address Acknowledge Wait States" "1 cycle,2 cycles,3 cycles,4 cycles" textline " " bitfld.long 0x00 16.--18. " PIPE_DEP ,Pipeline Depth" "1,2,3,4,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 12.--14. " PCI_RPTCNT ,PCI repeat count" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x00 8.--10. " RPTCNT ,PCI/PCI DMA Repeat Count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 6. " WPARK ,WOP Parking" "CPU,Not parked" textline " " bitfld.long 0x00 4.--5. " APARK ,Address Parking" "To master,To last owner,Disabled,Reserved" bitfld.long 0x00 0.--3. " PARKM ,Parking Master" "PowerPC Core,PCI/PCI DMA,TPR2MG/SAP,?..." line.long 0x04 "ATR,Arbiter Timers Register" hexmask.long.word 0x04 16.--31. 1. " DTO ,Data Time-Out" hexmask.long.word 0x04 0.--15. 1. " ATO ,Address Time-Out" line.long 0x08 "ATER,Arbiter Transfer Error Register" bitfld.long 0x08 5. " ETEA ,External /TEA" "Not reported,Reported" bitfld.long 0x08 4. " RES ,Reserved Transfer Type" "Not reported,Reported" textline " " bitfld.long 0x08 3. " ECW ,External Control Word Transfer Type" "Not reported,Reported" bitfld.long 0x08 2. " AO ,Address Only Transfer Type" "Not reported,Reported" textline " " bitfld.long 0x08 1. " DTO ,Data Time Out" "Not reported,Reported" bitfld.long 0x08 0. " ATO ,Address Time Out" "Not reported,Reported" line.long 0x0c "AER,Arbiter Event Register" eventfld.long 0x0c 5. " ETEA ,External /TEA" "No Error,Error" eventfld.long 0x0c 4. " RES ,Reserved Transfer Type" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " ECW ,External Control Word Transfer Type" "Not occurred,Occurred" eventfld.long 0x0c 2. " AO ,Address Only Transfer Type" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " DTO ,Data Time Out" "Not expired,Expired" eventfld.long 0x0c 0. " ATO ,Address Time Out" "Not expired,Expired" line.long 0x10 "AIDR,Arbiter Interrupt Definition Register" bitfld.long 0x10 5. " ETEA ,External /TEA Interrupt" "Regular,MCP" bitfld.long 0x10 4. " RES ,Reserved Transfer Type Interrupt" "Regular,MCP" textline " " bitfld.long 0x10 3. " ECW ,External Control Word Transfer Type Interrupt" "Regular,MCP" bitfld.long 0x10 2. " AO ,Address Only Transfer Type Interrupt" "Regular,MCP" textline " " bitfld.long 0x10 1. " DTO ,Data Time Out Interrupt" "Regular,MCP" bitfld.long 0x10 0. " ATO ,Address Time Out Interrupt" "Regular,MCP" line.long 0x14 "AMR,Arbiter Mask Register" bitfld.long 0x14 5. " ETEA ,External /TEA Interrupt" "Disabled,Enabled" bitfld.long 0x14 4. " RES ,Reserved Transfer Type Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " ECW ,External Control Word Transfer Type Interrupt" "Disabled,Enabled" bitfld.long 0x14 2. " AO ,Address Only Transfer Type Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " DTO ,Data Time Out Interrupt" "Disabled,Enabled" bitfld.long 0x14 0. " ATO ,Address Time Out Interrupt" "Disabled,Enabled" if ((d.l(anc:(iobase()+0xd00+0x18))&0x800)==0x800) group.long 0xd18++0x07 line.long 0x00 "AEATR,Arbiter Event Attributes Register" bitfld.long 0x00 24.--26. " EVENT ,Event Type" "ATO,DTO,AO,ECW,RES,ETEA,Reserved,Reserved" bitfld.long 0x00 16.--20. " MSTR_ID ,Master Id" "PowerPC core data transaction,Reserved,PowerPC core instruction fetch,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,JTAG,TPR,Reserved,PCI,Reserved,PCI DMA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 11. " TBST ,Transfer Burst" "Up to 8 bytes,More than 8 bytes" bitfld.long 0x00 8.--10. " TSIZE ,Transfer Size" "8 Byte,1 Byte,2 Byte,3 Byte,4 Byte,5 Byte,6 Byte,7 Byte" textline " " bitfld.long 0x00 0.--4. " TTYPE ,Transfer Type" "Address-only,Address-only,Single beat/burst write,Reserved,Address-only,Reserved,Burst write,Reserved,Address-only,Address-only,Single beat/burst read,Single beat/burst read,Address-only,Address-only,Burst read,Reserved,Address-only,Reserved,Single beat write,Reserved,ECOWX,Reserved,Reserved,Reserved,Address-only,Reserved,Single beat/burst read,Reserved,ECIWX,Reserved,Burst read,Reserved" else group.long 0xd18++0x07 line.long 0x00 "AEATR,Arbiter Event Attributes Register" bitfld.long 0x00 24.--26. " EVENT ,Event Type" "ATO,DTO,AO,ECW,RES,ETEA,Reserved,Reserved" bitfld.long 0x00 16.--20. " MSTR_ID ,Master Id" "PowerPC core data transaction,Reserved,PowerPC core instruction fetch,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,JTAG,TPR,Reserved,PCI,Reserved,PCI DMA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 11. " TBST ,Transfer Burst" "Up to 8 bytes,More than 8 bytes" bitfld.long 0x00 8.--10. " TSIZE ,Transfer Size" "16 bytes,24 bytes,32 bytes,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 0.--4. " TTYPE ,Transfer Type" "Address-only,Address-only,Single beat/burst write,Reserved,Address-only,Reserved,Burst write,Reserved,Address-only,Address-only,Single beat/burst read,Single beat/burst read,Address-only,Address-only,Burst read,Reserved,Address-only,Reserved,Single beat write,Reserved,ECOWX,Reserved,Reserved,Reserved,Address-only,Reserved,Single beat/burst read,Reserved,ECIWX,Reserved,Burst read,Reserved" endif group.long 0xd1c++0x07 line.long 0x00 "AEADR,Arbiter Event Address Register" group.long 0xd20++0x03 line.long 0x00 "AERR,Arbiter Event Response Register" bitfld.long 0x00 5. " ETEA ,External /TEA" "Interrupt,Reset" bitfld.long 0x00 4. " RES ,Reserved Transfer Type" "Interrupt,Reset" textline " " bitfld.long 0x00 3. " ECW ,External Control Word Transfer Type" "Interrupt,Reset" bitfld.long 0x00 2. " AO ,Address Only Transfer Type" "Interrupt,Reset" textline " " bitfld.long 0x00 1. " DTO ,Data Time Out" "Interrupt,Reset" bitfld.long 0x00 0. " ATO ,Address Time Out" "Interrupt,Reset" width 0xb tree.end tree "DMA (Direct Memory Access IMMRBAR + 0x14000)" width 0xa group.long 0x14000++0x03 line.long 0x00 "DMACR,DMA Control Register" bitfld.long 0x00 31. " EDCG ,Enable Clock Dynamic Gating" "Disabled,Enabled" bitfld.long 0x00 14.--15. " GRP3PRI ,Channel Group 3 Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x00 12.--13. " GRP2PRI ,Channel Group 2 Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.long 0x00 10.--11. " GRP1PRI ,Channel Group 1 Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x00 8.--9. " GRP0PRI ,Channel Group 0 Priority" "Level 0,Level 1,Level 2,Level 3" bitfld.long 0x00 3. " ERGA ,Enable Round Robin Group Arbitration" "Fixed,Round" textline " " bitfld.long 0x00 2. " ERCA ,Enable Round Robin Channel Arbitration" "Fixed,Round" bitfld.long 0x00 1. " EDBG ,Enable Debug" "Ignored,Stalled" rgroup.long 0x14004++0x03 line.long 0x00 "DMAES,DMA Error Status" bitfld.long 0x00 31. " VLD ,Logical OR of All DMAERRH and DMAERRL Status Bit" "No DMAER,DMAER" bitfld.long 0x00 15. " GPE ,Group Priority Error" "No error,Error" bitfld.long 0x00 14. " CPE ,Channel Priority Error" "No error,Error" textline " " bitfld.long 0x00 8.--13. " ERRCHN[5:0] ,Error Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " SAE ,Source Address Error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source Offset Configuration" "No error,Error" textline " " bitfld.long 0x00 5. " DAE ,Destination Address Error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination Offset Error" "No error,Error" bitfld.long 0x00 3. " NCE ,Nbytes/Citer Configuration Error" "No error,Error" textline " " bitfld.long 0x00 2. " SGE ,Scatter/Gather Configuration Error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source Bus Error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination Bus Error" "No error,Error" width 0xa group.long 0x14008++0x0f line.long 0x00 "DMAERQH,DMA Enable Request High" bitfld.long 0x00 31. " ERQ63 ,Enable DMA Request 63" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ62 ,Enable DMA Request 62" "Disabled,Enabled" bitfld.long 0x00 29. " ERQ61 ,Enable DMA Request 61" "Disabled,Enabled" bitfld.long 0x00 28. " ERQ60 ,Enable DMA Request 60" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " ERQ59 ,Enable DMA Request 59" "Disabled,Enabled" bitfld.long 0x00 26. " ERQ58 ,Enable DMA Request 58" "Disabled,Enabled" bitfld.long 0x00 25. " ERQ57 ,Enable DMA Request 57" "Disabled,Enabled" bitfld.long 0x00 24. " ERQ56 ,Enable DMA Request 56" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " ERQ55 ,Enable DMA Request 55" "Disabled,Enabled" bitfld.long 0x00 22. " ERQ54 ,Enable DMA Request 54" "Disabled,Enabled" bitfld.long 0x00 21. " ERQ53 ,Enable DMA Request 53" "Disabled,Enabled" bitfld.long 0x00 20. " ERQ52 ,Enable DMA Request 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " ERQ51 ,Enable DMA Request 51" "Disabled,Enabled" bitfld.long 0x00 18. " ERQ50 ,Enable DMA Request 50" "Disabled,Enabled" bitfld.long 0x00 17. " ERQ49 ,Enable DMA Request 49" "Disabled,Enabled" bitfld.long 0x00 16. " ERQ48 ,Enable DMA Request 48" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " ERQ47 ,Enable DMA Request 47" "Disabled,Enabled" bitfld.long 0x00 14. " ERQ46 ,Enable DMA Request 46" "Disabled,Enabled" bitfld.long 0x00 13. " ERQ45 ,Enable DMA Request 45" "Disabled,Enabled" bitfld.long 0x00 12. " ERQ44 ,Enable DMA Request 44" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ERQ43 ,Enable DMA Request 43" "Disabled,Enabled" bitfld.long 0x00 10. " ERQ42 ,Enable DMA Request 42" "Disabled,Enabled" bitfld.long 0x00 9. " ERQ41 ,Enable DMA Request 41" "Disabled,Enabled" bitfld.long 0x00 8. " ERQ40 ,Enable DMA Request 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ERQ39 ,Enable DMA Request 39" "Disabled,Enabled" bitfld.long 0x00 6. " ERQ38 ,Enable DMA Request 38" "Disabled,Enabled" bitfld.long 0x00 5. " ERQ37 ,Enable DMA Request 37" "Disabled,Enabled" bitfld.long 0x00 4. " ERQ36 ,Enable DMA Request 36" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ERQ35 ,Enable DMA Request 35" "Disabled,Enabled" bitfld.long 0x00 2. " ERQ34 ,Enable DMA Request 34" "Disabled,Enabled" bitfld.long 0x00 1. " ERQ33 ,Enable DMA Request 33" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ32 ,Enable DMA Request 32" "Disabled,Enabled" line.long 0x04 "DMAERQL,DMA Enable Request Low" bitfld.long 0x04 31. " ERQ31 ,Enable DMA Request 31" "Disabled,Enabled" bitfld.long 0x04 30. " ERQ30 ,Enable DMA Request 30" "Disabled,Enabled" bitfld.long 0x04 29. " ERQ29 ,Enable DMA Request 29" "Disabled,Enabled" bitfld.long 0x04 28. " ERQ28 ,Enable DMA Request 28" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " ERQ27 ,Enable DMA Request 27" "Disabled,Enabled" bitfld.long 0x04 26. " ERQ26 ,Enable DMA Request 26" "Disabled,Enabled" bitfld.long 0x04 25. " ERQ25 ,Enable DMA Request 25" "Disabled,Enabled" bitfld.long 0x04 24. " ERQ24 ,Enable DMA Request 24" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " ERQ23 ,Enable DMA Request 23" "Disabled,Enabled" bitfld.long 0x04 22. " ERQ22 ,Enable DMA Request 22" "Disabled,Enabled" bitfld.long 0x04 21. " ERQ21 ,Enable DMA Request 21" "Disabled,Enabled" bitfld.long 0x04 20. " ERQ20 ,Enable DMA Request 20" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " ERQ19 ,Enable DMA Request 19" "Disabled,Enabled" bitfld.long 0x04 18. " ERQ18 ,Enable DMA Request 18" "Disabled,Enabled" bitfld.long 0x04 17. " ERQ17 ,Enable DMA Request 17" "Disabled,Enabled" bitfld.long 0x04 16. " ERQ16 ,Enable DMA Request 16" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " ERQ15 ,Enable DMA Request 15" "Disabled,Enabled" bitfld.long 0x04 14. " ERQ14 ,Enable DMA Request 14" "Disabled,Enabled" bitfld.long 0x04 13. " ERQ13 ,Enable DMA Request 13" "Disabled,Enabled" bitfld.long 0x04 12. " ERQ12 ,Enable DMA Request 12" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ERQ11 ,Enable DMA Request 11" "Disabled,Enabled" bitfld.long 0x04 10. " ERQ10 ,Enable DMA Request 10" "Disabled,Enabled" bitfld.long 0x04 9. " ERQ9 ,Enable DMA Request 9" "Disabled,Enabled" bitfld.long 0x04 8. " ERQ8 ,Enable DMA Request 8" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " ERQ7 ,Enable DMA Request 7" "Disabled,Enabled" bitfld.long 0x04 6. " ERQ6 ,Enable DMA Request 6" "Disabled,Enabled" bitfld.long 0x04 5. " ERQ5 ,Enable DMA Request 5" "Disabled,Enabled" bitfld.long 0x04 4. " ERQ4 ,Enable DMA Request 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " ERQ3 ,Enable DMA Request 3" "Disabled,Enabled" bitfld.long 0x04 2. " ERQ2 ,Enable DMA Request 2" "Disabled,Enabled" bitfld.long 0x04 1. " ERQ1 ,Enable DMA Request 1" "Disabled,Enabled" bitfld.long 0x04 0. " ERQ0 ,Enable DMA Request 0" "Disabled,Enabled" line.long 0x08 "DMAEEIH,DMA Enable Error Interrupt High" bitfld.long 0x08 31. " EEI63 ,Enable Error Interrupt 63" "Disabled,Enabled" bitfld.long 0x08 30. " EEI62 ,Enable Error Interrupt 62" "Disabled,Enabled" bitfld.long 0x08 29. " EEI61 ,Enable Error Interrupt 61" "Disabled,Enabled" bitfld.long 0x08 28. " EEI60 ,Enable Error Interrupt 60" "Disabled,Enabled" textline " " bitfld.long 0x08 27. " EEI59 ,Enable Error Interrupt 59" "Disabled,Enabled" bitfld.long 0x08 26. " EEI58 ,Enable Error Interrupt 58" "Disabled,Enabled" bitfld.long 0x08 25. " EEI57 ,Enable Error Interrupt 57" "Disabled,Enabled" bitfld.long 0x08 24. " EEI56 ,Enable Error Interrupt 56" "Disabled,Enabled" textline " " bitfld.long 0x08 23. " EEI55 ,Enable Error Interrupt 55" "Disabled,Enabled" bitfld.long 0x08 22. " EEI54 ,Enable Error Interrupt 54" "Disabled,Enabled" bitfld.long 0x08 21. " EEI53 ,Enable Error Interrupt 53" "Disabled,Enabled" bitfld.long 0x08 20. " EEI52 ,Enable Error Interrupt 52" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " EEI51 ,Enable Error Interrupt 51" "Disabled,Enabled" bitfld.long 0x08 18. " EEI50 ,Enable Error Interrupt 50" "Disabled,Enabled" bitfld.long 0x08 17. " EEI49 ,Enable Error Interrupt 49" "Disabled,Enabled" bitfld.long 0x08 16. " EEI48 ,Enable Error Interrupt 48" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " EEI47 ,Enable Error Interrupt 47" "Disabled,Enabled" bitfld.long 0x08 14. " EEI46 ,Enable Error Interrupt 46" "Disabled,Enabled" bitfld.long 0x08 13. " EEI45 ,Enable Error Interrupt 45" "Disabled,Enabled" bitfld.long 0x08 12. " EEI44 ,Enable Error Interrupt 44" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " EEI43 ,Enable Error Interrupt 43" "Disabled,Enabled" bitfld.long 0x08 10. " EEI42 ,Enable Error Interrupt 42" "Disabled,Enabled" bitfld.long 0x08 9. " EEI41 ,Enable Error Interrupt 41" "Disabled,Enabled" bitfld.long 0x08 8. " EEI40 ,Enable Error Interrupt 40" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " EEI39 ,Enable Error Interrupt 39" "Disabled,Enabled" bitfld.long 0x08 6. " EEI38 ,Enable Error Interrupt 38" "Disabled,Enabled" bitfld.long 0x08 5. " EEI37 ,Enable Error Interrupt 37" "Disabled,Enabled" bitfld.long 0x08 4. " EEI36 ,Enable Error Interrupt 36" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EEI35 ,Enable Error Interrupt 35" "Disabled,Enabled" bitfld.long 0x08 2. " EEI34 ,Enable Error Interrupt 34" "Disabled,Enabled" bitfld.long 0x08 1. " EEI33 ,Enable Error Interrupt 33" "Disabled,Enabled" bitfld.long 0x08 0. " EEI32 ,Enable Error Interrupt 32" "Disabled,Enabled" line.long 0x0c "DMAERQL,DMA Enable Request Low" bitfld.long 0x0c 31. " EEI31 ,Enable Error Interrupt 31" "Disabled,Enabled" bitfld.long 0x0c 30. " EEI30 ,Enable Error Interrupt 30" "Disabled,Enabled" bitfld.long 0x0c 29. " EEI29 ,Enable Error Interrupt 29" "Disabled,Enabled" bitfld.long 0x0c 28. " EEI28 ,Enable Error Interrupt 28" "Disabled,Enabled" textline " " bitfld.long 0x0c 27. " EEI27 ,Enable Error Interrupt 27" "Disabled,Enabled" bitfld.long 0x0c 26. " EEI26 ,Enable Error Interrupt 26" "Disabled,Enabled" bitfld.long 0x0c 25. " EEI25 ,Enable Error Interrupt 25" "Disabled,Enabled" bitfld.long 0x0c 24. " EEI24 ,Enable Error Interrupt 24" "Disabled,Enabled" textline " " bitfld.long 0x0c 23. " EEI23 ,Enable Error Interrupt 23" "Disabled,Enabled" bitfld.long 0x0c 22. " EEI22 ,Enable Error Interrupt 22" "Disabled,Enabled" bitfld.long 0x0c 21. " EEI21 ,Enable Error Interrupt 21" "Disabled,Enabled" bitfld.long 0x0c 20. " EEI20 ,Enable Error Interrupt 20" "Disabled,Enabled" textline " " bitfld.long 0x0c 19. " EEI19 ,Enable Error Interrupt 19" "Disabled,Enabled" bitfld.long 0x0c 18. " EEI18 ,Enable Error Interrupt 18" "Disabled,Enabled" bitfld.long 0x0c 17. " EEI17 ,Enable Error Interrupt 17" "Disabled,Enabled" bitfld.long 0x0c 16. " EEI16 ,Enable Error Interrupt 16" "Disabled,Enabled" textline " " bitfld.long 0x0c 15. " EEI15 ,Enable Error Interrupt 15" "Disabled,Enabled" bitfld.long 0x0c 14. " EEI14 ,Enable Error Interrupt 14" "Disabled,Enabled" bitfld.long 0x0c 13. " EEI13 ,Enable Error Interrupt 13" "Disabled,Enabled" bitfld.long 0x0c 12. " EEI12 ,Enable Error Interrupt 12" "Disabled,Enabled" textline " " bitfld.long 0x0c 11. " EEI11 ,Enable Error Interrupt 11" "Disabled,Enabled" bitfld.long 0x0c 10. " EEI10 ,Enable Error Interrupt 10" "Disabled,Enabled" bitfld.long 0x0c 9. " EEI9 ,Enable Error Interrupt 9" "Disabled,Enabled" bitfld.long 0x0c 8. " EEI8 ,Enable Error Interrupt 8" "Disabled,Enabled" textline " " bitfld.long 0x0c 7. " EEI7 ,Enable Error Interrupt 7" "Disabled,Enabled" bitfld.long 0x0c 6. " EEI6 ,Enable Error Interrupt 6" "Disabled,Enabled" bitfld.long 0x0c 5. " EEI5 ,Enable Error Interrupt 5" "Disabled,Enabled" bitfld.long 0x0c 4. " EEI4 ,Enable Error Interrupt 4" "Disabled,Enabled" textline " " bitfld.long 0x0c 3. " EEI3 ,Enable Error Interrupt 3" "Disabled,Enabled" bitfld.long 0x0c 2. " EEI2 ,Enable Error Interrupt 2" "Disabled,Enabled" bitfld.long 0x0c 1. " EEI1 ,Enable Error Interrupt 1" "Disabled,Enabled" bitfld.long 0x0c 0. " EEI0 ,Enable Error Interrupt 0" "Disabled,Enabled" width 0xa wgroup.byte 0x14018++0x07 line.byte 0x00 "DMASERQ,DMA Set Enable Request Register" hexmask.byte 0x00 0.--6. 1. " SERQ[6:0] ,Set Enable Request" line.byte 0x01 "DMACERQ,DMA Clear Enable Request Register" hexmask.byte 0x01 0.--6. 1. " CERQ[6:0] ,Clear Enable Request" line.byte 0x02 "DMASEEI,DMA Set Enable Error Interrupt Register" hexmask.byte 0x02 0.--6. 1. " SEEI[6:0] ,Set Enable Error Interrupt" line.byte 0x03 "DMACEEI,DMA Clear Enable Error Interrupt Register" hexmask.byte 0x03 0.--6. 1. " CEEI[6:0] ,Clear Enable Error Interrupt" line.byte 0x04 "DMACINT,DMA Clear Interrupt Request Register" hexmask.byte 0x04 0.--6. 1. " CINT[6:0] ,Clear Interrupt Request" line.byte 0x05 "DMACERR,DMA Clear Error Register" hexmask.byte 0x05 0.--6. 1. " CERR[6:0] ,Clear Error Indicator" line.byte 0x06 "DMASSRT,DMA Set START Bit Register" hexmask.byte 0x06 0.--6. 1. " SSRT[6:0] ,Set START Bit (Channel Service Request)" line.byte 0x07 "DMACDNE,DMA Clear DONE Status Register" hexmask.byte 0x07 0.--6. 1. " CDNE[6:0] ,Clear DONE Status Bit" width 0xa group.long 0x14020++0x0f line.long 0x00 "DMAINTH,DMA Interrupt Request High Register" bitfld.long 0x00 31. " INT63 ,DMA Interrupt Request 63" "Cleared,Activated" bitfld.long 0x00 30. " INT62 ,DMA Interrupt Request 62" "Cleared,Activated" bitfld.long 0x00 29. " INT61 ,DMA Interrupt Request 61" "Cleared,Activated" bitfld.long 0x00 28. " INT60 ,DMA Interrupt Request 60" "Cleared,Activated" textline " " bitfld.long 0x00 27. " INT59 ,DMA Interrupt Request 59" "Cleared,Activated" bitfld.long 0x00 26. " INT58 ,DMA Interrupt Request 58" "Cleared,Activated" bitfld.long 0x00 25. " INT57 ,DMA Interrupt Request 57" "Cleared,Activated" bitfld.long 0x00 24. " INT56 ,DMA Interrupt Request 56" "Cleared,Activated" textline " " bitfld.long 0x00 23. " INT55 ,DMA Interrupt Request 55" "Cleared,Activated" bitfld.long 0x00 22. " INT54 ,DMA Interrupt Request 54" "Cleared,Activated" bitfld.long 0x00 21. " INT53 ,DMA Interrupt Request 53" "Cleared,Activated" bitfld.long 0x00 20. " INT52 ,DMA Interrupt Request 52" "Cleared,Activated" textline " " bitfld.long 0x00 19. " INT51 ,DMA Interrupt Request 51" "Cleared,Activated" bitfld.long 0x00 18. " INT50 ,DMA Interrupt Request 50" "Cleared,Activated" bitfld.long 0x00 17. " INT49 ,DMA Interrupt Request 49" "Cleared,Activated" bitfld.long 0x00 16. " INT48 ,DMA Interrupt Request 48" "Cleared,Activated" textline " " bitfld.long 0x00 15. " INT47 ,DMA Interrupt Request 47" "Cleared,Activated" bitfld.long 0x00 14. " INT46 ,DMA Interrupt Request 46" "Cleared,Activated" bitfld.long 0x00 13. " INT45 ,DMA Interrupt Request 45" "Cleared,Activated" bitfld.long 0x00 12. " INT44 ,DMA Interrupt Request 44" "Cleared,Activated" textline " " bitfld.long 0x00 11. " INT43 ,DMA Interrupt Request 43" "Cleared,Activated" bitfld.long 0x00 10. " INT42 ,DMA Interrupt Request 42" "Cleared,Activated" bitfld.long 0x00 9. " INT41 ,DMA Interrupt Request 41" "Cleared,Activated" bitfld.long 0x00 8. " INT40 ,DMA Interrupt Request 40" "Cleared,Activated" textline " " bitfld.long 0x00 7. " INT39 ,DMA Interrupt Request 39" "Cleared,Activated" bitfld.long 0x00 6. " INT38 ,DMA Interrupt Request 38" "Cleared,Activated" bitfld.long 0x00 5. " INT37 ,DMA Interrupt Request 37" "Cleared,Activated" bitfld.long 0x00 4. " INT36 ,DMA Interrupt Request 36" "Cleared,Activated" textline " " bitfld.long 0x00 3. " INT35 ,DMA Interrupt Request 35" "Cleared,Activated" bitfld.long 0x00 2. " INT34 ,DMA Interrupt Request 34" "Cleared,Activated" bitfld.long 0x00 1. " INT33 ,DMA Interrupt Request 33" "Cleared,Activated" bitfld.long 0x00 0. " INT32 ,DMA Interrupt Request 32" "Cleared,Activated" line.long 0x04 "DMAINTL,DMA Interrupt Request Low Register" bitfld.long 0x04 31. " INT31 ,DMA Interrupt Request 31" "Cleared,Activated" bitfld.long 0x04 30. " INT30 ,DMA Interrupt Request 30" "Cleared,Activated" bitfld.long 0x04 29. " INT29 ,DMA Interrupt Request 29" "Cleared,Activated" bitfld.long 0x04 28. " INT28 ,DMA Interrupt Request 28" "Cleared,Activated" textline " " bitfld.long 0x04 27. " INT27 ,DMA Interrupt Request 27" "Cleared,Activated" bitfld.long 0x04 26. " INT26 ,DMA Interrupt Request 26" "Cleared,Activated" bitfld.long 0x04 25. " INT25 ,DMA Interrupt Request 25" "Cleared,Activated" bitfld.long 0x04 24. " INT24 ,DMA Interrupt Request 24" "Cleared,Activated" textline " " bitfld.long 0x04 23. " INT23 ,DMA Interrupt Request 23" "Cleared,Activated" bitfld.long 0x04 22. " INT22 ,DMA Interrupt Request 22" "Cleared,Activated" bitfld.long 0x04 21. " INT21 ,DMA Interrupt Request 21" "Cleared,Activated" bitfld.long 0x04 20. " INT20 ,DMA Interrupt Request 20" "Cleared,Activated" textline " " bitfld.long 0x04 19. " INT19 ,DMA Interrupt Request 19" "Cleared,Activated" bitfld.long 0x04 18. " INT18 ,DMA Interrupt Request 18" "Cleared,Activated" bitfld.long 0x04 17. " INT17 ,DMA Interrupt Request 17" "Cleared,Activated" bitfld.long 0x04 16. " INT16 ,DMA Interrupt Request 16" "Cleared,Activated" textline " " bitfld.long 0x04 15. " INT15 ,DMA Interrupt Request 15" "Cleared,Activated" bitfld.long 0x04 14. " INT14 ,DMA Interrupt Request 14" "Cleared,Activated" bitfld.long 0x04 13. " INT13 ,DMA Interrupt Request 13" "Cleared,Activated" bitfld.long 0x04 12. " INT12 ,DMA Interrupt Request 12" "Cleared,Activated" textline " " bitfld.long 0x04 11. " INT11 ,DMA Interrupt Request 11" "Cleared,Activated" bitfld.long 0x04 10. " INT10 ,DMA Interrupt Request 10" "Cleared,Activated" bitfld.long 0x04 9. " INT9 ,DMA Interrupt Request 9" "Cleared,Activated" bitfld.long 0x04 8. " INT8 ,DMA Interrupt Request 8" "Cleared,Activated" textline " " bitfld.long 0x04 7. " INT7 ,DMA Interrupt Request 7" "Cleared,Activated" bitfld.long 0x04 6. " INT6 ,DMA Interrupt Request 6" "Cleared,Activated" bitfld.long 0x04 5. " INT5 ,DMA Interrupt Request 5" "Cleared,Activated" bitfld.long 0x04 4. " INT4 ,DMA Interrupt Request 4" "Cleared,Activated" textline " " bitfld.long 0x04 3. " INT3 ,DMA Interrupt Request 3" "Cleared,Activated" bitfld.long 0x04 2. " INT2 ,DMA Interrupt Request 2" "Cleared,Activated" bitfld.long 0x04 1. " INT1 ,DMA Interrupt Request 1" "Cleared,Activated" bitfld.long 0x04 0. " INT0 ,DMA Interrupt Request 0" "Cleared,Activated" width 0xa line.long 0x08 "DMAERRH,DMA Error High Register" eventfld.long 0x08 31. " ERR63 ,DMA Error 63" "Not occurred,Occurred" eventfld.long 0x08 30. " ERR62 ,DMA Error 62" "Not occurred,Occurred" eventfld.long 0x08 29. " ERR61 ,DMA Error 61" "Not occurred,Occurred" textline " " eventfld.long 0x08 28. " ERR60 ,DMA Error 60" "Not occurred,Occurred" eventfld.long 0x08 27. " ERR59 ,DMA Error 59" "Not occurred,Occurred" eventfld.long 0x08 26. " ERR58 ,DMA Error 58" "Not occurred,Occurred" textline " " eventfld.long 0x08 25. " ERR57 ,DMA Error 57" "Not occurred,Occurred" eventfld.long 0x08 24. " ERR56 ,DMA Error 56" "Not occurred,Occurred" eventfld.long 0x08 23. " ERR55 ,DMA Error 55" "Not occurred,Occurred" textline " " eventfld.long 0x08 22. " ERR54 ,DMA Error 54" "Not occurred,Occurred" eventfld.long 0x08 21. " ERR53 ,DMA Error 53" "Not occurred,Occurred" eventfld.long 0x08 20. " ERR52 ,DMA Error 52" "Not occurred,Occurred" textline " " eventfld.long 0x08 19. " ERR51 ,DMA Error 51" "Not occurred,Occurred" eventfld.long 0x08 18. " ERR50 ,DMA Error 50" "Not occurred,Occurred" eventfld.long 0x08 17. " ERR49 ,DMA Error 49" "Not occurred,Occurred" textline " " eventfld.long 0x08 16. " ERR48 ,DMA Error 48" "Not occurred,Occurred" eventfld.long 0x08 15. " ERR47 ,DMA Error 47" "Not occurred,Occurred" eventfld.long 0x08 14. " ERR46 ,DMA Error 46" "Not occurred,Occurred" textline " " eventfld.long 0x08 13. " ERR45 ,DMA Error 45" "Not occurred,Occurred" eventfld.long 0x08 12. " ERR44 ,DMA Error 44" "Not occurred,Occurred" eventfld.long 0x08 11. " ERR43 ,DMA Error 43" "Not occurred,Occurred" textline " " eventfld.long 0x08 10. " ERR42 ,DMA Error 42" "Not occurred,Occurred" eventfld.long 0x08 9. " ERR41 ,DMA Error 41" "Not occurred,Occurred" eventfld.long 0x08 8. " ERR40 ,DMA Error 40" "Not occurred,Occurred" textline " " eventfld.long 0x08 7. " ERR39 ,DMA Error 39" "Not occurred,Occurred" eventfld.long 0x08 6. " ERR38 ,DMA Error 38" "Not occurred,Occurred" eventfld.long 0x08 5. " ERR37 ,DMA Error 37" "Not occurred,Occurred" textline " " eventfld.long 0x08 4. " ERR36 ,DMA Error 36" "Not occurred,Occurred" eventfld.long 0x08 3. " ERR35 ,DMA Error 35" "Not occurred,Occurred" eventfld.long 0x08 2. " ERR34 ,DMA Error 34" "Not occurred,Occurred" textline " " eventfld.long 0x08 1. " ERR33 ,DMA Error 33" "Not occurred,Occurred" eventfld.long 0x08 0. " ERR32 ,DMA Error 32" "Not occurred,Occurred" line.long 0x0c "DMAERRL,DMA Error Low Register" eventfld.long 0x0c 31. " ERR31 ,DMA Error 31" "Not occurred,Occurred" eventfld.long 0x0c 30. " ERR30 ,DMA Error 30" "Not occurred,Occurred" eventfld.long 0x0c 29. " ERR29 ,DMA Error 29" "Not occurred,Occurred" textline " " eventfld.long 0x0c 28. " ERR28 ,DMA Error 28" "Not occurred,Occurred" eventfld.long 0x0c 27. " ERR27 ,DMA Error 27" "Not occurred,Occurred" eventfld.long 0x0c 26. " ERR26 ,DMA Error 26" "Not occurred,Occurred" textline " " eventfld.long 0x0c 25. " ERR25 ,DMA Error 25" "Not occurred,Occurred" eventfld.long 0x0c 24. " ERR24 ,DMA Error 24" "Not occurred,Occurred" eventfld.long 0x0c 23. " ERR23 ,DMA Error 23" "Not occurred,Occurred" textline " " eventfld.long 0x0c 22. " ERR22 ,DMA Error 22" "Not occurred,Occurred" eventfld.long 0x0c 21. " ERR21 ,DMA Error 21" "Not occurred,Occurred" eventfld.long 0x0c 20. " ERR20 ,DMA Error 20" "Not occurred,Occurred" textline " " eventfld.long 0x0c 19. " ERR19 ,DMA Error 19" "Not occurred,Occurred" eventfld.long 0x0c 18. " ERR18 ,DMA Error 18" "Not occurred,Occurred" eventfld.long 0x0c 17. " ERR17 ,DMA Error 17" "Not occurred,Occurred" textline " " eventfld.long 0x0c 16. " ERR16 ,DMA Error 16" "Not occurred,Occurred" eventfld.long 0x0c 15. " ERR15 ,DMA Error 15" "Not occurred,Occurred" eventfld.long 0x0c 14. " ERR14 ,DMA Error 14" "Not occurred,Occurred" textline " " eventfld.long 0x0c 13. " ERR13 ,DMA Error 13" "Not occurred,Occurred" eventfld.long 0x0c 12. " ERR12 ,DMA Error 12" "Not occurred,Occurred" eventfld.long 0x0c 11. " ERR11 ,DMA Error 11" "Not occurred,Occurred" textline " " eventfld.long 0x0c 10. " ERR10 ,DMA Error 10" "Not occurred,Occurred" eventfld.long 0x0c 9. " ERR9 ,DMA Error 9" "Not occurred,Occurred" eventfld.long 0x0c 8. " ERR8 ,DMA Error 8" "Not occurred,Occurred" textline " " eventfld.long 0x0c 7. " ERR7 ,DMA Error 7" "Not occurred,Occurred" eventfld.long 0x0c 6. " ERR6 ,DMA Error 6" "Not occurred,Occurred" eventfld.long 0x0c 5. " ERR5 ,DMA Error 5" "Not occurred,Occurred" textline " " eventfld.long 0x0c 4. " ERR4 ,DMA Error 4" "Not occurred,Occurred" eventfld.long 0x0c 3. " ERR3 ,DMA Error 3" "Not occurred,Occurred" eventfld.long 0x0c 2. " ERR2 ,DMA Error 2" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " ERR1 ,DMA Error 1" "Not occurred,Occurred" eventfld.long 0x0c 0. " ERR0 ,DMA Error 0" "Not occurred,Occurred" rgroup.long 0x14030++0x07 line.long 0x00 "DMAHRSH,DMA Hardware Request Status Register High" bitfld.long 0x00 31. " HSA63 ,DMA Hardware Request Status 63" "Not present,Present" bitfld.long 0x00 30. " HSA62 ,DMA Hardware Request Status 62" "Not present,Present" bitfld.long 0x00 29. " HSA61 ,DMA Hardware Request Status 61" "Not present,Present" textline " " bitfld.long 0x00 28. " HSA60 ,DMA Hardware Request Status 60" "Not present,Present" bitfld.long 0x00 27. " HSA59 ,DMA Hardware Request Status 59" "Not present,Present" bitfld.long 0x00 26. " HSA58 ,DMA Hardware Request Status 58" "Not present,Present" textline " " bitfld.long 0x00 25. " HSA57 ,DMA Hardware Request Status 57" "Not present,Present" bitfld.long 0x00 24. " HSA56 ,DMA Hardware Request Status 56" "Not present,Present" bitfld.long 0x00 23. " HSA55 ,DMA Hardware Request Status 55" "Not present,Present" textline " " bitfld.long 0x00 22. " HSA54 ,DMA Hardware Request Status 54" "Not present,Present" bitfld.long 0x00 21. " HSA53 ,DMA Hardware Request Status 53" "Not present,Present" bitfld.long 0x00 20. " HSA52 ,DMA Hardware Request Status 52" "Not present,Present" textline " " bitfld.long 0x00 19. " HSA51 ,DMA Hardware Request Status 51" "Not present,Present" bitfld.long 0x00 18. " HSA50 ,DMA Hardware Request Status 50" "Not present,Present" bitfld.long 0x00 17. " HSA49 ,DMA Hardware Request Status 49" "Not present,Present" textline " " bitfld.long 0x00 16. " HSA48 ,DMA Hardware Request Status 48" "Not present,Present" bitfld.long 0x00 15. " HSA47 ,DMA Hardware Request Status 47" "Not present,Present" bitfld.long 0x00 14. " HSA46 ,DMA Hardware Request Status 46" "Not present,Present" textline " " bitfld.long 0x00 13. " HSA45 ,DMA Hardware Request Status 45" "Not present,Present" bitfld.long 0x00 12. " HSA44 ,DMA Hardware Request Status 44" "Not present,Present" bitfld.long 0x00 11. " HSA43 ,DMA Hardware Request Status 43" "Not present,Present" textline " " bitfld.long 0x00 10. " HSA42 ,DMA Hardware Request Status 42" "Not present,Present" bitfld.long 0x00 9. " HSA41 ,DMA Hardware Request Status 41" "Not present,Present" bitfld.long 0x00 8. " HSA40 ,DMA Hardware Request Status 40" "Not present,Present" textline " " bitfld.long 0x00 7. " HSA39 ,DMA Hardware Request Status 39" "Not present,Present" bitfld.long 0x00 6. " HSA38 ,DMA Hardware Request Status 38" "Not present,Present" bitfld.long 0x00 5. " HSA37 ,DMA Hardware Request Status 37" "Not present,Present" textline " " bitfld.long 0x00 4. " HSA36 ,DMA Hardware Request Status 36" "Not present,Present" bitfld.long 0x00 3. " HSA35 ,DMA Hardware Request Status 35" "Not present,Present" bitfld.long 0x00 2. " HSA34 ,DMA Hardware Request Status 34" "Not present,Present" textline " " bitfld.long 0x00 1. " HSA33 ,DMA Hardware Request Status 33" "Not present,Present" bitfld.long 0x00 0. " HSA32 ,DMA Hardware Request Status 32" "Not present,Present" line.long 0x04 "DMAHRSL,DMA Hardware Request Status Register Low" bitfld.long 0x04 31. " HSA31 ,DMA Hardware Request Status 31" "Not present,Present" bitfld.long 0x04 30. " HSA30 ,DMA Hardware Request Status 30" "Not present,Present" bitfld.long 0x04 29. " HSA29 ,DMA Hardware Request Status 29" "Not present,Present" textline " " bitfld.long 0x04 28. " HSA28 ,DMA Hardware Request Status 28" "Not present,Present" bitfld.long 0x04 27. " HSA27 ,DMA Hardware Request Status 27" "Not present,Present" bitfld.long 0x04 26. " HSA26 ,DMA Hardware Request Status 26" "Not present,Present" textline " " bitfld.long 0x04 25. " HSA25 ,DMA Hardware Request Status 25" "Not present,Present" bitfld.long 0x04 24. " HSA24 ,DMA Hardware Request Status 24" "Not present,Present" bitfld.long 0x04 23. " HSA23 ,DMA Hardware Request Status 23" "Not present,Present" textline " " bitfld.long 0x04 22. " HSA22 ,DMA Hardware Request Status 22" "Not present,Present" bitfld.long 0x04 21. " HSA21 ,DMA Hardware Request Status 21" "Not present,Present" bitfld.long 0x04 20. " HSA20 ,DMA Hardware Request Status 20" "Not present,Present" textline " " bitfld.long 0x04 19. " HSA19 ,DMA Hardware Request Status 19" "Not present,Present" bitfld.long 0x04 18. " HSA18 ,DMA Hardware Request Status 18" "Not present,Present" bitfld.long 0x04 17. " HSA17 ,DMA Hardware Request Status 17" "Not present,Present" textline " " bitfld.long 0x04 16. " HSA16 ,DMA Hardware Request Status 16" "Not present,Present" bitfld.long 0x04 15. " HSA15 ,DMA Hardware Request Status 15" "Not present,Present" bitfld.long 0x04 14. " HSA14 ,DMA Hardware Request Status 14" "Not present,Present" textline " " bitfld.long 0x04 13. " HSA13 ,DMA Hardware Request Status 13" "Not present,Present" bitfld.long 0x04 12. " HSA12 ,DMA Hardware Request Status 12" "Not present,Present" bitfld.long 0x04 11. " HSA11 ,DMA Hardware Request Status 11" "Not present,Present" textline " " bitfld.long 0x04 10. " HSA10 ,DMA Hardware Request Status 10" "Not present,Present" bitfld.long 0x04 9. " HSA9 ,DMA Hardware Request Status 9" "Not present,Present" bitfld.long 0x04 8. " HSA8 ,DMA Hardware Request Status 8" "Not present,Present" textline " " bitfld.long 0x04 7. " HSA7 ,DMA Hardware Request Status 7" "Not present,Present" bitfld.long 0x04 6. " HSA6 ,DMA Hardware Request Status 6" "Not present,Present" bitfld.long 0x04 5. " HSA5 ,DMA Hardware Request Status 5" "Not present,Present" textline " " bitfld.long 0x04 4. " HSA4 ,DMA Hardware Request Status 4" "Not present,Present" bitfld.long 0x04 3. " HSA3 ,DMA Hardware Request Status 3" "Not present,Present" bitfld.long 0x04 2. " HSA2 ,DMA Hardware Request Status 2" "Not present,Present" textline " " bitfld.long 0x04 1. " HSA1 ,DMA Hardware Request Status 1" "Not present,Present" bitfld.long 0x04 0. " HSA0 ,DMA Hardware Request Status 0" "Not present,Present" width 0xa group.long 0x14038++0x07 line.long 0x00 "DMAIHSA,DMA Interrupt Select AXE High" bitfld.long 0x00 31. " ISA63 ,DMA Interrupt 63 Selects AXE" "IPIC,AXE" bitfld.long 0x00 30. " ISA62 ,DMA Interrupt 62 Selects AXE" "IPIC,AXE" bitfld.long 0x00 29. " ISA61 ,DMA Interrupt 61 Selects AXE" "IPIC,AXE" bitfld.long 0x00 28. " ISA60 ,DMA Interrupt 60 Selects AXE" "IPIC,AXE" bitfld.long 0x00 27. " ISA59 ,DMA Interrupt 59 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 26. " ISA58 ,DMA Interrupt 58 Selects AXE" "IPIC,AXE" bitfld.long 0x00 25. " ISA57 ,DMA Interrupt 57 Selects AXE" "IPIC,AXE" bitfld.long 0x00 24. " ISA56 ,DMA Interrupt 56 Selects AXE" "IPIC,AXE" bitfld.long 0x00 23. " ISA55 ,DMA Interrupt 55 Selects AXE" "IPIC,AXE" bitfld.long 0x00 22. " ISA54 ,DMA Interrupt 54 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 21. " ISA53 ,DMA Interrupt 53 Selects AXE" "IPIC,AXE" bitfld.long 0x00 20. " ISA52 ,DMA Interrupt 52 Selects AXE" "IPIC,AXE" bitfld.long 0x00 19. " ISA51 ,DMA Interrupt 51 Selects AXE" "IPIC,AXE" bitfld.long 0x00 18. " ISA50 ,DMA Interrupt 50 Selects AXE" "IPIC,AXE" bitfld.long 0x00 17. " ISA49 ,DMA Interrupt 49 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 16. " ISA48 ,DMA Interrupt 48 Selects AXE" "IPIC,AXE" bitfld.long 0x00 15. " ISA47 ,DMA Interrupt 47 Selects AXE" "IPIC,AXE" bitfld.long 0x00 14. " ISA46 ,DMA Interrupt 46 Selects AXE" "IPIC,AXE" bitfld.long 0x00 13. " ISA45 ,DMA Interrupt 45 Selects AXE" "IPIC,AXE" bitfld.long 0x00 12. " ISA44 ,DMA Interrupt 44 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 11. " ISA43 ,DMA Interrupt 43 Selects AXE" "IPIC,AXE" bitfld.long 0x00 10. " ISA42 ,DMA Interrupt 42 Selects AXE" "IPIC,AXE" bitfld.long 0x00 9. " ISA41 ,DMA Interrupt 41 Selects AXE" "IPIC,AXE" bitfld.long 0x00 8. " ISA40 ,DMA Interrupt 40 Selects AXE" "IPIC,AXE" bitfld.long 0x00 7. " ISA39 ,DMA Interrupt 39 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 6. " ISA38 ,DMA Interrupt 38 Selects AXE" "IPIC,AXE" bitfld.long 0x00 5. " ISA37 ,DMA Interrupt 37 Selects AXE" "IPIC,AXE" bitfld.long 0x00 4. " ISA36 ,DMA Interrupt 36 Selects AXE" "IPIC,AXE" bitfld.long 0x00 3. " ISA35 ,DMA Interrupt 35 Selects AXE" "IPIC,AXE" bitfld.long 0x00 2. " ISA34 ,DMA Interrupt 34 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x00 1. " ISA33 ,DMA Interrupt 33 Selects AXE" "IPIC,AXE" bitfld.long 0x00 0. " ISA32 ,DMA Interrupt 32 Selects AXE" "IPIC,AXE" line.long 0x04 "DMAILSA,DMA Interrupt Select AXE Low" bitfld.long 0x04 31. " ISA31 ,DMA Interrupt 31 Selects AXE" "IPIC,AXE" bitfld.long 0x04 30. " ISA30 ,DMA Interrupt 30 Selects AXE" "IPIC,AXE" bitfld.long 0x04 29. " ISA29 ,DMA Interrupt 29 Selects AXE" "IPIC,AXE" bitfld.long 0x04 28. " ISA28 ,DMA Interrupt 28 Selects AXE" "IPIC,AXE" bitfld.long 0x04 27. " ISA27 ,DMA Interrupt 27 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 26. " ISA26 ,DMA Interrupt 26 Selects AXE" "IPIC,AXE" bitfld.long 0x04 25. " ISA25 ,DMA Interrupt 25 Selects AXE" "IPIC,AXE" bitfld.long 0x04 24. " ISA24 ,DMA Interrupt 24 Selects AXE" "IPIC,AXE" bitfld.long 0x04 23. " ISA23 ,DMA Interrupt 23 Selects AXE" "IPIC,AXE" bitfld.long 0x04 22. " ISA22 ,DMA Interrupt 22 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 21. " ISA21 ,DMA Interrupt 21 Selects AXE" "IPIC,AXE" bitfld.long 0x04 20. " ISA20 ,DMA Interrupt 20 Selects AXE" "IPIC,AXE" bitfld.long 0x04 19. " ISA19 ,DMA Interrupt 19 Selects AXE" "IPIC,AXE" bitfld.long 0x04 18. " ISA18 ,DMA Interrupt 18 Selects AXE" "IPIC,AXE" bitfld.long 0x04 17. " ISA17 ,DMA Interrupt 17 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 16. " ISA16 ,DMA Interrupt 16 Selects AXE" "IPIC,AXE" bitfld.long 0x04 15. " ISA15 ,DMA Interrupt 15 Selects AXE" "IPIC,AXE" bitfld.long 0x04 14. " ISA14 ,DMA Interrupt 14 Selects AXE" "IPIC,AXE" bitfld.long 0x04 13. " ISA13 ,DMA Interrupt 13 Selects AXE" "IPIC,AXE" bitfld.long 0x04 12. " ISA12 ,DMA Interrupt 12 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 11. " ISA11 ,DMA Interrupt 11 Selects AXE" "IPIC,AXE" bitfld.long 0x04 10. " ISA10 ,DMA Interrupt 10 Selects AXE" "IPIC,AXE" bitfld.long 0x04 9. " ISA9 ,DMA Interrupt 9 Selects AXE" "IPIC,AXE" bitfld.long 0x04 8. " ISA8 ,DMA Interrupt 8 Selects AXE" "IPIC,AXE" bitfld.long 0x04 7. " ISA7 ,DMA Interrupt 7 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 6. " ISA6 ,DMA Interrupt 6 Selects AXE" "IPIC,AXE" bitfld.long 0x04 5. " ISA5 ,DMA Interrupt 5 Selects AXE" "IPIC,AXE" bitfld.long 0x04 4. " ISA4 ,DMA Interrupt 4 Selects AXE" "IPIC,AXE" bitfld.long 0x04 3. " ISA3 ,DMA Interrupt 3 Selects AXE" "IPIC,AXE" bitfld.long 0x04 2. " ISA2 ,DMA Interrupt 2 Selects AXE" "IPIC,AXE" textline " " bitfld.long 0x04 1. " ISA1 ,DMA Interrupt 1 Selects AXE" "IPIC,AXE" bitfld.long 0x04 0. " ISA0 ,DMA Interrupt 0 Selects AXE" "IPIC,AXE" width 10. tree "DMA Channel Priority Registers" group.byte 0x14100++0x3f line.byte 0x0 "DCHPRI0 ,DMA Channel 0 Priority" bitfld.byte 0x0 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x0 4.--5. " GRPPRI[1:0] ,Channel 0 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x0 0.--3. " CHPRI[3:0] ,Channel 0 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1 "DCHPRI1 ,DMA Channel 1 Priority" bitfld.byte 0x1 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1 4.--5. " GRPPRI[1:0] ,Channel 1 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1 0.--3. " CHPRI[3:0] ,Channel 1 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2 "DCHPRI2 ,DMA Channel 2 Priority" bitfld.byte 0x2 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2 4.--5. " GRPPRI[1:0] ,Channel 2 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2 0.--3. " CHPRI[3:0] ,Channel 2 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3 "DCHPRI3 ,DMA Channel 3 Priority" bitfld.byte 0x3 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3 4.--5. " GRPPRI[1:0] ,Channel 3 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3 0.--3. " CHPRI[3:0] ,Channel 3 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x4 "DCHPRI4 ,DMA Channel 4 Priority" bitfld.byte 0x4 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x4 4.--5. " GRPPRI[1:0] ,Channel 4 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x4 0.--3. " CHPRI[3:0] ,Channel 4 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x5 "DCHPRI5 ,DMA Channel 5 Priority" bitfld.byte 0x5 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x5 4.--5. " GRPPRI[1:0] ,Channel 5 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x5 0.--3. " CHPRI[3:0] ,Channel 5 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x6 "DCHPRI6 ,DMA Channel 6 Priority" bitfld.byte 0x6 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x6 4.--5. " GRPPRI[1:0] ,Channel 6 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x6 0.--3. " CHPRI[3:0] ,Channel 6 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x7 "DCHPRI7 ,DMA Channel 7 Priority" bitfld.byte 0x7 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x7 4.--5. " GRPPRI[1:0] ,Channel 7 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x7 0.--3. " CHPRI[3:0] ,Channel 7 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x8 "DCHPRI8 ,DMA Channel 8 Priority" bitfld.byte 0x8 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x8 4.--5. " GRPPRI[1:0] ,Channel 8 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x8 0.--3. " CHPRI[3:0] ,Channel 8 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x9 "DCHPRI9 ,DMA Channel 9 Priority" bitfld.byte 0x9 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x9 4.--5. " GRPPRI[1:0] ,Channel 9 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x9 0.--3. " CHPRI[3:0] ,Channel 9 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xA "DCHPRI10,DMA Channel 10 Priority" bitfld.byte 0xA 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xA 4.--5. " GRPPRI[1:0] ,Channel 10 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xA 0.--3. " CHPRI[3:0] ,Channel 10 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xB "DCHPRI11,DMA Channel 11 Priority" bitfld.byte 0xB 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xB 4.--5. " GRPPRI[1:0] ,Channel 11 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xB 0.--3. " CHPRI[3:0] ,Channel 11 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xC "DCHPRI12,DMA Channel 12 Priority" bitfld.byte 0xC 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xC 4.--5. " GRPPRI[1:0] ,Channel 12 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xC 0.--3. " CHPRI[3:0] ,Channel 12 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xD "DCHPRI13,DMA Channel 13 Priority" bitfld.byte 0xD 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xD 4.--5. " GRPPRI[1:0] ,Channel 13 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xD 0.--3. " CHPRI[3:0] ,Channel 13 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xE "DCHPRI14,DMA Channel 14 Priority" bitfld.byte 0xE 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xE 4.--5. " GRPPRI[1:0] ,Channel 14 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xE 0.--3. " CHPRI[3:0] ,Channel 14 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0xF "DCHPRI15,DMA Channel 15 Priority" bitfld.byte 0xF 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0xF 4.--5. " GRPPRI[1:0] ,Channel 15 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0xF 0.--3. " CHPRI[3:0] ,Channel 15 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x10 "DCHPRI16,DMA Channel 16 Priority" bitfld.byte 0x10 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x10 4.--5. " GRPPRI[1:0] ,Channel 16 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x10 0.--3. " CHPRI[3:0] ,Channel 16 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x11 "DCHPRI17,DMA Channel 17 Priority" bitfld.byte 0x11 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x11 4.--5. " GRPPRI[1:0] ,Channel 17 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x11 0.--3. " CHPRI[3:0] ,Channel 17 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x12 "DCHPRI18,DMA Channel 18 Priority" bitfld.byte 0x12 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x12 4.--5. " GRPPRI[1:0] ,Channel 18 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x12 0.--3. " CHPRI[3:0] ,Channel 18 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x13 "DCHPRI19,DMA Channel 19 Priority" bitfld.byte 0x13 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x13 4.--5. " GRPPRI[1:0] ,Channel 19 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x13 0.--3. " CHPRI[3:0] ,Channel 19 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x14 "DCHPRI20,DMA Channel 20 Priority" bitfld.byte 0x14 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x14 4.--5. " GRPPRI[1:0] ,Channel 20 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x14 0.--3. " CHPRI[3:0] ,Channel 20 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x15 "DCHPRI21,DMA Channel 21 Priority" bitfld.byte 0x15 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x15 4.--5. " GRPPRI[1:0] ,Channel 21 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x15 0.--3. " CHPRI[3:0] ,Channel 21 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x16 "DCHPRI22,DMA Channel 22 Priority" bitfld.byte 0x16 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x16 4.--5. " GRPPRI[1:0] ,Channel 22 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x16 0.--3. " CHPRI[3:0] ,Channel 22 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x17 "DCHPRI23,DMA Channel 23 Priority" bitfld.byte 0x17 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x17 4.--5. " GRPPRI[1:0] ,Channel 23 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x17 0.--3. " CHPRI[3:0] ,Channel 23 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x18 "DCHPRI24,DMA Channel 24 Priority" bitfld.byte 0x18 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x18 4.--5. " GRPPRI[1:0] ,Channel 24 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x18 0.--3. " CHPRI[3:0] ,Channel 24 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x19 "DCHPRI25,DMA Channel 25 Priority" bitfld.byte 0x19 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x19 4.--5. " GRPPRI[1:0] ,Channel 25 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x19 0.--3. " CHPRI[3:0] ,Channel 25 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1A "DCHPRI26,DMA Channel 26 Priority" bitfld.byte 0x1A 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1A 4.--5. " GRPPRI[1:0] ,Channel 26 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1A 0.--3. " CHPRI[3:0] ,Channel 26 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1B "DCHPRI27,DMA Channel 27 Priority" bitfld.byte 0x1B 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1B 4.--5. " GRPPRI[1:0] ,Channel 27 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1B 0.--3. " CHPRI[3:0] ,Channel 27 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1C "DCHPRI28,DMA Channel 28 Priority" bitfld.byte 0x1C 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1C 4.--5. " GRPPRI[1:0] ,Channel 28 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1C 0.--3. " CHPRI[3:0] ,Channel 28 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1D "DCHPRI29,DMA Channel 29 Priority" bitfld.byte 0x1D 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1D 4.--5. " GRPPRI[1:0] ,Channel 29 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1D 0.--3. " CHPRI[3:0] ,Channel 29 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1E "DCHPRI30,DMA Channel 30 Priority" bitfld.byte 0x1E 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1E 4.--5. " GRPPRI[1:0] ,Channel 30 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1E 0.--3. " CHPRI[3:0] ,Channel 30 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x1F "DCHPRI31,DMA Channel 31 Priority" bitfld.byte 0x1F 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x1F 4.--5. " GRPPRI[1:0] ,Channel 31 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x1F 0.--3. " CHPRI[3:0] ,Channel 31 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x20 "DCHPRI32,DMA Channel 32 Priority" bitfld.byte 0x20 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x20 4.--5. " GRPPRI[1:0] ,Channel 32 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x20 0.--3. " CHPRI[3:0] ,Channel 32 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x21 "DCHPRI33,DMA Channel 33 Priority" bitfld.byte 0x21 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x21 4.--5. " GRPPRI[1:0] ,Channel 33 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x21 0.--3. " CHPRI[3:0] ,Channel 33 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x22 "DCHPRI34,DMA Channel 34 Priority" bitfld.byte 0x22 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x22 4.--5. " GRPPRI[1:0] ,Channel 34 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x22 0.--3. " CHPRI[3:0] ,Channel 34 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x23 "DCHPRI35,DMA Channel 35 Priority" bitfld.byte 0x23 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x23 4.--5. " GRPPRI[1:0] ,Channel 35 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x23 0.--3. " CHPRI[3:0] ,Channel 35 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x24 "DCHPRI36,DMA Channel 36 Priority" bitfld.byte 0x24 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x24 4.--5. " GRPPRI[1:0] ,Channel 36 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x24 0.--3. " CHPRI[3:0] ,Channel 36 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x25 "DCHPRI37,DMA Channel 37 Priority" bitfld.byte 0x25 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x25 4.--5. " GRPPRI[1:0] ,Channel 37 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x25 0.--3. " CHPRI[3:0] ,Channel 37 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x26 "DCHPRI38,DMA Channel 38 Priority" bitfld.byte 0x26 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x26 4.--5. " GRPPRI[1:0] ,Channel 38 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x26 0.--3. " CHPRI[3:0] ,Channel 38 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x27 "DCHPRI39,DMA Channel 39 Priority" bitfld.byte 0x27 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x27 4.--5. " GRPPRI[1:0] ,Channel 39 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x27 0.--3. " CHPRI[3:0] ,Channel 39 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x28 "DCHPRI40,DMA Channel 40 Priority" bitfld.byte 0x28 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x28 4.--5. " GRPPRI[1:0] ,Channel 40 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x28 0.--3. " CHPRI[3:0] ,Channel 40 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x29 "DCHPRI41,DMA Channel 41 Priority" bitfld.byte 0x29 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x29 4.--5. " GRPPRI[1:0] ,Channel 41 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x29 0.--3. " CHPRI[3:0] ,Channel 41 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2A "DCHPRI42,DMA Channel 42 Priority" bitfld.byte 0x2A 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2A 4.--5. " GRPPRI[1:0] ,Channel 42 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2A 0.--3. " CHPRI[3:0] ,Channel 42 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2B "DCHPRI43,DMA Channel 43 Priority" bitfld.byte 0x2B 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2B 4.--5. " GRPPRI[1:0] ,Channel 43 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2B 0.--3. " CHPRI[3:0] ,Channel 43 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2C "DCHPRI44,DMA Channel 44 Priority" bitfld.byte 0x2C 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2C 4.--5. " GRPPRI[1:0] ,Channel 44 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2C 0.--3. " CHPRI[3:0] ,Channel 44 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2D "DCHPRI45,DMA Channel 45 Priority" bitfld.byte 0x2D 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2D 4.--5. " GRPPRI[1:0] ,Channel 45 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2D 0.--3. " CHPRI[3:0] ,Channel 45 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2E "DCHPRI46,DMA Channel 46 Priority" bitfld.byte 0x2E 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2E 4.--5. " GRPPRI[1:0] ,Channel 46 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2E 0.--3. " CHPRI[3:0] ,Channel 46 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x2F "DCHPRI47,DMA Channel 47 Priority" bitfld.byte 0x2F 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x2F 4.--5. " GRPPRI[1:0] ,Channel 47 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x2F 0.--3. " CHPRI[3:0] ,Channel 47 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x30 "DCHPRI48,DMA Channel 48 Priority" bitfld.byte 0x30 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x30 4.--5. " GRPPRI[1:0] ,Channel 48 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x30 0.--3. " CHPRI[3:0] ,Channel 48 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x31 "DCHPRI49,DMA Channel 49 Priority" bitfld.byte 0x31 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x31 4.--5. " GRPPRI[1:0] ,Channel 49 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x31 0.--3. " CHPRI[3:0] ,Channel 49 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x32 "DCHPRI50,DMA Channel 50 Priority" bitfld.byte 0x32 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x32 4.--5. " GRPPRI[1:0] ,Channel 50 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x32 0.--3. " CHPRI[3:0] ,Channel 50 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x33 "DCHPRI51,DMA Channel 51 Priority" bitfld.byte 0x33 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x33 4.--5. " GRPPRI[1:0] ,Channel 51 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x33 0.--3. " CHPRI[3:0] ,Channel 51 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x34 "DCHPRI52,DMA Channel 52 Priority" bitfld.byte 0x34 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x34 4.--5. " GRPPRI[1:0] ,Channel 52 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x34 0.--3. " CHPRI[3:0] ,Channel 52 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x35 "DCHPRI53,DMA Channel 53 Priority" bitfld.byte 0x35 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x35 4.--5. " GRPPRI[1:0] ,Channel 53 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x35 0.--3. " CHPRI[3:0] ,Channel 53 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x36 "DCHPRI54,DMA Channel 54 Priority" bitfld.byte 0x36 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x36 4.--5. " GRPPRI[1:0] ,Channel 54 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x36 0.--3. " CHPRI[3:0] ,Channel 54 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x37 "DCHPRI55,DMA Channel 55 Priority" bitfld.byte 0x37 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x37 4.--5. " GRPPRI[1:0] ,Channel 55 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x37 0.--3. " CHPRI[3:0] ,Channel 55 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x38 "DCHPRI56,DMA Channel 56 Priority" bitfld.byte 0x38 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x38 4.--5. " GRPPRI[1:0] ,Channel 56 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x38 0.--3. " CHPRI[3:0] ,Channel 56 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x39 "DCHPRI57,DMA Channel 57 Priority" bitfld.byte 0x39 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x39 4.--5. " GRPPRI[1:0] ,Channel 57 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x39 0.--3. " CHPRI[3:0] ,Channel 57 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3A "DCHPRI58,DMA Channel 58 Priority" bitfld.byte 0x3A 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3A 4.--5. " GRPPRI[1:0] ,Channel 58 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3A 0.--3. " CHPRI[3:0] ,Channel 58 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3B "DCHPRI59,DMA Channel 59 Priority" bitfld.byte 0x3B 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3B 4.--5. " GRPPRI[1:0] ,Channel 59 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3B 0.--3. " CHPRI[3:0] ,Channel 59 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3C "DCHPRI60,DMA Channel 60 Priority" bitfld.byte 0x3C 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3C 4.--5. " GRPPRI[1:0] ,Channel 60 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3C 0.--3. " CHPRI[3:0] ,Channel 60 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3D "DCHPRI61,DMA Channel 61 Priority" bitfld.byte 0x3D 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3D 4.--5. " GRPPRI[1:0] ,Channel 61 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3D 0.--3. " CHPRI[3:0] ,Channel 61 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3E "DCHPRI62,DMA Channel 62 Priority" bitfld.byte 0x3E 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3E 4.--5. " GRPPRI[1:0] ,Channel 62 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3E 0.--3. " CHPRI[3:0] ,Channel 62 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.byte 0x3F "DCHPRI63,DMA Channel 63 Priority" bitfld.byte 0x3F 7. " ECP ,Enable Channel Preemption" "Not suspended,Suspended" bitfld.byte 0x3F 4.--5. " GRPPRI[1:0] ,Channel 63 Current Group Priority" "Level 0,Level 1,Level 2,Level 3" textline " " bitfld.byte 0x3F 0.--3. " CHPRI[3:0] ,Channel 63 Arbitration Priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" tree.end width 10. tree "Transfer Control Descriptor Registers" group.long 0x15000++0x01f "Transfer Control Descriptor Register 0 " line.long 0x00 "TCD0 W0,TCD0 Word 0 Field (SADDR)" line.long 0x04 "TCD0 W1,TCD0 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD0 W2,TCD0 Word 2 Field (NBYTES)" line.long 0x0c "TCD0 W3,TCD0 Word 3 Field (SLAST)" line.long 0x10 "TCD0 W4,TCD0 Word 4 Field (DADDR)" line.long 0x14 "TCD0 W5,TCD0 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD0 W6,TCD0 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD0 W7,TCD0 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15020++0x01f "Transfer Control Descriptor Register 1 " line.long 0x00 "TCD1 W0,TCD1 Word 0 Field (SADDR)" line.long 0x04 "TCD1 W1,TCD1 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD1 W2,TCD1 Word 2 Field (NBYTES)" line.long 0x0c "TCD1 W3,TCD1 Word 3 Field (SLAST)" line.long 0x10 "TCD1 W4,TCD1 Word 4 Field (DADDR)" line.long 0x14 "TCD1 W5,TCD1 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD1 W6,TCD1 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD1 W7,TCD1 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15040++0x01f "Transfer Control Descriptor Register 2 " line.long 0x00 "TCD2 W0,TCD2 Word 0 Field (SADDR)" line.long 0x04 "TCD2 W1,TCD2 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD2 W2,TCD2 Word 2 Field (NBYTES)" line.long 0x0c "TCD2 W3,TCD2 Word 3 Field (SLAST)" line.long 0x10 "TCD2 W4,TCD2 Word 4 Field (DADDR)" line.long 0x14 "TCD2 W5,TCD2 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD2 W6,TCD2 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD2 W7,TCD2 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15060++0x01f "Transfer Control Descriptor Register 3 " line.long 0x00 "TCD3 W0,TCD3 Word 0 Field (SADDR)" line.long 0x04 "TCD3 W1,TCD3 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD3 W2,TCD3 Word 2 Field (NBYTES)" line.long 0x0c "TCD3 W3,TCD3 Word 3 Field (SLAST)" line.long 0x10 "TCD3 W4,TCD3 Word 4 Field (DADDR)" line.long 0x14 "TCD3 W5,TCD3 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD3 W6,TCD3 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD3 W7,TCD3 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15080++0x01f "Transfer Control Descriptor Register 4 " line.long 0x00 "TCD4 W0,TCD4 Word 0 Field (SADDR)" line.long 0x04 "TCD4 W1,TCD4 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD4 W2,TCD4 Word 2 Field (NBYTES)" line.long 0x0c "TCD4 W3,TCD4 Word 3 Field (SLAST)" line.long 0x10 "TCD4 W4,TCD4 Word 4 Field (DADDR)" line.long 0x14 "TCD4 W5,TCD4 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD4 W6,TCD4 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD4 W7,TCD4 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x150A0++0x01f "Transfer Control Descriptor Register 5 " line.long 0x00 "TCD5 W0,TCD5 Word 0 Field (SADDR)" line.long 0x04 "TCD5 W1,TCD5 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD5 W2,TCD5 Word 2 Field (NBYTES)" line.long 0x0c "TCD5 W3,TCD5 Word 3 Field (SLAST)" line.long 0x10 "TCD5 W4,TCD5 Word 4 Field (DADDR)" line.long 0x14 "TCD5 W5,TCD5 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD5 W6,TCD5 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD5 W7,TCD5 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x150C0++0x01f "Transfer Control Descriptor Register 6 " line.long 0x00 "TCD6 W0,TCD6 Word 0 Field (SADDR)" line.long 0x04 "TCD6 W1,TCD6 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD6 W2,TCD6 Word 2 Field (NBYTES)" line.long 0x0c "TCD6 W3,TCD6 Word 3 Field (SLAST)" line.long 0x10 "TCD6 W4,TCD6 Word 4 Field (DADDR)" line.long 0x14 "TCD6 W5,TCD6 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD6 W6,TCD6 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD6 W7,TCD6 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x150E0++0x01f "Transfer Control Descriptor Register 7 " line.long 0x00 "TCD7 W0,TCD7 Word 0 Field (SADDR)" line.long 0x04 "TCD7 W1,TCD7 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD7 W2,TCD7 Word 2 Field (NBYTES)" line.long 0x0c "TCD7 W3,TCD7 Word 3 Field (SLAST)" line.long 0x10 "TCD7 W4,TCD7 Word 4 Field (DADDR)" line.long 0x14 "TCD7 W5,TCD7 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD7 W6,TCD7 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD7 W7,TCD7 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15100++0x01f "Transfer Control Descriptor Register 8 " line.long 0x00 "TCD8 W0,TCD8 Word 0 Field (SADDR)" line.long 0x04 "TCD8 W1,TCD8 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD8 W2,TCD8 Word 2 Field (NBYTES)" line.long 0x0c "TCD8 W3,TCD8 Word 3 Field (SLAST)" line.long 0x10 "TCD8 W4,TCD8 Word 4 Field (DADDR)" line.long 0x14 "TCD8 W5,TCD8 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD8 W6,TCD8 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD8 W7,TCD8 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15120++0x01f "Transfer Control Descriptor Register 9 " line.long 0x00 "TCD9 W0,TCD9 Word 0 Field (SADDR)" line.long 0x04 "TCD9 W1,TCD9 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD9 W2,TCD9 Word 2 Field (NBYTES)" line.long 0x0c "TCD9 W3,TCD9 Word 3 Field (SLAST)" line.long 0x10 "TCD9 W4,TCD9 Word 4 Field (DADDR)" line.long 0x14 "TCD9 W5,TCD9 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD9 W6,TCD9 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD9 W7,TCD9 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15140++0x01f "Transfer Control Descriptor Register 10" line.long 0x00 "TCD10W0,TCD10 Word 0 Field (SADDR)" line.long 0x04 "TCD10W1,TCD10 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD10W2,TCD10 Word 2 Field (NBYTES)" line.long 0x0c "TCD10W3,TCD10 Word 3 Field (SLAST)" line.long 0x10 "TCD10W4,TCD10 Word 4 Field (DADDR)" line.long 0x14 "TCD10W5,TCD10 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD10W6,TCD10 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD10W7,TCD10 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15160++0x01f "Transfer Control Descriptor Register 11" line.long 0x00 "TCD11W0,TCD11 Word 0 Field (SADDR)" line.long 0x04 "TCD11W1,TCD11 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD11W2,TCD11 Word 2 Field (NBYTES)" line.long 0x0c "TCD11W3,TCD11 Word 3 Field (SLAST)" line.long 0x10 "TCD11W4,TCD11 Word 4 Field (DADDR)" line.long 0x14 "TCD11W5,TCD11 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD11W6,TCD11 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD11W7,TCD11 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15180++0x01f "Transfer Control Descriptor Register 12" line.long 0x00 "TCD12W0,TCD12 Word 0 Field (SADDR)" line.long 0x04 "TCD12W1,TCD12 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD12W2,TCD12 Word 2 Field (NBYTES)" line.long 0x0c "TCD12W3,TCD12 Word 3 Field (SLAST)" line.long 0x10 "TCD12W4,TCD12 Word 4 Field (DADDR)" line.long 0x14 "TCD12W5,TCD12 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD12W6,TCD12 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD12W7,TCD12 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x151A0++0x01f "Transfer Control Descriptor Register 13" line.long 0x00 "TCD13W0,TCD13 Word 0 Field (SADDR)" line.long 0x04 "TCD13W1,TCD13 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD13W2,TCD13 Word 2 Field (NBYTES)" line.long 0x0c "TCD13W3,TCD13 Word 3 Field (SLAST)" line.long 0x10 "TCD13W4,TCD13 Word 4 Field (DADDR)" line.long 0x14 "TCD13W5,TCD13 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD13W6,TCD13 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD13W7,TCD13 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x151C0++0x01f "Transfer Control Descriptor Register 14" line.long 0x00 "TCD14W0,TCD14 Word 0 Field (SADDR)" line.long 0x04 "TCD14W1,TCD14 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD14W2,TCD14 Word 2 Field (NBYTES)" line.long 0x0c "TCD14W3,TCD14 Word 3 Field (SLAST)" line.long 0x10 "TCD14W4,TCD14 Word 4 Field (DADDR)" line.long 0x14 "TCD14W5,TCD14 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD14W6,TCD14 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD14W7,TCD14 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x151E0++0x01f "Transfer Control Descriptor Register 15" line.long 0x00 "TCD15W0,TCD15 Word 0 Field (SADDR)" line.long 0x04 "TCD15W1,TCD15 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD15W2,TCD15 Word 2 Field (NBYTES)" line.long 0x0c "TCD15W3,TCD15 Word 3 Field (SLAST)" line.long 0x10 "TCD15W4,TCD15 Word 4 Field (DADDR)" line.long 0x14 "TCD15W5,TCD15 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD15W6,TCD15 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD15W7,TCD15 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15200++0x01f "Transfer Control Descriptor Register 16" line.long 0x00 "TCD16W0,TCD16 Word 0 Field (SADDR)" line.long 0x04 "TCD16W1,TCD16 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD16W2,TCD16 Word 2 Field (NBYTES)" line.long 0x0c "TCD16W3,TCD16 Word 3 Field (SLAST)" line.long 0x10 "TCD16W4,TCD16 Word 4 Field (DADDR)" line.long 0x14 "TCD16W5,TCD16 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD16W6,TCD16 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD16W7,TCD16 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15220++0x01f "Transfer Control Descriptor Register 17" line.long 0x00 "TCD17W0,TCD17 Word 0 Field (SADDR)" line.long 0x04 "TCD17W1,TCD17 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD17W2,TCD17 Word 2 Field (NBYTES)" line.long 0x0c "TCD17W3,TCD17 Word 3 Field (SLAST)" line.long 0x10 "TCD17W4,TCD17 Word 4 Field (DADDR)" line.long 0x14 "TCD17W5,TCD17 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD17W6,TCD17 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD17W7,TCD17 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15240++0x01f "Transfer Control Descriptor Register 18" line.long 0x00 "TCD18W0,TCD18 Word 0 Field (SADDR)" line.long 0x04 "TCD18W1,TCD18 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD18W2,TCD18 Word 2 Field (NBYTES)" line.long 0x0c "TCD18W3,TCD18 Word 3 Field (SLAST)" line.long 0x10 "TCD18W4,TCD18 Word 4 Field (DADDR)" line.long 0x14 "TCD18W5,TCD18 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD18W6,TCD18 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD18W7,TCD18 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15260++0x01f "Transfer Control Descriptor Register 19" line.long 0x00 "TCD19W0,TCD19 Word 0 Field (SADDR)" line.long 0x04 "TCD19W1,TCD19 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD19W2,TCD19 Word 2 Field (NBYTES)" line.long 0x0c "TCD19W3,TCD19 Word 3 Field (SLAST)" line.long 0x10 "TCD19W4,TCD19 Word 4 Field (DADDR)" line.long 0x14 "TCD19W5,TCD19 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD19W6,TCD19 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD19W7,TCD19 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15280++0x01f "Transfer Control Descriptor Register 20" line.long 0x00 "TCD20W0,TCD20 Word 0 Field (SADDR)" line.long 0x04 "TCD20W1,TCD20 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD20W2,TCD20 Word 2 Field (NBYTES)" line.long 0x0c "TCD20W3,TCD20 Word 3 Field (SLAST)" line.long 0x10 "TCD20W4,TCD20 Word 4 Field (DADDR)" line.long 0x14 "TCD20W5,TCD20 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD20W6,TCD20 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD20W7,TCD20 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x152A0++0x01f "Transfer Control Descriptor Register 21" line.long 0x00 "TCD21W0,TCD21 Word 0 Field (SADDR)" line.long 0x04 "TCD21W1,TCD21 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD21W2,TCD21 Word 2 Field (NBYTES)" line.long 0x0c "TCD21W3,TCD21 Word 3 Field (SLAST)" line.long 0x10 "TCD21W4,TCD21 Word 4 Field (DADDR)" line.long 0x14 "TCD21W5,TCD21 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD21W6,TCD21 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD21W7,TCD21 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x152C0++0x01f "Transfer Control Descriptor Register 22" line.long 0x00 "TCD22W0,TCD22 Word 0 Field (SADDR)" line.long 0x04 "TCD22W1,TCD22 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD22W2,TCD22 Word 2 Field (NBYTES)" line.long 0x0c "TCD22W3,TCD22 Word 3 Field (SLAST)" line.long 0x10 "TCD22W4,TCD22 Word 4 Field (DADDR)" line.long 0x14 "TCD22W5,TCD22 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD22W6,TCD22 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD22W7,TCD22 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x152E0++0x01f "Transfer Control Descriptor Register 23" line.long 0x00 "TCD23W0,TCD23 Word 0 Field (SADDR)" line.long 0x04 "TCD23W1,TCD23 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD23W2,TCD23 Word 2 Field (NBYTES)" line.long 0x0c "TCD23W3,TCD23 Word 3 Field (SLAST)" line.long 0x10 "TCD23W4,TCD23 Word 4 Field (DADDR)" line.long 0x14 "TCD23W5,TCD23 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD23W6,TCD23 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD23W7,TCD23 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15300++0x01f "Transfer Control Descriptor Register 24" line.long 0x00 "TCD24W0,TCD24 Word 0 Field (SADDR)" line.long 0x04 "TCD24W1,TCD24 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD24W2,TCD24 Word 2 Field (NBYTES)" line.long 0x0c "TCD24W3,TCD24 Word 3 Field (SLAST)" line.long 0x10 "TCD24W4,TCD24 Word 4 Field (DADDR)" line.long 0x14 "TCD24W5,TCD24 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD24W6,TCD24 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD24W7,TCD24 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15320++0x01f "Transfer Control Descriptor Register 25" line.long 0x00 "TCD25W0,TCD25 Word 0 Field (SADDR)" line.long 0x04 "TCD25W1,TCD25 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD25W2,TCD25 Word 2 Field (NBYTES)" line.long 0x0c "TCD25W3,TCD25 Word 3 Field (SLAST)" line.long 0x10 "TCD25W4,TCD25 Word 4 Field (DADDR)" line.long 0x14 "TCD25W5,TCD25 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD25W6,TCD25 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD25W7,TCD25 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15340++0x01f "Transfer Control Descriptor Register 26" line.long 0x00 "TCD26W0,TCD26 Word 0 Field (SADDR)" line.long 0x04 "TCD26W1,TCD26 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD26W2,TCD26 Word 2 Field (NBYTES)" line.long 0x0c "TCD26W3,TCD26 Word 3 Field (SLAST)" line.long 0x10 "TCD26W4,TCD26 Word 4 Field (DADDR)" line.long 0x14 "TCD26W5,TCD26 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD26W6,TCD26 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD26W7,TCD26 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15360++0x01f "Transfer Control Descriptor Register 27" line.long 0x00 "TCD27W0,TCD27 Word 0 Field (SADDR)" line.long 0x04 "TCD27W1,TCD27 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD27W2,TCD27 Word 2 Field (NBYTES)" line.long 0x0c "TCD27W3,TCD27 Word 3 Field (SLAST)" line.long 0x10 "TCD27W4,TCD27 Word 4 Field (DADDR)" line.long 0x14 "TCD27W5,TCD27 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD27W6,TCD27 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD27W7,TCD27 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15380++0x01f "Transfer Control Descriptor Register 28" line.long 0x00 "TCD28W0,TCD28 Word 0 Field (SADDR)" line.long 0x04 "TCD28W1,TCD28 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD28W2,TCD28 Word 2 Field (NBYTES)" line.long 0x0c "TCD28W3,TCD28 Word 3 Field (SLAST)" line.long 0x10 "TCD28W4,TCD28 Word 4 Field (DADDR)" line.long 0x14 "TCD28W5,TCD28 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD28W6,TCD28 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD28W7,TCD28 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x153A0++0x01f "Transfer Control Descriptor Register 29" line.long 0x00 "TCD29W0,TCD29 Word 0 Field (SADDR)" line.long 0x04 "TCD29W1,TCD29 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD29W2,TCD29 Word 2 Field (NBYTES)" line.long 0x0c "TCD29W3,TCD29 Word 3 Field (SLAST)" line.long 0x10 "TCD29W4,TCD29 Word 4 Field (DADDR)" line.long 0x14 "TCD29W5,TCD29 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD29W6,TCD29 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD29W7,TCD29 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x153C0++0x01f "Transfer Control Descriptor Register 30" line.long 0x00 "TCD30W0,TCD30 Word 0 Field (SADDR)" line.long 0x04 "TCD30W1,TCD30 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD30W2,TCD30 Word 2 Field (NBYTES)" line.long 0x0c "TCD30W3,TCD30 Word 3 Field (SLAST)" line.long 0x10 "TCD30W4,TCD30 Word 4 Field (DADDR)" line.long 0x14 "TCD30W5,TCD30 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD30W6,TCD30 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD30W7,TCD30 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x153E0++0x01f "Transfer Control Descriptor Register 31" line.long 0x00 "TCD31W0,TCD31 Word 0 Field (SADDR)" line.long 0x04 "TCD31W1,TCD31 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD31W2,TCD31 Word 2 Field (NBYTES)" line.long 0x0c "TCD31W3,TCD31 Word 3 Field (SLAST)" line.long 0x10 "TCD31W4,TCD31 Word 4 Field (DADDR)" line.long 0x14 "TCD31W5,TCD31 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD31W6,TCD31 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD31W7,TCD31 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15400++0x01f "Transfer Control Descriptor Register 32" line.long 0x00 "TCD32W0,TCD32 Word 0 Field (SADDR)" line.long 0x04 "TCD32W1,TCD32 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD32W2,TCD32 Word 2 Field (NBYTES)" line.long 0x0c "TCD32W3,TCD32 Word 3 Field (SLAST)" line.long 0x10 "TCD32W4,TCD32 Word 4 Field (DADDR)" line.long 0x14 "TCD32W5,TCD32 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD32W6,TCD32 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD32W7,TCD32 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15420++0x01f "Transfer Control Descriptor Register 33" line.long 0x00 "TCD33W0,TCD33 Word 0 Field (SADDR)" line.long 0x04 "TCD33W1,TCD33 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD33W2,TCD33 Word 2 Field (NBYTES)" line.long 0x0c "TCD33W3,TCD33 Word 3 Field (SLAST)" line.long 0x10 "TCD33W4,TCD33 Word 4 Field (DADDR)" line.long 0x14 "TCD33W5,TCD33 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD33W6,TCD33 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD33W7,TCD33 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15440++0x01f "Transfer Control Descriptor Register 34" line.long 0x00 "TCD34W0,TCD34 Word 0 Field (SADDR)" line.long 0x04 "TCD34W1,TCD34 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD34W2,TCD34 Word 2 Field (NBYTES)" line.long 0x0c "TCD34W3,TCD34 Word 3 Field (SLAST)" line.long 0x10 "TCD34W4,TCD34 Word 4 Field (DADDR)" line.long 0x14 "TCD34W5,TCD34 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD34W6,TCD34 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD34W7,TCD34 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15460++0x01f "Transfer Control Descriptor Register 35" line.long 0x00 "TCD35W0,TCD35 Word 0 Field (SADDR)" line.long 0x04 "TCD35W1,TCD35 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD35W2,TCD35 Word 2 Field (NBYTES)" line.long 0x0c "TCD35W3,TCD35 Word 3 Field (SLAST)" line.long 0x10 "TCD35W4,TCD35 Word 4 Field (DADDR)" line.long 0x14 "TCD35W5,TCD35 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD35W6,TCD35 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD35W7,TCD35 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15480++0x01f "Transfer Control Descriptor Register 36" line.long 0x00 "TCD36W0,TCD36 Word 0 Field (SADDR)" line.long 0x04 "TCD36W1,TCD36 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD36W2,TCD36 Word 2 Field (NBYTES)" line.long 0x0c "TCD36W3,TCD36 Word 3 Field (SLAST)" line.long 0x10 "TCD36W4,TCD36 Word 4 Field (DADDR)" line.long 0x14 "TCD36W5,TCD36 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD36W6,TCD36 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD36W7,TCD36 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x154A0++0x01f "Transfer Control Descriptor Register 37" line.long 0x00 "TCD37W0,TCD37 Word 0 Field (SADDR)" line.long 0x04 "TCD37W1,TCD37 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD37W2,TCD37 Word 2 Field (NBYTES)" line.long 0x0c "TCD37W3,TCD37 Word 3 Field (SLAST)" line.long 0x10 "TCD37W4,TCD37 Word 4 Field (DADDR)" line.long 0x14 "TCD37W5,TCD37 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD37W6,TCD37 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD37W7,TCD37 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x154C0++0x01f "Transfer Control Descriptor Register 38" line.long 0x00 "TCD38W0,TCD38 Word 0 Field (SADDR)" line.long 0x04 "TCD38W1,TCD38 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD38W2,TCD38 Word 2 Field (NBYTES)" line.long 0x0c "TCD38W3,TCD38 Word 3 Field (SLAST)" line.long 0x10 "TCD38W4,TCD38 Word 4 Field (DADDR)" line.long 0x14 "TCD38W5,TCD38 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD38W6,TCD38 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD38W7,TCD38 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x154E0++0x01f "Transfer Control Descriptor Register 39" line.long 0x00 "TCD39W0,TCD39 Word 0 Field (SADDR)" line.long 0x04 "TCD39W1,TCD39 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD39W2,TCD39 Word 2 Field (NBYTES)" line.long 0x0c "TCD39W3,TCD39 Word 3 Field (SLAST)" line.long 0x10 "TCD39W4,TCD39 Word 4 Field (DADDR)" line.long 0x14 "TCD39W5,TCD39 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD39W6,TCD39 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD39W7,TCD39 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15500++0x01f "Transfer Control Descriptor Register 40" line.long 0x00 "TCD40W0,TCD40 Word 0 Field (SADDR)" line.long 0x04 "TCD40W1,TCD40 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD40W2,TCD40 Word 2 Field (NBYTES)" line.long 0x0c "TCD40W3,TCD40 Word 3 Field (SLAST)" line.long 0x10 "TCD40W4,TCD40 Word 4 Field (DADDR)" line.long 0x14 "TCD40W5,TCD40 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD40W6,TCD40 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD40W7,TCD40 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15520++0x01f "Transfer Control Descriptor Register 41" line.long 0x00 "TCD41W0,TCD41 Word 0 Field (SADDR)" line.long 0x04 "TCD41W1,TCD41 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD41W2,TCD41 Word 2 Field (NBYTES)" line.long 0x0c "TCD41W3,TCD41 Word 3 Field (SLAST)" line.long 0x10 "TCD41W4,TCD41 Word 4 Field (DADDR)" line.long 0x14 "TCD41W5,TCD41 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD41W6,TCD41 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD41W7,TCD41 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15540++0x01f "Transfer Control Descriptor Register 42" line.long 0x00 "TCD42W0,TCD42 Word 0 Field (SADDR)" line.long 0x04 "TCD42W1,TCD42 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD42W2,TCD42 Word 2 Field (NBYTES)" line.long 0x0c "TCD42W3,TCD42 Word 3 Field (SLAST)" line.long 0x10 "TCD42W4,TCD42 Word 4 Field (DADDR)" line.long 0x14 "TCD42W5,TCD42 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD42W6,TCD42 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD42W7,TCD42 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15560++0x01f "Transfer Control Descriptor Register 43" line.long 0x00 "TCD43W0,TCD43 Word 0 Field (SADDR)" line.long 0x04 "TCD43W1,TCD43 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD43W2,TCD43 Word 2 Field (NBYTES)" line.long 0x0c "TCD43W3,TCD43 Word 3 Field (SLAST)" line.long 0x10 "TCD43W4,TCD43 Word 4 Field (DADDR)" line.long 0x14 "TCD43W5,TCD43 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD43W6,TCD43 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD43W7,TCD43 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15580++0x01f "Transfer Control Descriptor Register 44" line.long 0x00 "TCD44W0,TCD44 Word 0 Field (SADDR)" line.long 0x04 "TCD44W1,TCD44 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD44W2,TCD44 Word 2 Field (NBYTES)" line.long 0x0c "TCD44W3,TCD44 Word 3 Field (SLAST)" line.long 0x10 "TCD44W4,TCD44 Word 4 Field (DADDR)" line.long 0x14 "TCD44W5,TCD44 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD44W6,TCD44 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD44W7,TCD44 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x155A0++0x01f "Transfer Control Descriptor Register 45" line.long 0x00 "TCD45W0,TCD45 Word 0 Field (SADDR)" line.long 0x04 "TCD45W1,TCD45 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD45W2,TCD45 Word 2 Field (NBYTES)" line.long 0x0c "TCD45W3,TCD45 Word 3 Field (SLAST)" line.long 0x10 "TCD45W4,TCD45 Word 4 Field (DADDR)" line.long 0x14 "TCD45W5,TCD45 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD45W6,TCD45 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD45W7,TCD45 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x155C0++0x01f "Transfer Control Descriptor Register 46" line.long 0x00 "TCD46W0,TCD46 Word 0 Field (SADDR)" line.long 0x04 "TCD46W1,TCD46 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD46W2,TCD46 Word 2 Field (NBYTES)" line.long 0x0c "TCD46W3,TCD46 Word 3 Field (SLAST)" line.long 0x10 "TCD46W4,TCD46 Word 4 Field (DADDR)" line.long 0x14 "TCD46W5,TCD46 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD46W6,TCD46 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD46W7,TCD46 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x155E0++0x01f "Transfer Control Descriptor Register 47" line.long 0x00 "TCD47W0,TCD47 Word 0 Field (SADDR)" line.long 0x04 "TCD47W1,TCD47 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD47W2,TCD47 Word 2 Field (NBYTES)" line.long 0x0c "TCD47W3,TCD47 Word 3 Field (SLAST)" line.long 0x10 "TCD47W4,TCD47 Word 4 Field (DADDR)" line.long 0x14 "TCD47W5,TCD47 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD47W6,TCD47 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD47W7,TCD47 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15600++0x01f "Transfer Control Descriptor Register 48" line.long 0x00 "TCD48W0,TCD48 Word 0 Field (SADDR)" line.long 0x04 "TCD48W1,TCD48 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD48W2,TCD48 Word 2 Field (NBYTES)" line.long 0x0c "TCD48W3,TCD48 Word 3 Field (SLAST)" line.long 0x10 "TCD48W4,TCD48 Word 4 Field (DADDR)" line.long 0x14 "TCD48W5,TCD48 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD48W6,TCD48 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD48W7,TCD48 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15620++0x01f "Transfer Control Descriptor Register 49" line.long 0x00 "TCD49W0,TCD49 Word 0 Field (SADDR)" line.long 0x04 "TCD49W1,TCD49 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD49W2,TCD49 Word 2 Field (NBYTES)" line.long 0x0c "TCD49W3,TCD49 Word 3 Field (SLAST)" line.long 0x10 "TCD49W4,TCD49 Word 4 Field (DADDR)" line.long 0x14 "TCD49W5,TCD49 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD49W6,TCD49 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD49W7,TCD49 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15640++0x01f "Transfer Control Descriptor Register 50" line.long 0x00 "TCD50W0,TCD50 Word 0 Field (SADDR)" line.long 0x04 "TCD50W1,TCD50 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD50W2,TCD50 Word 2 Field (NBYTES)" line.long 0x0c "TCD50W3,TCD50 Word 3 Field (SLAST)" line.long 0x10 "TCD50W4,TCD50 Word 4 Field (DADDR)" line.long 0x14 "TCD50W5,TCD50 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD50W6,TCD50 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD50W7,TCD50 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15660++0x01f "Transfer Control Descriptor Register 51" line.long 0x00 "TCD51W0,TCD51 Word 0 Field (SADDR)" line.long 0x04 "TCD51W1,TCD51 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD51W2,TCD51 Word 2 Field (NBYTES)" line.long 0x0c "TCD51W3,TCD51 Word 3 Field (SLAST)" line.long 0x10 "TCD51W4,TCD51 Word 4 Field (DADDR)" line.long 0x14 "TCD51W5,TCD51 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD51W6,TCD51 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD51W7,TCD51 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15680++0x01f "Transfer Control Descriptor Register 52" line.long 0x00 "TCD52W0,TCD52 Word 0 Field (SADDR)" line.long 0x04 "TCD52W1,TCD52 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD52W2,TCD52 Word 2 Field (NBYTES)" line.long 0x0c "TCD52W3,TCD52 Word 3 Field (SLAST)" line.long 0x10 "TCD52W4,TCD52 Word 4 Field (DADDR)" line.long 0x14 "TCD52W5,TCD52 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD52W6,TCD52 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD52W7,TCD52 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x156A0++0x01f "Transfer Control Descriptor Register 53" line.long 0x00 "TCD53W0,TCD53 Word 0 Field (SADDR)" line.long 0x04 "TCD53W1,TCD53 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD53W2,TCD53 Word 2 Field (NBYTES)" line.long 0x0c "TCD53W3,TCD53 Word 3 Field (SLAST)" line.long 0x10 "TCD53W4,TCD53 Word 4 Field (DADDR)" line.long 0x14 "TCD53W5,TCD53 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD53W6,TCD53 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD53W7,TCD53 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x156C0++0x01f "Transfer Control Descriptor Register 54" line.long 0x00 "TCD54W0,TCD54 Word 0 Field (SADDR)" line.long 0x04 "TCD54W1,TCD54 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD54W2,TCD54 Word 2 Field (NBYTES)" line.long 0x0c "TCD54W3,TCD54 Word 3 Field (SLAST)" line.long 0x10 "TCD54W4,TCD54 Word 4 Field (DADDR)" line.long 0x14 "TCD54W5,TCD54 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD54W6,TCD54 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD54W7,TCD54 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x156E0++0x01f "Transfer Control Descriptor Register 55" line.long 0x00 "TCD55W0,TCD55 Word 0 Field (SADDR)" line.long 0x04 "TCD55W1,TCD55 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD55W2,TCD55 Word 2 Field (NBYTES)" line.long 0x0c "TCD55W3,TCD55 Word 3 Field (SLAST)" line.long 0x10 "TCD55W4,TCD55 Word 4 Field (DADDR)" line.long 0x14 "TCD55W5,TCD55 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD55W6,TCD55 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD55W7,TCD55 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15700++0x01f "Transfer Control Descriptor Register 56" line.long 0x00 "TCD56W0,TCD56 Word 0 Field (SADDR)" line.long 0x04 "TCD56W1,TCD56 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD56W2,TCD56 Word 2 Field (NBYTES)" line.long 0x0c "TCD56W3,TCD56 Word 3 Field (SLAST)" line.long 0x10 "TCD56W4,TCD56 Word 4 Field (DADDR)" line.long 0x14 "TCD56W5,TCD56 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD56W6,TCD56 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD56W7,TCD56 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15720++0x01f "Transfer Control Descriptor Register 57" line.long 0x00 "TCD57W0,TCD57 Word 0 Field (SADDR)" line.long 0x04 "TCD57W1,TCD57 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD57W2,TCD57 Word 2 Field (NBYTES)" line.long 0x0c "TCD57W3,TCD57 Word 3 Field (SLAST)" line.long 0x10 "TCD57W4,TCD57 Word 4 Field (DADDR)" line.long 0x14 "TCD57W5,TCD57 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD57W6,TCD57 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD57W7,TCD57 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15740++0x01f "Transfer Control Descriptor Register 58" line.long 0x00 "TCD58W0,TCD58 Word 0 Field (SADDR)" line.long 0x04 "TCD58W1,TCD58 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD58W2,TCD58 Word 2 Field (NBYTES)" line.long 0x0c "TCD58W3,TCD58 Word 3 Field (SLAST)" line.long 0x10 "TCD58W4,TCD58 Word 4 Field (DADDR)" line.long 0x14 "TCD58W5,TCD58 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD58W6,TCD58 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD58W7,TCD58 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15760++0x01f "Transfer Control Descriptor Register 59" line.long 0x00 "TCD59W0,TCD59 Word 0 Field (SADDR)" line.long 0x04 "TCD59W1,TCD59 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD59W2,TCD59 Word 2 Field (NBYTES)" line.long 0x0c "TCD59W3,TCD59 Word 3 Field (SLAST)" line.long 0x10 "TCD59W4,TCD59 Word 4 Field (DADDR)" line.long 0x14 "TCD59W5,TCD59 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD59W6,TCD59 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD59W7,TCD59 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x15780++0x01f "Transfer Control Descriptor Register 60" line.long 0x00 "TCD60W0,TCD60 Word 0 Field (SADDR)" line.long 0x04 "TCD60W1,TCD60 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD60W2,TCD60 Word 2 Field (NBYTES)" line.long 0x0c "TCD60W3,TCD60 Word 3 Field (SLAST)" line.long 0x10 "TCD60W4,TCD60 Word 4 Field (DADDR)" line.long 0x14 "TCD60W5,TCD60 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD60W6,TCD60 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD60W7,TCD60 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x157A0++0x01f "Transfer Control Descriptor Register 61" line.long 0x00 "TCD61W0,TCD61 Word 0 Field (SADDR)" line.long 0x04 "TCD61W1,TCD61 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD61W2,TCD61 Word 2 Field (NBYTES)" line.long 0x0c "TCD61W3,TCD61 Word 3 Field (SLAST)" line.long 0x10 "TCD61W4,TCD61 Word 4 Field (DADDR)" line.long 0x14 "TCD61W5,TCD61 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD61W6,TCD61 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD61W7,TCD61 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x157C0++0x01f "Transfer Control Descriptor Register 62" line.long 0x00 "TCD62W0,TCD62 Word 0 Field (SADDR)" line.long 0x04 "TCD62W1,TCD62 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD62W2,TCD62 Word 2 Field (NBYTES)" line.long 0x0c "TCD62W3,TCD62 Word 3 Field (SLAST)" line.long 0x10 "TCD62W4,TCD62 Word 4 Field (DADDR)" line.long 0x14 "TCD62W5,TCD62 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD62W6,TCD62 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD62W7,TCD62 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" group.long 0x157E0++0x01f "Transfer Control Descriptor Register 63" line.long 0x00 "TCD63W0,TCD63 Word 0 Field (SADDR)" line.long 0x04 "TCD63W1,TCD63 Word 1 Field" bitfld.long 0x04 27.--31. " SMOD[4:0] ,Source Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " SSIZE[2:0] ,Source Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " bitfld.long 0x04 19.--23. " DMOD[4:0] ,Destination Address Modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--18. " DSIZE[2:0] ,Destination Data Transfer Size" "8-bit,16-bit,32-bit,Reserved,16-bit,32-bit,Reserved,Reserved" textline " " hexmask.long.word 0x04 0.--15. 1. " SOFF[15:0] ,Source Address Signed Offset" line.long 0x08 "TCD63W2,TCD63 Word 2 Field (NBYTES)" line.long 0x0c "TCD63W3,TCD63 Word 3 Field (SLAST)" line.long 0x10 "TCD63W4,TCD63 Word 4 Field (DADDR)" line.long 0x14 "TCD63W5,TCD63 Word 5 Field" bitfld.long 0x14 31. " CITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x14 25.--30. 1. " CITER[14:9] ,Current Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x14 16.--24. 1. " CITER[8:0] ,Current Major Iteration Count" hexmask.long.word 0x14 0.--15. 1. " DOFF[15:0] ,Destination Address Signed Offset" line.long 0x18 "TCD63W6,TCD63 Word 6 Field (DLAST_SGA)" line.long 0x1c "TCD63W7,TCD63 Word 7 Field" bitfld.long 0x1c 31. " BITER.E_LINK ,Enable Channel-to-Channel Linking on Minor Loop Complete" "Disabled,Enabled" hexmask.long.byte 0x1c 25.--30. 1. " BITER[14:9] ,Beginning Major Iteration Count/Link Channel Number" textline " " hexmask.long.word 0x1c 16.--24. 1. " BITER[8:0] ,Beginning Major Iteration Count" bitfld.long 0x1c 14.--15. " BWC[1:0] ,Bandwidth Control" "No DMA_ENGINE,Priority elevation,4 cycles,8 cycles" textline " " hexmask.long.byte 0x1c 8.--13. 1. " MAJOR.LINKCH[5:0] ,Link Channel Number" bitfld.long 0x1c 7. " DONE ,Channel Done" "Not completed,Completed" textline " " bitfld.long 0x1c 6. " ACTIVE ,Channel Active" "Completed/Error,Activated" bitfld.long 0x1c 5. " MAJOR.E_LINK ,Enable channel-to-channel Linking on Major Loop Complete" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " E_SG ,Enable Scatter/Gather Processing" "Normal,Scatter/gather" bitfld.long 0x1c 3. " D_REQ ,Disable Request" "Not affected,Cleared" textline " " bitfld.long 0x1c 2. " INT_HALF ,Enable an Interrupt When Major Counter is Half Complete" "Disabled,Enabled" bitfld.long 0x1c 1. " INT_MAJ ,Enable an Interrupt When Major Iteration Count Completes" "Disabled,Enabled" textline " " bitfld.long 0x1c 0. " START ,Channel Start" "Not explicitly started,Explicitly started" tree.end width 0xb tree.end tree "DIU (Display Interface Unit IMMRBAR + 0x2100)" width 0xe group.long 0x2100++0x73 line.long 0x00 "DESC_1,Plane 1 Area Descriptor Pointer Register" line.long 0x04 "DESC_2,Plane 2 Area Descriptor Pointer Register" line.long 0x08 "DESC_3,Plane 3 Area Descriptor Pointer Register" line.long 0x0c "GAMMA,GAMMA Register" line.long 0x10 "PALETTE,PALETTE Register" line.long 0x14 "CURSOR,CURSOR Register" line.long 0x18 "CURS_POS,CURS_POS Register" hexmask.long.word 0x18 16.--26. 1. " CURSOR_Y[11:0] ,Vertical Position of the Cursor" hexmask.long.word 0x18 0.--10. 1. " CURSOR_X[11:0] ,Horizontal Position of the Cursor" line.long 0x1c "DIU_MODE,DIU_MODE Register" bitfld.long 0x1c 0.--2. " DIU_MODE ,DIU Operation Mode" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Reserved,Reserved,Reserved" line.long 0x20 "BGND,BGND Register" hexmask.long.byte 0x20 16.--23. 1. " BGND_R ,Default Background Color for Plane One" hexmask.long.byte 0x20 8.--15. 1. " BGND_G ,Default Background Color for Plane One" textline " " hexmask.long.byte 0x20 0.--7. 1. " BGND_B ,Default Background Color for Plane One" line.long 0x24 "BGND_WB,BGND_WB Register" hexmask.long.byte 0x24 16.--23. 1. " BGND_WB_R ,Default Background Color for Write Back Planes" hexmask.long.byte 0x24 8.--15. 1. " BGND_WB_G ,Default Background Color for Write Back Planes" textline " " hexmask.long.byte 0x24 0.--7. 1. " BGND_WB_B ,Default Background Color for Write Back Planes" line.long 0x28 "DISP_SIZE,DISP_SIZE Register" hexmask.long.word 0x28 16.--26. 1. " DELTA_Y[11:0] ,Vertical Resolution for Display Size" hexmask.long.word 0x28 0.--10. 1. " DELTA_X[11:0] ,Horizontal Resolution for Display Size" line.long 0x2c "WB_SIZE,WB_SIZE Register" hexmask.long.word 0x2c 16.--26. 1. " DELTA_Y_WB[11:0] ,Vertical Resolution for The Write Back Frame Size" hexmask.long.word 0x2c 0.--10. 1. " DELTA_X_WB[11:0] ,Horizontal Resolution for The Write Back Frame Size" line.long 0x30 "WB_MEM_ADDR,WB_MEM_ADDR Register" line.long 0x34 "HSYN_PARA,HSYN_PARA Register" hexmask.long.word 0x34 22.--31. 1. " BP_H ,HSYNC Back-Porch Pulse Width" hexmask.long.word 0x34 11.--20. 1. " PW_H ,HSYNC Active Pulse Width" textline " " hexmask.long.word 0x34 0.--9. 1. " FP_H ,HSYNC Front-Porch Pulse Width" line.long 0x38 "VSYN_PARA,VSYN_PARA Register" hexmask.long.word 0x38 22.--31. 1. " BP_V ,VSYNC Back-Porch Pulse Width" hexmask.long.word 0x38 11.--20. 1. " PW_V ,VSYNC Active Pulse Width" textline " " hexmask.long.word 0x38 0.--9. 1. " FP_V ,VSYNC Front-Porch Pulse Width" line.long 0x3c "SYN_POL,SYN_POL Register" bitfld.long 0x3c 4. " BP_VS ,Bypass Vertical Synchronize Signal" "Not bypass,Bypass" bitfld.long 0x3c 3. " BP_HS ,Bypass Horizontal Synchronize Signal" "Not bypass,Bypass" textline " " bitfld.long 0x3c 2. " INV_CS ,Invert Composite Synchronize Signal" "Not inverted/High,Inverted/Low" bitfld.long 0x3c 1. " INV_VS ,Invert Vertical Synchronize Signal" "Not inverted/High,Inverted/Low" textline " " bitfld.long 0x3c 0. " INV_HS ,Invert Horizontal Synchronize Signal" "Not inverted/High,Inverted/Low" line.long 0x40 "THRESHOLDS,THRESHOLDS Register" hexmask.long.word 0x40 16.--26. 1. " LS_BF_VS ,Lines Before Vsync Threshold" hexmask.long.byte 0x40 0.--7. 1. " OUT_BUF_LOW ,Output Buffer Filling Low Threshold" line.long 0x44 "INT_STATUS,INT_STATUS Register" bitfld.long 0x44 5. " WB_PEND ,Write Back Pending Interrupt" "No interrupt,Interrupt" bitfld.long 0x44 4. " LS_BF_VS ,Lines Before Vsync Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x44 3. " PARERR ,Display Parameters Error Interrupt" "No interrupt,Interrupt" bitfld.long 0x44 2. " UNDRUN ,Under Run Exception Interrupt" "Not asserted,Asserted" textline " " bitfld.long 0x44 1. " VSYNC_WB ,Vertical Synchronize Interrupt" "No interrupt,Interrupt" bitfld.long 0x44 0. " VSYNC ,Vertical Synchronize Interrupt" "No interrupt,Interrupt" line.long 0x48 "INT_MASK,INT_MASK Register" bitfld.long 0x48 5. " M_WB_PEND ,Write Back Pending Interrupt" "Enabled,Disabled" bitfld.long 0x48 4. " M_LS_BF_VS ,Lines Before Vsync Interrupt Enable" "Enabled,Disabled" textline " " bitfld.long 0x48 3. " M_PARERR ,Display Parameters Error Interrupt Enable" "Enabled,Disabled" bitfld.long 0x48 2. " M_UNDRUN ,Under Run Exception Interrupt Enable" "Enabled,Disabled" textline " " bitfld.long 0x48 1. " M_VSYNC_WB ,Vertical Synchronize Interrupt Enable" "Enabled,Disabled" bitfld.long 0x48 0. " M_VSYNC ,Vertical Synchronize Interrupt Enable" "Enabled,Disabled" width 14. line.long 0x4c "COLORBAR_1,COLORBAR_1 Register" hexmask.long.byte 0x4c 16.--23. 1. " COLBAR_1_R ,Generates Color Bar" hexmask.long.byte 0x4c 8.--15. 1. " COLBAR_1_G ,Generates Color Bar" hexmask.long.byte 0x4c 0.--7. 1. " COLBAR_1_B ,Generates Color Bar" line.long 0x50 "COLORBAR_2,COLORBAR_2 Register" hexmask.long.byte 0x50 16.--23. 1. " COLBAR_2_R ,Generates Color Bar" hexmask.long.byte 0x50 8.--15. 1. " COLBAR_2_G ,Generates Color Bar" hexmask.long.byte 0x50 0.--7. 1. " COLBAR_2_B ,Generates Color Bar" line.long 0x54 "COLORBAR_3,COLORBAR_3 Register" hexmask.long.byte 0x54 16.--23. 1. " COLBAR_3_R ,Generates Color Bar" hexmask.long.byte 0x54 8.--15. 1. " COLBAR_3_G ,Generates Color Bar" hexmask.long.byte 0x54 0.--7. 1. " COLBAR_3_B ,Generates Color Bar" line.long 0x58 "COLORBAR_4,COLORBAR_4 Register" hexmask.long.byte 0x58 16.--23. 1. " COLBAR_4_R ,Generates Color Bar" hexmask.long.byte 0x58 8.--15. 1. " COLBAR_4_G ,Generates Color Bar" hexmask.long.byte 0x58 0.--7. 1. " COLBAR_4_B ,Generates Color Bar" line.long 0x5c "COLORBAR_5,COLORBAR_5 Register" hexmask.long.byte 0x5c 16.--23. 1. " COLBAR_5_R ,Generates Color Bar" hexmask.long.byte 0x5c 8.--15. 1. " COLBAR_5_G ,Generates Color Bar" hexmask.long.byte 0x5c 0.--7. 1. " COLBAR_5_B ,Generates Color Bar" line.long 0x60 "COLORBAR_6,COLORBAR_6 Register" hexmask.long.byte 0x60 16.--23. 1. " COLBAR_6_R ,Generates Color Bar" hexmask.long.byte 0x60 8.--15. 1. " COLBAR_6_G ,Generates Color Bar" hexmask.long.byte 0x60 0.--7. 1. " COLBAR_6_B ,Generates Color Bar" line.long 0x64 "COLORBAR_7,COLORBAR_7 Register" hexmask.long.byte 0x64 16.--23. 1. " COLBAR_7_R ,Generates Color Bar" hexmask.long.byte 0x64 8.--15. 1. " COLBAR_7_G ,Generates Color Bar" hexmask.long.byte 0x64 0.--7. 1. " COLBAR_7_B ,Generates Color Bar" line.long 0x68 "COLORBAR_8,COLORBAR_8 Register" hexmask.long.byte 0x68 16.--23. 1. " COLBAR_8_R ,Generates Color Bar" hexmask.long.byte 0x68 8.--15. 1. " COLBAR_8_G ,Generates Color Bar" hexmask.long.byte 0x68 0.--7. 1. " COLBAR_8_B ,Generates Color Bar" line.long 0x6c "FILLING,FILLING Register" hexmask.long.word 0x6c 16.--25. 1. " FILLING_OBF ,Filling Status of the Output Buffer" bitfld.long 0x6c 12.--15. " FILLING_WB ,Filling Status of the Write Back Pixel Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6c 8.--11. " FILLING_P3 ,Filling Status of Plane Three Input Pixel Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x6c 4.--7. " FILLING_P2 ,Filling Status of Plane Two Input Pixel Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6c 0.--3. " FILLING_P1 ,Filling Status of Plane One Input Pixel Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x70 "PLUT,PLUT Register" bitfld.long 0x70 28.--31. " PRIORITY_7 ,The Priority 7 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x70 24.--27. " PRIORITY_6 ,The Priority 6 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x70 20.--23. " PRIORITY_5 ,The Priority 5 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x70 16.--19. " PRIORITY_4 ,The Priority 4 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x70 12.--15. " PRIORITY_3 ,The Priority 3 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x70 8.--11. " PRIORITY_2 ,The Priority 2 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x70 4.--7. " PRIORITY_1 ,The Priority 1 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x70 0.--3. " PRIORITY_0 ,The Priority 0 Look Up Table Components" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "DRAM Controller (IMMRBAR + 0x9000)" width 21. group.long 0x9000++0x0f line.long 0x00 "DDR_SYS_CONFIG,DDR System Configuration Register" bitfld.long 0x00 31. " RST_B ,DRAM Controller Soft Reset" "Reset state,Out of reset" bitfld.long 0x00 30. " CKE ,Value on the DRAM CKE Pin" "Low,High" textline " " bitfld.long 0x00 29. " CLK_ON ,DRAM Clock Run/Stop" "Stopped,Run" bitfld.long 0x00 28. " CMD_MODE ,DRAM Controller Normal/Command Mode" "Normal,Command" textline " " bitfld.long 0x00 25.--27. " DRAM_ROW_SELECT ,The Multiplexing of the Magenta Address Control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--24. " DRAM_BANK_SELECT ,The Multiplexing of the Magenta Address Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 19.--20. " READ_TEST ,Protection Test" "0,1,2,3" bitfld.long 0x00 18. " SELFREFEN ,Self Refresh Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " 16-BIT_MODE ,DRAM Controller 16-BIT MODE Enable" "32-bit,16-bit" bitfld.long 0x00 13.--16. " RDLY[3:0] ,Delay Control" "0,1,2,3,4,5,6,7,%d..." textline " " bitfld.long 0x00 12. " HALF_DQS_DLY ,Read Delay Control" "0 CSB,1/2 CSB" bitfld.long 0x00 11. " QUART_DQS_DLY ,Read Delay Control" "0 CSB,1/4 CSB" textline " " bitfld.long 0x00 8.--10. " WDLY[2:0] ,Write Latency (WL) for Write Commands Control" "Reserved,1,2,3,4,Reserved,Reserved,Reserved" bitfld.long 0x00 7. " EARLY_ODT ,The ODT Signal Assertion Control" "Not asserted,Asserted" textline " " bitfld.long 0x00 6. " ON_DIE_TERMINATE ,On-die Termination" "Not generated,Generated" bitfld.long 0x00 5. " FIFO_OV_CLEAR ,FIFO OV Interrupt Clear" "No effect,Cleared" textline " " bitfld.long 0x00 4. " FIFO_UV_CLEAR ,FIFO UV Interrupt Clear" "No effect,Cleared" bitfld.long 0x00 3. " FIFO_OV_PEN ,FIFO OV Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 2. " FIFO_UV_PEN ,FIFO UV Interrupt Pending" "Not pending,Pending" bitfld.long 0x00 1. " FIFO_OV_EN ,FIFO OV Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FIFO_UV_EN ,FIFO UV Interrupt Enable" "Disabled,Enabled" line.long 0x04 "DDR_TIME_CONFIG0,DDR Time Config 0 Register" hexmask.long.word 0x04 16.--31. 1. " DRAM_REFRESH_TIME[15:0] ,Refresh Interval of the DRAM" hexmask.long.byte 0x04 8.--15. 1. " DRAM_COMMAND_TIME[7:0] ,Time-out After Sending a Command to the DRAM in Bypass Mode" textline " " hexmask.long.byte 0x04 0.--7. 1. " DRAM_BANK_PRE_TIME[7:0] ,Time-out" line.long 0x08 "DDR_TIME_CONFIG1,DDR Time Config 1 Register" hexmask.long.byte 0x08 26.--31. 1. " DRAM_TIME_RFC[5:0] ,REFRESH to ACTIVE or REFRESH to REFRESH Command Interval" bitfld.long 0x08 21.--25. " DRAM_TIME_WR1[4:0] ,Write Recovery Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 17.--20. " DRAM_TIME_WRT1[3:0] ,Write to Read Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 11.--16. 1. " DRAM_TIME_RRD[5:0] ,ACTIVE Bank A to ACTIVE Bank B Command" textline " " hexmask.long.byte 0x08 5.--10. 1. " DRAM_TIME_RC[5:0] ,ACTIVE to ACTIVE (Same Bank) Command" bitfld.long 0x08 0.--4. " DRAM_TIME_RAS[4:0] ,ACTIVE to PRECHARGE Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0c "DDR_TIME_CONFIG2,DDR Time Config 2 Register" bitfld.long 0x0c 28.--31. " DRAM_TIME_RCD[3:0] ,ACTIVE to READ or WRITE Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 23.--27. " DRAM_TIME_FAW[4:0] ,4-Bank Activate Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0c 19.--22. " DRAM_TIME_RTW1[3:0] ,Read to Write Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 15.--18. " DRAM_TIME_CCD[3:0] ,CAS to CAS Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0c 10.--14. " DRAM_TIME_RTP[4:0] ,Read to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 5.--9. " DRAM_TIME_RP[4:0] ,Precharge Command Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0c 0.--4. " DRAM_TIME_RPA[4:0] ,Precharge All Command Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x9010++0x03 line.long 0x00 "DDR_COMMAND,Command Register" bitfld.long 0x00 24. " CMD_REQ ,CMD Request" "Low,High" hexmask.long 0x00 0.--23. 1. " DRAM_COMMAND[23:0] ,DRAM Command" wgroup.long 0x9014++0x03 line.long 0x00 "DDR_COMPACT_COMMAND,Compact Command Register" hexmask.long.word 0x00 0.--15. 1. " DRAM_COMPACT_COMMAND[15:0] ,DRAM compact command" group.long 0x9018++0x03 line.long 0x00 "SELF_REFRESH_CMD_0,Self Refresh Command 0 Register" group.long 0x901c++0x03 line.long 0x00 "SELF_REFRESH_CMD_1,Self Refresh Command 1 Register" group.long 0x9020++0x03 line.long 0x00 "SELF_REFRESH_CMD_2,Self Refresh Command 2 Register" group.long 0x9024++0x03 line.long 0x00 "SELF_REFRESH_CMD_3,Self Refresh Command 3 Register" group.long 0x9028++0x03 line.long 0x00 "SELF_REFRESH_CMD_4,Self Refresh Command 4 Register" group.long 0x902c++0x03 line.long 0x00 "SELF_REFRESH_CMD_5,Self Refresh Command 5 Register" group.long 0x9030++0x03 line.long 0x00 "SELF_REFRESH_CMD_6,Self Refresh Command 6 Register" wgroup.long 0x9034++0x03 line.long 0x00 "SELF_REFRESH_CMD_7,Self Refresh Command 7 Register" group.long 0x9038++0x07 line.long 0x00 "DQS_CONF_OFF_CNT,DQS Config Offset Count Register" hexmask.long.byte 0x00 24.--30. 1. " DQS_SOC_3[6:0] ,Offset Counted in Elemental Gate Delay" hexmask.long.byte 0x00 16.--22. 1. " DQS_SOC_2[6:0] ,Offset Counted in Elemental Gate Delay" textline " " hexmask.long.byte 0x00 8.--14. 1. " DQS_SOC_1[6:0] ,Offset Counted in Elemental Gate Delay" hexmask.long.byte 0x00 0.--6. 1. " DQS_SOC_0[6:0] ,Offset Counted in Elemental Gate Delay" line.long 0x04 "DQS_CONF_OFF_TIM,DQS Config Offset Time Register" hexmask.long.byte 0x04 24.--28. 1. " DQS_SOT_3[4:0] ,Offset Counted in Time Units" hexmask.long.byte 0x04 16.--20. 1. " DQS_SOT_2[4:0] ,Offset Counted in Time Units" textline " " hexmask.long.byte 0x04 8.--12. 1. " DQS_SOT_1[4:0] ,Offset Counted in Time Units" hexmask.long.byte 0x04 0.--4. 1. " DQS_SOT_0[4:0] ,Offset Counted in Time Units" group.long 0x9040++0x03 line.long 0x00 "DQS_DEL_STS,DQS Delay Status" hexmask.long.word 0x00 16.--27. 1. " DQS_MC_2[12:0] ,Delay Count Output By The Controller For The First DQS Master" hexmask.long.word 0x00 0.--11. 1. " DQS_MC_1[12:0] ,Delay Count Output By The Controller For The Second DQS Master" width 0xb tree.end tree "DRAM Controller Priority Manager (IMMRBAR + 0x9000)" width 0xc group.long 0x9080++0x0b line.long 0x00 "PR_CONF1,PRIOMAN_CONFIG1 Register" bitfld.long 0x00 28.--29. " LUTSEL4[1:0] ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Reserved" bitfld.long 0x00 26.--27. " LUTSEL3[1:0] ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Reserved" textline " " bitfld.long 0x00 24.--25. " LUTSEL2[1:0] ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Reserved" bitfld.long 0x00 22.--23. " LUTSEL1[1:0] ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Reserved" textline " " bitfld.long 0x00 20.--21. " LUTSEL0[1:0] ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Reserved" bitfld.long 0x00 16.--19. " ACK_COUNT4[3:0] ,Number of ACKs For The Self-channel Counted" "1,2,3,4,6,8,12,16,24,32,48,63,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 12.--15. " ACK_COUNT3[3:0] ,Number of ACKs For The Self-channel Counted" "1,2,3,4,6,8,12,16,24,32,48,63,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 8.--11. " ACK_COUNT2[3:0] ,Number of ACKs For The Self-channel Counted" "1,2,3,4,6,8,12,16,24,32,48,63,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 4.--7. " ACK_COUNT1[3:0] ,Number of ACKs For The Self-channel Counted" "1,2,3,4,6,8,12,16,24,32,48,63,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 0.--3. " ACK_COUNT0[3:0] ,Number of ACKs For The Self-channel Counted" "1,2,3,4,6,8,12,16,24,32,48,63,Reserved,Reserved,Reserved,Reserved" line.long 0x04 "PR_CONF2,PRIOMAN_CONFIG2 Register" bitfld.long 0x04 6. " CONGESTED ,CONGESTED Flag Status" "Cleared,Set" bitfld.long 0x04 5. " DIU-OVERRULE ,DIU Priority Overrule" "Normal,From DIU" textline " " bitfld.long 0x04 4. " ACK_SEL4 ,Not Requesting Channel Status" "No overrule,Overrule" textline " " bitfld.long 0x04 3. " ACK_SEL3 ,Not Requesting Channel Status" "No overrule,Overrule" bitfld.long 0x04 2. " ACK_SEL2 ,Not Requesting Channel Status" "No overrule,Overrule" textline " " bitfld.long 0x04 1. " ACK_SEL1 ,Not Requesting Channel Status" "No overrule,Overrule" bitfld.long 0x04 0. " ACK_SEL0 ,Not Requesting Channel Status" "No overrule,Overrule" line.long 0x08 "HIPRIO_CONF,HIPRIO_CONFIG Register" hexmask.long.byte 0x08 24.--31. 1. " SET_CONG_LVL[12:4] ,Set The Congested Flag" hexmask.long.byte 0x08 16.--23. 1. " CL_CONG_LVL[12:4] ,Clear The Congested Flag" textline " " bitfld.long 0x08 13.--15. " FILTER_BANDWIDTH[2:0] ,The Averaging Time of The Filter Control" "W0=8ACKS/K=0.125,W0=16ACKS/K=0.0625,W0=32ACKS/K=0.0312,W0=64ACKS/K=0.0156,W0=128ACKS/K=0.0078,W0=256ACKS/K=0.0039,W0=512ACKS/K=0.0020,W0=1024ACKS/K=0.0010" hexmask.long.word 0x08 0.--12. 1. " AVER_HIPRIO[12:0] ,Average Number of High Priority Requests to DRAM" width 0xc textline "" group.long 0x908c++0x13 line.long 0x0 "LUT0MUR,LUT0 Main Upper Register" bitfld.long 0x0 28.--31. " PRIO15[3:0] ,Priority Setting If 15 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x4 "LUT1MUR,LUT1 Main Upper Register" bitfld.long 0x4 28.--31. " PRIO15[3:0] ,Priority Setting If 15 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x8 "LUT2MUR,LUT2 Main Upper Register" bitfld.long 0x8 28.--31. " PRIO15[3:0] ,Priority Setting If 15 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0xC "LUT3MUR,LUT3 Main Upper Register" bitfld.long 0xC 28.--31. " PRIO15[3:0] ,Priority Setting If 15 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x10 "LUT4MUR,LUT4 Main Upper Register" bitfld.long 0x10 28.--31. " PRIO15[3:0] ,Priority Setting If 15 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." group.long 0x90a0++0x13 line.long 0x0 "LUT0MLR,LUT0 Main Lower Register" bitfld.long 0x0 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x4 "LUT1MLR,LUT1 Main Lower Register" bitfld.long 0x4 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x8 "LUT2MLR,LUT2 Main Lower Register" bitfld.long 0x8 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0xC "LUT3MLR,LUT3 Main Lower Register" bitfld.long 0xC 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x10 "LUT4MLR,LUT4 Main Lower Register" bitfld.long 0x10 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." group.long 0x90b4++0x13 line.long 0x0 "LUT0AUR,LUT0 Alternate Upper Register" bitfld.long 0x0 28.--31. " PRIO15[3:0] ,Priority Setting If 15 or more ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x4 "LUT1AUR,LUT1 Alternate Upper Register" bitfld.long 0x4 28.--31. " PRIO15[3:0] ,Priority Setting If 15 or more ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x8 "LUT2AUR,LUT2 Alternate Upper Register" bitfld.long 0x8 28.--31. " PRIO15[3:0] ,Priority Setting If 15 or more ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0xC "LUT3AUR,LUT3 Alternate Upper Register" bitfld.long 0xC 28.--31. " PRIO15[3:0] ,Priority Setting If 15 or more ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x10 "LUT4AUR,LUT4 Alternate Upper Register" bitfld.long 0x10 28.--31. " PRIO15[3:0] ,Priority Setting If 15 or more ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 24.--27. " PRIO14[3:0] ,Priority Setting If 14 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 20.--23. " PRIO13[3:0] ,Priority Setting If 13 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 16.--19. " PRIO12[3:0] ,Priority Setting If 12 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 12.--15. " PRIO11[3:0] ,Priority Setting If 11 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 8.--11. " PRIO10[3:0] ,Priority Setting If 10 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 4.--7. " PRIO9[3:0] ,Priority Setting If 9 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 0.--3. " PRIO8[3:0] ,Priority Setting If 8 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." group.long 0x90c8++0x13 line.long 0x0 "LUT0ALR,LUT0 Alternate Lower Register" bitfld.long 0x0 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x0 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x0 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x4 "LUT1ALR,LUT1 Alternate Lower Register" bitfld.long 0x4 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x4 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x4 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x8 "LUT2ALR,LUT2 Alternate Lower Register" bitfld.long 0x8 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x8 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x8 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0xC "LUT3ALR,LUT3 Alternate Lower Register" bitfld.long 0xC 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0xC 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0xC 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." line.long 0x10 "LUT4ALR,LUT4 Alternate Lower Register" bitfld.long 0x10 28.--31. " PRIO7[3:0] ,Priority Setting If 7 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 24.--27. " PRIO6[3:0] ,Priority Setting If 6 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 20.--23. " PRIO5[3:0] ,Priority Setting If 5 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 16.--19. " PRIO4[3:0] ,Priority Setting If 4 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 12.--15. " PRIO3[3:0] ,Priority Setting If 3 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 8.--11. " PRIO2[3:0] ,Priority Setting If 2 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." textline " " bitfld.long 0x10 4.--7. " PRIO1[3:0] ,Priority Setting If 1 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." bitfld.long 0x10 0.--3. " PRIO0[3:0] ,Priority Setting If 0 ACKs For Own Channel Counted" "Lowest,1,2,Highest,?..." width 0xc group.long 0x90dc++0x1b line.long 0x00 "PER_CONF,PERMON_CONFIG Register" bitfld.long 0x00 31. " INT ,Interrupt Pending" "Not pending,Pending" bitfld.long 0x00 30. " INTCLEAR ,INT Bit Status" "No effect,Cleared" textline " " bitfld.long 0x00 29. " INTEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAREQ ,DMA Request" "No request,Request" textline " " bitfld.long 0x00 27. " DMAREQSTOP ,DMA Request Functions Status" "Expected,Cleared" bitfld.long 0x00 26. " EVENTCOUNTFREERUN ,Event Counter Mode" "Single-shot,Free run" textline " " bitfld.long 0x00 25. " EVENTCOUNTTRIGGER ,Count Registers to Buffer Registers Transformation" "Not occurred,Occurred" bitfld.long 0x00 8.--9. " LUT_SEL4 ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Alternate" textline " " bitfld.long 0x00 6.--7. " LUT_SEL3 ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Alternate" bitfld.long 0x00 4.--5. " LUT_SEL2 ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Alternate" textline " " bitfld.long 0x00 2.--3. " LUT_SEL1 ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Alternate" bitfld.long 0x00 0.--1. " LUT_SEL0 ,Primary/Secondary Look-Up Table Configuration Register Selection" "Main,Alternate,Alternate,Alternate" width 0xc line.long 0x04 "ETCR,Event Time Counter Register" hexmask.long 0x04 0.--23. 1. " EVENT_TIME_COUNT[23:0] ,Counter Value" line.long 0x08 "ETPR,Event Time Preset Register" hexmask.long 0x08 0.--23. 1. " EVENT_TIME_PRESET[23:0] ,Present Value" line.long 0x0c "PM1ALR,Performance Monitor 1 Address Low Register" hexmask.long 0x0c 5.--31. 0x20 " PER_MON1_ADDR[31:5] ,Performance Monitor 1 Address Low" line.long 0x10 "PM2ALR,Performance Monitor 2 Address Low Register" hexmask.long 0x10 5.--31. 0x20 " PER_MON2_ADDR[31:5] ,Performance Monitor 2 Address Low" line.long 0x14 "PM1AHR,Performance Monitor 1 Address High Register" hexmask.long 0x14 5.--31. 0x20 " PER_MON1_ADDR[31:5] ,Performance Monitor 1 Address High" line.long 0x18 "PM2AHR,Performance Monitor 2 Address High Register" hexmask.long 0x18 5.--31. 0x20 " PER_MON2_ADDR[31:5] ,Performance Monitor 2 Address High" rgroup.long 0x9100++0x0f line.long 0x00 "PM1RC,Performance Monitor 1 Read Counter" hexmask.long 0x00 0.--23. 1. " PER_MON1_READ_COUNT[15:0] ,Performance Monitor 1 Read Counter" line.long 0x04 "PM2RC,Performance Monitor 2 Read Counter" hexmask.long 0x04 0.--23. 1. " PER_MON2_READ_COUNT[15:0] ,Performance Monitor 2 Read Counter" line.long 0x08 "PM1WC,Performance Monitor 1 Write Counter" hexmask.long 0x08 0.--23. 1. " PER_MON1_WRITE_COUNT[15:0] ,Performance Monitor 1 Write Counter" line.long 0x0c "PM2WC,Performance Monitor 2 Write Counter" hexmask.long 0x0c 0.--23. 1. " PER_MON2_WRITE_COUNT[15:0] ,Performance Monitor 2 Write Counter" rgroup.long 0x9110++0x13 line.long 0x0 "GACKC0,Granted Ack Counter 0" hexmask.long 0x0 0.--23. 1. " GRANT_ACK_COUNT0[23:16] ,Granted ACK Counter 0 Value" line.long 0x4 "GACKC1,Granted Ack Counter 1" hexmask.long 0x4 0.--23. 1. " GRANT_ACK_COUNT1[23:16] ,Granted ACK Counter 1 Value" line.long 0x8 "GACKC2,Granted Ack Counter 2" hexmask.long 0x8 0.--23. 1. " GRANT_ACK_COUNT2[23:16] ,Granted ACK Counter 2 Value" line.long 0xC "GACKC3,Granted Ack Counter 3" hexmask.long 0xC 0.--23. 1. " GRANT_ACK_COUNT3[23:16] ,Granted ACK Counter 3 Value" line.long 0x10 "GACKC4,Granted Ack Counter 4" hexmask.long 0x10 0.--23. 1. " GRANT_ACK_COUNT4[23:16] ,Granted ACK Counter 4 Value" rgroup.long 0x9124++0x13 line.long 0x0 "CWC0,Cumulative Wait Counter 0" hexmask.long 0x0 0.--23. 1. " CUMUL_WAIT_COUNT0[15:0] ,Cumulative Wait Counter 0 Value" line.long 0x4 "CWC1,Cumulative Wait Counter 1" hexmask.long 0x4 0.--23. 1. " CUMUL_WAIT_COUNT1[15:0] ,Cumulative Wait Counter 1 Value" line.long 0x8 "CWC2,Cumulative Wait Counter 2" hexmask.long 0x8 0.--23. 1. " CUMUL_WAIT_COUNT2[15:0] ,Cumulative Wait Counter 2 Value" line.long 0xC "CWC3,Cumulative Wait Counter 3" hexmask.long 0xC 0.--23. 1. " CUMUL_WAIT_COUNT3[15:0] ,Cumulative Wait Counter 3 Value" line.long 0x10 "CWC4,Cumulative Wait Counter 4" hexmask.long 0x10 0.--23. 1. " CUMUL_WAIT_COUNT4[15:0] ,Cumulative Wait Counter 4 Value" rgroup.long 0x9138++0x13 line.long 0x0 "SPC0,Summed Priority Counter 0" hexmask.long 0x0 0.--23. 1. " SUM_PRIO_COUNT0[15:0] ,Summed Priority Counter 0 Value" line.long 0x4 "SPC1,Summed Priority Counter 1" hexmask.long 0x4 0.--23. 1. " SUM_PRIO_COUNT1[15:0] ,Summed Priority Counter 1 Value" line.long 0x8 "SPC2,Summed Priority Counter 2" hexmask.long 0x8 0.--23. 1. " SUM_PRIO_COUNT2[15:0] ,Summed Priority Counter 2 Value" line.long 0xC "SPC3,Summed Priority Counter 3" hexmask.long 0xC 0.--23. 1. " SUM_PRIO_COUNT3[15:0] ,Summed Priority Counter 3 Value" line.long 0x10 "SPC4,Summed Priority Counter 4" hexmask.long 0x10 0.--23. 1. " SUM_PRIO_COUNT4[15:0] ,Summed Priority Counter 4 Value" tree.end tree "FEC (Fast Ethernet Controller IMMRBAR + 0x2800)" width 0xe if (data.long(ANC:iobase()+0xf04)&0x00002000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else rgroup.long 0x2800++0x0b line.long 0x0 "FEC_ID,FEC ID Register" hexmask.long.word 0x0 16.--31. 1. " FEC_ID ,Unique identifier for FEC" bitfld.long 0x0 10. " DMA ,DMA function included in the FEC" "Not included,Included" textline " " bitfld.long 0x0 9. " FIFO ,FIFO function included in the FEC" "Not included,Included" bitfld.long 0x00 8. " SMII ,The Ethernet PHY interface configuration" "MII/7-wire,SMII" textline " " hexmask.long.byte 0x0 0.--7. 1. " FEC_REV ,Value identifies the FEC revision" group.long 0x2804++0x07 line.long 0x00 "IEVENT,FEC Interrupt Event Register" eventfld.long 0x00 31. " HBERR ,Heartbeat Error" "No error,Error" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "No error,Error" textline " " eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "Pending,Paused" textline " " eventfld.long 0x00 27. " TFINT ,Transmit frame interrupt" "Not updated,Updated" eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "Not updated,Updated" textline " " eventfld.long 0x00 25. " RFINT ,Receive frame interrupt" "Not updated,Updated" eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "Not updated,Updated" textline " " eventfld.long 0x00 23. " MII ,MII Interrupt" "Disabled,Enabled" eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" textline " " eventfld.long 0x00 21. " LATE_COL ,Late Collision occurred" "Not occurred,Occurred" eventfld.long 0x00 20. " COL_RETRY_LIM ,Collision Retry Limit" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " XFIFO_UN ,Transmit FIFO Underrun Error" "No error,Error" line.long 0x04 "IMASK,Interrupt Mask Register" bitfld.long 0x04 31. " HBEEN ,Heartbeat Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 30. " BREN ,Babbling Receiver Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " BTEN ,Babbling Transmitter Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 28. " GRAEN ,Graceful Stop Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " TFIEN ,Transmit Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBIEN ,Transmit Buffer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " RFIEN ,Receive Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 24. " RBIEN ,Receive Buffer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " MIIEN ,MII Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 22. " EBERREN ,Ethernet Controller Bus Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " LCEN ,Late Collision Enable" "Disabled,Enabled" bitfld.long 0x04 20. " CRLEN ,Collision Retry Limit Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " XFUNEN ,Transmit FIFO Underrun Enable" "Disabled,Enabled" rgroup.long 0x2810++0x07 line.long 0x0 "R_DES_ACTIVE, CSR Receive Descriptor Active Register" bitfld.long 0x0 24. " R_DES_ACTIVE ,Rx Descriptor Active" "Inactive,Active" line.long 0x4 "X_DES_ACTIVE, CSR Transmit Descriptor Active Register" bitfld.long 0x4 24. " X_DES_ACTIVE ,Tx Descriptor Active" "Inactive,Active" group.long 0x2824++0x3 line.long 0x0 "ECNTRL,FEC Ethernet Control Register" bitfld.long 0x0 1. " ETHER_EN ,Ethernet Enable" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Ethernet Controller Reset" "No reset,Reset" group.long 0x2840++0x7 line.long 0x0 "MII_DATA,MII Management Frame Register" bitfld.long 0x0 30.--31. " ST ,Start of Frame Delimiter" "Not valid,Valid,Not valid,Not valid" bitfld.long 0x0 28.--29. " OP ,Operation Code" "00,01,10,11" textline " " hexmask.long.byte 0x0 23.--27. 1. " PA ,PHY Address" hexmask.long.byte 0x0 18.--22. 1. " RA ,Register Address" textline " " bitfld.long 0x0 16.--17. " TA ,TurnAround" "Not valid,Not valid,Valid,Not valid" hexmask.long.word 0x0 0.--15. 1. " DATA ,Management Frame Data" line.long 0x04 "MII_SPEED,MII Speed Control Register" bitfld.long 0x04 7. " DIS_PREAMBLE ,Preamble (32 ones) not prepended to the MII management frame" "False,True" hexmask.long.byte 0x04 1.--6. 1. " MII_SPEED ,Frequency of the MII management interface clock" group.long 0x2864++0x3 line.long 0x0 "MIB_CONTROL,MIB Control Register" bitfld.long 0x0 31. " MIB_DISABLE ,A read/write control bit" "Enabled,Disabled" bitfld.long 0x0 30. " MIB_IDLE ,A read-only status bit" "Busy,Idle" group.long 0x2884++0x3 line.long 0x0 "R_CNTRL,Receive Control Register" hexmask.long.word 0x0 16.--26. 1. " MAX_FL ,Maximum Frame Length" bitfld.long 0x0 5. " FCE ,Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x0 3. " PROM ,Promiscuous mode" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " MII_MODE ,Selects external interface mode" "7 wire,MII" bitfld.long 0x0 1. " DRT ,Disable Receive on Transmit" "Enabled,Disabled" textline " " bitfld.long 0x0 0. " LOOP ,Internal Loopback" "Disabled,Enabled" rgroup.long 0x2888++0x3 line.long 0x0 "R_HASH,FEC HASH Register" bitfld.long 0x0 31. " FCE_DC ,Read-only view of the R_CNTRL register FCE bit" "Disabled,Enabled" bitfld.long 0x0 30. " MULTICAST ,Current Rx frame contained a multi-cast destination address" "Other,Multicast" textline " " hexmask.long.byte 0x0 24.--29. 1. " HASH ,Corresponds to hash value of current Rx frame's destination address" group.long 0x28c4++0x3 line.long 0x0 "X_CNTRL,Transmit Control Register" bitfld.long 0x0 4. " RFC_PAUSE ,Full duplex flow control pause frame is received" "Pending,Paused" bitfld.long 0x0 3. " TFC_PAUSE ,Transmit a PAUSE frame." "Pending,Paused" textline " " bitfld.long 0x0 2. " FDEN ,Full Duplex Enable." "Disabled,Enabled" bitfld.long 0x0 1. " HBC ,Heartbeat Control" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " GTS ,Graceful Transmit Stop" "Disabled,Enabled" group.long 0x28e4++0xb line.long 0x0 "PADDR1,FEC Physical Address Low" line.long 0x04 "PADDR2,FEC Physical Address High" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Last 2Bytes of the 6-byte individual address in PAUSE frames" hexmask.long.word 0x04 0.--15. 1. " TYPE ,16bit constant value, hex 8808" line.long 0x8 "OP_PAUSE,FEC Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field used in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames" group.long 0x2918++0xf line.long 0x00 "IADDR1,FEC Descriptor Individual Address 1" line.long 0x04 "IADDR2,FEC Descriptor Individual Address 2" line.long 0x08 "GADDR1,FEC Descriptor Group Address 1" line.long 0x0c "GADDR2,FEC Descriptor Group Address 2" group.long 0x2944++0x03 line.long 0x00 "X_WMRK,FIFO Transmit FIFO Watermark" bitfld.long 0x00 0.--1. " X_WMRK ,Transmit FIFO Watermark" "64 Bytes,64 Bytes,128 Bytes,192 Bytes" rgroup.long 0x294c++0x03 line.long 0x00 "R_BOUND,FIFO Receive Bound Register" hexmask.long.byte 0x00 2.--9. 1. " R_BOUND ,Highest valid FIFO RAM address" group.long 0x2950++0x03 line.long 0x00 "R_FSTART,FIFO Receive Start Register" hexmask.long.byte 0x00 2.--9. 1. " R_FSTART ,Address of the first receive FIFO location" group.long 0x2980++0x0b line.long 0x00 "R_DES_START,Beginning of Receive Descriptor Ring" hexmask.long 0x00 2.--31. 0x4 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "X_DES_START,Beginning of Transmit Descriptor Ring" hexmask.long 0x04 2.--31. 0x4 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "R_BUFF_SIZE,Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,The receive buffer size" group.long 0x29f4++0x03 line.long 0x00 "DMA_CONTROL,DMA Function Code Register" bitfld.long 0x00 31. " DATA_BO ,The byte order control for data DMA transfers" "Little endian,Big endian" bitfld.long 0x00 30. " DESC_BO ,The byte order control for descriptor DMA transfers" "Little endian,Big endian" textline " " hexmask.long.byte 0x00 0.--7. 1. " DMA_REV ,DMA revision" width 20. endif tree "MIB Block Counters" if (data.long(ANC:iobase()+0xf04)&0x00002000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x2a00++0x077 line.long 0x000 "RMON_T_DROP,FEC Count of Frames Not Counted Correctly" line.long 0x004 "RMON_T_PACKETS,FEC RMON Tx Packet Count" line.long 0x008 "RMON_T_BC_PKT,FEC RMON Tx Broadcast Packets" line.long 0x00C "RMON_T_MC_PKT,FEC RMON Tx Multicast Packets" line.long 0x010 "RMON_T_CRC_ALIGN,FEC RMON Tx Packets W CRC/Align Error" line.long 0x014 "RMON_T_UNDERSIZE,FEC RMON Tx Packets < 64 Bytes Good CRC" line.long 0x018 "RMON_T_OVERSIZE,FEC RMON Tx Packets > MAX_FL Bytes Good CRC" line.long 0x01C "RMON_T_FRAG,FEC RMON Tx Packets < 64 Bytes Bad CRC" line.long 0x020 "RMON_T_JAB,FEC RMON Tx Packets > MAX_FL Bytes Bad CRC" line.long 0x024 "RMON_T_COL,FEC RMON Tx Collision Count" line.long 0x028 "RMON_T_P64,FEC RMON Tx 64 Byte Packets" line.long 0x02C "RMON_T_P65TO127,FEC RMON Tx 65 to 127 Byte Packets" line.long 0x030 "RMON_T_P128TO255,FEC RMON Tx 128 to 255 Byte Packets" line.long 0x034 "RMON_T_P256TO511,FEC RMON Tx 256 to 511 Byte Packets" line.long 0x038 "RMON_T_P512TO1023,FEC RMON Tx 512 to 1023 Byte Packets" line.long 0x03C "RMON_T_P1024TO2047,FEC RMON Tx 1024 to 2047 Byte Packets" line.long 0x040 "RMON_T_P_GTE2048,FEC RMON Tx Packets W > 2048 Bytes" line.long 0x044 "RMON_T_OCTETS,FEC RMON Tx Octets" line.long 0x048 "IEEE_T_DROP,FEC Count of Frames Not Counted Correctly" line.long 0x04C "IEEE_T_FRAME_OK,FEC Frames Transmitted OK" line.long 0x050 "IEEE_T_1COL,FEC Frames Transmitted With Single Collision" line.long 0x054 "IEEE_T_MCOL,FEC Frames Transmitted With Multiple Collisions" line.long 0x058 "IEEE_T_DEF,FEC Frames Transmitted After Deferral Delay" line.long 0x05c "IEEE_T_LCOL,FEC Frames Transmitted With Late Collision" line.long 0x060 "IEEE_T_EXCOL,FEC Frames Transmitted With Excessive Collisions" line.long 0x064 "IEEE_T_MACERR,FEC Frames Transmitted With Tx FIFO Underrun" line.long 0x068 "IEEE_T_CSERR,FEC Frames Transmitted With Carrier Sense Error" line.long 0x06C "IEEE_T_SQE,FEC Frames Transmitted With SQE Error" line.long 0x070 "IEEE_T_FDXFC,FEC Flow Control Pause Frames Transmitted" line.long 0x074 "IEEE_T_OCTETS_OK,FEC Octet Count for Frames Transmitted W/O Error" group.long 0x2a80++0x063 line.long 0x000 "RMON_R_DROP,FEC Count of Frames Not Counted Correctly" line.long 0x004 "RMON_R_PACKETS,FEC RMON Rx Packet Count" line.long 0x008 "RMON_R_BC_PKT,FEC RMON Rx Broadcast Packets" line.long 0x00c "RMON_R_MC_PKT,FEC RMON Rx Multicast Packets" line.long 0x010 "RMON_R_CRC_ALIGN,FEC RMON Rx Packets W CRC/Align Error" line.long 0x014 "RMON_R_UNDERSIZE,FEC RMON Rx Packets < 64 Bytes Good CRC" line.long 0x018 "RMON_R_OVERSIZE,FEC RMON Rx Packets > MAX_FL Bytes Good CRC" line.long 0x01c "RMON_R_FRAG,FEC RMON Rx Packets < 64 Bytes Bad CRC" line.long 0x020 "RMON_R_JAB,FEC RMON Rx Packets > MAX_FL Bytes Bad CRC" line.long 0x024 "RMON_R_RESVD_0,FEC Reserved" line.long 0x028 "RMON_R_P64,FEC RMON Rx 64 Byte Packets" line.long 0x02c "RMON_R_P65TO127,FEC RMON Rx 65 to 127 Byte Packets" line.long 0x030 "RMON_R_P128TO255,FEC RMON Rx 128 to 255 Byte Packets" line.long 0x034 "RMON_R_P256TO511,FEC RMON Rx 256 to 511 Byte Packets" line.long 0x038 "RMON_R_P512TO1023,FEC RMON Rx 512 to 1023 Byte Packets" line.long 0x03c "RMON_R_P1024TO2047,FEC RMON Rx 1024 to 2047 Byte Packets" line.long 0x040 "RMON_R_P_GTE2048,FEC RMON Rx Packets W > 2048 Bytes" line.long 0x044 "RMON_R_OCTETS,FEC RMON Rx Octets" line.long 0x048 "IEEE_R_DROP,FEC Count of Frames Not Counted Correctly" line.long 0x04c "IEEE_R_FRAME_OK,FEC Frames Received OK" line.long 0x050 "IEEE_R_CRC,FEC Frames Received With CRC Error" line.long 0x054 "IEEE_R_ALIGN,FEC Frames Received With Alignment Error" line.long 0x058 "IEEE_R_MACERR,FEC Receive Fifo Overflow Count" line.long 0x05c "IEEE_R_FDXFC,FEC Flow Control Pause Frames Received" line.long 0x060 "IEEE_R_OCTETS_OK,FEC Octet Count for Frames Rcvd W/O Error" endif tree.end base ((d.l(anc:iobase()+0x2980))&0xfffffffc) width 0xa tree "RxBD,Ethernet Receive Buffer Descriptor" if (data.long(ANC:iobase()+0xf04)&0x00002000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.word 0x00++0x03 line.word 0x00 "BDSCIR,Buffer Descriptor Status/Control Information Register" bitfld.word 0x00 15. " E ,Empty" "Not empty,Empty" bitfld.word 0x00 14. " RO1 ,Receive software ownership" "Low,High" bitfld.word 0x00 13. " W ,Wrap location" "Consecutive,Defined in R_DES_START" textline " " bitfld.word 0x00 12. " RO2 ,Receive software ownership" "Low,High" bitfld.word 0x00 11. " L ,Last in frame" "Not last,Last" bitfld.word 0x00 8. " M ,Miss" "Address recognition hit,Promiscuous mode" textline " " bitfld.word 0x00 7. " BC ,DA is broadcast" "Not occurred,Occurred" bitfld.word 0x00 6. " MC ,DA is multicast and not BC" "Not occurred,Occurred" bitfld.word 0x00 5. " LG ,Rx frame length violation" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " NO ,Receive non-octet aligned frame" "Not occurred,Occurred" bitfld.word 0x00 2. " CR ,Receive CRC error" "No error,Error" textline " " bitfld.word 0x00 1. " OV ,Overrun" "No overrun,Overrun" bitfld.word 0x00 0. " TR ,Receive Frame is truncated" "Not truncated,Truncated" line.word 0x02 "BDDLR,Buffer Descriptor Data Length Register" group.long 0x04++0x03 line.long 0x00 "BDRxDP,Buffer Descriptor Rx Data Buffer Pointer" endif tree.end base ((d.l(anc:iobase()+0x2984))&0xfffffffc) tree "TxBD,Ethernet Transmit Buffer Descriptor" if (data.long(ANC:iobase()+0xf04)&0x00002000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.word 0x00++0x03 line.word 0x00 "BDSCIR,Buffer Descriptor Status/Control Information Register" bitfld.word 0x00 15. " R ,Ready" "Not ready,Ready" bitfld.word 0x00 14. " TO1 ,Transmit software ownership" "Low,High" bitfld.word 0x00 13. " W ,Wrap location" "Consecutive,Defined in X_DES_START" textline " " bitfld.word 0x00 12. " TO2 ,Transmit software ownership" "Low,High" bitfld.word 0x00 11. " L ,Last in frame" "Not last,Last" bitfld.word 0x00 10. " TC ,Transmit CRC after last data byte" "End of transmission,Continued" textline " " bitfld.word 0x00 9. " ABC ,Append bad CRC" "No effect,Inverted" line.word 0x02 "BDDLR,Buffer Descriptor Data Length Register" group.long 0x04++0x03 line.long 0x00 "BDTxDP,Buffer Descriptor Tx Data Buffer Pointer" wgroup 0x00++0x00 endif tree.end base ANC:iobase() tree.end tree "GPIO (General Purpose I/O IMMRBAR + 0x1100)" width 0xa group.long 0x1100++0x1b line.long 0x00 "GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " D0 ,Direction 0" "Input,Output" bitfld.long 0x00 30. " D1 ,Direction 1" "Input,Output" bitfld.long 0x00 29. " D2 ,Direction 2" "Input,Output" bitfld.long 0x00 28. " D3 ,Direction 3" "Input,Output" textline " " bitfld.long 0x00 27. " D4 ,Direction 4" "Input,Output" bitfld.long 0x00 26. " D5 ,Direction 5" "Input,Output" bitfld.long 0x00 25. " D6 ,Direction 6" "Input,Output" bitfld.long 0x00 24. " D7 ,Direction 7" "Input,Output" textline " " bitfld.long 0x00 23. " D8 ,Direction 8" "Input,Output" bitfld.long 0x00 22. " D9 ,Direction 9" "Input,Output" bitfld.long 0x00 21. " D10 ,Direction 10" "Input,Output" bitfld.long 0x00 20. " D11 ,Direction 11" "Input,Output" textline " " bitfld.long 0x00 19. " D12 ,Direction 12" "Input,Output" bitfld.long 0x00 18. " D13 ,Direction 13" "Input,Output" bitfld.long 0x00 17. " D14 ,Direction 14" "Input,Output" bitfld.long 0x00 16. " D15 ,Direction 15" "Input,Output" textline " " bitfld.long 0x00 15. " D16 ,Direction 16" "Input,Output" bitfld.long 0x00 14. " D17 ,Direction 17" "Input,Output" bitfld.long 0x00 13. " D18 ,Direction 18" "Input,Output" bitfld.long 0x00 12. " D19 ,Direction 19" "Input,Output" textline " " bitfld.long 0x00 11. " D20 ,Direction 20" "Input,Output" bitfld.long 0x00 10. " D21 ,Direction 21" "Input,Output" bitfld.long 0x00 9. " D22 ,Direction 22" "Input,Output" bitfld.long 0x00 8. " D23 ,Direction 23" "Input,Output" textline " " bitfld.long 0x00 7. " D24 ,Direction 24" "Input,Output" bitfld.long 0x00 6. " D25 ,Direction 25" "Input,Output" bitfld.long 0x00 5. " D26 ,Direction 26" "Input,Output" bitfld.long 0x00 4. " D27 ,Direction 27" "Input,Output" textline " " bitfld.long 0x00 3. " D28 ,Direction 28" "Input,Output" bitfld.long 0x00 2. " D29 ,Direction 29" "Input,Output" bitfld.long 0x00 1. " D30 ,Direction 30" "Input,Output" bitfld.long 0x00 0. " D31 ,Direction 31" "Input,Output" line.long 0x04 "GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " D0 ,Output drive configuration 0" "Output,Open-drain" bitfld.long 0x04 30. " D1 ,Output drive configuration 1" "Output,Open-drain" bitfld.long 0x04 29. " D2 ,Output drive configuration 2" "Output,Open-drain" bitfld.long 0x04 28. " D3 ,Output drive configuration 3" "Output,Open-drain" textline " " bitfld.long 0x04 27. " D4 ,Output drive configuration 4" "Output,Open-drain" bitfld.long 0x04 26. " D5 ,Output drive configuration 5" "Output,Open-drain" bitfld.long 0x04 25. " D6 ,Output drive configuration 6" "Output,Open-drain" bitfld.long 0x04 24. " D7 ,Output drive configuration 7" "Output,Open-drain" textline " " bitfld.long 0x04 23. " D8 ,Output drive configuration 8" "Output,Open-drain" bitfld.long 0x04 22. " D9 ,Output drive configuration 9" "Output,Open-drain" bitfld.long 0x04 21. " D10 ,Output drive configuration 10" "Output,Open-drain" bitfld.long 0x04 20. " D11 ,Output drive configuration 11" "Output,Open-drain" textline " " bitfld.long 0x04 19. " D12 ,Output drive configuration 12" "Output,Open-drain" bitfld.long 0x04 18. " D13 ,Output drive configuration 13" "Output,Open-drain" bitfld.long 0x04 17. " D14 ,Output drive configuration 14" "Output,Open-drain" bitfld.long 0x04 16. " D15 ,Output drive configuration 15" "Output,Open-drain" textline " " bitfld.long 0x04 15. " D16 ,Output drive configuration 16" "Output,Open-drain" bitfld.long 0x04 14. " D17 ,Output drive configuration 17" "Output,Open-drain" bitfld.long 0x04 13. " D18 ,Output drive configuration 18" "Output,Open-drain" bitfld.long 0x04 12. " D19 ,Output drive configuration 19" "Output,Open-drain" textline " " bitfld.long 0x04 11. " D20 ,Output drive configuration 20" "Output,Open-drain" bitfld.long 0x04 10. " D21 ,Output drive configuration 21" "Output,Open-drain" bitfld.long 0x04 9. " D22 ,Output drive configuration 22" "Output,Open-drain" bitfld.long 0x04 8. " D23 ,Output drive configuration 23" "Output,Open-drain" textline " " bitfld.long 0x04 7. " D24 ,Output drive configuration 24" "Output,Open-drain" bitfld.long 0x04 6. " D25 ,Output drive configuration 25" "Output,Open-drain" bitfld.long 0x04 5. " D26 ,Output drive configuration 26" "Output,Open-drain" bitfld.long 0x04 4. " D27 ,Output drive configuration 27" "Output,Open-drain" width 0xa line.long 0x08 "GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D0 ,Data 0" "Low,High" bitfld.long 0x08 30. " D1 ,Data 1" "Low,High" bitfld.long 0x08 29. " D2 ,Data 2" "Low,High" bitfld.long 0x08 28. " D3 ,Data 3" "Low,High" bitfld.long 0x08 27. " D4 ,Data 4" "Low,High" bitfld.long 0x08 26. " D5 ,Data 5" "Low,High" textline " " bitfld.long 0x08 25. " D6 ,Data 6" "Low,High" bitfld.long 0x08 24. " D7 ,Data 7" "Low,High" bitfld.long 0x08 23. " D8 ,Data 8" "Low,High" bitfld.long 0x08 22. " D9 ,Data 9" "Low,High" bitfld.long 0x08 21. " D10 ,Data 10" "Low,High" bitfld.long 0x08 20. " D11 ,Data 11" "Low,High" textline " " bitfld.long 0x08 19. " D12 ,Data 12" "Low,High" bitfld.long 0x08 18. " D13 ,Data 13" "Low,High" bitfld.long 0x08 17. " D14 ,Data 14" "Low,High" bitfld.long 0x08 16. " D15 ,Data 15" "Low,High" bitfld.long 0x08 15. " D16 ,Data 16" "Low,High" bitfld.long 0x08 14. " D17 ,Data 17" "Low,High" textline " " bitfld.long 0x08 13. " D18 ,Data 18" "Low,High" bitfld.long 0x08 12. " D19 ,Data 19" "Low,High" bitfld.long 0x08 11. " D20 ,Data 20" "Low,High" bitfld.long 0x08 10. " D21 ,Data 21" "Low,High" bitfld.long 0x08 9. " D22 ,Data 22" "Low,High" bitfld.long 0x08 8. " D23 ,Data 23" "Low,High" textline " " bitfld.long 0x08 7. " D24 ,Data 24" "Low,High" bitfld.long 0x08 6. " D25 ,Data 25" "Low,High" bitfld.long 0x08 5. " D26 ,Data 26" "Low,High" bitfld.long 0x08 4. " D27 ,Data 27" "Low,High" bitfld.long 0x08 3. " D28 ,Data 28" "Low,High" bitfld.long 0x08 2. " D29 ,Data 29" "Low,High" textline " " bitfld.long 0x08 1. " D30 ,Data 30" "Low,High" bitfld.long 0x08 0. " D31 ,Data 31" "Low,High" width 0xa line.long 0x0c "GPIER,GPIO Interrupt Event Register" eventfld.long 0x0c 31. " D0 ,Interrupt event 0" "Not occurred,Occurred" eventfld.long 0x0c 30. " D1 ,Interrupt event 1" "Not occurred,Occurred" eventfld.long 0x0c 29. " D2 ,Interrupt event 2" "Not occurred,Occurred" textline " " eventfld.long 0x0c 28. " D3 ,Interrupt event 3" "Not occurred,Occurred" eventfld.long 0x0c 27. " D4 ,Interrupt event 4" "Not occurred,Occurred" eventfld.long 0x0c 26. " D5 ,Interrupt event 5" "Not occurred,Occurred" textline " " eventfld.long 0x0c 25. " D6 ,Interrupt event 6" "Not occurred,Occurred" eventfld.long 0x0c 24. " D7 ,Interrupt event 7" "Not occurred,Occurred" eventfld.long 0x0c 23. " D8 ,Interrupt event 8" "Not occurred,Occurred" textline " " eventfld.long 0x0c 22. " D9 ,Interrupt event 9" "Not occurred,Occurred" eventfld.long 0x0c 21. " D10 ,Interrupt event 10" "Not occurred,Occurred" eventfld.long 0x0c 20. " D11 ,Interrupt event 11" "Not occurred,Occurred" textline " " eventfld.long 0x0c 19. " D12 ,Interrupt event 12" "Not occurred,Occurred" eventfld.long 0x0c 18. " D13 ,Interrupt event 13" "Not occurred,Occurred" eventfld.long 0x0c 17. " D14 ,Interrupt event 14" "Not occurred,Occurred" textline " " eventfld.long 0x0c 16. " D15 ,Interrupt event 15" "Not occurred,Occurred" eventfld.long 0x0c 15. " D16 ,Interrupt event 16" "Not occurred,Occurred" eventfld.long 0x0c 14. " D17 ,Interrupt event 17" "Not occurred,Occurred" textline " " eventfld.long 0x0c 13. " D18 ,Interrupt event 18" "Not occurred,Occurred" eventfld.long 0x0c 12. " D19 ,Interrupt event 19" "Not occurred,Occurred" eventfld.long 0x0c 11. " D20 ,Interrupt event 20" "Not occurred,Occurred" textline " " eventfld.long 0x0c 10. " D21 ,Interrupt event 21" "Not occurred,Occurred" eventfld.long 0x0c 9. " D22 ,Interrupt event 22" "Not occurred,Occurred" eventfld.long 0x0c 8. " D23 ,Interrupt event 23" "Not occurred,Occurred" textline " " eventfld.long 0x0c 7. " D24 ,Interrupt event 24" "Not occurred,Occurred" eventfld.long 0x0c 6. " D25 ,Interrupt event 25" "Not occurred,Occurred" eventfld.long 0x0c 5. " D26 ,Interrupt event 26" "Not occurred,Occurred" textline " " eventfld.long 0x0c 4. " D27 ,Interrupt event 27" "Not occurred,Occurred" eventfld.long 0x0c 3. " D28 ,Interrupt event 28" "Not occurred,Occurred" eventfld.long 0x0c 2. " D29 ,Interrupt event 29" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " D30 ,Interrupt event 30" "Not occurred,Occurred" eventfld.long 0x0c 0. " D31 ,Interrupt event 31" "Not occurred,Occurred" width 0xa line.long 0x10 "GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " D0 ,Interrupt mask 0" "Masked,Not masked" bitfld.long 0x10 30. " D1 ,Interrupt mask 1" "Masked,Not masked" bitfld.long 0x10 29. " D2 ,Interrupt mask 2" "Masked,Not masked" bitfld.long 0x10 28. " D3 ,Interrupt mask 3" "Masked,Not masked" textline " " bitfld.long 0x10 27. " D4 ,Interrupt mask 4" "Masked,Not masked" bitfld.long 0x10 26. " D5 ,Interrupt mask 5" "Masked,Not masked" bitfld.long 0x10 25. " D6 ,Interrupt mask 6" "Masked,Not masked" bitfld.long 0x10 24. " D7 ,Interrupt mask 7" "Masked,Not masked" textline " " bitfld.long 0x10 23. " D8 ,Interrupt mask 8" "Masked,Not masked" bitfld.long 0x10 22. " D9 ,Interrupt mask 9" "Masked,Not masked" bitfld.long 0x10 21. " D10 ,Interrupt mask 10" "Masked,Not masked" bitfld.long 0x10 20. " D11 ,Interrupt mask 11" "Masked,Not masked" textline " " bitfld.long 0x10 19. " D12 ,Interrupt mask 12" "Masked,Not masked" bitfld.long 0x10 18. " D13 ,Interrupt mask 13" "Masked,Not masked" bitfld.long 0x10 17. " D14 ,Interrupt mask 14" "Masked,Not masked" bitfld.long 0x10 16. " D15 ,Interrupt mask 15" "Masked,Not masked" textline " " bitfld.long 0x10 15. " D16 ,Interrupt mask 16" "Masked,Not masked" bitfld.long 0x10 14. " D17 ,Interrupt mask 17" "Masked,Not masked" bitfld.long 0x10 13. " D18 ,Interrupt mask 18" "Masked,Not masked" bitfld.long 0x10 12. " D19 ,Interrupt mask 19" "Masked,Not masked" textline " " bitfld.long 0x10 11. " D20 ,Interrupt mask 20" "Masked,Not masked" bitfld.long 0x10 10. " D21 ,Interrupt mask 21" "Masked,Not masked" bitfld.long 0x10 9. " D22 ,Interrupt mask 22" "Masked,Not masked" bitfld.long 0x10 8. " D23 ,Interrupt mask 23" "Masked,Not masked" textline " " bitfld.long 0x10 7. " D24 ,Interrupt mask 24" "Masked,Not masked" bitfld.long 0x10 6. " D25 ,Interrupt mask 25" "Masked,Not masked" bitfld.long 0x10 5. " D26 ,Interrupt mask 26" "Masked,Not masked" bitfld.long 0x10 4. " D27 ,Interrupt mask 27" "Masked,Not masked" textline " " bitfld.long 0x10 3. " D28 ,Interrupt mask 28" "Masked,Not masked" bitfld.long 0x10 2. " D29 ,Interrupt mask 29" "Masked,Not masked" bitfld.long 0x10 1. " D30 ,Interrupt mask 30" "Masked,Not masked" bitfld.long 0x10 0. " D31 ,Interrupt mask 31" "Masked,Not masked" line.long 0x14 "GP1ICR,GPIO1 Interrupt Control Register" bitfld.long 0x14 30.--31. " D0 ,Edge detection mode 0" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 28.--29. " D1 ,Edge detection mode 1" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 26.--27. " D2 ,Edge detection mode 2" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 24.--25. " D3 ,Edge detection mode 3" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x14 22.--23. " D4 ,Edge detection mode 4" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 20.--21. " D5 ,Edge detection mode 5" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 18.--19. " D6 ,Edge detection mode 6" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 16.--17. " D7 ,Edge detection mode 7" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x14 14.--15. " D8 ,Edge detection mode 8" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 12.--13. " D9 ,Edge detection mode 9" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 10.--11. " D10 ,Edge detection mode 10" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 8.--9. " D11 ,Edge detection mode 11" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x14 6.--7. " D12 ,Edge detection mode 12" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 4.--5. " D13 ,Edge detection mode 13" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 2.--3. " D14 ,Edge detection mode 14" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x14 0.--1. " D15 ,Edge detection mode 15" "Any change,Low-to-high,High-to-low,Pulse" line.long 0x18 "GP1ICR,GPIO1 Interrupt Control Register" bitfld.long 0x18 30.--31. " D16 ,Edge detection mode 16" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 28.--29. " D17 ,Edge detection mode 17" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 26.--27. " D18 ,Edge detection mode 18" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 24.--25. " D19 ,Edge detection mode 19" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x18 22.--23. " D20 ,Edge detection mode 20" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 20.--21. " D21 ,Edge detection mode 21" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 18.--19. " D22 ,Edge detection mode 22" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 16.--17. " D23 ,Edge detection mode 23" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x18 14.--15. " D24 ,Edge detection mode 24" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 12.--13. " D25 ,Edge detection mode 25" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 10.--11. " D26 ,Edge detection mode 26" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 8.--9. " D27 ,Edge detection mode 27" "Any change,Low-to-high,High-to-low,Pulse" textline " " bitfld.long 0x18 6.--7. " D28 ,Edge detection mode 28" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 4.--5. " D29 ,Edge detection mode 29" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 2.--3. " D30 ,Edge detection mode 30" "Any change,Low-to-high,High-to-low,Pulse" bitfld.long 0x18 0.--1. " D31 ,Edge detection mode 31" "Any change,Low-to-high,High-to-low,Pulse" tree.end tree "GPT (General Purpose Timers IMMRBAR + 0x0b00)" width 0xa tree "GPT0 Registers" group.long 0xB00++0x0f line.long 0x0 "GPT0EMS,GPT0 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT0ICO,GPT0 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT0PWM,GPT0 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT0STA,GPT0 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT1 Registers" group.long 0xB10++0x0f line.long 0x0 "GPT1EMS,GPT1 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT1ICO,GPT1 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT1PWM,GPT1 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT1STA,GPT1 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT2 Registers" group.long 0xB20++0x0f line.long 0x0 "GPT2EMS,GPT2 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT2ICO,GPT2 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT2PWM,GPT2 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT2STA,GPT2 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT3 Registers" group.long 0xB30++0x0f line.long 0x0 "GPT3EMS,GPT3 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT3ICO,GPT3 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT3PWM,GPT3 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT3STA,GPT3 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT4 Registers" group.long 0xB40++0x0f line.long 0x0 "GPT4EMS,GPT4 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT4ICO,GPT4 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT4PWM,GPT4 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT4STA,GPT4 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT5 Registers" group.long 0xB50++0x0f line.long 0x0 "GPT5EMS,GPT5 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT5ICO,GPT5 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT5PWM,GPT5 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT5STA,GPT5 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT6 Registers" group.long 0xB60++0x0f line.long 0x0 "GPT6EMS,GPT6 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT6ICO,GPT6 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT6PWM,GPT6 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT6STA,GPT6 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree "GPT7 Registers" group.long 0xB70++0x0f line.long 0x0 "GPT7EMS,GPT7 Enable and Mode Select Register" hexmask.long.byte 0x0 24.--31. 1. " OCPW ,Output Compare Pulse Width" bitfld.long 0x0 20.--21. " OCT ,Output Compare Type" "Special case,Output pulses high,Output pulses low,Output toggles" textline " " bitfld.long 0x0 18.--19. " ICM ,Input Capture Mode" "Normal,Up submode,Updown submode,Rotary submode" bitfld.long 0x0 16.--17. " ICT ,Input Capture Type" "Any Transition,Rising Edge,Falling Edge,Pulse" textline " " bitfld.long 0x0 12. " CE ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " Stop_Cont ,Stop Continuous" "Stop,Continous" bitfld.long 0x0 9. " Open_Drn ,Open Drain" "Normal,Open drain" textline " " bitfld.long 0x0 8. " IntEn ,Enable Interrupt" "Disabled,Enabled" bitfld.long 0x0 4.--5. " GPIO ,GPIO Mode Type" "Input,Input,Output value=0,Output value=1" textline " " bitfld.long 0x0 0.--2. " Timer_MS ,Timer Mode Select" "Disabled,Input Capture,Output Compare,PWM,Simple GPIO,Simple GPIO,Simple GPIO,Simple GPIO" line.long 0x04 "GPT7ICO,GPT7 Input and Up/Down Counter Output Register" hexmask.long.word 0x04 16.--31. 1. " PRESCALE ,Prescale amount applied to internal counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Sets number of prescaled counts applied to reference events" line.long 0x08 "GPT7PWM,GPT7 PWM Configuration Register" hexmask.long.word 0x08 16.--31. 1. " WIDTH ,ON time for output in prescaled counts" bitfld.long 0x08 8. " PWMOP ,Pulse Width Mode Output Polarity" "0,1" textline " " bitfld.long 0x08 0. " LOAD ,Bit forces immediate period update" "Not updated,Updated" line.long 0x0c "GPT7STA,GPT7 Status Register" hexmask.long.word 0x0c 16.--31. 1. " CAPTURE ,Read of internal counter, latch at reference event" bitfld.long 0x0c 12.--14. " OVF ,Represents how many times internal counter has rolled over" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8. " PIN ,Registered state of the I/O PIN" "Low,High" eventfld.long 0x0c 4. " UDOV ,Updown counter overflow/underflow" "Not occurred,Occurred" textline " " eventfld.long 0x0c 3. " TEXP ,Timer Expired in Internal Timer mode" "Not occurred,Occurred" eventfld.long 0x0c 2. " PWMP ,PWM end of period occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0c 1. " COMP ,OC reference event occurred" "Not occurred,Occurred" eventfld.long 0x0c 0. " CAPT ,IC reference event occurred" "Not occurred,Occurred" tree.end tree.end tree "IIM/Fusebox (IMMRBAR + 0xb000)" width 0xa if (data.long(ANC:iobase()+0xf08)&0x00080000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0xb000++0x1b line.long 0x00 "STAT,Status Register" bitfld.long 0x00 7. " BUSY ,Indicates whether the IIM is busy with a program or sense cycle" "Not busy,Busy" eventfld.long 0x00 1. " PRGD ,Program Done" "Not Done,Done" textline " " eventfld.long 0x00 0. " SNSD ,Explicit Sense Cycle Done" "Not done,Done" line.long 0x04 "STATM,Status IRQ Mask" bitfld.long 0x04 1. " PRGD_M ,Program Mask" "No IRQ,IRQ" bitfld.long 0x04 0. " SNSD_M ,Explicitly Sense Cycle Done Mask" "No IRQ,IRQ" line.long 0x08 "ERR,Module Errors Register" eventfld.long 0x08 6. " WPE ,Write Protect Error" "No error,Error" eventfld.long 0x08 5. " OPE ,Override Protect Error" "No error,Error" textline " " eventfld.long 0x08 4. " RPE ,Read Protect Error" "No error,Error" eventfld.long 0x08 3. " WLRE ,Write to Locked Register Error" "No error,Error" textline " " eventfld.long 0x08 2. " SNSE ,Explicit Sense Cycle Error" "No error,Error" eventfld.long 0x08 1. " PARITYE ,Parity Error of Cache" "No error,Error" line.long 0x0c "EMASK,Error IRQ Mask Register" bitfld.long 0x0c 6. " WPE_M ,Write Protect Error Mask" "No IRQ,IRQ" textline " " bitfld.long 0x0c 5. " OPE_M ,Override Protect Error" "No IRQ,IRQ" bitfld.long 0x0c 4. " RPE_M ,Read Protect Error Mask" "No IRQ,IRQ" textline " " bitfld.long 0x0c 3. " WLRE_M ,Write to Locked Register Error Mask" "No IRQ,IRQ" bitfld.long 0x0c 2. " SNSE_M ,Explicit Sense Cycle Error Mask" "No IRQ,IRQ" textline " " bitfld.long 0x0c 1. " PARITYE_M ,Parity Error of Cache Mask" "No IRQ,IRQ" line.long 0x10 "FCTL,Fuse Control Register" bitfld.long 0x10 4.--6. " PRG_LENGTH[2:0] ,Program Length" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 3. " ESNS_N ,Explicit Sense/Normal" "No effect,Initiate" bitfld.long 0x10 2. " ESNS_0 ,Explicit Sense/0 Stressed" "No effect,Initiate" textline " " bitfld.long 0x10 1. " ESNS_1 ,Explicit Sense/1 Stressed" "No effect,Initiate" bitfld.long 0x10 0. " PRG ,Program" "No effect,Initiate" line.long 0x14 "UA,Upper Address Register" hexmask.long.byte 0x14 0.--5. 1. " A[13:8] ,The Top Six Bits of The Address of The e-Fuse Bit" line.long 0x18 "LA,Lower Address Register" hexmask.long.byte 0x18 0.--7. 1. " A[7:0] ,The Bottom Eight Bits of The Address of The e-Fuse Bit" rgroup.long 0xb01c++0x03 line.long 0x00 "SDAT,Explicit Sense Data Register" hexmask.long.byte 0x00 0.--7. 1. " D[7:0] ,The Data Sensed From the Fuses" group.long 0xb028++0x03 line.long 0x00 "PRG_P,Program Protection Register" hexmask.long.byte 0x00 0.--7. 1. " PROTECTION_REG[7:0] ,Protection Value" group.long 0xb03c++0x03 line.long 0x00 "DIVIDE,Divide Factor Register" hexmask.long.byte 0x00 0.--7. 1. " DIVIDE[7:0] ,A Divide Factor" group.long 0xbc00++0xa3 line.long 0x00 "FBAC1,Fuse Bank 1 Protection Register" bitfld.long 0x00 7. " FBWP ,Fuse Bank Write Protection" "Unblown,Blown" bitfld.long 0x00 6. " FBOP ,Fuse Bank Override Protection" "Unblown,Blown" textline " " bitfld.long 0x00 5. " FBRP ,Fuse Bank Read Protection" "Unblown,Blown" bitfld.long 0x00 3. " FBESP ,Fuse Banks Explicit Sense Protection" "Unblown,Blown" line.long 0x4 "FB1W1,Fuse Bank 1 Data Register 0" bitfld.long 0x4 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x4 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x4 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x4 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x4 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x4 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x4 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x4 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x8 "FB1W1,Fuse Bank 1 Data Register 1" bitfld.long 0x8 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x8 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x8 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x8 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x8 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x8 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x8 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x8 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0xC "FB1W1,Fuse Bank 1 Data Register 2" bitfld.long 0xC 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0xC 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0xC 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0xC 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0xC 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0xC 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0xC 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0xC 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x10 "FB1W1,Fuse Bank 1 Data Register 3" bitfld.long 0x10 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x10 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x10 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x10 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x10 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x10 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x10 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x10 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x14 "FB1W1,Fuse Bank 1 Data Register 4" bitfld.long 0x14 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x14 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x14 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x14 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x14 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x14 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x14 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x14 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x18 "FB1W1,Fuse Bank 1 Data Register 5" bitfld.long 0x18 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x18 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x18 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x18 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x18 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x18 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x18 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x18 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x1C "FB1W1,Fuse Bank 1 Data Register 6" bitfld.long 0x1C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x1C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x1C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x1C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x1C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x1C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x1C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x1C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x20 "FB1W1,Fuse Bank 1 Data Register 7" bitfld.long 0x20 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x20 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x20 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x20 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x20 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x20 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x20 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x20 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x24 "FB1W1,Fuse Bank 1 Data Register 8" bitfld.long 0x24 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x24 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x24 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x24 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x24 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x24 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x24 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x24 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x28 "FB1W1,Fuse Bank 1 Data Register 9" bitfld.long 0x28 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x28 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x28 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x28 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x28 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x28 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x28 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x28 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x2C "FB1W1,Fuse Bank 1 Data Register 10" bitfld.long 0x2C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x2C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x2C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x2C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x2C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x2C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x2C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x2C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x30 "FB1W1,Fuse Bank 1 Data Register 11" bitfld.long 0x30 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x30 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x30 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x30 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x30 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x30 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x30 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x30 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x34 "FB1W1,Fuse Bank 1 Data Register 12" bitfld.long 0x34 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x34 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x34 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x34 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x34 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x34 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x34 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x34 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x38 "FB1W1,Fuse Bank 1 Data Register 13" bitfld.long 0x38 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x38 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x38 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x38 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x38 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x38 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x38 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x38 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x3C "FB1W1,Fuse Bank 1 Data Register 14" bitfld.long 0x3C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x3C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x3C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x3C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x3C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x3C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x3C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x3C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x40 "FB1W1,Fuse Bank 1 Data Register 15" bitfld.long 0x40 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x40 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x40 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x40 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x40 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x40 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x40 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x40 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x44 "FB1W1,Fuse Bank 1 Data Register 16" bitfld.long 0x44 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x44 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x44 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x44 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x44 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x44 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x44 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x44 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x48 "FB1W1,Fuse Bank 1 Data Register 17" bitfld.long 0x48 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x48 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x48 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x48 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x48 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x48 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x48 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x48 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x4C "FB1W1,Fuse Bank 1 Data Register 18" bitfld.long 0x4C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x4C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x4C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x4C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x4C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x4C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x4C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x4C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x50 "FB1W1,Fuse Bank 1 Data Register 19" bitfld.long 0x50 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x50 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x50 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x50 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x50 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x50 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x50 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x50 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x54 "FB1W1,Fuse Bank 1 Data Register 20" bitfld.long 0x54 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x54 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x54 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x54 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x54 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x54 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x54 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x54 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x58 "FB1W1,Fuse Bank 1 Data Register 21" bitfld.long 0x58 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x58 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x58 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x58 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x58 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x58 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x58 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x58 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x5C "FB1W1,Fuse Bank 1 Data Register 22" bitfld.long 0x5C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x5C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x5C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x5C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x5C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x5C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x5C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x5C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x60 "FB1W1,Fuse Bank 1 Data Register 23" bitfld.long 0x60 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x60 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x60 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x60 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x60 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x60 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x60 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x60 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x64 "FB1W1,Fuse Bank 1 Data Register 24" bitfld.long 0x64 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x64 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x64 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x64 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x64 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x64 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x64 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x64 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x68 "FB1W1,Fuse Bank 1 Data Register 25" bitfld.long 0x68 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x68 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x68 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x68 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x68 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x68 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x68 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x68 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x6C "FB1W1,Fuse Bank 1 Data Register 26" bitfld.long 0x6C 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x6C 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x6C 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x6C 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x6C 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x6C 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x6C 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x6C 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x70 "FB1W1,Fuse Bank 1 Data Register 27" bitfld.long 0x70 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x70 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x70 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x70 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x70 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x70 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x70 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x70 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x74 "FB1W1,Fuse Bank 1 Data Register 28" bitfld.long 0x74 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x74 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x74 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x74 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x74 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x74 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x74 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x74 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" line.long 0x78 "FB1W1,Fuse Bank 1 Data Register 29" bitfld.long 0x78 7. " DATA7 ,Fuse Bank 1 Data 7" "0,1" bitfld.long 0x78 6. " DATA6 ,Fuse Bank 1 Data 6" "0,1" bitfld.long 0x78 5. " DATA5 ,Fuse Bank 1 Data 5" "0,1" bitfld.long 0x78 4. " DATA4 ,Fuse Bank 1 Data 4" "0,1" textline " " bitfld.long 0x78 3. " DATA3 ,Fuse Bank 1 Data 3" "0,1" bitfld.long 0x78 2. " DATA2 ,Fuse Bank 1 Data 2" "0,1" bitfld.long 0x78 1. " DATA1 ,Fuse Bank 1 Data 1" "0,1" bitfld.long 0x78 0. " DATA0 ,Fuse Bank 1 Data 0" "0,1" endif tree.end tree "IPIC (Integrated Programmable Interrupt Controller IMMRBAR + 0x0c00)" width 9. group.long 0x0c00++0x03 line.long 0x00 "SICFR,System Global Interrupt Configuration Register" hexmask.long.byte 0x00 24.--30. 1. " HPI ,Highest Priority Interrupt" bitfld.long 0x00 22. " MPSB ,Mixed Interrupts Priority Scheme for group B" "Grouped,Spread" bitfld.long 0x00 21. " MPSA ,Mixed Interrupts Priority Scheme for group A" "Grouped,Spread" textline " " bitfld.long 0x00 19. " IPSD ,Internal interrupt Priority Scheme for group D" "Grouped,Spread" bitfld.long 0x00 18. " IPSC ,Internal interrupt Priority Scheme for group C" "Grouped,Spread" bitfld.long 0x00 17. " IPSB ,Internal interrupt Priority Scheme for group B" "Grouped,Spread" textline " " bitfld.long 0x00 16. " IPSA ,Internal interrupt Priority Scheme for group A" "Grouped,Spread" bitfld.long 0x00 8.--9. " HPIT ,HPI priority position IPIC" "/INT,/SMI,/CINT,Reserved" rgroup.long 0x0c04++0x0b line.long 0x00 "SIVCR,System Global Interrupt Vector Register" hexmask.long.byte 0x00 0.--6. 1. " IVEC ,Interrupt Vector" line.long 0x04 "SIPNR_H,System Internal Interrupt Pending Register" bitfld.long 0x04 31. " PSC4 ,PSC4 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 30. " PSC5 ,PSC5 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 29. " PSC6 ,PSC6 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 28. " PSC7 ,PSC7 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 27. " PSC8 ,PSC8 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 26. " PSC9 ,PSC9 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 25. " PSC10 ,PSC10 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 24. " PSC11 ,PSC11 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 23. " FIFOC ,FIFOC Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 22. " SPDIF ,SPDIF Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 21. " AXE ,AXE Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 20. " USB_ULPI ,USB_ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 19. " USB_UTMI ,USB_UTMI Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 15. " PCI ,PCI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 14. " PCI_DMA ,PCI_DMA Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 13. " PCI_MU ,PCI_MU Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 12. " FEC ,FEC Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 11. " PATA ,PATA Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 10. " NFC ,NFC Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 9. " LPC ,LPC Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 8. " SDHC ,SDHC Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7. " I2C1 ,I2C1 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 6. " I2C2 ,I2C2 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 5. " I2C3 ,I2C3 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 4. " MSCAN1 ,MSCAN1 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 3. " MSCAN2 ,MSCAN2 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 2. " BDLC ,BDLC Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 1. " GPT0 ,GPT0 Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " GPT1 ,GPT1 Interrupt" "No interrupt,Interrupt" line.long 0x08 "SIPNR_L,System Internal Interrupt Pending Register" bitfld.long 0x08 31. " IPI_INT_INTERNAL[32] ,IPI_INT_INTERNAL Interrupt[32]" "No interrupt,Interrupt" textline " " bitfld.long 0x08 30. " IPI_INT_INTERNAL[33] ,IPI_INT_INTERNAL[33] Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 29. " IPI_INT_INTERNAL[34] ,IPI_INT_INTERNAL[34] Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 28. " IPI_INT_INTERNAL[35] ,IPI_INT_INTERNAL[35] Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 27. " PSC0 ,PSC0 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 26. " PSC1 ,PSC1 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 25. " PSC2 ,PSC2 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 24. " PSC3 ,PSC3 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 23. " GPT2 ,GPT2 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 22. " GPT3 ,GPT3 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 21. " GPT4 ,GPT4 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 20. " GPT5 ,GPT5 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 19. " GPT6 ,GPT6 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 18. " GPT7 ,GPT7 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 17. " GPIO ,GPIO Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 16. " RTC_SEC ,RTC_SEC Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 15. " RTC_ALARM ,RTC_ALARM Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 14. " DDR ,DDR Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 13. " SBA ,SBA Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 12. " PMC ,PMC Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 11. " USB2_OTG1_WKUP ,USB2_OTG1_WKUP Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 10. " USB2_OTG2_WKUP ,USB2_OTG2_WKUP Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 9. " GPIO2 ,GPIO2 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " TEMP_105C ,TEMP_105C Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 7. " IIM ,IIM Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 6. " PRIOMON ,PRIOMON Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 5. " MSCAN3 ,MSCAN1 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 4. " MSCAN4 ,MSCAN2 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 3. " GPT12 ,GPT12 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 2. " GPT13 ,GPT13 Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 1. " GPT14 ,GPT14 Interrupt" "No interrupt,Interrupt" bitfld.long 0x08 0. " GPT15 ,GPT15 Interrupt" "No interrupt,Interrupt" group.long 0x0c10++0x1b line.long 0x00 "SIPRR_A,System Internal Interrupt Group A Priority Register" bitfld.long 0x00 29.--31. " SYSA0P ,SYSA0 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" bitfld.long 0x00 26.--28. " SYSA1P ,SYSA1 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" bitfld.long 0x00 23.--25. " SYSA2P ,SYSA2 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" textline " " bitfld.long 0x00 20.--22. " SYSA3P ,SYSA3 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" bitfld.long 0x00 13.--15. " SYSA4P ,SYSA4 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" bitfld.long 0x00 10.--12. " SYSA5P ,SYSA5 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" textline " " bitfld.long 0x00 7.--9. " SYSA6P ,SYSA6 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" bitfld.long 0x00 4.--6. " SYSA7P ,SYSA7 Priority Order" "PSC4,PSC5,PSC6,PSC7,PSC8,PSC9,PSC10,PSC11" line.long 0x04 "SIPRR_B,System Internal Interrupt Group B Priority Register" bitfld.long 0x04 29.--31. " SYSB0P ,SYSB0 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" bitfld.long 0x04 26.--28. " SYSB1P ,SYSB1 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" bitfld.long 0x04 23.--25. " SYSB2P ,SYSB2 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" textline " " bitfld.long 0x04 20.--22. " SYSB3P ,SYSB3 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" bitfld.long 0x04 13.--15. " SYSB4P ,SYSB4 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" bitfld.long 0x04 10.--12. " SYSB5P ,SYSB5 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" textline " " bitfld.long 0x04 7.--9. " SYSB6P ,SYSB6 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" bitfld.long 0x04 4.--6. " SYSB7P ,SYSB7 Priority Order" "FIFOC,SPDIF,AXE,USB_ULPI,USB_UTMI,SATA,Reserved,Reserved" line.long 0x08 "SIPRR_C,System Internal Interrupt Group C Priority Register" bitfld.long 0x08 29.--31. " SYSC0P ,SYSC0 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" bitfld.long 0x08 26.--28. " SYSC1P ,SYSC1 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" bitfld.long 0x08 23.--25. " SYSC2P ,SYSC2 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" textline " " bitfld.long 0x08 20.--22. " SYSC3P ,SYSC3 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" bitfld.long 0x08 13.--15. " SYSC4P ,SYSC4 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" bitfld.long 0x08 10.--12. " SYSC5P ,SYSC5 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" textline " " bitfld.long 0x08 7.--9. " SYSC6P ,SYSC6 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" bitfld.long 0x08 4.--6. " SYSC7P ,SYSC7 Priority Order" "PCI,PCI_DMA,PCI_MU,FEC,PATA,NFC,LPC,SDHC" line.long 0x0c "SIPRR_D,System Internal Interrupt Group D Priority Register" bitfld.long 0x0c 29.--31. " SYSD0P ,SYSD0 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" bitfld.long 0x0c 26.--28. " SYSD1P ,SYSD1 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" bitfld.long 0x0c 23.--25. " SYSD2P ,SYSD2 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" textline " " bitfld.long 0x0c 20.--22. " SYSD3P ,SYSD3 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" bitfld.long 0x0c 13.--15. " SYSD4P ,SYSD4 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" bitfld.long 0x0c 10.--12. " SYSD5P ,SYSD5 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" textline " " bitfld.long 0x0c 7.--9. " SYSD6P ,SYSD6 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" bitfld.long 0x0c 4.--6. " SYSD7P ,SYSD7 Priority Order" "I2C1,I2C2,I2C3,MSCAN1,MSCAN2,BDLC,GPT0,GPT1" line.long 0x10 "SIMSR_H,System Internal Interrupt Mask Register" bitfld.long 0x10 31. " PSC4 ,PSC4 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 30. " PSC5 ,PSC5 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 29. " PSC6 ,PSC6 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 28. " PSC7 ,PSC7 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 27. " PSC8 ,PSC8 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 26. " PSC9 ,PSC9 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 25. " PSC10 ,PSC10 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 24. " PSC11 ,PSC11 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 23. " FIFOC ,FIFOC Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 22. " SPDIF ,SPDIF Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 21. " AXE ,AXE Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 20. " USB_ULPI ,USB_ULPI Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 19. " USB_UTMI ,USB_UTMI Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 15. " PCI ,PCI Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 14. " PCI_DMA ,PCI_DMA Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 13. " PCI_MU ,PCI_MU Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 12. " FEC ,FEC Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 11. " PATA ,PATA Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 10. " NFC ,NFC Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 9. " LPC ,LPC Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 8. " SDHC ,SDHC Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 7. " I2C1 ,I2C1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 6. " I2C2 ,I2C2 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 5. " I2C3 ,I2C3 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 4. " MSCAN1 ,MSCAN1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 3. " MSCAN2 ,MSCAN2 Timer Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x10 2. " BDLC ,BDLC Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 1. " GPT0 ,GPT0 Interrupt Mask" "Masked,Not masked" bitfld.long 0x10 0. " GPT1 ,GPT1 Interrupt Mask" "Masked,Not masked" line.long 0x14 "SIMSR_L,System Internal Interrupt Mask Register" bitfld.long 0x14 31. " IPI_INT_INTERNAL[32] ,IPI_INT_INTERNAL Interrupt[32]" "Masked,Not masked" textline " " bitfld.long 0x14 30. " IPI_INT_INTERNAL[33] ,IPI_INT_INTERNAL[33] Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 29. " IPI_INT_INTERNAL[34] ,IPI_INT_INTERNAL[34] Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 28. " IPI_INT_INTERNAL[35] ,IPI_INT_INTERNAL[35] Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 27. " PSC0 ,PSC0 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 26. " PSC1 ,PSC1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 25. " PSC2 ,PSC2 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x14 24. " PSC3 ,PSC3 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 23. " GPT2 ,GPT2 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 22. " GPT3 ,GPT3 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x14 21. " GPT4 ,GPT4 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 20. " GPT5 ,GPT5 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 19. " GPT6 ,GPT6 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x14 18. " GPT7 ,GPT7 Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 17. " GPIO ,GPIO Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 16. " RTC_SEC ,RTC_SEC Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x14 15. " RTC_ALARM ,RTC_ALARM Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 14. " DDR ,DDR Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 13. " SBA ,SBA Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x14 12. " PMC ,PMC Interrupt Mask" "Masked,Not masked" bitfld.long 0x14 11. " USB2_OTG1_WKUP ,USB2_OTG1_WKUP Interrupt" "Masked,Not masked" bitfld.long 0x14 10. " USB2_OTG2_WKUP ,USB2_OTG2_WKUP Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 9. " GPIO2 ,GPIO2 Interrupt" "Masked,Not masked" bitfld.long 0x14 8. " TEMP_105C ,TEMP_105C Interrupt" "Masked,Not masked" bitfld.long 0x14 7. " IIM ,IIM Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 6. " PRIOMON ,PRIOMON Interrupt" "Masked,Not masked" bitfld.long 0x14 5. " MSCAN3 ,MSCAN1 Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 4. " MSCAN4 ,MSCAN2 Interrupt" "Masked,Not masked" bitfld.long 0x14 3. " GPT12 ,GPT12 Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 2. " GPT13 ,GPT13 Interrupt" "Masked,Not masked" bitfld.long 0x14 1. " GPT14 ,GPT14 Interrupt" "Masked,Not masked" textline " " bitfld.long 0x14 0. " GPT15 ,GPT15 Interrupt" "Masked,Not masked" line.long 0x18 "SICNR,System Internal Interrupt Control Register" bitfld.long 0x18 30.--31. " SYSD0T ,SYSD0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x18 28.--29. " SYSD1T ,SYSD1 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x18 22.--23. " SYSC0T ,SYSC0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" textline " " bitfld.long 0x18 20.--21. " SYSC1T ,SYSC1 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x18 14.--15. " SYSB0T ,SYSB0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x18 12.--13. " SYSB1T ,SYSB1 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" textline " " bitfld.long 0x18 6.--7. " SYSA0T ,SYSA0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x18 4.--5. " SYSA1T ,SYSA0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" if ((d.l(anc:(iobase()+0xc00+0x38))&0x8000)==0x0) group.long 0x0c2c++0x3 line.long 0x00 "SEPNR,System External Interrupt Pending Register" eventfld.long 0x00 31. " IRQ0 ,IRQ0 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt" "No interrupt,Interrupt" else group.long 0x0c2c++0x3 line.long 0x00 "SEPNR,System External Interrupt Pending Register" eventfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt" "No interrupt,Interrupt" endif group.long 0x0c30++0x7 line.long 0x00 "SMPRR_A,System Mixed Interrupt Group A Priority Register" bitfld.long 0x00 29.--31. " MIXA0P ,MIXA0 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" bitfld.long 0x00 26.--28. " MIXA1P ,MIXA1 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" bitfld.long 0x00 23.--25. " MIXA2P ,MIXA2 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" textline " " bitfld.long 0x00 20.--22. " MIXA3P ,MIXA3 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" bitfld.long 0x00 13.--15. " MIXA4P ,MIXA4 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" bitfld.long 0x00 10.--12. " MIXA5P ,MIXA5 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" textline " " bitfld.long 0x00 7.--9. " MIXA6P ,MIXA6 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" bitfld.long 0x00 4.--6. " MIXA7P ,MIXA7 Priority Order" "IPI_INT_INTERNAL[32],IPI_INT_INTERNAL[33],IPI_INT_INTERNAL[34],IPI_INT_INTERNAL[35],IPP_IND_EXT_INT[0],IPP_IND_EXT_INT[1],IPP_IND_EXT_INT[2],IPP_IND_EXT_INT[3]" line.long 0x04 "SMPRR_B,System Mixed Interrupt Group B Priority Register" bitfld.long 0x04 29.--31. " MIXB0P ,MIXB0 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x04 26.--28. " MIXB1P ,MIXB1 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x04 23.--25. " MIXB2P ,MIXB2 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x04 20.--22. " MIXB3P ,MIXB3 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x04 13.--15. " MIXB4P ,MIXB4 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x04 10.--12. " MIXB5P ,MIXB5 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x04 7.--9. " MIXB6P ,MIXB6 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x04 4.--6. " MIXB7P ,MIXB7 Priority Order" "PSC0,PSC1,PSC2,PSC3,Reserved,Reserved,Reserved,Reserved" if ((d.l(anc:(iobase()+0xc00+0x38))&0x8000)==0x0) group.long 0x0c38++0x3 line.long 0x00 "SEMSR,System External Interrupt Mask Register" bitfld.long 0x00 31. " IRQ0 ,IRQ0 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 15. " SIRQ0 ,Steer IRQ0" "Interrupt,MCP" else group.long 0x0c38++0x3 line.long 0x00 "SEMSR,System External Interrupt Mask Mask Register" textline " " bitfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 15. " SIRQ0 ,Steer IRQ0" "Interrupt,MCP" endif group.long 0x0c3c++0x3 line.long 0x00 "SECNR,System External Interrupt Control Register" bitfld.long 0x00 30.--31. " MIXB0T ,MIXB0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x00 28.--29. " MIXB1T ,MIXB1 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x00 22.--23. " MIXA0T ,MIXA0 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" textline " " bitfld.long 0x00 20.--21. " MIXA1T ,MIXA1 priority position IPIC output interrupt type" "/int,/smi,/cint,Reserved" bitfld.long 0x00 15. " EDI0 ,Edge detect mode" "Low level,Falling" bitfld.long 0x00 14. " EDI1 ,Edge detect mode" "Low level,Falling" if ((d.l(anc:(iobase()+0xc00+0x38))&0x8000)==0x0) group.long 0x0c40++0x7 line.long 0x00 "SERSR,System Error Status Register" bitfld.long 0x00 31. " IPP_IND_EXT_INT[0] ,IPP_IND_EXT_INT[0] Error" "No error,Error" bitfld.long 0x00 30. " WDT ,WDT Error" "No error,Error" bitfld.long 0x00 29. " SBA ,SBA Error" "No error,Error" textline " " bitfld.long 0x00 26. " PCI ,PCI Error" "No error,Error" bitfld.long 0x00 24. " MU ,MU Error" "No error,Error" bitfld.long 0x00 22. " TEMP125C ,TEMPL125C Error" "No error,Error" line.long 0x04 "SERMR,System Error Mask Register" bitfld.long 0x04 31. " IPP_IND_EXT_INT[0] ,IPP_IND_EXT_INT[0] Error Mask" "Masked,Not masked" bitfld.long 0x04 30. " WDT ,WDT Error Mask" "Masked,Not masked" bitfld.long 0x04 29. " SBA ,SBA Error Mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " PCI ,PCI Error Mask" "Masked,Not masked" bitfld.long 0x04 24. " MU ,MU Error Mask" "Masked,Not masked" bitfld.long 0x04 22. " TEMP125C ,TEMP125C Error Mask" "Masked,Not masked" else group.long 0x0c40++0x7 line.long 0x00 "SERSR,System Error Status Register" bitfld.long 0x00 30. " WDT ,WDT Error" "No error,Error" bitfld.long 0x00 29. " SBA ,SBA Error" "No error,Error" textline " " bitfld.long 0x00 26. " PCI ,PCI Error" "No error,Error" bitfld.long 0x00 24. " MU ,MU Error" "No error,Error" bitfld.long 0x00 22. " TEMP125C ,TEMPL125C Error" "No error,Error" line.long 0x04 "SERMR,System Error Mask Register" bitfld.long 0x04 30. " WDT ,WDT Error Mask" "Masked,Not masked" bitfld.long 0x04 29. " SBA ,SBA Error Mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " PCI ,PCI Error Mask" "Masked,Not masked" bitfld.long 0x04 24. " MU ,MU Error Mask" "Masked,Not masked" bitfld.long 0x04 22. " TEMP125C ,TEMP125C Error Mask" "Masked,Not masked" endif rgroup.long 0x0c4c++0x3 line.long 0x00 "SEPCR,System External Interrupt Polarity Check Register" bitfld.long 0x00 31. " EIP0 ,Each bit defines the active state for the external IRQn" "Low,High" bitfld.long 0x00 30. " EIP1 ,Each bit defines the active state for the external IRQn" "Low,High" group.long 0x0c50++0x7 line.long 0x00 "SIFCR_H,System Internal Interrupt Force Register" bitfld.long 0x00 31. " PSC4 ,PSC4 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 30. " PSC5 ,PSC5 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 29. " PSC6 ,PSC6 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 28. " PSC7 ,PSC7 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 27. " PSC8 ,PSC8 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 26. " PSC9 ,PSC9 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 25. " GPT8 ,GPT8 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 24. " GPT9 ,GPT9 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 23. " FIFOC ,FIFOC Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 20. " USB2_OTG1 ,USB2_OTG1 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 19. " USB2_OTG2 ,USB2_OTG2 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 15. " GPT10 ,GPT10 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 14. " GPT11 ,GPT11 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 13. " SDHC2 ,SDHC2 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 12. " FEC1 ,FEC1 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 11. " FEC2 ,FEC2 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 10. " NFC ,NFC Interrupt Force" "Not forced,Forced" bitfld.long 0x00 9. " LPC ,LPC Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 8. " SDHC1 ,SDHC1 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 7. " I2C1 ,I2C1 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 6. " I2C2 ,I2C2 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 5. " I2C3 ,I2C3 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 4. " MSCAN1 ,MSCAN1 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 3. " MSCAN2 ,MSCAN2 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " BDLC ,BDLC Interrupt Force" "Not forced,Forced" bitfld.long 0x00 1. " GPT0 ,GPT0 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 0. " GPT1 ,GPT1 Interrupt Force" "Not forced,Forced" line.long 0x04 "SIPNR_L,System Internal Interrupt Pending Register" bitfld.long 0x04 31. " DIU ,DIU Interrupt Force" "Not forced,Forced" bitfld.long 0x04 30. " DMA2 ,DMA2 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 27. " PSC0 ,PSC0 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 26. " PSC1 ,PSC1 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 25. " PSC2 ,PSC2 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 24. " PSC3 ,PSC3 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 23. " GPT2 ,GPT2 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 22. " GPT3 ,GPT3 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 21. " GPT4 ,GPT4 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 20. " GPT5 ,GPT5 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 19. " GPT6 ,GPT6 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 18. " GPT7 ,GPT7 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 17. " GPIO1 ,GPIO1 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 16. " RTC_SEC ,RTC_SEC Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 15. " RTC_ALARM ,RTC_ALARM Interrupt Force" "Not forced,Forced" bitfld.long 0x04 14. " DDR ,DDR Interrupt Force" "Not forced,Forced" bitfld.long 0x04 13. " SBA ,SBA Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 12. " PMC ,PMC Interrupt Force" "Not forced,Forced" bitfld.long 0x04 11. " USB2_OTG1_WKUP ,USB2_OTG1_WKUP Interrupt Force" "Not forced,Forced" bitfld.long 0x04 10. " USB2_OTG2_WKUP ,USB2_OTG2_WKUP Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 9. " GPIO2 ,GPIO2 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 8. " TEMP_105C ,TEMP_105C Interrupt Force" "Not forced,Forced" bitfld.long 0x04 7. " IIM ,IIM Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 6. " PRIOMON ,PRIOMON Interrupt Force" "Not forced,Forced" bitfld.long 0x04 5. " MSCAN3 ,MSCAN1 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 4. " MSCAN4 ,MSCAN1 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 3. " GPT12 ,GPT12 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 2. " GPT13 ,GPT13 Interrupt Force" "Not forced,Forced" bitfld.long 0x04 1. " GPT14 ,GPT14 Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x04 0. " GPT15 ,GPT15 Interrupt Force" "Not forced,Forced" if ((d.l(anc:(iobase()+0xc00+0x38))&0x8000)==0x8000) group.long 0x0c58++0x7 line.long 0x00 "SEFCR,System External Interrupt Force Register" bitfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt Force" "Not forced,Forced" line.long 0x04 "SERFR,System Error Force Register" bitfld.long 0x04 31. " IRQ0 ,IRQ0 Error Force" "Not forced,Forced" bitfld.long 0x04 30. " WDT ,WDT Error Force" "Not forced,Forced" bitfld.long 0x04 29. " SBA ,SBA Error Force" "Not forced,Forced" textline " " bitfld.long 0x04 22. " TEMP125C ,TEMP125C Error Force" "Not forced,Forced" else group.long 0x0c58++0x7 line.long 0x00 "SEFCR,System External Interrupt Force Register" bitfld.long 0x00 31. " IRQ0 ,IRQ0 Interrupt Force" "Not forced,Forced" bitfld.long 0x00 30. " IRQ1 ,IRQ1 Interrupt Force" "Not forced,Forced" line.long 0x04 "SERFR,System Error Force Register" bitfld.long 0x04 30. " WDT ,WDT Error Force" "Not forced,Forced" bitfld.long 0x04 29. " SBA ,SBA Error Force" "Not forced,Forced" textline " " bitfld.long 0x04 22. " TEMP125C ,TEMP125C Error Force" "Not forced,Forced" endif rgroup.long 0x0c60++0x7 line.long 0x00 "SCVCR,System Critical Interrupt Vector Register" hexmask.long.byte 0x00 0.--6. 1. " CVEC ,Critical interrupt vector" line.long 0x04 "SMVCR,System Management Interrupt Vector Register" hexmask.long.byte 0x04 0.--6. 1. " MVEC ,System management interrupt vector" width 0xb tree.end tree "I2C (Inter-Integrated Circuit IMMRBAR + 0x1700)" tree "I2C Channel 1" width 0xa group.long 0x1700++0x0b line.long 0x00 "MADR,I2C1 Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " ADR[7:1] ,Slave address" line.long 0x04 "MFDR,I2C1 Frequency Divider Register" hexmask.long.byte 0x04 24.--31. 1. " FDR[7:0] ,Frequency divider ratio" line.long 0x08 "MCR,I2C1 Control Register" bitfld.long 0x08 31. " EN ,Module enable" "Disabled,Enabled" bitfld.long 0x08 30. " IEN ,Module interrupt enable" "Disabled,Enabled" bitfld.long 0x08 29. " STA ,Master/slave mode START" "Slave,Master" textline " " bitfld.long 0x08 28. " TX ,Transmit/receive mode select" "Receive,Transmit" bitfld.long 0x08 27. " TXAK ,Transfer acknowledge" "Acknowledge,No acknowledge" bitfld.long 0x08 26. " RSTA ,Repeat START" "No START,Repeat START" rgroup.long (0x1700+0x0c)++0x03 line.long 0x00 "MSR,I2C1 Status Register" bitfld.long 0x00 31. " CF ,Data transfer" "In progress,Completed" bitfld.long 0x00 30. " AAS ,Addressed as a slave" "Not addressed,Addressed" bitfld.long 0x00 29. " BB ,Bus busy" "Idle,Busy" textline " " bitfld.long 0x00 28. " AL ,Arbitration lost" "Not lost,Lost" bitfld.long 0x00 27. " AKF ,Acknowledge Cycle Falling Edge" "1st interrupt on rising,2nd interrupt on rising" bitfld.long 0x00 26. " SRW ,Slave read/write" "Write,Read" textline " " bitfld.long 0x00 25. " IF ,I2C interrupt" "No interrupt,Interrupt" bitfld.long 0x00 24. " RXAK ,Received acknowledge" "Acknowledge,No acknowledge" group.long (0x1700+0x10)++0x3 line.long 0x00 "MDR,I2C1 Data Register" hexmask.long.byte 0x00 24.--31. 1. " D[7:0] ,I/O Data" tree.end tree "I2C Channel 2" width 0xa group.long 0x1720++0x0b line.long 0x00 "MADR,I2C2 Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " ADR[7:1] ,Slave address" line.long 0x04 "MFDR,I2C2 Frequency Divider Register" hexmask.long.byte 0x04 24.--31. 1. " FDR[7:0] ,Frequency divider ratio" line.long 0x08 "MCR,I2C2 Control Register" bitfld.long 0x08 31. " EN ,Module enable" "Disabled,Enabled" bitfld.long 0x08 30. " IEN ,Module interrupt enable" "Disabled,Enabled" bitfld.long 0x08 29. " STA ,Master/slave mode START" "Slave,Master" textline " " bitfld.long 0x08 28. " TX ,Transmit/receive mode select" "Receive,Transmit" bitfld.long 0x08 27. " TXAK ,Transfer acknowledge" "Acknowledge,No acknowledge" bitfld.long 0x08 26. " RSTA ,Repeat START" "No START,Repeat START" rgroup.long (0x1720+0x0c)++0x03 line.long 0x00 "MSR,I2C2 Status Register" bitfld.long 0x00 31. " CF ,Data transfer" "In progress,Completed" bitfld.long 0x00 30. " AAS ,Addressed as a slave" "Not addressed,Addressed" bitfld.long 0x00 29. " BB ,Bus busy" "Idle,Busy" textline " " bitfld.long 0x00 28. " AL ,Arbitration lost" "Not lost,Lost" bitfld.long 0x00 27. " AKF ,Acknowledge Cycle Falling Edge" "1st interrupt on rising,2nd interrupt on rising" bitfld.long 0x00 26. " SRW ,Slave read/write" "Write,Read" textline " " bitfld.long 0x00 25. " IF ,I2C interrupt" "No interrupt,Interrupt" bitfld.long 0x00 24. " RXAK ,Received acknowledge" "Acknowledge,No acknowledge" group.long (0x1720+0x10)++0x3 line.long 0x00 "MDR,I2C2 Data Register" hexmask.long.byte 0x00 24.--31. 1. " D[7:0] ,I/O Data" tree.end tree "I2C Channel 3" width 0xa group.long 0x1740++0x0b line.long 0x00 "MADR,I2C3 Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " ADR[7:1] ,Slave address" line.long 0x04 "MFDR,I2C3 Frequency Divider Register" hexmask.long.byte 0x04 24.--31. 1. " FDR[7:0] ,Frequency divider ratio" line.long 0x08 "MCR,I2C3 Control Register" bitfld.long 0x08 31. " EN ,Module enable" "Disabled,Enabled" bitfld.long 0x08 30. " IEN ,Module interrupt enable" "Disabled,Enabled" bitfld.long 0x08 29. " STA ,Master/slave mode START" "Slave,Master" textline " " bitfld.long 0x08 28. " TX ,Transmit/receive mode select" "Receive,Transmit" bitfld.long 0x08 27. " TXAK ,Transfer acknowledge" "Acknowledge,No acknowledge" bitfld.long 0x08 26. " RSTA ,Repeat START" "No START,Repeat START" rgroup.long (0x1740+0x0c)++0x03 line.long 0x00 "MSR,I2C3 Status Register" bitfld.long 0x00 31. " CF ,Data transfer" "In progress,Completed" bitfld.long 0x00 30. " AAS ,Addressed as a slave" "Not addressed,Addressed" bitfld.long 0x00 29. " BB ,Bus busy" "Idle,Busy" textline " " bitfld.long 0x00 28. " AL ,Arbitration lost" "Not lost,Lost" bitfld.long 0x00 27. " AKF ,Acknowledge Cycle Falling Edge" "1st interrupt on rising,2nd interrupt on rising" bitfld.long 0x00 26. " SRW ,Slave read/write" "Write,Read" textline " " bitfld.long 0x00 25. " IF ,I2C interrupt" "No interrupt,Interrupt" bitfld.long 0x00 24. " RXAK ,Received acknowledge" "Acknowledge,No acknowledge" group.long (0x1740+0x10)++0x3 line.long 0x00 "MDR,I2C3 Data Register" hexmask.long.byte 0x00 24.--31. 1. " D[7:0] ,I/O Data" tree.end tree "I2C Control Registers" width 0xa group.long 0x1760++0x07 line.long 0x00 "ICR,I2C Interrupt Control Register" bitfld.long 0x00 29. " BNBE3 ,Bus Not Busy Enable 3" "No interrupt,Interrupt" bitfld.long 0x00 28. " IE3 ,Interrupt Enable 3" "No interrupt,Interrupt" bitfld.long 0x00 27. " BNBE2 ,Bus Not Busy Enable 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 26. " IE2 ,Interrupt Enable 2" "No interrupt,Interrupt" bitfld.long 0x00 25. " BNBE1 ,Bus Not Busy Enable 1" "No interrupt,Interrupt" bitfld.long 0x00 24. " IE1 ,Interrupt Enable 1" "No interrupt,Interrupt" line.long 0x04 "MIFR,I2C Filter Register" bitfld.long 0x04 24.--27. " FR[7:4] ,Programming controls for the width of glitch the filter should absorb" "No filter,1 IPBUS,2 IPBUS,3 IPBUS,4 IPBUS,5 IPBUS,6 IPBUS,7 IPBUS,8 IPBUS,9 IPBUS,10 IPBUS,11 IPBUS,12 IPBUS,13 IPBUS,14 IPBUS,15 IPBUS" tree.end tree.end tree "IO Control ( IMMRBAR + 0xa000)" width 0x18 if (data.long(ANC:iobase()+0xf04)&0x80000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0xa000++0x07 line.long 0x00 "IO_CONTROL_MEM,MEM IO Control Register" bitfld.long 0x00 6. " 16BIT ,Pin Muxing in DRAM 16 bit Mode Enable" "Disabled,Enabled" bitfld.long 0x00 3.--5. " CONT_DS ,CONT_DS controls the slew rate of all DRAM control pads" "DDR pad configuration 0,DDR pad configuration 1,DDR pad configuration 2,DDR pad configuration 3,Reserved,Reserved,DDR pad configuration 6,Reserved" textline " " bitfld.long 0x00 0.--2. " DATA_DS ,DATA_DS controls the slew rate of all DRAM data pads" "DDR pad configuration 0,DDR pad configuration 1,DDR pad configuration 2,DDR pad configuration 3,Reserved,Reserved,DDR pad configuration 6,Reserved" line.long 0x04 "IO_CONTROL_GP,GP MUX Control Register" bitfld.long 0x04 7. " GP_MUX7 ,Muxing Control Between GPIO7 and GPT7" "GPT7,GPIO7" bitfld.long 0x04 6. " GP_MUX6 ,Muxing Control Between GPIO6 and GPT6" "GPT6,GPIO6" textline " " bitfld.long 0x04 5. " GP_MUX5 ,Muxing Control Between GPIO5 and GPT5" "GPT5,GPIO5" bitfld.long 0x04 4. " GP_MUX4 ,Muxing Control Between GPIO4 and GPT4" "GPT4,GPIO4" textline " " bitfld.long 0x04 3. " GP_MUX3 ,Muxing Control Between GPIO3 and GPT3" "GPT3,GPIO3" bitfld.long 0x04 2. " GP_MUX2 ,Muxing Control Between GPIO2 and GPT2" "GPT2,GPIO2" textline " " bitfld.long 0x04 1. " GP_MUX1 ,Muxing Control Between GPIO1 and GPT1" "GPT1,GPIO1" bitfld.long 0x04 0. " GP_MUX0 ,Muxing Control Between GPIO0 and GPT0" "GPT0,GPIO0" group.long 0xa008++0x2f3 line.long 0x00 "IO_CONTROL_LPC_CLK,LPC_CLK Pad Control Register" bitfld.long 0x00 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "LPC_CLK,TPA,CKSTP_IN,Reserved" bitfld.long 0x00 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x04 "IO_CONTROL_/LPC_OE,/LPC_OE Pad Control Register" bitfld.long 0x04 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/LPC_OE,Reserved,Reserved,Reserved" bitfld.long 0x04 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x08 "IO_CONTROL_LPC_RW,LPC_RW Pad Control Register" bitfld.long 0x08 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "LPC_RW,Reserved,Reserved,Reserved" bitfld.long 0x08 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x0c "IO_CONTROL_/LPC_ACK,/LPC_ACK Pad Control Register" bitfld.long 0x0c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/LPC_ACK,/LPC_CS7,Reserved,GPIO24" bitfld.long 0x0c 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x0c 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x0c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x10 "IO_CONTROL_/LPC_CS0,/LPC_CS0 Pad Control Register" bitfld.long 0x10 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/LPC_CS0,Reserved,Reserved,GPIO25" bitfld.long 0x10 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x10 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x10 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x14 "IO_CONTROL_/NFC_CE0,/NFC_CE0 Pad Control Register" bitfld.long 0x14 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/NFC_CE0,LPC_CS3,PSC_MCLK_IN,GPIO26" bitfld.long 0x14 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x14 3. " PUE ,The pull usage enable" "Disabled,Enabled" bitfld.long 0x14 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x18 "IO_CONTROL_/LPC_CS1,/LPC_CS1 Pad Control Register" bitfld.long 0x18 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/LPC_CS1,SPDIF_TXCLK,Reserved,GPIO7" bitfld.long 0x18 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x18 3. " PUE ,The pull usage enable" "Disabled,Enabled" bitfld.long 0x18 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1c "IO_CONTROL_/LPC_CS2,/LPC_CS2 Pad Control Register" bitfld.long 0x1c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/LPC_CS2,/NFC_CE1,Reserved,GPIO0" bitfld.long 0x1c 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x1c 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x1c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x20 "IO_CONTROL_LPC_AX03,LPC_AX03 Pad Control Register" bitfld.long 0x20 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "LPC_AX03,Reserved,Reserved,GPIO1" bitfld.long 0x20 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x24 "IO_CONTROL_EMB_AX02,EMB_AX02 Pad Control Register" bitfld.long 0x24 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "EMB_AX02,Reserved,Reserved,GPIO2" bitfld.long 0x24 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x28 "IO_CONTROL_EMB_AX01,EMB_AX01 Pad Control Register" bitfld.long 0x28 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "EMB_AX01,Reserved,Reserved,GPIO3" bitfld.long 0x28 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2c "IO_CONTROL_EMB_AX00,EMB_AX00 Pad Control Register" bitfld.long 0x2c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "EMB_AX00,Reserved,Reserved,Reserved" bitfld.long 0x2c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x30 "IO_CONTROL_EMB_AD31,EMB_AD31 Pad Control Register" bitfld.long 0x30 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD31,Reserved" bitfld.long 0x30 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x34 "IO_CONTROL_EMB_AD30,EMB_AD30 Pad Control Register" bitfld.long 0x34 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD30,Reserved" bitfld.long 0x34 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x38 "IO_CONTROL_EMB_AD29,EMB_AD29 Pad Control Register" bitfld.long 0x38 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD29,Reserved" bitfld.long 0x38 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x3c "IO_CONTROL_EMB_AD28,EMB_AD28 Pad Control Register" bitfld.long 0x3c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD28,Reserved" bitfld.long 0x3c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x40 "IO_CONTROL_EMB_AD27,EMB_AD27 Pad Control Register" bitfld.long 0x40 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD27,Reserved" bitfld.long 0x40 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x44 "IO_CONTROL_EMB_AD26,EMB_AD26 Pad Control Register" bitfld.long 0x44 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD26,Reserved" bitfld.long 0x44 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x48 "IO_CONTROL_EMB_AD25,EMB_AD25 Pad Control Register" bitfld.long 0x48 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD25,Reserved" bitfld.long 0x48 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x4c "IO_CONTROL_EMB_AD24,EMB_AD24 Pad Control Register" bitfld.long 0x4c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD24,Reserved" bitfld.long 0x4c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x50 "IO_CONTROL_EMB_AD23,EMB_AD23 Pad Control Register" bitfld.long 0x50 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD23,Reserved" bitfld.long 0x50 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x54 "IO_CONTROL_EMB_AD22,EMB_AD22 Pad Control Register" bitfld.long 0x54 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD22,Reserved" bitfld.long 0x54 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x58 "IO_CONTROL_EMB_AD21,EMB_AD21 Pad Control Register" bitfld.long 0x58 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD21,Reserved" bitfld.long 0x58 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x5c "IO_CONTROL_EMB_AD20,EMB_AD20 Pad Control Register" bitfld.long 0x5c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD20,Reserved" bitfld.long 0x5c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x60 "IO_CONTROL_EMB_AD19,EMB_AD19 Pad Control Register" bitfld.long 0x60 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD19,Reserved" bitfld.long 0x60 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x64 "IO_CONTROL_EMB_AD18,EMB_AD18 Pad Control Register" bitfld.long 0x64 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD18,Reserved" bitfld.long 0x64 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x68 "IO_CONTROL_EMB_AD17,EMB_AD17 Pad Control Register" bitfld.long 0x68 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD17,Reserved" bitfld.long 0x68 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x6c "IO_CONTROL_EMB_AD16,EMB_AD16 Pad Control Register" bitfld.long 0x6c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD16,Reserved" bitfld.long 0x6c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x70 "IO_CONTROL_EMB_AD15,EMB_AD15 Pad Control Register" bitfld.long 0x70 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD15,Reserved" bitfld.long 0x70 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x74 "IO_CONTROL_EMB_AD14,EMB_AD14 Pad Control Register" bitfld.long 0x74 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD14,Reserved" bitfld.long 0x74 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x78 "IO_CONTROL_EMB_AD13,EMB_AD13 Pad Control Register" bitfld.long 0x78 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD13,Reserved" bitfld.long 0x78 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x7c "IO_CONTROL_EMB_AD12,EMB_AD12 Pad Control Register" bitfld.long 0x7c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD12,Reserved" bitfld.long 0x7c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x80 "IO_CONTROL_EMB_AD11,EMB_AD11 Pad Control Register" bitfld.long 0x80 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD11,Reserved" bitfld.long 0x80 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x84 "IO_CONTROL_EMB_AD10,EMB_AD10 Pad Control Register" bitfld.long 0x84 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD10,Reserved" bitfld.long 0x84 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x88 "IO_CONTROL_EMB_AD09,EMB_AD09 Pad Control Register" bitfld.long 0x88 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD09,Reserved" bitfld.long 0x88 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x8c "IO_CONTROL_EMB_AD08,EMB_AD08 Pad Control Register" bitfld.long 0x8c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD08,Reserved" bitfld.long 0x8c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x90 "IO_CONTROL_EMB_AD07,EMB_AD07 Pad Control Register" bitfld.long 0x90 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD07,Reserved" bitfld.long 0x90 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x94 "IO_CONTROL_EMB_AD06,EMB_AD06 Pad Control Register" bitfld.long 0x94 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD06,Reserved" bitfld.long 0x94 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x98 "IO_CONTROL_EMB_AD05,EMB_AD05 Pad Control Register" bitfld.long 0x98 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD05,Reserved" bitfld.long 0x98 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x9c "IO_CONTROL_EMB_AD04,EMB_AD04 Pad Control Register" bitfld.long 0x9c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD04,Reserved" bitfld.long 0x9c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xa0 "IO_CONTROL_EMB_AD03,EMB_AD03 Pad Control Register" bitfld.long 0xa0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD03,Reserved" bitfld.long 0xa0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xa4 "IO_CONTROL_EMB_AD02,EMB_AD02 Pad Control Register" bitfld.long 0xa4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD02,Reserved" bitfld.long 0xa4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xa8 "IO_CONTROL_EMB_AD01,EMB_AD01 Pad Control Register" bitfld.long 0xa8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD01,Reserved" bitfld.long 0xa8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xac "IO_CONTROL_EMB_AD00,EMB_AD00 Pad Control Register" bitfld.long 0xac 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "Reserved,Reserved,EMB_AD00,Reserved" bitfld.long 0xac 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xb0 "IO_CONTROL_/PATA_CE1,/PATA_CE1 Pad Control Register" bitfld.long 0xb0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PATA_CE1,/LPC_CS4,Reserved,GPIO9" bitfld.long 0xb0 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xb0 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xb0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xb4 "IO_CONTROL_/PATA_CE2,/PATA_CE2 Pad Control Register" bitfld.long 0xb4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PATA_CE2,/LPC_CS5,Reserved,GPIO10" bitfld.long 0xb4 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xb4 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xb4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xb8 "IO_CONTROL_PATA_ISOLATE,PATA_ISOLATE Pad Control Register" bitfld.long 0xb8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PATA_ISOLATE,CAN3_TX,Reserved,GPIO11" bitfld.long 0xb8 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xb8 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xb8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xbc "IO_CONTROL_/PATA_IOR,/PATA_IOR Pad Control Register" bitfld.long 0xbc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PATA_IOR,SDHC_CLK,Reserved,GPIO12" bitfld.long 0xbc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xc0 "IO_CONTROL_/PATA_IOW,/PATA_IOW Pad Control Register" bitfld.long 0xc0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PATA_IOW,SDHC_CMD,LPC_AX08,GPIO13" bitfld.long 0xc0 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xc0 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xc0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xc4 "IO_CONTROL_PATA_IOCHRDY,PATA_IOCHRDY Pad Control Register" bitfld.long 0xc4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PATA_IOCHRDY,SDHC_D0,LPC_AX07,GPIO14" bitfld.long 0xc4 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xc4 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xc4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xc8 "IO_CONTROL_PATA_INTRQ,PATA_INTRQ Pad Control Register" bitfld.long 0xc8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PATA_INTRQ,SDHC_D1_IRQ,LPC_AX06,GPIO15" bitfld.long 0xc8 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xc8 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xc8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xcc "IO_CONTROL_PATA_DRQ,PATA_DRQ Pad Control Register" bitfld.long 0xcc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PATA_DRQ,SDHC_D2,LPC_AX05,GPIO16" bitfld.long 0xcc 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xcc 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xcc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xd0 "IO_CONTROL_/PATA_DACK,/PATA_DACK Pad Control Register" bitfld.long 0xd0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PATA_DACK,SDHC_D3_CD,LPC_AX04,GPIO17" bitfld.long 0xd0 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xd0 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xd0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xd4 "IO_CONTROL_/NFC_WP,/NFC_WP Pad Control Register" bitfld.long 0xd4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/NFC_WP,SDHC_CLK,LPC_AX09,GPIO18" bitfld.long 0xd4 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xd4 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xd4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xd8 "IO_CONTROL_NFC_R/B,NFC_R/B Pad Control Register" bitfld.long 0xd8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "NFC_R/B,SDHC_CMD,LPC_AX08,GPIO19" bitfld.long 0xd8 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xd8 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xd8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xdc "IO_CONTROL_NFC_ALE,NFC_ALE Pad Control Register" bitfld.long 0xdc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "NFC_ALE,SDHC_D0,LPC_AX07,GPIO20" bitfld.long 0xdc 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xdc 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xdc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xe0 "IO_CONTROL_NFC_CLE,NFC_CLE Pad Control Register" bitfld.long 0xe0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "NFC_CLE,SDHC_D1_IRQ,LPC_AX06,GPIO21" bitfld.long 0xe0 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xe0 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xe0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xe4 "IO_CONTROL_/NFC_WE,/NFC_WE Pad Control Register" bitfld.long 0xe4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/NFC_WE,SDHC_D2,LPC_AX05,GPIO22" bitfld.long 0xe4 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xe4 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xe4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xe8 "IO_CONTROL_/NFC_RE,/NFC_RE Pad Control Register" bitfld.long 0xe8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/NFC_RE,SDHC_D3_CD,LPC_AX04,GPIO23" bitfld.long 0xe8 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0xe8 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0xe8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0xec "IO_CONTROL_PCI_AD31,PCI_AD31 Pad Control Register" bitfld.long 0xec 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD31,USB0_CLK,DIU_LD22,GPIO0" bitfld.long 0xec 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0xec 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" bitfld.long 0xec 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0xf0 "IO_CONTROL_PCI_AD30,PCI_AD30 Pad Control Register" bitfld.long 0xf0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD30,USB0_DIR,DIU_LD23,GPIO1" bitfld.long 0xf0 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0xf0 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0xf4 "IO_CONTROL_PCI_AD29,PCI_AD29 Pad Control Register" bitfld.long 0xf4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD29,Reserved,USB1_DATA7,GPIO2" bitfld.long 0xf4 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0xf4 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0xf8 "IO_CONTROL_PCI_AD28,PCI_AD28 Pad Control Register" bitfld.long 0xf8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD28,Reserved,USB1_DATA6,GPIO3" bitfld.long 0xf8 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0xf8 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0xfc "IO_CONTROL_PCI_AD27,PCI_AD27 Pad Control Register" bitfld.long 0xfc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD27,Reserved,USB1_DATA5,GPIO4" bitfld.long 0xfc 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0xfc 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x100 "IO_CONTROL_PCI_AD26,PCI_AD26 Pad Control Register" bitfld.long 0x100 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD26,Reserved,USB1_DATA4,GPIO5" bitfld.long 0x100 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x100 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x104 "IO_CONTROL_PCI_AD25,PCI_AD25 Pad Control Register" bitfld.long 0x104 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD25,Reserved,USB1_DATA3,GPIO6" bitfld.long 0x104 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x104 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x108 "IO_CONTROL_PCI_AD24,PCI_AD24 Pad Control Register" bitfld.long 0x108 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD24,Reserved,USB1_DATA2,GPIO7" bitfld.long 0x108 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x108 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x10c "IO_CONTROL_PCI_AD23,PCI_AD23 Pad Control Register" bitfld.long 0x10c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD23,Reserved,USB1_DATA1,GPIO8" bitfld.long 0x10c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x10c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x110 "IO_CONTROL_PCI_AD22,PCI_AD22 Pad Control Register" bitfld.long 0x110 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD22,Reserved,USB1_DATA0,GPIO9" bitfld.long 0x110 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x110 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x114 "IO_CONTROL_PCI_AD21,PCI_AD21 Pad Control Register" bitfld.long 0x114 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD21,Reserved,USB1_STOP,GPIO10" bitfld.long 0x114 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x114 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x118 "IO_CONTROL_PCI_AD20,PCI_AD20 Pad Control Register" bitfld.long 0x118 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD20,Reserved,USB1_NEXT,GPIO11" bitfld.long 0x118 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x118 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x11c "IO_CONTROL_PCI_AD19,PCI_AD19 Pad Control Register" bitfld.long 0x11c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD19,Reserved,USB1_CLK,GPIO12" bitfld.long 0x11c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x11c 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" bitfld.long 0x11c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x120 "IO_CONTROL_PCI_AD18,PCI_AD18 Pad Control Register" bitfld.long 0x120 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD18,Reserved,USB1_DIR,GPIO13" bitfld.long 0x120 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x120 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x124 "IO_CONTROL_PCI_AD17,PCI_AD17 Pad Control Register" bitfld.long 0x124 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD17,VIU_DATA0,FEC_TXD_3,GPIO14" bitfld.long 0x124 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x124 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x128 "IO_CONTROL_PCI_AD16,PCI_AD16 Pad Control Register" bitfld.long 0x128 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD16,VIU_DATA1,FEC_TXD_2,GPIO15" bitfld.long 0x128 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x128 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x12c "IO_CONTROL_PCI_AD15,PCI_AD15 Pad Control Register" bitfld.long 0x12c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD15,VIU_DATA2,FEC_TXD_1,GPIO16" bitfld.long 0x12c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x12c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x130 "IO_CONTROL_PCI_AD14,PCI_AD14 Pad Control Register" bitfld.long 0x130 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD14,Reserved,FEC_TXD_0,GPIO17" bitfld.long 0x130 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x130 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x134 "IO_CONTROL_PCI_AD13,PCI_AD13 Pad Control Register" bitfld.long 0x134 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD13,VIU_DATA3,FEC_RXD_3,GPIO18" bitfld.long 0x134 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x134 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x138 "IO_CONTROL_PCI_AD12,PCI_AD12 Pad Control Register" bitfld.long 0x138 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD12,VIU_DATA4,FEC_RXD_2,GPIO19" bitfld.long 0x138 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x138 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x13c "IO_CONTROL_PCI_AD11,PCI_AD11 Pad Control Register" bitfld.long 0x13c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD11,VIU_DATA5,FEC_RXD_1,GPIO20" bitfld.long 0x13c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x13c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x140 "IO_CONTROL_PCI_AD10,PCI_AD10 Pad Control Register" bitfld.long 0x140 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD10,Reserved,FEC_RXD_0,GPIO21" bitfld.long 0x140 5.--6. " HOLD ,HOLD controls the PCI output hold delay elements" "Class 1,Class 2,Class 3,Class 4" textline " " bitfld.long 0x140 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x144 "IO_CONTROL_PCI_AD09,PCI_AD09 Pad Control Register" bitfld.long 0x144 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD09,Reserved,FEC_RX_CLK,GPIO22" bitfld.long 0x144 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x144 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" bitfld.long 0x144 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x148 "IO_CONTROL_PCI_AD08,PCI_AD08 Pad Control Register" bitfld.long 0x148 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD08,Reserved,FEC_TX_CLK,GPIO23" bitfld.long 0x148 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x148 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" bitfld.long 0x148 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x14c "IO_CONTROL_PCI_AD07,PCI_AD07 Pad Control Register" bitfld.long 0x14c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD07,VIU_DATA7,FEC_RX_ER,GPIO24" bitfld.long 0x14c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x14c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x150 "IO_CONTROL_PCI_AD06,PCI_AD06 Pad Control Register" bitfld.long 0x150 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD06,Reserved,FEC_RX_DV,GPIO25" bitfld.long 0x150 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x150 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x154 "IO_CONTROL_PCI_AD05,PCI_AD05 Pad Control Register" bitfld.long 0x154 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD05,Reserved,FEC_TX_EN,GPIO26" bitfld.long 0x154 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x154 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x158 "IO_CONTROL_PCI_AD04,PCI_AD04 Pad Control Register" bitfld.long 0x158 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD04,VIU_PIX_CLK,FEC_TX_ER,GPIO27" bitfld.long 0x158 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x158 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x15c "IO_CONTROL_PCI_AD03,PCI_AD03 Pad Control Register" bitfld.long 0x15c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD03,VIU_DATA6,FEC_CRS,GPIO0" bitfld.long 0x15c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x15c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x160 "IO_CONTROL_PCI_AD02,PCI_AD02 Pad Control Register" bitfld.long 0x160 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD02,VIU_DATA8,FEC_MDC,GPIO1" bitfld.long 0x160 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x160 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x164 "IO_CONTROL_PCI_AD01,PCI_AD01 Pad Control Register" bitfld.long 0x164 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD01,VIU_DATA9,FEC_MDIO,GPIO2" bitfld.long 0x164 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x164 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x168 "IO_CONTROL_PCI_AD00,PCI_AD00 Pad Control Register" bitfld.long 0x168 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_AD00,VIU_DATA10,FEC_COL,GPIO3" bitfld.long 0x168 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x168 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x16c "IO_CONTROL_PCI_C/BE0,PCI_C/BE0 Pad Control Register" bitfld.long 0x16c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_C/BE0,USB0_DATA5,DIU_LD03,GPIO4" bitfld.long 0x16c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x16c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x170 "IO_CONTROL_PCI_C/BE1,PCI_C/BE1 Pad Control Register" bitfld.long 0x170 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_C/BE1,USB0_DATA4,DIU_LD02,GPIO5" bitfld.long 0x170 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x170 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x174 "IO_CONTROL_PCI_C/BE2,PCI_C/BE2 Pad Control Register" bitfld.long 0x174 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_C/BE2,USB0_DATA3,DIU_LD00,GPIO6" bitfld.long 0x174 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x174 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x178 "IO_CONTROL_PCI_C/BE3,PCI_C/BE3 Pad Control Register" bitfld.long 0x178 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_C/BE3,USB0_DATA2,DIU_LD01,GPIO7" bitfld.long 0x178 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x178 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x17c "IO_CONTROL_/PCI_GNT2,/PCI_GNT2 Pad Control Register" bitfld.long 0x17c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_GRANT2,Reserved,DIU_LD21,GPIO8" bitfld.long 0x17c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x17c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x180 "IO_CONTROL_/PCI_REQ2,/PCI_REQ2 Pad Control Register" bitfld.long 0x180 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_REQ2,Reserved,DIU_LD20,GPIO9" bitfld.long 0x180 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x180 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x184 "IO_CONTROL_/PCI_GNT1,/PCI_GNT1 Pad Control Register" bitfld.long 0x184 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_GRANT1,Reserved,DIU_LD19,GPIO10" bitfld.long 0x184 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x184 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x188 "IO_CONTROL_/PCI_REQ1,/PCI_REQ1 Pad Control Register" bitfld.long 0x188 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_REQ1,Reserved,DIU_LD18,GPIO11" bitfld.long 0x188 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x188 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x18c "IO_CONTROL_/PCI_GNT0,/PCI_GNT0 Pad Control Register" bitfld.long 0x18c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_GRANT0,Reserved,DIU_LD12,GPIO12" bitfld.long 0x18c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x18c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x190 "IO_CONTROL_/PCI_REQ0,/PCI_REQ0 Pad Control Register" bitfld.long 0x190 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_REQ0,Reserved,DIU_LD11,GPIO13" bitfld.long 0x190 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x190 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x194 "IO_CONTROL_/PCI_INTA,/PCI_INTA Pad Control Register" bitfld.long 0x194 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_INTA,Reserved,DIU_LD15,GPIO14" bitfld.long 0x194 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x194 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x198 "IO_CONTROL_PCI_CLK,PCI_CLK Pad Control Register" bitfld.long 0x198 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_CLK,Reserved,DIU_LD14,GPIO15" bitfld.long 0x198 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x198 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x19c "IO_CONTROL_/PCI_RST_OUT,/PCI_RST_OUT Pad Control Register" bitfld.long 0x19c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_RST_OUT,Reserved,DIU_LD13,GPIO16" bitfld.long 0x19c 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x19c 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1a0 "IO_CONTROL_/PCI_FRAME,/PCI_FRAME Pad Control Register" bitfld.long 0x1a0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_FRAME,Reserved,DIU_LD10,GPIO17" bitfld.long 0x1a0 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1a0 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1a4 "IO_CONTROL_PCI_IDSEL,PCI_IDSEL Pad Control Register" bitfld.long 0x1a4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_IDSEL,Reserved,DIU_LD07,GPIO18" bitfld.long 0x1a4 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1a4 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1a8 "IO_CONTROL_/PCI_DEVSEL,/PCI_DEVSEL Pad Control Register" bitfld.long 0x1a8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_DEVSEL,Reserved,DIU_LD06,GPIO19" bitfld.long 0x1a8 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1a8 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1ac "IO_CONTROL_/PCI_IRDY,/PCI_IRDY Pad Control Register" bitfld.long 0x1ac 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_IRDY,USB0_DATA7,DIU_LD05,GPIO20" bitfld.long 0x1ac 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1ac 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1b0 "IO_CONTROL_/PCI_TRDY,/PCI_TRDY Pad Control Register" bitfld.long 0x1b0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_TRDY,USB0_DATA6,DIU_LD04,GPIO21" bitfld.long 0x1b0 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1b0 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1b4 "IO_CONTROL_/PCI_STOP,/PCI_STOP Pad Control Register" bitfld.long 0x1b4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_STOP,USB0_DATA1,DIU_LD08,GPIO22" bitfld.long 0x1b4 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1b4 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1b8 "IO_CONTROL_PCI_PAR,PCI_PAR Pad Control Register" bitfld.long 0x1b8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PCI_PAR,USB0_DATA0,DIU_LD09,GPIO23" bitfld.long 0x1b8 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1b8 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1bc "IO_CONTROL_/PCI_PERR,/PCI_PERR Pad Control Register" bitfld.long 0x1bc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_PERR,USB0_STOP,DIU_LD16,GPIO24" bitfld.long 0x1bc 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1bc 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1c0 "IO_CONTROL_/PCI_SERR,/PCI_SERR Pad Control Register" bitfld.long 0x1c0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/PCI_SERR,USB0_NEXT,DIU_LD17,GPIO25" bitfld.long 0x1c0 5.--6. " HOLD ,HOLD controls the PCI output hold delay" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" textline " " bitfld.long 0x1c0 0. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1" line.long 0x1c4 "IO_CONTROL_SPDIF_TXCLK,SPDIF_TXCLK Pad Control Register" bitfld.long 0x1c4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "SPDIF_TXCLK,FEC_RX_DV,DIU_CLK,GPIO26" bitfld.long 0x1c4 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1c4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1c8 "IO_CONTROL_SPDIF_TX,SPDIF_TX Pad Control Register" bitfld.long 0x1c8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "SPDIF_TX,FEC_TX_ER,DIU_VSYNC,GPIO27" bitfld.long 0x1c8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1cc "IO_CONTROL_SPDIF_RX,SPDIF_RX Pad Control Register" bitfld.long 0x1cc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "SPDIF_RX,FEC_CRS,DIU_HSYNC,GPIO0" bitfld.long 0x1cc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1d0 "IO_CONTROL_I2C0_SCL,I2C0_SCL Pad Control Register" bitfld.long 0x1d0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C0_SCL,Reserved,Reserved,GPIO7/GPT7" bitfld.long 0x1d0 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1d0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1d4 "IO_CONTROL_I2C0_SDA,I2C0_SDA Pad Control Register" bitfld.long 0x1d4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C0_SDA,Reserved,Reserved,GPIO1" bitfld.long 0x1d4 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1d4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1d8 "IO_CONTROL_I2C1_SCL,I2C1_SCL Pad Control Register" bitfld.long 0x1d8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C1_SCL,Reserved,SPDIF_TX,GPIO2" bitfld.long 0x1d8 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1d8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1dc "IO_CONTROL_I2C1_SDA,I2C1_SDA Pad Control Register" bitfld.long 0x1dc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C1_SDA,Reserved,SPDIF_RX,GPIO3" bitfld.long 0x1dc 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1dc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1e0 "IO_CONTROL_I2C2_SCL,I2C2_SCL Pad Control Register" bitfld.long 0x1e0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C2_SCL,Reserved,CAN4_TX,GPIO4" bitfld.long 0x1e0 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1e0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1e4 "IO_CONTROL_I2C2_SDA,I2C2_SDA Pad Control Register" bitfld.long 0x1e4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "I2C2_SDA,Reserved,CAN4_RX,GPIO5" bitfld.long 0x1e4 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1e4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1e8 "IO_CONTROL_IRQ0,IRQ0 Pad Control Register" bitfld.long 0x1e8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "IRQ0,Reserved,CAN3_TX,GPIO4/GPT4" bitfld.long 0x1e8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1ec "IO_CONTROL_IRQ1,IRQ1 Pad Control Register" bitfld.long 0x1ec 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "IRQ1,SPDIF_TXCLK,CAN3_RX,GPIO5/GPT5" bitfld.long 0x1ec 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x1ec 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1f0 "IO_CONTROL_CAN1_TX,CAN1_TX Pad Control Register" bitfld.long 0x1f0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "CAN1_TX,Reserved,Reserved,GPIO6" bitfld.long 0x1f0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1f4 "IO_CONTROL_CAN2_TX,CAN2_TX Pad Control Register" bitfld.long 0x1f4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "CAN2_TX,Reserved,Reserved,GPIO8" bitfld.long 0x1f4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1f8 "IO_CONTROL_J1850_TX,J1850_TX Pad Control Register" bitfld.long 0x1f8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "J1850_TX,Reserved,GPIO4,CAN4_TX" bitfld.long 0x1f8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x1fc "IO_CONTROL_J1850_RX,J1850_RX Pad Control Register" bitfld.long 0x1fc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "J1850_RX,CAN4_RX,/LPC_CS6,GPIO27" bitfld.long 0x1fc 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x1fc 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x1fc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x200 "IO_CONTROL_PSC_MCLK_IN,PSC_MCLK_IN Pad Control Register" bitfld.long 0x200 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC_MCLK_IN,Reserved,DIU_DE,GPIO6/GPT6" bitfld.long 0x200 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x200 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x204 "IO_CONTROL_PSC0_0,PSC0_0 Pad Control Register" bitfld.long 0x204 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC0_0,FEC_COL,USB0_DATA7,GPIO8" bitfld.long 0x204 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x204 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x208 "IO_CONTROL_PSC0_1,PSC0_1 Pad Control Register" bitfld.long 0x208 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC0_1,FEC_TX_EN,USB0_DATA6,GPIO9" bitfld.long 0x208 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x20c "IO_CONTROL_PSC0_2,PSC0_2 Pad Control Register" bitfld.long 0x20c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC0_2,FEC_TX_CLK,USB0_DATA5,GPIO10" bitfld.long 0x20c 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x20c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x210 "IO_CONTROL_PSC0_3,PSC0_3 Pad Control Register" bitfld.long 0x210 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC0_3,FEC_TXD_0,USB0_DATA4,GPIO11" bitfld.long 0x210 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x214 "IO_CONTROL_PSC0_4,PSC0_4 Pad Control Register" bitfld.long 0x214 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC0_4,FEC_TXD_1,USB0_DATA3,GPIO0/GPT0" bitfld.long 0x214 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x218 "IO_CONTROL_PSC1_0,PSC1_0 Pad Control Register" bitfld.long 0x218 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC1_0,FEC_TXD_2,USB0_DATA2,GPIO12" bitfld.long 0x218 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x218 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x21c "IO_CONTROL_PSC1_1,PSC1_1 Pad Control Register" bitfld.long 0x21c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC1_1,FEC_TXD_3,USB0_DATA1,GPIO13" bitfld.long 0x21c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x220 "IO_CONTROL_PSC1_2,PSC1_2 Pad Control Register" bitfld.long 0x220 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC1_2,FEC_MDC,USB0_DATA0,GPIO14" bitfld.long 0x220 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x224 "IO_CONTROL_PSC1_3,PSC1_3 Pad Control Register" bitfld.long 0x224 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC1_3,FEC_RX_ER,USB0_STOP,GPIO15" bitfld.long 0x224 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x228 "IO_CONTROL_PSC1_4,PSC1_4 Pad Control Register" bitfld.long 0x228 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC1_4,FEC_RXD_3,USB0_NEXT,GPIO1/GPT1" bitfld.long 0x228 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x22c "IO_CONTROL_PSC2_0,PSC2_0 Pad Control Register" bitfld.long 0x22c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC2_0,FEC_RXD_2,USB0_CLK,GPIO16" bitfld.long 0x22c 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x22c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x230 "IO_CONTROL_PSC2_1,PSC2_1 Pad Control Register" bitfld.long 0x230 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC2_1,FEC_RXD_1,USB0_DIR,GPIO17" bitfld.long 0x230 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x234 "IO_CONTROL_PSC2_2,PSC2_2 Pad Control Register" bitfld.long 0x234 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC2_2,FEC_RXD_0,Reserved,GPIO18" bitfld.long 0x234 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x238 "IO_CONTROL_PSC2_3,PSC2_3 Pad Control Register" bitfld.long 0x238 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC2_3,FEC_MDIO,Reserved,GPIO19" bitfld.long 0x238 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x23c "IO_CONTROL_PSC2_4,PSC2_4 Pad Control Register" bitfld.long 0x23c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC2_4,FEC_RX_CLK,Reserved,GPIO2/GPT2" bitfld.long 0x23c 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x23c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x240 "IO_CONTROL_PSC3_0,PSC3_0 Pad Control Register" bitfld.long 0x240 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC3_0,USB1_DATA0,Reserved,GPIO20" bitfld.long 0x240 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x240 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x244 "IO_CONTROL_PSC3_1,PSC3_1 Pad Control Register" bitfld.long 0x244 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC3_1,USB1_DATA1,Reserved,GPIO21" bitfld.long 0x244 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x248 "IO_CONTROL_PSC3_2,PSC3_2 Pad Control Register" bitfld.long 0x248 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC3_2,USB1_DATA2,Reserved,GPIO22" bitfld.long 0x248 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x24c "IO_CONTROL_PSC3_3,PSC3_3 Pad Control Register" bitfld.long 0x24c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC3_3,USB1_DATA3,Reserved,GPIO23" bitfld.long 0x24c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x250 "IO_CONTROL_PSC3_4,PSC3_4 Pad Control Register" bitfld.long 0x250 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC3_4,/LPC_CS6,VIU_PIX_CLK,GPIO3/GPT3" bitfld.long 0x250 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x254 "IO_CONTROL_PSC4_0,PSC4_0 Pad Control Register" bitfld.long 0x254 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC4_0,USB1_DATA4,VIU_DATA0,GPIO24" bitfld.long 0x254 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x254 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x258 "IO_CONTROL_PSC4_1,PSC4_1 Pad Control Register" bitfld.long 0x258 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC4_1,USB1_DATA5,VIU_DATA1,GPIO25" bitfld.long 0x258 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x25c "IO_CONTROL_PSC4_2,PSC4_2 Pad Control Register" bitfld.long 0x25c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC4_2,USB1_DATA6,VIU_DATA2,GPIO26" bitfld.long 0x25c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x260 "IO_CONTROL_PSC4_3,PSC4_3 Pad Control Register" bitfld.long 0x260 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC4_3,USB1_DATA7,VIU_DATA3,GPIO27" bitfld.long 0x260 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x264 "IO_CONTROL_PSC4_4,PSC4_4 Pad Control Register" bitfld.long 0x264 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC4_4,/NFC_CE2,VIU_DATA4,GPIO4/GPT4" bitfld.long 0x264 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x268 "IO_CONTROL_PSC5_0,PSC5_0 Pad Control Register" bitfld.long 0x268 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC5_0,USB1_CLK,VIU_DATA5,GPIO8" bitfld.long 0x268 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x268 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x26c "IO_CONTROL_PSC5_1,PSC5_1 Pad Control Register" bitfld.long 0x26c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC5_1,USB1_NEXT,VIU_DATA6,GPIO9" bitfld.long 0x26c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x270 "IO_CONTROL_PSC5_2,PSC5_2 Pad Control Register" bitfld.long 0x270 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC5_2,USB1_STOP,VIU_DATA7,GPIO10" bitfld.long 0x270 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x274 "IO_CONTROL_PSC5_3,PSC5_3 Pad Control Register" bitfld.long 0x274 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC5_3,USB1_DIR,VIU_DATA8,GPIO11" bitfld.long 0x274 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x278 "IO_CONTROL_PSC5_4,PSC5_4 Pad Control Register" bitfld.long 0x278 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC5_4,/NFC_CE3,VIU_DATA9,GPIO5/GPT5" bitfld.long 0x278 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x27c "IO_CONTROL_PSC6_0,PSC6_0 Pad Control Register" bitfld.long 0x27c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC6_0,LPC_TSIZ1,DIU_CLK,GPIO12" bitfld.long 0x27c 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x27c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x280 "IO_CONTROL_PSC6_1,PSC6_1 Pad Control Register" bitfld.long 0x280 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC6_1,LPC_TSIZ2,DIU_HSYNC,GPIO13" bitfld.long 0x280 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x284 "IO_CONTROL_PSC6_2,PSC6_2 Pad Control Register" bitfld.long 0x284 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC6_2,Reserved,Reserved,GPIO14" bitfld.long 0x284 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x288 "IO_CONTROL_PSC6_3,PSC6_3 Pad Control Register" bitfld.long 0x288 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC6_3,Reserved,Reserved,GPIO15" bitfld.long 0x288 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x28c "IO_CONTROL_PSC6_4,PSC6_4 Pad Control Register" bitfld.long 0x28c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC6_4,LPC_TS,DIU_VSYNC,GPIO6/GPT6" bitfld.long 0x28c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x290 "IO_CONTROL_PSC7_0,PSC7_0 Pad Control Register" bitfld.long 0x290 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC7_0,SDHC_CMD,DIU_LD23,GPIO16" bitfld.long 0x290 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x290 3. " PUE ,The pull usage enable" "Disabled,Enabled" bitfld.long 0x290 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x290 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x294 "IO_CONTROL_PSC7_1,PSC7_1 Pad Control Register" bitfld.long 0x294 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC7_1,SDHC_D0,DIU_LD22,GPIO17" bitfld.long 0x294 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x294 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x294 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x298 "IO_CONTROL_PSC7_2,PSC7_2 Pad Control Register" bitfld.long 0x298 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC7_2,SDHC_D1_IRQ,DIU_LD17,GPIO18" bitfld.long 0x298 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x298 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x298 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x29c "IO_CONTROL_PSC7_3,PSC7_3 Pad Control Register" bitfld.long 0x29c 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC7_3,SDHC_D2,DIU_LD16,GPIO19" bitfld.long 0x29c 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x29c 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x29c 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2a0 "IO_CONTROL_PSC7_4,PSC7_4 Pad Control Register" bitfld.long 0x2a0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC7_4,SDHC_D3_CD,DIU_LD09,GPIO7/GPT7" bitfld.long 0x2a0 4. " PUD ,PUD controls the direction of the pull resistors" "Pull-down,Pull-up" textline " " bitfld.long 0x2a0 3. " PUE ,PUE enables the pull usage" "Disabled,Enabled" bitfld.long 0x2a0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2a4 "IO_CONTROL_PSC8_0,PSC8_0 Pad Control Register" bitfld.long 0x2a4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC8_0,Reserved,DIU_LD08,GPIO20" bitfld.long 0x2a4 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x2a4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2a8 "IO_CONTROL_PSC8_1,PSC8_1 Pad Control Register" bitfld.long 0x2a8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC8_1,Reserved,DIU_LD01,GPIO21" bitfld.long 0x2a8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2ac "IO_CONTROL_PSC8_2,PSC8_2 Pad Control Register" bitfld.long 0x2ac 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC8_2,Reserved,DIU_LD00,GPIO22" bitfld.long 0x2ac 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2b0 "IO_CONTROL_PSC8_3,PSC8_3 Pad Control Register" bitfld.long 0x2b0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC8_3,Reserved,DIU_LD02,GPIO23" bitfld.long 0x2b0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2b4 "IO_CONTROL_PSC8_4,PSC8_4 Pad Control Register" bitfld.long 0x2b4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC8_4,SDHC_CLK,DIU_LD03,GPIO0/GTP0" bitfld.long 0x2b4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2b8 "IO_CONTROL_PSC9_0,PSC9_0 Pad Control Register" bitfld.long 0x2b8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC9_0,Reserved,DIU_LD04,GPIO24" bitfld.long 0x2b8 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x2b8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2bc "IO_CONTROL_PSC9_1,PSC9_1 Pad Control Register" bitfld.long 0x2bc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC9_1,Reserved,DIU_LD05,GPIO25" bitfld.long 0x2bc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2c0 "IO_CONTROL_PSC9_2,PSC9_2 Pad Control Register" bitfld.long 0x2c0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC9_2,Reserved,DIU_LD06,GPIO26" bitfld.long 0x2c0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2c4 "IO_CONTROL_PSC9_3,PSC9_3 Pad Control Register" bitfld.long 0x2c4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC9_3,Reserved,DIU_LD07,GPIO27" bitfld.long 0x2c4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2c8 "IO_CONTROL_PSC9_4,PSC9_4 Pad Control Register" bitfld.long 0x2c8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC9_4,Reserved,DIU_LD10,GPIO1/GPT1" bitfld.long 0x2c8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2cc "IO_CONTROL_PSC10_0,PSC10_0 Pad Control Register" bitfld.long 0x2cc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC10_0,Reserved,DIU_LD11,GPIO8" bitfld.long 0x2cc 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x2cc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2d0 "IO_CONTROL_PSC10_1,PSC10_1 Pad Control Register" bitfld.long 0x2d0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC10_1,Reserved,DIU_LD12,GPIO9" bitfld.long 0x2d0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2d4 "IO_CONTROL_PSC10_2,PSC10_2 Pad Control Register" bitfld.long 0x2d4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC10_2,Reserved,DIU_LD13,GPIO10" bitfld.long 0x2d4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2d8 "IO_CONTROL_PSC10_3,PSC10_3 Pad Control Register" bitfld.long 0x2d8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC10_3,Reserved,DIU_LD14,GPIO11" bitfld.long 0x2d8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2dc "IO_CONTROL_PSC10_4,PSC10_4 Pad Control Register" bitfld.long 0x2dc 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC10_4,Reserved,DIU_LD15,GPIO2/GPT2" bitfld.long 0x2dc 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2e0 "IO_CONTROL_PSC11_0,PSC11_0 Pad Control Register" bitfld.long 0x2e0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC11_0,Reserved,DIU_LD18,GPIO12" bitfld.long 0x2e0 2. " ST ,Schmitt Trigger input of the pad enable" "Disabled,Enabled" textline " " bitfld.long 0x2e0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2e4 "IO_CONTROL_PSC11_1,PSC11_1 Pad Control Register" bitfld.long 0x2e4 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC11_1,Reserved,DIU_LD19,GPIO13" bitfld.long 0x2e4 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2e8 "IO_CONTROL_PSC11_2,PSC11_2 Pad Control Register" bitfld.long 0x2e8 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC11_2,Reserved,DIU_LD20,GPIO14" bitfld.long 0x2e8 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2ec "IO_CONTROL_PSC11_3,PSC11_3 Pad Control Register" bitfld.long 0x2ec 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC11_3,Reserved,DIU_LD21,GPIO15" bitfld.long 0x2ec 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" line.long 0x2f0 "IO_CONTROL_PSC11_4,PSC11_4 Pad Control Register" bitfld.long 0x2f0 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "PSC11_4,USBPHYDBG_IDDIG,DIU_DE,GPIO3/GPT3" bitfld.long 0x2f0 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" group.long 0xa304++0x03 line.long 0x00 "IO_CONTROL_/CKSTP_OUT,/CKSTP_OUT Pad Control Register" bitfld.long 0x00 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "/CKSTP_OUT,TPA,Reserved,Reserved" bitfld.long 0x00 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" group.long 0xa310++0x03 line.long 0x00 "IO_CONTROL_USB_PHY_DRVV,USB_PHY_DRVV Pad Control Register" bitfld.long 0x00 7.--8. " FUNCMUX ,FUNCMUX controls the functional pin muxing of the pad" "USB_PHY_DRVVBUS,Reserved,Reserved,Reserved" bitfld.long 0x00 0.--1. " DS ,DS controls slew rate of General IO pad" "Configuration 0,Configuration 1,Configuration 2,Configuration 3" endif width 0xb tree.end tree "LPC (LocalPlus Bus IMMRBAR + 0x10000)" width 0xa tree "Chip Select Registers" group.long 0x10000++0x03 line.long 0x00 "CS0BCR,Chip Select 0/Boot Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x00 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x00 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x00 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x00 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x00 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x00 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x00 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x00 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x00 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x00 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x00 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RO ,Read Only" "Disabled,Enabled" group.long 0x10004++0x1b line.long 0x0 "CS1CR,Chip Select 1 Configuration Register" hexmask.long.byte 0x0 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x0 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x0 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x0 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x0 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x0 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x0 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x0 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x0 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x0 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x0 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x0 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x0 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x0 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RO ,Read Only" "Disabled,Enabled" line.long 0x4 "CS2CR,Chip Select 2 Configuration Register" hexmask.long.byte 0x4 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x4 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x4 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x4 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x4 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x4 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x4 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x4 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x4 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x4 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x4 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x4 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x4 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x4 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x4 0. " RO ,Read Only" "Disabled,Enabled" line.long 0x8 "CS3CR,Chip Select 3 Configuration Register" hexmask.long.byte 0x8 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x8 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x8 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x8 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x8 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x8 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x8 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x8 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x8 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x8 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x8 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x8 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x8 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x8 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x8 0. " RO ,Read Only" "Disabled,Enabled" line.long 0xC "CS4CR,Chip Select 4 Configuration Register" hexmask.long.byte 0xC 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0xC 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0xC 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0xC 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0xC 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0xC 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0xC 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0xC 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0xC 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0xC 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0xC 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0xC 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0xC 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0xC 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0xC 0. " RO ,Read Only" "Disabled,Enabled" line.long 0x10 "CS5CR,Chip Select 5 Configuration Register" hexmask.long.byte 0x10 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x10 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x10 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x10 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x10 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x10 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x10 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x10 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x10 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x10 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x10 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x10 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x10 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x10 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x10 0. " RO ,Read Only" "Disabled,Enabled" line.long 0x14 "CS6CR,Chip Select 6 Configuration Register" hexmask.long.byte 0x14 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x14 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x14 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x14 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x14 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x14 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x14 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x14 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x14 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x14 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x14 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x14 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x14 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x14 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x14 0. " RO ,Read Only" "Disabled,Enabled" line.long 0x18 "CS7CR,Chip Select 7 Configuration Register" hexmask.long.byte 0x18 24.--31. 1. " WaitP ,Number of Wait States to Insert" hexmask.long.byte 0x18 16.--23. 1. " WaitX ,The base number of wait states to insert or to be Combined With Waitp" textline " " bitfld.long 0x18 15. " MX ,Transaction State" "Non-muxed,Muxed" bitfld.long 0x18 14. " ALEV ,ALE Level" "Low,High" textline " " bitfld.long 0x18 13. " AA ,ACK Active" "Not active,Active" bitfld.long 0x18 12. " CE ,CS OperationFor The Corresponding CS Pin Enabe" "Disabled,Enabled" textline " " bitfld.long 0x18 10.--11. " ALEN ,ALE Length" "1 clock,2 clocks,3 clocks,4 clocks" bitfld.long 0x18 8.--9. " DS ,Data Size" "1 byte,2 bytes,Reserved,4 bytes" textline " " bitfld.long 0x18 7. " BM ,Burst Mode" "Synchronous,Asynchronous" bitfld.long 0x18 6. " ADDRM ,Address Mode" "Byte,Short/word" textline " " bitfld.long 0x18 4.--5. " WTyp ,Wait State Type Bits" "Waitx to R/W,Waitx to R/Waitp to W,Waitx to R/Waitp|Waitx to W,Waitp/Waitx to R/W" bitfld.long 0x18 3. " WS ,Write Swap" "Not occurred,Occurred" textline " " bitfld.long 0x18 2. " RS ,Read Swap" "Not occurred,Occurred" bitfld.long 0x18 1. " WO ,Write Only " "Disabled,Enabled" textline " " bitfld.long 0x18 0. " RO ,Read Only" "Disabled,Enabled" group.long 0x10020++0x017 line.long 0x00 "CSCR,Chip Select Control Register" bitfld.long 0x00 27. " IE ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " ME ,Master Enable" "Disabled,Enabled" line.long 0x04 "CSSR,Chip Select Status Register" eventfld.long 0x04 29. " WOerr ,Write-Only Error" "No Error,Error" eventfld.long 0x04 28. " ROerr ,Read-Only Error" "No Error,Error" textline " " bitfld.long 0x04 24.--26. " CSxerr ,Chip Select Error" "0,1,2,3,4,5,6,7" line.long 0x08 "CSBCR,Chip Select Burst Control Register" bitfld.long 0x08 31. " CW7 ,Chip Select 7 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 30. " SLB7 ,Chip Select 7 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 29. " BWE7 ,Chip Select 7 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 28. " BRE7 ,Chip Select 7 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 27. " CW6 ,Chip Select 6 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 26. " SLB6 ,Chip Select 6 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 25. " BWE6 ,Chip Select 6 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 24. " BRE6 ,Chip Select 6 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 23. " CW5 ,Chip Select 5 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 22. " SLB5 ,Chip Select 5 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 21. " BWE5 ,Chip Select 5 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 20. " BRE5 ,Chip Select 5 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " CW4 ,Chip Select 4 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 18. " SLB4 ,Chip Select 4 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 17. " BWE4 ,Chip Select 4 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 16. " BRE4 ,Chip Select 4 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " CW3 ,Chip Select 3 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 14. " SLB3 ,Chip Select 3 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 13. " BWE3 ,Chip Select 3 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 12. " BRE3 ,Chip Select 3 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " CW2 ,Chip Select 2 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 10. " SLB2 ,Chip Select 2 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 9. " BWE2 ,Chip Select 2 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 8. " BRE2 ,Chip Select 2 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " CW1 ,Chip Select 1 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 6. " SLB1 ,Chip Select 1 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 5. " BWE1 ,Chip Select 1 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 4. " BRE1 ,Chip Select 1 Burst Read Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " CW0 ,Chip Select 0 Cache Wrap-Capable" "No Cache,Cache" bitfld.long 0x08 2. " SLB0 ,Chip Select 0 Short/Long Burst" "Short,Long" textline " " bitfld.long 0x08 1. " BWE0 ,Chip Select 0 Burst Write Enable" "Disabled,Enabled" bitfld.long 0x08 0. " BRE0 ,Chip Select 0 Burst Read Enable" "Disabled,Enabled" line.long 0x0c "CSDCR,Chip Select Deadcycle Control Register" bitfld.long 0x0c 28.--29. " DC7 ,Chip Select 7 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x0c 24.--25. " DC6 ,Chip Select 6 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x0c 20.--21. " DC5 ,Chip Select 5 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x0c 16.--17. " DC4 ,Chip Select 4 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x0c 12.--13. " DC3 ,Chip Select 3 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x0c 8.--9. " DC2 ,Chip Select 2 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x0c 4.--5. " DC1 ,Chip Select 1 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x0c 0.--1. " DC0 ,Chip Select 0 Deadcycles" "1 cycle,2 cycle,3 cycles,4 cycles" line.long 0x10 "CSHCR,Chip Select Holdcycle Control Register" bitfld.long 0x10 28.--29. " HC7 ,Chip Select 7 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x10 24.--25. " HC6 ,Chip Select 6 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x10 20.--21. " HC5 ,Chip Select 5 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x10 16.--17. " HC4 ,Chip Select 4 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x10 12.--13. " HC3 ,Chip Select 3 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x10 8.--9. " HC2 ,Chip Select 2 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" textline " " bitfld.long 0x10 4.--5. " HC1 ,Chip Select 1 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" bitfld.long 0x10 0.--1. " HC0 ,Chip Select 0 Holdcycles" "1 cycle,2 cycle,3 cycles,4 cycles" line.long 0x14 "ALTR,Address Latch Timing Register" bitfld.long 0x14 7. " ALT7 ,Chip Select 7 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" bitfld.long 0x14 6. " ALT6 ,Chip Select 6 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" textline " " bitfld.long 0x14 5. " ALT5 ,Chip Select 5 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" bitfld.long 0x14 4. " ALT4 ,Chip Select 4 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" textline " " bitfld.long 0x14 3. " ALT3 ,Chip Select 3 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" bitfld.long 0x14 2. " ALT2 ,Chip Select 2 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" textline " " bitfld.long 0x14 1. " ALT1 ,Chip Select 1 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" bitfld.long 0x14 0. " ALT0 ,Chip Select 0 address latch timing modification for multiplexed mode" "ALE,(ALEN + 1) x LPC_CLK" tree.end tree "SCLPC Registers" group.long 0x10100++0x17 line.long 0x00 "SCLPCPC,SCLPC Packet Size Register" bitfld.long 0x00 31. " RESTART ,Restart" "No restart,Restart" hexmask.long 0x00 0.--30. 1. " Packet_Size ,The Number of Bytes SCLPC Must Transact Before Going Idle/Reset" line.long 0x04 "SCLPCSA,SCLPC Start Address Register" line.long 0x08 "SCLPCC,SCLPC Control Register" bitfld.long 0x08 24.--26. " CSX ,Chip Select Number Associated With Each DMA Transaction" "0,1,2,3,4,5,6,7" bitfld.long 0x08 17. " Flush ,The SCLPC Requestor Assertion Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " R/W ,Direction of the DMA Transaction" "Write/FIFO transmit,Read/FIFO receive" bitfld.long 0x08 8. " DAI ,Disable Auto Increment" "Enabled,Disabled" textline " " hexmask.long.byte 0x08 0.--5. 1. " BPT ,Number of Bytes Per Transaction" line.long 0x0c "SCLPCE,SCLPC Enable Register" bitfld.long 0x0C 24. " RC ,Reset Controller" "No reset,Reset" bitfld.long 0x0C 16. " RF ,Reset FIFO" "No reset,Reset" textline " " bitfld.long 0x0C 9. " AIE ,Abort Interrupt Enable" "No error,Error" bitfld.long 0x0C 8. " NIE ,Normal Interrupt Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x0C 0. " ME ,Master Enable" "No restart,Restart" line.long 0x10 "SCLPCNA,SCLPC NextAddress Register" line.long 0x14 "SCLPCS,SCLPC Status Register" eventfld.long 0x14 28. " AT ,Abort Termination" "No error,Error" eventfld.long 0x14 24. " NT ,Normal Termination" "Error,No error" rgroup.long 0x10118++0x03 line.long 0x00 "SCLPCBD,SCLPC Bytes Done Register" group.long 0x1011c++0x03 line.long 0x00 "ESWC,EMB Share and Wait Count Register" hexmask.long.word 0x00 16.--31. 1. " EMB_SHARE_COUNT ,The Length of The Time Slot Control Value" textline " " hexmask.long.byte 0x00 10.--14. 1. " NFC_WAIT_COUNT ,Indicated How Long the Bus Remains Assigned to NFC" hexmask.long.byte 0x00 5.--9. 1. " ATA_WAIT_COUNT ,Indicated How Long the Bus Remains Assigned to ATA" textline " " hexmask.long.byte 0x00 0.--4. 1. " LPC_WAIT_COUNT ,Indicated How Long the Bus Remains Assigned to LPC" group.long 0x10120++0x03 line.long 0x00 "EPC,EMB Pause Control Register" bitfld.long 0x00 1. " ATA_P ,ATA PIO Pause Disable" "Enabled,Disabled" bitfld.long 0x00 0. " LPC_P ,LPC CSB Pause Disable" "Enabled,Disabled" tree.end tree "SCLPC FIFO Registers" group.long 0x10140++0x0f line.long 0x00 "LRTFDW,LPC RX/TX FIFO Data Word Register" line.long 0x04 "LRTFS,LPC RX/TX FIFO Status Register" eventfld.long 0x04 22. " ERR ,Error" "No Error,Error" eventfld.long 0x04 21. " UF ,Underflow" "Not occurred,Occurred" textline " " eventfld.long 0x04 20. " OF ,Overflow" "Not occurred,Occurred" bitfld.long 0x04 18. " FULL ,FIFO Full " "Not full,Full" textline " " bitfld.long 0x04 17. " ALARM ,Alarm" "No alarm,Alarm" bitfld.long 0x04 16. " EMPTY ,FIFO Empty" "Not empty,Empty" line.long 0x08 "LRTFC,LPC RX/TX FIFO Control Register" bitfld.long 0x08 24.--26. " GR ,Granularity" "Waites to be full/empty,Stopped when 1 word remained,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.long 0x0c "LRTFA,LPC RX/TX FIFO Alarm Register" hexmask.long.word 0x0c 0.--9. 1. " ALARM ,Setting of Level Watermark" tree.end tree.end tree "MSCAN (IMMRBAR + 0x1300)" tree "MSCAN 0" width 0xa if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte 0x1300++0x01 line.byte 0x0 "CANCTL0,MSCAN0 Control 0 Register" eventfld.byte 0x0 7. " RXFRM ,Received Frame Flag" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Not requested,Requested" line.byte 0x01 "CANCTL1,MSCAN0 Control 1 Register" bitfld.byte 0x01 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CLKSRC ,MSCAN Clock Source" "Bus,Ips" textline " " bitfld.byte 0x01 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x01 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " BORM ,Bus-off State Recovery Mode" "Upon request,Automatic" textline " " bitfld.byte 0x01 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" bitfld.byte 0x01 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group.byte (0x1300+0x04)++0x01 line.byte 0x0 "CANBTR0,MSCAN0 Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW[1:0] ,Synchronization Jump Width" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.byte 0x0 0.--5. " BRP[5:0] ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x01 "CANBTR1,MSCAN0 Bus Timing Register 1" bitfld.byte 0x01 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x01 4.--6. " TSEG[22:20] ,Time Segment 2" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.byte 0x01 0.--3. " TSEG[13:10] ,Time Segment 1" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" group.byte (0x1300+0x08)++0x01 line.byte 0x0 "CANRFLG,MSCAN0 Receiver Flag Register" eventfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" eventfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " eventfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun" eventfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" line.byte 0x01 "CANRIER,MSCAN0 Receiver Interrupt Enable Register" bitfld.byte 0x01 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x01 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x01 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x01 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x01 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group.byte (0x1300+0x0c)++0x01 line.byte 0x0 "CANTFLG,MSCAN0 Transmitter Flag Register" eventfld.byte 0x0 2. " TXE2IF ,Transmitter Buffer Status" "Full,Empty" eventfld.byte 0x0 1. " TXE1IF ,Transmitter Buffer Status" "Full,Empty" textline " " eventfld.byte 0x0 0. " TXE0IF ,Transmitter Buffer Status" "Full,Empty" line.byte 0x01 "CANTIER,MSCAN0 Transmitter Interrupt Enable Register" bitfld.byte 0x01 2. " TXEIE2 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXEIE1 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " TXEIE0 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" group.byte (0x1300+0x10)++0x0 line.byte 0x0 "CANTARQ,MSCAN0 Transmitter Message Abort Request" bitfld.byte 0x0 2. " ABTRQ2 ,Abort Request" "Not requested,Requested" bitfld.byte 0x0 1. " ABTRQ1 ,Abort Request" "Not requested,Requested" textline " " bitfld.byte 0x0 0. " ABTRQ0 ,Abort Request" "Not requested,Requested" rgroup.byte (0x1300+0x11)++0x0 line.byte 0x0 "CANTAAK,MSCAN0 Transmitter Message Abort Acknowledge" bitfld.byte 0x0 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted" bitfld.byte 0x0 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted" textline " " bitfld.byte 0x0 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted" group.byte (0x1300+0x14)++0x1 line.byte 0x0 "CANTBSEL,MSCAN0 Transmitter Buffer Selection" bitfld.byte 0x0 2. " TX2 ,Transmit Buffer Select" "Deselected,Selected" bitfld.byte 0x0 1. " TX1 ,Transmit Buffer Select" "Deselected,Selected" textline " " bitfld.byte 0x0 0. " TX0 ,Transmit Buffer Select" "Deselected,Selected" line.byte 0x01 "CANIDAC,IMSCAN0 Identifier Acceptance Control Register" bitfld.byte 0x01 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x01 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" group.byte (0x1300+0x19)++0x0 line.byte 0x00 "CANMISC,MSCAN0 MISC Register" eventfld.byte 0x00 0. " BOFFHOLD ,Bus-off State Hold" "Not Bus-off,Bus-off" rgroup.byte (0x1300+0x1c)++0x1 line.byte 0x0 "CANRXERR,MSCAN0 Receive Error Counter Register" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN Receive Error Counter." line.byte 0x01 "CANTXERR,MSCAN0 Transmit Error Counter Register" hexmask.byte 0x01 0.--7. 1. " TxERR[7:0] ,Status of the MSCAN Transmit Error Counter." group.byte (0x1300+0x20)++0x01 line.byte 0x0 "CANIDAR0,MSCAN0 Identifier Acceptance Register 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR1,MSCAN0 Identifier Acceptance Register 1" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1300+0x24)++0x01 line.byte 0x0 "CANIDAR2,MSCAN0 Identifier Acceptance Register 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR3,MSCAN0 Identifier Acceptance Register 3" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1300+0x30)++0x01 line.byte 0x0 "CANIDAR4,MSCAN0 Identifier Acceptance Register 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR5,MSCAN0 Identifier Acceptance Register 5" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1300+0x34)++0x01 line.byte 0x0 "CANIDAR6,MSCAN0 Identifier Acceptance Register 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR7,MSCAN0 Identifier Acceptance Register 7" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1300+0x28)++0x01 line.byte 0x0 "CANIDMR0,MSCAN0 Identifier Mask Register 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR1,MSCAN0 Identifier Mask Register 1" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1300+0x2c)++0x01 line.byte 0x0 "CANIDMR2,MSCAN0 Identifier Mask Register 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR3,MSCAN0 Identifier Mask Register 3" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1300+0x38)++0x1 line.byte 0x0 "CANIDMR4,MSCAN0 Identifier Mask Register 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR5,MSCAN0 Identifier Mask Register 5" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1300+0x3c)++0x01 line.byte 0x0 "CANIDMR6,MSCAN0 Identifier Mask Register 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR7,MSCAN0 Identifier Mask Register 7" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" endif tree "Receive Message Buffers" if (((d.b(anc:(iobase()+0x1300+0x41))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1300+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN0 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "RXIDR1,MSCAN0 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x1300+0x44)++0x01 line.byte 0x0 "RXIDR2,MSCAN0 Receive Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "RXIDR3,MSCAN0 Receive Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x1300+0x41))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1300+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN0 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "RXIDR1,MSCAN0 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " RTR ,Remote Transmission Request" "Data frame,Remote frame" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x1300+0x44)++0x01 hide.byte 0x0 "RXIDR2,MSCAN0 Receive Identifier Register 2" hide.byte 0x1 "RXIDR3,MSCAN0 Receive Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x1300+0x48)++0x01 line.byte 0x00 "RXDSR0,MSCAN0 Receive Data Segment Register 0" line.byte 0x01 "RXDSR1,MSCAN0 Receive Data Segment Register 1" group.byte (0x1300+0x4C)++0x01 line.byte 0x00 "RXDSR2,MSCAN0 Receive Data Segment Register 2" line.byte 0x01 "RXDSR3,MSCAN0 Receive Data Segment Register 3" group.byte (0x1300+0x50)++0x01 line.byte 0x00 "RXDSR4,MSCAN0 Receive Data Segment Register 4" line.byte 0x01 "RXDSR5,MSCAN0 Receive Data Segment Register 5" group.byte (0x1300+0x54)++0x01 line.byte 0x00 "RXDSR6,MSCAN0 Receive Data Segment Register 6" line.byte 0x01 "RXDSR7,MSCAN0 Receive Data Segment Register 7" group.byte (0x1300+0x58)++0x0 line.byte 0x00 "RXDLR,MSCAN0 Receive Data Length Register" bitfld.byte 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.byte (0x1300+0x5c)++0x01 line.byte 0x00 "RXTSRH,MSCAN0 Receive Time Stamp Register High" line.byte 0x01 "RXTSRL,MSCAN0 Receive Time Stamp Register Low" endif tree.end tree "Transmit Message Buffers" if (((d.b(anc:(iobase()+0x1300+0x61))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1300+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN0 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "TXIDR1,MSCAN0 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x1300+0x64)++0x01 line.byte 0x0 "TXIDR2,MSCAN0 Transmit Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "TXIDR3,MSCAN0 Transmit Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x1300+0x61))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1300+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN0 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "TXIDR1,MSCAN0 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x1300+0x64)++0x01 hide.byte 0x0 "TXIDR2,MSCAN0 Transmit Identifier Register 2" hide.byte 0x1 "TXIDR3,MSCAN0 Transmit Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x1300+0x68)++0x01 line.byte 0x00 "TXDSR0,MSCAN0 Transmit Data Segment Register 0" line.byte 0x01 "TXDSR1,MSCAN0 Transmit Data Segment Register 1" group.byte (0x1300+0x6c)++0x01 line.byte 0x00 "TXDSR2,MSCAN0 Transmit Data Segment Register 2" line.byte 0x01 "TXDSR3,MSCAN0 Transmit Data Segment Register 3" group.byte (0x1300+0x70)++0x01 line.byte 0x00 "TXDSR4,MSCAN0 Transmit Data Segment Register 4" line.byte 0x01 "TXDSR5,MSCAN0 Transmit Data Segment Register 5" group.byte (0x1300+0x74)++0x01 line.byte 0x00 "TXDSR6,MSCAN0 Transmit Data Segment Register 6" line.byte 0x01 "TXDSR7,TMSCAN0 ransmit Data Segment Register 7" group.byte (0x1300+0x78)++0x01 line.byte 0x00 "TXDLR,MSCAN0 Transmit Data Length Register" bitfld.byte 0x00 0.--3. " DLR ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.byte 0x01 "TBPR,MSCAN0 Transmit Buffer Priority Register" rgroup.byte (0x1300+0x7c)++0x01 line.byte 0x00 "TXTSRH,MSCAN0 Transmit Time Stamp Register High" line.byte 0x01 "TXTSRL,MSCAN0 Transmit Time Stamp Register Low" endif tree.end tree.end tree "MSCAN 1" width 0xa if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte 0x1380++0x01 line.byte 0x0 "CANCTL0,MSCAN1 Control 0 Register" eventfld.byte 0x0 7. " RXFRM ,Received Frame Flag" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Not requested,Requested" line.byte 0x01 "CANCTL1,MSCAN1 Control 1 Register" bitfld.byte 0x01 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CLKSRC ,MSCAN Clock Source" "Bus,Ips" textline " " bitfld.byte 0x01 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x01 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " BORM ,Bus-off State Recovery Mode" "Upon request,Automatic" textline " " bitfld.byte 0x01 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" bitfld.byte 0x01 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group.byte (0x1380+0x04)++0x01 line.byte 0x0 "CANBTR0,MSCAN1 Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW[1:0] ,Synchronization Jump Width" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.byte 0x0 0.--5. " BRP[5:0] ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x01 "CANBTR1,MSCAN1 Bus Timing Register 1" bitfld.byte 0x01 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x01 4.--6. " TSEG[22:20] ,Time Segment 2" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.byte 0x01 0.--3. " TSEG[13:10] ,Time Segment 1" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" group.byte (0x1380+0x08)++0x01 line.byte 0x0 "CANRFLG,MSCAN1 Receiver Flag Register" eventfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" eventfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " eventfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun" eventfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" line.byte 0x01 "CANRIER,MSCAN1 Receiver Interrupt Enable Register" bitfld.byte 0x01 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x01 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x01 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x01 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x01 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group.byte (0x1380+0x0c)++0x01 line.byte 0x0 "CANTFLG,MSCAN1 Transmitter Flag Register" eventfld.byte 0x0 2. " TXE2IF ,Transmitter Buffer Status" "Full,Empty" eventfld.byte 0x0 1. " TXE1IF ,Transmitter Buffer Status" "Full,Empty" textline " " eventfld.byte 0x0 0. " TXE0IF ,Transmitter Buffer Status" "Full,Empty" line.byte 0x01 "CANTIER,MSCAN1 Transmitter Interrupt Enable Register" bitfld.byte 0x01 2. " TXEIE2 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXEIE1 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " TXEIE0 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" group.byte (0x1380+0x10)++0x0 line.byte 0x0 "CANTARQ,MSCAN1 Transmitter Message Abort Request" bitfld.byte 0x0 2. " ABTRQ2 ,Abort Request" "Not requested,Requested" bitfld.byte 0x0 1. " ABTRQ1 ,Abort Request" "Not requested,Requested" textline " " bitfld.byte 0x0 0. " ABTRQ0 ,Abort Request" "Not requested,Requested" rgroup.byte (0x1380+0x11)++0x0 line.byte 0x0 "CANTAAK,MSCAN1 Transmitter Message Abort Acknowledge" bitfld.byte 0x0 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted" bitfld.byte 0x0 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted" textline " " bitfld.byte 0x0 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted" group.byte (0x1380+0x14)++0x1 line.byte 0x0 "CANTBSEL,MSCAN1 Transmitter Buffer Selection" bitfld.byte 0x0 2. " TX2 ,Transmit Buffer Select" "Deselected,Selected" bitfld.byte 0x0 1. " TX1 ,Transmit Buffer Select" "Deselected,Selected" textline " " bitfld.byte 0x0 0. " TX0 ,Transmit Buffer Select" "Deselected,Selected" line.byte 0x01 "CANIDAC,IMSCAN1 Identifier Acceptance Control Register" bitfld.byte 0x01 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x01 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" group.byte (0x1380+0x19)++0x0 line.byte 0x00 "CANMISC,MSCAN1 MISC Register" eventfld.byte 0x00 0. " BOFFHOLD ,Bus-off State Hold" "Not Bus-off,Bus-off" rgroup.byte (0x1380+0x1c)++0x1 line.byte 0x0 "CANRXERR,MSCAN1 Receive Error Counter Register" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN Receive Error Counter." line.byte 0x01 "CANTXERR,MSCAN1 Transmit Error Counter Register" hexmask.byte 0x01 0.--7. 1. " TxERR[7:0] ,Status of the MSCAN Transmit Error Counter." group.byte (0x1380+0x20)++0x01 line.byte 0x0 "CANIDAR0,MSCAN1 Identifier Acceptance Register 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR1,MSCAN1 Identifier Acceptance Register 1" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1380+0x24)++0x01 line.byte 0x0 "CANIDAR2,MSCAN1 Identifier Acceptance Register 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR3,MSCAN1 Identifier Acceptance Register 3" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1380+0x30)++0x01 line.byte 0x0 "CANIDAR4,MSCAN1 Identifier Acceptance Register 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR5,MSCAN1 Identifier Acceptance Register 5" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1380+0x34)++0x01 line.byte 0x0 "CANIDAR6,MSCAN1 Identifier Acceptance Register 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR7,MSCAN1 Identifier Acceptance Register 7" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x1380+0x28)++0x01 line.byte 0x0 "CANIDMR0,MSCAN1 Identifier Mask Register 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR1,MSCAN1 Identifier Mask Register 1" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1380+0x2c)++0x01 line.byte 0x0 "CANIDMR2,MSCAN1 Identifier Mask Register 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR3,MSCAN1 Identifier Mask Register 3" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1380+0x38)++0x1 line.byte 0x0 "CANIDMR4,MSCAN1 Identifier Mask Register 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR5,MSCAN1 Identifier Mask Register 5" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x1380+0x3c)++0x01 line.byte 0x0 "CANIDMR6,MSCAN1 Identifier Mask Register 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR7,MSCAN1 Identifier Mask Register 7" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" endif tree "Receive Message Buffers" if (((d.b(anc:(iobase()+0x1380+0x41))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1380+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN1 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "RXIDR1,MSCAN1 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x1380+0x44)++0x01 line.byte 0x0 "RXIDR2,MSCAN1 Receive Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "RXIDR3,MSCAN1 Receive Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x1380+0x41))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1380+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN1 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "RXIDR1,MSCAN1 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " RTR ,Remote Transmission Request" "Data frame,Remote frame" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x1380+0x44)++0x01 hide.byte 0x0 "RXIDR2,MSCAN1 Receive Identifier Register 2" hide.byte 0x1 "RXIDR3,MSCAN1 Receive Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x1380+0x48)++0x01 line.byte 0x00 "RXDSR0,MSCAN1 Receive Data Segment Register 0" line.byte 0x01 "RXDSR1,MSCAN1 Receive Data Segment Register 1" group.byte (0x1380+0x4C)++0x01 line.byte 0x00 "RXDSR2,MSCAN1 Receive Data Segment Register 2" line.byte 0x01 "RXDSR3,MSCAN1 Receive Data Segment Register 3" group.byte (0x1380+0x50)++0x01 line.byte 0x00 "RXDSR4,MSCAN1 Receive Data Segment Register 4" line.byte 0x01 "RXDSR5,MSCAN1 Receive Data Segment Register 5" group.byte (0x1380+0x54)++0x01 line.byte 0x00 "RXDSR6,MSCAN1 Receive Data Segment Register 6" line.byte 0x01 "RXDSR7,MSCAN1 Receive Data Segment Register 7" group.byte (0x1380+0x58)++0x0 line.byte 0x00 "RXDLR,MSCAN1 Receive Data Length Register" bitfld.byte 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.byte (0x1380+0x5c)++0x01 line.byte 0x00 "RXTSRH,MSCAN1 Receive Time Stamp Register High" line.byte 0x01 "RXTSRL,MSCAN1 Receive Time Stamp Register Low" endif tree.end tree "Transmit Message Buffers" if (((d.b(anc:(iobase()+0x1380+0x61))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1380+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN1 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "TXIDR1,MSCAN1 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x1380+0x64)++0x01 line.byte 0x0 "TXIDR2,MSCAN1 Transmit Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "TXIDR3,MSCAN1 Transmit Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x1380+0x61))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x1380+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN1 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "TXIDR1,MSCAN1 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x1380+0x64)++0x01 hide.byte 0x0 "TXIDR2,MSCAN1 Transmit Identifier Register 2" hide.byte 0x1 "TXIDR3,MSCAN1 Transmit Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x1380+0x68)++0x01 line.byte 0x00 "TXDSR0,MSCAN1 Transmit Data Segment Register 0" line.byte 0x01 "TXDSR1,MSCAN1 Transmit Data Segment Register 1" group.byte (0x1380+0x6c)++0x01 line.byte 0x00 "TXDSR2,MSCAN1 Transmit Data Segment Register 2" line.byte 0x01 "TXDSR3,MSCAN1 Transmit Data Segment Register 3" group.byte (0x1380+0x70)++0x01 line.byte 0x00 "TXDSR4,MSCAN1 Transmit Data Segment Register 4" line.byte 0x01 "TXDSR5,MSCAN1 Transmit Data Segment Register 5" group.byte (0x1380+0x74)++0x01 line.byte 0x00 "TXDSR6,MSCAN1 Transmit Data Segment Register 6" line.byte 0x01 "TXDSR7,TMSCAN1 ransmit Data Segment Register 7" group.byte (0x1380+0x78)++0x01 line.byte 0x00 "TXDLR,MSCAN1 Transmit Data Length Register" bitfld.byte 0x00 0.--3. " DLR ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.byte 0x01 "TBPR,MSCAN1 Transmit Buffer Priority Register" rgroup.byte (0x1380+0x7c)++0x01 line.byte 0x00 "TXTSRH,MSCAN1 Transmit Time Stamp Register High" line.byte 0x01 "TXTSRL,MSCAN1 Transmit Time Stamp Register Low" endif tree.end tree.end tree "MSCAN 2" width 0xa if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte 0x2300++0x01 line.byte 0x0 "CANCTL0,MSCAN2 Control 0 Register" eventfld.byte 0x0 7. " RXFRM ,Received Frame Flag" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Not requested,Requested" line.byte 0x01 "CANCTL1,MSCAN2 Control 1 Register" bitfld.byte 0x01 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CLKSRC ,MSCAN Clock Source" "Bus,Ips" textline " " bitfld.byte 0x01 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x01 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " BORM ,Bus-off State Recovery Mode" "Upon request,Automatic" textline " " bitfld.byte 0x01 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" bitfld.byte 0x01 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group.byte (0x2300+0x04)++0x01 line.byte 0x0 "CANBTR0,MSCAN2 Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW[1:0] ,Synchronization Jump Width" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.byte 0x0 0.--5. " BRP[5:0] ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x01 "CANBTR1,MSCAN2 Bus Timing Register 1" bitfld.byte 0x01 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x01 4.--6. " TSEG[22:20] ,Time Segment 2" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.byte 0x01 0.--3. " TSEG[13:10] ,Time Segment 1" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" group.byte (0x2300+0x08)++0x01 line.byte 0x0 "CANRFLG,MSCAN2 Receiver Flag Register" eventfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" eventfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " eventfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun" eventfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" line.byte 0x01 "CANRIER,MSCAN2 Receiver Interrupt Enable Register" bitfld.byte 0x01 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x01 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x01 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x01 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x01 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group.byte (0x2300+0x0c)++0x01 line.byte 0x0 "CANTFLG,MSCAN2 Transmitter Flag Register" eventfld.byte 0x0 2. " TXE2IF ,Transmitter Buffer Status" "Full,Empty" eventfld.byte 0x0 1. " TXE1IF ,Transmitter Buffer Status" "Full,Empty" textline " " eventfld.byte 0x0 0. " TXE0IF ,Transmitter Buffer Status" "Full,Empty" line.byte 0x01 "CANTIER,MSCAN2 Transmitter Interrupt Enable Register" bitfld.byte 0x01 2. " TXEIE2 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXEIE1 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " TXEIE0 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" group.byte (0x2300+0x10)++0x0 line.byte 0x0 "CANTARQ,MSCAN2 Transmitter Message Abort Request" bitfld.byte 0x0 2. " ABTRQ2 ,Abort Request" "Not requested,Requested" bitfld.byte 0x0 1. " ABTRQ1 ,Abort Request" "Not requested,Requested" textline " " bitfld.byte 0x0 0. " ABTRQ0 ,Abort Request" "Not requested,Requested" rgroup.byte (0x2300+0x11)++0x0 line.byte 0x0 "CANTAAK,MSCAN2 Transmitter Message Abort Acknowledge" bitfld.byte 0x0 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted" bitfld.byte 0x0 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted" textline " " bitfld.byte 0x0 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted" group.byte (0x2300+0x14)++0x1 line.byte 0x0 "CANTBSEL,MSCAN2 Transmitter Buffer Selection" bitfld.byte 0x0 2. " TX2 ,Transmit Buffer Select" "Deselected,Selected" bitfld.byte 0x0 1. " TX1 ,Transmit Buffer Select" "Deselected,Selected" textline " " bitfld.byte 0x0 0. " TX0 ,Transmit Buffer Select" "Deselected,Selected" line.byte 0x01 "CANIDAC,IMSCAN2 Identifier Acceptance Control Register" bitfld.byte 0x01 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x01 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" group.byte (0x2300+0x19)++0x0 line.byte 0x00 "CANMISC,MSCAN2 MISC Register" eventfld.byte 0x00 0. " BOFFHOLD ,Bus-off State Hold" "Not Bus-off,Bus-off" rgroup.byte (0x2300+0x1c)++0x1 line.byte 0x0 "CANRXERR,MSCAN2 Receive Error Counter Register" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN Receive Error Counter." line.byte 0x01 "CANTXERR,MSCAN2 Transmit Error Counter Register" hexmask.byte 0x01 0.--7. 1. " TxERR[7:0] ,Status of the MSCAN Transmit Error Counter." group.byte (0x2300+0x20)++0x01 line.byte 0x0 "CANIDAR0,MSCAN2 Identifier Acceptance Register 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR1,MSCAN2 Identifier Acceptance Register 1" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2300+0x24)++0x01 line.byte 0x0 "CANIDAR2,MSCAN2 Identifier Acceptance Register 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR3,MSCAN2 Identifier Acceptance Register 3" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2300+0x30)++0x01 line.byte 0x0 "CANIDAR4,MSCAN2 Identifier Acceptance Register 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR5,MSCAN2 Identifier Acceptance Register 5" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2300+0x34)++0x01 line.byte 0x0 "CANIDAR6,MSCAN2 Identifier Acceptance Register 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR7,MSCAN2 Identifier Acceptance Register 7" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2300+0x28)++0x01 line.byte 0x0 "CANIDMR0,MSCAN2 Identifier Mask Register 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR1,MSCAN2 Identifier Mask Register 1" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2300+0x2c)++0x01 line.byte 0x0 "CANIDMR2,MSCAN2 Identifier Mask Register 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR3,MSCAN2 Identifier Mask Register 3" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2300+0x38)++0x1 line.byte 0x0 "CANIDMR4,MSCAN2 Identifier Mask Register 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR5,MSCAN2 Identifier Mask Register 5" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2300+0x3c)++0x01 line.byte 0x0 "CANIDMR6,MSCAN2 Identifier Mask Register 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR7,MSCAN2 Identifier Mask Register 7" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" endif tree "Receive Message Buffers" if (((d.b(anc:(iobase()+0x2300+0x41))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2300+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN2 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "RXIDR1,MSCAN2 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x2300+0x44)++0x01 line.byte 0x0 "RXIDR2,MSCAN2 Receive Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "RXIDR3,MSCAN2 Receive Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x2300+0x41))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2300+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN2 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "RXIDR1,MSCAN2 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " RTR ,Remote Transmission Request" "Data frame,Remote frame" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x2300+0x44)++0x01 hide.byte 0x0 "RXIDR2,MSCAN2 Receive Identifier Register 2" hide.byte 0x1 "RXIDR3,MSCAN2 Receive Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x2300+0x48)++0x01 line.byte 0x00 "RXDSR0,MSCAN2 Receive Data Segment Register 0" line.byte 0x01 "RXDSR1,MSCAN2 Receive Data Segment Register 1" group.byte (0x2300+0x4C)++0x01 line.byte 0x00 "RXDSR2,MSCAN2 Receive Data Segment Register 2" line.byte 0x01 "RXDSR3,MSCAN2 Receive Data Segment Register 3" group.byte (0x2300+0x50)++0x01 line.byte 0x00 "RXDSR4,MSCAN2 Receive Data Segment Register 4" line.byte 0x01 "RXDSR5,MSCAN2 Receive Data Segment Register 5" group.byte (0x2300+0x54)++0x01 line.byte 0x00 "RXDSR6,MSCAN2 Receive Data Segment Register 6" line.byte 0x01 "RXDSR7,MSCAN2 Receive Data Segment Register 7" group.byte (0x2300+0x58)++0x0 line.byte 0x00 "RXDLR,MSCAN2 Receive Data Length Register" bitfld.byte 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.byte (0x2300+0x5c)++0x01 line.byte 0x00 "RXTSRH,MSCAN2 Receive Time Stamp Register High" line.byte 0x01 "RXTSRL,MSCAN2 Receive Time Stamp Register Low" endif tree.end tree "Transmit Message Buffers" if (((d.b(anc:(iobase()+0x2300+0x61))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2300+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN2 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "TXIDR1,MSCAN2 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x2300+0x64)++0x01 line.byte 0x0 "TXIDR2,MSCAN2 Transmit Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "TXIDR3,MSCAN2 Transmit Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x2300+0x61))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2300+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN2 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "TXIDR1,MSCAN2 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x2300+0x64)++0x01 hide.byte 0x0 "TXIDR2,MSCAN2 Transmit Identifier Register 2" hide.byte 0x1 "TXIDR3,MSCAN2 Transmit Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x2300+0x68)++0x01 line.byte 0x00 "TXDSR0,MSCAN2 Transmit Data Segment Register 0" line.byte 0x01 "TXDSR1,MSCAN2 Transmit Data Segment Register 1" group.byte (0x2300+0x6c)++0x01 line.byte 0x00 "TXDSR2,MSCAN2 Transmit Data Segment Register 2" line.byte 0x01 "TXDSR3,MSCAN2 Transmit Data Segment Register 3" group.byte (0x2300+0x70)++0x01 line.byte 0x00 "TXDSR4,MSCAN2 Transmit Data Segment Register 4" line.byte 0x01 "TXDSR5,MSCAN2 Transmit Data Segment Register 5" group.byte (0x2300+0x74)++0x01 line.byte 0x00 "TXDSR6,MSCAN2 Transmit Data Segment Register 6" line.byte 0x01 "TXDSR7,TMSCAN2 ransmit Data Segment Register 7" group.byte (0x2300+0x78)++0x01 line.byte 0x00 "TXDLR,MSCAN2 Transmit Data Length Register" bitfld.byte 0x00 0.--3. " DLR ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.byte 0x01 "TBPR,MSCAN2 Transmit Buffer Priority Register" rgroup.byte (0x2300+0x7c)++0x01 line.byte 0x00 "TXTSRH,MSCAN2 Transmit Time Stamp Register High" line.byte 0x01 "TXTSRL,MSCAN2 Transmit Time Stamp Register Low" endif tree.end tree.end tree "MSCAN 3" width 0xa if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte 0x2380++0x01 line.byte 0x0 "CANCTL0,MSCAN3 Control 0 Register" eventfld.byte 0x0 7. " RXFRM ,Received Frame Flag" "No valid message,Valid message" bitfld.byte 0x0 6. " RXACT ,Receiver Active Status" "Transmitting,Receiving" textline " " bitfld.byte 0x0 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized" textline " " bitfld.byte 0x0 3. " TIME ,Timer Enable" "Disabled,Enabled" bitfld.byte 0x0 2. " WUPE ,WakeUp Enable" "Disabled,Enabled" textline " " bitfld.byte 0x0 1. " SLPRQ ,Sleep Mode Request" "Running,Sleep mode" bitfld.byte 0x0 0. " INITRQ ,Initialization Mode Request" "Not requested,Requested" line.byte 0x01 "CANCTL1,MSCAN3 Control 1 Register" bitfld.byte 0x01 7. " CANE ,MSCAN Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CLKSRC ,MSCAN Clock Source" "Bus,Ips" textline " " bitfld.byte 0x01 5. " LOOPB ,Loop-Back Self-Test Mode" "Disabled,Enabled" bitfld.byte 0x01 4. " LISTEN ,Listen-Only Mode" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " BORM ,Bus-off State Recovery Mode" "Upon request,Automatic" textline " " bitfld.byte 0x01 1. " SLPAK ,Sleep Mode Acknowledge" "Running,Sleep mode" bitfld.byte 0x01 0. " INITAK ,Initialization Mode Acknowledge" "Running,Initialization mode" group.byte (0x2380+0x04)++0x01 line.byte 0x0 "CANBTR0,MSCAN3 Bus Timing Register 0" bitfld.byte 0x0 6.--7. " SJW[1:0] ,Synchronization Jump Width" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.byte 0x0 0.--5. " BRP[5:0] ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x01 "CANBTR1,MSCAN3 Bus Timing Register 1" bitfld.byte 0x01 7. " SAMP ,Sampling" "One sample,Three samples" bitfld.byte 0x01 4.--6. " TSEG[22:20] ,Time Segment 2" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.byte 0x01 0.--3. " TSEG[13:10] ,Time Segment 1" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" group.byte (0x2380+0x08)++0x01 line.byte 0x0 "CANRFLG,MSCAN3 Receiver Flag Register" eventfld.byte 0x0 7. " WUPIF ,WakeUp Interrupt Flag" "No wakeup,Wakeup" eventfld.byte 0x0 6. " CSCIF ,CAN Status Change Interrupt Flag" "Not changed,Changed" textline " " bitfld.byte 0x0 4.--5. " RSTAT ,Receiver Status bits" "RxOK,RxWRN,RxERR,BusOff" bitfld.byte 0x0 2.--3. " TSTAT ,Transmitter Status bits" "TxOK,TxWRN,TxERR,BusOff" textline " " eventfld.byte 0x0 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun" eventfld.byte 0x0 0. " RXF ,Receive Buffer Full" "No new message,New message" line.byte 0x01 "CANRIER,MSCAN3 Receiver Interrupt Enable Register" bitfld.byte 0x01 7. " WUPIE ,WakeUp Interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " CSCIE ,CAN Status Change Interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x01 4.--5. " RSTATE ,Receiver Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" bitfld.byte 0x01 2.--3. " TSTATE ,Transmitter Status Change Enable" "No CSCIF,CSCIF,CSCIF,CSCIF" textline " " bitfld.byte 0x01 1. " OVRIE ,Overrun Interrupt" "Disabled,Enabled" bitfld.byte 0x01 0. " RXFIE ,Receiver Full Interrupt" "Disabled,Enabled" group.byte (0x2380+0x0c)++0x01 line.byte 0x0 "CANTFLG,MSCAN3 Transmitter Flag Register" eventfld.byte 0x0 2. " TXE2IF ,Transmitter Buffer Status" "Full,Empty" eventfld.byte 0x0 1. " TXE1IF ,Transmitter Buffer Status" "Full,Empty" textline " " eventfld.byte 0x0 0. " TXE0IF ,Transmitter Buffer Status" "Full,Empty" line.byte 0x01 "CANTIER,MSCAN3 Transmitter Interrupt Enable Register" bitfld.byte 0x01 2. " TXEIE2 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXEIE1 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " TXEIE0 ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" group.byte (0x2380+0x10)++0x0 line.byte 0x0 "CANTARQ,MSCAN3 Transmitter Message Abort Request" bitfld.byte 0x0 2. " ABTRQ2 ,Abort Request" "Not requested,Requested" bitfld.byte 0x0 1. " ABTRQ1 ,Abort Request" "Not requested,Requested" textline " " bitfld.byte 0x0 0. " ABTRQ0 ,Abort Request" "Not requested,Requested" rgroup.byte (0x2380+0x11)++0x0 line.byte 0x0 "CANTAAK,MSCAN3 Transmitter Message Abort Acknowledge" bitfld.byte 0x0 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted" bitfld.byte 0x0 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted" textline " " bitfld.byte 0x0 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted" group.byte (0x2380+0x14)++0x1 line.byte 0x0 "CANTBSEL,MSCAN3 Transmitter Buffer Selection" bitfld.byte 0x0 2. " TX2 ,Transmit Buffer Select" "Deselected,Selected" bitfld.byte 0x0 1. " TX1 ,Transmit Buffer Select" "Deselected,Selected" textline " " bitfld.byte 0x0 0. " TX0 ,Transmit Buffer Select" "Deselected,Selected" line.byte 0x01 "CANIDAC,IMSCAN3 Identifier Acceptance Control Register" bitfld.byte 0x01 4.--5. " IDAM[1:0] ,Identifier Acceptance Mode" "32-bit,16-bit,8-bit,Closed" bitfld.byte 0x01 0.--2. " IDHIT[2:0] ,Identifier Acceptance Hit Indicator" "Filter 0,Filter 1,Filter 2,Filter 3,Filter 4,Filter 5,Filter 6,Filter 7" group.byte (0x2380+0x19)++0x0 line.byte 0x00 "CANMISC,MSCAN3 MISC Register" eventfld.byte 0x00 0. " BOFFHOLD ,Bus-off State Hold" "Not Bus-off,Bus-off" rgroup.byte (0x2380+0x1c)++0x1 line.byte 0x0 "CANRXERR,MSCAN3 Receive Error Counter Register" hexmask.byte 0x0 0.--7. 1. " RxERR[7:0] ,Status of the MSCAN Receive Error Counter." line.byte 0x01 "CANTXERR,MSCAN3 Transmit Error Counter Register" hexmask.byte 0x01 0.--7. 1. " TxERR[7:0] ,Status of the MSCAN Transmit Error Counter." group.byte (0x2380+0x20)++0x01 line.byte 0x0 "CANIDAR0,MSCAN3 Identifier Acceptance Register 0" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR1,MSCAN3 Identifier Acceptance Register 1" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2380+0x24)++0x01 line.byte 0x0 "CANIDAR2,MSCAN3 Identifier Acceptance Register 2" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR3,MSCAN3 Identifier Acceptance Register 3" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2380+0x30)++0x01 line.byte 0x0 "CANIDAR4,MSCAN3 Identifier Acceptance Register 4" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR5,MSCAN3 Identifier Acceptance Register 5" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2380+0x34)++0x01 line.byte 0x0 "CANIDAR6,MSCAN3 Identifier Acceptance Register 6" hexmask.byte 0x0 0.--7. 1. " AC[7:0] ,Acceptance Code" line.byte 0x01 "CANIDAR7,MSCAN3 Identifier Acceptance Register 7" hexmask.byte 0x01 0.--7. 1. " AC[7:0] ,Acceptance Code" group.byte (0x2380+0x28)++0x01 line.byte 0x0 "CANIDMR0,MSCAN3 Identifier Mask Register 0" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR1,MSCAN3 Identifier Mask Register 1" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2380+0x2c)++0x01 line.byte 0x0 "CANIDMR2,MSCAN3 Identifier Mask Register 2" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR3,MSCAN3 Identifier Mask Register 3" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2380+0x38)++0x1 line.byte 0x0 "CANIDMR4,MSCAN3 Identifier Mask Register 4" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR5,MSCAN3 Identifier Mask Register 5" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" group.byte (0x2380+0x3c)++0x01 line.byte 0x0 "CANIDMR6,MSCAN3 Identifier Mask Register 6" bitfld.byte 0x0 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x0 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x0 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" line.byte 0x01 "CANIDMR7,MSCAN3 Identifier Mask Register 7" bitfld.byte 0x01 7. " AM[7] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 6. " AM[6] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 5. " AM[5] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 4. " AM[4] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 3. " AM[3] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 2. " AM[2] ,Acceptance Mask" "Matched,Ignored" textline " " bitfld.byte 0x01 1. " AM[1] ,Acceptance Mask" "Matched,Ignored" bitfld.byte 0x01 0. " AM[0] ,Acceptance Mask" "Matched,Ignored" endif tree "Receive Message Buffers" if (((d.b(anc:(iobase()+0x2380+0x41))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2380+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN3 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "RXIDR1,MSCAN3 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x2380+0x44)++0x01 line.byte 0x0 "RXIDR2,MSCAN3 Receive Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "RXIDR3,MSCAN3 Receive Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x2380+0x41))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2380+0x40)++0x01 line.byte 0x0 "RXIDR0,MSCAN3 Receive Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "RXIDR1,MSCAN3 Receive Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " RTR ,Remote Transmission Request" "Data frame,Remote frame" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x2380+0x44)++0x01 hide.byte 0x0 "RXIDR2,MSCAN3 Receive Identifier Register 2" hide.byte 0x1 "RXIDR3,MSCAN3 Receive Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x2380+0x48)++0x01 line.byte 0x00 "RXDSR0,MSCAN3 Receive Data Segment Register 0" line.byte 0x01 "RXDSR1,MSCAN3 Receive Data Segment Register 1" group.byte (0x2380+0x4C)++0x01 line.byte 0x00 "RXDSR2,MSCAN3 Receive Data Segment Register 2" line.byte 0x01 "RXDSR3,MSCAN3 Receive Data Segment Register 3" group.byte (0x2380+0x50)++0x01 line.byte 0x00 "RXDSR4,MSCAN3 Receive Data Segment Register 4" line.byte 0x01 "RXDSR5,MSCAN3 Receive Data Segment Register 5" group.byte (0x2380+0x54)++0x01 line.byte 0x00 "RXDSR6,MSCAN3 Receive Data Segment Register 6" line.byte 0x01 "RXDSR7,MSCAN3 Receive Data Segment Register 7" group.byte (0x2380+0x58)++0x0 line.byte 0x00 "RXDLR,MSCAN3 Receive Data Length Register" bitfld.byte 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.byte (0x2380+0x5c)++0x01 line.byte 0x00 "RXTSRH,MSCAN3 Receive Time Stamp Register High" line.byte 0x01 "RXTSRL,MSCAN3 Receive Time Stamp Register Low" endif tree.end tree "Transmit Message Buffers" if (((d.b(anc:(iobase()+0x2380+0x61))&0x8)==0x8)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2380+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN3 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[28:21] ,Extended format identifier" line.byte 0x1 "TXIDR1,MSCAN3 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[20:18] ,Extended format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" bitfld.byte 0x1 0.--2. " ID[17:15] ,Extended format identifier" "0,1,2,3,4,5,6,7" group.byte (0x2380+0x64)++0x01 line.byte 0x0 "TXIDR2,MSCAN3 Transmit Identifier Register 2" hexmask.byte 0x0 0.--7. 1. " ID[14:7] ,Extended Format Identifier" line.byte 0x01 "TXIDR3,MSCAN3 Transmit Identifier Register 3" hexmask.byte 0x01 1.--7. 1. " ID[6:0] ,Standard format identifier" bitfld.byte 0x01 0. " RTR ,Remote Transmission Request" "Data,Remote" elif (((d.b(anc:(iobase()+0x2380+0x61))&0x8)==0x0)&&((d.l(ANC:iobase()+0xf08)&(0x02000000))!=0)) group.byte (0x2380+0x60)++0x01 line.byte 0x0 "TXIDR0,MSCAN3 Transmit Identifier Register 0" hexmask.byte 0x0 0.--7. 1. " ID[10:3] ,Standart format identifier" line.byte 0x1 "TXIDR1,MSCAN3 Transmit Identifier Register 1" bitfld.byte 0x1 5.--7. " ID[2:0] ,Standart format identifier" "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. " SRR ,Substitute Remote Request" "Not requested,Requested" textline " " bitfld.byte 0x1 3. " IDE ,ID Extended" "Standard,Extended" hgroup.byte (0x2380+0x64)++0x01 hide.byte 0x0 "TXIDR2,MSCAN3 Transmit Identifier Register 2" hide.byte 0x1 "TXIDR3,MSCAN3 Transmit Identifier Register 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf08)&0x02000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.byte (0x2380+0x68)++0x01 line.byte 0x00 "TXDSR0,MSCAN3 Transmit Data Segment Register 0" line.byte 0x01 "TXDSR1,MSCAN3 Transmit Data Segment Register 1" group.byte (0x2380+0x6c)++0x01 line.byte 0x00 "TXDSR2,MSCAN3 Transmit Data Segment Register 2" line.byte 0x01 "TXDSR3,MSCAN3 Transmit Data Segment Register 3" group.byte (0x2380+0x70)++0x01 line.byte 0x00 "TXDSR4,MSCAN3 Transmit Data Segment Register 4" line.byte 0x01 "TXDSR5,MSCAN3 Transmit Data Segment Register 5" group.byte (0x2380+0x74)++0x01 line.byte 0x00 "TXDSR6,MSCAN3 Transmit Data Segment Register 6" line.byte 0x01 "TXDSR7,TMSCAN3 ransmit Data Segment Register 7" group.byte (0x2380+0x78)++0x01 line.byte 0x00 "TXDLR,MSCAN3 Transmit Data Length Register" bitfld.byte 0x00 0.--3. " DLR ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.byte 0x01 "TBPR,MSCAN3 Transmit Buffer Priority Register" rgroup.byte (0x2380+0x7c)++0x01 line.byte 0x00 "TXTSRH,MSCAN3 Transmit Time Stamp Register High" line.byte 0x01 "TXTSRL,MSCAN3 Transmit Time Stamp Register Low" endif tree.end tree.end tree.end tree "NFC (NAND Flash Controller NFCBAR)" base anc:Data.Long(ANC:(iobase()+0x000C8)) sif CPU()=="MPC5125" width 0x15 if (data.long(ANC:iobase()+0xf04)&0x20000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long (0x00000000+0x3f00)++0x03 line.long 0x00 "FLASH_CMD1,Flash Command 1 Register" hexmask.long.byte 0x00 24.--31. 1. 0. "FLASH_CMD_BYTE2 ,Second command byte that may be sent to flash device" hexmask.long.byte 0x00 16.--23. 1. 0. " FLASH_CMD_BYTE3 ,Third command byte that may be sent to flash device" group.long (0x00000000+0x3f04)++0x03 line.long 0x00 "FLASH_CMD2,Flash Command 2 Register" hexmask.long.byte 0x00 24.--31. 1. 0. "FLASH_CMD_BYTE1 ,First command byte that may be sent to flash device" hexmask.long.word 0x00 08.--23. 1. 0. " FLASH_CMD_CODE ,User defined flash operation sequencer" textline " " bitfld.long 0x00 00.--01. " BUFNO ,Internal buffer number used for this command" "0,1,2,3" group.long (0x00000000+0x3f08)++0x03 line.long 0x00 "COL_ADDR,Column Address Register" hexmask.long.byte 0x00 08.--15. 1. 0. "COL_ADDR2 ,Second byte of column address" hexmask.long.byte 0x00 00.--07. 1. 0. " COL_ADDR1 ,First byte of column address" group.long (0x00000000+0x3f0C)++0x03 line.long 0x00 "ROW_ADDR,Row Address Register" bitfld.long 0x00 28.--31. "CHIP_SEL_RB ,The field CHIP_SEL determines which NFC_CE line will go low" "----,---0,--1-,--10,-2--,-2-0,-21-,-210,3---,3--0,3-1-,3-10,32--,32-0,321-,3210" bitfld.long 0x00 24.--27. " CHIP_SEL ,Chip select - Bit mask to enable/disable each of the four chip selects" "----,---0,--1-,--10,-2--,-2-0,-21-,-210,3---,3--0,3-1-,3-10,32--,32-0,321-,3210" textline " " hexmask.long.byte 0x00 16.--23. 1. 0. " ROW_ADDR3 ,Third byte of row address" hexmask.long.byte 0x00 08.--15. 1. 0. " ROW_ADDR2 ,Second byte of row address" hexmask.long.byte 0x00 00.--07. 1. 0. " ROW_ADDR1 ,Third byte of row address" group.long (0x00000000+0x3f10)++0x03 line.long 0x00 "FLASH_COMMAND_REPEAT,Flash Command Repeat Register" hexmask.long.word 0x00 00.--15. 1. 0. "REPEAT_COUNT ,Determines how many times FLASH_CMD_CODE in FLASH_CMD2 is executed. If 0 or 1, flash command is executed once" group.long (0x00000000+0x3f14)++0x03 line.long 0x00 "ROW_ADDR_INC,Row Address Increment register" hexmask.long.byte 0x00 16.--23. 1. 0. "ROW_ADDR3_INC ,Increment for the third byte of row address" hexmask.long.byte 0x00 08.--15. 1. 0. " ROW_ADDR2_INC ,Increment for the second byte of row address" hexmask.long.byte 0x00 00.--07. 1. 0. " ROW_ADDR1_INC ,Increment for the first byte of row address" group.long (0x00000000+0x3f18)++0x03 line.long 0x00 "FLASH_STATUS1,Flash Status 1 Register" hexmask.long.byte 0x00 24.--31. 1. 0. "ID_BYTE1 ,First byte returned by read ID command" hexmask.long.byte 0x00 16.--23. 1. 0. " ID_BYTE2 ,Second byte returned by read ID command" textline " " hexmask.long.byte 0x00 08.--15. 1. 0. " ID_BYTE3 ,Third byte returned by read ID command" hexmask.long.byte 0x00 00.--07. 1. 0. " ID_BYTE4 ,Fourth byte returned by read ID command" group.long (0x00000000+0x3f1c)++0x03 line.long 0x00 "FLASH_STATUS2,Flash Status 2 Register" hexmask.long.byte 0x00 24.--31. 1. 0. "ID_BYTE5 ,Fifth byte returned by read ID command" hexmask.long.byte 0x00 00.--07. 1. 0. " STATUS_BYTE1 ,Byte returned by read status command" group.long (0x00000000+0x3f20)++0x03 line.long 0x00 "DMA1_ADDR,DMA1 Address register" group.long (0x00000000+0x3f24)++0x03 line.long 0x00 "DMA_CONFIG,DMA Configuration register" hexmask.long.word 0x00 20.--31. 1. 0. "DMA1_CNT ,Byte count to be transferred by DMA for DMA channel 1" hexmask.long.word 0x00 13.--19. 1. 0. " DMA2_CNT ,Byte count to be transferred by DMA for DMA channel 2" textline " " hexmask.long.word 0x00 02.--12. 2. 0. " DMA2_OFFSET ,Byte offset for DMA channel 2" textline " " bitfld.long 0x00 01. " DMA1_ACT ,DMA Channel 1 Activity" "inactive,active" bitfld.long 0x00 00. " DMA2_ACT ,DMA Channel 2 Activity" "inactive,active" group.long (0x00000000+0x3f28)++0x03 line.long 0x00 "CACHE_SWAP,Cache Swap register" hexmask.long.word 0x00 17.--27. 8. 0. "CACHE_SWAP_ADDR2 ,Upper swap address" hexmask.long.word 0x00 01.--11. 8. 0. " CACHE_SWAP_ADDR1 ,Lower swap address" group.long (0x00000000+0x3f2C)++0x03 line.long 0x00 "SECTOR_SIZE,Sector Size register" hexmask.long.word 0x00 00.--12. 1. 0. "SECTOR_SIZE ,Size in bytes of one elementary transfer unit" group.long (0x00000000+0x3f30)++0x03 line.long 0x00 "FLASH_CONFIG,Flash Configuration register" bitfld.long 0x00 31. "STOP_ON_WERR ,Stop on Write Error" " no, yes" hexmask.long.word 0x00 22.--30. 8. 0. " ECC_SRAM_ADDR ,Byte address in SRAM where ECC status is written" textline " " bitfld.long 0x00 21. " ECC_SRAM_REQ ,Write ECC status to SRAM" " no, yes" bitfld.long 0x00 20. " DMA_REQ ,After ECC done transfer sector using DMA" " no, yes" textline " " bitfld.long 0x00 17.--19. " ECC_MODE ,ECC mode" "disabled, 4-ECC, 6-ECC, 8-ECC, 12-ECC, 16-ECC, 24-ECC, 32-ECC" bitfld.long 0x00 16. " FAST_FLASH ,Fast flash timing. Clock in read data 1/2 clock later than rising edge of read strobe" " no, yes" textline " " bitfld.long 0x00 13.--15. " ID_COUNT ,Number of bytes that will be read for the read id command" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 08.--12. 1. 0. " CMD_TIMEOUT ,The number of flash_clk cycles from NFC_WE high to NAND flash busy (tWB) or from NFC_WE high to NFC_RE low (tWHR)" textline " " bitfld.long 0x00 07. " 16BIT ,8/16-bit wide flash mode" " 8-bit,16-bit" bitfld.long 0x00 06. " BOOT_MODE ,Boot mode" "normal, boot" textline " " bitfld.long 0x00 05. " BUFNO_AUTO_INCR ,Auto increment buffer number" " no, yes" bitfld.long 0x00 04. " ADDR_AUTO_INCR ,Auto-increment flash row address" " no, yes" textline " " hexmask.long.byte 0x00 00.--03. 1. 0. " PAGE_CNT ,The number of flash_clk cycles from NFC_WE high to NAND flash busy (tWB) or from NFC_WE high to NFC_RE low (tWHR)" group.long (0x00000000+0x3f34)++0x03 line.long 0x00 "DMA2_ADDR,DMA2 Address register" group.long (0x00000000+0x3f38)++0x03 line.long 0x00 "IRQ_STATUS,IRQ and Status register" bitfld.long 0x00 31. "WERR_IRQ ,Write error interrupt" " no, yes" bitfld.long 0x00 30. " CMD_DONE_IRQ ,Command done interrupt" " no, yes" textline " " bitfld.long 0x00 29. " IDLE_IRQ ,Command idle interrupt" " no, yes" bitfld.long 0x00 27. " WERR_STATUS ,Write error status" " no, yes" textline " " bitfld.long 0x00 26. " FLASH_CMD_BUSY ,Set if command execution is busy" " no, yes" bitfld.long 0x00 25. " RESIDUE_BUSY ,Set if the residue engine is busy" " no, yes" textline " " bitfld.long 0x00 24. " ECC_BUSY ,Set if the ECC engine is busy" " no, yes" bitfld.long 0x00 23. " DMA_BUSY ,Set if the DMA engine is busy" " no, yes" textline " " bitfld.long 0x00 22. " WERR_EN ,Enable bit for WERR_IRQ" " no, yes" bitfld.long 0x00 21. " CMD_DONE_EN ,Enable bit for CMD_DONE_IRQ" " no, yes" bitfld.long 0x00 20. " IDLE_EN ,Enable bit for command IDLE_IRQ" " no, yes" textline " " eventfld.long 0x00 19. " WERR_CLEAR ,Clear bit for WERR_IRQ" " -, clr" eventfld.long 0x00 18. " CMD_DONE_CLEAR ,Clear bit for CMD_DONE_IRQ" " -, clr" eventfld.long 0x00 17. " IDLE_CLEAR ,Clear bit for IDLE_IRQ" " -, clr" textline " " bitfld.long 0x00 04.--05. " RESIDUE_BUFF_NO ,Residue buffer number" "0,1,2,3" bitfld.long 0x00 02.--03. " ECC_BUFF_NO ,ECC buffer number" "0,1,2,3" bitfld.long 0x00 00.--01. " DMA_BUFF_NO ,DMA buffer number" "0,1,2,3" endif else width 0x14 if (data.long(ANC:iobase()+0xf04)&0x20000000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else rgroup.word (0x00000000+0x1e00)++0x01 line.word 0x00 "SRAM,Internal SRAM Size" bitfld.word 0x00 0.--3. " NFC_BUFSIZE ,NFC Buffer Size" "1 Kbytes,2 Kbytes,3 Kbytes,4 Kbytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.word (0x00000000+0x1e04)++0x05 line.word 0x00 "RAM_Buffer_Address,Buffer Number for the Page Data Transfer to/from the Flash Memory" bitfld.word 0x00 0.--3. " RBA ,Ram Buffer Transferred to/from Flash Memory" "1st internal,2nd internal,3rd internal,4th internal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.word 0x02 "NAND_Flash_Add,NAND Flash Add Register" line.word 0x04 "NAND_Flash_CMD,NAND Flash Command Register" group.word (0x00000000+0x1e0a)++0x01 line.word 0x00 "NFC_Configuration,NAND Flash Controller Internal Buffer Lock Control" bitfld.word 0x00 0.--1. " BLS ,Buffer Lock Set" "Locked,Locked,Unlocked,Locked" rgroup.word (0x00000000+0x1e0c)++0x01 line.word 0x00 "RECC_Status_Result,Controller Status and the Result of Flash Operation" bitfld.word 0x00 2.--3. " ERm ,ECC Error for Main Area Data" "No error,1-bit error,2-bits error,Reserved" bitfld.word 0x00 0.--1. " ERs ,ECC Error for Spare Area Data" "No error,1-bit error,2-bits error,Reserved" rgroup.word (0x00000000+0x1e0e)++0x01 line.word 0x00 "ECC_Rslt_Main_Area,ECC Error Position of Main Area Data Error (NAND Flash X8 Data Bus Case)" hexmask.word 0x00 3.--11. 0x8 " ECC_Result_1 ,ECC Error Position Address Which Selects One of Main Area Data Bytes" bitfld.word 0x00 0.--2. " ECC_Result_2 ,ECC Error Position Address Which Selects One of The 8 Data Bits in The Byte" "000,001,010,011,100,101,110,111" rgroup.word (0x00000000+0x1e0e)++0x01 line.word 0x00 "ECC_Rslt_Main_Area,ECC Error Position of Main Area Data Error (NAND Flash X16 Data Bus Case)" hexmask.word.byte 0x00 4.--11. 0x10 " ECC_Result_1 ,ECC Error Position Address Which Selects One of Main Area Data Bytes" bitfld.word 0x00 0.--3. " ECC_Result_2 ,ECC Error Position Address Which Selects One of The 16 Data Bits in The Byte" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup.word (0x00000000+0x1e10)++0x01 line.word 0x00 "ECC_Rslt_Spare_Area,ECC Error Position of Spare Area Data Error (NAND Flash X8 Data Bus Case)" bitfld.word 0x00 3.--4. " ECC_Result_4 ,ECC Error Position Address Which Selects One of Logical Sector Number" "00,01,10,11" bitfld.word 0x00 0.--2. " ECC_Result_3 ,ECC Error Position Address Which Selects One of The 8 Data Bits in The Byte" "000,001,010,011,100,101,110,111" rgroup.word (0x00000000+0x1e10)++0x01 line.word 0x00 "ECC_Rslt_Spare_Area,ECC Error Position of Spare Area Data Error (NAND Flash X16 Data Bus Case)" bitfld.word 0x00 4. " ECC_Result_4 ,ECC Error Position Address Which Selects One of Logical Sector Number" "0,1" bitfld.word 0x00 0.--3. " ECC_Result_3 ,ECC Error Position Address Which Selects One of The 16 Data Bits in The Half word" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" group.word (0x00000000+0x1e12)++0x05 line.word 0x00 "NF_WR_Prot,Nand Flash Write Protection Command to Make NAND Flash Secured" bitfld.word 0x00 0.--2. " WPC ,Write Protection Command" "Reserved,Lock-tight locked,Lock all NAND,Reserved,Unlock NAND,Reserved,Reserved,Reserved" line.word 0x02 "Unlock_Start_Blk_Add,Start of NAND Flash Block Address to Unlock in Write Protection Mode" line.word 0x04 "Unlock_End_Blk_Add,End of NAND Flash Block Address to Unlock in Write Protection Mode" rgroup.word (0x00000000+0x1e18)++0x01 line.word 0x00 "NAND_Flash_WR_Pr_St,Current NAND Flash Write Protection Status Whether Unlocked /Locked/Lock-Tighten" bitfld.word 0x00 2. " US ,Unlocked Status" "No unlocked blocks,Unlocked blocks" bitfld.word 0x00 1. " LS ,Locked Status" "Not all locked blocks,All locked blocks" textline " " bitfld.word 0x00 0. " LTS ,Lock-tighten Status" "Not lock-tightened,Lock-tightened" group.word (0x00000000+0x1e1a)++0x03 line.word 0x00 "NAND_Flash_Config1,NAND Flash Operation Configuration 1 Register" bitfld.word 0x00 7. " FLASH_CE ,Assosiated NAND FLASH Chip Enable" "Reserved,/ipp_DO_nfc_ce" bitfld.word 0x00 6. " REG_WRESET ,Warm Reset to NAND_Flash_Config2" "Reserved,Reset" textline " " bitfld.word 0x00 5. " FLASH_BIG ,Big endianess for Flash side" "Little,Big" bitfld.word 0x00 4. " INT_MSK ,Mask Interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " ECC_EN ,ECC operation Enable" "Bypassed,Executed" bitfld.word 0x00 2. " SP_EN ,NAND Flash Spare ENable" "Main/spare,Spare" line.word 0x02 "NAND_Flash_Config2,NAND Flash Operation Configuration 2 Register" bitfld.word 0x02 15. " INT ,Interrupt" "Not done,Done" bitfld.word 0x02 3.--5. " FDO ,NAND Flash Data Output" "Reserved,One page,ID data,Reserved,Status register,Reserved,Reserved,Reserved" textline " " bitfld.word 0x02 3. " FDI ,NAND Flash Data Input" "Inactive,Active" bitfld.word 0x02 1. " IFADD ,NAND Flash Address Input" "Inactive,Active" textline " " bitfld.word 0x02 0. " FCMD ,NAND Flash Command Input" "Inactive,Active" endif endif base anc:iobase() tree.end tree "PATA (Parallel Advanced Technology Attachment IMMRBAR + 0x10200)" width 0xa group.long 0x10200++0x17 line.long 0x00 "TR1,Timing Register 1" hexmask.long.byte 0x00 24.--31. 1. " TIME_OFF ,TOFF Control" hexmask.long.byte 0x00 16.--23. 1. " TIME_ON ,TON Control" textline " " hexmask.long.byte 0x00 8.--15. 1. " TIME_1 ,T1 Control" hexmask.long.byte 0x00 0.--7. 1. " TIME_2W ,T2 During Write Cycles Control" line.long 0x04 "TR2,Timing Register 2" hexmask.long.byte 0x04 24.--31. 1. " TIME_2R ,T2 During Read Cycles Control" hexmask.long.byte 0x04 16.--23. 1. " TIME_AX ,TA Control" textline " " hexmask.long.byte 0x04 8.--15. 1. " TIME_PIO_RDX ,TRD Control" hexmask.long.byte 0x04 0.--7. 1. " TIME_4 ,T4 Control" line.long 0x08 "TR3,Timing Register 3" hexmask.long.byte 0x08 24.--31. 1. " TIME_9 ,T9 Control" hexmask.long.byte 0x08 16.--23. 1. " TIME_M ,TM Control" textline " " hexmask.long.byte 0x08 8.--15. 1. " TIME_JN ,TJ and TN Control" hexmask.long.byte 0x08 0.--7. 1. " TIME_D ,TD Control" line.long 0x0c "TR4,Timing Register 4" hexmask.long.byte 0x0c 24.--31. 1. " TIME_K ,TK Control" hexmask.long.byte 0x0c 16.--23. 1. " TIME_ACK ,TACK Control" textline " " hexmask.long.byte 0x0c 8.--15. 1. " TIME_ENV ,TENV Control" hexmask.long.byte 0x0c 0.--7. 1. " TIME_RPX ,TRP Control" line.long 0x10 "TR5,Timing Register 5" hexmask.long.byte 0x10 24.--31. 1. " TIME_ZAH ,TZAH Control" hexmask.long.byte 0x10 16.--23. 1. " TIME_MLIX ,TMLI Control" textline " " hexmask.long.byte 0x10 8.--15. 1. " TIME_DVH ,TDVH Control" hexmask.long.byte 0x10 0.--7. 1. " TIME_DZFS ,TDZFS During Control" line.long 0x14 "TR6,Timing Register 6" hexmask.long.byte 0x14 24.--31. 1. " TIME_DVS ,TDVS Control" hexmask.long.byte 0x14 16.--23. 1. " TIME_CVH ,TCVH Control" textline " " hexmask.long.byte 0x14 8.--15. 1. " TIME_SS ,TSS Control" hexmask.long.byte 0x14 0.--7. 1. " TIME_CYC ,TCYC and T2CYC Control" hgroup.long 0x10218++0x03 hide.long 0x00 "FD32,FIFO_Data_32 Register" in hgroup.long 0x1021c++0x03 hide.long 0x00 "FD16,FIFO_Data_16 Register" in rgroup.long 0x10220++0x03 line.long 0x00 "FF,FIFO_Fill Register" hexmask.long.byte 0x00 24.--31. 1. " FIFO_FILL[7:0] ,Current number of 16-bit half-words present in FIFO" group.long 0x10224++0x03 line.long 0x00 "ACR,ATA_Control Register" bitfld.long 0x00 31. " FIFO_RST_B ,Internal FIFO Enable" "Reset,Enabled" bitfld.long 0x00 30. " ATA_RST_B ,The Level on the ata_reset_b Pin," "0/Reset,1/No reset" textline " " bitfld.long 0x00 29. " FIFO_TX_EN ,FIFO Transmit Data Requests to DMA" "Disabled,Enabled" bitfld.long 0x00 28. " FIFO_RCV_EN ,FIFO Receive Data Requests to DMA" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DMA_PENDING ,ATA Interface Responds to a DMA Request" "Stopped,Started" bitfld.long 0x00 26. " DMA_ULTRA_SEL ,DMA Protocol Status" "Ultra DMA,Multiword DMA" textline " " bitfld.long 0x00 25. " DMA_WRITE ,The Data Direction on any DMA Burst Started" "DMA in burst,DMA out burst" bitfld.long 0x00 24. " IORDY_EN ,ata_iordy Handshake Status" "Used,Disregarded" rgroup.long 0x10228++0x03 line.long 0x00 "IPR,Interrupt_Pending Register" bitfld.long 0x00 30. " FIFO_UNDERFLOW ,FIFO Underflow Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " FIFO_OVERFLOW ,FIFO OVerflow Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " CONTROLER_IDLE ,Controller Idle Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " ATA_IRTRQ2 ,ATA_IRTRQ2 Interrupt" "No interrupt,Interrupt" group.long 0x1022c++0x03 line.long 0x00 "IER,Interrupt_Enable Register" bitfld.long 0x00 30. " FIFO_UNDERFLOW ,FIFO Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " FIFO_OVERFLOW ,FIFO OVerflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " CONTROLER_IDLE ,Controller Idle Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " ATA_IRTRQ2 ,ATA_IRTRQ2 Interrupt Enable" "Disabled,Enabled" wgroup.long 0x10230++0x03 line.long 0x00 "ICR,Interrupt_Clear Register" bitfld.long 0x00 30. " FIFO_UNDERFLOW ,FIFO Underflow Interrupt Clear" "No effect,Clear" bitfld.long 0x00 29. " FIFO_OVERFLOW ,FIFO OVerflow Interrupt Clear" "No effect,Clear" group.long 0x10234++0x03 line.long 0x00 "FAR,FIFO_Alarm Register" hexmask.long.byte 0x00 0.--7. 1. " FIFO_ALARM[7:0] ,The Threshold to Generate fifo_rcv_alarm and fifo_tx_alarm to the DMA Interface" tree "Registers Present in the Drive Connected to the ATA Bus" width 0x1a group.long 0x102a0++0x1f line.long 0x00 "Drive_Data,Drive Data Register" line.long 0x04 "Drive_Features,Drive Features Register" line.long 0x08 "Drive_Sector_Count,Drive Sector Count Register" line.long 0x0c "Drive_Sector_Num,Drive Sector Number Register" line.long 0x10 "Drive_Cyl_Low,Drive Cylinder Low Register" line.long 0x14 "Drive_Cyl_High,Drive Cylinder High Register" line.long 0x18 "Drive_Dev_Head,Drive Device Head Register" line.long 0x1c "Drive_Command/Status,Drive Command/Status Register" group.long 0x102d8++0x03 line.long 0x00 "Drive_Alt_Status/Control,Drive Alternate Status/Control Register" tree.end tree.end tree "PCI (PCI Controller IMMRBAR + 0x8500)" width 0xf tree "Control and Status Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8500++0x2B line.long 0x00 "PCI_ESR,PCI Error Status Register" eventfld.long 0x00 31. " MERR ,Multiple errors" "Not occurred,Occurred" eventfld.long 0x00 10. " APAR ,Address parity error" "No error,Error" eventfld.long 0x00 9. " PCISERR ,PCI system error" "No error,Error" textline " " eventfld.long 0x00 8. " MPERR ,Master parity error" "No error,Error" eventfld.long 0x00 7. " TPERR ,Target parity error" "No error,Error" eventfld.long 0x00 6. " NORSP ,No response" "Response,No response" textline " " eventfld.long 0x00 5. " TABT ,Target abort" "Not aborted,Aborted" line.long 0x04 "PCI_ECDR,PCI Error Capture Disable Register" bitfld.long 0x04 10. " APAR ,Address parity error capture enable" "Enabled,Disabled" bitfld.long 0x04 9. " PCISERR ,PCI system error capture enable" "Enabled,Disabled" bitfld.long 0x04 8. " MPERR ,Master parity error capture enable" "Enabled,Disabled" textline " " bitfld.long 0x04 7. " TPERR ,Target parity error capture enable" "Enabled,Disabled" bitfld.long 0x04 6. " NORSP ,No response error capture enable" "Enabled,Disabled" bitfld.long 0x04 5. " TABT ,Target abort error capture enable" "Enabled,Disabled" line.long 0x08 "PCI_EER,PCI Error Enable Register" bitfld.long 0x08 10. " APAR ,Address parity error" "Disabled,Enabled" bitfld.long 0x08 9. " PCISERR ,PCI system error" "Disabled,Enabled" bitfld.long 0x08 8. " MPERR ,Master parity error" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " TPERR ,Target parity error" "Disabled,Enabled" bitfld.long 0x08 6. " NORSP ,No response" "Disabled,Enabled" bitfld.long 0x08 5. " TABT ,Target abort" "Disabled,Enabled" line.long 0x0c "PCI_EATCR,PCI Error Attributes Capture Register" bitfld.long 0x0c 28.--30. " ERRTYPE ,First error type" "Address parity,Write data parity,Read data parity,Master abort,Target abort,System,Parity/read,Parity/write" bitfld.long 0x0c 24.--27. " BN ,Beat number" "1st,2nd,3rd,4th,5th,6th,7th,8th,9th,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0c 20.--21. " TS ,Transaction size" "4 dwords,1 dword,2 dwords,3 dwords" textline " " bitfld.long 0x0c 16.--19. " ES ,Error source" "External master,Reserved,Reserved,Reserved,Reserved,DMA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x0c 12.--15. " CMD ,PCI command" "b'0000,b'0001,b'0010,b'0011,b'0100,b'0101,b'0110,b'0111,b'1000,b'1001,b'1010,b'1011,b'1100,b'1101,b'1110,b'1111" bitfld.long 0x0c 4.--7. " BE ,PCI byte enables" "b'0000,b'0001,b'0010,b'0011,b'0100,b'0101,b'0110,b'0111,b'1000,b'1001,b'1010,b'1011,b'1100,b'1101,b'1110,b'1111" textline " " bitfld.long 0x0c 1. " PB ,Parity bit" "0,1" bitfld.long 0x0c 0. " VI ,Error information valid" "Not valid,Valid" line.long 0x10 "PCI_EACR,PCI Error Address Capture Register" line.long 0x14 "PCI_EEACR,PCI Error Extended Address Capture Register" line.long 0x18 "PCI_EDLCR,PCI Error Data Capture Register" line.long 0x20 "PCI_GCR,PCI General Control Register" bitfld.long 0x20 2. " BBR ,Block bus request" "Normal,Blocked" bitfld.long 0x20 1. " PPL ,PCI pins low" "Normal,Low" bitfld.long 0x20 0. " SPRST ,Soft PCI reset" "Low,High" line.long 0x24 "PCI_ECR,PCI Error Control Register" bitfld.long 0x24 10. " APAR ,Address parity error" "Interrupt,Machine check" bitfld.long 0x24 9. " PCISERR ,PCI system error" "Interrupt,Machine check" bitfld.long 0x24 8. " MPERR ,Master parity error" "Interrupt,Machine check" textline " " bitfld.long 0x24 7. " TPERR ,Target parity error" "Interrupt,Machine check" bitfld.long 0x24 6. " NORSP ,No response" "Interrupt,Machine check" bitfld.long 0x24 5. " TABT ,Target abort" "Interrupt,Machine check" line.long 0x28 "PCI_GSR,PCI General Status Register" bitfld.long 0x28 0. " IDLE ,PCI controller is idle" "Active,Idle" group.long 0x8538++0x03 line.long 0x00 "PITAR2,PCI Inbound Translation Address Register 2" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long 0x8550++0x03 line.long 0x00 "PITAR1,PCI Inbound Translation Address Register 1" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long 0x8568++0x03 line.long 0x00 "PITAR0,PCI Inbound Translation Address Register 0" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long 0x8540++0x03 line.long 0x00 "PIBAR2,PCI Inbound Base Address Register 2" group.long 0x8558++0x03 line.long 0x00 "PIBAR1,PCI Inbound Base Address Register 1" group.long 0x8570++0x03 line.long 0x00 "PIBAR0,PCI Inbound Base Address Register 0" group.long 0x8544++0x03 line.long 0x00 "PIEBAR2,PCI Inbound Extended Base Address Register 2" hexmask.long 0x00 0.--19. 1. " EBA ,Extended Base Address" group.long 0x855c++0x03 line.long 0x00 "PIEBAR1,PCI Inbound Extended Base Address Register 1" hexmask.long 0x00 0.--19. 1. " EBA ,Extended Base Address" group.long 0x8548++0x03 line.long 0x00 "PIWAR2,PCI Inbound Window Attribute Register 2" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SBS ,Special Byte Swap" "No swap,Swap" textline " " bitfld.long 0x00 29. " PF ,Prefetchable" "Not prefetchable,Prefetchable" bitfld.long 0x00 16.--19. " RTT ,Read transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 12.--15. " WTT ,Write transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 0.--5. " IWS ,Inbound window size" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4-Kbyte,8-Kbyte,16-Kbyte,32-Kbyte,64-Kbyte,128-Kbyte,256-Kbyte,512-Kbyte,1-Mbyte,2-Mbyte,4-Mbyte,8-Mbyte,16-Mbyte,32-Mbyte,64-Mbyte,128-Mbyte,256-Mbyte,512-Mbyte,1-Gbyte,2-Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0x8560++0x03 line.long 0x00 "PIWAR1,PCI Inbound Window Attribute Register 1" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SBS ,Special Byte Swap" "No swap,Swap" textline " " bitfld.long 0x00 29. " PF ,Prefetchable" "Not prefetchable,Prefetchable" bitfld.long 0x00 16.--19. " RTT ,Read transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 12.--15. " WTT ,Write transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 0.--5. " IWS ,Inbound window size" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4-Kbyte,8-Kbyte,16-Kbyte,32-Kbyte,64-Kbyte,128-Kbyte,256-Kbyte,512-Kbyte,1-Mbyte,2-Mbyte,4-Mbyte,8-Mbyte,16-Mbyte,32-Mbyte,64-Mbyte,128-Mbyte,256-Mbyte,512-Mbyte,1-Gbyte,2-Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0x8578++0x03 line.long 0x00 "PIWAR0,PCI Inbound Window Attribute Register 0" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SBS ,Special Byte Swap" "No swap,Swap" textline " " bitfld.long 0x00 29. " PF ,Prefetchable" "Not prefetchable,Prefetchable" bitfld.long 0x00 16.--19. " RTT ,Read transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 12.--15. " WTT ,Write transaction type" "Reserved,Reserved,Reserved,Reserved,W/o snoop,With snoop,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 0.--5. " IWS ,Inbound window size" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,4-Kbyte,8-Kbyte,16-Kbyte,32-Kbyte,64-Kbyte,128-Kbyte,256-Kbyte,512-Kbyte,1-Mbyte,2-Mbyte,4-Mbyte,8-Mbyte,16-Mbyte,32-Mbyte,64-Mbyte,128-Mbyte,256-Mbyte,512-Mbyte,1-Gbyte,2-Gbyte,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" endif tree.end tree "PCI Configuration Space Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000000xx line.word 0x00 "VID,Vendor ID" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000000xx line.word 0x00 "DID,Device ID Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000001xx line.word 0x00 "PCI_CMD,PCI Command" bitfld.word 0x00 10. " INTD ,Interrupt disable" "Enabled,Disabled" textline " " bitfld.word 0x00 8. " SERREN ,SERR enable" "Disabled,Enabled" bitfld.word 0x00 6. " PERRR ,Parity error response" "Ignored,Standard" textline " " bitfld.word 0x00 4. " MWI ,Memory-write-and-invalidate" "0,Reserved" bitfld.word 0x00 3. " SC ,Special cycles" "0,Reserved" textline " " bitfld.word 0x00 2. " BMST ,Bus master" "Not master,Master" bitfld.word 0x00 1. " MEM ,Memory space" "Not responding,Responding" textline " " bitfld.word 0x00 0. " I/O ,I/O space" "0,Reserved" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000001xx line.word 0x00 "PSC,PCI Status Configuration Register" eventfld.word 0x00 15. " DPERR ,Detected parity error" "No error,Error" eventfld.word 0x00 14. " SSERR ,Signalled system error" "No error,Error" textline " " eventfld.word 0x00 13. " RMA ,Received master abort" "Not aborted,Aborted" eventfld.word 0x00 12. " RTA ,Received target abort" "Not aborted,Aborted" textline " " eventfld.word 0x00 11. " STA ,Signalled target abort" "Not aborted,Aborted" bitfld.word 0x00 9.--10. " DEVSEL_T ,DEVSEL timing" "00,Reserved,Reserved,Reserved" textline " " eventfld.word 0x00 8. " DPD ,Master data parity error" "No error,Error" bitfld.word 0x00 7. " FB_BC ,Fast back-to-back capable" "Reserved,1" textline " " bitfld.word 0x00 5. " 66M ,66 MHz capable" "Reserved,1" bitfld.word 0x00 4. " CL ,Capabilities list" "0,Reserved" textline " " eventfld.word 0x00 3. " INTS ,Interrupt status" "No interrupt,Interrupt" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000010xx line.byte 0x00 "RIDC,Revision ID Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000010xx line.byte 0x00 "SPIC,Standard Programming Interface Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000010xx line.byte 0x00 "SCC,Subclass Code Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000010xx line.byte 0x00 "BCCC,Base Class Code Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000011xx line.byte 0x00 "CLSC,Cache Line Size Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000011xx line.byte 0x00 "LTC,Latency Timer Configuration Register" hexmask.byte 0x00 3.--7. 8. " LT ,Latency Timer" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000011xx line.byte 0x00 "HTC,Header Type Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000011xx line.byte 0x00 "BCC,BIST Control Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000100xx line.long 0x00 "PBAR,PIMMR Base Address Configuration Register" hexmask.long 0x00 4.--31. 0x10 " BA ,Base address" bitfld.long 0x00 3. " PRE ,Prefetchable" "0,Reserved" textline " " bitfld.long 0x00 1.--2. " T[2:1] ,Type" "00,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " MSI ,Memory space indicator" "0,Reserved" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000101xx line.long 0x00 "GBAR0,GPL Base Address Register 0" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address" bitfld.long 0x00 3. " PRE ,Prefetchable" "Low,High" textline " " bitfld.long 0x00 1.--2. " T[2:1] ,Type" "00,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " MSI ,Memory space indicator" "0,Reserved" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx000110xx line.long 0x00 "GBAR1,GPL Base Address Register 1" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address" bitfld.long 0x00 3. " PRE ,Prefetchable" "Low,High" textline " " bitfld.long 0x00 1.--2. " T[2:1] ,Type" "Reserved,Reserved,10,Reserved" bitfld.long 0x00 0. " MSI ,Memory space indicator" "0,Reserved" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001000xx line.long 0x00 "GBAR2,GPL Base Address Register 2" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address" bitfld.long 0x00 3. " PRE ,Prefetchable" "Low,High" textline " " bitfld.long 0x00 1.--2. " T[2:1] ,Type" "Reserved,Reserved,10,Reserved" bitfld.long 0x00 0. " MSI ,Memory space indicator" "0,Reserved" ;hgroup.long 0x851c++0x03 ; hide.long 0x00 "GEBAR1,GPL Extended Base Address Register 1" ;hgroup.long 0x8524++0x03 ; hide.long 0x00 "GEBAR2,GPL Extended Base Address Register 2" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001011xx line.word 0x00 "SSVID,Sub-System Vendor ID Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001011xx line.word 0x00 "SSDIV,Sub-System Device ID Configuration Register" rgroup.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001101xx line.byte 0x00 "CPC,Capabilities Pointer Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001111xx line.byte 0x00 "ILC,Interrupt Line Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001111xx line.byte 0x00 "IPC,Interrupt Pin Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001111xx line.byte 0x00 "MGC,MIN GNT Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx001111xx line.byte 0x00 "MLC,MAX LAT Configuration Register" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx010001xx line.word 0x00 "PFC,PCI Function Configuration Register" bitfld.word 0x00 5. " CFG_LOCK ,Configuration lock" "Not locked,Locked" bitfld.word 0x00 2. " TLTD ,Target latency timeout disable" "Enabled,Disabled" textline " " bitfld.word 0x00 1. " MLTD ,Master latency timer disable" "Enabled,Disabled" bitfld.word 0x00 0. " HA ,Host/Agent" "Host,Reserved" group.long (0x8300+0x04)++0x03 saveout 0x8300 %l 0y1xxxxxxxxxxxxxxxxxxxxxxx010001xx line.word 0x00 "PCI_ACR,PCI Arbiter Control Register" bitfld.word 0x00 15. " AD ,Arbiter disable" "Enabled,Disabled" bitfld.word 0x00 14. " PM ,Parking mode" "Last device,PCI controller" textline " " bitfld.word 0x00 12. " PBMD ,PCI broken master disable" "Enabled,Disabled" bitfld.word 0x00 6. " PRI0 ,Priority level for master 0" "Low,High" textline " " bitfld.word 0x00 5. " PRI1 ,Priority level for master 1" "Low,High" bitfld.word 0x00 4. " PRI2 ,Priority level for master 2" "Low,High" textline " " bitfld.word 0x00 0. " MPRI ,My priority" "Low,High" endif tree.end endian.le tree "Software Configuration Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8300++0x03 line.long 0x00 "CONFIG_ADDRESS,CONFIG_ADDRESS Register" bitfld.long 0x00 31. " EN ,Enable configuration transaction" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " BN ,Bus number" textline " " bitfld.long 0x00 11.--15. " DN ,Device number" "Internal access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,31,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Special/Int. ACK" bitfld.long 0x00 8.--10. " FN ,Function number" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 2.--7. 1. " RN ,Register number" endif if (((data.long(ANC:iobase()+(0x8300))&0x80000000)==0x80000000)&&((d.l(ANC:iobase()+0xf04)&(0x00000800))!=0)) group.long 0x8304++0x03 line.long 0x00 "CONFIG_DATA,CONFIG_DATA Register" elif (((data.long(ANC:iobase()+(0x8300))&0x80000000)==0x0)&&((d.l(ANC:iobase()+0xf04)&(0x00000800))!=0)) wgroup.long 0x8304++0x03 line.long 0x00 "CONFIG_DATA,CONFIG_DATA Register" else group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else hgroup.long 0x8308++0x03 hide.long 0x00 "PCI_INT_ACK,PCI Interrupt Acknowledge Register" in endif tree.end endian.be tree.end tree "IOS (I/O Sequencer for PCI Subsystem IMMRBAR + 0x8400)" width 0xa if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8400++0x3 line.long 0x00 "POTAR0,PCI Outbound Translation Address Register 0" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8400+0x8)++0x3 line.long 0x00 "POBAR0,PCI Outbound Base Address Register 0" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8400+0x10)++0x3 line.long 0x00 "POCMR0,PCI Outbound Comparison Mask Register 0" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" group.long 0x8418++0x3 line.long 0x00 "POTAR1,PCI Outbound Translation Address Register 1" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8418+0x8)++0x3 line.long 0x00 "POBAR1,PCI Outbound Base Address Register 1" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8418+0x10)++0x3 line.long 0x00 "POCMR1,PCI Outbound Comparison Mask Register 1" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" group.long 0x8430++0x3 line.long 0x00 "POTAR2,PCI Outbound Translation Address Register 2" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8430+0x8)++0x3 line.long 0x00 "POBAR2,PCI Outbound Base Address Register 2" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8430+0x10)++0x3 line.long 0x00 "POCMR2,PCI Outbound Comparison Mask Register 2" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" group.long 0x8448++0x3 line.long 0x00 "POTAR3,PCI Outbound Translation Address Register 3" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8448+0x8)++0x3 line.long 0x00 "POBAR3,PCI Outbound Base Address Register 3" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8448+0x10)++0x3 line.long 0x00 "POCMR3,PCI Outbound Comparison Mask Register 3" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" group.long 0x8460++0x3 line.long 0x00 "POTAR4,PCI Outbound Translation Address Register 4" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8460+0x8)++0x3 line.long 0x00 "POBAR4,PCI Outbound Base Address Register 4" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8460+0x10)++0x3 line.long 0x00 "POCMR4,PCI Outbound Comparison Mask Register 4" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" group.long 0x8478++0x3 line.long 0x00 "POTAR5,PCI Outbound Translation Address Register 5" hexmask.long 0x00 0.--19. 1. " TA ,Translation Address" group.long (0x8478+0x8)++0x3 line.long 0x00 "POBAR5,PCI Outbound Base Address Register 5" hexmask.long 0x00 0.--19. 1. " BA ,Base Address" group.long (0x8478+0x10)++0x3 line.long 0x00 "POCMR5,PCI Outbound Comparison Mask Register 5" bitfld.long 0x00 31. " EN ,Address Translation Window Enable" "Disabled,Enabled" bitfld.long 0x00 30. " IO ,I/O Space" "Memory,I/O" bitfld.long 0x00 29. " PRES ,Prefetchable" "Not prefetchable,Prefetchable" textline " " bitfld.long 0x00 20. " SBS ,Special Byte Swap" "Normal,Special" bitfld.long 0x00 19. " CM19 ,Comparison Mask 19" "0,1" bitfld.long 0x00 18. " CM18 ,Comparison Mask 18" "0,1" textline " " bitfld.long 0x00 17. " CM17 ,Comparison Mask 17" "0,1" bitfld.long 0x00 16. " CM16 ,Comparison Mask 16" "0,1" bitfld.long 0x00 15. " CM15 ,Comparison Mask 15" "0,1" textline " " bitfld.long 0x00 14. " CM14 ,Comparison Mask 14" "0,1" bitfld.long 0x00 13. " CM13 ,Comparison Mask 13" "0,1" bitfld.long 0x00 12. " CM12 ,Comparison Mask 12" "0,1" textline " " bitfld.long 0x00 11. " CM11 ,Comparison Mask 11" "0,1" bitfld.long 0x00 10. " CM10 ,Comparison Mask 10" "0,1" bitfld.long 0x00 9. " CM9 ,Comparison Mask 9" "0,1" textline " " bitfld.long 0x00 8. " CM8 ,Comparison Mask 8" "0,1" bitfld.long 0x00 7. " CM7 ,Comparison Mask 7" "0,1" bitfld.long 0x00 6. " CM6 ,Comparison Mask 6" "0,1" textline " " bitfld.long 0x00 5. " CM5 ,Comparison Mask 5" "0,1" bitfld.long 0x00 4. " CM4 ,Comparison Mask 4" "0,1" bitfld.long 0x00 3. " CM3 ,Comparison Mask 3" "0,1" textline " " bitfld.long 0x00 2. " CM2 ,Comparison Mask 2" "0,1" bitfld.long 0x00 1. " CM1 ,Comparison Mask 1" "0,1" bitfld.long 0x00 0. " CM0 ,Comparison Mask 0" "0,1" rgroup.long 0x84f0++0x03 line.long 0x00 "PMCR,Power Management Control Register" bitfld.long 0x00 0. " IDLE ,Logic idle" "Active,Idle" group.long 0x84f8++0x03 line.long 0x00 "DTCR,Discard Time Control Register" bitfld.long 0x00 31. " EN ,Discard Timer Enable" "Disabled,Enabled" hexmask.long 0x00 0.--23. 1. " PTV ,Preload timer value" endif tree.end tree "PCI DMA (DMA for PCI Subsystem IMMRBAR + 0x8000)" width 0xa tree "Outbound Message Interrupt Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8030++0x07 line.long 0x00 "OMISR,Outbound Message Interrupt Status Register" bitfld.long 0x00 3. " ODI ,Outbound Doorbell Interrupt" "No doorbell,Doorbell" eventfld.long 0x00 1. " OM1I ,Outbound Message 1 Interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " OM0I ,Outbound Message 0 Interrupt" "Not occurred,Occurred" line.long 0x04 "OMIMR,Outbound Message Interrupt Mask Register" bitfld.long 0x04 3. " ODIM ,Outbound Doorbell Interrupt Mask" "Allowed,Masked" bitfld.long 0x04 1. " OM1IM ,Outbound Message 1 Interrupt Mask" "Allowed,Masked" textline " " bitfld.long 0x04 0. " OM0IM ,Outbound Message 0 Interrupt Mask" "Allowed,Masked" endif tree.end tree "Message Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8050++0x0f line.long 0x00 "IMR0,Inbound Message Register 0" line.long 0x04 "IMR1,Inbound Message Register 1" line.long 0x08 "OMR0,Outbound Message Register 0" line.long 0x0c "OMR1,Outbound Message Register 1" endif tree.end tree "Doorbell Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8060++0x03 line.long 0x00 "ODR,Outbound Doorbell Register" bitfld.long 0x00 28. " ODR28 ,Outbound Doorbell 28" "No interrupt,Interrupt" bitfld.long 0x00 27. " ODR27 ,Outbound Doorbell 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " ODR26 ,Outbound Doorbell 26" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " ODR25 ,Outbound Doorbell 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " ODR24 ,Outbound Doorbell 24" "No interrupt,Interrupt" bitfld.long 0x00 23. " ODR23 ,Outbound Doorbell 23" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " ODR22 ,Outbound Doorbell 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ODR21 ,Outbound Doorbell 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ODR20 ,Outbound Doorbell 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ODR19 ,Outbound Doorbell 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ODR18 ,Outbound Doorbell 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ODR17 ,Outbound Doorbell 17" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " ODR16 ,Outbound Doorbell 16" "No interrupt,Interrupt" bitfld.long 0x00 15. " ODR15 ,Outbound Doorbell 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " ODR14 ,Outbound Doorbell 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " ODR13 ,Outbound Doorbell 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ODR12 ,Outbound Doorbell 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " ODR11 ,Outbound Doorbell 11" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ODR10 ,Outbound Doorbell 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " ODR9 ,Outbound Doorbell 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " ODR8 ,Outbound Doorbell 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " ODR7 ,Outbound Doorbell 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " ODR6 ,Outbound Doorbell 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " ODR5 ,Outbound Doorbell 5" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " ODR4 ,Outbound Doorbell 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " ODR3 ,Outbound Doorbell 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ODR2 ,Outbound Doorbell 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " ODR1 ,Outbound Doorbell 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ODR0 ,Outbound Doorbell 0" "No interrupt,Interrupt" group.long 0x8068++0x03 line.long 0x00 "IDR,Inbound Doorbell Register" eventfld.long 0x00 31. " IMC ,Inbound Machine Check" "No interrupt,Interrupt" eventfld.long 0x00 30. " IDR30 ,Inbound Doorbell 30" "No interrupt,Interrupt" eventfld.long 0x00 29. " IDR29 ,Inbound Doorbell 29" "No interrupt,Interrupt" textline " " eventfld.long 0x00 28. " IDR28 ,Inbound Doorbell 28" "No interrupt,Interrupt" eventfld.long 0x00 27. " IDR27 ,Inbound Doorbell 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " IDR26 ,Inbound Doorbell 26" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " IDR25 ,Inbound Doorbell 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " IDR24 ,Inbound Doorbell 24" "No interrupt,Interrupt" eventfld.long 0x00 23. " IDR23 ,Inbound Doorbell 23" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " IDR22 ,Inbound Doorbell 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " IDR21 ,Inbound Doorbell 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " IDR20 ,Inbound Doorbell 20" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " IDR19 ,Inbound Doorbell 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " IDR18 ,Inbound Doorbell 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " IDR17 ,Inbound Doorbell 17" "No interrupt,Interrupt" textline " " eventfld.long 0x00 16. " IDR16 ,Inbound Doorbell 16" "No interrupt,Interrupt" eventfld.long 0x00 15. " IDR15 ,Inbound Doorbell 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " IDR14 ,Inbound Doorbell 14" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " IDR13 ,Inbound Doorbell 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " IDR12 ,Inbound Doorbell 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " IDR11 ,Inbound Doorbell 11" "No interrupt,Interrupt" textline " " eventfld.long 0x00 10. " IDR10 ,Inbound Doorbell 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " IDR9 ,Inbound Doorbell 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " IDR8 ,Inbound Doorbell 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " IDR7 ,Inbound Doorbell 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " IDR6 ,Inbound Doorbell 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " IDR5 ,Inbound Doorbell 5" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " IDR4 ,Inbound Doorbell 4" "No interrupt,Interrupt" eventfld.long 0x00 3. " IDR3 ,Inbound Doorbell 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " IDR2 ,Inbound Doorbell 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " IDR1 ,Inbound Doorbell 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " IDR0 ,Inbound Doorbell 0" "No interrupt,Interrupt" endif tree.end tree "Inbound Message Interrupt Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8080++0x07 line.long 0x00 "IMISR,Inbound Message Interrupt Status Register" bitfld.long 0x00 4. " MCI ,Machine Check Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " IDI ,Inbound Doorbell Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " IM1I ,Inbound Message 1 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " IM0I ,Inbound Message 0 Interrupt" "No interrupt,Interrupt" line.long 0x04 "IMIMR,Inbound Message Interrupt Mask Register" bitfld.long 0x04 4. " MCIM ,Machine Check Interrupt Mask" "Allowed,Masked" bitfld.long 0x04 3. " IDIM ,Inbound Doorbell Interrupt Mask" "Allowed,Masked" textline " " bitfld.long 0x04 1. " IM1IM ,Inbound Message 1 Interrupt Mask" "Allowed,Masked" bitfld.long 0x04 0. " IM0IM ,Inbound Message 0 Interrupt Mask" "Allowed,Masked" endif tree.end tree "DMA Registers" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x8100++0x0b "Channel 0" line.long 0x00 "DMAMR0,DMA Mode Register 0" bitfld.long 0x00 24.--27. " DRCNT ,DMA Request CouNt" "Reserved,Reserved,Reserved,Reserved,Reserved,1 cache line,2 cache lines,4 cache lines,8 cache lines,6 cache lines,32 cache lines,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 21.--23. " BWC ,Bandwidth Control" "1 cache line,2 cache lines,4 cache lines,8 cache lines,16 cache lines,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 20. " DMSEN ,Direct Mode Snoop Enable" "Disabled,Enabled" bitfld.long 0x00 19. " IRQS ,Interrupt Stee" "Local processor,PCI bus" textline " " bitfld.long 0x00 18. " EMSEN ,External Master Start Enable" "By software,By hardware" bitfld.long 0x00 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" textline " " bitfld.long 0x00 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination Address Hold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SAHE ,Source Address Hold Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " PRC ,PCI Read Command" "Read,Read Line,Read Multiple,Reserved" textline " " bitfld.long 0x00 7. " EOTIE ,End-of-Transfer Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 3. " TEM ,Transfer Error Mask" "Halted,Completed" textline " " bitfld.long 0x00 2. " CTM ,Channel Transfer Mode" "Chaining,Direct" bitfld.long 0x00 1. " CC ,Channel Continue" "No restart,Restart" textline " " bitfld.long 0x00 0. " CS ,Channel Start" "Stopped,Started" line.long 0x04 "DMASR0,DMA Status Register 0" eventfld.long 0x04 7. " TE ,Transfer Error" "No error,Error" bitfld.long 0x04 2. " CB ,Channel Busy" "Not busy,Busy" textline " " eventfld.long 0x04 1. " EOSI ,End-of-Segment Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 0. " EOCDI ,End-of-Chain/Direct Interrupt" "No interrupt,Interrupt" line.long 0x08 "DMACDAR0,DMA Current Descriptor Address Register 0" hexmask.long 0x08 5.--31. 0x20 " CDA ,Current Descriptor Address" bitfld.long 0x08 4. " SNEN ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EOSIE ,End-of-Segment Interrupt Enable" "Not generated,Generated" group.long (0x8100+0x10)++0x03 line.long 0x00 "DMASAR0,DMA Source Address Register 0" group.long (0x8100+0x18)++0x03 line.long 0x00 "DMADAR0,DMA Destination Address Register 0" group.long (0x8100+0x20)++0x07 line.long 0x00 "DMABCR0,DMA Byte Count Register 0" hexmask.long 0x00 0.--25. 1. " BC ,Byte Count" line.long 0x04 "DMANDAR0,DMA Next Descriptor Address Register 0" hexmask.long 0x04 5.--31. 0x20 " NDA ,Next Descriptor Address" bitfld.long 0x04 4. " NSNEN ,Next Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " NEOSIE ,Next End-of-Segment Interrupt Enable" "Not generated,Generated" bitfld.long 0x04 0. " EOTD ,End-of-Transfer Descriptor" "Not last one,Last one" group.long 0x8180++0x0b "Channel 1" line.long 0x00 "DMAMR1,DMA Mode Register 1" bitfld.long 0x00 24.--27. " DRCNT ,DMA Request CouNt" "Reserved,Reserved,Reserved,Reserved,Reserved,1 cache line,2 cache lines,4 cache lines,8 cache lines,6 cache lines,32 cache lines,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 21.--23. " BWC ,Bandwidth Control" "1 cache line,2 cache lines,4 cache lines,8 cache lines,16 cache lines,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 20. " DMSEN ,Direct Mode Snoop Enable" "Disabled,Enabled" bitfld.long 0x00 19. " IRQS ,Interrupt Stee" "Local processor,PCI bus" textline " " bitfld.long 0x00 18. " EMSEN ,External Master Start Enable" "By software,By hardware" bitfld.long 0x00 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" textline " " bitfld.long 0x00 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination Address Hold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SAHE ,Source Address Hold Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " PRC ,PCI Read Command" "Read,Read Line,Read Multiple,Reserved" textline " " bitfld.long 0x00 7. " EOTIE ,End-of-Transfer Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 3. " TEM ,Transfer Error Mask" "Halted,Completed" textline " " bitfld.long 0x00 2. " CTM ,Channel Transfer Mode" "Chaining,Direct" bitfld.long 0x00 1. " CC ,Channel Continue" "No restart,Restart" textline " " bitfld.long 0x00 0. " CS ,Channel Start" "Stopped,Started" line.long 0x04 "DMASR1,DMA Status Register 1" eventfld.long 0x04 7. " TE ,Transfer Error" "No error,Error" bitfld.long 0x04 2. " CB ,Channel Busy" "Not busy,Busy" textline " " eventfld.long 0x04 1. " EOSI ,End-of-Segment Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 0. " EOCDI ,End-of-Chain/Direct Interrupt" "No interrupt,Interrupt" line.long 0x08 "DMACDAR1,DMA Current Descriptor Address Register 1" hexmask.long 0x08 5.--31. 0x20 " CDA ,Current Descriptor Address" bitfld.long 0x08 4. " SNEN ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EOSIE ,End-of-Segment Interrupt Enable" "Not generated,Generated" group.long (0x8180+0x10)++0x03 line.long 0x00 "DMASAR1,DMA Source Address Register 1" group.long (0x8180+0x18)++0x03 line.long 0x00 "DMADAR1,DMA Destination Address Register 1" group.long (0x8180+0x20)++0x07 line.long 0x00 "DMABCR1,DMA Byte Count Register 1" hexmask.long 0x00 0.--25. 1. " BC ,Byte Count" line.long 0x04 "DMANDAR1,DMA Next Descriptor Address Register 1" hexmask.long 0x04 5.--31. 0x20 " NDA ,Next Descriptor Address" bitfld.long 0x04 4. " NSNEN ,Next Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " NEOSIE ,Next End-of-Segment Interrupt Enable" "Not generated,Generated" bitfld.long 0x04 0. " EOTD ,End-of-Transfer Descriptor" "Not last one,Last one" group.long 0x8200++0x0b "Channel 2" line.long 0x00 "DMAMR2,DMA Mode Register 2" bitfld.long 0x00 24.--27. " DRCNT ,DMA Request CouNt" "Reserved,Reserved,Reserved,Reserved,Reserved,1 cache line,2 cache lines,4 cache lines,8 cache lines,6 cache lines,32 cache lines,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 21.--23. " BWC ,Bandwidth Control" "1 cache line,2 cache lines,4 cache lines,8 cache lines,16 cache lines,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 20. " DMSEN ,Direct Mode Snoop Enable" "Disabled,Enabled" bitfld.long 0x00 19. " IRQS ,Interrupt Stee" "Local processor,PCI bus" textline " " bitfld.long 0x00 18. " EMSEN ,External Master Start Enable" "By software,By hardware" bitfld.long 0x00 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" textline " " bitfld.long 0x00 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination Address Hold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SAHE ,Source Address Hold Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " PRC ,PCI Read Command" "Read,Read Line,Read Multiple,Reserved" textline " " bitfld.long 0x00 7. " EOTIE ,End-of-Transfer Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 3. " TEM ,Transfer Error Mask" "Halted,Completed" textline " " bitfld.long 0x00 2. " CTM ,Channel Transfer Mode" "Chaining,Direct" bitfld.long 0x00 1. " CC ,Channel Continue" "No restart,Restart" textline " " bitfld.long 0x00 0. " CS ,Channel Start" "Stopped,Started" line.long 0x04 "DMASR2,DMA Status Register 2" eventfld.long 0x04 7. " TE ,Transfer Error" "No error,Error" bitfld.long 0x04 2. " CB ,Channel Busy" "Not busy,Busy" textline " " eventfld.long 0x04 1. " EOSI ,End-of-Segment Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 0. " EOCDI ,End-of-Chain/Direct Interrupt" "No interrupt,Interrupt" line.long 0x08 "DMACDAR2,DMA Current Descriptor Address Register 2" hexmask.long 0x08 5.--31. 0x20 " CDA ,Current Descriptor Address" bitfld.long 0x08 4. " SNEN ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EOSIE ,End-of-Segment Interrupt Enable" "Not generated,Generated" group.long (0x8200+0x10)++0x03 line.long 0x00 "DMASAR2,DMA Source Address Register 2" group.long (0x8200+0x18)++0x03 line.long 0x00 "DMADAR2,DMA Destination Address Register 2" group.long (0x8200+0x20)++0x07 line.long 0x00 "DMABCR2,DMA Byte Count Register 2" hexmask.long 0x00 0.--25. 1. " BC ,Byte Count" line.long 0x04 "DMANDAR2,DMA Next Descriptor Address Register 2" hexmask.long 0x04 5.--31. 0x20 " NDA ,Next Descriptor Address" bitfld.long 0x04 4. " NSNEN ,Next Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " NEOSIE ,Next End-of-Segment Interrupt Enable" "Not generated,Generated" bitfld.long 0x04 0. " EOTD ,End-of-Transfer Descriptor" "Not last one,Last one" group.long 0x8280++0x0b "Channel 3" line.long 0x00 "DMAMR3,DMA Mode Register 3" bitfld.long 0x00 24.--27. " DRCNT ,DMA Request CouNt" "Reserved,Reserved,Reserved,Reserved,Reserved,1 cache line,2 cache lines,4 cache lines,8 cache lines,6 cache lines,32 cache lines,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 21.--23. " BWC ,Bandwidth Control" "1 cache line,2 cache lines,4 cache lines,8 cache lines,16 cache lines,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 20. " DMSEN ,Direct Mode Snoop Enable" "Disabled,Enabled" bitfld.long 0x00 19. " IRQS ,Interrupt Stee" "Local processor,PCI bus" textline " " bitfld.long 0x00 18. " EMSEN ,External Master Start Enable" "By software,By hardware" bitfld.long 0x00 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" textline " " bitfld.long 0x00 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination Address Hold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SAHE ,Source Address Hold Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " PRC ,PCI Read Command" "Read,Read Line,Read Multiple,Reserved" textline " " bitfld.long 0x00 7. " EOTIE ,End-of-Transfer Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 3. " TEM ,Transfer Error Mask" "Halted,Completed" textline " " bitfld.long 0x00 2. " CTM ,Channel Transfer Mode" "Chaining,Direct" bitfld.long 0x00 1. " CC ,Channel Continue" "No restart,Restart" textline " " bitfld.long 0x00 0. " CS ,Channel Start" "Stopped,Started" line.long 0x04 "DMASR3,DMA Status Register 3" eventfld.long 0x04 7. " TE ,Transfer Error" "No error,Error" bitfld.long 0x04 2. " CB ,Channel Busy" "Not busy,Busy" textline " " eventfld.long 0x04 1. " EOSI ,End-of-Segment Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 0. " EOCDI ,End-of-Chain/Direct Interrupt" "No interrupt,Interrupt" line.long 0x08 "DMACDAR3,DMA Current Descriptor Address Register 3" hexmask.long 0x08 5.--31. 0x20 " CDA ,Current Descriptor Address" bitfld.long 0x08 4. " SNEN ,Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EOSIE ,End-of-Segment Interrupt Enable" "Not generated,Generated" group.long (0x8280+0x10)++0x03 line.long 0x00 "DMASAR3,DMA Source Address Register 3" group.long (0x8280+0x18)++0x03 line.long 0x00 "DMADAR3,DMA Destination Address Register 3" group.long (0x8280+0x20)++0x07 line.long 0x00 "DMABCR3,DMA Byte Count Register 3" hexmask.long 0x00 0.--25. 1. " BC ,Byte Count" line.long 0x04 "DMANDAR3,DMA Next Descriptor Address Register 3" hexmask.long 0x04 5.--31. 0x20 " NDA ,Next Descriptor Address" bitfld.long 0x04 4. " NSNEN ,Next Snoop Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " NEOSIE ,Next End-of-Segment Interrupt Enable" "Not generated,Generated" bitfld.long 0x04 0. " EOTD ,End-of-Transfer Descriptor" "Not last one,Last one" endif tree.end tree "General Status Register" if (data.long(ANC:iobase()+0xf04)&0x00000800)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else rgroup.long 0x82a8++0x03 line.long 0x00 "DMAGSR,DMA General Status Register" hexmask.long.byte 0x00 24.--31. 1. " Ch0Stat ,Channel 0 Status" hexmask.long.byte 0x00 16.--23. 1. " Ch1Stat ,Channel 1 Status" textline " " hexmask.long.byte 0x00 8.--15. 1. " Ch2Stat ,Channel 2 Status" hexmask.long.byte 0x00 0.--7. 1. " Ch3Stat ,Channel 3 Status" endif tree.end tree.end tree "FIFOC (PSC Centralized FIFO Controller IMMRBAR + 0x11f00)" width 0x11 tree "PSC0" group.long 0x11080++0x07 line.long 0x00 "PSC0_TX_CMD,Command Register for PSC0 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC0_TX_ALARM,Alarm Level For PSC0 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11080+0x08)++0x03 line.long 0x00 "PSC0_TX_SR,Status Register For PSC0 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11080+0x0c)++0x07 line.long 0x00 "PSC0_TX_ISR,Interrupt status Register For PSC0 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC0_TX_IMR,Interrupt Mask Register For PSC0 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11080+0x14)++0x07 line.long 0x00 "PSC0_TX_COUNT,FIFO Count For PSC0 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC0_TX_POINTER,FIFO Pointer For PSC0 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11080+0x1c)++0x03 line.long 0x00 "PSC0_TX_SIZE,FIFO Size Register For PSC0 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11080+0x3c)++0x03 line.long 0x00 "PSC0_TX_DATA,FIFO Data Register For PSC0 TX Slice" group.long 0x110C0++0x07 line.long 0x00 "PSC0_RX_CMD,Command Register for PSC0 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC0_RX_ALARM,Alarm Level For PSC0 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x110C0+0x08)++0x03 line.long 0x00 "PSC0_RX_SR,Status Register For PSC0 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x110C0+0x0c)++0x07 line.long 0x00 "PSC0_RX_INTSTAT,Interrupt status Register For PSC0 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC0_RX_INTMASK,Interrupt Mask Register For PSC0 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x110C0+0x14)++0x07 line.long 0x00 "PSC0_RX_COUNT,FIFO Count For PSC0 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC0_RX_POINTER,FIFO Pointer For PSC0 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x110C0+0x1c)++0x03 line.long 0x00 "PSC0_RX_SIZE,FIFO Size Register For PSC0 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x110C0+0x3c)++0x03 hide.long 0x00 "PSC0_RX_DATA,FIFO Data Register For PSC0 RX Slice" in tree.end tree "PSC1" group.long 0x11180++0x07 line.long 0x00 "PSC1_TX_CMD,Command Register for PSC1 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC1_TX_ALARM,Alarm Level For PSC1 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11180+0x08)++0x03 line.long 0x00 "PSC1_TX_SR,Status Register For PSC1 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11180+0x0c)++0x07 line.long 0x00 "PSC1_TX_ISR,Interrupt status Register For PSC1 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC1_TX_IMR,Interrupt Mask Register For PSC1 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11180+0x14)++0x07 line.long 0x00 "PSC1_TX_COUNT,FIFO Count For PSC1 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC1_TX_POINTER,FIFO Pointer For PSC1 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11180+0x1c)++0x03 line.long 0x00 "PSC1_TX_SIZE,FIFO Size Register For PSC1 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11180+0x3c)++0x03 line.long 0x00 "PSC1_TX_DATA,FIFO Data Register For PSC1 TX Slice" group.long 0x111C0++0x07 line.long 0x00 "PSC1_RX_CMD,Command Register for PSC1 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC1_RX_ALARM,Alarm Level For PSC1 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x111C0+0x08)++0x03 line.long 0x00 "PSC1_RX_SR,Status Register For PSC1 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x111C0+0x0c)++0x07 line.long 0x00 "PSC1_RX_INTSTAT,Interrupt status Register For PSC1 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC1_RX_INTMASK,Interrupt Mask Register For PSC1 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x111C0+0x14)++0x07 line.long 0x00 "PSC1_RX_COUNT,FIFO Count For PSC1 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC1_RX_POINTER,FIFO Pointer For PSC1 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x111C0+0x1c)++0x03 line.long 0x00 "PSC1_RX_SIZE,FIFO Size Register For PSC1 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x111C0+0x3c)++0x03 hide.long 0x00 "PSC1_RX_DATA,FIFO Data Register For PSC1 RX Slice" in tree.end tree "PSC2" group.long 0x11280++0x07 line.long 0x00 "PSC2_TX_CMD,Command Register for PSC2 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC2_TX_ALARM,Alarm Level For PSC2 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11280+0x08)++0x03 line.long 0x00 "PSC2_TX_SR,Status Register For PSC2 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11280+0x0c)++0x07 line.long 0x00 "PSC2_TX_ISR,Interrupt status Register For PSC2 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC2_TX_IMR,Interrupt Mask Register For PSC2 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11280+0x14)++0x07 line.long 0x00 "PSC2_TX_COUNT,FIFO Count For PSC2 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC2_TX_POINTER,FIFO Pointer For PSC2 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11280+0x1c)++0x03 line.long 0x00 "PSC2_TX_SIZE,FIFO Size Register For PSC2 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11280+0x3c)++0x03 line.long 0x00 "PSC2_TX_DATA,FIFO Data Register For PSC2 TX Slice" group.long 0x112C0++0x07 line.long 0x00 "PSC2_RX_CMD,Command Register for PSC2 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC2_RX_ALARM,Alarm Level For PSC2 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x112C0+0x08)++0x03 line.long 0x00 "PSC2_RX_SR,Status Register For PSC2 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x112C0+0x0c)++0x07 line.long 0x00 "PSC2_RX_INTSTAT,Interrupt status Register For PSC2 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC2_RX_INTMASK,Interrupt Mask Register For PSC2 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x112C0+0x14)++0x07 line.long 0x00 "PSC2_RX_COUNT,FIFO Count For PSC2 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC2_RX_POINTER,FIFO Pointer For PSC2 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x112C0+0x1c)++0x03 line.long 0x00 "PSC2_RX_SIZE,FIFO Size Register For PSC2 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x112C0+0x3c)++0x03 hide.long 0x00 "PSC2_RX_DATA,FIFO Data Register For PSC2 RX Slice" in tree.end tree "PSC3" group.long 0x11380++0x07 line.long 0x00 "PSC3_TX_CMD,Command Register for PSC3 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC3_TX_ALARM,Alarm Level For PSC3 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11380+0x08)++0x03 line.long 0x00 "PSC3_TX_SR,Status Register For PSC3 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11380+0x0c)++0x07 line.long 0x00 "PSC3_TX_ISR,Interrupt status Register For PSC3 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC3_TX_IMR,Interrupt Mask Register For PSC3 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11380+0x14)++0x07 line.long 0x00 "PSC3_TX_COUNT,FIFO Count For PSC3 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC3_TX_POINTER,FIFO Pointer For PSC3 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11380+0x1c)++0x03 line.long 0x00 "PSC3_TX_SIZE,FIFO Size Register For PSC3 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11380+0x3c)++0x03 line.long 0x00 "PSC3_TX_DATA,FIFO Data Register For PSC3 TX Slice" group.long 0x113C0++0x07 line.long 0x00 "PSC3_RX_CMD,Command Register for PSC3 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC3_RX_ALARM,Alarm Level For PSC3 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x113C0+0x08)++0x03 line.long 0x00 "PSC3_RX_SR,Status Register For PSC3 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x113C0+0x0c)++0x07 line.long 0x00 "PSC3_RX_INTSTAT,Interrupt status Register For PSC3 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC3_RX_INTMASK,Interrupt Mask Register For PSC3 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x113C0+0x14)++0x07 line.long 0x00 "PSC3_RX_COUNT,FIFO Count For PSC3 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC3_RX_POINTER,FIFO Pointer For PSC3 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x113C0+0x1c)++0x03 line.long 0x00 "PSC3_RX_SIZE,FIFO Size Register For PSC3 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x113C0+0x3c)++0x03 hide.long 0x00 "PSC3_RX_DATA,FIFO Data Register For PSC3 RX Slice" in tree.end tree "PSC4" group.long 0x11480++0x07 line.long 0x00 "PSC4_TX_CMD,Command Register for PSC4 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC4_TX_ALARM,Alarm Level For PSC4 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11480+0x08)++0x03 line.long 0x00 "PSC4_TX_SR,Status Register For PSC4 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11480+0x0c)++0x07 line.long 0x00 "PSC4_TX_ISR,Interrupt status Register For PSC4 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC4_TX_IMR,Interrupt Mask Register For PSC4 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11480+0x14)++0x07 line.long 0x00 "PSC4_TX_COUNT,FIFO Count For PSC4 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC4_TX_POINTER,FIFO Pointer For PSC4 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11480+0x1c)++0x03 line.long 0x00 "PSC4_TX_SIZE,FIFO Size Register For PSC4 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11480+0x3c)++0x03 line.long 0x00 "PSC4_TX_DATA,FIFO Data Register For PSC4 TX Slice" group.long 0x114C0++0x07 line.long 0x00 "PSC4_RX_CMD,Command Register for PSC4 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC4_RX_ALARM,Alarm Level For PSC4 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x114C0+0x08)++0x03 line.long 0x00 "PSC4_RX_SR,Status Register For PSC4 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x114C0+0x0c)++0x07 line.long 0x00 "PSC4_RX_INTSTAT,Interrupt status Register For PSC4 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC4_RX_INTMASK,Interrupt Mask Register For PSC4 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x114C0+0x14)++0x07 line.long 0x00 "PSC4_RX_COUNT,FIFO Count For PSC4 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC4_RX_POINTER,FIFO Pointer For PSC4 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x114C0+0x1c)++0x03 line.long 0x00 "PSC4_RX_SIZE,FIFO Size Register For PSC4 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x114C0+0x3c)++0x03 hide.long 0x00 "PSC4_RX_DATA,FIFO Data Register For PSC4 RX Slice" in tree.end tree "PSC5" group.long 0x11580++0x07 line.long 0x00 "PSC5_TX_CMD,Command Register for PSC5 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC5_TX_ALARM,Alarm Level For PSC5 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11580+0x08)++0x03 line.long 0x00 "PSC5_TX_SR,Status Register For PSC5 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11580+0x0c)++0x07 line.long 0x00 "PSC5_TX_ISR,Interrupt status Register For PSC5 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC5_TX_IMR,Interrupt Mask Register For PSC5 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11580+0x14)++0x07 line.long 0x00 "PSC5_TX_COUNT,FIFO Count For PSC5 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC5_TX_POINTER,FIFO Pointer For PSC5 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11580+0x1c)++0x03 line.long 0x00 "PSC5_TX_SIZE,FIFO Size Register For PSC5 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11580+0x3c)++0x03 line.long 0x00 "PSC5_TX_DATA,FIFO Data Register For PSC5 TX Slice" group.long 0x115C0++0x07 line.long 0x00 "PSC5_RX_CMD,Command Register for PSC5 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC5_RX_ALARM,Alarm Level For PSC5 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x115C0+0x08)++0x03 line.long 0x00 "PSC5_RX_SR,Status Register For PSC5 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x115C0+0x0c)++0x07 line.long 0x00 "PSC5_RX_INTSTAT,Interrupt status Register For PSC5 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC5_RX_INTMASK,Interrupt Mask Register For PSC5 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x115C0+0x14)++0x07 line.long 0x00 "PSC5_RX_COUNT,FIFO Count For PSC5 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC5_RX_POINTER,FIFO Pointer For PSC5 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x115C0+0x1c)++0x03 line.long 0x00 "PSC5_RX_SIZE,FIFO Size Register For PSC5 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x115C0+0x3c)++0x03 hide.long 0x00 "PSC5_RX_DATA,FIFO Data Register For PSC5 RX Slice" in tree.end tree "PSC6" group.long 0x11680++0x07 line.long 0x00 "PSC6_TX_CMD,Command Register for PSC6 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC6_TX_ALARM,Alarm Level For PSC6 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11680+0x08)++0x03 line.long 0x00 "PSC6_TX_SR,Status Register For PSC6 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11680+0x0c)++0x07 line.long 0x00 "PSC6_TX_ISR,Interrupt status Register For PSC6 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC6_TX_IMR,Interrupt Mask Register For PSC6 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11680+0x14)++0x07 line.long 0x00 "PSC6_TX_COUNT,FIFO Count For PSC6 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC6_TX_POINTER,FIFO Pointer For PSC6 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11680+0x1c)++0x03 line.long 0x00 "PSC6_TX_SIZE,FIFO Size Register For PSC6 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11680+0x3c)++0x03 line.long 0x00 "PSC6_TX_DATA,FIFO Data Register For PSC6 TX Slice" group.long 0x116C0++0x07 line.long 0x00 "PSC6_RX_CMD,Command Register for PSC6 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC6_RX_ALARM,Alarm Level For PSC6 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x116C0+0x08)++0x03 line.long 0x00 "PSC6_RX_SR,Status Register For PSC6 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x116C0+0x0c)++0x07 line.long 0x00 "PSC6_RX_INTSTAT,Interrupt status Register For PSC6 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC6_RX_INTMASK,Interrupt Mask Register For PSC6 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x116C0+0x14)++0x07 line.long 0x00 "PSC6_RX_COUNT,FIFO Count For PSC6 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC6_RX_POINTER,FIFO Pointer For PSC6 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x116C0+0x1c)++0x03 line.long 0x00 "PSC6_RX_SIZE,FIFO Size Register For PSC6 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x116C0+0x3c)++0x03 hide.long 0x00 "PSC6_RX_DATA,FIFO Data Register For PSC6 RX Slice" in tree.end tree "PSC7" group.long 0x11780++0x07 line.long 0x00 "PSC7_TX_CMD,Command Register for PSC7 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC7_TX_ALARM,Alarm Level For PSC7 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11780+0x08)++0x03 line.long 0x00 "PSC7_TX_SR,Status Register For PSC7 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11780+0x0c)++0x07 line.long 0x00 "PSC7_TX_ISR,Interrupt status Register For PSC7 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC7_TX_IMR,Interrupt Mask Register For PSC7 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11780+0x14)++0x07 line.long 0x00 "PSC7_TX_COUNT,FIFO Count For PSC7 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC7_TX_POINTER,FIFO Pointer For PSC7 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11780+0x1c)++0x03 line.long 0x00 "PSC7_TX_SIZE,FIFO Size Register For PSC7 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11780+0x3c)++0x03 line.long 0x00 "PSC7_TX_DATA,FIFO Data Register For PSC7 TX Slice" group.long 0x117C0++0x07 line.long 0x00 "PSC7_RX_CMD,Command Register for PSC7 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC7_RX_ALARM,Alarm Level For PSC7 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x117C0+0x08)++0x03 line.long 0x00 "PSC7_RX_SR,Status Register For PSC7 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x117C0+0x0c)++0x07 line.long 0x00 "PSC7_RX_INTSTAT,Interrupt status Register For PSC7 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC7_RX_INTMASK,Interrupt Mask Register For PSC7 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x117C0+0x14)++0x07 line.long 0x00 "PSC7_RX_COUNT,FIFO Count For PSC7 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC7_RX_POINTER,FIFO Pointer For PSC7 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x117C0+0x1c)++0x03 line.long 0x00 "PSC7_RX_SIZE,FIFO Size Register For PSC7 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x117C0+0x3c)++0x03 hide.long 0x00 "PSC7_RX_DATA,FIFO Data Register For PSC7 RX Slice" in tree.end tree "PSC8" group.long 0x11880++0x07 line.long 0x00 "PSC8_TX_CMD,Command Register for PSC8 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC8_TX_ALARM,Alarm Level For PSC8 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11880+0x08)++0x03 line.long 0x00 "PSC8_TX_SR,Status Register For PSC8 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11880+0x0c)++0x07 line.long 0x00 "PSC8_TX_ISR,Interrupt status Register For PSC8 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC8_TX_IMR,Interrupt Mask Register For PSC8 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11880+0x14)++0x07 line.long 0x00 "PSC8_TX_COUNT,FIFO Count For PSC8 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC8_TX_POINTER,FIFO Pointer For PSC8 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11880+0x1c)++0x03 line.long 0x00 "PSC8_TX_SIZE,FIFO Size Register For PSC8 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11880+0x3c)++0x03 line.long 0x00 "PSC8_TX_DATA,FIFO Data Register For PSC8 TX Slice" group.long 0x118C0++0x07 line.long 0x00 "PSC8_RX_CMD,Command Register for PSC8 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC8_RX_ALARM,Alarm Level For PSC8 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x118C0+0x08)++0x03 line.long 0x00 "PSC8_RX_SR,Status Register For PSC8 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x118C0+0x0c)++0x07 line.long 0x00 "PSC8_RX_INTSTAT,Interrupt status Register For PSC8 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC8_RX_INTMASK,Interrupt Mask Register For PSC8 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x118C0+0x14)++0x07 line.long 0x00 "PSC8_RX_COUNT,FIFO Count For PSC8 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC8_RX_POINTER,FIFO Pointer For PSC8 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x118C0+0x1c)++0x03 line.long 0x00 "PSC8_RX_SIZE,FIFO Size Register For PSC8 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x118C0+0x3c)++0x03 hide.long 0x00 "PSC8_RX_DATA,FIFO Data Register For PSC8 RX Slice" in tree.end tree "PSC9" group.long 0x11980++0x07 line.long 0x00 "PSC9_TX_CMD,Command Register for PSC9 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC9_TX_ALARM,Alarm Level For PSC9 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11980+0x08)++0x03 line.long 0x00 "PSC9_TX_SR,Status Register For PSC9 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11980+0x0c)++0x07 line.long 0x00 "PSC9_TX_ISR,Interrupt status Register For PSC9 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC9_TX_IMR,Interrupt Mask Register For PSC9 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11980+0x14)++0x07 line.long 0x00 "PSC9_TX_COUNT,FIFO Count For PSC9 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC9_TX_POINTER,FIFO Pointer For PSC9 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11980+0x1c)++0x03 line.long 0x00 "PSC9_TX_SIZE,FIFO Size Register For PSC9 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11980+0x3c)++0x03 line.long 0x00 "PSC9_TX_DATA,FIFO Data Register For PSC9 TX Slice" group.long 0x119C0++0x07 line.long 0x00 "PSC9_RX_CMD,Command Register for PSC9 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC9_RX_ALARM,Alarm Level For PSC9 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x119C0+0x08)++0x03 line.long 0x00 "PSC9_RX_SR,Status Register For PSC9 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x119C0+0x0c)++0x07 line.long 0x00 "PSC9_RX_INTSTAT,Interrupt status Register For PSC9 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC9_RX_INTMASK,Interrupt Mask Register For PSC9 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x119C0+0x14)++0x07 line.long 0x00 "PSC9_RX_COUNT,FIFO Count For PSC9 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC9_RX_POINTER,FIFO Pointer For PSC9 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x119C0+0x1c)++0x03 line.long 0x00 "PSC9_RX_SIZE,FIFO Size Register For PSC9 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x119C0+0x3c)++0x03 hide.long 0x00 "PSC9_RX_DATA,FIFO Data Register For PSC9 RX Slice" in tree.end tree "PSC10" group.long 0x11A80++0x07 line.long 0x00 "PSC10_TX_CMD,Command Register for PSC10 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC10_TX_ALARM,Alarm Level For PSC10 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11A80+0x08)++0x03 line.long 0x00 "PSC10_TX_SR,Status Register For PSC10 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11A80+0x0c)++0x07 line.long 0x00 "PSC10_TX_ISR,Interrupt status Register For PSC10 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC10_TX_IMR,Interrupt Mask Register For PSC10 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11A80+0x14)++0x07 line.long 0x00 "PSC10_TX_COUNT,FIFO Count For PSC10 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC10_TX_POINTER,FIFO Pointer For PSC10 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11A80+0x1c)++0x03 line.long 0x00 "PSC10_TX_SIZE,FIFO Size Register For PSC10 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11A80+0x3c)++0x03 line.long 0x00 "PSC10_TX_DATA,FIFO Data Register For PSC10 TX Slice" group.long 0x11AC0++0x07 line.long 0x00 "PSC10_RX_CMD,Command Register for PSC10 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC10_RX_ALARM,Alarm Level For PSC10 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11AC0+0x08)++0x03 line.long 0x00 "PSC10_RX_SR,Status Register For PSC10 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11AC0+0x0c)++0x07 line.long 0x00 "PSC10_RX_INTSTAT,Interrupt status Register For PSC10 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC10_RX_INTMASK,Interrupt Mask Register For PSC10 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11AC0+0x14)++0x07 line.long 0x00 "PSC10_RX_COUNT,FIFO Count For PSC10 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC10_RX_POINTER,FIFO Pointer For PSC10 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11AC0+0x1c)++0x03 line.long 0x00 "PSC10_RX_SIZE,FIFO Size Register For PSC10 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x11AC0+0x3c)++0x03 hide.long 0x00 "PSC10_RX_DATA,FIFO Data Register For PSC10 RX Slice" in tree.end tree "PSC11" group.long 0x11B80++0x07 line.long 0x00 "PSC11_TX_CMD,Command Register for PSC11 TX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC11_TX_ALARM,Alarm Level For PSC11 TX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11B80+0x08)++0x03 line.long 0x00 "PSC11_TX_SR,Status Register For PSC11 TX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11B80+0x0c)++0x07 line.long 0x00 "PSC11_TX_ISR,Interrupt status Register For PSC11 TX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC11_TX_IMR,Interrupt Mask Register For PSC11 TX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11B80+0x14)++0x07 line.long 0x00 "PSC11_TX_COUNT,FIFO Count For PSC11 TX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC11_TX_POINTER,FIFO Pointer For PSC11 TX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11B80+0x1c)++0x03 line.long 0x00 "PSC11_TX_SIZE,FIFO Size Register For PSC11 TX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" group.long (0x11B80+0x3c)++0x03 line.long 0x00 "PSC11_TX_DATA,FIFO Data Register For PSC11 TX Slice" group.long 0x11BC0++0x07 line.long 0x00 "PSC11_RX_CMD,Command Register for PSC11 RX Slice" bitfld.long 0x00 8. " EOF ,End of Frame" "Reserved,Next data word" bitfld.long 0x00 7. " Reset_Slice ,Reset the This FIFO Slice" "Reserved,Reset" textline " " bitfld.long 0x00 3. " AXE_EN ,Request to The AXE Engine Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMA_EN ,Request To The DMA Engine Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SLICE_EN ,Slice of the FIFO Enable" "Disabled,Enabled" line.long 0x04 "PSC11_RX_ALARM,Alarm Level For PSC11 RX Slice Register" hexmask.long.word 0x04 0.--11. 1. " ALARM_LEVEL ,The number of data bytes in the FIFO when the alarm status appears" rgroup.long (0x11BC0+0x08)++0x03 line.long 0x00 "PSC11_RX_SR,Status Register For PSC11 RX Slice" bitfld.long 0x00 15. " DEBUG MODE ,Debug Mode" "Disabled,Enabled" bitfld.long 0x00 7. " SIZE ZERO ,Size Zero" "Not zero,Zero" textline " " bitfld.long 0x00 6. " MEM ERROR ,Memory Access Error" "No error,Error" bitfld.long 0x00 5. " DATA READY ,Data Ready" "Empty,Not empty" textline " " bitfld.long 0x00 4. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.long 0x00 3. " URERR ,Underrun Error" "No error,Error" bitfld.long 0x00 2. " ALARM ,FIFO Alarm" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FULL ,FIFO Full" "Not full,Full" bitfld.long 0x00 0. " EMPTY ,FIFO Empty" "Not empty,Empty" group.long (0x11BC0+0x0c)++0x07 line.long 0x00 "PSC11_RX_INTSTAT,Interrupt status Register For PSC11 RX Slice" eventfld.long 0x00 6. " MEM_ERROR ,Memory Access Error Interrupt" "Not generated,Generated" eventfld.long 0x00 5. " DATA_READY ,Data Ready Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 4. " ORERR ,Overrun Error Interrupt" "Not generated,Generated" eventfld.long 0x00 3. " URERR ,Underrun Error Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 2. " ALARM ,FIFO Alarm Interrupt" "Not generated,Generated" eventfld.long 0x00 1. " FULL ,FIFO Full Interrupt" "Not generated,Generated" textline " " eventfld.long 0x00 0. " EMPTY ,FIFO Empty Interrupt" "Not generated,Generated" line.long 0x04 "PSC11_RX_INTMASK,Interrupt Mask Register For PSC11 RX Slice" bitfld.long 0x04 6. " MEM_Error ,Memory Access Error Interrupt" "Masked,Enabled" bitfld.long 0x04 5. " DATA_READY ,Data Ready Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 4. " ORERR ,Overrun Error Interrupt" "Masked,Enabled" bitfld.long 0x04 3. " URERR ,Underrun Error Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 2. " ALARM ,FIFO Alarm Interrupt" "Masked,Enabled" bitfld.long 0x04 1. " FULL ,FIFO Full Interrupt" "Masked,Enabled" textline " " bitfld.long 0x04 0. " EMPTY ,FIFO Empty Interrupt" "Masked,Enabled" rgroup.long (0x11BC0+0x14)++0x07 line.long 0x00 "PSC11_RX_COUNT,FIFO Count For PSC11 RX Slice" hexmask.long.word 0x00 0.--12. 1. " COUNT ,Number of Bytes in The FIFO" line.long 0x04 "PSC11_RX_POINTER,FIFO Pointer For PSC11 RX Slice" hexmask.long.word 0x04 16.--28. 1. " WRITE_POINTER ,Current Write Position in Memory Without The Offset For The Slice Number" hexmask.long.word 0x04 0.--12. 1. " READ_POINTER ,Current Read Position in Memory Without The Offset For The Slice Number" group.long (0x11BC0+0x1c)++0x03 line.long 0x00 "PSC11_RX_SIZE,FIFO Size Register For PSC11 RX Slice" hexmask.long.word 0x00 16.--25. 1. " FIFO_START_ADDRESS ,Start Address For This FIFO Slice" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Size (Number of Words) of This FIFO Slice" hgroup.long (0x11BC0+0x3c)++0x03 hide.long 0x00 "PSC11_RX_DATA,FIFO Data Register For PSC11 RX Slice" in tree.end tree "FIFOC Common Registers" ;adress: base / base + 0xf00 (0x12e00) group.long 0x11f00++0x03 line.long 0x00 "FIFOC_CMD,FIFOC Command Register" bitfld.long 0x00 0. " CLOCK_GATE_EN ,Dynamic Cock Gating Enabled" "Disabled,Enabled" rgroup.long 0x11f04++0x0b line.long 0x00 "FIFOC_INT,FIFOC Interrupt Register" bitfld.long 0x00 27. " FIFOC_RX_INT11 ,PSC11 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 26. " FIFOC_RX_INT10 ,PSC10 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 25. " FIFOC_RX_INT9 ,PSC9 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 24. " FIFOC_RX_INT8 ,PSC8 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 23. " FIFOC_RX_INT7 ,PSC7 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 22. " FIFOC_RX_INT6 ,PSC6 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 21. " FIFOC_RX_INT5 ,PSC5 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 20. " FIFOC_RX_INT4 ,PSC4 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 19. " FIFOC_RX_INT3 ,PSC3 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 18. " FIFOC_RX_INT2 ,PSC2 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 17. " FIFOC_RX_INT1 ,PSC1 FIFOC RX Interrupt" "Not pending,Pending" bitfld.long 0x00 16. " FIFOC_RX_INT0 ,PSC0 FIFOC RX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 11. " FIFOC_TX_INT11 ,PSC11 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 10. " FIFOC_TX_INT10 ,PSC10 FIFOC TX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 9. " FIFOC_TX_INT9 ,PSC9 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 8. " FIFOC_TX_INT8 ,PSC8 FIFOC TX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 7. " FIFOC_TX_INT7 ,PSC7 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 6. " FIFOC_TX_INT6 ,PSC6 FIFOC TX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 5. " FIFOC_TX_INT5 ,PSC5 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 4. " FIFOC_TX_INT4 ,PSC4 FIFOC TX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 3. " FIFOC_TX_INT3 ,PSC3 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 2. " FIFOC_TX_INT2 ,PSC2 FIFOC TX Interrupt" "Not pending,Pending" textline " " bitfld.long 0x00 1. " FIFOC_TX_INT1 ,PSC1 FIFOC TX Interrupt" "Not pending,Pending" bitfld.long 0x00 0. " FIFOC_TX_INT0 ,PSC0 FIFOC TX Interrupt" "Not pending,Pending" line.long 0x04 "FIFOC_DMA,FIFOC DMA Request Register" bitfld.long 0x04 27. " FIFOC_RX_DMA_REQ11 ,PSC11 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 26. " FIFOC_RX_DMA_REQ10 ,PSC10 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 25. " FIFOC_RX_DMA_REQ9 ,PSC9 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 24. " FIFOC_RX_DMA_REQ8 ,PSC8 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 23. " FIFOC_RX_DMA_REQ7 ,PSC7 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 22. " FIFOC_RX_DMA_REQ6 ,PSC6 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 21. " FIFOC_RX_DMA_REQ5 ,PSC5 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 20. " FIFOC_RX_DMA_REQ4 ,PSC4 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FIFOC_RX_DMA_REQ3 ,PSC3 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 18. " FIFOC_RX_DMA_REQ2 ,PSC2 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 17. " FIFOC_RX_DMA_REQ1 ,PSC1 FIFOC RX DMA Request" "Not requested,Requested" bitfld.long 0x04 16. " FIFOC_RX_DMA_REQ0 ,PSC0 FIFOC RX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 11. " FIFOC_TX_DMA_REQ11 ,PSC11 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 10. " FIFOC_TX_DMA_REQ10 ,PSC10 FIFOC TX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 9. " FIFOC_TX_DMA_REQ9 ,PSC9 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 8. " FIFOC_TX_DMA_REQ8 ,PSC8 FIFOC TX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 7. " FIFOC_TX_DMA_REQ7 ,PSC7 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 6. " FIFOC_TX_DMA_REQ6 ,PSC6 FIFOC TX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 5. " FIFOC_TX_DMA_REQ5 ,PSC5 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 4. " FIFOC_TX_DMA_REQ4 ,PSC4 FIFOC TX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 3. " FIFOC_TX_DMA_REQ3 ,PSC3 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 2. " FIFOC_TX_DMA_REQ2 ,PSC2 FIFOC TX DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 1. " FIFOC_TX_DMA_REQ1 ,PSC1 FIFOC TX DMA Request" "Not requested,Requested" bitfld.long 0x04 0. " FIFOC_TX_DMA_REQ0 ,PSC0 FIFOC TX DMA Request" "Not requested,Requested" line.long 0x08 "FIFOC_AXE,FIFOC AXE Request Register" bitfld.long 0x08 27. " FIFOC_RX_AXE_REQ11 ,PSC11 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 26. " FIFOC_RX_AXE_REQ10 ,PSC10 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 25. " FIFOC_RX_AXE_REQ9 ,PSC9 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 24. " FIFOC_RX_AXE_REQ8 ,PSC8 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 23. " FIFOC_RX_AXE_REQ7 ,PSC7 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 22. " FIFOC_RX_AXE_REQ6 ,PSC6 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 21. " FIFOC_RX_AXE_REQ5 ,PSC5 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 20. " FIFOC_RX_AXE_REQ4 ,PSC4 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 19. " FIFOC_RX_AXE_REQ3 ,PSC3 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 18. " FIFOC_RX_AXE_REQ2 ,PSC2 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 17. " FIFOC_RX_AXE_REQ1 ,PSC1 FIFOC RX AXE Request" "Not requested,Requested" bitfld.long 0x08 16. " FIFOC_RX_AXE_REQ0 ,PSC0 FIFOC RX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 11. " FIFOC_TX_AXE_REQ11 ,PSC11 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 10. " FIFOC_TX_AXE_REQ10 ,PSC10 FIFOC TX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 9. " FIFOC_TX_AXE_REQ9 ,PSC9 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 8. " FIFOC_TX_AXE_REQ8 ,PSC8 FIFOC TX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 7. " FIFOC_TX_AXE_REQ7 ,PSC7 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 6. " FIFOC_TX_AXE_REQ6 ,PSC6 FIFOC TX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 5. " FIFOC_TX_AXE_REQ5 ,PSC5 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 4. " FIFOC_TX_AXE_REQ4 ,PSC4 FIFOC TX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 3. " FIFOC_TX_AXE_REQ3 ,PSC3 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 2. " FIFOC_TX_AXE_REQ2 ,PSC2 FIFOC TX AXE Request" "Not requested,Requested" textline " " bitfld.long 0x08 1. " FIFOC_TX_AXE_REQ1 ,PSC1 FIFOC TX AXE Request" "Not requested,Requested" bitfld.long 0x08 0. " FIFOC_TX_AXE_REQ0 ,PSC0 FIFOC TX AXE Request" "Not requested,Requested" group.long 0x11f10++0x03 line.long 0x00 "FIFOC_DEBUG,FIFOC Debug Register" bitfld.long 0x00 1. " LOCK ,State maChine Lock" "Normal,Locked" bitfld.long 0x00 0. " DEBUG ,Debug Mode" "Normal,Debug" tree.end tree.end tree "PMC (Power Management Control Module IMMRBAR + 0x1000)" width 0x8 group.long 0x1000++0x0f line.long 0x00 "PMCCR,PMC Configuration Register" bitfld.long 0x00 4. " PRE_DIV ,Pre_Div Copy Enable Mode" "Disabled,Enabled" bitfld.long 0x00 3. " CCM ,Clock Change Mode" "No operation,On-the fly" textline " " bitfld.long 0x00 2. " DSMEN ,Deep-sleep Mode Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DDROFF ,DDR SDRAM Low-Power Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " COREOFF ,System Low-Power Enable" "Disabled,Enabled" line.long 0x04 "PMCER,PMC Event Register" bitfld.long 0x04 0. " PMCI ,PMC Interrupt" "Not occurred,Occurred" line.long 0x08 "PMCMR,PMC Mask Register" bitfld.long 0x08 0. " PMCIE ,PMC Interrupt Enable" "Disabled,Enabled" line.long 0x0c "PMCSR,PMC Shadow Register" hexmask.long.byte 0x0c 0.--6. 1. " PMCSR ,New Core_PLL Configuration Data" tree.end tree "PSC (Programmable Serial Controller IMMRBAR + 11000 + n*100)" tree "PSC Channel 0" width 0xa if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 0" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 0" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 0" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 0" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11000))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 0" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 0" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 0" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 0" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 0" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 0" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 0" elif (((d.b(anc:(iobase()+0x11000))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11000+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 0" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11000)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 0" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11000)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 0" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte 0x11000++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 0" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte 0x11000++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 0" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 0" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 0" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.word (0x11000+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 0" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 0" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 0" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.byte (0x11000+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 0" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11000+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 0" in elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 0" hgroup.long (0x11000+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.byte (0x11000+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 0" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.byte (0x11000+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 0" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.byte (0x11000+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 0" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.word (0x11000+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.word (0x11000+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.word (0x11000+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.word (0x11000+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 0" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.word (0x11000+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.byte (0x11000+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 0" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.byte (0x11000+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 0" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 0" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) group.long (0x11000+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 0" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.long (0x11000+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.long (0x11000+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 0" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11000+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 0" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11000+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 0" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.long (0x11000+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 0" hgroup.long (0x11000+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 0" hgroup.long (0x11000+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.byte (0x11000+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 0" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.byte (0x11000+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 0" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) rgroup.byte (0x11000+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 0" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.byte (0x11000+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 0" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11000+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 0" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) wgroup.byte (0x11000+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 0" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11000+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 0" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11000+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>0.))!=0)) hgroup.byte (0x11000+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 0" hgroup.byte (0x11000+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 0" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 1" width 0xa if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 1" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 1" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 1" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 1" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11100))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 1" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 1" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 1" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 1" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 1" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 1" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 1" elif (((d.b(anc:(iobase()+0x11100))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11100+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 1" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11100)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 1" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11100)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 1" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte 0x11100++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 1" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte 0x11100++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 1" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 1" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 1" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.word (0x11100+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 1" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 1" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 1" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.byte (0x11100+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 1" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11100+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 1" in elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 1" hgroup.long (0x11100+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.byte (0x11100+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 1" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.byte (0x11100+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 1" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.byte (0x11100+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 1" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.word (0x11100+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.word (0x11100+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.word (0x11100+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.word (0x11100+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 1" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.word (0x11100+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.byte (0x11100+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 1" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.byte (0x11100+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 1" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 1" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) group.long (0x11100+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 1" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.long (0x11100+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.long (0x11100+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 1" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11100+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 1" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11100+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 1" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.long (0x11100+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 1" hgroup.long (0x11100+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 1" hgroup.long (0x11100+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.byte (0x11100+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 1" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.byte (0x11100+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 1" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) rgroup.byte (0x11100+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 1" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.byte (0x11100+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 1" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11100+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 1" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) wgroup.byte (0x11100+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 1" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11100+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 1" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11100+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>1.))!=0)) hgroup.byte (0x11100+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 1" hgroup.byte (0x11100+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 1" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 2" width 0xa if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 2" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 2" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 2" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 2" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11200))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 2" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 2" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 2" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 2" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 2" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 2" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 2" elif (((d.b(anc:(iobase()+0x11200))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11200+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 2" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11200)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 2" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11200)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 2" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte 0x11200++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 2" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte 0x11200++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 2" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 2" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 2" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.word (0x11200+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 2" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 2" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 2" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.byte (0x11200+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 2" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11200+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 2" in elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 2" hgroup.long (0x11200+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.byte (0x11200+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 2" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.byte (0x11200+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 2" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.byte (0x11200+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 2" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.word (0x11200+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.word (0x11200+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.word (0x11200+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.word (0x11200+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 2" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.word (0x11200+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.byte (0x11200+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 2" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.byte (0x11200+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 2" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 2" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) group.long (0x11200+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 2" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.long (0x11200+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.long (0x11200+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 2" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11200+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 2" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11200+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 2" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.long (0x11200+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 2" hgroup.long (0x11200+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 2" hgroup.long (0x11200+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.byte (0x11200+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 2" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.byte (0x11200+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 2" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) rgroup.byte (0x11200+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 2" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.byte (0x11200+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 2" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11200+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 2" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) wgroup.byte (0x11200+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 2" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11200+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 2" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11200+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>2.))!=0)) hgroup.byte (0x11200+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 2" hgroup.byte (0x11200+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 2" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 3" width 0xa if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 3" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 3" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 3" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 3" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11300))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 3" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 3" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 3" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 3" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 3" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 3" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 3" elif (((d.b(anc:(iobase()+0x11300))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11300+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 3" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11300)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 3" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11300)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 3" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte 0x11300++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 3" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte 0x11300++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 3" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 3" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 3" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.word (0x11300+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 3" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 3" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 3" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.byte (0x11300+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 3" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11300+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 3" in elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 3" hgroup.long (0x11300+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.byte (0x11300+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 3" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.byte (0x11300+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 3" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.byte (0x11300+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 3" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.word (0x11300+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.word (0x11300+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.word (0x11300+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.word (0x11300+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 3" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.word (0x11300+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.byte (0x11300+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 3" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.byte (0x11300+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 3" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 3" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) group.long (0x11300+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 3" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.long (0x11300+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.long (0x11300+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 3" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11300+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 3" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11300+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 3" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.long (0x11300+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 3" hgroup.long (0x11300+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 3" hgroup.long (0x11300+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.byte (0x11300+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 3" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.byte (0x11300+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 3" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) rgroup.byte (0x11300+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 3" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.byte (0x11300+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 3" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11300+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 3" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) wgroup.byte (0x11300+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 3" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11300+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 3" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11300+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>3.))!=0)) hgroup.byte (0x11300+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 3" hgroup.byte (0x11300+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 3" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 4" width 0xa if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 4" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 4" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 4" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 4" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11400))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 4" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 4" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 4" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 4" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 4" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 4" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 4" elif (((d.b(anc:(iobase()+0x11400))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11400+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 4" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11400)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 4" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11400)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 4" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte 0x11400++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 4" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte 0x11400++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 4" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 4" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 4" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.word (0x11400+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 4" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 4" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 4" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.byte (0x11400+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 4" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11400+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 4" in elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 4" hgroup.long (0x11400+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.byte (0x11400+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 4" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.byte (0x11400+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 4" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.byte (0x11400+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 4" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.word (0x11400+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.word (0x11400+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.word (0x11400+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.word (0x11400+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 4" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.word (0x11400+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.byte (0x11400+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 4" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.byte (0x11400+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 4" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 4" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) group.long (0x11400+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 4" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.long (0x11400+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.long (0x11400+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 4" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11400+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 4" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11400+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 4" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.long (0x11400+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 4" hgroup.long (0x11400+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 4" hgroup.long (0x11400+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.byte (0x11400+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 4" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.byte (0x11400+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 4" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) rgroup.byte (0x11400+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 4" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.byte (0x11400+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 4" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11400+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 4" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) wgroup.byte (0x11400+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 4" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11400+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 4" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11400+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>4.))!=0)) hgroup.byte (0x11400+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 4" hgroup.byte (0x11400+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 4" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 5" width 0xa if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 5" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 5" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 5" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 5" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11500))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 5" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 5" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 5" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 5" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 5" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 5" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 5" elif (((d.b(anc:(iobase()+0x11500))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11500+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 5" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11500)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 5" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11500)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 5" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte 0x11500++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 5" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte 0x11500++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 5" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 5" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 5" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.word (0x11500+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 5" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 5" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 5" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.byte (0x11500+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 5" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11500+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 5" in elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 5" hgroup.long (0x11500+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.byte (0x11500+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 5" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.byte (0x11500+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 5" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.byte (0x11500+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 5" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.word (0x11500+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.word (0x11500+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.word (0x11500+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.word (0x11500+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 5" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.word (0x11500+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.byte (0x11500+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 5" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.byte (0x11500+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 5" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 5" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) group.long (0x11500+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 5" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.long (0x11500+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.long (0x11500+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 5" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11500+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 5" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11500+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 5" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.long (0x11500+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 5" hgroup.long (0x11500+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 5" hgroup.long (0x11500+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.byte (0x11500+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 5" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.byte (0x11500+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 5" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) rgroup.byte (0x11500+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 5" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.byte (0x11500+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 5" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11500+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 5" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) wgroup.byte (0x11500+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 5" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11500+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 5" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11500+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>5.))!=0)) hgroup.byte (0x11500+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 5" hgroup.byte (0x11500+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 5" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 6" width 0xa if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 6" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 6" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 6" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 6" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11600))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 6" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 6" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 6" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 6" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 6" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 6" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 6" elif (((d.b(anc:(iobase()+0x11600))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11600+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 6" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11600)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 6" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11600)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 6" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte 0x11600++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 6" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte 0x11600++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 6" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 6" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 6" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.word (0x11600+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 6" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 6" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 6" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.byte (0x11600+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 6" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11600+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 6" in elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 6" hgroup.long (0x11600+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.byte (0x11600+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 6" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.byte (0x11600+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 6" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.byte (0x11600+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 6" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.word (0x11600+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.word (0x11600+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.word (0x11600+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.word (0x11600+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 6" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.word (0x11600+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.byte (0x11600+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 6" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.byte (0x11600+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 6" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 6" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) group.long (0x11600+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 6" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.long (0x11600+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.long (0x11600+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 6" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11600+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 6" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11600+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 6" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.long (0x11600+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 6" hgroup.long (0x11600+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 6" hgroup.long (0x11600+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.byte (0x11600+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 6" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.byte (0x11600+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 6" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) rgroup.byte (0x11600+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 6" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.byte (0x11600+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 6" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11600+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 6" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) wgroup.byte (0x11600+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 6" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11600+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 6" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11600+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>6.))!=0)) hgroup.byte (0x11600+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 6" hgroup.byte (0x11600+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 6" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 7" width 0xa if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 7" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 7" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 7" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 7" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11700))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 7" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 7" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 7" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 7" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 7" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 7" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 7" elif (((d.b(anc:(iobase()+0x11700))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11700+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 7" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11700)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 7" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11700)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 7" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte 0x11700++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 7" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte 0x11700++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 7" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 7" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 7" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.word (0x11700+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 7" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 7" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 7" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.byte (0x11700+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 7" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11700+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 7" in elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 7" hgroup.long (0x11700+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.byte (0x11700+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 7" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.byte (0x11700+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 7" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.byte (0x11700+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 7" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.word (0x11700+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.word (0x11700+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.word (0x11700+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.word (0x11700+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 7" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.word (0x11700+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.byte (0x11700+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 7" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.byte (0x11700+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 7" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 7" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) group.long (0x11700+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 7" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.long (0x11700+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.long (0x11700+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 7" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11700+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 7" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11700+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 7" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.long (0x11700+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 7" hgroup.long (0x11700+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 7" hgroup.long (0x11700+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.byte (0x11700+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 7" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.byte (0x11700+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 7" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) rgroup.byte (0x11700+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 7" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.byte (0x11700+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 7" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11700+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 7" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) wgroup.byte (0x11700+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 7" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11700+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 7" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11700+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>7.))!=0)) hgroup.byte (0x11700+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 7" hgroup.byte (0x11700+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 7" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 8" width 0xa if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 8" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 8" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 8" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 8" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11800))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 8" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 8" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 8" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 8" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 8" elif (((d.b(anc:(iobase()+0x11800))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11800+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 8" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11800)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 8" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11800)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 8" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte 0x11800++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 8" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte 0x11800++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 8" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 8" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 8" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.word (0x11800+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 8" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 8" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 8" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.byte (0x11800+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 8" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11800+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 8" in elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 8" hgroup.long (0x11800+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.byte (0x11800+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 8" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.byte (0x11800+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 8" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.byte (0x11800+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 8" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.word (0x11800+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.word (0x11800+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.word (0x11800+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.word (0x11800+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 8" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.word (0x11800+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.byte (0x11800+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 8" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.byte (0x11800+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 8" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 8" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) group.long (0x11800+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 8" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.long (0x11800+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.long (0x11800+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 8" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11800+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 8" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11800+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 8" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.long (0x11800+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 8" hgroup.long (0x11800+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 8" hgroup.long (0x11800+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.byte (0x11800+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 8" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.byte (0x11800+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 8" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) rgroup.byte (0x11800+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 8" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.byte (0x11800+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 8" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11800+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 8" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) wgroup.byte (0x11800+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 8" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11800+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 8" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11800+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>8.))!=0)) hgroup.byte (0x11800+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 8" hgroup.byte (0x11800+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 8" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 9" width 0xa if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 9" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 9" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 9" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 9" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11900))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 9" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 9" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 9" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 9" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 9" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 9" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 9" elif (((d.b(anc:(iobase()+0x11900))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11900+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 9" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11900)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 9" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11900)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 9" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte 0x11900++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 9" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte 0x11900++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 9" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 9" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 9" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.word (0x11900+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 9" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 9" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 9" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.byte (0x11900+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 9" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11900+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 9" in elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 9" hgroup.long (0x11900+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.byte (0x11900+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 9" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.byte (0x11900+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 9" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.byte (0x11900+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 9" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.word (0x11900+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.word (0x11900+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.word (0x11900+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.word (0x11900+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 9" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.word (0x11900+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.byte (0x11900+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 9" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.byte (0x11900+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 9" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 9" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) group.long (0x11900+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 9" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.long (0x11900+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.long (0x11900+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 9" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11900+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 9" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11900+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 9" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.long (0x11900+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 9" hgroup.long (0x11900+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 9" hgroup.long (0x11900+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.byte (0x11900+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 9" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.byte (0x11900+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 9" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) rgroup.byte (0x11900+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 9" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.byte (0x11900+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 9" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11900+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 9" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) wgroup.byte (0x11900+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 9" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11900+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 9" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11900+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>9.))!=0)) hgroup.byte (0x11900+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 9" hgroup.byte (0x11900+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 9" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 10" width 0xa if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 10" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 10" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 10" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 10" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11a00))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 10" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 10" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 10" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 10" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 10" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 10" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 10" elif (((d.b(anc:(iobase()+0x11a00))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11a00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11a00)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 10" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11a00)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 10" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte 0x11a00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 10" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte 0x11a00++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 10" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 10" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 10" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.word (0x11a00+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 10" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.byte (0x11a00+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 10" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11a00+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 10" in elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 10" hgroup.long (0x11a00+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.byte (0x11a00+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 10" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.byte (0x11a00+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 10" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.byte (0x11a00+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 10" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.word (0x11a00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 10" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.word (0x11a00+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.byte (0x11a00+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.byte (0x11a00+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 10" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 10" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) group.long (0x11a00+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 10" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.long (0x11a00+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.long (0x11a00+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 10" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11a00+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 10" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11a00+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 10" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.long (0x11a00+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 10" hgroup.long (0x11a00+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 10" hgroup.long (0x11a00+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.byte (0x11a00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 10" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.byte (0x11a00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 10" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) rgroup.byte (0x11a00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 10" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.byte (0x11a00+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 10" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11a00+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 10" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) wgroup.byte (0x11a00+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 10" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11a00+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 10" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11a00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>10.))!=0)) hgroup.byte (0x11a00+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 10" hgroup.byte (0x11a00+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 10" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree "PSC Channel 11" width 0xa if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x40)++0x3 "AC97 Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 11" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 31. " ACRB ,Cold Reset to the transceiver in PSC" "Reset,No reset" bitfld.long 0x0 30. " AWR ,Warm Reset" "Reset,No reset" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x40)++0x3 "UART Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 11" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x40)++0x3 "Codec Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 11" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " bitfld.long 0x0 29. " DTS1 ,Delay of time slot #1" "No delay,Rising edge" bitfld.long 0x0 28. " SHDIR ,Shift Direction" "MSB first,LSB first" textline " " bitfld.long 0x0 23. " GenClk ,Generate Bit Clock and Frame Sync" "External,Internal" bitfld.long 0x0 22. " I2S ,I2S mode" "No I2S,I2S" textline " " bitfld.long 0x0 21. " ClkPol ,Bit Clock Polarity" "Falling edge,Rising edge" bitfld.long 0x0 20. " SyncPol ,Frame Sync Polarity" "Low,High" textline " " bitfld.long 0x0 17. " ESAI ,Enhanced Serial Audio Interface" "Not supported,Supported" bitfld.long 0x0 16. " EnAC97 ,Enhanced AC97 mode" "No effect,Enabled" textline " " bitfld.long 0x0 15. " SPI ,SPI mode" "Not SPI,SPI" bitfld.long 0x0 14. " MSTR ,SPI Master mode" "Slave,Master" textline " " bitfld.long 0x0 13. " CPOL ,SPI Clock Polarity" "Inverted,Non-inverted" bitfld.long 0x0 12. " CPHA ,SPI Clock Phase" "Normal,Half cycle" textline " " bitfld.long 0x0 11. " UseEOF ,Use End-of-Frame" "Up to 4bytes,Multiple" bitfld.long 0x0 8. " En_OutBuf ,Enable Output Buffer" "If Tx/Rx Enabled,Independent" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x40)++0x3 "Idle Mode" textline " " line.long 0x0 "SICR,Serial Interface Control Register Channel 11" bitfld.long 0x0 24.--27. " SIM[3:0] ,PSC operation mode" "UART: /DCD ignored,Codec: 8-bit,Codec: 16-bit,AC97,Reserved,Reserved,Reserved,Codec: 24-bit,UART: /DCD effective,Codec: 12-bit,Codec: 20-bit,AC97,Reserved,Reserved,Reserved,Codec: 32-bit" textline " " textline " " textline " " textline "Please choose appropriate mode" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.b(anc:(iobase()+0x11b00))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 11" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Even,Odd" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 11" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Low,High" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 11" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Reserved,Reserved" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)==0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x0 "MR1,Mode Register 1 Channel 11" bitfld.byte 0x00 7. " RxRTS ,Receiver Request-to-Send" "No effect,Negated" bitfld.byte 0x00 5. " Time_Out_En ,Enable the Time Out Counter" "Disabled,Enabled" textline " " bitfld.byte 0x00 3.--4. " PM ,Parity mode" "With parity,Force parity,No parity,Multidrop mode" bitfld.byte 0x00 2. " PT ,Parity Type" "Data,Address" textline " " bitfld.byte 0x00 0.--1. " B/C ,Bits per Character" "5,6,7,8" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x00)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 11" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x08)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 11" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x10)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 11" elif (((d.b(anc:(iobase()+0x11b00))&0x18)==0x18)&&((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:(iobase()+0x11b00+0x08))&0x70)!=0x10)&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 11" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x0 "MR1,Mode Register 1 Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11b00)&0x3)==(0x00))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 11" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "1.063,1.125,1.188,1.250,1.313,1.375,1.438,1.500,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.b(anc:iobase()+0x11b00)&0x3)==(0x01||0x20||0x03))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 11" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 5. " TxRTS ,Transmitter Ready-to-Send" "No effect,Cleared" textline " " bitfld.byte 0x00 4. " TxCTS ,Transmitter Clear-to-Send" "No effect,Enabled" bitfld.byte 0x00 0.--3. " SB ,Length Control of the Stop-Bit" "0.563,0.625,0.688,0.750,0.813,0.875,0.938,1.000,1.563,1.625,1.688,1.750,1.813,1.875,1.938,2.000" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte 0x11b00++0x0 line.byte 0x00 "MR2,Mode Register 2 Channel 11" bitfld.byte 0x00 6.--7. " CM , Channel Mode" "Normal,Automatic echo,Local loop-back,Remote loop-back" bitfld.byte 0x00 2.--3. " RX_Channels ,The Additional Number of RX Channels" "One,Two,Three,Reserved" textline " " bitfld.byte 0x00 0.--1. " TX_Channels ,The Additional Number of TX Channels" "One,Two,Three,Reserved" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte 0x11b00++0x0 hide.byte 0x00 "MR2,Mode Register 2 Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 11" bitfld.word 0x00 15. " RB ,Received Break" "Not received,Received" bitfld.word 0x00 14. " FE ,Framing Error" "No error,Error" textline " " bitfld.word 0x00 13. " PE ,Parity Error" "No error,Error" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 7. " CDE ,DCD Status" "Negated,No error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 11" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x04)++0x01 line.word 0x00 "SR,Status Register Channel 11" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" textline " " bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" textline " " bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x04)++0x01 hide.word 0x00 "SR,Status Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.word (0x11b00+0x04)++0x01 line.word 0x00 "CSR,Clock Select Register Channel 11" bitfld.word 0x00 12.--15. " RCS ,Receiver Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" bitfld.word 0x00 8.--11. " TCS ,Transmitter Clock Select Register" "Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,Prescaler by 32,External clock source,Prescaler by 10" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 11" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x03000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 11" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x04)++0x01 hide.word 0x00 "CSR,Clock Select Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x01000000||0x9000000||0x2000000||0x03000000||0xa000000||0xb000000||0x7000000||0xf000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.byte (0x11b00+0x08)++0x00 line.byte 0x00 "CR,Command Register Channel 11" bitfld.byte 0x00 4.--6. " MISC ,MISC" "No command,Reset mode,Reset receiver,Reset transmitter,Reset error status,Reset break interrupt,Start break,Stop break" bitfld.byte 0x00 2.--3. " TC ,TC" "No action,Transmitter enabled,Transmitter disabled,Reserved" textline " " bitfld.byte 0x00 0.--1. " RC ,RC" "No action,Receiver enabled,Receiver disabled,Reserved" hgroup.long (0x11b00+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 11" in elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x05000000||0x6000000||0xc000000||0x0d000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x08)++0x00 hide.byte 0x00 "CR,Command Register Channel 11" hgroup.long (0x11b00+0x0c)++0x03 hide.long 0x00 "RB/TB,Rx Buffer Register/Tx Buffer Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.byte (0x11b00+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 11" bitfld.byte 0x00 7. " SYNC ,Sync Detected" "Not detected,Detected" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" textline " " bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.byte (0x11b00+0x10)++0x00 line.byte 0x00 "IPCR,Input Port Change Register Channel 11" bitfld.byte 0x00 5. " D_DCD ,Delta DCD" "Not changed,Changed" bitfld.byte 0x00 4. " D_CTS ,Delta CTS" "Not changed,Changed" textline " " bitfld.byte 0x00 1. " DCD ,Current state of /DCD port" "Low,High" bitfld.byte 0x00 0. " CTS ,Current state of /CTS port" "Low,High" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x10)++0x00 hide.byte 0x00 "IPCR,Input Port Change Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000||0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.byte (0x11b00+0x10)++0x00 line.byte 0x00 "ACR,Auxiliary Control Register Channel 11" bitfld.byte 0x00 1. " IEC1 ,Interrupt Enable Control for D_DCD" "No effect,ISR Set" bitfld.byte 0x00 0. " IEC0 ,Interrupt Enable Control for D_CTS" "No effect,ISR Set" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x05000000||0x06000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x10)++0x00 hide.byte 0x00 "ACR,Auxiliary Control Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "Not empty,Empty" bitfld.word 0x00 10. " DB ,Delta Break State" "Not detected,Detected" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" bitfld.word 0x00 5. " Time_Out ,Time Out" "Not occurred,Occurred" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "ISR,Interrupt Status Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "Not occurred,Occurred" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No error,Error" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No error,Error" bitfld.word 0x00 6. " Error ,Error Status Detect" "Not detected,Detected" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "Sent,Not sent" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "Not overwritten,Overwritten" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "Not valid,Valid" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "Not detected,Detected" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x4000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x14)++0x01 hide.word 0x00 "ISR,Interrupt Status Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " TxEMP ,Transmitter Empty" "No effect,Enable" bitfld.word 0x00 10. " DB ,Delta Break State" "No effect,Enable" textline " " bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" bitfld.word 0x00 5. " Time_Out ,Time Out" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.word (0x11b00+0x14)++0x01 line.word 0x00 "IMR,Interrupt Mask Register Channel 11" bitfld.word 0x00 15. " IPC ,Input Port Change Interrupt" "No effect,Enable" bitfld.word 0x00 12. " ORERR ,Overrun Error" "No effect,Enable" textline " " bitfld.word 0x00 11. " URERR ,Underrun Error" "No effect,Enable" bitfld.word 0x00 6. " Error ,Error Status Detect" "No effect,Enable" textline " " bitfld.word 0x00 3. " CMD_SEND ,Command Send Ready" "No effect,Enable" bitfld.word 0x00 2. " DATA_OVR ,Receive Status Data Overwrite" "No effect,Enable" textline " " bitfld.word 0x00 1. " DATA_VALID ,Received Status Data" "No effect,Enable" bitfld.word 0x00 0. " UNEX_RX_SLOT ,Unexpected Receive Slots Detect" "No effect,Enable" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.word (0x11b00+0x14)++0x01 hide.word 0x00 "IMR,Interrupt Mask Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.byte (0x11b00+0x18)++0x00 line.byte 0x00 "CTUR,Counter Timer Upper Register Channel 11" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x18)++0x00 hide.byte 0x00 "CTUR,Counter Timer Upper Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.byte (0x11b00+0x1c)++0x00 line.byte 0x00 "CTLR,Counter Timer Lower Register Channel 11" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x03000000||0xb000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x1c)++0x00 hide.byte 0x00 "CTLR,Counter Timer Lower Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 11" hexmask.long.byte 0x00 24.--31. 1. " FrameSyncDiv[0:7] ,Frame Sync Divider" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Bit Clock Divider" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) group.long (0x11b00+0x20)++0x03 line.long 0x00 "CCR,Codec Clock Register Channel 11" hexmask.long.word 0x00 8.--23. 1. " BCLKDiv[0:15] ,Time Out count value" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000||0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.long (0x11b00+0x20)++0x03 hide.long 0x00 "CCR,Codec Clock Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.long (0x11b00+0x24)++0x3 line.long 0x0 "AC97Slots, AC97 Slots Register Channel 11" hexmask.long.word 0x0 16.--25. 1. " TX_SLOTS[3:12] ,Expected Transmit Slots" hexmask.long.word 0x0 0.--9. 1. " RX_SLOTS[3:12] ,Expected Receive Slots" group.long (0x11b00+0x28)++0x3 line.long 0x0 "AC97CMD, AC97 Command Register Channel 11" bitfld.long 0x0 31. " AC97_CMD ,Enhanced AC97 Mode" "Write,Read" hexmask.long.byte 0x0 24.--30. 1. " AC97_CR ,AC97 Address" textline " " hexmask.long.word 0x0 8.--23. 1. " AC97_CD ,AC97 Command Data" rgroup.long (0x11b00+0x2c)++0x3 line.long 0x0 "AC97Data,AC97 Status Data Register Channel 11" hexmask.long.byte 0x0 24.--30. 1. " AC97_RIE ,AC97 Register Index Echo" hexmask.long.byte 0x0 8.--23. 1. " AC97_RRD ,AC97 Control Register Read Data" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000||0x4000000||0x5000000||0x6000000||0xc000000||0x0d000000||0x0e000000||0x01000000||0x09000000||0x02000000||0xa000000||0x07000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.long (0x11b00+0x24)++0x3 hide.long 0x0 "AC97Slots, AC97 Slots Register Channel 11" hgroup.long (0x11b00+0x28)++0x3 hide.long 0x0 "AC97CMD, AC97 Command Register Channel 11" hgroup.long (0x11b00+0x2c)++0x3 hide.long 0x0 "AC97Data,AC97 Status Data Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.byte (0x11b00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 11" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" textline " " bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.byte (0x11b00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 11" bitfld.byte 0x00 7. " LPWR ,Low-power mode in AC97 Mode" "Low-power,Normal" bitfld.byte 0x00 6. " TGL ,Test usage" "Low,High" textline " " bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x00000000||0x8000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) rgroup.byte (0x11b00+0x34)++0x00 line.byte 0x00 "IP,Input Port Register Channel 11" bitfld.byte 0x00 1. " DCD ,Current State of The /DCD Input" "Low,High" bitfld.byte 0x00 0. " CTS ,Current State of The /CTS Input" "Low,High" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x34)++0x00 hide.byte 0x00 "IP,Input Port Register Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x3000000||0xb000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.byte (0x11b00+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 11" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not asserted,Asserted" wgroup.byte (0x11b00+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 11" bitfld.byte 0x00 1. " RES ,Assert RES Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x01000000||0x9000000||0x2000000||0xa000000||0x7000000||0xf000000||0x00000000||0x08000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) wgroup.byte (0x11b00+0x38)++0x00 line.byte 0x00 "OP1,Output Port 1 Bit Set Channel 11" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not asserted,Asserted" wgroup.byte (0x11b00+0x3c)++0x00 line.byte 0x00 "OP0,Output Port 0 Bit Set Channel 11" bitfld.byte 0x00 0. " RTS ,Assert RTS Output" "Not negated,Negated" elif (((d.l(anc:(iobase()+0x11b00+0x40))&0xf000000)==(0x04000000||0x5000000||0x6000000||0xc000000||0xd000000||0xe000000))&&((d.l(ANC:iobase()+0xf04)&(0x08000000>>11.))!=0)) hgroup.byte (0x11b00+0x38)++0x00 hide.byte 0x00 "OP1,Output Port 1 Bit Set Channel 11" hgroup.byte (0x11b00+0x3c)++0x00 hide.byte 0x00 "OP0,Output Port 0 Bit Set Channel 11" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif width 0xb tree.end tree.end tree "RTC (Real Time Clock IMMRBAR + 0x0a00)" width 0x6 group.long 0x0a00++0x0f line.long 0x00 "TSET,RTC Time Set Register" bitfld.long 0x00 25. " SET_TIME ,New time to be programmed into the RTC" "Not set,Set" bitfld.long 0x00 24. " PAUSE_TIME ,Perform time update" "Normal,Updated" textline " " bitfld.long 0x00 21. " SlctHour ,Hour output format" "24-hour,12-hour" bitfld.long 0x00 16.--20. " C24Hour_set ,Hour in 24-hour format written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 8.--13. " Minute_set ,Minute written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" bitfld.long 0x00 0.--5. " Second_set ,Second written in RTC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" line.long 0x04 "DSET,RTC Date Set Register" bitfld.long 0x04 25. " SET_DATE ,New date to be programmed into the RTC" "Not set,Set" bitfld.long 0x04 24. " PAUSE_DATE ,Perform date update" "Normal,Update" textline " " bitfld.long 0x04 16.--20. " MONTH_SET ,New month written in RTC" "-,Jan,Febr,Mar,Apr,May,June,July,Aug,Sept,Oct,Nov,Dec,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x04 8.--13. " WEEKDAY_SET ,New weekday written in RTC" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x04 0.--5. " DATE_SET ,New date written in RTC" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" line.long 0x08 "NYSW,RTC New Year and Stopwatch Register" bitfld.long 0x08 24. " write_SW ,Stopwatch minute countdown begin" "Stopped,Started" hexmask.long.word 0x08 16.--26. 1. " SW_set ,Number of minutes to be written into stopwatch, max is 255" textline " " hexmask.long.word 0x08 0.--11. 1. " Year_set ,New year written in RTC after successful state machine transition by set_date and pause_date bits" line.long 0x0c "ALIE,RTC Alarm and Interrupt Enable Register" bitfld.long 0x0c 24. " Alm_enable ,Alarm Enable bit for once-a-day Alarm" "Disabled,Enabled" bitfld.long 0x0c 16.--20. " Alm_24Hset ,Hour setting (in 24 hour format)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x0c 8.--13. " Alm_Min_set ,Minute setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" bitfld.long 0x0c 3. " MPE ,Master Periodic Enable" "Enabled,Disabled" textline " " bitfld.long 0x0c 2. " IntEn_day ,Enable bit of periodic interrupts at midnight rollover" "Disabled,Enabled" bitfld.long 0x0c 1. " IntEn_min ,Enable bit of periodic interrupts at minute rollover" "Disabled,Enabled" textline " " bitfld.long 0x0c 0. " IntEn_sec ,Enable bit of periodic interrupts at second rollover" "Disabled,Enabled" if ((d.l(anc:iobase()+0xa00)&0x200000)==0x000000) rgroup.long 0xa10++0x03 line.long 0x0 "CTIM,RTC Current Time Register" bitfld.long 0x0 16.--20. " Hour ,Current time in 24-hour format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" bitfld.long 0x0 8.--13. " Minute ,Shows minutes in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" textline " " bitfld.long 0x0 0.--5. " Second ,Shows seconds in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" else rgroup.long 0xa10++0x03 line.long 0x0 "CTIM,RTC Current Time Register" bitfld.long 0x0 20. " Hour[0] ,AM/PM" "AM,PM" bitfld.long 0x0 16.--19. " Hour[1:4] ,Current time in 12-hour format" "0,1,2,3,4,5,6,7,8,9,10,11,12,-,-,-" textline " " bitfld.long 0x0 8.--13. " Minute ,Shows minutes in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" bitfld.long 0x0 0.--5. " Second ,Shows seconds in current time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" endif rgroup.long 0xa14++0x03 line.long 0x00 "CDR,RTC Current Date Register" bitfld.long 0x00 24.--27. " Month ,Shows current month" "-,Jan,Febr,Mar,Apr,May,June,July,Aug,Sept,Oct,Nov,Dec,-,-,-" bitfld.long 0x00 21.--23. " Weekday ,Indicates day of week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x00 16.--20. " Day ,Shows current date" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. " Year ,Shows current year, max is 4052" group.long 0xa18++0x0b line.long 0x0 "ALSI,RTC Alarm and Stopwatch Interrupt Register" eventfld.long 0x0 24. " Int_alm ,Enabled once-a-day Alarm has occurred" "Not occurred,Occurred" eventfld.long 0x0 16. " Int_SW ,Stopwatch expiration has occurred" "Not occurred,Occurred" textline " " eventfld.long 0x0 8. " Alm_status ,Once-a-day Alarm has occurred" "Not occurred,Occurred" hexmask.long.byte 0x0 0.--7. 1. " SW_min ,Minutes remaining in stopwatch" line.long 0x04 "PIBE,RTC Periodic Interrupt and Bus Error Register" eventfld.long 0x04 24. " Bus_error_1 ,Internal status register" "No error,Error" eventfld.long 0x04 16. " Int_day ,Periodic interrupt at midnight" "Not occurred,Occurred" textline " " eventfld.long 0x04 8. " Int_min ,Periodic interrupt at each minute rollover" "Not occurred,Occurred" eventfld.long 0x04 0. " Int_sec ,Periodic interrupt at each second rollover" "Not occurred,Occurred" line.long 0x08 "TTR,RTC Target Time Register" rgroup.long 0xa24++0x03 line.long 0x00 "ATC,RTC Actual Time Counter Register" group.long 0xa28++0x03 line.long 0x00 "KA,RTC Keep Alive Register" bitfld.long 0x00 29. " BC_7 ,Breadcrumb bit 7" "0,1" bitfld.long 0x00 28. " WU_SRC_1_EN ,Determines the Modes of the BC_0 / WU_SRC_1 bit" "Breadcrumb,Wakeup source" textline " " bitfld.long 0x00 27. " WU_SRC_2_EN ,Determines the Modes of the BC_1 / WU_SRC_2_bit" "Breadcrumb,Wakeup source" bitfld.long 0x00 26. " WU_SRC_3_EN ,Determines the Modes of the BC_2 / WU_SRC_3_bit" "Breadcrumb,Wakeup source" textline " " bitfld.long 0x00 25. " WU_SRC_4_EN ,Determines the Modes of the BC_3 / WU_SRC_4_bit" "Breadcrumb,Wakeup source" bitfld.long 0x00 24. " WU_SRC_5_EN ,Determines the Modes of the BC_4 / WU_SRC_5_bit" "Breadcrumb,Wakeup source" textline " " bitfld.long 0x00 21. " BC_8 ,Breadcrumb bit 8" "0,1" bitfld.long 0x00 20. " WU_SRC_1_LVL ,Program the Wakeup Source SET_WU_SRC[1]" "Low,High" textline " " bitfld.long 0x00 19. " WU_SRC_2_LVL ,Program the Wakeup Source SET_WU_SRC[2]" "Low,High" bitfld.long 0x00 18. " WU_SRC_3_LVL ,Program the Wakeup Source SET_WU_SRC[3]" "Low,High" textline " " bitfld.long 0x00 17. " WU_SRC_4_LVL ,Program the Wakeup Source SET_WU_SRC[4]" "Low,High" bitfld.long 0x00 16. " WU_SRC_5_LVL ,Program the Wakeup Source SET_WU_SRC[5]" "Low,High" textline " " eventfld.long 0x00 15. " WU_SRC_0 ,Wakeup Source" "Low,High" eventfld.long 0x00 14. " BC_0 ,Breadcrumb or Wakeup Source" "0,1" textline " " eventfld.long 0x00 13. " BC_1 ,Breadcrumb or Wakeup Source" "0,1" eventfld.long 0x00 12. " BC_2 ,Breadcrumb or Wakeup Source" "0,1" textline " " eventfld.long 0x00 11. " BC_3 ,Breadcrumb or Wakeup Source" "0,1" eventfld.long 0x00 10. " BC_4 ,Breadcrumb or Wakeup Source" "0,1" textline " " bitfld.long 0x00 9. " BC_5 ,Breadcrumb bit 5" "0,1" bitfld.long 0x00 8. " BC_6 ,Breadcrumb bit 6" "0,1" textline " " bitfld.long 0x00 7. " DIS_HIB_MODE ,HIB_MODE Output Pin Disable" "Enabled,Disabled" eventfld.long 0x00 2. " WU_SRC_MODE ,Proceeding SET_WU_SRC Signals Inhibition" "Not inhibited,Inhibited" textline " " eventfld.long 0x00 1. " TAMP ,TAMP Reset/Oscillator Status" "No reset/Running,Reset/Stopped" bitfld.long 0x00 0. " TTR_CMP ,Value of the TTR Compared to the ATC" "No reset,Reset" width 0xb tree.end tree "SATA (SATA Controller IMMRBAR + 0x20000)" width 0x14 tree "ATA Taskfile and Control Registers" group.long 0x20000++0x1f line.long 0x00 "DATA,Data port register" line.long 0x04 "Error_Features,Features/Error register" line.long 0x08 "ESector_Count,Sector count register" line.long 0x0c "Sector_Number,Sector number register" line.long 0x10 "Cylinder_Low,Cylinder low register" line.long 0x14 "Cylinder_High,Cylinder high register" line.long 0x18 "Device_Head,Device/Head register" line.long 0x1c "Status_Command,Status/Command register" group.long 0x20048++0x03 line.long 0x00 "Altstat_Devctrl,Alternate status/device control" tree.end width 0x7 tree "SATA Status and Control Registers" rgroup.long 0x20100++0x03 line.long 0x00 "SSR,SStatus Register" bitfld.long 0x00 8.--11. " IPM ,Current Interface Power Management State" "Not present,Active,PARTIAL,Reserved,Reserved,Reserved,SLUMBER,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 4.--7. " SPD ,Negotiated Interface Communication Speed" "No negotiated speed,1 communication rate,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 0.--3. " DET ,The Interface Device Detection and Phy State" "Not detected/not established,Detected/not established,Reserved,Detected/Established,Offline mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" group.long 0x20104++0x07 line.long 0x00 "SER,SError Register" bitfld.long 0x00 25. " F ,Unrecognized FIS type" "Not occurred,Occurred" bitfld.long 0x00 24. " T ,Transport State Transition Error" "No error,Error" textline " " bitfld.long 0x00 23. " S ,Link Sequence Error" "No error,Error" bitfld.long 0x00 22. " H ,Handshake Error" "No error,Error" textline " " bitfld.long 0x00 21. " C ,CRC Error" "No error,Error" bitfld.long 0x00 20. " D ,Disparity Error" "No error,Error" textline " " bitfld.long 0x00 19. " B ,10b to 8b Decode Error" "No error,Error" bitfld.long 0x00 18. " W ,Comm Wake" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I ,Phy Internal Error" "No error,Error" bitfld.long 0x00 16. " N ,PhyRdy Change" "Not changed,Changed" textline " " bitfld.long 0x00 11. " E ,Internal Error" "No error,Error" bitfld.long 0x00 10. " P ,Protocol Error" "No error,Error" textline " " bitfld.long 0x00 9. " C ,Non-Recovered Persistent Communication or Data Integrity Error" "No error,Error" bitfld.long 0x00 8. " T ,Non-Recovered Transient Data Integrity Error" "No error,Error" textline " " bitfld.long 0x00 1. " M ,Recovered Communications Error" "No error,Error" bitfld.long 0x00 0. " I ,Recovered Data Integrity Error" "No error,Error" line.long 0x04 "SCR,SControl Register" bitfld.long 0x04 8.--11. " IPM ,Interface Power Management States Enable" "No interface,PARTIAL,SLUMBER,Both,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x04 4.--7. " SPD ,The Highest Allowed Communication Speed" "No restrictions,>=1 communication rate,Reserved,Reserved,,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x04 0.--3. " DET ,Host Adapter Device Detection and Interface Initialization Control" "Not detected/not requested,Established,Reserved,Reserved,SATA Disabled/Offline mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" tree.end width 0x7 tree "Special Registers" group.long 0x20140++0x03 line.long 0x00 "TRC,Trans_cfg Register" bitfld.long 0x00 7.--9. " TX_WATERMARK ,Number of Locations in the Eight Deep TX FIFO" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 1.--6. 1. " RX_WATERMARK ,Number of Locations in the 48 Deep RX FIFO" textline " " bitfld.long 0x00 0. " BE ,Entry to Bist Mode Enable" "Disabled,Enabled" rgroup.long 0x20144++0x03 line.long 0x00 "TRST0,Trans_status0 Register" bitfld.long 0x00 26. " SRST_CLEARED ,SRST bit Clear" "Not cleared,Cleared" bitfld.long 0x00 25. " SRST_SET ,SRST bit Set" "Not set,Set" textline " " bitfld.long 0x00 24. " TRANSMIT_CRF ,Frame Control Transmition" "Not occurred,Occurred" bitfld.long 0x00 20.--23. " SEND_FIS_SM ,Send FIS State Machine." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 17.--19. " GET_FIS_SM ,Get FIS State Machine." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " RX_FIFO_EMPTY ,The receive FIFO State" "Not empty,Empty" textline " " bitfld.long 0x00 15. " TRANS_READY ,Transport Layer Ready" "Not ready,Ready" hexmask.long.byte 0x00 7.--14. 1. " R_STATUS ,Transport Layer Status Taskfile" textline " " bitfld.long 0x00 6. " LAST_FIS_EQ_PSUW ,Last FIS Was PIO SU Write" "Not occurred,Occurred" bitfld.long 0x00 5. " LAST_FIS_EQ_PSUR ,Last FIS Was PIO SU Read" "Not occurred,Occurred" textline " " hexmask.long.byte 0x00 0.--4. 1. " TRANS_STATE ,Transport Layer Main State Machine" group.long 0x20148++0x0b line.long 0x00 "LKC0,Link_cfg0 Register" bitfld.long 0x00 30. " CFG_EN_PART ,Partial Power Management Mode Enable" "Disabled,Enabled" bitfld.long 0x00 29. " CFG_LINK_WAKEUP ,Link Layer From Partial/slumber Power Management Mode Wake Up " "No wakeup,Wakeup" textline " " bitfld.long 0x00 28. " CFG_LK_GO_SLUM ,Link Layer Far End to Enter Slumber Power Management Mode Request" "Not requested,Requested" bitfld.long 0x00 27. " CFG_LK_GO_PART ,Link Layer Far End to Enter Partial Power Management Mode Request" "Not requested,Requested" textline " " bitfld.long 0x00 26. " CFG_PRIM_OVR_EN ,Primitive Override Enable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " CFG_PHY_RDY_TIM ,Timeout Value of the PHY_READY Timer" textline " " hexmask.long.byte 0x00 8.--15. 1. " CFG_ALI_RATE ,CFG_ALIGN_RATE Setting" bitfld.long 0x00 7. " CFG_EN_PHY_TO ,Link Layer Re-issue a PHY_RESET Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CFG_SEND_4_ALI ,Four ALIGN Primitives Transmitted at the Specified Rate" "Not asserted,Asserted" bitfld.long 0x00 5. " CFG_EN_SLUMBER ,Slumber Power Management Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " CFG_RX_SCRBL ,De-scrambling of the Receive Data Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CFG_TX_SCRAMBLE ,Scrambling of the Transmit Data Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CFG_TXPRM_JK ,Scrambled Junk Data is Sent After a CONT Primitive" "Sent,Not sent" bitfld.long 0x00 1. " CFG_TX_CONT ,Transmission of CONT Primitives Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CFG_TX_BADCRC ,A bad CRC Value Transmission " "Not occurred,Occurred" line.long 0x04 "LKC1,Link_cfg1 Register" bitfld.long 0x04 7. " CFG_RX_BADCRC ,Bad CRC Detection" "Not detected,Detected" bitfld.long 0x04 6. " CFG_CD ,Data Type" "Character,Primitive" textline " " hexmask.long.byte 0x04 0.--5. 1. " CFG_PRM_OVR_STA ,Used in the Primitive Override Debug Functionality" line.long 0x08 "LKC2,Link_cfg2 Register" rgroup.long 0x20154++0x0f line.long 0x00 "LKS0,Link_status0 Register" bitfld.long 0x00 2.--7. " LAT_LINK_STATE ,Current Value of the Link Layer State Machine" "L_Reset,L_Idle,HL_SendChkRdy,DL_SendChkRdy,L_TPMPartial,L_TPMSlumber,L_RcvWaitFifo,L_PMOff,L_PMDeny,L_NoCommErr,L_NoComm,L_SendAlign,L_SendSOF,L_SendData,WAIT_FOR_SYNC,L_SendCRC,L_SendHold,L_RcvHold,L_SendEOF,L_Wait,L_ChkPhyRdy,L_NoCommPower,L_WakeUp1,L_WakeUp2,L_RcvChkRdy,L_RcvData,L_BadEnd,L_RcvEOF,L_SendHoldA,L_Hold,L_GoodCRC,L_GoodEnd,L_PMOff_2,L_PMOff_3,L_PMOff_4,WAIT_PMACK_SENT_1,WAIT_PMACK_SENT_2,WAIT_PMACK_SENT_3,WAIT_PMACK_SENT_4,WAIT_PMACK_SENT_5,WAIT_PMACK_SENT_6,BIST0,BIST1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" line.long 0x04 "LKS1,Link_status1 Register" hexmask.long.byte 0x04 24.--31. 1. " KCHAR_ERR_COUNT ,The number of doublewords that have been received from the PHY" hexmask.long.byte 0x04 16.--23. 1. " INT_ERR_COUNT ,The number of doublewords that have been received from the PHY" textline " " hexmask.long.byte 0x04 8.--15. 1. " CODE_ERR_COUNT ,The number of doublewords that have been received from the PHY" hexmask.long.byte 0x04 0.--7. 1. " DISP_ERR_COUNT ,The number of doublewords that have been received from the PHY" group.long 0x20174++0x03 line.long 0x00 "PHC,Phy_cfg Register" bitfld.long 0x00 15.--17. " CFG_TX_PRE_EM_CTRL ,Drives TxPreEmCtrl of Phy when prot2PhyTstEnL equals 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11.--14. " CFG_TX_AMP_CTRL ,Drives TxAmpCtrl of Phy when prot2PhyTstEnL equals 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10. " CFG_ENDEC ,Drives enDec of PCS when prot2PhyTstEnL equals 0" "Not driven,Driven" bitfld.long 0x00 9. " CFG_RX_SSC_MODE ,Drives RxSSCMode of Phy when prot2PhyTstEnL equals 0" "Not driven,Driven" textline " " bitfld.long 0x00 6.--8. " CFG_TX_SSC_MODE ,Drives TxSSCMode of PCS when prot2PhyTstEnL equals 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5. " CFG_FRC_PHYRDY ,Drives frcPhyRdy of PCS when prot2PhyTstEnL equals 0" "Not driven,Driven" textline " " bitfld.long 0x00 4. " CFG_RXREFMODE ,Drives rxRefMode of PCS when prot2PhyTstEnL equals 0" "Not driven,Driven" bitfld.long 0x00 3. " ENLWALIGN ,Enable Longword Alignment" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " CFG_LBEN ,Drives lbEn of PCS when prot2PhyTstEnL equals 0" "0,1,2,3" bitfld.long 0x00 0. " CFG_BIST ,Drives bist of PCS when prot2PhyTstEnL equals 0" "Not driven,Driven" rgroup.long 0x20178++0x03 line.long 0x00 "TS1,Trans_status1 Register" bitfld.long 0x00 17. " RX_FIFO_OVERFLOW ,FIFO Overflow" "No overflow,Overflow" bitfld.long 0x00 16. " TX_FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" textline " " hexmask.long.word 0x00 0.--15. 1. " CUR_TRANS_VALUE ,Current value of transfer count" group.long 0x2017c++0x23 line.long 0x00 "TxBD0,Tx_bist_dat0 Register" line.long 0x04 "BD0S,Bist_dat0_sel Register" bitfld.long 0x04 0. " S ,TX_BIST_DAT0 Type" "Data,Primitive" line.long 0x08 "TXD1,Tx_bist_dat1 Register" line.long 0x0c "BD1S,Bist_dat1_sel Register" bitfld.long 0x0c 0. " S ,TX_BIST_DAT1 Type" "Data,Primitive" line.long 0x10 "TXBM,Tx_bist_mode Register" bitfld.long 0x10 7. " T ,Far end transmit only mode" "Not occurred,Occurred" bitfld.long 0x10 6. " A ,ALIGN Bypass" "No bypass,Bypass" textline " " bitfld.long 0x10 5. " S ,Bypass Scrambling" "No bypass,Bypass" bitfld.long 0x10 4. " L ,Far end Retimed Loopback" "No Loopback,Loopback" textline " " bitfld.long 0x10 3. " F ,Far end Analog Loopback" "No Loopback,Loopback" bitfld.long 0x10 2. " P ,Primitive bit" "Not occurred,Occurred" textline " " bitfld.long 0x10 0. " V ,Vendor unique Test Mode" "Normal,Test mode" line.long 0x14 "BW,Bist_written Register" bitfld.long 0x14 0. " BW ,Host Initiated BIST Trigger" "Not triggered,Triggered" line.long 0x18 "BS,Bist_status Register" bitfld.long 0x18 1. " BE ,BIST Error" "No error,Error" bitfld.long 0x18 0. " BA ,Bist Active" "Inactive,Active" line.long 0x1c "TXSD,Tx_send_dmat Register" bitfld.long 0x1c 0. " SD ,Asks Link Layer to Send a DMAT Primitive When This Bit is Set to One" "Not sent,Sent" line.long 0x20 "AE,Atapi_en Register" bitfld.long 0x20 0. " AE ,ATAPI Mode Enable" "Disabled,Enabled" tree.end width 0x7 tree "Additional Registers" group.long 0x201c0++0x03 line.long 0x00 "RCC,rxCdrCtrl Register" rgroup.long 0x201c4++0x03 line.long 0x00 "RCS,rxCdrStat Register" group.long 0x201c8++0x0b line.long 0x00 "RC,rxCtrl Register" line.long 0x04 "TC,txCtrl Register" line.long 0x08 "VLC,vregLvlCtrl Register" group.long 0x201d4++0x03 line.long 0x00 "PMC,PMCtrl Register" bitfld.long 0x00 7. " LBENASEL ,Drive output lbEnA to Phy Selection" "lbEnA,lbEnA_fsl" bitfld.long 0x00 4.--6. " LBENA_FSL ,Provides additional working mode for Freescale SATA Phy" "lbEnA,lbEnA,lbEnA,Disabled digital reset,Far-end analog loopback,goParallel,goSlumber,Invalid" textline " " bitfld.long 0x00 3. " SATA_CTL_EN ,This bit is sata controller enable" "Disabled,Enabled" bitfld.long 0x00 2. " SATA_PCS_EN ,This bit is sata pcs enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PHY_ENABLE ,SATA Phy Enable" "Disabled,Enabled" rgroup.long 0x201d8++0x03 line.long 0x00 "PMS,PMStat Register" bitfld.long 0x00 2. " RXLOCKONCEDET ,Receiver PLL lock once detect" "Not detected,Detected" bitfld.long 0x00 1. " TXLOCKONCEDET ,Transmitter PLL lock once detect" "Not detected,Detected" group.long 0x201e0++0x07 line.long 0x00 "DE,DmaEndian Register" bitfld.long 0x00 0. " DMA_ENDIAN ,DMA Interface Type" "Big-endian,Little-endian" tree.end tree "DMA Registers" ;no description for STALLINT, STALLINT_EN bits group.long 0x21080++0x03 line.long 0x00 "DSC,Dma_stat_ctrl Register" bitfld.long 0x00 28.--30. " RDPNTRA ,Read pointer for FIFO A" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " RDPNTRB ,Read pointer for FIFO B" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 22.--24. " WRPNTRA ,Write pointer for FIFO A" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " WRPNTRB ,Write pointer for FIFO B" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 17.--18. " BUFSTAT ,DMA Buffer Status" "Disabled,Stalled,On progress,Reserved" bitfld.long 0x00 16. " STALINT ,DMA Stall Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " STALINTEN ,DMA Stall Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DISKREAD ,Disk Read/Write Operation" "Write,Read" textline " " bitfld.long 0x00 0. " DMAEN ,DMA Enable" "Disabled,Enabled" rgroup.long 0x21084++0x03 line.long 0x00 "DRA,Dma_remain_ahb Register" group.long 0x21088++0x07 line.long 0x00 "DMC,Dma_max_cnt Register" hexmask.long 0x00 0.--24. 1. " DMA_MAX_CNT ,Maximum Size For DMA Transferring" line.long 0x04 "DS,Dma_start Register" rgroup.long 0x21090++0x07 line.long 0x00 "DC,Dma_current Register" line.long 0x04 "DRT,Dma_remain_tc Register" tree.end tree.end tree "SDHC (Secure Digital Host Controller IMMRBAR + 0x1500)" width 0xe group.long 0x1500++0x1f line.long 0x00 "STR_STP_CLK,SDHC Clock Control Register" bitfld.long 0x00 3. " SDHC_RESET ,SDHC Reset" "No effect,Reset" bitfld.long 0x00 1. " START_CLK ,Start MMC_SD_CLK Clock" "No effect,Started" textline " " bitfld.long 0x00 0. " STOP_CLK ,Stop MMC_SD_CLK Clock" "No effect,Stopped" line.long 0x04 "STATUS,SDHC Status Register" eventfld.long 0x04 31. " CARD_INSERTION ,Card Insertion" "Not detected,Detected" eventfld.long 0x04 30. " CARD_REMOVAL ,Card Removal" "Not detected,Detected" textline " " bitfld.long 0x04 29. " YBUF_EMPTY ,Y Data Buffer Empty" "Not empty,Empty" bitfld.long 0x04 28. " XBUF_EMPTY ,X Data Buffer Empty" "Not empty,Empty" textline " " bitfld.long 0x04 27. " YBUF_FULL ,Y Data Buffer Full" "Not full,Full" bitfld.long 0x04 26. " XBUF_FULL ,X Data Buffer Full" "Not full,Full" textline " " bitfld.long 0x04 25. " BUF_UND_RUN ,Buffer Underrun" "Not occurred,Occurred" bitfld.long 0x04 24. " BUF_OVFL ,Buffer Overflow" "Not occurred,Occurred" textline " " eventfld.long 0x04 14. " SDIO_INT_ACTIVE ,SDIO Interrupt Active" "Not detected,Detected" eventfld.long 0x04 13. " END_CMD_RESP ,End Command Response" "No response,Response" textline " " eventfld.long 0x04 12. " WRITE_OP_DONE ,Write Operation Done" "Incomplete,Complete" eventfld.long 0x04 11. " READ_OP_DONE ,Read Operation Done" "Incomplete,Complete" textline " " bitfld.long 0x04 9.--10. " WR_CRC_ERROR_CODE ,Write CRC Error Code" "No error,Error,No Response,Reserved" bitfld.long 0x04 8. " CARD_BUS_CLK_RUN ,Card Bus Clock Run" "Stopped,Running" textline " " bitfld.long 0x04 7. " BUF_READ_READY ,Buffer Read Ready" "Not ready,Ready" bitfld.long 0x04 6. " BUF_WRITE_READY ,Buffer Write Ready" "Not ready,Ready" textline " " eventfld.long 0x04 5. " RESP_CRC_ERR ,Response CRC Error" "No error,Error" eventfld.long 0x04 3. " READ_CRC_ERR ,Read CRC Error" "No error,Error" textline " " eventfld.long 0x04 2. " WRITE_CRC_ERR ,Write CRC Error" "No error,Error" eventfld.long 0x04 1. " TIME_OUT_RESP ,Time Out Response" "No error,Error" textline " " eventfld.long 0x04 0. " TIME_OUT_READ ,Time Out Read" "No error,Error" line.long 0x08 "CLK_RATE,SDHC Clock Rate Register" hexmask.long.word 0x08 4.--15. 1. " CLK_PRESCALER ,Clock Prescaler" bitfld.long 0x08 0.--3. " CLK_DIVIDER ,Clock Divider" "SDHC_CLK,SDHC_CLK/2,SDHC_CLK/3,SDHC_CLK/4,SDHC_CLK/5,SDHC_CLK/6,SDHC_CLK/7,SDHC_CLK/8,SDHC_CLK/9,SDHC_CLK/10,SDHC_CLK/11,SDHC_CLK/12,SDHC_CLK/13,SDHC_CLK/14,SDHC_CLK/15,SDHC_CLK/16" line.long 0x0c "CMD_DAT_CONT,SDHC Command and Data Control Register" bitfld.long 0x0c 15. " CMD_RESUME ,Command Resume" "Issued,Not issued" bitfld.long 0x0c 12. " CMD_RESP_LONG_OFF ,Command Response Long Off" "Not cleared,Cleared" textline " " bitfld.long 0x0c 11. " STOP_READWAIT ,Stop Read/Wait" "No offect,Stopped" bitfld.long 0x0c 10. " START_READWAIT ,Start Read/Wait" "No effect,Started" textline " " bitfld.long 0x0c 8.--9. " BUS_WIDTH ,Bus Width" "1-bit,Reserved,4-bit,Reserved" bitfld.long 0x0c 7. " INIT ,Initialize" "Disabled,Enabled" textline " " bitfld.long 0x0c 4. " WRITE_READ ,Write/Read" "Read,Write" bitfld.long 0x0c 3. " DATA_ENABLE ,Data Transfer Enable" "Not included,Included" textline " " bitfld.long 0x0c 0.--2. " FORMAT_OF_RESPONSE ," "No response,Format R1/R5/R6,Format R2,Format R3/R4,Reserved,Reserved,Reserved,Reserved" line.long 0x10 "RES_TO,SDHC Response Time Out Register" hexmask.long.byte 0x10 0.--7. 1. " RESPONSE_TIME_OUT ,Response Timeout" line.long 0x14 "READ_TO,SDHC Read Time Out Register" hexmask.long.word 0x14 0.--15. 1. " DATA_READ_TIME_OUT ,Data Read Timeout" line.long 0x18 "BLK_LEN,SDHC Block Length Register" hexmask.long.word 0x18 0.--11. 1. " BLOCK_LENGTH ,Block Length" line.long 0x1c "NOB,SDHC Number of Blocks Register" hexmask.long.word 0x1c 0.--15. 1. " NOB ,Number of Blocks in a Block Transfer" rgroup.long 0x1520++0x03 line.long 0x00 "REV_NO,SDHC Revision Number Register" hexmask.long.word 0x00 0.--15. 1. " Rev_Numb[15:0] ,Revision Number of MMC/SD Module" group.long 0x1524++0x0b line.long 0x00 "INT_CNTR,SDHC Interrupt Control Register" bitfld.long 0x00 15. " CARD_INSERTION_EN ,Card Insertion Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " CARD_REMOVAL_EN ,Card Removal Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SDIO_IRQ_EN ,SDIO Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. " DAT0_EN ,Data Enable" "SD_DAT[3:0] = b110x,SD_DAT[3:0] = b1101" textline " " bitfld.long 0x00 4. " BUF_READ_EN ,Bus Read Enable" "Disabled,Enabled" bitfld.long 0x00 3. " BUF_WRITE_EN ,Bus Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " END_CMD_RES ,End Command Response Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " WRITE_OP_DONE ,Write Operation Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " READ_OP_DONE ,Read Operation Done Interrupt Enable" "Disabled,Enabled" line.long 0x04 "CMD,SDHC Command Number Register" bitfld.long 0x04 0.--5. " COMMAND_NUMBER ,Command Number" "CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CMD8,CMD9,CMD10,CMD11,CMD12,CMD13,CMD14,CMD15,CMD16,CMD17,CMD18,CMD19,CMD20,CMD21,CMD22,CMD23,CMD24,CMD25,CMD26,CMD27,CMD28,CMD29,CMD30,CMD31,CMD32,CMD33,CMD34,CMD35,CMD36,CMD37,CMD38,CMD39,CMD40,CMD41,CMD42,CMD43,CMD44,CMD45,CMD46,CMD47,CMD48,CMD49,CMD50,CMD51,CMD52,CMD53,CMD54,CMD55,CMD56,CMD57,CMD58,CMD59,CMD60,CMD61,CMD62,CMD63" line.long 0x08 "ARG,SDHC CMD Argument Register" hgroup.long 0x1534++0x03 hide.long 0x00 "RES_FIFO,SDHC Response FIFO Access Register" in hgroup.long 0x1538++0x03 hide.long 0x00 "BUFFER_ACCESS,SDHC Data Buffer Access Register" in tree.end tree "WDT (Software Watchdog Timer IMMRBAR + 0x900)" width 0x7 group.long 0x904++0x03 line.long 0x00 "SWCRR,System Watchdog Control Register" hexmask.long.byte 0x00 16.--31. 1. " SWTC ,Software Watchdog Time Count" bitfld.long 0x00 2. " SWEN ,Watchdog Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SWRI ,Software Watchdog Reset/Interrupt Select" "Interrupt,Reset" bitfld.long 0x00 0. " SWPR ,Software Watchdog Counter Prescale" "Not prescaled,Prescaled" rgroup.long 0x908++0x03 line.long 0x00 "SWCNR,System Watchdog Count Register" hexmask.long.word 0x00 0.--15. 1. " SWCN ,Software Watchdog Count" wgroup.word 0x90e++0x01 line.word 0x00 "SWSRR,System Watchdog Service Register" tree.end tree "SPDIF (Sony/Philips Digital Interface IMMRBAR + 0x1600)" width 0xa if (data.long(ANC:iobase()+0xf08)&0x00800000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x1600++0x0b line.long 0x00 "SCR,EBU_Config Register" bitfld.long 0x00 31. " RCVFIFO_CTRL ,RCV FIFO Control" "Normal,Read 0" bitfld.long 0x00 30. " RCVFIFO_OFF/ON ,RCV FIFO Status" "On,Off" textline " " bitfld.long 0x00 29. " RCVFIFO_RST ,RCV FIFO Reset" "No reset,Reset" bitfld.long 0x00 27.--28. " RCVFIFOFULL_SEL ,RCV FIFO Full Select" "1 sample,4 sample,8 sample,12 sample" textline " " bitfld.long 0x00 26. " RCVAUTOSYNC ,RCV FIFO Auto Sync Enable" "Off,On" bitfld.long 0x00 25. " TXAUTOSYNC ,Tx FIFO Auto Sync Enable" "Off,On" textline " " bitfld.long 0x00 23.--24. " TXFIFOEMPTY_SEL ,Tx FIFO Empty Select" "Tx FIFO empty,<= 4 sample,<= 8 sample,Tx FIFO empty" bitfld.long 0x00 18.--19. " TXFIFO_CTRL ,Tx FIFO Control" "0 on SPIDF Tx,Normal,Reset to 1 sample,Reserved" textline " " bitfld.long 0x00 17. " PDIR_RCV ,PDIR RCV Full Request" "Not sent,Sent" bitfld.long 0x00 16. " PDIR_TX ,Transmit FIFO Empty Request" "Not sent,Sent" textline " " bitfld.long 0x00 13. " VALCTRL ,Outgoing Validity Control" "Set,Cleared" bitfld.long 0x00 10.--12. " TXSEL ,Tx Select" "Off/output 0,Feed-through,Reserved,Reserved,Reserved,Normal,Reserved..." textline " " bitfld.long 0x00 8.--9. " USRC_SEL ,U Channel Source Select" "No embeded,SPDIF receive block,Reserved,On-chip transmitter" line.long 0x04 "SRCD,CDText Control Register" bitfld.long 0x04 23. " PRSETEN ,Free-running Sync Position Counter Status" "No action,Present" hexmask.long.byte 0x04 16.--22. 1. " PRSETCOUNT ,Presetting Count For Sync Position" textline " " bitfld.long 0x04 9. " USYNCMODE ,Usync Mode" "Non-CD data,CD user channel subcode" bitfld.long 0x04 8. " UCHANTXTIM ,U Channel Tx Timing" "Reserved,To register" line.long 0x08 "SRPC,PhaseConfig Register" bitfld.long 0x08 14. " LOCK ,Internal DPLL Lock" "Not Locked,Locked" bitfld.long 0x08 11.--13. " COEFSEL ,Coef Selection" "24,16,12,8,6,4,3,3" textline " " bitfld.long 0x08 8.--10. " CLKSRC_SEL ,Clock Source Selection" "SPDIF_RCVCLK/STClk,Reserved,Reserved,STClk,Reserved,Reserved,Reserved,Reserved" textline "" textline "" rgroup.long 0x162c++0x03 line.long 0x00 "SRFM,FreqMeas Register" hexmask.long 0x00 8.--31. 1. " FREQMEAS ,A ratio of measured clock freqency to reference clock frequency" group.long 0x1650++0x03 line.long 0x00 "STC,Transmit Clock Control Register" bitfld.long 0x00 16.--17. " TXCLK_SEL ,Tx Clock Selection" "STClk,Reserved,Reserved,Reserved" bitfld.long 0x00 8.--11. " TXCLK_DF ,Divider Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif tree "Interrupt Registers" if (data.long(ANC:iobase()+0xf08)&0x00800000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long 0x160c++0x03 line.long 0x00 "SIE,InterruptEn Register" bitfld.long 0x00 27. " TXUNOV ,SPDIF transmit fifo under/overrun Enable" "Disabled,Enabled" bitfld.long 0x00 26. " TXRESYN ,SPDIF transmit fifo resync Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CNEW ,SPDIF receive change in value of control channel Enable" "Disabled,Enabled" bitfld.long 0x00 24. " VALNOGOOD ,SPDIF validity flag no good Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SYMERR ,SPDIF receiver found illegal symbol Enable" "Disabled,Enabled" bitfld.long 0x00 22. " BITERR ,SPDIF receiver found parity bit error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " UTXEM ,UChannel transmit register empty Enable" "Disabled,Enabled" bitfld.long 0x00 20. " UTXUNDER ,UChannel transmit register underrun Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " UTX_NEXTFIRST ,UChannel transmit register next byte is first Enable" "Disabled,Enabled" bitfld.long 0x00 18. " URXFUL ,UChannel receive register full Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " URXOV ,UChannel receive register overrun Enable" "Disabled,Enabled" bitfld.long 0x00 16. " QRXFUL ,QChannel receive register full Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " QRXOV ,QChannel receive register overrun Enable" "Disabled,Enabled" bitfld.long 0x00 14. " UQSYNC ,U/Q Channel sync found Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " UQERR ,UQERR U/Q Channel framing error Enable" "Disabled,Enabled" bitfld.long 0x00 12. " PDIRUNOV ,Processor data input underrun/overrun Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PDIRRESYN ,Processor data input resync Enable" "Disabled,Enabled" bitfld.long 0x00 10. " LOCKLOSS ,SPDIF receiver loss of lock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " TXEM ,SPDIF Transmit FIFO emcpty Enable" "Disabled,Enabled" bitfld.long 0x00 8. " PDIRFUL ,PDIRFUL Processor Data Input Full Enable" "Disabled,Enabled" rgroup.long 0x1618++0x03 line.long 0x00 "SIS,InterruptStat Register" bitfld.long 0x00 27. " TXUNOV ,SPDIF transmit fifo under/overrun Status" "No interrupt,Interrupt" bitfld.long 0x00 26. " TXRESYN ,SPDIF transmit fifo resync Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " CNEW ,SPDIF receive change in value of control channel Status" "No interrupt,Interrupt" bitfld.long 0x00 24. " VALNOGOOD ,SPDIF validity flag no good Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " SYMERR ,SPDIF receiver found illegal symbol Status" "No interrupt,Interrupt" bitfld.long 0x00 22. " BITERR ,SPDIF receiver found parity bit error Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " UTXEM ,UChannel transmit register empty Status" "No interrupt,Interrupt" bitfld.long 0x00 20. " UTXUNDER ,UChannel transmit register underrun Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " UTX_NEXTFIRST ,UChannel transmit register next byte is first Status" "No interrupt,Interrupt" bitfld.long 0x00 18. " URXFUL ,UChannel receive register full Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " URXOV ,UChannel receive register overrun Status" "No interrupt,Interrupt" bitfld.long 0x00 16. " QRXFUL ,QChannel receive register full Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " QRXOV ,QChannel receive register overrun Status" "No interrupt,Interrupt" bitfld.long 0x00 14. " UQSYNC ,U/Q Channel sync found Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " UQERR ,UQERR U/Q Channel framing error Status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PDIRUNOV ,Processor data input underrun/overrun Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PDIRRESYN ,Processor data input resync Status" "No interrupt,Interrupt" bitfld.long 0x00 10. " LOCKLOSS ,SPDIF receiver loss of lock Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " TXEM ,SPDIF Transmit FIFO emcpty Status" "No interrupt,Interrupt" bitfld.long 0x00 8. " PDIRFUL ,PDIRFUL Processor Data Input Full Status" "No interrupt,Interrupt" endif tree.end tree "SPIDF Reception Registers" if (data.long(ANC:iobase()+0xf08)&0x00800000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else rgroup.long 0x1610++0x07 line.long 0x00 "SRXL,EbuRcvLeft Register" hexmask.long 0x00 8.--31. 1. " RCVDATALEFT ,Processor receive SPDIF data left" line.long 0x04 "SRXR,EbuRcvRight Register" hexmask.long 0x04 8.--31. 1. " RCVDATALEFT ,Processor receive SPDIF data right" rgroup.long 0x161c++0x0f line.long 0x00 "SRCSH,EBU_RxCChannel_h Register" hexmask.long 0x00 8.--31. 1. " RXCCHANNEL_H ,First 24 bits of C channel" line.long 0x04 "SRCSL,EBU_RxCChannel_I Register" hexmask.long 0x04 8.--31. 1. " RXCCHANNEL_I ,Next 24 bits of C channel" line.long 0x08 "SRU,EBU_RxUChannel Register" hexmask.long 0x08 8.--31. 1. " RXUCHANNEL ,Next 3 U channel bytes" line.long 0x0c "SRQ,EBU_RxQChannel" hexmask.long 0x0c 8.--31. 1. " RXQCHANNEL ,Next 3 Q channel bytes" endif tree.end tree "SPDIF Transmission Registers" if (data.long(ANC:iobase()+0xf08)&0x00800000)==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else wgroup.long 0x1630++0x07 line.long 0x00 "STXL,EbuTxLeft Register" hexmask.long 0x00 8.--31. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STXR,EbuTxRight Register" hexmask.long 0x04 8.--31. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x1638++0x07 line.long 0x00 "STCSH,EBU_TxCChannelCons_h Register" hexmask.long 0x00 8.--31. 1. " TXCCHANNELCONS_H ,First 24 bits of C channel" line.long 0x04 "STCSL,EBU_TxCChannelCons_I Register" hexmask.long 0x04 8.--31. 1. " TXCCHANNELCONS_I ,Next 24 bits of C channel" group.long 0x1648++0x03 line.long 0x00 "STU,EBU_TxUChannel Register" hexmask.long 0x00 8.--31. 1. " TXUCHANNEL ,Next 3 U channel bytes" endif tree.end tree.end tree "USB-OTG (Universal Serial Bus Interface with On-The-Go IMMARBAR + 0x3000/0x4000)" tree "USB0 - UTMI" width 0xa if (data.long(ANC:iobase()+0xf08)&(0x08000000<<0.))==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long (0x4000+0x1a8)++0x03 "Mode Register" line.long 0x00 "USBMODE,USB Mode Register" bitfld.long 0x00 5. " VBPS ,Vbus Power Select" "Low,High" bitfld.long 0x00 4. " SDIS ,Stream Disable" "Inactive,Active" textline " " bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" textline " " bitfld.long 0x00 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" endif ;HOST MODE if (((d.l(anc:(iobase()+0x4000+0x1a8))&0x03)==0x03)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) rgroup.long 0x4000++0x0b "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" line.long 0x08 "HWHOST,Host Hardware Parameters" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Transaction translator periodic contexts" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Transaction translator contexts" textline " " bitfld.long 0x08 1.--3. " NPORT ,Indicates the number of ports in host mode minus 1" "000,001,010,011,100,101,110,111" bitfld.long 0x08 0. " HC ,Host Capable" "Reserved,Capable" hgroup.long (0x4000+0x0c)++0x03 hide.long 0x00 "HWDEVICE,Device Hardware Parameters Register" rgroup.long (0x4000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x4000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" rgroup.word (0x4000+0x102)++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version" hexmask.word 0x00 0.--15. 1. " HCIVERSION ,EHCI revision number" rgroup.long (0x4000+0x104)++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16. " PI ,Port indicators" "Reserved,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Number Ports per CC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Power Port Control" "Not supported,Supported" textline " " bitfld.long 0x00 0.--3. " N_PORTS ,Number of Ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Reserved,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Reserved,Supported" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "32-bit,64-bit" hgroup.long (0x4000+0x120)++0x7 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd group.long (0x4000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" line.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 0 Load Value" group.long (0x4000+0x88)++0x03 line.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 1 Load Value" group.long (0x4000+0x84)++0x03 line.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x4000+0x8c)++0x03 line.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x4000+0x90)++0x03 line.long 0x00 "SBUSCFG,System Bus Interface Configuration" bitfld.long 0x00 0.--2. " AHBBRST ,Options for the m_nburst signal of the AMBAMI" "INCR,INCR4,INCR8,INCR16,Reserved,INCR4 smaller length,INCR8 smaller length,INCR16 smaller length" width 0x10 ;scetion group.long (0x4000+0x140)++0x0f "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " eventfld.long 0x04 19. " UPI ,USB Host Periodic Interrupt" "Not occurred,Occurred" eventfld.long 0x04 18. " UAI ,USB Host Asynchronous Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation" "Non-empty,Empty" textline " " bitfld.long 0x04 12. " HCH ,HCHaIted" "Running,Halted" eventfld.long 0x04 10. " ULPI ,ULPI Interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x04 7. " SRI ,Non-EHCI status bit" "Low,High" textline " " eventfld.long 0x04 5. " AAI ,Interrupt on Async Advance" "No interrupt,Interrupt" eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" textline " " eventfld.long 0x04 3. " FRI ,Frame List Rollover" "Not occurred,Occurred" eventfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " UPIA ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " UAIE ,USB Host Async. Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ULPIE ,ULPI Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x08 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x0c "FRINDEX,Frame Index Register" hexmask.long.word 0x0c 0.--13. 1. " FRINDEX ,Frame index" group.long (0x4000+0x154)++0x13 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " PERBASE ,Base Address" line.long 0x04 "ASYNCLISTADDR,Current Asynchronous List Address Register" hexmask.long 0x04 5.--31. 0x20 " ASYBASE ,Link Pointer Low (LPL)" line.long 0x08 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" hexmask.long.byte 0x08 24.--30. 1. " TTHA ,Internal TT Hub Address Representation" line.long 0x0c "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x0c 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x0c 0.--7. 1. " RXPBURST ,Programable RX Burst Length" line.long 0x10 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" hexmask.long.byte 0x10 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" bitfld.long 0x10 8.--12. " TXSCHHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x10 0.--6. 1. " TXSCHOH ,Scheduler Overhead" group.long (0x4000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x4000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x4000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x4000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Green,Undefined" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 9. " HSP ,High Speed Port" "Not high speed,High speed" textline " " bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. 2. " SUSP/PE ,Suspend/Port Enable" "Disabled,Disabled,Enabled,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " OCC ,Over-current Change" "No over-current,Over-current" bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Disabled" textline " " eventfld.long 0x00 1. " CSC ,Connect Change Status" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not present,Present" group.long (0x4000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" hgroup.long (0x4000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" group.long (0x4000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x4000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;DEVICE MODE elif (((d.l(anc:(iobase()+0x4000+0x1a8))&0x03)==0x02)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) width 0xa rgroup.long 0x4000++0x07 "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" hgroup.long (0x4000+0x08)++0x03 hide.long 0x00 "HWHOST,Host Hardware Parameters" group.long (0x4000+0x0c)++0x03 line.long 0x00 "HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device capable" "Reserved,Capable" rgroup.long (0x4000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x4000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" hgroup.word (0x4000+0x102)++0x1 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x4000+0x104)++0x7 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" rgroup.long (0x4000+0x120)++0x3 line.long 0x00 "DCIVERSION,Device Controller Interface Version" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Device interface revision number" rgroup.long (0x4000+0x124)++0x3 line.long 0x00 "DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 8. " HC ,Host Capable" "Incapable,Capable" bitfld.long 0x00 7. " DC ,Device Capable" "Incapable,Capable" textline " " hexmask.long.byte 0x00 0.--4. 1. " DEN ,Device Endpoint Number" width 0xd group.long (0x4000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" line.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 0 Load Value" group.long (0x4000+0x88)++0x03 line.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 1 Load Value" group.long (0x4000+0x84)++0x03 line.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x4000+0x8c)++0x03 line.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x4000+0x90)++0x03 line.long 0x00 "SBUSCFG,System Bus Interface Configuration" bitfld.long 0x00 0.--2. " AHBBRST ,Options for the m_nburst signal of the AMBAMI" "INCR,INCR4,INCR8,INCR16,Reserved,INCR4 smaller length,INCR8 smaller length,INCR16 smaller length" width 0x10 group.long (0x4000+0x140)++0x0b "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 10. " ULPI ,ULPI Interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x04 8. " SLI ,DCSuspend" "Active,Suspended" textline " " eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB Reset Received" "Not received,Received" textline " " eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" eventfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ULPIE ,ULPI Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" rgroup.long (0x4000+0x14c)++0x3 line.long 0x00 "FRINDEX,Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" group.long (0x4000+0x154)++0x3 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device Address Write Advance" "Instantaneous,Staged" group.long (0x4000+0x158)++0x3 line.long 0x00 "ENDPOINTLISTADDR,Endpoint List Address Register" hexmask.long 0x00 11.--31. 0x800 " EPBASE ,Endpoint List Address" hgroup.long (0x4000+0x15c)++0x03 hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" group.long (0x4000+0x160)++0x03 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programable RX Burst Length" hgroup.long (0x4000+0x164)++0x03 hide.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" group.long (0x4000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x4000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x4000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x4000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 9. " HSP ,Port Reset" "Not operated,Operated" textline " " bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " OCC ,Over-current Change" "No over-current,Over-current" bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Enabled,Disabled" bitfld.long 0x00 2. " PE ,Port Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached" group.long (0x4000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Low,High" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" group.long (0x4000+0x1ac)++0xb line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" eventfld.long 0x00 3. " SDIS3 ,Setup Endpoint 3 Status" "Not received,Received" eventfld.long 0x00 2. " SDIS2 ,Setup Endpoint 2 Status" "Not received,Received" textline " " eventfld.long 0x00 1. " SDIS1 ,Setup Endpoint 1 Status" "Not received,Received" eventfld.long 0x00 0. " SDIS0 ,Setup Endpoint 0 Status" "Not received,Received" line.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 19. " PETB3 ,Prime Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 17. " PETB1 ,Prime Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 1. " PERB1 ,Prime Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" bitfld.long 0x08 19. " FETB3 ,Flush Endpoint 3 Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint 2 Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 17. " FETB1 ,Flush Endpoint 1 Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint 0 Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint 3 Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint 2 Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 1. " FERB1 ,Flush Endpoint 1 Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint 0 Receive Buffer" "Not flushed,Flushed" rgroup.long (0x4000+0x1b8)++0x3 line.long 0x00 "ENDPTSTATUS,Endpoint Status Register" bitfld.long 0x00 19. " ETBR3 ,Endpoint 3 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint 2 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 17. " ETBR1 ,Endpoint 1 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint 0 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint 3 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint 2 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 1. " ERBR1 ,Endpoint 1 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint 0 Receive Buffer Ready" "Not ready,Ready" group.long (0x4000+0x1bc)++0x3 line.long 0x00 "ENDPTCOMPLETE,Endpoint Complete Register" eventfld.long 0x00 19. " ETCE3 ,Endpoint 3 Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint 2 Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " ETCE1 ,Endpoint 1 Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint 0 Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint 3 Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint 2 Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " ERCE1 ,Endpoint 1 Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint 0 Receive Complete Event" "Not occurred,Occurred" group.long (0x4000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x4000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;IDLE MODE elif (((d.l(anc:(iobase()+0x4000+0x1a8))&0x03)==0x00)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) width 0xa rgroup.long 0x4000++0x07 "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" hgroup.long (0x4000+0x08)++0x07 hide.long 0x00 "HWHOST,Host Hardware Parameters" hide.long 0x04 "HWDEVICE,Device Hardware Parameters Register" rgroup.long (0x4000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x4000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" hgroup.word (0x4000+0x102)++0x01 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x4000+0x104)++0x07 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hgroup.long (0x4000+0x120)++0x07 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd hgroup.long (0x4000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" hide.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hgroup.long (0x4000+0x88)++0x03 hide.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hgroup.long (0x4000+0x84)++0x03 hide.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" hgroup.long (0x4000+0x8c)++0x03 hide.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" hgroup.long (0x4000+0x90)++0x03 hide.long 0x00 "SBUSCFG,System Bus Interface Configuration" width 0x10 group.long (0x4000+0x140)++0xb "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" hgroup.long (0x4000+0x14c)++0x3 hide.long 0x00 "FRINDEX,Frame Index Register" hgroup.long (0x4000+0x154)++0x7 hide.long 0x00 "PERIOD/DEVICE,Device Address/Periodic Frame List Base Address Register" hide.long 0x04 "ASYNC/ENDPOINT,Current Asynchronous List Address/Endpoint List Address Register" hgroup.long (0x4000+0x15c)++0x03 hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" group.long (0x4000+0x160)++0x03 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programable RX Burst Length" hgroup.long (0x4000+0x164)++0x03 hide.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" group.long (0x4000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x4000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x4000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x4000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" group.long (0x4000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Low,High" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" hgroup.long (0x4000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" group.long (0x4000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x4000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;RESERVED elif (((d.l(anc:(iobase()+0x4000+0x1a8))&0x03)==0x01)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) width 0xa hgroup.long 0x4000++0x07 "Module Identification Registers" hide.long 0x00 "ID,Identification Register" hide.long 0x04 "HWGENERAL,General Hardware Parameters" hide.long 0x08 "HWHOST,Host Hardware Parameters" hide.long 0x0c "HWDEVICE,Device Hardware Parameters Register" hide.long 0x10 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hide.long 0x14 "HWRXBUF,Receive Buffer Hardware Parameters Register" width 0xd hgroup.word (0x4000+0x100)++0x03 "Capability Registers" hide.word 0x00 "CAPLENGTH,Capability Registers Length" hide.word 0x02 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x4000+0x104)++0x7 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hgroup.long (0x4000+0x120)++0x7 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd hgroup.long (0x4000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" hide.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hgroup.long (0x4000+0x88)++0x03 hide.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hgroup.long (0x4000+0x84)++0x03 hide.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" hgroup.long (0x4000+0x8c)++0x03 hide.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" hgroup.long (0x4000+0x90)++0x03 hide.long 0x00 "SBUSCFG,System Bus Interface Configuration" width 0x10 hgroup.long (0x4000+0x140)++0xb "Operational Registers" hide.long 0x00 "USBCMD,USB Command Register" hide.long 0x04 "USBSTS,USB Status Register" hide.long 0x08 "USBINTR,USB Interrupt Enable Register" hgroup.long (0x4000+0x14c)++0x3 hide.long 0x00 "FRINDEX,Frame Index Register" hgroup.long (0x4000+0x154)++0x7 hide.long 0x00 "PERIOD/DEVICE,Device Address/Periodic Frame List Base Address Register" hide.long 0x04 "ASYNC/ENDPOINT,Current Asynchronous List Address/Endpoint List Address Register" hgroup.long (0x4000+0x15c)++0x0b hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" hide.long 0x04 "BURSTSIZE,Master Interface Data Burst Size Register" hide.long 0x08 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" hgroup.long (0x4000+0x170)++0x3 hide.long 0x00 "ULPIVIEWPORT,ULPI Register Access" hgroup.long (0x4000+0x178)++0x0b hide.long 0x00 "ENDPTNAK,Endpoint NAK" hide.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" hide.long 0x08 "CONFIGFLAG,Configure Flag Register" hgroup.long (0x4000+0x0184)++0x3 hide.long 0x00 "PORTSC1,Port Status and Control Register 1" hgroup.long (0x4000+0x1a4)++0x03 hide.long 0x00 "OTGSC,On-The-Go Status and Control" hgroup.long (0x4000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" hgroup.long (0x4000+0x01c0)++0x0f hide.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" hide.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" hide.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" hide.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" hgroup.long (0x4000+0x204)++0x03 hide.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x4000+0x1a8))&0x04)==0x00)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) ;Little Endian hgroup.long (0x4000+0x200)++0x03 hide.long 0x00 "USBGENCTRL,USB General Control Register" wgroup 0x00++0x00 elif (((d.l(anc:(iobase()+0x4000+0x1a8))&0x04)==0x04)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<0.))!=0)) ;Big Endian group.long (0x4000+0x200)++0x03 line.long 0x00 "USBGENCTRL0,USB General Control Register" eventfld.long 0x00 5. " WU_INT_CLR ,Wake-up Interrupt Clear" "No action,Clear" bitfld.long 0x00 4. " ULPI_SEL ,ULPI I/F Select" "UTMI I/F,ULPI I/F" textline " " bitfld.long 0x00 3. " PPP ,Port Power Polarity" "Not inverted,Inverted" bitfld.long 0x00 2. " PFP ,Power Fault Polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 1. " WU_ULPI_EN ,WakeUp On ULPI Interrupt Event" "Disabled,Enabled" bitfld.long 0x00 0. " WU_IE ,WakeUp Interrupt Enable" "Disabled,Enabled" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif tree.end tree "USB1 - ULPI" width 0xa if (data.long(ANC:iobase()+0xf08)&(0x08000000<<1.))==0 group VM:0x00++0x0 TEXTLINE "" TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." else group.long (0x3000+0x1a8)++0x03 "Mode Register" line.long 0x00 "USBMODE,USB Mode Register" bitfld.long 0x00 5. " VBPS ,Vbus Power Select" "Low,High" bitfld.long 0x00 4. " SDIS ,Stream Disable" "Inactive,Active" textline " " bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" textline " " bitfld.long 0x00 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" endif ;HOST MODE if (((d.l(anc:(iobase()+0x3000+0x1a8))&0x03)==0x03)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) rgroup.long 0x3000++0x0b "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" line.long 0x08 "HWHOST,Host Hardware Parameters" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Transaction translator periodic contexts" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Transaction translator contexts" textline " " bitfld.long 0x08 1.--3. " NPORT ,Indicates the number of ports in host mode minus 1" "000,001,010,011,100,101,110,111" bitfld.long 0x08 0. " HC ,Host Capable" "Reserved,Capable" hgroup.long (0x3000+0x0c)++0x03 hide.long 0x00 "HWDEVICE,Device Hardware Parameters Register" rgroup.long (0x3000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x3000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" rgroup.word (0x3000+0x102)++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version" hexmask.word 0x00 0.--15. 1. " HCIVERSION ,EHCI revision number" rgroup.long (0x3000+0x104)++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16. " PI ,Port indicators" "Reserved,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Number Ports per CC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Power Port Control" "Not supported,Supported" textline " " bitfld.long 0x00 0.--3. " N_PORTS ,Number of Ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Reserved,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Reserved,Supported" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "32-bit,64-bit" hgroup.long (0x3000+0x120)++0x7 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd group.long (0x3000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" line.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 0 Load Value" group.long (0x3000+0x88)++0x03 line.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 1 Load Value" group.long (0x3000+0x84)++0x03 line.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x3000+0x8c)++0x03 line.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x3000+0x90)++0x03 line.long 0x00 "SBUSCFG,System Bus Interface Configuration" bitfld.long 0x00 0.--2. " AHBBRST ,Options for the m_nburst signal of the AMBAMI" "INCR,INCR4,INCR8,INCR16,Reserved,INCR4 smaller length,INCR8 smaller length,INCR16 smaller length" width 0x10 ;scetion group.long (0x3000+0x140)++0x0f "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " eventfld.long 0x04 19. " UPI ,USB Host Periodic Interrupt" "Not occurred,Occurred" eventfld.long 0x04 18. " UAI ,USB Host Asynchronous Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x04 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation" "Non-empty,Empty" textline " " bitfld.long 0x04 12. " HCH ,HCHaIted" "Running,Halted" eventfld.long 0x04 10. " ULPI ,ULPI Interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x04 7. " SRI ,Non-EHCI status bit" "Low,High" textline " " eventfld.long 0x04 5. " AAI ,Interrupt on Async Advance" "No interrupt,Interrupt" eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" textline " " eventfld.long 0x04 3. " FRI ,Frame List Rollover" "Not occurred,Occurred" eventfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " UPIA ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " UAIE ,USB Host Async. Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ULPIE ,ULPI Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x08 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x0c "FRINDEX,Frame Index Register" hexmask.long.word 0x0c 0.--13. 1. " FRINDEX ,Frame index" group.long (0x3000+0x154)++0x13 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" hexmask.long 0x00 12.--31. 0x1000 " PERBASE ,Base Address" line.long 0x04 "ASYNCLISTADDR,Current Asynchronous List Address Register" hexmask.long 0x04 5.--31. 0x20 " ASYBASE ,Link Pointer Low (LPL)" line.long 0x08 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" hexmask.long.byte 0x08 24.--30. 1. " TTHA ,Internal TT Hub Address Representation" line.long 0x0c "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x0c 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x0c 0.--7. 1. " RXPBURST ,Programable RX Burst Length" line.long 0x10 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" hexmask.long.byte 0x10 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" bitfld.long 0x10 8.--12. " TXSCHHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x10 0.--6. 1. " TXSCHOH ,Scheduler Overhead" group.long (0x3000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x3000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x3000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x3000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Green,Undefined" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 9. " HSP ,High Speed Port" "Not high speed,High speed" textline " " bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. 2. " SUSP/PE ,Suspend/Port Enable" "Disabled,Disabled,Enabled,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " OCC ,Over-current Change" "No over-current,Over-current" bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Disabled" textline " " eventfld.long 0x00 1. " CSC ,Connect Change Status" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not present,Present" group.long (0x3000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" hgroup.long (0x3000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" group.long (0x3000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x3000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;DEVICE MODE elif (((d.l(anc:(iobase()+0x3000+0x1a8))&0x03)==0x02)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) width 0xa rgroup.long 0x3000++0x07 "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" hgroup.long (0x3000+0x08)++0x03 hide.long 0x00 "HWHOST,Host Hardware Parameters" group.long (0x3000+0x0c)++0x03 line.long 0x00 "HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device capable" "Reserved,Capable" rgroup.long (0x3000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x3000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" hgroup.word (0x3000+0x102)++0x1 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x3000+0x104)++0x7 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" rgroup.long (0x3000+0x120)++0x3 line.long 0x00 "DCIVERSION,Device Controller Interface Version" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Device interface revision number" rgroup.long (0x3000+0x124)++0x3 line.long 0x00 "DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 8. " HC ,Host Capable" "Incapable,Capable" bitfld.long 0x00 7. " DC ,Device Capable" "Incapable,Capable" textline " " hexmask.long.byte 0x00 0.--4. 1. " DEN ,Device Endpoint Number" width 0xd group.long (0x3000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" line.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 0 Load Value" group.long (0x3000+0x88)++0x03 line.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hexmask.long 0x00 0.--23. 1. " GPTLD ,General Purpose Timer 1 Load Value" group.long (0x3000+0x84)++0x03 line.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x3000+0x8c)++0x03 line.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" bitfld.long 0x00 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Run" bitfld.long 0x00 30. " GPTRST ,General Purpose Timer Reset" "No action,Load counter" textline " " bitfld.long 0x00 24. " GPTMODE ,General Purpose Timer Mode" "Single countdown,Looped countdown" hexmask.long 0x00 0.--23. 1. " GPTCNT ,General Purpose Timer Counter's Value of The Running TImer" group.long (0x3000+0x90)++0x03 line.long 0x00 "SBUSCFG,System Bus Interface Configuration" bitfld.long 0x00 0.--2. " AHBBRST ,Options for the m_nburst signal of the AMBAMI" "INCR,INCR4,INCR8,INCR16,Reserved,INCR4 smaller length,INCR8 smaller length,INCR16 smaller length" width 0x10 group.long (0x3000+0x140)++0x0b "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 10. " ULPI ,ULPI Interrupt" "Not occurred,Occurred" textline " " eventfld.long 0x04 8. " SLI ,DCSuspend" "Active,Suspended" textline " " eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB Reset Received" "Not received,Received" textline " " eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" eventfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ULPIE ,ULPI Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" rgroup.long (0x3000+0x14c)++0x3 line.long 0x00 "FRINDEX,Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" group.long (0x3000+0x154)++0x3 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device Address Write Advance" "Instantaneous,Staged" group.long (0x3000+0x158)++0x3 line.long 0x00 "ENDPOINTLISTADDR,Endpoint List Address Register" hexmask.long 0x00 11.--31. 0x800 " EPBASE ,Endpoint List Address" hgroup.long (0x3000+0x15c)++0x03 hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" group.long (0x3000+0x160)++0x03 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programable RX Burst Length" hgroup.long (0x3000+0x164)++0x03 hide.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" group.long (0x3000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x3000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x3000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x3000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 9. " HSP ,Port Reset" "Not operated,Operated" textline " " bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " OCC ,Over-current Change" "No over-current,Over-current" bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Enabled,Disabled" bitfld.long 0x00 2. " PE ,Port Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached" group.long (0x3000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Low,High" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" group.long (0x3000+0x1ac)++0xb line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" eventfld.long 0x00 3. " SDIS3 ,Setup Endpoint 3 Status" "Not received,Received" eventfld.long 0x00 2. " SDIS2 ,Setup Endpoint 2 Status" "Not received,Received" textline " " eventfld.long 0x00 1. " SDIS1 ,Setup Endpoint 1 Status" "Not received,Received" eventfld.long 0x00 0. " SDIS0 ,Setup Endpoint 0 Status" "Not received,Received" line.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 19. " PETB3 ,Prime Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 17. " PETB1 ,Prime Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 1. " PERB1 ,Prime Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" bitfld.long 0x08 19. " FETB3 ,Flush Endpoint 3 Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint 2 Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 17. " FETB1 ,Flush Endpoint 1 Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint 0 Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint 3 Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint 2 Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 1. " FERB1 ,Flush Endpoint 1 Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint 0 Receive Buffer" "Not flushed,Flushed" rgroup.long (0x3000+0x1b8)++0x3 line.long 0x00 "ENDPTSTATUS,Endpoint Status Register" bitfld.long 0x00 19. " ETBR3 ,Endpoint 3 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint 2 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 17. " ETBR1 ,Endpoint 1 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint 0 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint 3 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint 2 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 1. " ERBR1 ,Endpoint 1 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint 0 Receive Buffer Ready" "Not ready,Ready" group.long (0x3000+0x1bc)++0x3 line.long 0x00 "ENDPTCOMPLETE,Endpoint Complete Register" eventfld.long 0x00 19. " ETCE3 ,Endpoint 3 Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint 2 Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " ETCE1 ,Endpoint 1 Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint 0 Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint 3 Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint 2 Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " ERCE1 ,Endpoint 1 Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint 0 Receive Complete Event" "Not occurred,Occurred" group.long (0x3000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x3000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;IDLE MODE elif (((d.l(anc:(iobase()+0x3000+0x1a8))&0x03)==0x00)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) width 0xa rgroup.long 0x3000++0x07 "Module Identification Registers" line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision number of the module" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones complement version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration number" line.long 0x04 "HWGENERAL,General Hardware Parameters" bitfld.long 0x04 9.--10. " SM ,SERIAL_MODE" "0,1,2,3" bitfld.long 0x04 6.--8. " PHYM ,PHY_MODE" "000,001,010,011,100,101,110,111" textline " " bitfld.long 0x04 4.--5. " PHYW ,PHY Width" "00,01,10,11" bitfld.long 0x04 3. " BWT ,Reserved for manufacturing test" "0,1" textline " " bitfld.long 0x04 1.--2. " CLKC ,Reserved for manufacturing test" "00,01,10,11" bitfld.long 0x04 0. " RT ,Reserved for manufacturing test" "0,1" hgroup.long (0x3000+0x08)++0x07 hide.long 0x00 "HWHOST,Host Hardware Parameters" hide.long 0x04 "HWDEVICE,Device Hardware Parameters Register" rgroup.long (0x3000+0x10)++0x07 line.long 0x00 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Transmit channel address" textline " " hexmask.long.byte 0x00 8.--15. 1. " TXADD ,Transmit address" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Transmit burst" line.long 0x04 "HWRXBUF,Receive Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Receive address" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Receive burst" width 0xd rgroup.word (0x3000+0x100)++0x01 "Capability Registers" line.word 0x00 "CAPLENGTH,Capability Registers Length" hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" hgroup.word (0x3000+0x102)++0x01 hide.word 0x00 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x3000+0x104)++0x07 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hgroup.long (0x3000+0x120)++0x07 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd hgroup.long (0x3000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" hide.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hgroup.long (0x3000+0x88)++0x03 hide.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hgroup.long (0x3000+0x84)++0x03 hide.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" hgroup.long (0x3000+0x8c)++0x03 hide.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" hgroup.long (0x3000+0x90)++0x03 hide.long 0x00 "SBUSCFG,System Bus Interface Configuration" width 0x10 group.long (0x3000+0x140)++0xb "Operational Registers" line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" textline " " bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not extracted,Extracted" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Invalid,1,2,3" textline " " bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset (Not Implemented)" "0,1" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 4. " SEI ,System Error" "Normal,Error" textline " " eventfld.long 0x04 1. " UEI ,USB Error Interrupt (USBERRINT)" "No error,Error" eventfld.long 0x04 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" line.long 0x08 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x08 25. " TIE1 ,General Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" hgroup.long (0x3000+0x14c)++0x3 hide.long 0x00 "FRINDEX,Frame Index Register" hgroup.long (0x3000+0x154)++0x7 hide.long 0x00 "PERIOD/DEVICE,Device Address/Periodic Frame List Base Address Register" hide.long 0x04 "ASYNC/ENDPOINT,Current Asynchronous List Address/Endpoint List Address Register" hgroup.long (0x3000+0x15c)++0x03 hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" group.long (0x3000+0x160)++0x03 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programable RX Burst Length" hgroup.long (0x3000+0x164)++0x03 hide.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" group.long (0x3000+0x170)++0x3 line.long 0x00 "ULPIVIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPIWU ,ULPI Wake Up" "No wake up,Wake up" bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "Completed,Running" textline " " bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write" bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Other,Normal" textline " " bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address" textline " " hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read Value" hexmask.long.byte 0x00 0.--7. 1. " ULPIDTWR ,ULPI Data Write Value" group.long (0x3000+0x178)++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK" eventfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1 Handshake on a Received IN Token" "No handshake,Handshake" eventfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0 Handshake on a Received IN Token" "No handshake,Handshake" textline " " eventfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2 Handshake on a Received OUT/PING Token" "No handshake,Handshake" textline " " eventfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1 Handshake on a Received OUT/PING Token" "No handshake,Handshake" eventfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0 Handshake on a Received OUT/PING Token" "No handshake,Handshake" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" eventfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " eventfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" hgroup.long (0x3000+0x180)++0x03 hide.long 0x00 "CONFIGFLAG,Configure Flag Register" group.long (0x3000+0x0184)++0x3 line.long 0x00 "PORTSC1,Port Status and Control Register 1" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI parallel,Reserved,ULPI parallel,FS/LS" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" textline " " bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Reserved" bitfld.long 0x00 24. " PFSC ,Port Force Full-speed Connect" "High,Full" textline " " bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Normal,Low power" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Not enabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 13. " PO ,Port Owner" "No owner,Internal companion" bitfld.long 0x00 12. " PP ,Port Power" "Off,On" textline " " bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" group.long (0x3000+0x1a4)++0x3 line.long 0x00 "OTGSC,On-The-Go Status and Control" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " 1msS ,1 millisecond timer Interrupt Status" "Low,High" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" bitfld.long 0x00 13. " 1msT ,1 millisecond Timer Toggle" "0,1" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Above,Below" bitfld.long 0x00 11. " BSV ,B Session Valid" "Below,Above" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Below,Above" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Below,Above" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Stopped,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not asserted,Asserted" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS discharge" "Charged,Discharged" hgroup.long (0x3000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" group.long (0x3000+0x01c0)++0x0f line.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Reserved,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint type" "Control,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint type" "Control,Reserved,Reserved,Reserved" bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "Not synchronized,Synchronized" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "Not synchronized,Synchronized" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory/DMA,Reserved" textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" group.long (0x3000+0x204)++0x03 line.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" bitfld.long 0x00 5. " OCO ,Oscillator Control Override" "USB PHY,ISIPHYCTRL.PXE" bitfld.long 0x00 4. " PHYE ,On-Chip UTMI PHY Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSENH ,Bit Stuff Enable High" "Disabled,Enabled" bitfld.long 0x00 2. " BSEN ,Bit Stuff Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LSFE ,Line State Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " PXE ,PHY Oscillator Enable" "Disabled,Enabled" ;RESERVED elif (((d.l(anc:(iobase()+0x3000+0x1a8))&0x03)==0x01)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) width 0xa hgroup.long 0x3000++0x07 "Module Identification Registers" hide.long 0x00 "ID,Identification Register" hide.long 0x04 "HWGENERAL,General Hardware Parameters" hide.long 0x08 "HWHOST,Host Hardware Parameters" hide.long 0x0c "HWDEVICE,Device Hardware Parameters Register" hide.long 0x10 "HWTXBUF,Transmit Buffer Hardware Parameters Register" hide.long 0x14 "HWRXBUF,Receive Buffer Hardware Parameters Register" width 0xd hgroup.word (0x3000+0x100)++0x03 "Capability Registers" hide.word 0x00 "CAPLENGTH,Capability Registers Length" hide.word 0x02 "HCIVERSION,Host Controller Interface Version" hgroup.long (0x3000+0x104)++0x7 hide.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" hide.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hgroup.long (0x3000+0x120)++0x7 hide.long 0x00 "DCIVERSION,Device Controller Interface Version" hide.long 0x04 "DCCPARAMS,Device Controller Capability Parameters" width 0xd hgroup.long (0x3000+0x80)++0x03 "Device/Host Timer Registers (Non-EHCI)" hide.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hgroup.long (0x3000+0x88)++0x03 hide.long 0x00 "GPTIMER1LD,General Purpose Timer 1 Load Register" hgroup.long (0x3000+0x84)++0x03 hide.long 0x00 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" hgroup.long (0x3000+0x8c)++0x03 hide.long 0x00 "GPTIMER1CTRL,General Purpose Timer 1 Control Register" hgroup.long (0x3000+0x90)++0x03 hide.long 0x00 "SBUSCFG,System Bus Interface Configuration" width 0x10 hgroup.long (0x3000+0x140)++0xb "Operational Registers" hide.long 0x00 "USBCMD,USB Command Register" hide.long 0x04 "USBSTS,USB Status Register" hide.long 0x08 "USBINTR,USB Interrupt Enable Register" hgroup.long (0x3000+0x14c)++0x3 hide.long 0x00 "FRINDEX,Frame Index Register" hgroup.long (0x3000+0x154)++0x7 hide.long 0x00 "PERIOD/DEVICE,Device Address/Periodic Frame List Base Address Register" hide.long 0x04 "ASYNC/ENDPOINT,Current Asynchronous List Address/Endpoint List Address Register" hgroup.long (0x3000+0x15c)++0x0b hide.long 0x00 "HCETTABS,Host Controller Embedded TT Asynchronous Buffer Status" hide.long 0x04 "BURSTSIZE,Master Interface Data Burst Size Register" hide.long 0x08 "TXFILLTUNING,Transmit FIFO Tuning Controls Register" hgroup.long (0x3000+0x170)++0x3 hide.long 0x00 "ULPIVIEWPORT,ULPI Register Access" hgroup.long (0x3000+0x178)++0x0b hide.long 0x00 "ENDPTNAK,Endpoint NAK" hide.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable" hide.long 0x08 "CONFIGFLAG,Configure Flag Register" hgroup.long (0x3000+0x0184)++0x3 hide.long 0x00 "PORTSC1,Port Status and Control Register 1" hgroup.long (0x3000+0x1a4)++0x03 hide.long 0x00 "OTGSC,On-The-Go Status and Control" hgroup.long (0x3000+0x1ac)++0x13 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "ENDPTFLUSH,Endpoint Flush Register" hide.long 0x0c "ENDPTSTAT,Endpoint Status Register" hide.long 0x10 "ENDPTCOMPLETE,Endpoint Complete Register" hgroup.long (0x3000+0x01c0)++0x0f hide.long 0x00 "ENDPTCTRL0,Endpoint Control Register 0" hide.long 0x4 "ENDPTCTRL1,Endpoint Control Register 1" hide.long 0x8 "ENDPTCTRL2,Endpoint Control Register 2" hide.long 0xC "ENDPTCTRL3,Endpoint Control Register 3" hgroup.long (0x3000+0x204)++0x03 hide.long 0x00 "ISIPHYCTRL,On-Chip PHY Control Register" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif if (((d.l(anc:(iobase()+0x3000+0x1a8))&0x04)==0x00)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) ;Little Endian hgroup.long (0x3000+0x200)++0x03 hide.long 0x00 "USBGENCTRL,USB General Control Register" wgroup 0x00++0x00 elif (((d.l(anc:(iobase()+0x3000+0x1a8))&0x04)==0x04)&&((d.l(ANC:iobase()+0xf08)&(0x08000000<<1.))!=0)) ;Big Endian group.long (0x3000+0x200)++0x03 line.long 0x00 "USBGENCTRL1,USB General Control Register" eventfld.long 0x00 5. " WU_INT_CLR ,Wake-up Interrupt Clear" "No action,Clear" textline " " bitfld.long 0x00 1. " WU_ULPI_EN ,WakeUp On ULPI Interrupt Event" "Disabled,Enabled" bitfld.long 0x00 0. " WU_IE ,WakeUp Interrupt Enable" "Disabled,Enabled" else group VM:0x00++0x0 TEXTLINE " " TEXTLINE "The system clock for this peripheral block is currently disabled," TEXTLINE "registers can not be displayed in this state. See Clock Control Module." endif tree.end tree.end tree "VIU (Video-In IMMRBAR + 0x2400)" width 27. group.long 0x2400++0x27 line.long 0x00 "STATUS_CONFIG,Status and Configuration Register" bitfld.long 0x00 31. " MODE_32BIT ,MODE_32BIT (RGB format)" "RGB565,RGBa888" bitfld.long 0x00 30. " ROUND_ON ,Round is on " "Off,On" textline " " bitfld.long 0x00 29. " DITHER_ON ,Dithering is on" "Off,On" bitfld.long 0x00 28. " FIELD_NO ,Field number" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " DMA_ACT ,Enable DMA transfer" "Disabled,Enabled" bitfld.long 0x00 21. " ERROR_IRQ ,Error event occurs" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " DMA_END_IRQ ,Active field data transfer is done" "Not occurred,Occurred" bitfld.long 0x00 19. " VSTART_IRQ ,Active field starts on ITU interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " HSYNC_IRQ ,Active line is over on ITU interface" "Not occurred,Occurred" bitfld.long 0x00 17. " VSYNC_IRQ ,Active field is over on ITU interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " FIELD_IRQ ,Field number is changed" "Not occurred,Occurred" bitfld.long 0x00 14. " ECC_EN ,Enable bit for ECC" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " ERROR_EN ,Interrupt enable bit for ERROR_IRQ" "Disabled,Enabled" bitfld.long 0x00 12. " DMA_END_EN ,Interrupt enable bit for DMA_END_IRQ" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " VSTART_EN ,Interrupt enable bit for VSTART_IRQ" "Disabled,Enabled" bitfld.long 0x00 10. " HSYNC_EN ,Interrupt enable bit for HSYNC_IRQ" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " VSYNC_EN ,Interrupt enable bit for VSYNC_IRQ" "Disabled,Enabled" bitfld.long 0x00 8. " FIELD_EN ,Interrupt enable bit for FIELD_IRQ" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " ERROR_CODE ,Signals error that triggered error IRQ" "No error,DMA (vertical active),DMA (vertical blanking),Reserved,Line too long,Too many lines in field,Line too short,Not enough lines in field,FIFO overflow,FIFO underflow,One bit ECC error,Two or more bits ECC error,Reserved,Reserved,Reserved,Reserved" textline " " bitfld.long 0x00 0. " SOFT_RESET ,Internal reset" "No effect,Reset" line.long 0x04 "LUMINANCE_COEFFICIENTS,Luminance Coefficients For Red, Green and Blue Matrix" hexmask.long.word 0x04 22.--31. 1. " Y_RED[9:0] ,Luminance coefficient for red matrix" hexmask.long.word 0x04 11.--20. 1. " Y_GREEN[9:0] ,Luminance coefficient for green matrix" textline " " hexmask.long.word 0x04 0.--9. 1. " Y_BLUE[9:0] ,Luminance coefficient for blue matrix" line.long 0x08 "RED_CHROMA_COEFFICIENTS,Chroma Coefficients For Red Matrix" hexmask.long.word 0x08 16.--26. 1. " CR_RED[10:0] ,Cr coefficient for red matrix" hexmask.long.word 0x08 0.--11. 1. " CB_RED[11:0] ,Cb coefficient for red matrix" line.long 0x0C "GREEN_CHROMA_COEFFICIENTS,Chroma Coefficients For Red Matrix" hexmask.long.word 0x0C 16.--26. 1. " CR_GREEN[10:0] ,Cr coefficient for green matrix" hexmask.long.word 0x0C 0.--11. 1. " CB_GREEN[11:0] ,Cb coefficient for green matrix" line.long 0x10 "BLUE_CHROMA_COEFFICIENTS,Chroma Coefficients For Red Matrix" hexmask.long.word 0x10 16.--26. 1. " CR_BLUE[10:0] ,Cr coefficient for blue matrix" hexmask.long.word 0x10 0.--11. 1. " CB_BLUE[11:0] ,Cb coefficient for blue matrix" line.long 0x14 "DMA_ADDRESS,Base Address Of Every Field Of Picture In Memory" hexmask.long 0x14 3.--31. 0x08 " DMA_ADDRESS[31:3] ,Base address of every field of picture" line.long 0x18 "DMA_INCREMENT,Horizontal Dma Increment" hexmask.long.word 0x18 3.--15. 1. " DMA_INCREMENT[15:3] ,Zero or memory size that one active line occupies in memory" line.long 0x1C "PICTURE_COUNT,Max Pixel and Line Count" hexmask.long.word 0x1C 16.--31. 1. " LINE_COUNT[15:0] ,Active lines in each field" hexmask.long.word 0x1C 0.--15. 1. " PIXEL_COUNT[15:0] ,Active pixels in each line" line.long 0x20 "HI_PRIO_ALARM,High Priority Transfer Request Alarm" hexmask.long.word 0x20 0.--15. 1. " HI_PRIO_ALARM[15:0] ,High priority alarm threshold" line.long 0x24 "ALPHA,Programable Alpha Value" hexmask.long.byte 0x24 0.--7. 1. " ALPHA[7:0] ,Alpha value used for picture blending" width 0xb tree.end textline "" textline ""