; -------------------------------------------------------------------------------- ; @Title: Peripherals of MPC107 PCI Bridge/Memory Controller ; @Author: rweiss ; @Chiplist: MPC745 MPC755 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permpc107.per 11638 2020-02-27 14:53:08Z rweiss $ BASE ANC:0 tree.open "MPC107 Registers (Address Map B)" config 16. 8. width 16. endian.le tree "PCI Configuration Space Header" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000000 line.word 0. "0x00 VENDOR,Vendor ID" line.word 2. "0x02 ID,Device ID" group.word ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000004 line.word 0. "0x04 PCICMD,PCI command register" bitfld.word 0. 9. " FBTB ,Fast back-to-back" "0,1" bitfld.word 0. 8. " SERR ,Enables the SERR driver" "0,1" bitfld.word 0. 6. " PERR ,Parity error response" "0,1" bitfld.word 0. 4. " MWAI ,Memory-write-and-invalidate" "0,1" textline " " bitfld.word 0. 3. " SC ,Special cycles" "0,1" bitfld.word 0. 2. " BM ,Bus master" "0,1" bitfld.word 0. 1. " MS ,Memory space" "0,1" bitfld.word 0. 0. " IO ,I/O space" "0,1" line.word 2. "0x06 PCISTAT,PCI status register" bitfld.word 2. 15. " DPE ,Detected Parity Error" "0,1" bitfld.word 2. 14. " SSE ,Signal SystemError" "0,1" bitfld.word 2. 13. " RMA ,Received Master-Abort" "0,1" bitfld.word 2. 12. " RTA ,Received Target-Abort" "0,1" textline " " bitfld.word 2. 11. " STA ,Signaled Target-Abort" "0,1" bitfld.word 2. 9.--10. " DEVSEL ,Device Select Timing" "0,1" bitfld.word 2. 08. " DPD ,Data Parity Detected" "0,1" bitfld.word 2. 07. " FB2BC ,Fast Back-to-Back Capable" "0,1" bitfld.word 2. 05. " 66 ,66-MHz Capable" "0,1" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000008 line.byte 0. "0x08 REVID,Revision ID" line.byte 1. "0x09 SPI,Standard programming interface" line.byte 2. "0x0A SUBCCODE,Subclass code" line.byte 3. "0x0B CCODE,Base class code" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x8000000C line.byte 0. "0x0C CACHESIZ,Cache Line Size" line.byte 1. "0x0D LATTIMER,Latency Timer" line.byte 2. "0x0E HEADTYPE,Header Type" line.byte 3. "0x0F BISTCTRL,BIST Control" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000010 line.long 0. "0x10 LMBAR,Local Memory Base Address Register (reserved in the MPC107)" hexmask.long 0. 12.--31. 0x1000 0. " IMBA ,Inbound memory base address" bitfld.long 0. 03.--03. " Pre ,space is prefetchable" "0,1" bitfld.long 0. 01.--02. " TYPE ,inbound memory window may be located within the PCI address space" "00,01,10,11" bitfld.long 0. 00.--00. " MSI ,Memory space indicator" "0,1" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000014 line.long 0. "0x14 PCSRBAR,Peripheral Control and Status Base Address Register" hexmask.long 0. 12.--31. 0x1000 0. " ADDR ,PCI base address mapped to the runtime register (DMA,I2O,...)" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x8000003C line.byte 0. "0x3C ILR,Interrupt Line" line.byte 1. "0x3D INTPIN,Interrupt Pin" line.byte 2. "0x3E MIN_GNT,Specifies the length of the device's burst period" line.byte 3. "0x3F MAX_LAT,Specifies how often the device needs to gain access to the PCI bus" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000040 line.byte 0. "0x40 BUSNB,Bus number" line.byte 1. "0x41 SBUSNB,Subordinate bus number" group.word ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000044 line.word 2. "0x46 PCIARB,PCI Arbiter Control Register" bitfld.word 2. 15. " EPCI ,Enable internal PCI arbitration" "0,1" bitfld.word 2. 13.--14. " PM ,Parking mode control" "last device use bus,device using REQ0/GNT0,MPC107,res" bitfld.word 2. 10. " RPCC ,Retry PCI configuration cycle" "respond,retries all" bitfld.word 2. 07. " PL ,MPC107 priority level" "low,high" hexmask.word 2. 00.--04. 1. 0. " EDPL ,External device priority levels" tree.end tree "Peripheral Logic Power Management / Output/Clock Driver / Misc I/O" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000070 line.word 0. "0x70 PMCR1, Power Management Configuration Register 1" bitfld.word 0. 15. " NO_NAP_MSG ,HALT command broadcast not supported on the MPC107" "0,1" bitfld.word 0. 14. " NO_SLEEP_MSG ,Sleep message broadcast. Not supported on the MPC107" "0,1" bitfld.word 0. 12. " LP_REF_EN ,Low-power refresh" "0,1" textline " " bitfld.word 0. 07. " PM ,Power management enable" "0,1" bitfld.word 0. 05. " DOZE ,Ena/dis the DOZE mode capability. Only valid if PMCR1[PM]=1." "0,1" bitfld.word 0. 04. " NAP ,Ena/dis the NAP mode capability. Only valid if PMCR1[PM]=1." "0,1" bitfld.word 0. 03. " SLEEP ,Ena/dis the SLEEP mode capability. Only valid if PMCR1[PM]=1." "0,1" textline " " bitfld.word 0. 01--02 " CKO_MODE ,Selects the clock source for the test clock output when CKO_SEL = 1" "dis, internal sys_logic-clk,one-half of the PCI rate clock,internal PCI rate clock" textline " " bitfld.word 0. 00. " CKO_SEL ,output for the CKO signal" "core clock,system logic clock" line.byte 2. "0x72 PMCR2, Power Management Configuration Register 2" bitfld.byte 2. 07. " DLL_EXTEND ,used to shift the lock-range of the DLL by half of a PCI clock cycle" "0,1" bitfld.byte 2. 04--06 " PCI_HOLD_DEL ,PCI output hold delay value relative to the PCI_SYNC_IN signal." "000(66MHz),001,010,011,100(33MHz),101,110(def),111" bitfld.word 2. 02. " PLL_SLEEP ,Power management enable" "0,1" line.byte 3. "0x73 ODCR,Output Driver Control Register" bitfld.byte 3. 07. " DRV_PCI ,Driver capability for PCI and EPIC" "25 Ohm,50 Ohm " textline " " bitfld.byte 3. 06. " DRV_STD ,Driver capability for standard signals" "20 Ohm,40 Ohm " textline " " bitfld.byte 3. 04.--05. " DRV_MEM_CTRL ,Driver capability for address signals" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.byte 3. 02.--03. " DRV_PCI_CLK ,Driver capability. Control drive strength of PCI_CLK, PCI_CLK_SYNC_OUT" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.byte 3. 00.--01. " DRV_MEM_CLK ,Driver capability. Control drive strength of SDRAM_CLK, SDRAM_SYNC_OUT" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000074 line.word 0 "0x74 CLKDCR,CLK Driver Control Register" bitfld.word 0. 15. " PCI_SYNC_OUT ,disables the PCI_CLK_SYNC_OUT signal" "0,1" textline " " bitfld.word 0. 14. " PCI_CLK0_DIS ,disables the PCI_CLK0 output" "0,1" bitfld.word 0. 13. " PCI_CLK1_DIS ,disables the PCI_CLK1 output" "0,1" bitfld.word 0. 12. " PCI_CLK2_DIS ,disables the PCI_CLK2 output" "0,1" textline " " bitfld.word 0. 11. " PCI_CLK3_DIS ,disables the PCI_CLK3 output" "0,1" bitfld.word 0. 10. " PCI_CLK4_DIS ,disables the PCI_CLK4 output" "0,1" textline " " bitfld.word 0. 8.--9. " DRV_CPU_CLK ,Driver capability for the CPU_CLK[0:2]" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.word 0. 07. " SDRAM_SYNC_OUT ,disables the SDRAM_SYNC_OUT output" "0,1" textline " " bitfld.word 0. 06. " SDRAM_CLK0_DIS ,SDRAM_CLK0 output" "0,1" bitfld.word 0. 05. " SDRAM_CLK1_DIS ,SDRAM_CLK1 output" "0,1" textline " " bitfld.word 0. 04. " SDRAM_CLK2_DIS ,SDRAM_CLK2 output" "0,1" bitfld.word 0. 03. " SDRAM_CLK3_DIS ,SDRAM_CLK3 output" "0,1" textline " " bitfld.word 0. 02. " CPU_CLK0_DIS ,disables the CPU_CLK0_DIS output" "0,1" bitfld.word 0. 01. " CPU_CLK1_DIS ,disables the CPU_CLK1_DIS output" "0,1" bitfld.word 0. 00. " CPU_CLK2_DIS ,disables the CPU_CLK2_DIS output" "0,1" line.byte 2. "0x76 MDCR" bitfld.byte 2. 07. " MCP_OD_MODE ,MCP output open-drain" "0,1" bitfld.byte 2. 06. " SRESET_OD_MODE ,SRESET output open-drain" "0,1" bitfld.byte 2. 05. " NO_HI-Z_QACK ,always drive QACK" "0,1" tree.end tree "Memory Interface Configuration Register" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000080 line.long 0. "0x80 MSAR1,Memory Starting Address Register 1" hexmask.byte.long 0. 0.--7. 0x1000000 0. " Start Address 0 ,Starting address bank 0" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0. " Start Address 1 ,Starting address bank 1" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0. " Start Address 2 ,Starting address bank 2" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0. " Start Address 3 ,Starting address bank 3" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000084 line.long 0 "0x84 MSAR2 ,Memory Starting Address Register 2" hexmask.byte.long 0. 0.--7. 0x1000000 0. " Start Address 4 ,Starting address bank 4" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0. " Start Address 5 ,Starting address bank 5" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0. " Start Address 6 ,Starting address bank 6" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0. " Start Address 7 ,Starting address bank 7" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000088 line.long 0 "0x88 EMSAR1 ,Extended Memory Starting Address Register 1" bitfld.byte 0. 00.--01. " Ext. Start address 0 ,Ext. Starting address bank 0" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. Start address 1 ,Ext. Starting address bank 1" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. Start address 2 ,Ext. Starting address bank 2" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. Start address 3 ,Ext. Starting address bank 3" "0,1,2,3" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x8000008C line.long 0 "0x8C EMSAR2 ,Extended Memory Starting Address Register 2" bitfld.byte 0. 00.--01. " Ext. Start address 4 ,Ext. Starting address bank 4" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. Start address 5 ,Ext. Starting address bank 5" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. Start address 6 ,Ext. Starting address bank 6" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. Start address 7 ,Ext. Starting address bank 7" "0,1,2,3" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000090 line.long 0 "0x90 MEAR1 ,Memory Ending Address Register 1" hexmask.byte.long 0. 0.--7. 0x1000000 0xFFFFFF " End Address 0 ,Ending address bank 1" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0xFFFFFF " End Address 1 ,Ending address bank 1" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0xFFFFFF " End Address 2 ,Ending address bank 2" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0xFFFFFF " End Address 3 ,Ending address bank 3" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000094 line.long 0 "0x94 MEAR2 ,Memory Ending Address Register 2" hexmask.byte.long 0. 0.--7. 0x1000000 0xFFFFFF " End Address 4 ,Ending address bank 4" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0xFFFFFF " End Address 5 ,Ending address bank 5" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0xFFFFFF " End Address 6 ,Ending address bank 6" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0xFFFFFF " End Address 7 ,Ending address bank 7" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80000098 line.long 0 "0x98 EMEAR1 ,Extended Memory Ending Address Register 1" bitfld.byte 0. 00.--01. " Ext. End Address 0 ,Ext. Ending address bank 0" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. End Address 1 ,Ext. Ending address bank 1" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. End Address 2 ,Ext. Ending address bank 2" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. End Address 3 ,Ext. Ending address bank 3" "0,1,2,3" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x8000009C line.long 0 "0x9C EMEAR2 ,Extended Memory Ending Address Register 2" bitfld.byte 0. 00.--01. " Ext. End Address 4 ,Ext. Ending address bank 4" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. End Address 5 ,Ext. Ending address bank 5" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. End Address 6 ,Ext. Ending address bank 6" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. End Address 7 ,Ext. Ending address bank 7" "0,1,2,3" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000A0 line.byte 0 "0xA0 MBNKEN,Memory Bank Enable Register" bitfld.byte 0. 7. " B7 ,Bank7" "0,1" bitfld.byte 0. 6. " B6 ,Bank6" "0,1" bitfld.byte 0. 5. " B5 ,Bank5" "0,1" bitfld.byte 0. 4. " B4 ,Bank4" "0,1" textline " " bitfld.byte 0. 3. " B3 ,Bank3" "0,1" bitfld.byte 0. 2. " B2 ,Bank2" "0,1" bitfld.byte 0. 1. " B1 ,Bank1" "0,1" bitfld.byte 0. 0. " B0 ,Bank0" "0,1" textline "" line.byte 3 "0xA3 MPMOD ,Memory Page Mode Register" hexmask.byte 3. 0.--7. 1. 0. " PGMAX " tree.end tree "Processor Interface Configuration Register" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000A8 line.long 0 "0xA8 PICR1,Processor Interface Configuration Register 1" bitfld.long 0. 22.--23. " CF_BREAD_WS ,Burst read wait states" "0,1,2,3" bitfld.long 0. 20. " RSC0 ,ROM Location" "PCI,Local Bus" textline " " bitfld.long 0. 17.--18. " PROC_TYPE ,Processor Type" "res,res,603e/7xx/74xx,res" textline " " bitfld.long 0. 16. " ADDR_MAP ,Address Map" "B,A" textline " " bitfld.long 0. 14.--15. " CF_MP_ID ,Multiprocessor identifier" "0,1" bitfld.long 0. 13. " CF_LBA_EN ,Local bus slave access enable" "0,1" textline " " bitfld.long 0. 12. " FLASH_WR_EN ,Flash write enable" "0,1" bitfld.long 0. 11. " MCP_EN ,Machine check enable" "0,1" bitfld.long 0. 10. " TEA_EN ,Assert TEA upon detecting a bus error" "0,1" textline " " bitfld.long 0. 07. " NO_BWIDTH_CK ,flash write not restricted to bus width" "0,1" bitfld.long 0. 06. " ST_GATH_EN ,ena/dis gathering of writes from the proc to PCI memory space" "0,1" bitfld.long 0. 05. " LE_MODE ,MPC107 in little endian mode" "0,1" textline " " bitfld.long 0. 04. " CF_LP_SNOOP ,enable snooping" "0,1" bitfld.long 0. 03. " CF_APARK ,Indicates that the last processor that used the 60x bus is parked" "0,1" bitfld.long 0. 02. " SPCIR ,Speculative PCI reads" "0,1" bitfld.long 0. 00.--01. " CF_MP ,Multiprocessor configuration" "Uniprocessor system,res,res,Multiprocessor system" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000AC line.long 0 "0xAC PICR2, Processor Interface Configuration Register 2" bitfld.long 0. 29. " NO_SER_CFG ,Configuration writes to PCI devices from the processor do not cause serialization" "0,1" bitfld.long 0. 27. " NO_SNOOP_EN ,generates snoop transaction on the peripheral bus for PCI-to-system memory transactions" "0,1" textline " " bitfld.long 0. 26. " CF_FF0_LOCAL ,ROM mapping enable" "0,1" bitfld.long 0. 25. " FLASH_WR_LKO ,Flash write lock-out" "0,1" textline " " bitfld.long 0. 18.--19. " CF_SNOOPS_WS ,Snoop wait states" "0,1,2,3" bitfld.long 0. 9.--10. " CF_LBCLM_WS ,Snoop wait states" "0,1,2,3" bitfld.long 0. 2.--3. " CF_APHASE_WS ,Address phase wait states" "0,1,2,3" tree.end TREE "Error Handling and Exceptions" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000B8 line.byte 0. "0xB8 ECCCNT,ECC Single-Bit error counter" line.byte 1. "0xB9 ECCTRG,ECC Single-Bit Trigger" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000C0 line.byte 0. "0xC0 ERRENR1,Error Enabling Register 1" bitfld.byte 0. 7. " RX_SERR ,Enables the reporting of SERR assertions that occur on the PCI bus two clock cycles after the address phase of transactions where the MPC107 is the initiator" "0,1" bitfld.byte 0. 6. " PCI target PERR ,Enables the reporting of data parity errors on the PCI bus for transactions involving the MPC107 as a target" "0,1" textline " " bitfld.byte 0. 5. " Memory select error ,Enables the reporting of memory select errors that occur on (attempted) accesses to system memory" "0,1" bitfld.byte 0. 4. " Memory refresh overflow ,Enables the reporting of memory refresh overflow errors" "0,1" textline " " bitfld.byte 0. 3. " PCI Master PERR ,Enables the reporting of data parity errors on the PCI bus for transactions involving the MPC107 as a master" "0,1" bitfld.byte 0. 2. " Memory parity/ECC error ,Enables the reporting of system memory read parity errors that occur on accesses to system memory or those that exceed the ECC single-bit error threshold" "0,1" textline " " bitfld.byte 0. 1. " PCI master-abort error ,Enables the reporting of master-abort errors that occur on the PCI bus for transactions involving the MPC107 as a master" "0,1" bitfld.byte 0. 0. " Proc. transaction error ,Enables the reporting of processor transaction errors" "0,1" textline "" line.byte 1. "0xC1 ERRDR1,Error Detection Register 1" bitfld.byte 1. 7. " PCI SERR ,SERR detected" "0,1" bitfld.byte 1. 6. " PCI target PERR ,Detected data parity errors on the PCI bus for transactions involving the MPC107 as a target" "0,1" textline " " bitfld.byte 1. 5. " Memory select error ,Detected memory select errors that occur on (attempted) accesses to system memory" "0,1" bitfld.byte 1. 4. " Memory refresh overflow ,Detected memory refresh overflow errors" "0,1" textline " " bitfld.byte 1. 3. " Processor/PCI cycle ,Error occurred on a PCI-initiated cycle." "0,1" bitfld.byte 1. 2. " Memory parity/ECC error ,Memory read parity error/ECC single-bit error trigger exceeded" "0,1" textline " " bitfld.byte 1. 0.--1. " Unsupp. proc. trans ,Unsupported processor transaction" "0,1,res,res" textline "" line.byte 3. "0xC3 PBESR,Processor Bus Error Status Register" hexmask.byte 3. 3.--7. 1. 0. " TT[0:4] " hexmask.byte 3. 0.--2. 1. 0. " TSIZ[0:2] " textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000C4 line.byte 0. "0xC4 ERRENR2,Error Enabling Register 2" bitfld.byte 0. 7. " PCI addr parity error ,Enables PCI address parity errors" "0,1" bitfld.byte 0. 6. " PCI SERR ,Enables the reporting of SERR assertions that occur on the PCI bus" "0,1" textline " " bitfld.byte 0. 3. " ECC multi-bit error ,Enables the detection of ECC multibit errors" "0,1" bitfld.byte 0. 2. " Proc mem wr parity err ,Enables the detection of processor memory write parity errors" "0,1" textline " " bitfld.byte 0. 1. " PCI rec tgt abort error ,enables the detection of target abort errors received by the PCI interface" "0,1" bitfld.byte 0. 0. " Flash ROM write error ,Enables error on writing protected flash" "0,1" textline "" line.byte 1. "0xC5 ERRDR2, Error detection register 2" bitfld.byte 1. 7. " Invalid error address ,address stored in the processor/PCI error address register is valid" "val,inv" bitfld.byte 1. 6. " PCI SERR ,Detected SERR assertions that occur on the PCI bus" "0,1" textline " " bitfld.byte 1. 3. " ECC multi-bit error ,Detected ECC multibit errors" "0,1" bitfld.byte 1. 2. " Proc mem wr parity err ,Detected processor memory write parity errors" "0,1" textline " " bitfld.byte 1. 1. " PCI rec tgt abort error ,Detected of target abort errors received by the PCI interface" "0,1" bitfld.byte 1. 0. " Flash ROM write error ,Detected writing protected flash" "0,1" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000c4 line.byte 3. "0xC7 PCIBESR, PCI Bus Error Status register" bitfld.byte 3. 4. " MTS ,MPC107 master/target status" "Master,Target" hexmask.byte 3. 0.--2. 1. 0. " C/BE ,copy of C/BE[3-0]" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000c8 line.long 0. "0xC8 ERRADR,Processor/PCI error address register" tree.end TREE "Address Map B Option Register" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000E0 line.byte 0 "0xE0 AMBOR , Address Map B Option Register" bitfld.byte 0 7. " CPU_FD_ALIAS_EN ,Used to direct proc. accesses to addresses that begin with 0xFDxx_xxxx" "0,1" textline " " bitfld.byte 0 6. " PCI_FD_ALIAS_EN ,Used to direct proc. responses to addresses that begin with 0xFDxx_xxxx" "0,1" textline " " bitfld.byte 0 3. " PCI_COMPATIBILIY_HOLE ,Used only for address map B and not supported in agent mode" "0,1" textline " " bitfld.byte 0 2. " PROC_COMPATIBILITY_HOLE ,Used only for address map B and not supported in agent mode" "0,1" tree.end tree "Memory Control Configuration Registers" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000F0 line.long 0 "0xF0 MCCR1,Memory Control Configuration Register 1" hexmask.long.byte 0. 28.--31. 1. 0. " ROMNAL ,Controls next access time(SDRAM) and measure the write pulse recovery (high) time (FLASH)" hexmask.long.byte 0. 23.--27. 1. 0. " ROMFAL ,Controls first access time(SDRAM) and measure the write pulse (low) time (FLASH)" bitfld.long 0. 21.--22. " DBUS_SIZE[0-1] ,State of the ROM bank 0 data path width configuration signals DL[0],FOE" "32,8,64,8/64" textline " " bitfld.long 0. 20. " BURST ,Burst mode ROM timing enable" "standard,burst" bitfld.long 0. 19. " MEMGO ,RAM interface logic enable." "0,1" bitfld.long 0. 18. " SREN ,Self-refresh-enable" "0,1" bitfld.long 0. 17. " RAM_TYPE ,RAM Type" "SDRAM,DRAM/EDO" textline " " bitfld.long 0. 16. " PCKEN ,Memory interface parity checking/generation enable" "0,1" textline " " bitfld.long 0. 14.--15. " BANK_7 ,RAM bank 7 row address bit count." "9,10,11,12/13" bitfld.long 0. 12.--13. " BANK_6 ,RAM bank 6 row address bit count." "9,10,11,12/13" bitfld.long 0. 10.--11. " BANK_5 ,RAM bank 5 row address bit count." "9,10,11,12/13" bitfld.long 0. 08.--09. " BANK_4 ,RAM bank 4 row address bit count." "9,10,11,12/13" textline " " bitfld.long 0. 06.--07. " BANK_3 ,RAM bank 3 row address bit count." "9,10,11,12/13" bitfld.long 0. 04.--05. " BANK_2 ,RAM bank 2 row address bit count." "9,10,11,12/13" bitfld.long 0. 02.--03. " BANK_1 ,RAM bank 1 row address bit count." "9,10,11,12/13" bitfld.long 0. 00.--01. " BANK_0 ,RAM bank 0 row address bit count." "9,10,11,12/13" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000F4 line.long 0. "0xF4 MCCR2,Memory Control Configuration Register 2" bitfld.long 0. 29.--31. " TS_WAIT_TIMER ,Transaction start wait states timer" "0,1,2,3,4,5,6,7" bitfld.long 0. 25.--28. " ASRISE ,AS rise time" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 21.--24. " ASFALL ,AS fall time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0. 20. " INL_PAR_NOT_ECC ,Inline parity - not ECC." "0,1" bitfld.long 0. 19. " INLINE_WR_EN ,In-line parity error reporting enable" "0,1" bitfld.long 0. 18. " INLINE_RD_ EN ,In-line read parity or ECC check/correction enable" "0,1" textline " " bitfld.long 0. 17. " ECC_EN ,ECC enable" "0,1" bitfld.long 0. 16. " EDO ,EDO enable" "0,1" textline " " hexmask.long.word 0. 02.--15. 1. 0. " REFINT ,Refresh interval" textline " " bitfld.long 0. 01. " RSV_PG ,Reserve page register" "0,1" bitfld.long 0. 00. " RMW_PAR ,Read-modify-write (RMW) parity enable" "0,1" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000F8 line.long 0. "0xF8 MCCR3,Memory Control Configuration Register 3" hexmask.long.byte 0. 28.--31. 1. 0. " BSTOPRE[2-5] ,Burst to precharge. SDRAM only" bitfld.long 0. 24.--27. " REFREC ,Refresh to activate interval." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 20.--23. " RDLAT ,Data latency from read command." "res,1,2,3,4,5,6,res,res,res,res,res,res,res,res,res" textline " " bitfld.long 0. 19. " CPX ,CAS write timing modifier. For DRAM/EDO only." "unmodified,modified" textline " " bitfld.long 0. 15.--18. " RAS_6P ,RAS assertion interval for CBR refresh." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 12.--14. " CAS_5 ,CAS assertion interval for page mode access." "8,1,2,3,4,5,6,7" bitfld.long 0. 09.--11. " CP ,CAS precharge interaval. For DRAM/EDO only." "res,1,2,res,res,res,res,res" textline " " bitfld.long 0. 06.--08. " CAS_3 ,CAS assertion interval for the first access." "8,1,2,3,4,5,6,7" bitfld.long 0. 03.--05. " RCD_2 ,RAS to CAS delay interval." "8,res,2,3,4,5,6,7" bitfld.long 0. 00.--02. " RP_1 ,RAS precharge interval. For DRAM/EDO only." "res,res,2,3,4,5,res,res" textline "" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x800000FC line.long 0 "MCCR4, Memory Control Configuration Register 4" bitfld.long 0. 28.--31. " PRETOACT ,Precharge to activate interval. For SDRAM only." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 24.--27. " ACTOPRE ,Activate to precharge interval. For SDRAM only." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 23. " WMODE ,Length of burst for 32-bit data." "4,8" textline " " bitfld.long 0. 20. 22. " BUF_TYPE[0-1] ,internal memory datapath buffering scheme" "res,registered buffer,inline buffer,res" textline " " bitfld.long 0. 21. " EXTROM ,Extended ROM space enable" "0,1" bitfld.long 0. 18.--19. " BSTOPRE[0-1] ,Burst to precharge. For SDRAM only." "00,01,10,11" bitfld.long 0. 15. " REGDIMM ,Registered DIMMs." "Normal,Registered" textline " " bitfld.long 0. 12.--14. " DBUS_SIZE[2] ," "0,1" bitfld.long 0. 11. " SDMODE_WRAP ,Wrap type. For SDRAM only." "Sequential,Interleaved" bitfld.long 0. 08.--10. " SDMODE_BURST ,Burst length. For SDRAM only." "res,res,4,8,res,res,res,res" textline " " bitfld.long 0. 04.--07. " ACTORW ,Activate to read/write interval. For SDRAM only." "16,res,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 00.--03. " BSTOPRE[6-9] ,Burst to precharge. For SDRAM only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end TREE "Address Translation (only supported in agent mode)" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80002300 line.long 0 "0x2300 OMBAR ,Outbound Translation Window Register" hexmask.long 0. 12.--30. 1000 0. " OMBA ,Outbound Memory Base Address" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80002308 line.long 0 "0x2308 OTWR ,Outbound Translation Window Register" hexmask.long 0. 12.--31. 0x1000 0. " OTBA ,Outbound Translation Base Address" bitfld.long 0. 0.--4. " Size ,Inbound Window Size" "Disabled,00001 (res),00010 (res),00011 (res),00100 (res),00101 (res),00110 (res),00111 (res),01000 (res),01001 (res),01010 (res),01011 (4K (2^12)),01100 (8K (2^13)),01101 (16K (2^14)),01110 (32K (2^15)),01111 (64K (2^16)),10000 (128K (2^17)),10001 (256K (2^18)),10010 (512K (2^19)),10011 (1M (2^20)),10100 (2M (2^21)),10101 (4M (2^22)),10110 (8M (2^23)),10111 (16M (2^24)),11000 (32M (2^25)),11001 (64M (2^26)),11010 (128M (2^27)),11011 (256M (2^28)),11100 (512M (2^29)),11101 (1G (2^30)),11110 (res),11111 (res)" group.long ANC:0xFEE00000++3 saveout ANC:0xFEC00000 %Long %LE 0x80002310 line.long 0 "0x2310 ITWR,Inbound Translation Window Register " hexmask.long 0. 12.--31. 0x1000 0. " ITBA ,Inbound Translation Base Address" bitfld.long 0. 0.--4. " Size ,Inbound Window Size" "Disabled,00001 (res),00010 (res),00011 (res),00100 (res),00101 (res),00110 (res),00111 (res),01000 (res),01001 (res),01010 (res),01011 (4K (2^12)),01100 (8K (2^13)),01101 (16K (2^14)),01110 (32K (2^15)),01111 (64K (2^16)),10000 (128K (2^17)),10001 (256K (2^18)),10010 (512K (2^19)),10011 (1M (2^20)),10100 (2M (2^21)),10101 (4M (2^22)),10110 (8M (2^23)),10111 (16M (2^24)),11000 (32M (2^25)),11001 (64M (2^26)),11010 (128M (2^27)),11011 (256M (2^28)),11100 (512M (2^29)),11101 (1G (2^30)),11110 (res),11111 (res)" tree.end tree "EUMB Interface" group.long ANC:0xFEE00000++3 SAVEOUT ANC:0xFEC00000 %l 0x80000078 LINE.LONG 0 "0x78 EUMBBAR, Embedded Utilities Memory Block Base Adress Register" HEXMASK.LONG 0. 20.--31. 0x100000 0. "ADDR ,Base address. Block size 1MB." TEXTLINE " Valid address: 0x80000000 <= ADDR <=0xFDF00000" BASESAVEOUT ANC:Data.Long.LE(ANC:0xFEE00000) ANC:0xFEC00000 %Long %LE 0x80000078 tree "Message Unit (I2O)" group 0x50++0x0f "Message Registers" line.long 0x0 "IMR0,Inbound Message Register 0" line.long 0x4 "IMR1,Inbound Message Register 1" line.long 0x8 "OMR0,Outbound Message Register 0" line.long 0x0c "OMR1,Outbound Message Register 1" group 0x60++0x03 "Door Bell Registers" line.long 0x0 "ODBR,Outbound Door Bell Register" group 0x68++0x03 line.long 0x0 "IDBR,Inbound Door Bell Register" group 0x100++0x07 "I2O Registers" line.long 0x0 "IMISR,Inbound Message Interrupt Status Register" line.long 0x4 "IMIMR,Inbound Message Interrupt Mask Register" group 0x120++0x03 line.long 0x0 "IFHPR,Inbound Free_FIFO Head Pointer Register" group 0x128++0x03 line.long 0x0 "IFTPR,Inbound Free_FIFO Tail Pointer Register" group 0x130++0x03 line.long 0x0 "IPHPR,Inbound Post_FIFO Head Pointer Register" group 0x138++0x03 line.long 0x0 "IPTPR,Inbound Post_FIFO Tail Pointer Register" group 0x140++0x03 line.long 0x0 "OFHPR,Outbound Free_FIFO Head Pointer Register" group 0x148++0x03 line.long 0x0 "OFTPR,Outbound Free_FIFO Tail Pointer Register" group 0x150++0x03 line.long 0x0 "OPHPR,Outbound Post_FIFO Head Pointer Register" group 0x158++0x03 line.long 0x0 "OPTPR,Outbound Post_FIFO Tail Pointer Register" group 0x164++0x03 line.long 0x0 "MUCR,Message Unit Control Register" group 0x170++0x03 line.long 0x0 "QBAR,Queue Base Address Register" tree.end tree "DMA Controller" group 0x1100++0x27 "Channel 0" line.long 0x0 "MR,Mode Register" bitfld.long 0x0 19. "IRQS ,Interrupt Steer" "no,yes" bitfld.long 0x0 18. " PDE ,Periodic DMA Enable" "no,yes" bitfld.long 0x0 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1b,2b,4b,8b" bitfld.long 0x0 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1b,2b,4b,8b" bitfld.long 0x0 13. " DAHE ,Destination Address Hold Enable" "no,yes" bitfld.long 0x0 12. " SAHE ,Source Address Hold Enable" "no,yes" textline " " bitfld.long 0x0 10.--11. " PRC ,PCI Read Command" "read,read line,read multiple,res" bitfld.long 0x0 8. " EIE ,Error Interrupt Enable" "no,yes" bitfld.long 0x0 7. " EOTIE ,End-Of-Transfer Interrupt Enable" "no,yes" bitfld.long 0x0 3. " DL ,Descriptor Location" "lcl,pci" bitfld.long 0x0 2. " CDM ,Channel Transfer Mode" "chaining,direct" bitfld.long 0x0 1. " CC ,Channel Continue" "no,yes" bitfld.long 0x0 0. " CS ,Channel Start" "no,yes" line.long 0x4 "SR,Status Register" eventfld.long 0x4 7. "LME ,Local Memory Error" "no,yes" eventfld.long 0x4 18. " PE ,PCI Error" "no,yes" bitfld.long 0x4 2. " CB ,Channel Busy" "no,yes" eventfld.long 0x4 1. " EOSI ,End-Of-Segment Interrupt" "no,yes" eventfld.long 0x4 0. " EOCAI ,End-Of-Chain/direct Interrupt" "no,yes" line.long 0x8 "CDAR,Current Descriptor Address Register" bitfld.long 0x8 4. "SNEN ,Snoop Enable" "no,yes" bitfld.long 0x8 3. " EOSIE ,End-of-Segment Interrupt Enable" "no,yes" bitfld.long 0x8 0x1--2. " CTT ,Channel Transfer Type" "lcl-lcl,lcl-pci,pci-lcl,pci-pci" line.long 0x10 "SAR,Source Address Register" line.long 0x18 "DAR,Destination Address Register" line.long 0x20 "BCR,Byte Count Register" line.long 0x24 "NDAR,Next Descriptor Address Register" bitfld.long 0x8 4. "NDSNEN ,Next Descriptor Snoop Enable" "no,yes" bitfld.long 0x8 3. " NDEOSIE ,Next Descriptor End-of-Segment Interrupt Enable" "no,yes" bitfld.long 0x8 0x1--2. " NDCTT ,Next Descriptor Channel Transfer Type" "lcl-lcl,lcl-pci,pci-lcl,pci-pci" group 0x1200++0x27 "Channel 1" copy tree.end tree "I2C Controller" group 0x3000++0x13 line.long 0x0 "I2CADR,I2C Address Register" line.long 0x4 "I2CFDR,I2C Frequency Divider Register" line.long 0x8 "I2CCR,I2C Control Register" bitfld.long 0x8 7. "MEN ,Module Enable" "no,yes" bitfld.long 0x8 6. " MIEN ,Module Interrupt Enable" "no,yes" bitfld.long 0x8 5. " MSTA ,Master/Slave Mode Select" "slave,master" bitfld.long 0x8 4. " MTX ,Transmit/Receive Mode Select" "receive,transmit" bitfld.long 0x8 3. " TXAK ,Transfer Acknowledge Enable" "no,yes" bitfld.long 0x8 2. " RSTA ,Repeat Start" "no,yes" line.long 0x0c "I2CSR,I2C Status Register" bitfld.long 0x0c 7. "MCF ,Data Transferring" "no,yes" bitfld.long 0x0c 6. " MAAS ,Addressed as a Slave" "no,yes" bitfld.long 0x0c 5. " MBB ,Bus Busy" "no,yes" bitfld.long 0x0c 4. " MAL ,Arbitration Lost" "no,yes" bitfld.long 0x0c 2. " SRW ,Slave Read/Write" "receive,transmit" bitfld.long 0x0c 1. " MIF ,Module Interrupt" "no,yes" bitfld.long 0x0c 0. " RXAK ,Received Acknownledge" "yes,no" line.long 0x10 "I2CDR,I2C Data Register" tree.end tree "Embedded Programmable Interrupt Controller" width 7. group 0x41000++0x03 "Global EPIC Registers" line.long 0x00 "FRR,Feature Reporting Register" hexmask.long.word 0x00 16.--26. 1. " NIRQ ,Number of interrupts" bitfld.long 0x00 8.--12. " NCPU ,Number of CPUs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " VID ,Version ID for this interrupt controller" group 0x41020++0x13 line.long 0x00 "GCR,Global Configuration Register" bitfld.long 0x00 31. " R ,Reset EPIC unit" "No reset,Reset" bitfld.long 0x00 29. " M ,Mode" "Pass-through,Mixed" line.long 0x10 "EICR,EPIC Interrupt Configuration Register" bitfld.long 0x10 28.--30. " R ,Clock ratio" "Reserved,2,4,6,8,10,12,14" bitfld.long 0x10 27. " SIE ,Serial interrupt enable" "Direct,Serial" group 0x41080++0x13 line.long 0x00 "EVI,EPIC Vendor Identification Register" hexmask.long.byte 0x00 16.--23. 1. " STEP ,Stepping" hexmask.long.byte 0x00 8.--15. 1. " DEVICE_ID ,Device identification" hexmask.long.byte 0x00 0.--7. 1. " VENDOR_ID ,Vendor identification" line.long 0x10 "PI,Processor Initialization Register" bitfld.long 0x10 0. " P0 ,Processor 0 soft reset" "No reset,Reset" group 0x410e0++0x03 line.long 0x00 "SVR,Spurious Vector Register" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Spurious interrupt vector" tree "Global Timer Registers" group 0x410f0++0x03 line.long 0x00 "TFRR,Timer Frequency Reporting Register" hexmask.long 0x00 0.--31. 1. " TIMER_FREQ ,Timer Frequency Reporting Register" group 0x41100++0x23 "Timer 0" line.long 0x00 "GTCCR0,Global Timer 0 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR0,Global Timer 0 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR0,Global Timer 0 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41100+0x30)++0x03 line.long 0x00 "GTDR0,Global Timer 0 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x41140++0x23 "Timer 1" line.long 0x00 "GTCCR1,Global Timer 1 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR1,Global Timer 1 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR1,Global Timer 1 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41140+0x30)++0x03 line.long 0x00 "GTDR1,Global Timer 1 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x41180++0x23 "Timer 2" line.long 0x00 "GTCCR2,Global Timer 2 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR2,Global Timer 2 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR2,Global Timer 2 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41180+0x30)++0x03 line.long 0x00 "GTDR2,Global Timer 2 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x411C0++0x23 "Timer 3" line.long 0x00 "GTCCR3,Global Timer 3 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR3,Global Timer 3 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR3,Global Timer 3 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x411C0+0x30)++0x03 line.long 0x00 "GTDR3,Global Timer 3 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Internal Interrupt Registers" group 0x50200++0x03 line.long 0x00 "IVPR0,Direct Interrupt Vector/Priority Register 0" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50220++0x03 line.long 0x00 "IVPR1,Direct Interrupt Vector/Priority Register 1" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50240++0x03 line.long 0x00 "IVPR2,Direct Interrupt Vector/Priority Register 2" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50260++0x03 line.long 0x00 "IVPR3,Direct Interrupt Vector/Priority Register 3" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50280++0x03 line.long 0x00 "IVPR4,Direct Interrupt Vector/Priority Register 4" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup 0x50210++0x03 line.long 0x00 "IDR0,Direct Interrupt Destination Register 0" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50230++0x03 line.long 0x00 "IDR1,Direct Interrupt Destination Register 1" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50250++0x03 line.long 0x00 "IDR2,Direct Interrupt Destination Register 2" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50270++0x03 line.long 0x00 "IDR3,Direct Interrupt Destination Register 3" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50290++0x03 line.long 0x00 "IDR4,Direct Interrupt Destination Register 4" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Serial Interrupt Registers" group 0x50200++0x03 line.long 0x00 "SVPR0,Serial Interrupt Vetor/Priority Register 0" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50220++0x03 line.long 0x00 "SVPR1,Serial Interrupt Vetor/Priority Register 1" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50240++0x03 line.long 0x00 "SVPR2,Serial Interrupt Vetor/Priority Register 2" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50260++0x03 line.long 0x00 "SVPR3,Serial Interrupt Vetor/Priority Register 3" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50280++0x03 line.long 0x00 "SVPR4,Serial Interrupt Vetor/Priority Register 4" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502A0++0x03 line.long 0x00 "SVPR5,Serial Interrupt Vetor/Priority Register 5" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502C0++0x03 line.long 0x00 "SVPR6,Serial Interrupt Vetor/Priority Register 6" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502E0++0x03 line.long 0x00 "SVPR7,Serial Interrupt Vetor/Priority Register 7" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50300++0x03 line.long 0x00 "SVPR8,Serial Interrupt Vetor/Priority Register 8" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50320++0x03 line.long 0x00 "SVPR9,Serial Interrupt Vetor/Priority Register 9" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50340++0x03 line.long 0x00 "SVPR10,Serial Interrupt Vetor/Priority Register 10" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50360++0x03 line.long 0x00 "SVPR11,Serial Interrupt Vetor/Priority Register 11" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50380++0x03 line.long 0x00 "SVPR12,Serial Interrupt Vetor/Priority Register 12" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503A0++0x03 line.long 0x00 "SVPR13,Serial Interrupt Vetor/Priority Register 13" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503C0++0x03 line.long 0x00 "SVPR14,Serial Interrupt Vetor/Priority Register 14" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503E0++0x03 line.long 0x00 "SVPR15,Serial Interrupt Vetor/Priority Register 15" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup 0x50210++0x03 line.long 0x00 "SDR0,Serial Interrupt Destination Register 0" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50230++0x03 line.long 0x00 "SDR1,Serial Interrupt Destination Register 1" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50250++0x03 line.long 0x00 "SDR2,Serial Interrupt Destination Register 2" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50270++0x03 line.long 0x00 "SDR3,Serial Interrupt Destination Register 3" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50290++0x03 line.long 0x00 "SDR4,Serial Interrupt Destination Register 4" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502B0++0x03 line.long 0x00 "SDR5,Serial Interrupt Destination Register 5" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502D0++0x03 line.long 0x00 "SDR6,Serial Interrupt Destination Register 6" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502F0++0x03 line.long 0x00 "SDR7,Serial Interrupt Destination Register 7" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50310++0x03 line.long 0x00 "SDR8,Serial Interrupt Destination Register 8" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50330++0x03 line.long 0x00 "SDR9,Serial Interrupt Destination Register 9" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50350++0x03 line.long 0x00 "SDR10,Serial Interrupt Destination Register 10" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50370++0x03 line.long 0x00 "SDR11,Serial Interrupt Destination Register 11" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50390++0x03 line.long 0x00 "SDR12,Serial Interrupt Destination Register 12" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503B0++0x03 line.long 0x00 "SDR13,Serial Interrupt Destination Register 13" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503D0++0x03 line.long 0x00 "SDR14,Serial Interrupt Destination Register 14" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503F0++0x03 line.long 0x00 "SDR15,Serial Interrupt Destination Register 15" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Onchip Module Interrupt Registers (I2C, DMA, MU)" rgroup 0x51020++0x03 line.long 0x00 "IIVPR0,I2C Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51020+0x10)++0x03 line.long 0x00 "IIDR0,I2C Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x51040++0x03 line.long 0x00 "IIVPR1,DMA Ch0 Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51040+0x10)++0x03 line.long 0x00 "IIDR1,DMA Ch0 Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x51060++0x03 line.long 0x00 "IIVPR2,DMA Ch1 Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51060+0x10)++0x03 line.long 0x00 "IIDR2,DMA Ch1 Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x510c0++0x03 line.long 0x00 "IIVPR3,Message Unit Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x510c0+0x10)++0x03 line.long 0x00 "IIDR3,Message Unit Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Processor-Related Registers" group 0x60080++0x03 line.long 0x00 "PCTPR,Processor Current Task Priority Register" bitfld.long 0x00 0.--3. " TASKP ,Task priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup 0x600a0++0x03 line.long 0x00 "IACK,Processor Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Interrupt vector" wgroup 0x600b0++0x03 line.long 0x00 "EOI,Processor End-of-Interrupt Register" bitfld.long 0x00 0.--3. " EOI_CODE ," "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f" tree.end tree.end tree.end tree.end tree "MPC107 Registers (Address Map A)" config 16. 8. width 16. endian.le tree "PCI Configuration Space Header" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000000 line.word 0. "0x00 VENDOR,Vendor ID" line.word 2. "0x02 ID,Device ID" group.word ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000004 line.word 0. "0x04 PCICMD,PCI command register" bitfld.word 0. 9. " FBTB ,Fast back-to-back" "0,1" bitfld.word 0. 8. " SERR ,Enables the SERR driver" "0,1" bitfld.word 0. 6. " PERR ,Parity error response" "0,1" bitfld.word 0. 4. " MWAI ,Memory-write-and-invalidate" "0,1" textline " " bitfld.word 0. 3. " SC ,Special cycles" "0,1" bitfld.word 0. 2. " BM ,Bus master" "0,1" bitfld.word 0. 1. " MS ,Memory space" "0,1" bitfld.word 0. 0. " IO ,I/O space" "0,1" line.word 2. "0x06 PCISTAT,PCI status register" bitfld.word 2. 15. " DPE ,Detected Parity Error" "0,1" bitfld.word 2. 14. " SSE ,Signal SystemError" "0,1" bitfld.word 2. 13. " RMA ,Received Master-Abort" "0,1" bitfld.word 2. 12. " RTA ,Received Target-Abort" "0,1" textline " " bitfld.word 2. 11. " STA ,Signaled Target-Abort" "0,1" bitfld.word 2. 9.--10. " DEVSEL ,Device Select Timing" "0,1" bitfld.word 2. 08. " DPD ,Data Parity Detected" "0,1" bitfld.word 2. 07. " FB2BC ,Fast Back-to-Back Capable" "0,1" bitfld.word 2. 05. " 66 ,66-MHz Capable" "0,1" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000008 line.byte 0. "0x08 REVID,Revision ID" line.byte 1. "0x09 SPI,Standard programming interface" line.byte 2. "0x0A SUBCCODE,Subclass code" line.byte 3. "0x0B CCODE,Base class code" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x8000000C line.byte 0. "0x0C CACHESIZ,Cache Line Size" line.byte 1. "0x0D LATTIMER,Latency Timer" line.byte 2. "0x0E HEADTYPE,Header Type" line.byte 3. "0x0F BISTCTRL,BIST Control" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000010 line.long 0. "0x10 LMBAR,Local Memory Base Address Register (reserved in the MPC107)" hexmask.long 0. 12.--31. 0x1000 0. " IMBA ,Inbound memory base address" bitfld.long 0. 03.--03. " Pre ,space is prefetchable" "0,1" bitfld.long 0. 01.--02. " TYPE ,inbound memory window may be located within the PCI address space" "00,01,10,11" bitfld.long 0. 00.--00. " MSI ,Memory space indicator" "0,1" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000014 line.long 0. "0x14 PCSRBAR,Peripheral Control and Status Base Address Register" hexmask.long 0. 12.--31. 0x1000 0. " ADDR ,PCI base address mapped to the runtime register (DMA,I2O,...)" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x8000003C line.byte 0. "0x3C ILR,Interrupt Line" line.byte 1. "0x3D INTPIN,Interrupt Pin" line.byte 2. "0x3E MIN_GNT,Specifies the length of the device's burst period" line.byte 3. "0x3F MAX_LAT,Specifies how often the device needs to gain access to the PCI bus" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000040 line.byte 0. "0x40 BUSNB,Bus number" line.byte 1. "0x41 SBUSNB,Subordinate bus number" group.word ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000044 line.word 2. "0x46 PCIARB,PCI Arbiter Control Register" bitfld.word 2. 15. " EPCI ,Enable internal PCI arbitration" "0,1" bitfld.word 2. 13.--14. " PM ,Parking mode control" "last device use bus,device using REQ0/GNT0,MPC107,res" bitfld.word 2. 10. " RPCC ,Retry PCI configuration cycle" "respond,retries all" bitfld.word 2. 07. " PL ,MPC107 priority level" "low,high" hexmask.word 2. 00.--04. 1. 0. " EDPL ,External device priority levels" tree.end tree "Peripheral Logic Power Management / Output/Clock Driver / Misc I/O" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000070 line.word 0. "0x70 PMCR1, Power Management Configuration Register 1" bitfld.word 0. 15. " NO_NAP_MSG ,HALT command broadcast not supported on the MPC107" "0,1" bitfld.word 0. 14. " NO_SLEEP_MSG ,Sleep message broadcast. Not supported on the MPC107" "0,1" bitfld.word 0. 12. " LP_REF_EN ,Low-power refresh" "0,1" textline " " bitfld.word 0. 07. " PM ,Power management enable" "0,1" bitfld.word 0. 05. " DOZE ,Ena/dis the DOZE mode capability. Only valid if PMCR1[PM]=1." "0,1" bitfld.word 0. 04. " NAP ,Ena/dis the NAP mode capability. Only valid if PMCR1[PM]=1." "0,1" bitfld.word 0. 03. " SLEEP ,Ena/dis the SLEEP mode capability. Only valid if PMCR1[PM]=1." "0,1" textline " " bitfld.word 0. 01--02 " CKO_MODE ,Selects the clock source for the test clock output when CKO_SEL = 1" "dis, internal sys_logic-clk,one-half of the PCI rate clock,internal PCI rate clock" textline " " bitfld.word 0. 00. " CKO_SEL ,output for the CKO signal" "core clock,system logic clock" line.byte 2. "0x72 PMCR2, Power Management Configuration Register 2" bitfld.byte 2. 07. " DLL_EXTEND ,used to shift the lock-range of the DLL by half of a PCI clock cycle" "0,1" bitfld.byte 2. 04--06 " PCI_HOLD_DEL ,PCI output hold delay value relative to the PCI_SYNC_IN signal." "000(66MHz),001,010,011,100(33MHz),101,110(def),111" bitfld.word 2. 02. " PLL_SLEEP ,Power management enable" "0,1" line.byte 3. "0x73 ODCR,Output Driver Control Register" bitfld.byte 3. 07. " DRV_PCI ,Driver capability for PCI and EPIC" "25 Ohm,50 Ohm " textline " " bitfld.byte 3. 06. " DRV_STD ,Driver capability for standard signals" "20 Ohm,40 Ohm " textline " " bitfld.byte 3. 04.--05. " DRV_MEM_CTRL ,Driver capability for address signals" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.byte 3. 02.--03. " DRV_PCI_CLK ,Driver capability. Control drive strength of PCI_CLK, PCI_CLK_SYNC_OUT" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.byte 3. 00.--01. " DRV_MEM_CLK ,Driver capability. Control drive strength of SDRAM_CLK, SDRAM_SYNC_OUT" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000074 line.word 0 "0x74 CLKDCR,CLK Driver Control Register" bitfld.word 0. 15. " PCI_SYNC_OUT ,disables the PCI_CLK_SYNC_OUT signal" "0,1" textline " " bitfld.word 0. 14. " PCI_CLK0_DIS ,disables the PCI_CLK0 output" "0,1" bitfld.word 0. 13. " PCI_CLK1_DIS ,disables the PCI_CLK1 output" "0,1" bitfld.word 0. 12. " PCI_CLK2_DIS ,disables the PCI_CLK2 output" "0,1" textline " " bitfld.word 0. 11. " PCI_CLK3_DIS ,disables the PCI_CLK3 output" "0,1" bitfld.word 0. 10. " PCI_CLK4_DIS ,disables the PCI_CLK4 output" "0,1" textline " " bitfld.word 0. 8.--9. " DRV_CPU_CLK ,Driver capability for the CPU_CLK[0:2]" "8 Ohm,13.3 Ohm,20 Ohm,40 Ohm" textline " " bitfld.word 0. 07. " SDRAM_SYNC_OUT ,disables the SDRAM_SYNC_OUT output" "0,1" textline " " bitfld.word 0. 06. " SDRAM_CLK0_DIS ,SDRAM_CLK0 output" "0,1" bitfld.word 0. 05. " SDRAM_CLK1_DIS ,SDRAM_CLK1 output" "0,1" textline " " bitfld.word 0. 04. " SDRAM_CLK2_DIS ,SDRAM_CLK2 output" "0,1" bitfld.word 0. 03. " SDRAM_CLK3_DIS ,SDRAM_CLK3 output" "0,1" textline " " bitfld.word 0. 02. " CPU_CLK0_DIS ,disables the CPU_CLK0_DIS output" "0,1" bitfld.word 0. 01. " CPU_CLK1_DIS ,disables the CPU_CLK1_DIS output" "0,1" bitfld.word 0. 00. " CPU_CLK2_DIS ,disables the CPU_CLK2_DIS output" "0,1" line.byte 2. "0x76 MDCR" bitfld.byte 2. 07. " MCP_OD_MODE ,MCP output open-drain" "0,1" bitfld.byte 2. 06. " SRESET_OD_MODE ,SRESET output open-drain" "0,1" bitfld.byte 2. 05. " NO_HI-Z_QACK ,always drive QACK" "0,1" tree.end tree "Memory Interface Configuration Register" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000080 line.long 0. "0x80 MSAR1,Memory Starting Address Register 1" hexmask.byte.long 0. 0.--7. 0x1000000 0. " Start Address 0 ,Starting address bank 0" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0. " Start Address 1 ,Starting address bank 1" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0. " Start Address 2 ,Starting address bank 2" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0. " Start Address 3 ,Starting address bank 3" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000084 line.long 0 "0x84 MSAR2 ,Memory Starting Address Register 2" hexmask.byte.long 0. 0.--7. 0x1000000 0. " Start Address 4 ,Starting address bank 4" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0. " Start Address 5 ,Starting address bank 5" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0. " Start Address 6 ,Starting address bank 6" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0. " Start Address 7 ,Starting address bank 7" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000088 line.long 0 "0x88 EMSAR1 ,Extended Memory Starting Address Register 1" bitfld.byte 0. 00.--01. " Ext. Start address 0 ,Ext. Starting address bank 0" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. Start address 1 ,Ext. Starting address bank 1" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. Start address 2 ,Ext. Starting address bank 2" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. Start address 3 ,Ext. Starting address bank 3" "0,1,2,3" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x8000008C line.long 0 "0x8C EMSAR2 ,Extended Memory Starting Address Register 2" bitfld.byte 0. 00.--01. " Ext. Start address 4 ,Ext. Starting address bank 4" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. Start address 5 ,Ext. Starting address bank 5" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. Start address 6 ,Ext. Starting address bank 6" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. Start address 7 ,Ext. Starting address bank 7" "0,1,2,3" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000090 line.long 0 "0x90 MEAR1 ,Memory Ending Address Register 1" hexmask.byte.long 0. 0.--7. 0x1000000 0xFFFFFF " End Address 0 ,Ending address bank 1" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0xFFFFFF " End Address 1 ,Ending address bank 1" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0xFFFFFF " End Address 2 ,Ending address bank 2" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0xFFFFFF " End Address 3 ,Ending address bank 3" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000094 line.long 0 "0x94 MEAR2 ,Memory Ending Address Register 2" hexmask.byte.long 0. 0.--7. 0x1000000 0xFFFFFF " End Address 4 ,Ending address bank 4" textline " " hexmask.byte.long 1. 0.--7. 0x1000000 0xFFFFFF " End Address 5 ,Ending address bank 5" textline " " hexmask.byte.long 2. 0.--7. 0x1000000 0xFFFFFF " End Address 6 ,Ending address bank 6" textline " " hexmask.byte.long 3. 0.--7. 0x1000000 0xFFFFFF " End Address 7 ,Ending address bank 7" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80000098 line.long 0 "0x98 EMEAR1 ,Extended Memory Ending Address Register 1" bitfld.byte 0. 00.--01. " Ext. End Address 0 ,Ext. Ending address bank 0" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. End Address 1 ,Ext. Ending address bank 1" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. End Address 2 ,Ext. Ending address bank 2" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. End Address 3 ,Ext. Ending address bank 3" "0,1,2,3" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x8000009C line.long 0 "0x9C EMEAR2 ,Extended Memory Ending Address Register 2" bitfld.byte 0. 00.--01. " Ext. End Address 4 ,Ext. Ending address bank 4" "0,1,2,3" textline " " bitfld.byte 1. 00.--01. " Ext. End Address 5 ,Ext. Ending address bank 5" "0,1,2,3" textline " " bitfld.byte 2. 00.--01. " Ext. End Address 6 ,Ext. Ending address bank 6" "0,1,2,3" textline " " bitfld.byte 3. 00.--01. " Ext. End Address 7 ,Ext. Ending address bank 7" "0,1,2,3" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000A0 line.byte 0 "0xA0 MBNKEN,Memory Bank Enable Register" bitfld.byte 0. 7. " B7 ,Bank7" "0,1" bitfld.byte 0. 6. " B6 ,Bank6" "0,1" bitfld.byte 0. 5. " B5 ,Bank5" "0,1" bitfld.byte 0. 4. " B4 ,Bank4" "0,1" textline " " bitfld.byte 0. 3. " B3 ,Bank3" "0,1" bitfld.byte 0. 2. " B2 ,Bank2" "0,1" bitfld.byte 0. 1. " B1 ,Bank1" "0,1" bitfld.byte 0. 0. " B0 ,Bank0" "0,1" textline "" line.byte 3 "0xA3 MPMOD ,Memory Page Mode Register" hexmask.byte 3. 0.--7. 1. 0. " PGMAX " tree.end tree "Processor Interface Configuration Register" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000A8 line.long 0 "0xA8 PICR1,Processor Interface Configuration Register 1" bitfld.long 0. 22.--23. " CF_BREAD_WS ,Burst read wait states" "0,1,2,3" bitfld.long 0. 20. " RSC0 ,ROM Location" "PCI,Local Bus" textline " " bitfld.long 0. 17.--18. " PROC_TYPE ,Processor Type" "res,res,603e/7xx/74xx,res" textline " " bitfld.long 0. 16. " ADDR_MAP ,Address Map" "B,A" textline " " bitfld.long 0. 14.--15. " CF_MP_ID ,Multiprocessor identifier" "0,1" bitfld.long 0. 13. " CF_LBA_EN ,Local bus slave access enable" "0,1" textline " " bitfld.long 0. 12. " FLASH_WR_EN ,Flash write enable" "0,1" bitfld.long 0. 11. " MCP_EN ,Machine check enable" "0,1" bitfld.long 0. 10. " TEA_EN ,Assert TEA upon detecting a bus error" "0,1" textline " " bitfld.long 0. 07. " NO_BWIDTH_CK ,flash write not restricted to bus width" "0,1" bitfld.long 0. 06. " ST_GATH_EN ,ena/dis gathering of writes from the proc to PCI memory space" "0,1" bitfld.long 0. 05. " LE_MODE ,MPC107 in little endian mode" "0,1" textline " " bitfld.long 0. 04. " CF_LP_SNOOP ,enable snooping" "0,1" bitfld.long 0. 03. " CF_APARK ,Indicates that the last processor that used the 60x bus is parked" "0,1" bitfld.long 0. 02. " SPCIR ,Speculative PCI reads" "0,1" bitfld.long 0. 00.--01. " CF_MP ,Multiprocessor configuration" "Uniprocessor system,res,res,Multiprocessor system" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000AC line.long 0 "0xAC PICR2, Processor Interface Configuration Register 2" bitfld.long 0. 29. " NO_SER_CFG ,Configuration writes to PCI devices from the processor do not cause serialization" "0,1" bitfld.long 0. 27. " NO_SNOOP_EN ,generates snoop transaction on the peripheral bus for PCI-to-system memory transactions" "0,1" textline " " bitfld.long 0. 26. " CF_FF0_LOCAL ,ROM mapping enable" "0,1" bitfld.long 0. 25. " FLASH_WR_LKO ,Flash write lock-out" "0,1" textline " " bitfld.long 0. 18.--19. " CF_SNOOPS_WS ,Snoop wait states" "0,1,2,3" bitfld.long 0. 9.--10. " CF_LBCLM_WS ,Snoop wait states" "0,1,2,3" bitfld.long 0. 2.--3. " CF_APHASE_WS ,Address phase wait states" "0,1,2,3" tree.end TREE "Error Handling and Exceptions" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000B8 line.byte 0. "0xB8 ECCCNT,ECC Single-Bit error counter" line.byte 1. "0xB9 ECCTRG,ECC Single-Bit Trigger" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000C0 line.byte 0. "0xC0 ERRENR1,Error Enabling Register 1" bitfld.byte 0. 7. " RX_SERR ,Enables the reporting of SERR assertions that occur on the PCI bus two clock cycles after the address phase of transactions where the MPC107 is the initiator" "0,1" bitfld.byte 0. 6. " PCI target PERR ,Enables the reporting of data parity errors on the PCI bus for transactions involving the MPC107 as a target" "0,1" textline " " bitfld.byte 0. 5. " Memory select error ,Enables the reporting of memory select errors that occur on (attempted) accesses to system memory" "0,1" bitfld.byte 0. 4. " Memory refresh overflow ,Enables the reporting of memory refresh overflow errors" "0,1" textline " " bitfld.byte 0. 3. " PCI Master PERR ,Enables the reporting of data parity errors on the PCI bus for transactions involving the MPC107 as a master" "0,1" bitfld.byte 0. 2. " Memory parity/ECC error ,Enables the reporting of system memory read parity errors that occur on accesses to system memory or those that exceed the ECC single-bit error threshold" "0,1" textline " " bitfld.byte 0. 1. " PCI master-abort error ,Enables the reporting of master-abort errors that occur on the PCI bus for transactions involving the MPC107 as a master" "0,1" bitfld.byte 0. 0. " Proc. transaction error ,Enables the reporting of processor transaction errors" "0,1" textline "" line.byte 1. "0xC1 ERRDR1,Error Detection Register 1" bitfld.byte 1. 7. " PCI SERR ,SERR detected" "0,1" bitfld.byte 1. 6. " PCI target PERR ,Detected data parity errors on the PCI bus for transactions involving the MPC107 as a target" "0,1" textline " " bitfld.byte 1. 5. " Memory select error ,Detected memory select errors that occur on (attempted) accesses to system memory" "0,1" bitfld.byte 1. 4. " Memory refresh overflow ,Detected memory refresh overflow errors" "0,1" textline " " bitfld.byte 1. 3. " Processor/PCI cycle ,Error occurred on a PCI-initiated cycle." "0,1" bitfld.byte 1. 2. " Memory parity/ECC error ,Memory read parity error/ECC single-bit error trigger exceeded" "0,1" textline " " bitfld.byte 1. 0.--1. " Unsupp. proc. trans ,Unsupported processor transaction" "0,1,res,res" textline "" line.byte 3. "0xC3 PBESR,Processor Bus Error Status Register" hexmask.byte 3. 3.--7. 1. 0. " TT[0:4] " hexmask.byte 3. 0.--2. 1. 0. " TSIZ[0:2] " textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000C4 line.byte 0. "0xC4 ERRENR2,Error Enabling Register 2" bitfld.byte 0. 7. " PCI addr parity error ,Enables PCI address parity errors" "0,1" bitfld.byte 0. 6. " PCI SERR ,Enables the reporting of SERR assertions that occur on the PCI bus" "0,1" textline " " bitfld.byte 0. 3. " ECC multi-bit error ,Enables the detection of ECC multibit errors" "0,1" bitfld.byte 0. 2. " Proc mem wr parity err ,Enables the detection of processor memory write parity errors" "0,1" textline " " bitfld.byte 0. 1. " PCI rec tgt abort error ,enables the detection of target abort errors received by the PCI interface" "0,1" bitfld.byte 0. 0. " Flash ROM write error ,Enables error on writing protected flash" "0,1" textline "" line.byte 1. "0xC5 ERRDR2, Error detection register 2" bitfld.byte 1. 7. " Invalid error address ,address stored in the processor/PCI error address register is valid" "val,inv" bitfld.byte 1. 6. " PCI SERR ,Detected SERR assertions that occur on the PCI bus" "0,1" textline " " bitfld.byte 1. 3. " ECC multi-bit error ,Detected ECC multibit errors" "0,1" bitfld.byte 1. 2. " Proc mem wr parity err ,Detected processor memory write parity errors" "0,1" textline " " bitfld.byte 1. 1. " PCI rec tgt abort error ,Detected of target abort errors received by the PCI interface" "0,1" bitfld.byte 1. 0. " Flash ROM write error ,Detected writing protected flash" "0,1" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000c4 line.byte 3. "0xC7 PCIBESR, PCI Bus Error Status register" bitfld.byte 3. 4. " MTS ,MPC107 master/target status" "Master,Target" hexmask.byte 3. 0.--2. 1. 0. " C/BE ,copy of C/BE[3-0]" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000c8 line.long 0. "0xC8 ERRADR,Processor/PCI error address register" tree.end TREE "Address Map B Option Register" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000E0 line.byte 0 "0xE0 AMBOR , Address Map B Option Register" bitfld.byte 0 7. " CPU_FD_ALIAS_EN ,Used to direct proc. accesses to addresses that begin with 0xFDxx_xxxx" "0,1" textline " " bitfld.byte 0 6. " PCI_FD_ALIAS_EN ,Used to direct proc. responses to addresses that begin with 0xFDxx_xxxx" "0,1" textline " " bitfld.byte 0 3. " PCI_COMPATIBILIY_HOLE ,Used only for address map B and not supported in agent mode" "0,1" textline " " bitfld.byte 0 2. " PROC_COMPATIBILITY_HOLE ,Used only for address map B and not supported in agent mode" "0,1" tree.end tree "Memory Control Configuration Registers" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000F0 line.long 0 "0xF0 MCCR1,Memory Control Configuration Register 1" hexmask.long.byte 0. 28.--31. 1. 0. " ROMNAL ,Controls next access time(SDRAM) and measure the write pulse recovery (high) time (FLASH)" hexmask.long.byte 0. 23.--27. 1. 0. " ROMFAL ,Controls first access time(SDRAM) and measure the write pulse (low) time (FLASH)" bitfld.long 0. 21.--22. " DBUS_SIZE[0-1] ,State of the ROM bank 0 data path width configuration signals DL[0],FOE" "32,8,64,8/64" textline " " bitfld.long 0. 20. " BURST ,Burst mode ROM timing enable" "standard,burst" bitfld.long 0. 19. " MEMGO ,RAM interface logic enable." "0,1" bitfld.long 0. 18. " SREN ,Self-refresh-enable" "0,1" bitfld.long 0. 17. " RAM_TYPE ,RAM Type" "SDRAM,DRAM/EDO" textline " " bitfld.long 0. 16. " PCKEN ,Memory interface parity checking/generation enable" "0,1" textline " " bitfld.long 0. 14.--15. " BANK_7 ,RAM bank 7 row address bit count." "9,10,11,12/13" bitfld.long 0. 12.--13. " BANK_6 ,RAM bank 6 row address bit count." "9,10,11,12/13" bitfld.long 0. 10.--11. " BANK_5 ,RAM bank 5 row address bit count." "9,10,11,12/13" bitfld.long 0. 08.--09. " BANK_4 ,RAM bank 4 row address bit count." "9,10,11,12/13" textline " " bitfld.long 0. 06.--07. " BANK_3 ,RAM bank 3 row address bit count." "9,10,11,12/13" bitfld.long 0. 04.--05. " BANK_2 ,RAM bank 2 row address bit count." "9,10,11,12/13" bitfld.long 0. 02.--03. " BANK_1 ,RAM bank 1 row address bit count." "9,10,11,12/13" bitfld.long 0. 00.--01. " BANK_0 ,RAM bank 0 row address bit count." "9,10,11,12/13" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000F4 line.long 0. "0xF4 MCCR2,Memory Control Configuration Register 2" bitfld.long 0. 29.--31. " TS_WAIT_TIMER ,Transaction start wait states timer" "0,1,2,3,4,5,6,7" bitfld.long 0. 25.--28. " ASRISE ,AS rise time" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 21.--24. " ASFALL ,AS fall time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0. 20. " INL_PAR_NOT_ECC ,Inline parity - not ECC." "0,1" bitfld.long 0. 19. " INLINE_WR_EN ,In-line parity error reporting enable" "0,1" bitfld.long 0. 18. " INLINE_RD_ EN ,In-line read parity or ECC check/correction enable" "0,1" textline " " bitfld.long 0. 17. " ECC_EN ,ECC enable" "0,1" bitfld.long 0. 16. " EDO ,EDO enable" "0,1" textline " " hexmask.long.word 0. 02.--15. 1. 0. " REFINT ,Refresh interval" textline " " bitfld.long 0. 01. " RSV_PG ,Reserve page register" "0,1" bitfld.long 0. 00. " RMW_PAR ,Read-modify-write (RMW) parity enable" "0,1" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000F8 line.long 0. "0xF8 MCCR3,Memory Control Configuration Register 3" hexmask.long.byte 0. 28.--31. 1. 0. " BSTOPRE[2-5] ,Burst to precharge. SDRAM only" bitfld.long 0. 24.--27. " REFREC ,Refresh to activate interval." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 20.--23. " RDLAT ,Data latency from read command." "res,1,2,3,4,5,6,res,res,res,res,res,res,res,res,res" textline " " bitfld.long 0. 19. " CPX ,CAS write timing modifier. For DRAM/EDO only." "unmodified,modified" textline " " bitfld.long 0. 15.--18. " RAS_6P ,RAS assertion interval for CBR refresh." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 12.--14. " CAS_5 ,CAS assertion interval for page mode access." "8,1,2,3,4,5,6,7" bitfld.long 0. 09.--11. " CP ,CAS precharge interaval. For DRAM/EDO only." "res,1,2,res,res,res,res,res" textline " " bitfld.long 0. 06.--08. " CAS_3 ,CAS assertion interval for the first access." "8,1,2,3,4,5,6,7" bitfld.long 0. 03.--05. " RCD_2 ,RAS to CAS delay interval." "8,res,2,3,4,5,6,7" bitfld.long 0. 00.--02. " RP_1 ,RAS precharge interval. For DRAM/EDO only." "res,res,2,3,4,5,res,res" textline "" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x800000FC line.long 0 "MCCR4, Memory Control Configuration Register 4" bitfld.long 0. 28.--31. " PRETOACT ,Precharge to activate interval. For SDRAM only." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 24.--27. " ACTOPRE ,Activate to precharge interval. For SDRAM only." "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 23. " WMODE ,Length of burst for 32-bit data." "4,8" textline " " bitfld.long 0. 20. 22. " BUF_TYPE[0-1] ,internal memory datapath buffering scheme" "res,registered buffer,inline buffer,res" textline " " bitfld.long 0. 21. " EXTROM ,Extended ROM space enable" "0,1" bitfld.long 0. 18.--19. " BSTOPRE[0-1] ,Burst to precharge. For SDRAM only." "00,01,10,11" bitfld.long 0. 15. " REGDIMM ,Registered DIMMs." "Normal,Registered" textline " " bitfld.long 0. 12.--14. " DBUS_SIZE[2] ," "0,1" bitfld.long 0. 11. " SDMODE_WRAP ,Wrap type. For SDRAM only." "Sequential,Interleaved" bitfld.long 0. 08.--10. " SDMODE_BURST ,Burst length. For SDRAM only." "res,res,4,8,res,res,res,res" textline " " bitfld.long 0. 04.--07. " ACTORW ,Activate to read/write interval. For SDRAM only." "16,res,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0. 00.--03. " BSTOPRE[6-9] ,Burst to precharge. For SDRAM only." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end TREE "Address Translation (only supported in agent mode)" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80002300 line.long 0 "0x2300 OMBAR ,Outbound Translation Window Register" hexmask.long 0. 12.--30. 1000 0. " OMBA ,Outbound Memory Base Address" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80002308 line.long 0 "0x2308 OTWR ,Outbound Translation Window Register" hexmask.long 0. 12.--31. 0x1000 0. " OTBA ,Outbound Translation Base Address" bitfld.long 0. 0.--4. " Size ,Inbound Window Size" "Disabled,00001 (res),00010 (res),00011 (res),00100 (res),00101 (res),00110 (res),00111 (res),01000 (res),01001 (res),01010 (res),01011 (4K (2^12)),01100 (8K (2^13)),01101 (16K (2^14)),01110 (32K (2^15)),01111 (64K (2^16)),10000 (128K (2^17)),10001 (256K (2^18)),10010 (512K (2^19)),10011 (1M (2^20)),10100 (2M (2^21)),10101 (4M (2^22)),10110 (8M (2^23)),10111 (16M (2^24)),11000 (32M (2^25)),11001 (64M (2^26)),11010 (128M (2^27)),11011 (256M (2^28)),11100 (512M (2^29)),11101 (1G (2^30)),11110 (res),11111 (res)" group.long ANC:0x80000CFC++3 saveout ANC:0x80000CF8 %Long %LE 0x80002310 line.long 0 "0x2310 ITWR,Inbound Translation Window Register " hexmask.long 0. 12.--31. 0x1000 0. " ITBA ,Inbound Translation Base Address" bitfld.long 0. 0.--4. " Size ,Inbound Window Size" "Disabled,00001 (res),00010 (res),00011 (res),00100 (res),00101 (res),00110 (res),00111 (res),01000 (res),01001 (res),01010 (res),01011 (4K (2^12)),01100 (8K (2^13)),01101 (16K (2^14)),01110 (32K (2^15)),01111 (64K (2^16)),10000 (128K (2^17)),10001 (256K (2^18)),10010 (512K (2^19)),10011 (1M (2^20)),10100 (2M (2^21)),10101 (4M (2^22)),10110 (8M (2^23)),10111 (16M (2^24)),11000 (32M (2^25)),11001 (64M (2^26)),11010 (128M (2^27)),11011 (256M (2^28)),11100 (512M (2^29)),11101 (1G (2^30)),11110 (res),11111 (res)" tree.end tree "EUMB Interface" group.long ANC:0x80000CFC++3 SAVEOUT ANC:0x80000CF8 %l 0x80000078 LINE.LONG 0 "0x78 EUMBBAR, Embedded Utilities Memory Block Base Adress Register" HEXMASK.LONG 0. 20.--31. 0x100000 0. "ADDR ,Base address. Block size 1MB." TEXTLINE " Valid address: 0x80000000 <= ADDR <=0xFDF00000" BASESAVEOUT ANC:Data.Long.LE(ANC:0x80000CFC) ANC:0x80000CF8 %Long %LE 0x80000078 tree "Message Unit (I2O)" group 0x50++0x0f "Message Registers" line.long 0x0 "IMR0,Inbound Message Register 0" line.long 0x4 "IMR1,Inbound Message Register 1" line.long 0x8 "OMR0,Outbound Message Register 0" line.long 0x0c "OMR1,Outbound Message Register 1" group 0x60++0x03 "Door Bell Registers" line.long 0x0 "ODBR,Outbound Door Bell Register" group 0x68++0x03 line.long 0x0 "IDBR,Inbound Door Bell Register" group 0x100++0x07 "I2O Registers" line.long 0x0 "IMISR,Inbound Message Interrupt Status Register" line.long 0x4 "IMIMR,Inbound Message Interrupt Mask Register" group 0x120++0x03 line.long 0x0 "IFHPR,Inbound Free_FIFO Head Pointer Register" group 0x128++0x03 line.long 0x0 "IFTPR,Inbound Free_FIFO Tail Pointer Register" group 0x130++0x03 line.long 0x0 "IPHPR,Inbound Post_FIFO Head Pointer Register" group 0x138++0x03 line.long 0x0 "IPTPR,Inbound Post_FIFO Tail Pointer Register" group 0x140++0x03 line.long 0x0 "OFHPR,Outbound Free_FIFO Head Pointer Register" group 0x148++0x03 line.long 0x0 "OFTPR,Outbound Free_FIFO Tail Pointer Register" group 0x150++0x03 line.long 0x0 "OPHPR,Outbound Post_FIFO Head Pointer Register" group 0x158++0x03 line.long 0x0 "OPTPR,Outbound Post_FIFO Tail Pointer Register" group 0x164++0x03 line.long 0x0 "MUCR,Message Unit Control Register" group 0x170++0x03 line.long 0x0 "QBAR,Queue Base Address Register" tree.end tree "DMA Controller" group 0x1100++0x27 "Channel 0" line.long 0x0 "MR,Mode Register" bitfld.long 0x0 19. "IRQS ,Interrupt Steer" "no,yes" bitfld.long 0x0 18. " PDE ,Periodic DMA Enable" "no,yes" bitfld.long 0x0 16.--17. " DAHTS ,Destination Address Hold Transfer Size" "1b,2b,4b,8b" bitfld.long 0x0 14.--15. " SAHTS ,Source Address Hold Transfer Size" "1b,2b,4b,8b" bitfld.long 0x0 13. " DAHE ,Destination Address Hold Enable" "no,yes" bitfld.long 0x0 12. " SAHE ,Source Address Hold Enable" "no,yes" textline " " bitfld.long 0x0 10.--11. " PRC ,PCI Read Command" "read,read line,read multiple,res" bitfld.long 0x0 8. " EIE ,Error Interrupt Enable" "no,yes" bitfld.long 0x0 7. " EOTIE ,End-Of-Transfer Interrupt Enable" "no,yes" bitfld.long 0x0 3. " DL ,Descriptor Location" "lcl,pci" bitfld.long 0x0 2. " CDM ,Channel Transfer Mode" "chaining,direct" bitfld.long 0x0 1. " CC ,Channel Continue" "no,yes" bitfld.long 0x0 0. " CS ,Channel Start" "no,yes" line.long 0x4 "SR,Status Register" eventfld.long 0x4 7. "LME ,Local Memory Error" "no,yes" eventfld.long 0x4 18. " PE ,PCI Error" "no,yes" bitfld.long 0x4 2. " CB ,Channel Busy" "no,yes" eventfld.long 0x4 1. " EOSI ,End-Of-Segment Interrupt" "no,yes" eventfld.long 0x4 0. " EOCAI ,End-Of-Chain/direct Interrupt" "no,yes" line.long 0x8 "CDAR,Current Descriptor Address Register" bitfld.long 0x8 4. "SNEN ,Snoop Enable" "no,yes" bitfld.long 0x8 3. " EOSIE ,End-of-Segment Interrupt Enable" "no,yes" bitfld.long 0x8 0x1--2. " CTT ,Channel Transfer Type" "lcl-lcl,lcl-pci,pci-lcl,pci-pci" line.long 0x10 "SAR,Source Address Register" line.long 0x18 "DAR,Destination Address Register" line.long 0x20 "BCR,Byte Count Register" line.long 0x24 "NDAR,Next Descriptor Address Register" bitfld.long 0x8 4. "NDSNEN ,Next Descriptor Snoop Enable" "no,yes" bitfld.long 0x8 3. " NDEOSIE ,Next Descriptor End-of-Segment Interrupt Enable" "no,yes" bitfld.long 0x8 0x1--2. " NDCTT ,Next Descriptor Channel Transfer Type" "lcl-lcl,lcl-pci,pci-lcl,pci-pci" group 0x1200++0x27 "Channel 1" copy tree.end tree "I2C Controller" group 0x3000++0x13 line.long 0x0 "I2CADR,I2C Address Register" line.long 0x4 "I2CFDR,I2C Frequency Divider Register" line.long 0x8 "I2CCR,I2C Control Register" bitfld.long 0x8 7. "MEN ,Module Enable" "no,yes" bitfld.long 0x8 6. " MIEN ,Module Interrupt Enable" "no,yes" bitfld.long 0x8 5. " MSTA ,Master/Slave Mode Select" "slave,master" bitfld.long 0x8 4. " MTX ,Transmit/Receive Mode Select" "receive,transmit" bitfld.long 0x8 3. " TXAK ,Transfer Acknowledge Enable" "no,yes" bitfld.long 0x8 2. " RSTA ,Repeat Start" "no,yes" line.long 0x0c "I2CSR,I2C Status Register" bitfld.long 0x0c 7. "MCF ,Data Transferring" "no,yes" bitfld.long 0x0c 6. " MAAS ,Addressed as a Slave" "no,yes" bitfld.long 0x0c 5. " MBB ,Bus Busy" "no,yes" bitfld.long 0x0c 4. " MAL ,Arbitration Lost" "no,yes" bitfld.long 0x0c 2. " SRW ,Slave Read/Write" "receive,transmit" bitfld.long 0x0c 1. " MIF ,Module Interrupt" "no,yes" bitfld.long 0x0c 0. " RXAK ,Received Acknownledge" "yes,no" line.long 0x10 "I2CDR,I2C Data Register" tree.end tree "Embedded Programmable Interrupt Controller" width 7. group 0x41000++0x03 "Global EPIC Registers" line.long 0x00 "FRR,Feature Reporting Register" hexmask.long.word 0x00 16.--26. 1. " NIRQ ,Number of interrupts" bitfld.long 0x00 8.--12. " NCPU ,Number of CPUs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " VID ,Version ID for this interrupt controller" group 0x41020++0x13 line.long 0x00 "GCR,Global Configuration Register" bitfld.long 0x00 31. " R ,Reset EPIC unit" "No reset,Reset" bitfld.long 0x00 29. " M ,Mode" "Pass-through,Mixed" line.long 0x10 "EICR,EPIC Interrupt Configuration Register" bitfld.long 0x10 28.--30. " R ,Clock ratio" "Reserved,2,4,6,8,10,12,14" bitfld.long 0x10 27. " SIE ,Serial interrupt enable" "Direct,Serial" group 0x41080++0x13 line.long 0x00 "EVI,EPIC Vendor Identification Register" hexmask.long.byte 0x00 16.--23. 1. " STEP ,Stepping" hexmask.long.byte 0x00 8.--15. 1. " DEVICE_ID ,Device identification" hexmask.long.byte 0x00 0.--7. 1. " VENDOR_ID ,Vendor identification" line.long 0x10 "PI,Processor Initialization Register" bitfld.long 0x10 0. " P0 ,Processor 0 soft reset" "No reset,Reset" group 0x410e0++0x03 line.long 0x00 "SVR,Spurious Vector Register" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Spurious interrupt vector" tree "Global Timer Registers" group 0x410f0++0x03 line.long 0x00 "TFRR,Timer Frequency Reporting Register" hexmask.long 0x00 0.--31. 1. " TIMER_FREQ ,Timer Frequency Reporting Register" group 0x41100++0x23 "Timer 0" line.long 0x00 "GTCCR0,Global Timer 0 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR0,Global Timer 0 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR0,Global Timer 0 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41100+0x30)++0x03 line.long 0x00 "GTDR0,Global Timer 0 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x41140++0x23 "Timer 1" line.long 0x00 "GTCCR1,Global Timer 1 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR1,Global Timer 1 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR1,Global Timer 1 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41140+0x30)++0x03 line.long 0x00 "GTDR1,Global Timer 1 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x41180++0x23 "Timer 2" line.long 0x00 "GTCCR2,Global Timer 2 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR2,Global Timer 2 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR2,Global Timer 2 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x41180+0x30)++0x03 line.long 0x00 "GTDR2,Global Timer 2 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" group 0x411C0++0x23 "Timer 3" line.long 0x00 "GTCCR3,Global Timer 3 Current Count Register" bitfld.long 0x00 31. " T ,Toggle" "Low,High" hexmask.long 0x00 0.--30. 1. " COUNT ,Current timer count" line.long 0x10 "GTBCR3,Global Timer 3 Base Count Register" bitfld.long 0x10 31. " CI ,Count inhibit" "Enabled,Inhibited" hexmask.long 0x10 0.--30. 1. " BASE_COUNT ,Base count" line.long 0x20 "GTVPR3,Global Timer 3 Vector/Priority Register" bitfld.long 0x20 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x20 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x20 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x20 0.--7. 1. " VECTOR ,Vector" group (0x411C0+0x30)++0x03 line.long 0x00 "GTDR3,Global Timer 3 Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Internal Interrupt Registers" group 0x50200++0x03 line.long 0x00 "IVPR0,Direct Interrupt Vector/Priority Register 0" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50220++0x03 line.long 0x00 "IVPR1,Direct Interrupt Vector/Priority Register 1" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50240++0x03 line.long 0x00 "IVPR2,Direct Interrupt Vector/Priority Register 2" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50260++0x03 line.long 0x00 "IVPR3,Direct Interrupt Vector/Priority Register 3" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50280++0x03 line.long 0x00 "IVPR4,Direct Interrupt Vector/Priority Register 4" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup 0x50210++0x03 line.long 0x00 "IDR0,Direct Interrupt Destination Register 0" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50230++0x03 line.long 0x00 "IDR1,Direct Interrupt Destination Register 1" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50250++0x03 line.long 0x00 "IDR2,Direct Interrupt Destination Register 2" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50270++0x03 line.long 0x00 "IDR3,Direct Interrupt Destination Register 3" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50290++0x03 line.long 0x00 "IDR4,Direct Interrupt Destination Register 4" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Serial Interrupt Registers" group 0x50200++0x03 line.long 0x00 "SVPR0,Serial Interrupt Vetor/Priority Register 0" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50220++0x03 line.long 0x00 "SVPR1,Serial Interrupt Vetor/Priority Register 1" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50240++0x03 line.long 0x00 "SVPR2,Serial Interrupt Vetor/Priority Register 2" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50260++0x03 line.long 0x00 "SVPR3,Serial Interrupt Vetor/Priority Register 3" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50280++0x03 line.long 0x00 "SVPR4,Serial Interrupt Vetor/Priority Register 4" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502A0++0x03 line.long 0x00 "SVPR5,Serial Interrupt Vetor/Priority Register 5" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502C0++0x03 line.long 0x00 "SVPR6,Serial Interrupt Vetor/Priority Register 6" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x502E0++0x03 line.long 0x00 "SVPR7,Serial Interrupt Vetor/Priority Register 7" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50300++0x03 line.long 0x00 "SVPR8,Serial Interrupt Vetor/Priority Register 8" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50320++0x03 line.long 0x00 "SVPR9,Serial Interrupt Vetor/Priority Register 9" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50340++0x03 line.long 0x00 "SVPR10,Serial Interrupt Vetor/Priority Register 10" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50360++0x03 line.long 0x00 "SVPR11,Serial Interrupt Vetor/Priority Register 11" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x50380++0x03 line.long 0x00 "SVPR12,Serial Interrupt Vetor/Priority Register 12" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503A0++0x03 line.long 0x00 "SVPR13,Serial Interrupt Vetor/Priority Register 13" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503C0++0x03 line.long 0x00 "SVPR14,Serial Interrupt Vetor/Priority Register 14" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" group 0x503E0++0x03 line.long 0x00 "SVPR15,Serial Interrupt Vetor/Priority Register 15" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 23. " P ,Polarity" "Active-low/Negative-edge,Active-high/Positive-edge" bitfld.long 0x00 22. " S ,Sense" "Edge,Level" textline " " bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup 0x50210++0x03 line.long 0x00 "SDR0,Serial Interrupt Destination Register 0" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50230++0x03 line.long 0x00 "SDR1,Serial Interrupt Destination Register 1" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50250++0x03 line.long 0x00 "SDR2,Serial Interrupt Destination Register 2" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50270++0x03 line.long 0x00 "SDR3,Serial Interrupt Destination Register 3" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50290++0x03 line.long 0x00 "SDR4,Serial Interrupt Destination Register 4" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502B0++0x03 line.long 0x00 "SDR5,Serial Interrupt Destination Register 5" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502D0++0x03 line.long 0x00 "SDR6,Serial Interrupt Destination Register 6" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x502F0++0x03 line.long 0x00 "SDR7,Serial Interrupt Destination Register 7" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50310++0x03 line.long 0x00 "SDR8,Serial Interrupt Destination Register 8" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50330++0x03 line.long 0x00 "SDR9,Serial Interrupt Destination Register 9" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50350++0x03 line.long 0x00 "SDR10,Serial Interrupt Destination Register 10" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50370++0x03 line.long 0x00 "SDR11,Serial Interrupt Destination Register 11" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x50390++0x03 line.long 0x00 "SDR12,Serial Interrupt Destination Register 12" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503B0++0x03 line.long 0x00 "SDR13,Serial Interrupt Destination Register 13" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503D0++0x03 line.long 0x00 "SDR14,Serial Interrupt Destination Register 14" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x503F0++0x03 line.long 0x00 "SDR15,Serial Interrupt Destination Register 15" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Onchip Module Interrupt Registers (I2C, DMA, MU)" rgroup 0x51020++0x03 line.long 0x00 "IIVPR0,I2C Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51020+0x10)++0x03 line.long 0x00 "IIDR0,I2C Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x51040++0x03 line.long 0x00 "IIVPR1,DMA Ch0 Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51040+0x10)++0x03 line.long 0x00 "IIDR1,DMA Ch0 Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x51060++0x03 line.long 0x00 "IIVPR2,DMA Ch1 Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x51060+0x10)++0x03 line.long 0x00 "IIDR2,DMA Ch1 Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" rgroup 0x510c0++0x03 line.long 0x00 "IIVPR3,Message Unit Interrupt Vector/Priority Register" bitfld.long 0x00 31. " M ,Mask" "Allowed,Masked" bitfld.long 0x00 30. " A ,Activity" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " PRIORITY ,Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Vector" rgroup (0x510c0+0x10)++0x03 line.long 0x00 "IIDR3,Message Unit Interrupt Destination Register" bitfld.long 0x00 0. " P0 ,Processor 0" "Not P0,P0" tree.end tree "Processor-Related Registers" group 0x60080++0x03 line.long 0x00 "PCTPR,Processor Current Task Priority Register" bitfld.long 0x00 0.--3. " TASKP ,Task priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup 0x600a0++0x03 line.long 0x00 "IACK,Processor Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " VECTOR ,Interrupt vector" wgroup 0x600b0++0x03 line.long 0x00 "EOI,Processor End-of-Interrupt Register" bitfld.long 0x00 0.--3. " EOI_CODE ," "0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f" tree.end tree.end tree.end tree.end