; --------------------------------------------------------------------------------
; @Title: IMXRT6XX On-Chip Peripherals
; @Props: Released
; @Author: KWI
; @Changelog: 2020-08-26 KWI
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated
; @Core: Cortex-M33
; @Chip: IMXRT633, IMXRT635, IMXRT685-CM33
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perimxrt6xx.per 12274 2020-08-26 12:26:10Z kwitkowski $
config 16. 8.
tree.close "Core Registers (Cortex-M33F)"
tree "System Control"
base ad:0xE000E000
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL      ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. "              DISITMATBFLUSH    ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. "            FPEXCODIS      ,Disables FPU exception outputs" "No,Yes"
textline "                     "
bitfld.long 0x00 9. " DISOOFP         ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD           ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. "            DISMCYCINT     ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10           ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. "      SU10              ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. "  SUS7           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 14. " SU7             ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. "    SUS6              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. "    SU6            ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 11. " SUS5            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. "      SU5               ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. "  SUS4           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 8. " SU4             ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. "    SUS3              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. "    SU3            ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 5. " SUS2            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. "      SU2               ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. "  SUS1           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 2. " SU1             ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. "    SUS0              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. "    SU0            ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG       ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. "      CLKSOURCE         ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. "       TICKINT        ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x04 0. " ENABLE          ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD          ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT         ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF           ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW              ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "        TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER     ,Indicates implementer"
bitfld.long 0x00 20.--23. "               VARIANT           ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "     ARCHITECTURE   ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO          ,Indicates part number"
bitfld.long 0x00 0.--3. "             REVISION          ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET      , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. "      PENDSVSET         , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. "    PENDSTSET      ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline "                     "
bitfld.long 0x00 24. " STTNS           ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. "       ISRPREEMPT        ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. "       ISRPENDING     ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline "                     "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING     ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. "             RETTOBASE         ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. "        VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF          ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT     ,Vector Key"
rbitfld.long 0x08 15. "             ENDIANNESS        ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. "  PRIS           ,Prioritize Secure exceptions" "Disabled,Enabled"
textline "                     "
bitfld.long 0x08 13. " BFHFNMINS       ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. "         PRIGROUP          ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. "    SYSRESETREQS   ,System reset request Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ     ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE     ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND       ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. "       SLEEPDEEPS        ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. "    SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                     "
bitfld.long 0x0C 1. " SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP              ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "         IC                ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "       DC             ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 10. " STKOFHFNMIGN    ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. "      BFHFNMIGN         ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. "    DIV_0_TRP      ,Controls the trap on divide by 0" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP     ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. "         USERSETMPEND      ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7           ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. "               PRI_6             ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. "             PRI_5          ,Priority of system handler 5, BusFault"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4           ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11          ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15          ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. "               PRI_14            ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. "             PRI_12         ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. "      SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. "    SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 18. " USGFAULTENA     ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. "         BUSFAULTENA       ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. "       MEMFAULTENA    ,MemManage exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED    ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. "      BUSFAULTPENDED    ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. "    MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED  ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. "      SYSTICKACT        ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. "     PENDSVACT      ,PendSV exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT      ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. "       SVCALLACT         ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. "     NMIACT         ,NMI exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 4. " SECUREFAULTACT  ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT       ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. "     HARDFAULTACT   ,HardFault exception status for the selected Security state" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT     ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. "       MEMFAULTACT       ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "     MMARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "        MLSPERR           ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "   MSTKERR        ,Stacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR       ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "     DACCVIOL          ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "   IACCVIOL       ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "     BFARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "        LSPERR            ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "   STKERR         ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR        ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "     IMPRECISERR       ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "   PRECISERR      ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR         ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. "     DIVBYZERO       ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. "         UNALIGNED         ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. "       STKOF          ,Stack overflow error" "No error,Error"
textline "                     "
eventfld.word 0x00 3. " NOCP            ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. "         INVPC             ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. "       INVSTATE       , Invalid Combination of EPSR and Instruction" "No error,Error"
textline "                     "
eventfld.word 0x00 0. " UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT        ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "     FORCED            ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. "   VECTTBL        ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10            ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. "       CP7               ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 12.--13. " CP6             ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. "       CP5               ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. "     CP4            ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 6.--7. " CP3             ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. "       CP2               ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. "     CP1            ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 0.--1. " CP0             ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(ad:0xE000ED48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11            ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. "         CP10              ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. "       CP7            ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " CP6             ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. "         CP5               ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. "       CP4            ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " CP3             ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. "         CP2               ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. "       CP1            ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 0. " CP0             ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID           ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x0B
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB      ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. "  LOU      ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. "        LOC           ,Level of Coherency" "Level 1,Level 2,?..."
textline "                   "
bitfld.long 0x00 18.--20. " CL7      ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. "   CL6      ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. "       CL5           ,Cache type field level 5" "No cache,?..."
textline "                   "
bitfld.long 0x00 9.--11. " CL4      ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. "          CL3      ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. "       CL2           ,Cache type field level 2" "No cache,?..."
textline "                   "
bitfld.long 0x00 0.--2. " CL1      ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(ad:0xE000E000+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. "          CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. "              ERG           ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline "                   "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0x80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "     WB       ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. "  RA            ,Indicates support available for read allocation" "Not supported,Supported"
textline "                   "
bitfld.long 0x00 28. " WA       ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. "     NUMSETS  ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline "                   "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. "           IND      ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "                    STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. "                      SECURITY       ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG  ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "                TCM            ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "                PMSASUP        ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT   ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. "                CMAINTSW       ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. "        CMAINTVA  ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "                DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "                BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. "                IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x00 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. "         MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline "                   "
bitfld.long 0x00 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. "                MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. "                THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "                SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline "                   "
bitfld.long 0x00 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x07
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. "                SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. "            BARRIER   ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. "                WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. "           UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base ad:0xE000E000
width 11.
if (((per.l(ad:0xE000E000+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0xB
tree.end    
tree "Memory Protection Unit"
base ad:0xE000ED00
width 15.
rgroup.long 0x90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION    ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "         SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0x94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "   HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "   ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0x98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x0
group.long 0x9C++0x03 "Region 0"
saveout 0x98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 0 (not implemented)"
saveout 0x98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x1
group.long 0x9C++0x03 "Region 1"
saveout 0x98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 1 (not implemented)"
saveout 0x98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x2
group.long 0x9C++0x03 "Region 2"
saveout 0x98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 2 (not implemented)"
saveout 0x98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x3
group.long 0x9C++0x03 "Region 3"
saveout 0x98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 3 (not implemented)"
saveout 0x98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x4
group.long 0x9C++0x03 "Region 4"
saveout 0x98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 4 (not implemented)"
saveout 0x98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x5
group.long 0x9C++0x03 "Region 5"
saveout 0x98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 5 (not implemented)"
saveout 0x98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x6
group.long 0x9C++0x03 "Region 6"
saveout 0x98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 6 (not implemented)"
saveout 0x98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x7
group.long 0x9C++0x03 "Region 7"
saveout 0x98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 7 (not implemented)"
saveout 0x98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x8
group.long 0x9C++0x03 "Region 8"
saveout 0x98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 8 (not implemented)"
saveout 0x98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x9
group.long 0x9C++0x03 "Region 9"
saveout 0x98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 9 (not implemented)"
saveout 0x98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xA
group.long 0x9C++0x03 "Region 10"
saveout 0x98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 10 (not implemented)"
saveout 0x98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xB
group.long 0x9C++0x03 "Region 11"
saveout 0x98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 11 (not implemented)"
saveout 0x98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xC
group.long 0x9C++0x03 "Region 12"
saveout 0x98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 12 (not implemented)"
saveout 0x98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xD
group.long 0x9C++0x03 "Region 13"
saveout 0x98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 13 (not implemented)"
saveout 0x98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xE
group.long 0x9C++0x03 "Region 14"
saveout 0x98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 14 (not implemented)"
saveout 0x98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xF
group.long 0x9C++0x03 "Region 15"
saveout 0x98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xA0++0x03
saveout 0x98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0x9C++0x03 "Region 15 (not implemented)"
saveout 0x98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline "                   "
hgroup.long 0xA0++0x03
saveout 0x98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
textline "                     "
group.long 0xC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
hexmask.long.byte 0x00 24.--31. 1. " ATTR3      ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
hexmask.long.byte 0x00 16.--23. 1. "         ATTR2    ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
hexmask.long.byte 0x00 8.--15. 1. "             ATTR1  ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
hexmask.long.byte 0x00 0.--7. 1. "        ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
hexmask.long.byte 0x04 24.--31. 1. " ATTR7      ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
hexmask.long.byte 0x04 16.--23. 1. "         ATTR6    ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
hexmask.long.byte 0x04 8.--15. 1. "             ATTR5  ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
hexmask.long.byte 0x04 0.--7. 1. "        ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
width 0x0b
tree.end
tree "Security Attribution Unit"
base ad:0xE000ED00
width 15.
group.long 0xD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS   ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. "  ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(ad:0xE000EDD0)
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x0
group.long 0xDC++0x03 "Region 0"
saveout 0xD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 0 (not implemented)"
saveout 0xD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x1
group.long 0xDC++0x03 "Region 1"
saveout 0xD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 1 (not implemented)"
saveout 0xD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x2
group.long 0xDC++0x03 "Region 2"
saveout 0xD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 2 (not implemented)"
saveout 0xD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x3
group.long 0xDC++0x03 "Region 3"
saveout 0xD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 3 (not implemented)"
saveout 0xD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x4
group.long 0xDC++0x03 "Region 4"
saveout 0xD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 4 (not implemented)"
saveout 0xD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x5
group.long 0xDC++0x03 "Region 5"
saveout 0xD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 5 (not implemented)"
saveout 0xD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x6
group.long 0xDC++0x03 "Region 6"
saveout 0xD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 6 (not implemented)"
saveout 0xD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x7
group.long 0xDC++0x03 "Region 7"
saveout 0xD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xE0++0x03
saveout 0xD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDC++0x03 "Region 7 (not implemented)"
saveout 0xD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDC++0x03 "Region 0 (not accessible)"
saveout 0xD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDC++0x03 "Region 1 (not accessible)"
saveout 0xD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDC++0x03 "Region 2 (not accessible)"
saveout 0xD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDC++0x03 "Region 3 (not accessible)"
saveout 0xD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDC++0x03 "Region 4 (not accessible)"
saveout 0xD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDC++0x03 "Region 5 (not accessible)"
saveout 0xD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDC++0x03 "Region 6 (not accessible)"
saveout 0xD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDC++0x03 "Region 7 (not accessible)"
saveout 0xD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xE0++0x03
saveout 0xD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR   ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. "  SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. "    LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. "  AUVIOL    ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER  ,Invalid exception return flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 1. " INVIS   ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. "  INVEP     ,Invalid entry point" "Not occurred,Occurred"
group.long 0xE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0b
tree.end    
tree "Nested Vectored Interrupt Controller"
base ad:0xE000E000
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31  ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS30  ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS29  ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS28  ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS27  ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS26  ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS25  ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS24  ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS23  ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS22  ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS21  ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS20  ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS19  ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS18  ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS17  ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS16  ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS15  ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS14  ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS13  ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS12  ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS11  ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS10  ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS9   ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS8   ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS7   ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS6   ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS5   ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS4   ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS3   ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS2   ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS1   ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS0   ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63  ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS62  ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS61  ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS60  ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS59  ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS58  ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS57  ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS56  ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS55  ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS54  ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS53  ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS52  ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS51  ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS50  ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS49  ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS48  ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS47  ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS46  ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS45  ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS44  ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS43  ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS42  ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS41  ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS40  ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS39  ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS38  ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS37  ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS36  ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS35  ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS34  ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS33  ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS32  ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95  ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS94  ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS93  ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS92  ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS91  ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS90  ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS89  ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS88  ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS87  ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS86  ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS85  ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS84  ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS83  ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS82  ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS81  ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS80  ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS79  ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS78  ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS77  ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS76  ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS75  ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS74  ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS73  ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS72  ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS71  ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS70  ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS69  ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS68  ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS67  ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS66  ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS65  ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS64  ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS99  ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS98  ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS97  ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS96  ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
tree.end 
sif CORENAME()=="CORTEXM33F"
tree "Floating-point Unit (FPU)"
base ad:0xE000EF34
width 8.
group.long 0x00++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN     ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. "       LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
textline "                 "
bitfld.long 0x00 28. " CLRONRET     ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. "                      CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. "    TS     ,Treat as Secure" "Disabled,Enabled"
textline "                 "
bitfld.long 0x00 10. " UFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. "                      SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. "           MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 7. " SFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. "                      BFRDY     ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "       MMRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 4. " HFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. "                      THREAD    ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. "        S      ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
textline "                 "
bitfld.long 0x00 1. " USER         ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "                  LSPACT    ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN        ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ     ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0x0C++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. "                 SQRROOT   ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. "      DIV    ,Indicates the hardware support for FP divide operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " DBLPREC      ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. "                 SNGLPREC  ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "      A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP   ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE  ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC     ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
tree.end
endif
tree "Debug"
base ad:0xE000ED00
width 7.
group.long 0x30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL   ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH       ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP      ,Indicates a debug event generated by the DWT" "Not generated,Generated"
textline "                "
eventfld.long 0x00 1. " BKPT       ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED       ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
hgroup.long 0xF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
wgroup.long 0xF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR     ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL       ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(ad:0xE000ED00+0xFC))&0x10000)==0x10000)
group.long 0xFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME         ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "     MON_REQ      ,DebugMonitor semaphore bit" "0,1"
textline "                "
bitfld.long 0x00 18. " MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
bitfld.long 0x00 17. "        MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN       ,Enable the DebugMonitor exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 11. " VC_SFERR   ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR   ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
bitfld.long 0x00 9. "       VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 8. " VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR   ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR     ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "       VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME         ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "     MON_REQ      ,DebugMonitor semaphore bit" "0,1"
textline "                "
bitfld.long 0x00 17. " MON_PEND   ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN       ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR   ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 11. " VC_SFERR   ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 9. "       VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR    ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR   ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 4. " VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "       VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
textline "                "
width 13.
group.long 0x104++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " SPIDENSEL  ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
textline "                      "
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS        ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. "   SBRSEL     ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. "   SBRSELEN  ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0x2B8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI        ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. "  SNE        ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. "            SI        ,Secure invasive debug features implemented" ",Implemented"
textline "                      "
bitfld.long 0x00 4. " SE         ,Secure invasive debug enabled" "0,1"
bitfld.long 0x00 3. "            NSNI       ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. "  NSNE      ,Non-secure non-invasive debug enabled" "0,1"
textline "                      "
bitfld.long 0x00 1. " NSI        ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. "  NSE        ,Non-secure invasive debug enabled" "0,1"
tree "Debug components"
width 14.
base ad:0xE00FF000
group.long 0x00++0x0F
line.long 0x00 "SCS,System Control Space"
line.long 0x04 "DWT,Data Watchpoint and Trace Unit"
line.long 0x08 "FPB,Flash Patch and Breakpoint Unit"
line.long 0x0C "ITM,Instrumentation Trace Macrocell"
group.long 0x14++0x0B
line.long 0x00 "ETM,Embedded Trace Macrocell"
line.long 0x04 "CTI,Cross Trigger Interface"
line.long 0x08 "MTB,Micro Trace Buffer"
group.long 0xFCC++0x03
line.long 0x00 "MEMTYPE,MEMTYPE"
bitfld.long 0x00 0. " MEMTYPE[0] ,Indicates that resources other than those listed in the ROM table are accessible in the same 32-bit address space using the DAP" "No,Yes"
tree "Coresight identification Registers"
width 6.
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFE0++0x1F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
line.long 0x10 "CID0,Component ID0 (Preamble)"
line.long 0x14 "CID1,Component ID1"
hexmask.long.byte 0x14 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x14 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x18 "CID2,Component ID2"
line.long 0x1c "CID3,Component ID3"
tree.end
tree.end
width 0x0b
tree "Flash Patch and Breakpoint Unit (FPB)"
base ad:0xE0002000
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV    ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "      NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. "         NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 1. " KEY    ,Key Field" "Low,High"
bitfld.long 0x00 0. "           ENABLE   ,Flash Patch Unit Enable" "Disabled,Enabled"
textline "                     "
if (((per.l(ad:0xE0002000+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 "  REMAP    ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(ad:0xE0002000+0x8))&0x01)==0x00)
group.long 0x8++0x1F
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x1F
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0xC))&0x01)==0x00)
group.long 0xC++0x1F
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x1F
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x10))&0x01)==0x00)
group.long 0x10++0x1F
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x1F
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x14))&0x01)==0x00)
group.long 0x14++0x1F
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x1F
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x18))&0x01)==0x00)
group.long 0x18++0x1F
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x1F
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x1C))&0x01)==0x00)
group.long 0x1C++0x1F
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x1F
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x20))&0x01)==0x00)
group.long 0x20++0x1F
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x1F
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(ad:0xE0002000+0x24))&0x01)==0x00)
group.long 0x24++0x1F
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x1F
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. "       BE       ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
if (((per.l(ad:0xE0002000+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
base ad:0xE0001000
width 16.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP    ,Number of comparators implemented" "0,1,2,3,4,?..."
rbitfld.long 0x00 27. "                     NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. "              NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline "                         "
rbitfld.long 0x00 24. " NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. "         CYCDISS    ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. "                        CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "              LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "                   SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 18. " EXCEVTENA  ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "              CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "                   EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "              SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "                 CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                         "
bitfld.long 0x00 5.--8. " POSTINIT   ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "                    POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "                         CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(ad:0xE0001000)&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(ad:0xE0001000)&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT     ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT     ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT     ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                         "
if ((per.l(ad:0xE0001000+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(ad:0xE0001000+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(ad:0xE0001000+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(ad:0xE0001000+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(ad:0xE0001000+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. "                            PRESENT        ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
tree.end
tree.end
tree.end
tree "ADC"
tree "ADC0"
base ad:0x4013A000
width 11.
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. " CMD_NUM  ,Command Buffer Number"
textline "                    "
hexmask.long.byte 0x00 16.--23. 1. " CV_NUM   ,Compare Value Number"
textline "                    "
hexmask.long.byte 0x00 8.--15. 1. " FIFOSIZE ,Result FIFO Depth"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " TRIG_NUM ,Trigger Number"
group.long 0x10++0x03
line.long 0x00 "CTRL,ADC Control Register"
bitfld.long 0x00 8. " RSTFIFO  ,Reset FIFO" "0: RSTFIFO_0,1: FIFO is reset"
textline "                    "
bitfld.long 0x00 2. " DOZEN    ,Doze Enable" "0: ADC is enabled in Doze mode,1: ADC is disabled in Doze mode"
textline "                    "
bitfld.long 0x00 1. " RST      ,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset"
textline "                    "
bitfld.long 0x00 0. " ADCEN    ,ADC Enable" "0: ADC is disabled,1: ADC is enabled"
group.long 0x14++0x03
line.long 0x00 "STAT,ADC Status Register"
rbitfld.long 0x00 24.--27. " CMDACT   ,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,,,,,,,,,,,,,15: Command 15 currently being executed"
textline "                    "
rbitfld.long 0x00 16.--19. " TRGACT   ,Trigger Active" "0: Command (sequence) associated with Trigger 0 currently being executed,1: Command (sequence) associated with Trigger 1 currently being executed,,,,,,,,,,,,,,15: Command (sequence) associated with Trigger 15 currently being executed"
textline "                    "
eventfld.long 0x00 1. " FOF      ,Result FIFO Overflow Flag" "0: No result FIFO overflow has occurred since the last time the flag was cleared,1: At least one result FIFO overflow has occurred since the last time the flag was cleared"
textline "                    "
rbitfld.long 0x00 0. " RDY      ,Result FIFO Ready Flag" "0: Result FIFO data level not above watermark level,1: Result FIFO holding data above watermark level"
group.long 0x18++0x03
line.long 0x00 "IE,Interrupt Enable Register"
bitfld.long 0x00 1. " FOFIE    ,Result FIFO Overflow Interrupt Enable" "0: FIFO overflow interrupts are not enabled,1: FIFO overflow interrupts are enabled"
textline "                    "
bitfld.long 0x00 0. " FWMIE    ,FIFO Watermark Interrupt Enable" "0: FIFO watermark interrupts are not enabled,1: FIFO watermark interrupts are enabled"
group.long 0x1C++0x03
line.long 0x00 "DE,DMA Enable Register"
bitfld.long 0x00 0. " FWMDE    ,FIFO Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
group.long 0x20++0x03
line.long 0x00 "CFG,ADC Configuration Register"
bitfld.long 0x00 28. " PWREN    ,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while conversions are active,1: ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the .."
textline "                    "
hexmask.long.byte 0x00 16.--23. 1. " PUDLY    ,Power Up Delay"
textline "                    "
bitfld.long 0x00 6.--7. " REFSEL   ,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,"
textline "                    "
bitfld.long 0x00 4.--5. " PWRSEL   ,Power Configuration Select" "0: Lowest power setting,1: Next lowest power setting,2: PWRSEL_2,3: Highest power setting"
textline "                    "
bitfld.long 0x00 0. " TPRICTRL ,ADC trigger priority control" "0: If a higher priority trigger is detected during command processing. the current conversion is aborte..,1: If a higher priority trigger is received during command processing. the current conversion is comple.."
group.long 0x24++0x03
line.long 0x00 "PAUSE,ADC Pause Register"
bitfld.long 0x00 31. " PAUSEEN  ,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled"
textline "                    "
hexmask.long.word 0x00 0.--8. 1. " PAUSEDLY ,Pause Delay"
group.long 0x30++0x03
line.long 0x00 "FCTRL,ADC FIFO Control Register"
bitfld.long 0x00 16.--19. " FWMARK   ,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
rbitfld.long 0x00 0.--4. " FCOUNT   ,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "SWTRIG,Software Trigger Register"
bitfld.long 0x00 15. " SWT15    ,Software trigger 15 event" "0: No trigger 15 event generated,1: Trigger 15 event generated"
textline "                    "
bitfld.long 0x00 14. " SWT14    ,Software trigger 14 event" "0: No trigger 14 event generated,1: Trigger 14 event generated"
textline "                    "
bitfld.long 0x00 13. " SWT13    ,Software trigger 13 event" "0: No trigger 13 event generated,1: Trigger 13 event generated"
textline "                    "
bitfld.long 0x00 12. " SWT12    ,Software trigger 12 event" "0: No trigger 12 event generated,1: Trigger 12 event generated"
textline "                    "
bitfld.long 0x00 11. " SWT11    ,Software trigger 11 event" "0: No trigger 11 event generated,1: Trigger 11 event generated"
textline "                    "
bitfld.long 0x00 10. " SWT10    ,Software trigger 10 event" "0: No trigger 10 event generated,1: Trigger 10 event generated"
textline "                    "
bitfld.long 0x00 9. " SWT9     ,Software trigger 9 event" "0: No trigger 9 event generated,1: Trigger 9 event generated"
textline "                    "
bitfld.long 0x00 8. " SWT8     ,Software trigger 8 event" "0: No trigger 8 event generated,1: Trigger 8 event generated"
textline "                    "
bitfld.long 0x00 7. " SWT7     ,Software trigger 7 event" "0: No trigger 7 event generated,1: Trigger 7 event generated"
textline "                    "
bitfld.long 0x00 6. " SWT6     ,Software trigger 6 event" "0: No trigger 6 event generated,1: Trigger 6 event generated"
textline "                    "
bitfld.long 0x00 5. " SWT5     ,Software trigger 5 event" "0: No trigger 5 event generated,1: Trigger 5 event generated"
textline "                    "
bitfld.long 0x00 4. " SWT4     ,Software trigger 4 event" "0: No trigger 4 event generated,1: Trigger 4 event generated"
textline "                    "
bitfld.long 0x00 3. " SWT3     ,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated"
textline "                    "
bitfld.long 0x00 2. " SWT2     ,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated"
textline "                    "
bitfld.long 0x00 1. " SWT1     ,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated"
textline "                    "
bitfld.long 0x00 0. " SWT0     ,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated"
group.long 0xC0++0x03
line.long 0x00 "TCTRL[0],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xC4++0x03
line.long 0x00 "TCTRL[1],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xC8++0x03
line.long 0x00 "TCTRL[2],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xCC++0x03
line.long 0x00 "TCTRL[3],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xD0++0x03
line.long 0x00 "TCTRL[4],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xD4++0x03
line.long 0x00 "TCTRL[5],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xD8++0x03
line.long 0x00 "TCTRL[6],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xDC++0x03
line.long 0x00 "TCTRL[7],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xE0++0x03
line.long 0x00 "TCTRL[8],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xE4++0x03
line.long 0x00 "TCTRL[9],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xE8++0x03
line.long 0x00 "TCTRL[10],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xEC++0x03
line.long 0x00 "TCTRL[11],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xF0++0x03
line.long 0x00 "TCTRL[12],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xF4++0x03
line.long 0x00 "TCTRL[13],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xF8++0x03
line.long 0x00 "TCTRL[14],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0xFC++0x03
line.long 0x00 "TCTRL[15],Trigger Control Register"
bitfld.long 0x00 24.--27. " TCMD     ,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,,,,,,15: CMD15 is executed"
textline "                    "
bitfld.long 0x00 16.--19. " TDLY     ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " TPRI     ,Trigger priority setting" "0: Set to highest priority. Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,,,,,,15: Set to lowest priority. Level 16"
textline "                    "
bitfld.long 0x00 0. " HTEN     ,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
group.long 0x100++0x03
line.long 0x00 "CMDL1,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x104++0x03
line.long 0x00 "CMDH1,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
textline "                    "
bitfld.long 0x00 0.--1. " CMPEN    ,Compare Function Enable" "0: Compare disabled,,2: Compare enabled,3: Compare enabled"
group.long 0x108++0x03
line.long 0x00 "CMDL2,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x10C++0x03
line.long 0x00 "CMDH2,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
textline "                    "
bitfld.long 0x00 0.--1. " CMPEN    ,Compare Function Enable" "0: Compare disabled,,2: Compare enabled,3: Compare enabled"
group.long 0x110++0x03
line.long 0x00 "CMDL3,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x114++0x03
line.long 0x00 "CMDH3,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
textline "                    "
bitfld.long 0x00 0.--1. " CMPEN    ,Compare Function Enable" "0: Compare disabled,,2: Compare enabled,3: Compare enabled"
group.long 0x118++0x03
line.long 0x00 "CMDL4,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x11C++0x03
line.long 0x00 "CMDH4,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
textline "                    "
bitfld.long 0x00 0.--1. " CMPEN    ,Compare Function Enable" "0: Compare disabled,,2: Compare enabled,3: Compare enabled"
group.long 0x120++0x03
line.long 0x00 "CMDL5,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x124++0x03
line.long 0x00 "CMDH5,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x128++0x03
line.long 0x00 "CMDL6,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x12C++0x03
line.long 0x00 "CMDH6,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x130++0x03
line.long 0x00 "CMDL7,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x134++0x03
line.long 0x00 "CMDH7,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x138++0x03
line.long 0x00 "CMDL8,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x13C++0x03
line.long 0x00 "CMDH8,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x140++0x03
line.long 0x00 "CMDL9,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x144++0x03
line.long 0x00 "CMDH9,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x148++0x03
line.long 0x00 "CMDL10,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x14C++0x03
line.long 0x00 "CMDH10,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x150++0x03
line.long 0x00 "CMDL11,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x154++0x03
line.long 0x00 "CMDH11,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x158++0x03
line.long 0x00 "CMDL12,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x15C++0x03
line.long 0x00 "CMDH12,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x160++0x03
line.long 0x00 "CMDL13,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x164++0x03
line.long 0x00 "CMDH13,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x168++0x03
line.long 0x00 "CMDL14,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x16C++0x03
line.long 0x00 "CMDH14,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x170++0x03
line.long 0x00 "CMDL15,ADC Command Low Buffer Register"
bitfld.long 0x00 13. " CSCALE   ,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
textline "                    "
bitfld.long 0x00 6. " DIFF     ,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
textline "                    "
bitfld.long 0x00 5. " ABSEL    ,A-side vs" "0: When DIFF=0b0. the associated A-side channel is converted as single-ended,1: When DIFF=0b0. the associated B-side channel is converted as single-ended"
textline "                    "
bitfld.long 0x00 0.--4. " ADCH     ,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,5: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,6: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,7: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,8: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,9: Select corresponding channel CHnA or CHnB or CHnA/CHnB pair,,,,,,,,,,,,,,,,,,,,,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x174++0x03
line.long 0x00 "CMDH15,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. " NEXT     ,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next command,2: Select corresponding CMD command buffer register as next command,3: Select corresponding CMD command buffer register as next command,4: Select corresponding CMD command buffer register as next command,5: Select corresponding CMD command buffer register as next command,6: Select corresponding CMD command buffer register as next command,7: Select corresponding CMD command buffer register as next command,8: Select corresponding CMD command buffer register as next command,9: Select corresponding CMD command buffer register as next command,,,,,,15: Select CMD15 command buffer register as next command"
textline "                    "
bitfld.long 0x00 16.--19. " LOOP     ,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,,,,,,15: Loop 15 times"
textline "                    "
bitfld.long 0x00 12.--14. " AVGS     ,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
textline "                    "
bitfld.long 0x00 8.--10. " STS      ,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 2^1 ADCK cycles. 5 ADCK cycles total sample time,2: 3 + 2^2 ADCK cycles. 7 ADCK cycles total sample time,3: 3 + 2^3 ADCK cycles. 11 ADCK cycles total sample time,4: 3 + 2^4 ADCK cycles. 19 ADCK cycles total sample time,5: 3 + 2^5 ADCK cycles. 35 ADCK cycles total sample time,6: 3 + 2^6 ADCK cycles. 67 ADCK cycles total sample time,7: 3 + 2^7 ADCK cycles. 131 ADCK cycles total sample time"
textline "                    "
bitfld.long 0x00 7. " LWI      ,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
group.long 0x200++0x03
line.long 0x00 "CV1,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. " CVH      ,Compare Value High"
textline "                    "
hexmask.long.word 0x00 0.--15. 1. " CVL      ,Compare Value Low"
group.long 0x204++0x03
line.long 0x00 "CV2,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. " CVH      ,Compare Value High"
textline "                    "
hexmask.long.word 0x00 0.--15. 1. " CVL      ,Compare Value Low"
group.long 0x208++0x03
line.long 0x00 "CV3,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. " CVH      ,Compare Value High"
textline "                    "
hexmask.long.word 0x00 0.--15. 1. " CVL      ,Compare Value Low"
group.long 0x20C++0x03
line.long 0x00 "CV4,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. " CVH      ,Compare Value High"
textline "                    "
hexmask.long.word 0x00 0.--15. 1. " CVL      ,Compare Value Low"
rgroup.long 0x300++0x03
line.long 0x00 "RESFIFO,ADC Data Result FIFO Register"
bitfld.long 0x00 31. " VALID    ,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid"
textline "                    "
bitfld.long 0x00 24.--27. " CMDSRC   ,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword in RESFIFO,1: CMD1 buffer used as control settings for this conversion,2: Corresponding command buffer used as control settings for this conversion,3: Corresponding command buffer used as control settings for this conversion,4: Corresponding command buffer used as control settings for this conversion,5: Corresponding command buffer used as control settings for this conversion,6: Corresponding command buffer used as control settings for this conversion,7: Corresponding command buffer used as control settings for this conversion,8: Corresponding command buffer used as control settings for this conversion,9: Corresponding command buffer used as control settings for this conversion,,,,,,15: CMD15 buffer used as control settings for this conversion"
textline "                    "
bitfld.long 0x00 20.--23. " LOOPCNT  ,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,,,,,,15: Result is from 16th conversion in command"
textline "                    "
bitfld.long 0x00 16.--19. " TSRC     ,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this conversion,3: Corresponding trigger source initiated this conversion,4: Corresponding trigger source initiated this conversion,5: Corresponding trigger source initiated this conversion,6: Corresponding trigger source initiated this conversion,7: Corresponding trigger source initiated this conversion,8: Corresponding trigger source initiated this conversion,9: Corresponding trigger source initiated this conversion,,,,,,15: Trigger source 15 initiated this conversion"
textline "                    "
hexmask.long.word 0x00 0.--15. 1. " D        ,Data result"
width 0x0B
tree.end
tree.end
tree "AHB_SECURE_CTRL"
base ad:0x40148000
width 27.
group.long 0x10++0x03
line.long 0x00 "ROM_MEM_RULE[0],Memory ROM Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x14++0x03
line.long 0x00 "ROM_MEM_RULE[1],Memory ROM Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x18++0x03
line.long 0x00 "ROM_MEM_RULE[2],Memory ROM Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1C++0x03
line.long 0x00 "ROM_MEM_RULE[3],Memory ROM Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x30++0x03
line.long 0x00 "FLEXSPI0_REGION0_RULE[0],FLEXSPI0 Region 0 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x34++0x03
line.long 0x00 "FLEXSPI0_REGION0_RULE[1],FLEXSPI0 Region 0 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x38++0x03
line.long 0x00 "FLEXSPI0_REGION0_RULE[2],FLEXSPI0 Region 0 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x3C++0x03
line.long 0x00 "FLEXSPI0_REGION0_RULE[3],FLEXSPI0 Region 0 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x40++0x03
line.long 0x00 "FLEXSPI0_REGION1_RULE0,FLEXSPI0 Region 1 Rule 0 Register"
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x50++0x03
line.long 0x00 "FLEXSPI0_REGION2_RULE0,FLEXSPI0 Region 2 Rule 0 Register"
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x60++0x03
line.long 0x00 "FLEXSPI0_REGION3_RULE0,FLEXSPI0 Region 3 Rule 0 Register"
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x70++0x03
line.long 0x00 "FLEXSPI0_REGION4_RULE0,FLEXSPI0 Region 4 Rule 0 Register"
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x90++0x03
line.long 0x00 "RAM00_RULE[0],SRAM Partition 00 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x94++0x03
line.long 0x00 "RAM00_RULE[1],SRAM Partition 00 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x98++0x03
line.long 0x00 "RAM00_RULE[2],SRAM Partition 00 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x9C++0x03
line.long 0x00 "RAM00_RULE[3],SRAM Partition 00 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xA0++0x03
line.long 0x00 "RAM01_RULE[0],SRAM Partition 01 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xA4++0x03
line.long 0x00 "RAM01_RULE[1],SRAM Partition 01 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xA8++0x03
line.long 0x00 "RAM01_RULE[2],SRAM Partition 01 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xAC++0x03
line.long 0x00 "RAM01_RULE[3],SRAM Partition 01 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xC0++0x03
line.long 0x00 "RAM02_RULE[0],SRAM Partition 02 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xC4++0x03
line.long 0x00 "RAM02_RULE[1],SRAM Partition 02 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xC8++0x03
line.long 0x00 "RAM02_RULE[2],SRAM Partition 02 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xCC++0x03
line.long 0x00 "RAM02_RULE[3],SRAM Partition 02 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xD0++0x03
line.long 0x00 "RAM03_RULE[0],SRAM Partition 03 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xD4++0x03
line.long 0x00 "RAM03_RULE[1],SRAM Partition 03 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xD8++0x03
line.long 0x00 "RAM03_RULE[2],SRAM Partition 03 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xDC++0x03
line.long 0x00 "RAM03_RULE[3],SRAM Partition 03 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xF0++0x03
line.long 0x00 "RAM04_RULE[0],SRAM Partition 04 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xF4++0x03
line.long 0x00 "RAM04_RULE[1],SRAM Partition 04 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xF8++0x03
line.long 0x00 "RAM04_RULE[2],SRAM Partition 04 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0xFC++0x03
line.long 0x00 "RAM04_RULE[3],SRAM Partition 04 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x100++0x03
line.long 0x00 "RAM05_RULE[0],SRAM Partition 05 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x104++0x03
line.long 0x00 "RAM05_RULE[1],SRAM Partition 05 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x108++0x03
line.long 0x00 "RAM05_RULE[2],SRAM Partition 05 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x10C++0x03
line.long 0x00 "RAM05_RULE[3],SRAM Partition 05 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x110++0x03
line.long 0x00 "RAM06_RULE[0],SRAM Partition 06 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x114++0x03
line.long 0x00 "RAM06_RULE[1],SRAM Partition 06 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x118++0x03
line.long 0x00 "RAM06_RULE[2],SRAM Partition 06 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x11C++0x03
line.long 0x00 "RAM06_RULE[3],SRAM Partition 06 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x120++0x03
line.long 0x00 "RAM07_RULE[0],SRAM Partition 07 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x124++0x03
line.long 0x00 "RAM07_RULE[1],SRAM Partition 07 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x128++0x03
line.long 0x00 "RAM07_RULE[2],SRAM Partition 07 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x12C++0x03
line.long 0x00 "RAM07_RULE[3],SRAM Partition 07 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x140++0x03
line.long 0x00 "RAM08_RULE[0],SRAM Partition 08 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x144++0x03
line.long 0x00 "RAM08_RULE[1],SRAM Partition 08 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x148++0x03
line.long 0x00 "RAM08_RULE[2],SRAM Partition 08 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x14C++0x03
line.long 0x00 "RAM08_RULE[3],SRAM Partition 08 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x150++0x03
line.long 0x00 "RAM09_RULE[0],SRAM Partition 09 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x154++0x03
line.long 0x00 "RAM09_RULE[1],SRAM Partition 09 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x158++0x03
line.long 0x00 "RAM09_RULE[2],SRAM Partition 09 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x15C++0x03
line.long 0x00 "RAM09_RULE[3],SRAM Partition 09 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x160++0x03
line.long 0x00 "RAM10_RULE[0],SRAM Partition 10 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x164++0x03
line.long 0x00 "RAM10_RULE[1],SRAM Partition 10 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x168++0x03
line.long 0x00 "RAM10_RULE[2],SRAM Partition 10 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x16C++0x03
line.long 0x00 "RAM10_RULE[3],SRAM Partition 10 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x170++0x03
line.long 0x00 "RAM11_RULE[0],SRAM Partition 11 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x174++0x03
line.long 0x00 "RAM11_RULE[1],SRAM Partition 11 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x178++0x03
line.long 0x00 "RAM11_RULE[2],SRAM Partition 11 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x17C++0x03
line.long 0x00 "RAM11_RULE[3],SRAM Partition 11 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x190++0x03
line.long 0x00 "RAM12_RULE[0],SRAM Partition 12 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x194++0x03
line.long 0x00 "RAM12_RULE[1],SRAM Partition 12 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x198++0x03
line.long 0x00 "RAM12_RULE[2],SRAM Partition 12 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x19C++0x03
line.long 0x00 "RAM12_RULE[3],SRAM Partition 12 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1A0++0x03
line.long 0x00 "RAM13_RULE[0],SRAM Partition 13 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1A4++0x03
line.long 0x00 "RAM13_RULE[1],SRAM Partition 13 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1A8++0x03
line.long 0x00 "RAM13_RULE[2],SRAM Partition 13 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1AC++0x03
line.long 0x00 "RAM13_RULE[3],SRAM Partition 13 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1B0++0x03
line.long 0x00 "RAM14_RULE[0],SRAM Partition 14 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1B4++0x03
line.long 0x00 "RAM14_RULE[1],SRAM Partition 14 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1B8++0x03
line.long 0x00 "RAM14_RULE[2],SRAM Partition 14 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1BC++0x03
line.long 0x00 "RAM14_RULE[3],SRAM Partition 14 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1C0++0x03
line.long 0x00 "RAM15_RULE[0],SRAM Partition 15 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1C4++0x03
line.long 0x00 "RAM15_RULE[1],SRAM Partition 15 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1C8++0x03
line.long 0x00 "RAM15_RULE[2],SRAM Partition 15 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1CC++0x03
line.long 0x00 "RAM15_RULE[3],SRAM Partition 15 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1E0++0x03
line.long 0x00 "RAM16_RULE[0],SRAM Partition 16 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1E4++0x03
line.long 0x00 "RAM16_RULE[1],SRAM Partition 16 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1E8++0x03
line.long 0x00 "RAM16_RULE[2],SRAM Partition 16 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1EC++0x03
line.long 0x00 "RAM16_RULE[3],SRAM Partition 16 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1F0++0x03
line.long 0x00 "RAM17_RULE[0],SRAM Partition 17 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1F4++0x03
line.long 0x00 "RAM17_RULE[1],SRAM Partition 17 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1F8++0x03
line.long 0x00 "RAM17_RULE[2],SRAM Partition 17 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x1FC++0x03
line.long 0x00 "RAM17_RULE[3],SRAM Partition 17 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x200++0x03
line.long 0x00 "RAM18_RULE[0],SRAM Partition 18 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x204++0x03
line.long 0x00 "RAM18_RULE[1],SRAM Partition 18 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x208++0x03
line.long 0x00 "RAM18_RULE[2],SRAM Partition 18 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x20C++0x03
line.long 0x00 "RAM18_RULE[3],SRAM Partition 18 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x210++0x03
line.long 0x00 "RAM19_RULE[0],SRAM Partition 19 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x214++0x03
line.long 0x00 "RAM19_RULE[1],SRAM Partition 19 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x218++0x03
line.long 0x00 "RAM19_RULE[2],SRAM Partition 19 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x21C++0x03
line.long 0x00 "RAM19_RULE[3],SRAM Partition 19 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x230++0x03
line.long 0x00 "RAM20_RULE[0],SRAM Partition 20 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x234++0x03
line.long 0x00 "RAM20_RULE[1],SRAM Partition 20 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x238++0x03
line.long 0x00 "RAM20_RULE[2],SRAM Partition 20 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x23C++0x03
line.long 0x00 "RAM20_RULE[3],SRAM Partition 20 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x240++0x03
line.long 0x00 "RAM21_RULE[0],SRAM Partition 21 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x244++0x03
line.long 0x00 "RAM21_RULE[1],SRAM Partition 21 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x248++0x03
line.long 0x00 "RAM21_RULE[2],SRAM Partition 21 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x24C++0x03
line.long 0x00 "RAM21_RULE[3],SRAM Partition 21 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x250++0x03
line.long 0x00 "RAM22_RULE[0],SRAM Partition 22 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x254++0x03
line.long 0x00 "RAM22_RULE[1],SRAM Partition 22 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x258++0x03
line.long 0x00 "RAM22_RULE[2],SRAM Partition 22 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x25C++0x03
line.long 0x00 "RAM22_RULE[3],SRAM Partition 22 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x260++0x03
line.long 0x00 "RAM23_RULE[0],SRAM Partition 23 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x264++0x03
line.long 0x00 "RAM23_RULE[1],SRAM Partition 23 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x268++0x03
line.long 0x00 "RAM23_RULE[2],SRAM Partition 23 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x26C++0x03
line.long 0x00 "RAM23_RULE[3],SRAM Partition 23 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x280++0x03
line.long 0x00 "RAM24_RULE[0],SRAM Partition 24 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x284++0x03
line.long 0x00 "RAM24_RULE[1],SRAM Partition 24 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x288++0x03
line.long 0x00 "RAM24_RULE[2],SRAM Partition 24 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x28C++0x03
line.long 0x00 "RAM24_RULE[3],SRAM Partition 24 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x290++0x03
line.long 0x00 "RAM25_RULE[0],SRAM Partition 25 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x294++0x03
line.long 0x00 "RAM25_RULE[1],SRAM Partition 25 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x298++0x03
line.long 0x00 "RAM25_RULE[2],SRAM Partition 25 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x29C++0x03
line.long 0x00 "RAM25_RULE[3],SRAM Partition 25 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2A0++0x03
line.long 0x00 "RAM26_RULE[0],SRAM Partition 26 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2A4++0x03
line.long 0x00 "RAM26_RULE[1],SRAM Partition 26 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2A8++0x03
line.long 0x00 "RAM26_RULE[2],SRAM Partition 26 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2AC++0x03
line.long 0x00 "RAM26_RULE[3],SRAM Partition 26 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2B0++0x03
line.long 0x00 "RAM27_RULE[0],SRAM Partition 27 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2B4++0x03
line.long 0x00 "RAM27_RULE[1],SRAM Partition 27 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2B8++0x03
line.long 0x00 "RAM27_RULE[2],SRAM Partition 27 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2BC++0x03
line.long 0x00 "RAM27_RULE[3],SRAM Partition 27 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2D0++0x03
line.long 0x00 "RAM28_RULE[0],SRAM Partition 28 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2D4++0x03
line.long 0x00 "RAM28_RULE[1],SRAM Partition 28 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2D8++0x03
line.long 0x00 "RAM28_RULE[2],SRAM Partition 28 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2DC++0x03
line.long 0x00 "RAM28_RULE[3],SRAM Partition 28 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2E0++0x03
line.long 0x00 "RAM29_RULE[0],SRAM Partition 29 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2E4++0x03
line.long 0x00 "RAM29_RULE[1],SRAM Partition 29 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2E8++0x03
line.long 0x00 "RAM29_RULE[2],SRAM Partition 29 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x2EC++0x03
line.long 0x00 "RAM29_RULE[3],SRAM Partition 29 Rule(n) Register"
bitfld.long 0x00 28.--29. " RULE7                             ,Rule 7" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 24.--25. " RULE6                             ,Rule 6" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 20.--21. " RULE5                             ,Rule 5" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,Rule 4" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " RULE3                             ,Rule 3" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,Rule 2" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,Rule 1" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,Rule 0" "0: Non-secure and non-privilege user access allowed,1: Non-secure and privilege access allowed,2: Secure and non-privilege user access allowed,3: Secure and privilege user access allowed"
group.long 0x320++0x03
line.long 0x00 "pif_hifi4_x_mem_rule0,Security access rules for HiFi 4 memory sectors (0x24000000--0x240FFFFF)"
bitfld.long 0x00 20.--21. " RULE5                             ,secure control rule5" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " RULE4                             ,secure control rule4" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,secure control rule1" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,secure control rule0" "0,1,2,3"
group.long 0x340++0x03
line.long 0x00 "apb_grp0_mem_rule0,Security access rules for APB Bridge 0 peripherals"
bitfld.long 0x00 24.--25. " PUFCTRL_RULE                      ,0x4000 6000--0x4000 6FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " IOPCTL_RULE                       ,0x4000 4000--0x4000 4FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " SYSCTL0_RULE                      ,0x4000 2000--0x4000 2FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " CLKCTL0_RULE                      ,0x4000 1000--0x4000 1FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RSTCTL0_RULE                      ,0x4000 0000--0x4000 0FFF" "0,1,2,3"
group.long 0x344++0x03
line.long 0x00 "apb_grp0_mem_rule1,Security access rules for APB Bridge 0 peripherals"
bitfld.long 0x00 28.--29. " UTICK_RULE                        ,0x4000 F000--0x4000 FFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 24.--25. " WWDT0_RULE                        ,0x4000 E000--0x4000 EFFF" "0,1,2,3"
group.long 0x350++0x03
line.long 0x00 "apb_grp1_mem_rule0,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 24.--25. " PERIPH_INPUT_MUX_RULE             ,0x4002 6000--0x4002 6FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 20.--21. " GPIO_INTR_CTRL_RULE               ,0x4002 5000--0x4002 5FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " SYSCTL1_RULE                      ,0x4002 2000--0x4002 2FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " CLKCTL1_RULE                      ,0x4002 1000--0x4002 1FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RSTCTL1_RULE                      ,0x4002 0000--0x4002 0FFF" "0,1,2,3"
group.long 0x354++0x03
line.long 0x00 "apb_grp1_mem_rule1,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 28.--29. " FREQME_RULE                       ,0x4002 F000--0x4002 FFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 24.--25. " WWDT1_RULE                        ,0x4002 E000--0x4002 EFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 20.--21. " MRT_RULE                          ,0x4002 D000--0x4002 DFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " CT32BIT4_RULE                     ,0x4002 C000--0x4002 CFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " CT32BIT3_RULE                     ,0x4002 B000--0x4002 BFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " CT32BIT2_RULE                     ,0x4002 A000--0x4002 AFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " CT32BIT1_RULE                     ,0x4002 9000--0x4002 9FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " CT32BIT0_RULE                     ,0x4002 8000--0x4002 8FFF" "0,1,2,3"
group.long 0x358++0x03
line.long 0x00 "apb_grp1_mem_rule2,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 24.--25. " I3C0_RULE                         ,0x4003 6000--0x4003 6FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RTC_RULE                          ,0x4003 0000--0x4003 0FFF" "0,1,2,3"
group.long 0x360++0x03
line.long 0x00 "ahb_periph0_slave_rule0,Security access rules for AHB peripheral slaves area 0x40100000--0x4010FFFF"
bitfld.long 0x00 28.--29. " DEBUG_MAILBOX_RULE                ,0x4010F000--0x4010FFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 24.--25. " FLEXCOMM3_RULE                    ,0x40109000--0x40109FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 20.--21. " FLEXCOMM2_RULE                    ,0x40108000--0x40108FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " FLEXCOMM1_RULE                    ,0x40107000--0x40107FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " FLEXCOMM0_RULE                    ,0x40106000--0x40106FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " DMA1_RULE                         ,0x40105000--0x40105FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " DMA0_RULE                         ,0x40104000--0x40104FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " HSGPIO_RULE                       ,0x40100000--0x40103FFF" "0,1,2,3"
group.long 0x370++0x03
line.long 0x00 "aips_bridge0_mem_rule0,0x40110000--0x4011FFFF"
bitfld.long 0x00 16.--17. " OS_EVENT_TIMER_DSP_RULE           ,0x4011 4000--0x4011 4FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " OS_EVENT_TIMER_M33_RULE           ,0x4011 3000--0x4011 3FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " SEMAPHORE_RULE                    ,0x4011 2000--0x4011 2FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " MU0_DSP_RULE                      ,0x4011 1000--0x4011 1FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " MU0_M33_RULE                      ,0x4011 0000--0x4011 0FFF" "0,1,2,3"
group.long 0x380++0x03
line.long 0x00 "ahb_periph1_slave_rule0,the memory map is 0x40120000--0x40127FFF"
bitfld.long 0x00 28.--29. " FLEXCOMM15_RULE                   ,0x40127000--0x40127FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 24.--25. " FLEXCOMM14_RULE                   ,0x40126000--0x40126FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 20.--21. " FLEXCOMM7_RULE                    ,0x40125000--0x40125FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " FLEXCOMM6_RULE                    ,0x40124000--0x40124FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " FLEXCOMM5_RULE                    ,0x40123000--0x40123FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " FLEXCOMM4_RULE                    ,0x40122000--0x40122FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " DMIC_RULE                         ,0x40121000--0x40121FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " CRC_RULE                          ,Security access rules for AHB peripheral slaves area 0x40120000--0x40120FFF" "0,1,2,3"
group.long 0x3A0++0x03
line.long 0x00 "aips_bridge1_mem_rule0,Security access rules for AIPS Bridge peripherals"
bitfld.long 0x00 28.--29. " SDIO1_RULE                        ,0x4013 7000--0x4013 7FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 24.--25. " SDIO0_RULE                        ,0x4013 6000--0x4013 6FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 16.--17. " FLEXSPI_AND_OTFAD_RULE            ,0x4013 4000--0x4013 4FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " OTP_RULE3                         ,0x4013 3000--0x4013 3FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " OTP_RULE2                         ,0x4013 2000--0x4013 2FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " OTP_RULE1                         ,0x4013 1000--0x4013 1FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " OTP_RULE0                         ,0x4013 0000--0x4013 0FFF" "0,1,2,3"
group.long 0x3A4++0x03
line.long 0x00 "aips_bridge1_mem_rule1,Security access rules for AIPS Bridge peripherals"
bitfld.long 0x00 12.--13. " USB_HS_PHY_RULE                   ,0x4013 B000--0x4013 BFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " ADC0_RULE                         ,0x4013 A000--0x4013 AFFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " ACMP0_RULE                        ,0x4013 9000--0x4013 9FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RNG_RULE                          ,0x4013 8000--0x4013 8FFF" "0,1,2,3"
group.long 0x3B0++0x03
line.long 0x00 "ahb_periph2_slave_rule0,Security access rules for AHB peripheral slaves area 0x40140000--0x4014BFFF"
bitfld.long 0x00 12.--13. " SCT_RULE                          ,0x40146000--0x40146FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " USB_HS_HOST_RULE                  ,0x40145000--0x40145FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " USB_HS_DEV_RULE                   ,0x40144000--0x40144FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " USB_HS_RAM_RULE                   ,0x40140000--0x40143FFF" "0,1,2,3"
group.long 0x3C0++0x03
line.long 0x00 "security_ctrl_mem_rule0,0x40148000--0x4014BFFF"
bitfld.long 0x00 12.--13. " RULE3                             ,secure control rule0" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " RULE2                             ,secure control rule0" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " RULE1                             ,secure control rule0" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " RULE0                             ,secure control rule0" "0,1,2,3"
group.long 0x3D0++0x03
line.long 0x00 "ahb_periph3_slave_rule0,Security access rules for AHB peripheral slaves area 0x40150000--0x40158FFF"
bitfld.long 0x00 16.--17. " HASH_RULE                         ,0x40158000--0x40158FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 12.--13. " SECURE_GPIO_RULE                  ,0x40154000--0x40157FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 8.--9. " CASPER_RAM_RULE                   ,0x40152000--0x40152FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 4.--5. " CASPER_COPRO_RULE                 ,0x40151000--0x40151FFF" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--1. " PQ_COPRO_RULE                     ,0x40150000--0x40150FFF" "0,1,2,3"
rgroup.long 0xE00++0x03
line.long 0x00 "sec_vio_addr[0],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE04++0x03
line.long 0x00 "sec_vio_addr[1],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE08++0x03
line.long 0x00 "sec_vio_addr[2],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE0C++0x03
line.long 0x00 "sec_vio_addr[3],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE10++0x03
line.long 0x00 "sec_vio_addr[4],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE14++0x03
line.long 0x00 "sec_vio_addr[5],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE18++0x03
line.long 0x00 "sec_vio_addr[6],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE1C++0x03
line.long 0x00 "sec_vio_addr[7],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE20++0x03
line.long 0x00 "sec_vio_addr[8],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE24++0x03
line.long 0x00 "sec_vio_addr[9],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE28++0x03
line.long 0x00 "sec_vio_addr[10],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE2C++0x03
line.long 0x00 "sec_vio_addr[11],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE30++0x03
line.long 0x00 "sec_vio_addr[12],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE34++0x03
line.long 0x00 "sec_vio_addr[13],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE38++0x03
line.long 0x00 "sec_vio_addr[14],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE3C++0x03
line.long 0x00 "sec_vio_addr[15],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE40++0x03
line.long 0x00 "sec_vio_addr[16],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE44++0x03
line.long 0x00 "sec_vio_addr[17],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. " SEC_VIO_ADDR                      ,security violation address for AHB layer"
rgroup.long 0xE80++0x03
line.long 0x00 "sec_vio_misc_info[0],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE84++0x03
line.long 0x00 "sec_vio_misc_info[1],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE88++0x03
line.long 0x00 "sec_vio_misc_info[2],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE8C++0x03
line.long 0x00 "sec_vio_misc_info[3],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE90++0x03
line.long 0x00 "sec_vio_misc_info[4],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE94++0x03
line.long 0x00 "sec_vio_misc_info[5],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE98++0x03
line.long 0x00 "sec_vio_misc_info[6],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xE9C++0x03
line.long 0x00 "sec_vio_misc_info[7],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEA0++0x03
line.long 0x00 "sec_vio_misc_info[8],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEA4++0x03
line.long 0x00 "sec_vio_misc_info[9],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEA8++0x03
line.long 0x00 "sec_vio_misc_info[10],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEAC++0x03
line.long 0x00 "sec_vio_misc_info[11],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEB0++0x03
line.long 0x00 "sec_vio_misc_info[12],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEB4++0x03
line.long 0x00 "sec_vio_misc_info[13],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEB8++0x03
line.long 0x00 "sec_vio_misc_info[14],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEBC++0x03
line.long 0x00 "sec_vio_misc_info[15],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEC0++0x03
line.long 0x00 "sec_vio_misc_info[16],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
rgroup.long 0xEC4++0x03
line.long 0x00 "sec_vio_misc_info[17],most recent security violation miscellaneous information for AHB layer n"
bitfld.long 0x00 8.--11. " SEC_VIO_INFO_MASTER               ,security violation master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--7. " SEC_VIO_INFO_MASTER_SEC_LEVEL     ,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and p.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 1. " SEC_VIO_INFO_DATA_ACCESS          ,security violation access data/code indicator. 0: code. 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " SEC_VIO_INFO_WRITE                ,security violation access read/write indicator. 0: read. 1: write" "0,1"
group.long 0xF00++0x03
line.long 0x00 "SEC_VIO_INFO_VALID,security violation address/information registers valid flags"
bitfld.long 0x00 17. " VIO_INFO_VALID17                  ,violation information valid flag for AHB layer 17" "0,1"
textline "                                    "
bitfld.long 0x00 16. " VIO_INFO_VALID16                  ,violation information valid flag for AHB layer 16" "0,1"
textline "                                    "
bitfld.long 0x00 15. " VIO_INFO_VALID15                  ,violation information valid flag for AHB layer 15" "0,1"
textline "                                    "
bitfld.long 0x00 14. " VIO_INFO_VALID14                  ,violation information valid flag for AHB layer 14" "0,1"
textline "                                    "
bitfld.long 0x00 13. " VIO_INFO_VALID13                  ,violation information valid flag for AHB layer 13" "0,1"
textline "                                    "
bitfld.long 0x00 12. " VIO_INFO_VALID12                  ,violation information valid flag for AHB layer 12" "0,1"
textline "                                    "
bitfld.long 0x00 11. " VIO_INFO_VALID11                  ,violation information valid flag for AHB layer 11" "0,1"
textline "                                    "
bitfld.long 0x00 10. " VIO_INFO_VALID10                  ,violation information valid flag for AHB layer 10" "0,1"
textline "                                    "
bitfld.long 0x00 9. " VIO_INFO_VALID9                   ,violation information valid flag for AHB layer 9" "0,1"
textline "                                    "
bitfld.long 0x00 8. " VIO_INFO_VALID8                   ,violation information valid flag for AHB layer 8" "0,1"
textline "                                    "
bitfld.long 0x00 7. " VIO_INFO_VALID7                   ,violation information valid flag for AHB layer 7" "0,1"
textline "                                    "
bitfld.long 0x00 6. " VIO_INFO_VALID6                   ,violation information valid flag for AHB layer 6" "0,1"
textline "                                    "
bitfld.long 0x00 5. " VIO_INFO_VALID5                   ,violation information valid flag for AHB layer 5" "0,1"
textline "                                    "
bitfld.long 0x00 4. " VIO_INFO_VALID4                   ,violation information valid flag for AHB layer 4" "0,1"
textline "                                    "
bitfld.long 0x00 3. " VIO_INFO_VALID3                   ,violation information valid flag for AHB layer 3" "0,1"
textline "                                    "
bitfld.long 0x00 2. " VIO_INFO_VALID2                   ,violation information valid flag for AHB layer 2" "0,1"
textline "                                    "
bitfld.long 0x00 1. " VIO_INFO_VALID1                   ,violation information valid flag for AHB layer 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " VIO_INFO_VALID0                   ,violation information valid flag for AHB layer 0" "0,1"
group.long 0xF80++0x03
line.long 0x00 "SEC_GPIO_MASK0,Secure GPIO mask for port 0 pins"
bitfld.long 0x00 31. " PIO0_PIN31_SEC_MASK               ,0 : Pin PIO0_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO0_PIN30_SEC_MASK               ,0 : Pin PIO0_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO0_PIN29_SEC_MASK               ,0 : Pin PIO0_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO0_PIN28_SEC_MASK               ,0 : Pin PIO0_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO0_PIN27_SEC_MASK               ,0 : Pin PIO0_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO0_PIN26_SEC_MASK               ,0 : Pin PIO0_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO0_PIN25_SEC_MASK               ,0 : Pin PIO0_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO0_PIN24_SEC_MASK               ,0 : Pin PIO0_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO0_PIN23_SEC_MASK               ,0 : Pin PIO0_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO0_PIN22_SEC_MASK               ,0 : Pin PIO0_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO0_PIN21_SEC_MASK               ,0 : Pin PIO0_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO0_PIN20_SEC_MASK               ,0 : Pin PIO0_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO0_PIN19_SEC_MASK               ,0 : Pin PIO0_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO0_PIN18_SEC_MASK               ,0 : Pin PIO0_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO0_PIN17_SEC_MASK               ,0 : Pin PIO0_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO0_PIN16_SEC_MASK               ,0 : Pin PIO0_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO0_PIN15_SEC_MASK               ,0 : Pin PIO0_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO0_PIN14_SEC_MASK               ,0 : Pin PIO0_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO0_PIN13_SEC_MASK               ,0 : Pin PIO0_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO0_PIN12_SEC_MASK               ,0 : Pin PIO0_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO0_PIN11_SEC_MASK               ,0 : Pin PIO0_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO0_PIN10_SEC_MASK               ,0 : Pin PIO0_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO0_PIN9_SEC_MASK                ,0 : Pin PIO0_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO0_PIN8_SEC_MASK                ,0 : Pin PIO0_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO0_PIN7_SEC_MASK                ,0 : Pin PIO0_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO0_PIN6_SEC_MASK                ,0 : Pin PIO0_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO0_PIN5_SEC_MASK                ,0 : Pin PIO0_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO0_PIN4_SEC_MASK                ,0 : Pin PIO0_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO0_PIN3_SEC_MASK                ,0 : Pin PIO0_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO0_PIN2_SEC_MASK                ,0 : Pin PIO0_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO0_PIN1_SEC_MASK                ,0 : Pin PIO0_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO0_PIN0_SEC_MASK                ,0 : Pin PIO0_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF84++0x03
line.long 0x00 "SEC_GPIO_MASK1,Secure GPIO mask for port 1 pins"
bitfld.long 0x00 31. " PIO1_PIN31_SEC_MASK               ,0 : Pin PIO1_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO1_PIN30_SEC_MASK               ,0 : Pin PIO1_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO1_PIN29_SEC_MASK               ,0 : Pin PIO1_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO1_PIN28_SEC_MASK               ,0 : Pin PIO1_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO1_PIN27_SEC_MASK               ,0 : Pin PIO1_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO1_PIN26_SEC_MASK               ,0 : Pin PIO1_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO1_PIN25_SEC_MASK               ,0 : Pin PIO1_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO1_PIN24_SEC_MASK               ,0 : Pin PIO1_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO1_PIN23_SEC_MASK               ,0 : Pin PIO1_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO1_PIN22_SEC_MASK               ,0 : Pin PIO1_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO1_PIN21_SEC_MASK               ,0 : Pin PIO1_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO1_PIN20_SEC_MASK               ,0 : Pin PIO1_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO1_PIN19_SEC_MASK               ,0 : Pin PIO1_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO1_PIN18_SEC_MASK               ,0 : Pin PIO1_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO1_PIN17_SEC_MASK               ,0 : Pin PIO1_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO1_PIN16_SEC_MASK               ,0 : Pin PIO1_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO1_PIN15_SEC_MASK               ,0 : Pin PIO1_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO1_PIN14_SEC_MASK               ,0 : Pin PIO1_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO1_PIN13_SEC_MASK               ,0 : Pin PIO1_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO1_PIN12_SEC_MASK               ,0 : Pin PIO1_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO1_PIN11_SEC_MASK               ,0 : Pin PIO1_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO1_PIN10_SEC_MASK               ,0 : Pin PIO1_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO1_PIN9_SEC_MASK                ,0 : Pin PIO1_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO1_PIN8_SEC_MASK                ,0 : Pin PIO1_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO1_PIN7_SEC_MASK                ,0 : Pin PIO1_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO1_PIN6_SEC_MASK                ,0 : Pin PIO1_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO1_PIN5_SEC_MASK                ,0 : Pin PIO1_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO1_PIN4_SEC_MASK                ,0 : Pin PIO1_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO1_PIN3_SEC_MASK                ,0 : Pin PIO1_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO1_PIN2_SEC_MASK                ,0 : Pin PIO1_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO1_PIN1_SEC_MASK                ,0 : Pin PIO1_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO1_PIN0_SEC_MASK                ,0 : Pin PIO1_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF88++0x03
line.long 0x00 "SEC_GPIO_MASK2,Secure GPIO mask for port 2 pins"
bitfld.long 0x00 31. " PIO2_PIN31_SEC_MASK               ,0 : Pin PIO2_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO2_PIN30_SEC_MASK               ,0 : Pin PIO2_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO2_PIN29_SEC_MASK               ,0 : Pin PIO2_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO2_PIN28_SEC_MASK               ,0 : Pin PIO2_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO2_PIN27_SEC_MASK               ,0 : Pin PIO2_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO2_PIN26_SEC_MASK               ,0 : Pin PIO2_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO2_PIN25_SEC_MASK               ,0 : Pin PIO2_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO2_PIN24_SEC_MASK               ,0 : Pin PIO2_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO2_PIN23_SEC_MASK               ,0 : Pin PIO2_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO2_PIN22_SEC_MASK               ,0 : Pin PIO2_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO2_PIN21_SEC_MASK               ,0 : Pin PIO2_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO2_PIN20_SEC_MASK               ,0 : Pin PIO2_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO2_PIN19_SEC_MASK               ,0 : Pin PIO2_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO2_PIN18_SEC_MASK               ,0 : Pin PIO2_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO2_PIN17_SEC_MASK               ,0 : Pin PIO2_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO2_PIN16_SEC_MASK               ,0 : Pin PIO2_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO2_PIN15_SEC_MASK               ,0 : Pin PIO2_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO2_PIN14_SEC_MASK               ,0 : Pin PIO2_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO2_PIN13_SEC_MASK               ,0 : Pin PIO2_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO2_PIN12_SEC_MASK               ,0 : Pin PIO2_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO2_PIN11_SEC_MASK               ,0 : Pin PIO2_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO2_PIN10_SEC_MASK               ,0 : Pin PIO2_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO2_PIN9_SEC_MASK                ,0 : Pin PIO2_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO2_PIN8_SEC_MASK                ,0 : Pin PIO2_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO2_PIN7_SEC_MASK                ,0 : Pin PIO2_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO2_PIN6_SEC_MASK                ,0 : Pin PIO2_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO2_PIN5_SEC_MASK                ,0 : Pin PIO2_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO2_PIN4_SEC_MASK                ,0 : Pin PIO2_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO2_PIN3_SEC_MASK                ,0 : Pin PIO2_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO2_PIN2_SEC_MASK                ,0 : Pin PIO2_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO2_PIN1_SEC_MASK                ,0 : Pin PIO2_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO2_PIN0_SEC_MASK                ,0 : Pin PIO2_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF8C++0x03
line.long 0x00 "SEC_GPIO_MASK3,Secure GPIO mask for port 3 pins"
bitfld.long 0x00 31. " PIO3_PIN31_SEC_MASK               ,0 : Pin PIO3_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO3_PIN30_SEC_MASK               ,0 : Pin PIO3_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO3_PIN29_SEC_MASK               ,0 : Pin PIO3_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO3_PIN28_SEC_MASK               ,0 : Pin PIO3_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO3_PIN27_SEC_MASK               ,0 : Pin PIO3_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO3_PIN26_SEC_MASK               ,0 : Pin PIO3_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO3_PIN25_SEC_MASK               ,0 : Pin PIO3_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO3_PIN24_SEC_MASK               ,0 : Pin PIO3_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO3_PIN23_SEC_MASK               ,0 : Pin PIO3_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO3_PIN22_SEC_MASK               ,0 : Pin PIO3_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO3_PIN21_SEC_MASK               ,0 : Pin PIO3_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO3_PIN20_SEC_MASK               ,0 : Pin PIO3_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO3_PIN19_SEC_MASK               ,0 : Pin PIO3_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO3_PIN18_SEC_MASK               ,0 : Pin PIO3_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO3_PIN17_SEC_MASK               ,0 : Pin PIO3_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO3_PIN16_SEC_MASK               ,0 : Pin PIO3_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO3_PIN15_SEC_MASK               ,0 : Pin PIO3_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO3_PIN14_SEC_MASK               ,0 : Pin PIO3_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO3_PIN13_SEC_MASK               ,0 : Pin PIO3_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO3_PIN12_SEC_MASK               ,0 : Pin PIO3_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO3_PIN11_SEC_MASK               ,0 : Pin PIO3_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO3_PIN10_SEC_MASK               ,0 : Pin PIO3_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO3_PIN9_SEC_MASK                ,0 : Pin PIO3_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO3_PIN8_SEC_MASK                ,0 : Pin PIO3_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO3_PIN7_SEC_MASK                ,0 : Pin PIO3_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO3_PIN6_SEC_MASK                ,0 : Pin PIO3_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO3_PIN5_SEC_MASK                ,0 : Pin PIO3_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO3_PIN4_SEC_MASK                ,0 : Pin PIO3_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO3_PIN3_SEC_MASK                ,0 : Pin PIO3_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO3_PIN2_SEC_MASK                ,0 : Pin PIO3_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO3_PIN1_SEC_MASK                ,0 : Pin PIO3_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO3_PIN0_SEC_MASK                ,0 : Pin PIO3_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF90++0x03
line.long 0x00 "SEC_GPIO_MASK4,Secure GPIO mask for port 4 pins"
bitfld.long 0x00 31. " PIO4_PIN31_SEC_MASK               ,0 : Pin PIO4_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO4_PIN30_SEC_MASK               ,0 : Pin PIO4_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO4_PIN29_SEC_MASK               ,0 : Pin PIO4_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO4_PIN28_SEC_MASK               ,0 : Pin PIO4_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO4_PIN27_SEC_MASK               ,0 : Pin PIO4_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO4_PIN26_SEC_MASK               ,0 : Pin PIO4_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO4_PIN25_SEC_MASK               ,0 : Pin PIO4_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO4_PIN24_SEC_MASK               ,0 : Pin PIO4_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO4_PIN23_SEC_MASK               ,0 : Pin PIO4_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO4_PIN22_SEC_MASK               ,0 : Pin PIO4_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO4_PIN21_SEC_MASK               ,0 : Pin PIO4_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO4_PIN20_SEC_MASK               ,0 : Pin PIO4_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO4_PIN19_SEC_MASK               ,0 : Pin PIO4_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO4_PIN18_SEC_MASK               ,0 : Pin PIO4_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO4_PIN17_SEC_MASK               ,0 : Pin PIO4_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO4_PIN16_SEC_MASK               ,0 : Pin PIO4_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO4_PIN15_SEC_MASK               ,0 : Pin PIO4_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO4_PIN14_SEC_MASK               ,0 : Pin PIO4_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO4_PIN13_SEC_MASK               ,0 : Pin PIO4_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO4_PIN12_SEC_MASK               ,0 : Pin PIO4_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO4_PIN11_SEC_MASK               ,0 : Pin PIO4_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO4_PIN10_SEC_MASK               ,0 : Pin PIO4_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO4_PIN9_SEC_MASK                ,0 : Pin PIO4_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO4_PIN8_SEC_MASK                ,0 : Pin PIO4_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO4_PIN7_SEC_MASK                ,0 : Pin PIO4_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO4_PIN6_SEC_MASK                ,0 : Pin PIO4_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO4_PIN5_SEC_MASK                ,0 : Pin PIO4_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO4_PIN4_SEC_MASK                ,0 : Pin PIO4_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO4_PIN3_SEC_MASK                ,0 : Pin PIO4_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO4_PIN2_SEC_MASK                ,0 : Pin PIO4_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO4_PIN1_SEC_MASK                ,0 : Pin PIO4_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO4_PIN0_SEC_MASK                ,0 : Pin PIO4_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF94++0x03
line.long 0x00 "SEC_GPIO_MASK5,Secure GPIO mask for port 5 pins"
bitfld.long 0x00 31. " PIO5_PIN31_SEC_MASK               ,0 : Pin PIO5_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO5_PIN30_SEC_MASK               ,0 : Pin PIO5_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO5_PIN29_SEC_MASK               ,0 : Pin PIO5_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO5_PIN28_SEC_MASK               ,0 : Pin PIO5_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO5_PIN27_SEC_MASK               ,0 : Pin PIO5_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO5_PIN26_SEC_MASK               ,0 : Pin PIO5_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO5_PIN25_SEC_MASK               ,0 : Pin PIO5_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO5_PIN24_SEC_MASK               ,0 : Pin PIO5_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO5_PIN23_SEC_MASK               ,0 : Pin PIO5_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO5_PIN22_SEC_MASK               ,0 : Pin PIO5_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO5_PIN21_SEC_MASK               ,0 : Pin PIO5_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO5_PIN20_SEC_MASK               ,0 : Pin PIO5_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO5_PIN19_SEC_MASK               ,0 : Pin PIO5_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO5_PIN18_SEC_MASK               ,0 : Pin PIO5_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO5_PIN17_SEC_MASK               ,0 : Pin PIO5_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO5_PIN16_SEC_MASK               ,0 : Pin PIO5_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO5_PIN15_SEC_MASK               ,0 : Pin PIO5_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO5_PIN14_SEC_MASK               ,0 : Pin PIO5_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO5_PIN13_SEC_MASK               ,0 : Pin PIO5_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO5_PIN12_SEC_MASK               ,0 : Pin PIO5_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO5_PIN11_SEC_MASK               ,0 : Pin PIO5_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO5_PIN10_SEC_MASK               ,0 : Pin PIO5_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO5_PIN9_SEC_MASK                ,0 : Pin PIO5_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO5_PIN8_SEC_MASK                ,0 : Pin PIO5_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO5_PIN7_SEC_MASK                ,0 : Pin PIO5_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO5_PIN6_SEC_MASK                ,0 : Pin PIO5_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO5_PIN5_SEC_MASK                ,0 : Pin PIO5_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO5_PIN4_SEC_MASK                ,0 : Pin PIO5_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO5_PIN3_SEC_MASK                ,0 : Pin PIO5_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO5_PIN2_SEC_MASK                ,0 : Pin PIO5_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO5_PIN1_SEC_MASK                ,0 : Pin PIO5_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO5_PIN0_SEC_MASK                ,0 : Pin PIO5_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF98++0x03
line.long 0x00 "SEC_GPIO_MASK6,Secure GPIO mask for port 6 pins"
bitfld.long 0x00 31. " PIO6_PIN31_SEC_MASK               ,0 : Pin PIO6_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO6_PIN30_SEC_MASK               ,0 : Pin PIO6_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO6_PIN29_SEC_MASK               ,0 : Pin PIO6_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO6_PIN28_SEC_MASK               ,0 : Pin PIO6_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO6_PIN27_SEC_MASK               ,0 : Pin PIO6_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO6_PIN26_SEC_MASK               ,0 : Pin PIO6_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO6_PIN25_SEC_MASK               ,0 : Pin PIO6_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO6_PIN24_SEC_MASK               ,0 : Pin PIO6_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO6_PIN23_SEC_MASK               ,0 : Pin PIO6_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO6_PIN22_SEC_MASK               ,0 : Pin PIO6_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO6_PIN21_SEC_MASK               ,0 : Pin PIO6_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO6_PIN20_SEC_MASK               ,0 : Pin PIO6_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO6_PIN19_SEC_MASK               ,0 : Pin PIO6_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO6_PIN18_SEC_MASK               ,0 : Pin PIO6_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO6_PIN17_SEC_MASK               ,0 : Pin PIO6_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO6_PIN16_SEC_MASK               ,0 : Pin PIO6_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO6_PIN15_SEC_MASK               ,0 : Pin PIO6_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO6_PIN14_SEC_MASK               ,0 : Pin PIO6_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO6_PIN13_SEC_MASK               ,0 : Pin PIO6_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO6_PIN12_SEC_MASK               ,0 : Pin PIO6_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO6_PIN11_SEC_MASK               ,0 : Pin PIO6_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO6_PIN10_SEC_MASK               ,0 : Pin PIO6_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO6_PIN9_SEC_MASK                ,0 : Pin PIO6_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO6_PIN8_SEC_MASK                ,0 : Pin PIO6_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO6_PIN7_SEC_MASK                ,0 : Pin PIO6_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO6_PIN6_SEC_MASK                ,0 : Pin PIO6_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO6_PIN5_SEC_MASK                ,0 : Pin PIO6_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO6_PIN4_SEC_MASK                ,0 : Pin PIO6_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO6_PIN3_SEC_MASK                ,0 : Pin PIO6_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO6_PIN2_SEC_MASK                ,0 : Pin PIO6_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO6_PIN1_SEC_MASK                ,0 : Pin PIO6_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO6_PIN0_SEC_MASK                ,0 : Pin PIO6_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xF9C++0x03
line.long 0x00 "SEC_GPIO_MASK7,Secure GPIO mask for port 7 pins"
bitfld.long 0x00 31. " PIO7_PIN31_SEC_MASK               ,0 : Pin PIO7_31 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " PIO7_PIN30_SEC_MASK               ,0 : Pin PIO7_30 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 29. " PIO7_PIN29_SEC_MASK               ,0 : Pin PIO7_29 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 28. " PIO7_PIN28_SEC_MASK               ,0 : Pin PIO7_28 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 27. " PIO7_PIN27_SEC_MASK               ,0 : Pin PIO7_27 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 26. " PIO7_PIN26_SEC_MASK               ,0 : Pin PIO7_26 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 25. " PIO7_PIN25_SEC_MASK               ,0 : Pin PIO7_25 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 24. " PIO7_PIN24_SEC_MASK               ,0 : Pin PIO7_24 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 23. " PIO7_PIN23_SEC_MASK               ,0 : Pin PIO7_23 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 22. " PIO7_PIN22_SEC_MASK               ,0 : Pin PIO7_22 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 21. " PIO7_PIN21_SEC_MASK               ,0 : Pin PIO7_21 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 20. " PIO7_PIN20_SEC_MASK               ,0 : Pin PIO7_20 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 19. " PIO7_PIN19_SEC_MASK               ,0 : Pin PIO7_19 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 18. " PIO7_PIN18_SEC_MASK               ,0 : Pin PIO7_18 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 17. " PIO7_PIN17_SEC_MASK               ,0 : Pin PIO7_17 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 16. " PIO7_PIN16_SEC_MASK               ,0 : Pin PIO7_16 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 15. " PIO7_PIN15_SEC_MASK               ,0 : Pin PIO7_15 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 14. " PIO7_PIN14_SEC_MASK               ,0 : Pin PIO7_14 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PIO7_PIN13_SEC_MASK               ,0 : Pin PIO7_13 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PIO7_PIN12_SEC_MASK               ,0 : Pin PIO7_12 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 11. " PIO7_PIN11_SEC_MASK               ,0 : Pin PIO7_11 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 10. " PIO7_PIN10_SEC_MASK               ,0 : Pin PIO7_10 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 9. " PIO7_PIN9_SEC_MASK                ,0 : Pin PIO7_9 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 8. " PIO7_PIN8_SEC_MASK                ,0 : Pin PIO7_8 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 7. " PIO7_PIN7_SEC_MASK                ,0 : Pin PIO7_7 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PIO7_PIN6_SEC_MASK                ,0 : Pin PIO7_6 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 5. " PIO7_PIN5_SEC_MASK                ,0 : Pin PIO7_5 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PIO7_PIN4_SEC_MASK                ,0 : Pin PIO7_4 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 3. " PIO7_PIN3_SEC_MASK                ,0 : Pin PIO7_3 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PIO7_PIN2_SEC_MASK                ,0 : Pin PIO7_2 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 1. " PIO7_PIN1_SEC_MASK                ,0 : Pin PIO7_1 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PIO7_PIN0_SEC_MASK                ,0 : Pin PIO7_0 state is readable by non-secure world through non-secure GPIO port control registers" "0,1"
group.long 0xFA0++0x03
line.long 0x00 "SEC_DSP_INT_MASK,secure general purpose register 8 used to mask interrupts to DSP for security purpose"
bitfld.long 0x00 31. " DSP_INTR31_SEC_MASK               ,0: INTR31 is invisible to DSP. 1: INTR31 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 30. " DSP_INTR30_SEC_MASK               ,0: INTR30 is invisible to DSP. 1: INTR30 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 29. " DSP_INTR29_SEC_MASK               ,0: INTR29 is invisible to DSP. 1: INTR29 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 28. " DSP_INTR28_SEC_MASK               ,0: INTR28 is invisible to DSP. 1: INTR28 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 27. " DSP_INTR27_SEC_MASK               ,0: INTR27 is invisible to DSP. 1: INTR27 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 26. " DSP_INTR26_SEC_MASK               ,0: INTR26 is invisible to DSP. 1: INTR26 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 25. " DSP_INTR25_SEC_MASK               ,0: INTR25 is invisible to DSP. 1: INTR25 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 24. " DSP_INTR24_SEC_MASK               ,0: INTR24 is invisible to DSP. 1: INTR24 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 23. " DSP_INTR23_SEC_MASK               ,0: INTR23 is invisible to DSP. 1: INTR23 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 22. " DSP_INTR22_SEC_MASK               ,0: INTR22 is invisible to DSP. 1: INTR22 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 21. " DSP_INTR21_SEC_MASK               ,0: INTR21 is invisible to DSP. 1: INTR21 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 20. " DSP_INTR20_SEC_MASK               ,0: INTR20 is invisible to DSP. 1: INTR20 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 19. " DSP_INTR19_SEC_MASK               ,0: INTR19 is invisible to DSP. 1: INTR19 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 18. " DSP_INTR18_SEC_MASK               ,0: INTR18 is invisible to DSP. 1: INTR18 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 17. " DSP_INTR17_SEC_MASK               ,0: INTR17 is invisible to DSP. 1: INTR17 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 16. " DSP_INTR16_SEC_MASK               ,0: INTR16 is invisible to DSP. 1: INTR16 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 15. " DSP_INTR15_SEC_MASK               ,0: INTR15 is invisible to DSP. 1: INTR15 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 14. " DSP_INTR14_SEC_MASK               ,0: INTR14 is invisible to DSP. 1: INTR14 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 13. " DSP_INTR13_SEC_MASK               ,0: INTR13 is invisible to DSP. 1: INTR13 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 12. " DSP_INTR12_SEC_MASK               ,0: INTR12 is invisible to DSP. 1: INTR12 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 11. " DSP_INTR11_SEC_MASK               ,0: INTR11 is invisible to DSP. 1: INTR11 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 10. " DSP_INTR10_SEC_MASK               ,0: INTR10 is invisible to DSP. 1: INTR10 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 9. " DSP_INTR9_SEC_MASK                ,0: INTR9 is invisible to DSP. 1: INTR9 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 8. " DSP_INTR8_SEC_MASK                ,0: INTR8 is invisible to DSP. 1: INTR8 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 7. " DSP_INTR7_SEC_MASK                ,0: INTR7 is invisible to DSP. 1: INTR7 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 6. " DSP_INTR6_SEC_MASK                ,0: INTR6 is invisible to DSP. 1: INTR6 is visible to DSP" "0,1"
textline "                                    "
bitfld.long 0x00 5. " DSP_INTR5_SEC_MASK                ,0: INTR5 is invisible to DSP. 1: INTR5 is visible to DSP" "0,1"
group.long 0xFBC++0x03
line.long 0x00 "SEC_MASK_LOCK,sec_gp_reg write-lock bits"
bitfld.long 0x00 16.--17. " SEC_DSP_INT_LOCK                  ,SEC_DSP_INT_MASK register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 14.--15. " SEC_GPIO_MASK7_LOCK               ,SEC_GPIO_MASK7 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 12.--13. " SEC_GPIO_MASK6_LOCK               ,SEC_GPIO_MASK6 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 10.--11. " SEC_GPIO_MASK5_LOCK               ,SEC_GPIO_MASK5 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 8.--9. " SEC_GPIO_MASK4_LOCK               ,SEC_GPIO_MASK4 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 6.--7. " SEC_GPIO_MASK3_LOCK               ,SEC_GPIO_MASK3 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 4.--5. " SEC_GPIO_MASK2_LOCK               ,SEC_GPIO_MASK2 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 2.--3. " SEC_GPIO_MASK1_LOCK               ,SEC_GPIO_MASK1 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 0.--1. " SEC_GPIO_MASK0_LOCK               ,SEC_GPIO_MASK0 register write-lock" ",1: Restrictive mode,2: WRITABLE,"
group.long 0xFD0++0x03
line.long 0x00 "MASTER_SEC_LEVEL,master secure level register"
bitfld.long 0x00 30.--31. " MASTER_SEC_LEVEL_LOCK             ,MASTER_SEC_LEVEL register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 14.--15. " SDIO1_SEC                         ,SDIO1 master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " SDIO0_SEC                         ,SDIO0 master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 10.--11. " DMA1_SEC                          ,DMA1 master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " DMA0_SEC                          ,DMA0 master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 6.--7. " DSP_SEC                           ,DSP master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " POWERQUAD_SEC                     ,POWERQUAD master secure level control" "0: Non-secure and Non-priviledge user access allowed,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xFD4++0x03
line.long 0x00 "MASTER_SEC_LEVEL_ANTI_POL,master secure level anti-pole register"
bitfld.long 0x00 30.--31. " MASTER_SEC_LEVEL_ANTI_POLE_LOCK   ,MASTER_SEC_LEVEL_ANTI_POL register write-lock" ",1: Restrictive mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 14.--15. " SDIO1_SEC                         ,SDIO1 master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 12.--13. " SDIO0_SEC                         ,SDIO0 master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 10.--11. " DMA1_SEC                          ,DMA1 master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 8.--9. " DMA0_SEC                          ,DMA0 master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 6.--7. " DSP_SEC                           ,DSP master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
textline "                                    "
bitfld.long 0x00 4.--5. " POWERQUAD_SEC                     ,POWERQUAD master secure level control anti-pole value (i" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access allowed"
group.long 0xFEC++0x03
line.long 0x00 "CM33_LOCK_REG,m33 lock control register"
bitfld.long 0x00 30.--31. " CM33_LOCK_REG_LOCK                ,CM33_LOCK_REG_LOCK write-lock" ",1: Restricted mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 8.--9. " LOCK_SAU                          ,m33 LOCKSAU write-lock" ",1: Restricted mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 6.--7. " LOCK_S_MPU                        ,m33 LOCKSMPU write-lock" ",1: Restricted mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 4.--5. " LOCK_S_VTOR                       ,m33 LOCKSVTOR write-lock" ",1: Restricted mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 2.--3. " LOCK_NS_MPU                       ,m33 LOCKNSMPU write-lock" ",1: Restricted mode,2: WRITABLE,"
textline "                                    "
bitfld.long 0x00 0.--1. " LOCK_NS_VTOR                      ,m33 LOCKNSVTOR write-lock" ",1: Restrictive mode,2: WRITABLE,"
group.long 0xFF8++0x03
line.long 0x00 "MISC_CTRL_DP_REG,secure control duplicate register"
bitfld.long 0x00 14.--15. " IDAU_ALL_NS                       ,Disable IDAU" ",1: IDAU is disabled,2: IDAU is enabled,"
textline "                                    "
bitfld.long 0x00 12.--13. " DISABLE_SMART_MASTER_STRICT_MODE  ,Disable smart master strict mode" ",1: Smart master in tier mode,2: Smart master in strict mode,"
textline "                                    "
bitfld.long 0x00 10.--11. " DISABLE_SIMPLE_MASTER_STRICT_MODE ,Disable simple master strict mode" ",1: Simple master in tier mode,2: Simple master in strict mode,"
textline "                                    "
bitfld.long 0x00 8.--9. " DISABLE_VIOLATION_ABORT           ,Disable secure violation abort" ",1: Violation assert secure_violation_irq,2: Violation causes abort,"
textline "                                    "
bitfld.long 0x00 6.--7. " ENABLE_NS_PRIV_CHECK              ,AHB bus matrix enable non-secure privilege check" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 4.--5. " ENABLE_S_PRIV_CHECK               ,AHB bus matrix enable secure privilege check" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 2.--3. " ENABLE_SECURE_CHECKING            ,AHB bus matrix enable secure checking" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 0.--1. " WRITE_LOCK                        ,Write lock" ",1: Restrictive mode,2: Secure control registers can be written,"
group.long 0xFFC++0x03
line.long 0x00 "MISC_CTRL_REG,secure control register"
bitfld.long 0x00 14.--15. " IDAU_ALL_NS                       ,Disable IDAU" ",1: IDAU is disabled,2: IDAU is enabled,"
textline "                                    "
bitfld.long 0x00 12.--13. " DISABLE_SMART_MASTER_STRICT_MODE  ,Disable smart master strict mode" ",1: Smart master in tier mode,2: Smart master in strict mode,"
textline "                                    "
bitfld.long 0x00 10.--11. " DISABLE_SIMPLE_MASTER_STRICT_MODE ,Disable simple master strict mode" ",1: Simple master in tier mode,2: Simple master in strict mode,"
textline "                                    "
bitfld.long 0x00 8.--9. " DISABLE_VIOLATION_ABORT           ,Disable secure violation abort" ",1: Violation assert secure_violation_irq,2: Violation causes abort,"
textline "                                    "
bitfld.long 0x00 6.--7. " ENABLE_NS_PRIV_CHECK              ,AHB bus matrix enable non-secure privilege check" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 4.--5. " ENABLE_S_PRIV_CHECK               ,AHB bus matrix enable secure privilege check" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 2.--3. " ENABLE_SECURE_CHECKING            ,AHB bus matrix enable secure checking" ",1: Restrictive mode,2: Disable check,"
textline "                                    "
bitfld.long 0x00 0.--1. " WRITE_LOCK                        ,Write lock" ",1: Restrictive mode,2: Secure control registers can be written,"
width 0x0B
tree.end
tree "CACHE64"
base ad:0x40033000
width 6.
group.long 0x800++0x03
line.long 0x00 "CCR,Cache control register"
bitfld.long 0x00 31. " GO           ,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24"
textline "               "
bitfld.long 0x00 27. " PUSHW1       ,Push Way 1" "0: no_operation,1: When setting the GO bit. push all modified lines in way 1"
textline "               "
bitfld.long 0x00 26. " INVW1        ,Invalidate Way 1" "0: no_operation,1: When setting the GO bit. invalidate all lines in way 1"
textline "               "
bitfld.long 0x00 25. " PUSHW0       ,Push Way 0" "0: no_operation,1: When setting the GO bit. push all modified lines in way 0"
textline "               "
bitfld.long 0x00 24. " INVW0        ,Invalidate Way 0" "0: no_operation,1: When setting the GO bit. invalidate all lines in way 0"
textline "               "
bitfld.long 0x00 1. " ENWRBUF      ,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
textline "               "
bitfld.long 0x00 0. " ENCACHE      ,Cache enable" "0: Cache disabled,1: Cache enabled"
group.long 0x804++0x03
line.long 0x00 "CLCR,Cache line control register"
bitfld.long 0x00 27. " LACC         ,Line access type" "0: read,1: write"
textline "               "
bitfld.long 0x00 26. " LADSEL       ,Line Address Select" "0: Cache address,1: Physical address"
textline "               "
bitfld.long 0x00 24.--25. " LCMD         ,Line Command" "0: Search and read or write,1: invalidate,2: push,3: clear"
textline "               "
bitfld.long 0x00 22. " LCWAY        ,Line Command Way" "0,1"
textline "               "
bitfld.long 0x00 21. " LCIMB        ,Line Command Initial Modified Bit" "0,1"
textline "               "
bitfld.long 0x00 20. " LCIVB        ,Line Command Initial Valid Bit" "0,1"
textline "               "
bitfld.long 0x00 16. " TDSEL        ,Tag/Data Select" "0: data,1: tag"
textline "               "
bitfld.long 0x00 14. " WSEL         ,Way select" "0: Way 0,1: Way 1"
textline "               "
hexmask.long.word 0x00 2.--13. 1. " CACHEADDR    ,Cache address"
textline "               "
bitfld.long 0x00 0. " LGO          ,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by bits 27-24"
group.long 0x808++0x03
line.long 0x00 "CSAR,Cache search address register"
bitfld.long 0x00 29.--31. " PHYADDR31_29 ,Physical Address" "0,1,2,3,4,5,6,7"
textline "               "
hexmask.long 0x00 1.--27. 1. " PHYADDR27_1  ,Physical Address"
textline "               "
bitfld.long 0x00 0. " LGO          ,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by bits CLCR[27:24]"
group.long 0x80C++0x03
line.long 0x00 "CCVR,Cache read/write value register"
hexmask.long 0x00 0.--31. 1. " DATA         ,Cache read/write Data"
width 0x0B
tree.end
tree "CACHE64_POLSEL"
base ad:0x40033000
width 10.
group.long 0x14++0x03
line.long 0x00 "REG0_TOP,Region 0 Top Boundary"
hexmask.long.tbyte 0x00 10.--26. 1. " REG0_TOP     ,Upper limit of Region 0"
group.long 0x18++0x03
line.long 0x00 "REG1_TOP,Region 1 Top Boundary"
hexmask.long.tbyte 0x00 10.--26. 1. " REG1_TOP     ,Upper limit of Region 1"
group.long 0x1C++0x03
line.long 0x00 "POLSEL,Policy Select"
bitfld.long 0x00 4.--5. " REG02_POLICY ,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG2_11"
textline "                   "
bitfld.long 0x00 2.--3. " REG1_POLICY  ,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG1_11"
textline "                   "
bitfld.long 0x00 0.--1. " REG0_POLICY  ,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG0_11"
width 0x0B
tree.end
tree "CASPER"
base ad:0x40151000
width 10.
group.long 0x00++0x03
line.long 0x00 "CTRL0,Contains the offsets of AB and CD in the RAM"
hexmask.long.word 0x00 18.--28. 1. " CDOFF     ,Word or DWord Offset of CD. with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be.."
textline "                   "
bitfld.long 0x00 16. " CDBPAIR   ,Which bank-pair the offset CDOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
textline "                   "
bitfld.long 0x00 2. " ABOFF     ,Word or DWord Offset of AB values. with B at [2]=0 and A at [2]=1 as far as the code sees (normally .." "0,1"
textline "                   "
bitfld.long 0x00 0. " ABBPAIR   ,Which bank-pair the offset ABOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
group.long 0x04++0x03
line.long 0x00 "CTRL1,Contains the opcode mode. iteration count. and result offset (in RAM) and also launches the accelera.."
bitfld.long 0x00 30.--31. " CSKIP     ,Skip rules on Carry if needed" "0: NO_SKIP,1: Skip if Carry is 1,2: Skip if Carry is 0,3: Set CTRLOFF to CDOFF and Skip"
textline "                   "
hexmask.long.word 0x00 18.--28. 1. " RESOFF    ,Word or DWord Offset of result"
textline "                   "
bitfld.long 0x00 16. " RESBPAIR  ,Which bank-pair the offset RESOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
textline "                   "
hexmask.long.byte 0x00 8.--15. 1. " MODE      ,Operation mode to perform"
textline "                   "
hexmask.long.byte 0x00 0.--7. 1. " ITER      ,Iteration counter"
group.long 0x08++0x03
line.long 0x00 "LOADER,Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations"
hexmask.long.word 0x00 18.--28. 1. " CTRLOFF   ,DWord Offset of CTRL pair to load next"
textline "                   "
bitfld.long 0x00 16. " CTRLBPAIR ,Which bank-pair the offset CTRLOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
textline "                   "
hexmask.long.byte 0x00 0.--7. 1. " COUNT     ,Number of control pairs to load 0 relative (so 1 means load 1)"
group.long 0x0C++0x03
line.long 0x00 "STATUS,Indicates operational status and would contain the carry bit if used"
rbitfld.long 0x00 5. " BUSY      ,Indicates if the accelerator is busy performing an operation" "0: Not busy - is idle,1: Is busy"
textline "                   "
rbitfld.long 0x00 4. " CARRY     ,Last carry value if operation produced a carry bit" "0: Carry was 0 or no carry,1: Carry was 1"
textline "                   "
bitfld.long 0x00 0. " DONE      ,Indicates if the accelerator has finished an operation" "0: Busy or just cleared,1: Completed last operation"
group.long 0x10++0x03
line.long 0x00 "INTENSET,Sets interrupts"
bitfld.long 0x00 0. " DONE      ,Set if the accelerator should interrupt when done" "0: Do not interrupt when done,1: Interrupt when done"
group.long 0x14++0x03
line.long 0x00 "INTENCLR,Clears interrupts"
eventfld.long 0x00 0. " DONE      ,Written to clear an interrupt set with INTENSET" "0: If written 0. ignored,1: If written 1. do not Interrupt when done"
group.long 0x18++0x03
line.long 0x00 "INTSTAT,Interrupt status bits (mask of INTENSET and STATUS)"
rbitfld.long 0x00 0. " DONE      ,If set. interrupt is caused by accelerator being done" "0: Not caused by accelerator being done,1: Caused by accelerator being done"
group.long 0x20++0x03
line.long 0x00 "AREG,A register"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to be fed into Multiplier"
group.long 0x24++0x03
line.long 0x00 "BREG,B register"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to be fed into Multiplier"
group.long 0x28++0x03
line.long 0x00 "CREG,C register"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to be fed into Multiplier"
group.long 0x2C++0x03
line.long 0x00 "DREG,D register"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to be fed into Multiplier"
group.long 0x30++0x03
line.long 0x00 "RES0,Result register 0"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to hold working result (from multiplier. adder/xor. etc)"
group.long 0x34++0x03
line.long 0x00 "RES1,Result register 1"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to hold working result (from multiplier. adder/xor. etc)"
group.long 0x38++0x03
line.long 0x00 "RES2,Result register 2"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to hold working result (from multiplier. adder/xor. etc)"
group.long 0x3C++0x03
line.long 0x00 "RES3,Result register 3"
hexmask.long 0x00 0.--31. 1. " REG_VALUE ,Register to hold working result (from multiplier. adder/xor. etc)"
group.long 0x60++0x03
line.long 0x00 "MASK,Optional mask register"
hexmask.long 0x00 0.--31. 1. " MASK      ,Mask to apply as side channel countermeasure"
group.long 0x64++0x03
line.long 0x00 "REMASK,Optional re-mask register"
hexmask.long 0x00 0.--31. 1. " MASK      ,Mask to apply as side channel countermeasure"
group.long 0x80++0x03
line.long 0x00 "LOCK,Security lock register"
hexmask.long.word 0x00 4.--16. 1. " KEY       ,Must be written as 0x73D to change the register"
textline "                   "
bitfld.long 0x00 0. " LOCK      ,Reads back with security level locked to. or 0" "0: UNLOCK,1: Lock to current security level"
width 0x0B
tree.end
tree "CLKCTL0"
base ad:0x40001000
width 21.
group.long 0x10++0x03
line.long 0x00 "PSCCTL0,clock control register 0"
bitfld.long 0x00 24. " SCT_CLK           ,SCT clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 23. " USBHS_SRAM_CLK    ,USBHS RAM clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 22. " USBHS_HOST_CLK    ,USB HOST clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 21. " USBHS_DEVICE_CLK  ,USB DEVICE clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 20. " USBHS_PHY_CLK     ,USB PHY clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 17. " OTP_CLK           ,OTP clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 16. " FLEXSPI_OTFAD_CLK ,FLEXSPI clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 12. " RNG_CLK           ,RNG clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 11. " PUF_CLK           ,PUF clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 10. " HASHCRYPT_CLK     ,HASHCRYPT clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 9. " CASPER_CLK        ,CAPSER clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 8. " POWERQUAD_CLK     ,powerquad clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 2. " ROM_CTL_128KB     ,128KB ROM control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
group.long 0x14++0x03
line.long 0x00 "PSCCTL1,clock control register 1"
bitfld.long 0x00 24. " SHSGPIO0_CLK      ,SHSGPIO0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 16. " ADC0_CLK          ,ADC clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 15. " ACMP0_CLK         ,Analog comparator clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 3. " SDIO1_CLK         ,SDIO1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 2. " SDIO0_CLK         ,SDIO0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
group.long 0x18++0x03
line.long 0x00 "PSCCTL2,clock control register 2"
bitfld.long 0x00 1. " WWDT0_CLK         ,wdt clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                              "
bitfld.long 0x00 0. " UTICK0_CLK        ,utick clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
group.long 0x40++0x03
line.long 0x00 "PSCCTL0_SET,clock set register 0"
bitfld.long 0x00 24. " SCT_CLK           ,SCT clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 23. " USBHS_SRAM_CLK    ,USBHS RAM clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 22. " USBHS_HOST_CLK    ,USB HOST clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 21. " USBHS_DEVICE_CLK  ,USB DEVICE clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 20. " USBHS_PHY_CLK     ,USB PHY clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 17. " OTP_CLK           ,OTP clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 16. " FLEXSPI_OTFAD_CLK ,FLEXSPI clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 12. " RNG_CLK           ,RNG clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 11. " PUF_CLK           ,PUF clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 10. " HASHCRYPT_CLK     ,HASHCRYPT clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 9. " CASPER_CLK        ,CAPSER clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 8. " POWERQUAD_CLK     ,powerquad clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 2. " ROM_CTL_128KB_CLK ,128KB ROM controller clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
wgroup.long 0x44++0x03
line.long 0x00 "PSCCTL1_SET,clock set register 1"
bitfld.long 0x00 24. " SHSGPIO0_CLK      ,SHSGPIO0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 16. " ADC0_CLK          ,ADC clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 15. " ACMP0_CLK         ,Analog comparator clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 3. " SDIO1_CLK         ,SDIO1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 2. " SDIO0_CLK         ,SDIO0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
wgroup.long 0x48++0x03
line.long 0x00 "PSCCTL2_SET,clock set register 2"
bitfld.long 0x00 1. " WWDT0_CLK         ,wdt clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                              "
bitfld.long 0x00 0. " UTICK0_CLK        ,utick clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
group.long 0x70++0x03
line.long 0x00 "PSCCTL0_CLR,clock clear register 0"
bitfld.long 0x00 24. " SCT_CLK           ,SCT clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 23. " USBHS_SRAM_CLK    ,USBHS RAM clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 22. " USBHS_HOST_CLK    ,USB HOST clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 21. " USBHS_DEVICE_CLK  ,USB DEVICE clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 20. " USBHS_PHY_CLK     ,USB PHY clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 17. " OTP_CLK           ,OTP clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 16. " FLEXSPI_OTFAD_CLK ,FLEXSPI clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 12. " RNG_CLK           ,RNG clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 11. " PUF_CLK           ,PUF clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 10. " HASHCRYPT_CLK     ,HASHCRYPT clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 9. " CASPER_CLK        ,CAPSER clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 8. " POWERQUAD_CLK     ,powerquad clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                              "
bitfld.long 0x00 2. " ROM_CTL_128KB_CLK ,ROM controller clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
wgroup.long 0x74++0x03
line.long 0x00 "PSCCTL1_CLR,clock clear register 1"
bitfld.long 0x00 24. " SHSGPIO0_CLK      ,SHSGPIO0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 16. " ADC0_CLK          ,ADC clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 15. " ACMP0_CLK         ,Analog comparator clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 3. " SDIO1_CLK         ,SDIO1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                              "
bitfld.long 0x00 2. " SDIO0_CLK         ,SDIO0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
wgroup.long 0x78++0x03
line.long 0x00 "PSCCTL2_CLR,clock clear register 2"
bitfld.long 0x00 1. " WWDT0_CLK         ,wdt clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                              "
bitfld.long 0x00 0. " UTICK0_CLK        ,utick clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
group.long 0x100++0x03
line.long 0x00 "FFROCTL0,FFRO control 0"
bitfld.long 0x00 18.--19. " TRIM_RANGE        ,Trims frequency range of clk" "0,1,2,3"
textline "                              "
hexmask.long.byte 0x00 11.--17. 1. " TRIM_FINE         ,Trims fine frequency of clk"
textline "                              "
bitfld.long 0x00 5.--10. " TRIM_COARSE       ,Trims coarse frequency of clk" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--4. " TRIM_TEMPCO       ,Trims temperature compensation of clk" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x104++0x03
line.long 0x00 "FFROCTL1,FFRO control 1"
bitfld.long 0x00 0. " UPDATE            ,Update Safe Mode Control" "0: NORMAL_MODE,1: UPDATE_SAFE_MODE"
group.long 0x160++0x03
line.long 0x00 "SYSOSCCTL0,system oscillator control 0"
bitfld.long 0x00 1. " BYPASS_ENABLE     ,Enable signal for external bypass clock" "0: NORMAL_MODE,1: BYPASS_MODE"
textline "                              "
bitfld.long 0x00 0. " LP_ENABLE         ,Enable signal for low power mode" "0: High Gain Mode(HP),1: Low Power mode (LP)"
group.long 0x168++0x03
line.long 0x00 "SYSOSCBYPASS,system oscillator bypass"
bitfld.long 0x00 0.--2. " SEL               ,XTALIN Functional Clock Source Selection" "0: External XTAL Clock,1: Clock IN Clock,,,,,,7: NONE"
group.long 0x190++0x03
line.long 0x00 "LPOSCCTL0,low power oscillator control 0"
bitfld.long 0x00 31. " CLKRDY            ,Clock ready flag status" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "OSC32KHZCTL0,32k oscillator control0"
bitfld.long 0x00 0. " ENA32KHZ          ,32KHz Enable" "0: DISABLED,1: ENABLED"
group.long 0x200++0x03
line.long 0x00 "SYSPLL0CLKSEL,system pll0 clock selection"
bitfld.long 0x00 0.--2. " SEL               ,System PLL Clock Source Selection" "0: SFRO Clock,1: SYSXTALIN Clock,2: FFRO Clock Divided by 2,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x204++0x03
line.long 0x00 "SYSPLL0CTL0,system pll0 control0"
hexmask.long.byte 0x00 16.--23. 1. " MULT              ,Multiplication Factor for FSYSPLL0_OUTPUT:"
textline "                              "
bitfld.long 0x00 13. " HOLDRINGOFF_ENA   ,Hold Ring Off Control: This bit is used to avoid multi wave within the VCO" "0: DSIABLE,1: ENABLE"
textline "                              "
bitfld.long 0x00 1. " RESET             ,SYSPLL0 Reset:" "0: SYSPLL0 reset is removed,1: SYSPLL0 is placed into reset"
textline "                              "
bitfld.long 0x00 0. " BYPASS            ,SYSPLL0 BYPASS Mode" "0: PFD output is PFD programmed clock,1: PFD output is PLL Input clock"
group.long 0x20C++0x03
line.long 0x00 "SYSPLL0LOCKTIMEDIV2,system pll0 lock time"
hexmask.long.word 0x00 0.--15. 1. " LOCKTIMEDIV2      ,SYSPLL0 Lock Time Divide by 2: Programmed lock time is in uS (micro-seconds) and is programmed as ha.."
group.long 0x210++0x03
line.long 0x00 "SYSPLL0NUM,system pll0 number"
hexmask.long 0x00 0.--29. 1. " NUM               ,This field contains the numerator of the SYSPLL0 fractional loop divider"
group.long 0x214++0x03
line.long 0x00 "SYSPLL0DENOM,system pll0 denom"
hexmask.long 0x00 0.--29. 1. " DENOM             ,This field contains the denominator of the SYSPLL0 fractional loop divider"
group.long 0x218++0x03
line.long 0x00 "SYSPLL0PFD,sys pll0 PFD"
bitfld.long 0x00 31. " PFD3_CLKGATE      ,PFD3 Clock Gate: 0: PFD3 clock is not gated" "0: PFD3 clock is not gated,1: PFD3 clock is gated"
textline "                              "
bitfld.long 0x00 30. " PFD3_CLKRDY       ,PFD3 Clock Ready Status Flag: Read as '1' clock ready" "0,1"
textline "                              "
bitfld.long 0x00 24.--29. " PFD3              ,PLL Fractional Divider 3: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 23. " PFD2_CLKGATE      ,PFD2 Clock Gate: 0: PFD2 clock is not gated" "0: PFD2 clock is not gated,1: PFD2 clock is gated"
textline "                              "
bitfld.long 0x00 22. " PFD2_CLKRDY       ,PFD2 Clock Ready Status Flag: Read as '1' clock ready" "0,1"
textline "                              "
bitfld.long 0x00 16.--21. " PFD2              ,PLL Fractional Divider 2: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 15. " PFD1_CLKGATE      ,PFD1 Clock Gate: 0: PFD1 clock is not gated" "0: PFD1 clock is not gated,1: PFD1 clock is gated"
textline "                              "
bitfld.long 0x00 14. " PFD1_CLKRDY       ,PFD1 Clock Ready Status Flag: Read as '1' clock ready" "0,1"
textline "                              "
bitfld.long 0x00 8.--13. " PFD1              ,PLL Fractional Divider 1: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 7. " PFD0_CLKGATE      ,PFD0 Clock Gate: 0: PFD0 clock is not gated" "0: PFD0 clock is not gated,1: PFD0 clock is gated"
textline "                              "
bitfld.long 0x00 6. " PFD0_CLKRDY       ,PFD0 Clock Ready Status Flag: Read as '1' clock ready" "0,1"
textline "                              "
bitfld.long 0x00 0.--5. " PFD0              ,PLL Fractional Divider 0: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x240++0x03
line.long 0x00 "MAINPLLCLKDIV,main pll clk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x244++0x03
line.long 0x00 "DSPPLLCLKDIV,dsp pll clk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x248++0x03
line.long 0x00 "AUX0PLLCLKDIV,aux0 pll clk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x24C++0x03
line.long 0x00 "AUX1PLLCLKDIV,aux1 pll clk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x400++0x03
line.long 0x00 "SYSCPUAHBCLKDIV,system cpu AHB clock divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x430++0x03
line.long 0x00 "MAINCLKSELA,main clock selection A"
bitfld.long 0x00 0.--1. " SEL               ,Control Main 1st Stage Control Clock Source" "0: FFRO Clock Divided by 4,1: SYSXTALIN Clock,2: Low Power Oscillator Clock (LPOSC),3: FFRO Clock"
group.long 0x434++0x03
line.long 0x00 "MAINCLKSELB,main clock selection B"
bitfld.long 0x00 0.--1. " SEL               ,Main Clock Source Selection" "0: MAINCLKSELA 1st Stage Clock,1: SFRO Clock,2: Main System PLL Clock,3: RTC 32KHz Clock"
group.long 0x500++0x03
line.long 0x00 "PFCDIV0,PFC divider register N"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x504++0x03
line.long 0x00 "PFCDIV1,PFC divider register N"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x620++0x03
line.long 0x00 "FLEXSPIFCLKSEL,FlexSPI FCLK selection"
bitfld.long 0x00 0.--2. " SEL               ,FlexSPI Functional Clock Source Selection" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0_AUX0_PLL_Clock,3: FFRO Clock,4: SYSPLL0_AUX1_PLL_Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x624++0x03
line.long 0x00 "FLEXSPIFCLKDIV,FlexSPI FCLK divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x640++0x03
line.long 0x00 "SCTFCLKSEL,SCT FCLK selection"
bitfld.long 0x00 0.--2. " SEL               ,SCT Functional Clock Source Selection" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0_AUX0_PLL_Clock,3: FFRO Clock,4: SYSPLL0_AUX1_PLL_Clock,5: AUDIO PLL Clock,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x644++0x03
line.long 0x00 "SCTFCLKDIV,SCT fclk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x660++0x03
line.long 0x00 "USBHSFCLKSEL,USBHS Fclk selection"
bitfld.long 0x00 0.--2. " SEL               ,USB HS Functional Clock Source Selection" "0: XTALIN Clock,1: Main Clock,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x664++0x03
line.long 0x00 "USBHSFCLKDIV,USBHS Fclk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x680++0x03
line.long 0x00 "SDIO0FCLKSEL,SDIO0 FCLK selection"
bitfld.long 0x00 0.--2. " SEL               ,SDIO0 Functional Clock Source Selection" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0_AUX0_PLL_Clock,3: FFRO Clock,4: SYSPLL0_AUX1_PLL_Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x684++0x03
line.long 0x00 "SDIO0FCLKDIV,SDIO0 FCLK divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x690++0x03
line.long 0x00 "SDIO1FCLKSEL,SDIO1 FCLK selection"
bitfld.long 0x00 0.--2. " SEL               ,SDIO0 Functional Clock Source Selection" "0: Main Clock,1: Main System PLL Clock,2: SYSPLL0_AUX0_PLL_Clock,3: FFRO Clock,4: SYSPLL0_AUX1_PLL_Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x694++0x03
line.long 0x00 "SDIO1FCLKDIV,SDIO1 FCLK divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x6D0++0x03
line.long 0x00 "ADC0FCLKSEL0,ADC0 fclk selection 0"
bitfld.long 0x00 0.--2. " SEL               ,Clock Output Select 1st Stage" "0: SFRO Clock,1: XTALIN Clock,2: Low Power Oscillator Clock (LPOSC),3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6D4++0x03
line.long 0x00 "ADC0FCLKSEL1,ADC0 fclk selection 1"
bitfld.long 0x00 0.--2. " SEL               ,ADC Functional Clock Source Selection" "0: ADC0FCLKSEL0 Multiplexed Output,1: SYSPLL0 MAIN_CLK (PFD0 Output),,3: SYSPLL0_AUX0_PLL_Clock,,5: SYSPLL0_AUX1_PLL_Clock,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6D8++0x03
line.long 0x00 "ADC0FCLKDIV,ADC0 fclk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
group.long 0x700++0x03
line.long 0x00 "UTICKFCLKSEL,UTICK fclk selection"
bitfld.long 0x00 0.--2. " SEL               ,uTICK Functional Clock Source Selection" "0: Low Power Oscillator Clock (LPOSC),,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x720++0x03
line.long 0x00 "WDT0FCLKSEL,wdt clock selection"
bitfld.long 0x00 0.--2. " SEL               ,WDT0 Functional Clock Source Selection" "0: Low Power Oscillator Clock (LPOSC),,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x730++0x03
line.long 0x00 "WAKECLK32KHZSEL,32k wake clock selection"
bitfld.long 0x00 0.--2. " SEL               ,32KHz Wake Clock Low Power Functional Clock Source Selection" "0: FREQ_32KHZ,1: LPOSC (Divided by 32 by default),,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x734++0x03
line.long 0x00 "WAKECLK32KHZDIV,32k wake clock divider"
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
group.long 0x760++0x03
line.long 0x00 "SYSTICKFCLKSEL,system tick fclk selection"
bitfld.long 0x00 0.--2. " SEL               ,SYSTICK Functional Clock Source Selection" "0: Systick Divider Output Clock,1: Low Power Oscillator Clock (LPOSC),2: 32KHz RTC Clock,3: SFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x764++0x03
line.long 0x00 "SYSTICKFCLKDIV,system tick fclk divider"
bitfld.long 0x00 31. " REQFLAG           ,Divider status flag" "0,1"
textline "                              "
bitfld.long 0x00 30. " HALT              ,Halts the divider counter" "0,1"
textline "                              "
bitfld.long 0x00 29. " RESET             ,Resets the divider counter" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DIV               ,Clock Divider Value Selection"
width 0x0B
tree.end
tree "CLKCTL1"
base ad:0x40021000
width 23.
group.long 0x10++0x03
line.long 0x00 "PSCCTL0,clock control register 0"
bitfld.long 0x00 27. " OSEVENT_TIMER_CLK     ,OS event timer clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 24. " DMIC0_CLK             ,DMIC0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 23. " FC15_I2C_CLK          ,flexcomm 15 i2c clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 22. " FC14_SPI_CLK          ,flexcomm 14 spi clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 15. " FC7_CLK               ,flexcomm 7 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 14. " FC6_CLK               ,flexcomm 6 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 13. " FC5_CLK               ,flexcomm 5 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 12. " FC4_CLK               ,flexcomm 4 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 11. " FC3_CLK               ,flexcomm 3 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 10. " FC2_CLK               ,flexcomm 2 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 9. " FC1_CLK               ,flexcomm 1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 8. " FC0_CLK               ,flexcomm 0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
group.long 0x14++0x03
line.long 0x00 "PSCCTL1,clock control register 1"
bitfld.long 0x00 31. " FREQME_CLK            ,FREQME clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 29. " SEMA_CLK              ,SEMA clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 28. " MU_CLK                ,MU clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 24. " DMAC1_CLK             ,DMAC1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 23. " DMAC0_CLK             ,DMAC0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 16. " CRC_CLK               ,CRC clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 7. " HSGPIO7_CLK           ,HSGPIO7 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 6. " HSGPIO6_CLK           ,HSGPIO6 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 5. " HSGPIO5_CLK           ,HSGPIO5 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 4. " HSGPIO4_CLK           ,HSGPIO4 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 3. " HSGPIO3_CLK           ,HSGPIO3 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 2. " HSGPIO2_CLK           ,HSGPIO2 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 1. " HSGPIO1_CLK           ,HSGPIO1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 0. " HSGPIO0_CLK           ,HSGPIO0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
group.long 0x18++0x03
line.long 0x00 "PSCCTL2,clock control register 2"
bitfld.long 0x00 31. " PIMCTL_CLK            ,PIMCTL clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 30. " GPIOINTCTL_CLK        ,GPIOINTCTL clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 16. " I3C0_CLK              ,i3c0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 10. " WWDT1_CLK             ,wdt1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 8. " MRT0_CLK              ,mrt0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 7. " RTC_LITE_CLK          ,rtc lite clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 4. " CT32BIT4_CLK          ,ct32bit timer 4 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 3. " CT32BIT3_CLK          ,ct32bit timer 3 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 2. " CT32BIT2_CLK          ,ct32bit timer 2 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 1. " CT32BIT1_CLK          ,ct32bit timer 1 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
textline "                                "
bitfld.long 0x00 0. " CT32BIT0_CLK          ,ct32bit timer 0 clock control" "0: DISABLE_CLOCK,1: ENABLE_CLOCK"
wgroup.long 0x40++0x03
line.long 0x00 "PSCCTL0_SET,clock set register 0"
bitfld.long 0x00 27. " OSEVENT_TIMER_CLK_SET ,OS event timer clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 24. " DMIC0_CLK_SET         ,DMIC0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 23. " FC15_I2C_CLK_SET      ,flexcomm 15 i2c clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 22. " FC14_SPI_CLK_SET      ,flexcomm 14 spi clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 15. " FC7_CLK_SET           ,flexcomm 7 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 14. " FC6_CLK_SET           ,flexcomm 6 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 13. " FC5_CLK_SET           ,flexcomm 5 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 12. " FC4_CLK_SET           ,flexcomm 4 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 11. " FC3_CLK_SET           ,flexcomm 3 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 10. " FC2_CLK_SET           ,flexcomm 2 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 9. " FC1_CLK_SET           ,flexcomm 1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 8. " FC0_CLK_SET           ,flexcomm 0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL0 Bit"
wgroup.long 0x44++0x03
line.long 0x00 "PSCCTL1_SET,clock set register 1"
bitfld.long 0x00 31. " FREQME_CLK_SET        ,FREQME clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 29. " SEMA_CLK_SET          ,SEMA clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 28. " MU_CLK_SET            ,MU clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 24. " DMAC1_CLK_SET         ,DMAC1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 23. " DMAC0_CLK_SET         ,DMAC0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 16. " CRC_CLK_SET           ,CRC clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 7. " HSGPIO7_CLK_SET       ,HSGPIO7 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 6. " HSGPIO6_CLK_SET       ,HSGPIO6 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 5. " HSGPIO5_CLK_SET       ,HSGPIO5 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 4. " HSGPIO4_CLK_SET       ,HSGPIO4 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 3. " HSGPIO3_CLK_SET       ,HSGPIO3 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 2. " HSGPIO2_CLK_SET       ,HSGPIO2 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 1. " HSGPIO1_CLK_SET       ,HSGPIO1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 0. " HSGPIO0_CLK_SET       ,HSGPIO0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL1 Bit"
wgroup.long 0x48++0x03
line.long 0x00 "PSCCTL2_SET,clock set register 2"
bitfld.long 0x00 31. " PIMCTL_CLK_SET        ,PIMCTL clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 30. " GPIOINTCTL_CLK_SET    ,GPIOINTCTL clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 16. " I3C0_CLK_SET          ,i3c0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 10. " WWDT1_CLK_SET         ,wdt1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 8. " MRT0_CLK_SET          ,mrt0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 7. " RTC_LITE_CLK_SET      ,rtc lite clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 4. " CT32BIT4_CLK_SET      ,ct32bit timer 4 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 3. " CT32BIT3_CLK_SET      ,ct32bit timer 3 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 2. " CT32BIT2_CLK_SET      ,ct32bit timer 2 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 1. " CT32BIT1_CLK_SET      ,ct32bit timer 1 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 0. " CT32BIT0_CLK_SET      ,ct32bit timer 0 clock set" "0: NO_EFFECT,1: Sets the PSCCTL2 Bit"
wgroup.long 0x70++0x03
line.long 0x00 "PSCCTL0_CLR,clock clear register 0"
bitfld.long 0x00 27. " OSEVENT_TIMER_CLK_CLR ,OS event timer clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 24. " DMIC0_CLK_CLR         ,DMIC0 clock set" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 23. " FC15_I2C_CLK_CLR      ,flexcomm 15 i2c clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 22. " FC14_SPI_CLK_CLR      ,flexcomm 14 spi clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 15. " FC7_CLK_CLR           ,flexcomm 7 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 14. " FC6_CLK_CLR           ,flexcomm 6 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 13. " FC5_CLK_CLR           ,flexcomm 5 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 12. " FC4_CLK_CLR           ,flexcomm 4 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 11. " FC3_CLK_CLR           ,flexcomm 3 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 10. " FC2_CLK_CLR           ,flexcomm 2 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 9. " FC1_CLK_CLR           ,flexcomm 1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
textline "                                "
bitfld.long 0x00 8. " FC0_CLK_CLR           ,flexcomm 0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL0 Bit"
wgroup.long 0x74++0x03
line.long 0x00 "PSCCTL1_CLR,clock clear register 1"
bitfld.long 0x00 31. " FREQME_CLK_CLR        ,FREQME clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 29. " SEMA_CLK_CLR          ,SEMA clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 28. " MU_CLK_CLR            ,MU clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 24. " DMAC1_CLK_CLR         ,DMAC1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 23. " DMAC0_CLK_CLR         ,DMAC0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 16. " CRC_CLK_CLR           ,CRC clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 7. " HSGPIO7_CLK_CLR       ,HSGPIO7 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 6. " HSGPIO6_CLK_CLR       ,HSGPIO6 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 5. " HSGPIO5_CLK_CLR       ,HSGPIO5 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 4. " HSGPIO4_CLK_CLR       ,HSGPIO4 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 3. " HSGPIO3_CLK_CLR       ,HSGPIO3 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 2. " HSGPIO2_CLK_CLR       ,HSGPIO2 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 1. " HSGPIO1_CLK_CLR       ,HSGPIO1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
textline "                                "
bitfld.long 0x00 0. " HSGPIO0_CLK_CLR       ,HSGPIO0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL1 Bit"
wgroup.long 0x78++0x03
line.long 0x00 "PSCCTL2_CLR,clock clear register 2"
bitfld.long 0x00 31. " PIMCTL_CLK_CLR        ,PIMCTL clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 30. " GPIOINTCTL_CLK_CLR    ,GPIOINTCTL clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 16. " I3C0_CLK_CLR          ,i3c0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 10. " WWDT1_CLK_CLR         ,wdt1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 8. " MRT0_CLK_CLR          ,mrt0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 7. " RTC_LITE_CLK_CLR      ,rtc lite clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 4. " CT32BIT4_CLK_CLR      ,ct32bit timer 4 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 3. " CT32BIT3_CLK_CLR      ,ct32bit timer 3 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 2. " CT32BIT2_CLK_CLR      ,ct32bit timer 2 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 1. " CT32BIT1_CLK_CLR      ,ct32bit timer 1 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
textline "                                "
bitfld.long 0x00 0. " CT32BIT0_CLK_CLR      ,ct32bit timer 0 clock clear" "0: NO_EFFECT,1: Clears the PSCCTL2 Bit"
group.long 0x200++0x03
line.long 0x00 "AUDIOPLL0CLKSEL,audio pll0 clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,System PLL Clock Source Selection" "0: SFRO Clock,1: XTALIN Clock,2: FFRO Clock Divided by 2,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x204++0x03
line.long 0x00 "AUDIOPLL0CTL0,audio pll0 control0"
hexmask.long.byte 0x00 16.--23. 1. " MULT                  ,Multiplication Factor for FAUDIOPLL0_OUTPUT:"
textline "                                "
bitfld.long 0x00 13. " HOLDRINGOFF_ENA       ,Hold Ring Off Control" "0: DSIABLE,1: ENABLE"
textline "                                "
bitfld.long 0x00 1. " RESET                 ,AUDIOPLL0 Reset:" "0: AUDIOPLL0 reset is removed,1: AUDIOPLL0 is placed into reset"
textline "                                "
bitfld.long 0x00 0. " BYPASS                ,AUDIOPLL0 BYPASS Mode" "0: PFD output is PFD programmed clock,1: PFD output is AUDIOPLL0 reference input clock"
group.long 0x20C++0x03
line.long 0x00 "AUDIOPLL0LOCKTIMEDIV2,audio pll0 lock time"
hexmask.long.word 0x00 0.--15. 1. " LOCKTIMEDIV2          ,AUDIOPLL0 Lock Time Divide by 2: Programmed lock time is in uS (micro-seconds) and is programmed as .."
group.long 0x210++0x03
line.long 0x00 "AUDIOPLL0NUM,audio pll0 number"
hexmask.long 0x00 0.--29. 1. " NUM                   ,This field contains the numerator of the AUDIOPLL0 fractional loop divider"
group.long 0x214++0x03
line.long 0x00 "AUDIOPLL0DENOM,Audio pll0 denom"
hexmask.long 0x00 0.--29. 1. " DENOM                 ,This field contains the denominator of the AUDIOPLL0 fractional loop divider"
group.long 0x218++0x03
line.long 0x00 "AUDIOPLL0PFD,audio pll0 PFD"
bitfld.long 0x00 31. " PFD3_CLKGATE          ,PFD3 Clock Gate: 0: PFD3 clock is not gated" "0: PFD3 clock is not gated,1: PFD3 clock is gated"
textline "                                "
bitfld.long 0x00 30. " PFD3_CLKRDY           ,PFD3 Clock Ready Status Flag: Read as 1 clock ready" "0,1"
textline "                                "
bitfld.long 0x00 24.--29. " PFD3                  ,PLL Fractional Divider 3: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                "
bitfld.long 0x00 23. " PFD2_CLKGATE          ,PFD2 Clock Gate: 0: PFD2 clock is not gated" "0: PFD2 clock is not gated,1: PFD2 clock is gated"
textline "                                "
bitfld.long 0x00 22. " PFD2_CLKRDY           ,PFD2 Clock Ready Status Flag: Read as 1 clock ready" "0,1"
textline "                                "
bitfld.long 0x00 16.--21. " PFD2                  ,PLL Fractional Divider 2: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                "
bitfld.long 0x00 15. " PFD1_CLKGATE          ,PFD1 Clock Gate: 0: PFD1 clock is not gated" "0: PFD1 clock is not gated,1: PFD1 clock is gated"
textline "                                "
bitfld.long 0x00 14. " PFD1_CLKRDY           ,PFD1 Clock Ready Status Flag: Read as 1 clock ready" "0,1"
textline "                                "
bitfld.long 0x00 8.--13. " PFD1                  ,PLL Fractional Divider 1: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                "
bitfld.long 0x00 7. " PFD0_CLKGATE          ,PFD0 Clock Gate: 0: PFD0 clock is not gated" "0: PFD0 clock is not gated,1: PFD0 clock is gated"
textline "                                "
bitfld.long 0x00 6. " PFD0_CLKRDY           ,PFD0 Clock Ready Status Flag: Read as 1 clock ready" "0,1"
textline "                                "
bitfld.long 0x00 0.--5. " PFD0                  ,PLL Fractional Divider 0: Controls the fractional divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x240++0x03
line.long 0x00 "AUDIOPLLCLKDIV,audio pll0 clock divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x400++0x03
line.long 0x00 "DSPCPUCLKDIV,DSP cpu clock divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x404++0x03
line.long 0x00 "DSPMAINRAMCLKDIV,DSP main ram clock divider"
bitfld.long 0x00 0.--1. " DSPMRAMCLKDIV         ,DSP MAINRAM Clock Ratio Control:" "0: DSP MAINRAM Clk = DSP Core CLK / 1,1: DSP MAINRAM Clk = DSP Core CLK / 2,2: DSP MAINRAM Clk = DSP Core CLK / 3,3: DSP MAINRAM Clk = DSP Core CLK / 4"
group.long 0x430++0x03
line.long 0x00 "DSPCPUCLKSELA,DSP clock selection A"
bitfld.long 0x00 0.--1. " SEL                   ,Control Main 1st Stage Control Clock Source" "0: FFRO Clock,1: XTALIN Clock,2: Low Power Oscillator Clock (LPOSC),3: SFRO Clock"
group.long 0x434++0x03
line.long 0x00 "DSPCPUCLKSELB,DSP clock selection B"
bitfld.long 0x00 0.--1. " SEL                   ,Main Clock Source Selection" "0: MAINCLKSELA 1st Stage Clock,1: Main System PLL Clock,2: DSP System PLL Clock,3: RTC 32KHz Clock"
group.long 0x480++0x03
line.long 0x00 "OSEVENTFCLKSEL,OS EVENT clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,OS Event Timer Functional Clock Source Selection" "0: Low Power Oscillator Clock (LPOSC),1: RTC 32KHz Clock,2: Teal Free Running Clock (Global Time Stamping),,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6C0++0x03
line.long 0x00 "FRG14CLKSEL,FRG clock selection register 14"
bitfld.long 0x00 0.--2. " SEL                   ,Fractional Gen" "0: Main Clock,1: Main System PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6C4++0x03
line.long 0x00 "FRG14CTL,FRG clock controller 14"
hexmask.long.byte 0x00 8.--15. 1. " MULT                  ,Numerator of the fractional divider"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Denominator of the fractional divider"
group.long 0x6C8++0x03
line.long 0x00 "FC14FCLKSEL,flexcomm14 clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6E0++0x03
line.long 0x00 "FRG15CLKSEL,FRG clock selection register 15"
bitfld.long 0x00 0.--2. " SEL                   ,Fractional Gen" "0: Main Clock,1: Main System PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6E4++0x03
line.long 0x00 "FRG15CTL,FRG clock controller 15"
hexmask.long.byte 0x00 8.--15. 1. " MULT                  ,Numerator of the fractional divider"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Denominator of the fractional divider"
group.long 0x6E8++0x03
line.long 0x00 "FC15FCLKSEL,flexcomm15 clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x6FC++0x03
line.long 0x00 "FRGPLLCLKDIV,FRG pll clock divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x700++0x03
line.long 0x00 "DMIC0FCLKSEL,DMIC0 clk selection"
bitfld.long 0x00 0.--2. " SEL                   ,DMIC Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: Low Power Oscillator Clock (LPOSC),5: WAKE_CLK_32KHZ,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x704++0x03
line.long 0x00 "DMIC0FCLKDIV,DMIC clock clock divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x720++0x03
line.long 0x00 "CT32BITFCLKSEL0,ct32bit timer N clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: Audio PLL Clock,4: Master Clock In,5: Low Power Oscillator Clock (LPOSC),,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x724++0x03
line.long 0x00 "CT32BITFCLKSEL1,ct32bit timer N clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: Audio PLL Clock,4: Master Clock In,5: Low Power Oscillator Clock (LPOSC),,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x728++0x03
line.long 0x00 "CT32BITFCLKSEL2,ct32bit timer N clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: Audio PLL Clock,4: Master Clock In,5: Low Power Oscillator Clock (LPOSC),,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x72C++0x03
line.long 0x00 "CT32BITFCLKSEL3,ct32bit timer N clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: Audio PLL Clock,4: Master Clock In,5: Low Power Oscillator Clock (LPOSC),,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x730++0x03
line.long 0x00 "CT32BITFCLKSEL4,ct32bit timer N clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: Audio PLL Clock,4: Master Clock In,5: Low Power Oscillator Clock (LPOSC),,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x740++0x03
line.long 0x00 "AUDIOMCLKSEL,audio mclock selection"
bitfld.long 0x00 0.--2. " SEL                   ,Audio MCLK Clock Source Selection" "0: FFRO Clock,1: AUDIO PLL Clock,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x744++0x03
line.long 0x00 "AUDIOMCLKDIV,audio mclock divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x760++0x03
line.long 0x00 "CLKOUTSEL0,clock out selection 0"
bitfld.long 0x00 0.--2. " SEL                   ,Clock Output Select 1st Stage" "0: SFRO Clock,1: XTALIN Clock,2: Low Power Oscillator Clock (LPOSC),3: FFRO Clock,4: Main Clock,,6: DSP Main Clock,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x764++0x03
line.long 0x00 "CLKOUTSEL1,clock out selection 1"
bitfld.long 0x00 0.--2. " SEL                   ,Clock out clock Source Selection" "0: CLKOUTSEL0 Multiplexed Output,1: Main System PLL Clock,2: SYSPLL0 AUX0_PLL_Clock,3: DSP PLL clock,4: SYSPLL0 AUX1_PLL_Clock,5: AUDIO PLL Clock,6: 32KHz RTC Clock,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x768++0x03
line.long 0x00 "CLKOUTDIV,clock_out divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x780++0x03
line.long 0x00 "I3C0FCLKSEL,I3C0 fclk selection"
bitfld.long 0x00 0.--2. " SEL                   ,I3C0 FClock Source Selection" "0: Main Clock,1: FFRO Clock,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x784++0x03
line.long 0x00 "I3C0FCLKSTCSEL,I3C0 fclk STC selection"
bitfld.long 0x00 0.--2. " SEL                   ,I3C0 Clock Source Selection" "0: I3C0_FCLK_SELECTION,1: Low Power Oscillator Clock (LPOSC),,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x788++0x03
line.long 0x00 "I3C0FCLKSTCDIV,I3C0 fclk STC divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x78C++0x03
line.long 0x00 "I3C0FCLKSDIV,I3C0 fclks divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x790++0x03
line.long 0x00 "I3C0FCLKDIV,I3C0 fclk divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
group.long 0x7A0++0x03
line.long 0x00 "WDT1FCLKSEL,WDT1 clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,WDT1 Functional Clock Source Selection" "0: Low Power Oscillator Clock (LPOSC),,,,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x7C0++0x03
line.long 0x00 "ACMP0FCLKSEL,acomparator 0 clock selection"
bitfld.long 0x00 0.--2. " SEL                   ,ACMP0 Fast Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock,2: FFRO Clock,3: SYSPLL0 AUX0_PLL_Clock,4: SYSPLL0 AUX1_PLL_Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x7C4++0x03
line.long 0x00 "ACMP0FCLKDIV,acomparator 0 fclk divider"
bitfld.long 0x00 31. " REQFLAG               ,Divider status flag" "0,1"
textline "                                "
bitfld.long 0x00 30. " HALT                  ,Halts the divider counter" "0,1"
textline "                                "
bitfld.long 0x00 29. " RESET                 ,Resets the divider counter" "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " DIV                   ,Clock Divider Value Selection"
tree "FLEXCOMM[0]"
width 11.
group.long 0x500++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x504++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x508++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[1]"
width 11.
group.long 0x520++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x524++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x528++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[2]"
width 11.
group.long 0x540++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x544++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x548++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[3]"
width 11.
group.long 0x560++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x564++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x568++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[4]"
width 11.
group.long 0x580++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x584++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x588++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[5]"
width 11.
group.long 0x5A0++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x5A4++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x5A8++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[6]"
width 11.
group.long 0x5C0++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x5C4++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x5C8++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
tree "FLEXCOMM[7]"
width 11.
group.long 0x5E0++0x03
line.long 0x00 "FRGCLKSEL,FRG clock selection register N"
bitfld.long 0x00 0.--2. " SEL  ,Fractional Gen" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock,3: FFRO Clock,,,,7: None. this may be selected in order to reduce power when no output is needed"
group.long 0x5E4++0x03
line.long 0x00 "FRGCTL,FRG clock controller"
hexmask.long.byte 0x00 8.--15. 1. " MULT ,Numerator of the fractional divider"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " DIV  ,Denominator of the fractional divider"
group.long 0x5E8++0x03
line.long 0x00 "FCFCLKSEL,flexcomm clock selection"
bitfld.long 0x00 0.--2. " SEL  ,Flexxcomm Functional Clock Source Selection" "0: SFRO Clock,1: FFRO Clock,2: Audio PLL Clock,3: Master Clock In,4: FCn FRG Clock,,,7: None. this may be selected in order to reduce power when no output is needed"
tree.end
width 0x0B
tree.end
tree "CMP"
base ad:0x40139000
width 13.
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. " MAJOR           ,Major Version Number"
textline "                      "
hexmask.long.byte 0x00 16.--23. 1. " MINOR           ,Minor Version Number"
textline "                      "
hexmask.long.word 0x00 0.--15. 1. " FEATURE         ,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long 0x00 0.--31. 1. " PARAM           ,Parameter Registers"
group.long 0x08++0x03
line.long 0x00 "C0,CMP Control Register 0"
bitfld.long 0x00 31. " LINKEN          ,CMP to DAC link enable" "0: CMP to DAC link is disabled,1: CMP to DAC link is enabled"
textline "                      "
bitfld.long 0x00 30. " DMAEN           ,DMA Enable" "0: DMA is disabled,1: DMA is enabled"
textline "                      "
bitfld.long 0x00 28. " IER             ,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
textline "                      "
bitfld.long 0x00 27. " IEF             ,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
textline "                      "
eventfld.long 0x00 26. " CFR             ,Analog Comparator Flag Rising" "0: A rising edge has not been detected on COUT,1: A rising edge on COUT has occurred"
textline "                      "
eventfld.long 0x00 25. " CFF             ,Analog Comparator Flag Falling" "0: A falling edge has not been detected on COUT,1: A falling edge on COUT has occurred"
textline "                      "
rbitfld.long 0x00 24. " COUT            ,Analog Comparator Output" "0,1"
textline "                      "
hexmask.long.byte 0x00 16.--23. 1. " FPR             ,Filter Sample Period"
textline "                      "
bitfld.long 0x00 15. " SE              ,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
textline "                      "
bitfld.long 0x00 14. " WE              ,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
textline "                      "
bitfld.long 0x00 12. " PMODE           ,Power Mode Select" "0: Low Speed (LS) comparison mode is selected,1: High Speed (HS) comparison mode is selected"
textline "                      "
bitfld.long 0x00 11. " INVT            ,Comparator invert" "0: Does not invert the comparator output,1: Inverts the comparator output"
textline "                      "
bitfld.long 0x00 10. " COS             ,Comparator Output Select" "0: Set CMPO to equal COUT (filtered comparator output),1: Set CMPO to equal COUTA (unfiltered comparator output)"
textline "                      "
bitfld.long 0x00 9. " OPE             ,Comparator Output Pin Enable" "0: When OPE is 0. the comparator output (after window/filter settings dependent on software configurati..,1: When OPE is 1. and if the software has configured the comparator to own a packaged pin. the comparat.."
textline "                      "
bitfld.long 0x00 8. " EN              ,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
textline "                      "
bitfld.long 0x00 4.--6. " FILTER_CNT      ,Filter Sample Count" "0: Filter is disabled,1: 1 consecutive sample must agree (comparator output is simply sampled),2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
textline "                      "
bitfld.long 0x00 0.--1. " HYSTCTR         ,Comparator hard block hysteresis control" "0: The hard block output has level 0 hysteresis internally,1: The hard block output has level 1 hysteresis internally,2: The hard block output has level 2 hysteresis internally,3: The hard block output has level 3 hysteresis internally"
group.long 0x0C++0x03
line.long 0x00 "C1,CMP Control Register 1"
bitfld.long 0x00 28.--30. " PSEL            ,Plus Input MUX Control" "0: Internal Posivite Input 0 for Plus Channel -- Internal Minus Input,1: External Input 1 for Plus Channel -- Reference Input 0,2: External Input 2 for Plus Channel -- Reference Input 1,3: External Input 3 for Plus Channel -- Reference Input 2,4: External Input 4 for Plus Channel -- Reference Input 3,5: External Input 4 for Plus Channel -- Reference Input 4,6: External Input 4 for Plus Channel -- Reference Input 5,7: Internal 8b DAC output"
textline "                      "
bitfld.long 0x00 24.--26. " MSEL            ,Minus Input MUX Control" "0: Internal Negative Input 0 for Minus Channel -- Internal Minus Input,1: External Input 1 for Minus Channel -- Reference Input 0,2: External Input 2 for Minus Channel -- Reference Input 1,3: External Input 3 for Minus Channel -- Reference Input 2,4: External Input 4 for Minus Channel -- Reference Input 3,5: External Input 5 for Minus Channel -- Reference Input 4,6: External Input 6 for Minus Channel -- Reference Input 5,7: Internal 8b DAC output"
textline "                      "
bitfld.long 0x00 21. " CHN5            ,Channel 5 input enable" "0,1"
textline "                      "
bitfld.long 0x00 20. " CHN4            ,Channel 4 input enable" "0,1"
textline "                      "
bitfld.long 0x00 19. " CHN3            ,Channel 3 input enable" "0,1"
textline "                      "
bitfld.long 0x00 18. " CHN2            ,Channel 2 input enable" "0,1"
textline "                      "
bitfld.long 0x00 17. " CHN1            ,Channel 1 input enable" "0,1"
textline "                      "
bitfld.long 0x00 16. " CHN0            ,Channel 0 input enable" "0,1"
textline "                      "
bitfld.long 0x00 10. " DACEN           ,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
textline "                      "
bitfld.long 0x00 9. " VRSEL           ,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network supply reference Vin,1: Vin2 is selected as resistor ladder network supply reference Vin"
textline "                      "
bitfld.long 0x00 8. " DMODE           ,DAC Mode Selection" "0: DAC is selected to work in low speed and low power mode,1: DAC is selected to work in high speed high power mode"
textline "                      "
hexmask.long.byte 0x00 0.--7. 1. " VOSEL           ,DAC Output Voltage Select"
group.long 0x10++0x03
line.long 0x00 "C2,CMP Control Register 2"
bitfld.long 0x00 30. " RRIE            ,Round-Robin interrupt enable" "0: The round-robin interrupt is disabled,1: The round-robin interrupt is enabled when a comparison result changes from the last sample"
textline "                      "
bitfld.long 0x00 29. " FXMP            ,Fixed MUX Port" "0: The Plus port is fixed,1: The Minus port is fixed"
textline "                      "
bitfld.long 0x00 25.--27. " FXMXCH          ,Fixed channel selection" "0: External Reference Input 0 is selected as the fixed reference input for the fixed mux port,1: External Reference Input 1 is selected as the fixed reference input for the fixed mux port,2: External Reference Input 2 is selected as the fixed reference input for the fixed mux port,3: External Reference Input 3 is selected as the fixed reference input for the fixed mux port,4: External Reference Input 4 is selected as the fixed reference input for the fixed mux port,5: External Reference Input 5 is selected as the fixed reference input for the fixed mux port,,7: The 8bit DAC is selected as the fixed reference input for the fixed mux port"
textline "                      "
eventfld.long 0x00 21. " CH5F            ,CH5F" "0,1"
textline "                      "
eventfld.long 0x00 20. " CH4F            ,CH4F" "0,1"
textline "                      "
eventfld.long 0x00 19. " CH3F            ,CH3F" "0,1"
textline "                      "
eventfld.long 0x00 18. " CH2F            ,CH2F" "0,1"
textline "                      "
eventfld.long 0x00 17. " CH1F            ,CH1F" "0,1"
textline "                      "
eventfld.long 0x00 16. " CH0F            ,CH0F" "0,1"
textline "                      "
bitfld.long 0x00 14.--15. " NSAM            ,Number of sample clocks" "0: The comparison result is sampled as soon as the active channel is scanned in one round-robin clock,1: The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock,2: The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock,3: The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock"
textline "                      "
bitfld.long 0x00 8.--13. " INITMOD         ,Comparator and DAC initialization delay modulus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
bitfld.long 0x00 0.--5. " ACOn            ,ACOn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "C3,CMP Control Register 3"
bitfld.long 0x00 28. " PCHCTEN         ,Positive Channel Continuous Mode Enable" "0: Positive channel is in Discrete Mode and special timing needs to be configured,1: Positive channel is in Continuous Mode and no special timing is requried"
textline "                      "
bitfld.long 0x00 24. " NCHCTEN         ,Negative Channel Continuous Mode Enable" "0: Negative channel is in Discrete Mode and special timing needs to be configured,1: Negative channel is in Continuous Mode and no special timing is requried"
textline "                      "
bitfld.long 0x00 20. " RDIVE           ,Resistor Divider Enable" "0: The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in th..,1: The resistor is enabled because the inputs are above 1.8v"
textline "                      "
bitfld.long 0x00 16. " DMCS            ,Discrete Mode Clock Selection" "0: Slow clock is selected for the timing generation,1: Fast clock is selected for the timing generation"
textline "                      "
bitfld.long 0x00 12.--14. " ACSAT           ,Analog Comparator Sampling Time control" "0: The sampling time equals to T,1: The sampling time equasl to 2*T,2: The sampling time equasl to 4*T,3: The sampling time equasl to 8*T,4: The sampling time equasl to 16*T,5: The sampling time equasl to 32*T,6: The sampling time equasl to 64*T,7: The sampling time equasl to 256*T"
textline "                      "
bitfld.long 0x00 8.--10. " ACPH1TC         ,Analog Comparator Phase1 Timing Control" "0: Phase1 active time in one sampling period equals to T,1: Phase1 active time in one sampling period equals to 2*T,2: Phase1 active time in one sampling period equals to 4*T,3: Phase1 active time in one sampling period equals to 8*T,4: Phase1 active time in one sampling period equals to T,5: Phase1 active time in one sampling period equals to T,6: Phase1 active time in one sampling period equals to T,7: Phase1 active time in one sampling period equals to 0"
textline "                      "
bitfld.long 0x00 4.--6. " ACPH2TC         ,Analog Comparator Phase2 Timing Control" "0: Phase2 active time in one sampling period equals to T,1: Phase2 active time in one sampling period equals to 2*T,2: Phase2 active time in one sampling period equals to 4*T,3: Phase2 active time in one sampling period equals to 8*T,4: Phase2 active time in one sampling period equals to 16*T,5: Phase2 active time in one sampling period equals to 32*T,6: Phase2 active time in one sampling period equals to 64*T,7: Phase2 active time in one sampling period equals to 16*T"
group.long 0x18++0x03
line.long 0x00 "RR_TIMER_CR,Round-Robin Timer Control Register"
bitfld.long 0x00 31. " RR_TIMER_ENA    ,RR_TIMER enable" "0,1"
textline "                      "
hexmask.long 0x00 0.--27. 1. " RR_TIMER_RELOAD ,This field establishes the repetitive count rate for the timer"
width 0x0B
tree.end
tree "CRC"
tree "CRC_ENGINE"
base ad:0x40120000
width 9.
group.long 0x00++0x03
line.long 0x00 "MODE,CRC mode register"
bitfld.long 0x00 5. " CMPL_SUM    ,CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM" "0,1"
textline "                  "
bitfld.long 0x00 4. " BIT_RVS_SUM ,CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM" "0,1"
textline "                  "
bitfld.long 0x00 3. " CMPL_WR     ,Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA" "0,1"
textline "                  "
bitfld.long 0x00 2. " BIT_RVS_WR  ,Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR.." "0,1"
textline "                  "
bitfld.long 0x00 0.--1. " CRC_POLY    ,CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "SEED,CRC seed register"
hexmask.long 0x00 0.--31. 1. " CRC_SEED    ,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order.."
rgroup.long 0x08++0x03
line.long 0x00 "SUM,CRC checksum register"
hexmask.long 0x00 0.--31. 1. " CRC_SUM     ,The most recent CRC sum can be read through this register with selected bit order and 1's complement.."
wgroup.long 0x08++0x03
line.long 0x00 "WR_DATA,CRC data register"
hexmask.long 0x00 0.--31. 1. " CRC_WR_DATA ,Data written to this register will be taken to perform CRC calculation with selected bit order and 1.."
width 0x0B
tree.end
tree.end
tree "CTIMER"
tree "CTIMER0"
base ad:0x40028000
width 8.
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. " CR3INT       ,Interrupt flag for capture channel 3 event" "0,1"
textline "                 "
bitfld.long 0x00 6. " CR2INT       ,Interrupt flag for capture channel 2 event" "0,1"
textline "                 "
bitfld.long 0x00 5. " CR1INT       ,Interrupt flag for capture channel 1 event" "0,1"
textline "                 "
bitfld.long 0x00 4. " CR0INT       ,Interrupt flag for capture channel 0 event" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR3INT       ,Interrupt flag for match channel 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR2INT       ,Interrupt flag for match channel 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR1INT       ,Interrupt flag for match channel 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0INT       ,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. " CRST         ,Counter reset" "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " CEN          ,Counter enable" "0: DISABLED,1: ENABLED"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. " TCVAL        ,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. " PRVAL        ,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. " PCVAL        ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. " MR3RL        ,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 26. " MR2RL        ,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 25. " MR1RL        ,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 24. " MR0RL        ,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 11. " MR3S         ,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 10. " MR3R         ,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
textline "                 "
bitfld.long 0x00 9. " MR3I         ,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 8. " MR2S         ,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 7. " MR2R         ,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
textline "                 "
bitfld.long 0x00 6. " MR2I         ,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 5. " MR1S         ,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 4. " MR1R         ,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR1I         ,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR0S         ,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR0R         ,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0I         ,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
group.long 0x18++0x03
line.long 0x00 "MR[0],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR[1],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR[2],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR[3],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. " CAP3I        ,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAP3FE       ,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 9. " CAP3RE       ,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 8. " CAP2I        ,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 7. " CAP2FE       ,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 6. " CAP2RE       ,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 5. " CAP1I        ,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 4. " CAP1FE       ,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 3. " CAP1RE       ,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 2. " CAP0I        ,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAP0FE       ,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 0. " CAP0RE       ,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents o.." "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "CR[0],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR[1],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR[2],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x38++0x03
line.long 0x00 "CR[3],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3         ,External Match Control 3" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 8.--9. " EMC2         ,External Match Control 2" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 6.--7. " EMC1         ,External Match Control 1" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 4.--5. " EMC0         ,External Match Control 0" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 3. " EM3          ,External Match 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " EM2          ,External Match 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " EM1          ,External Match 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " EM0          ,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC        ,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,,"
textline "                 "
bitfld.long 0x00 4. " ENCC         ,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event sp.." "0,1"
textline "                 "
bitfld.long 0x00 2.--3. " CINSEL       ,Count Input Select When bits 1:0 in this register are not 00. these bits select which CAP pin is sam.." "0: CHANNEL_0,1: CHANNEL_1,2: CHANNEL_2,3: CHANNEL_3"
textline "                 "
bitfld.long 0x00 0.--1. " CTMODE       ,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescal.." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. " PWMEN3       ,PWM mode enable for channel3" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 2. " PWMEN2       ,PWM mode enable for channel2" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 1. " PWMEN1       ,PWM mode enable for channel1" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 0. " PWMEN0       ,PWM mode enable for channel0" "0: MATCH,1: PWM"
group.long 0x78++0x03
line.long 0x00 "MSR[0],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x7C++0x03
line.long 0x00 "MSR[1],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x80++0x03
line.long 0x00 "MSR[2],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x84++0x03
line.long 0x00 "MSR[3],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
width 0x0B
tree.end
tree "CTIMER1"
base ad:0x40029000
width 8.
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. " CR3INT       ,Interrupt flag for capture channel 3 event" "0,1"
textline "                 "
bitfld.long 0x00 6. " CR2INT       ,Interrupt flag for capture channel 2 event" "0,1"
textline "                 "
bitfld.long 0x00 5. " CR1INT       ,Interrupt flag for capture channel 1 event" "0,1"
textline "                 "
bitfld.long 0x00 4. " CR0INT       ,Interrupt flag for capture channel 0 event" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR3INT       ,Interrupt flag for match channel 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR2INT       ,Interrupt flag for match channel 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR1INT       ,Interrupt flag for match channel 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0INT       ,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. " CRST         ,Counter reset" "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " CEN          ,Counter enable" "0: DISABLED,1: ENABLED"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. " TCVAL        ,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. " PRVAL        ,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. " PCVAL        ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. " MR3RL        ,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 26. " MR2RL        ,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 25. " MR1RL        ,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 24. " MR0RL        ,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 11. " MR3S         ,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 10. " MR3R         ,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
textline "                 "
bitfld.long 0x00 9. " MR3I         ,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 8. " MR2S         ,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 7. " MR2R         ,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
textline "                 "
bitfld.long 0x00 6. " MR2I         ,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 5. " MR1S         ,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 4. " MR1R         ,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR1I         ,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR0S         ,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR0R         ,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0I         ,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
group.long 0x18++0x03
line.long 0x00 "MR[0],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR[1],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR[2],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR[3],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. " CAP3I        ,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAP3FE       ,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 9. " CAP3RE       ,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 8. " CAP2I        ,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 7. " CAP2FE       ,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 6. " CAP2RE       ,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 5. " CAP1I        ,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 4. " CAP1FE       ,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 3. " CAP1RE       ,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 2. " CAP0I        ,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAP0FE       ,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 0. " CAP0RE       ,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents o.." "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "CR[0],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR[1],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR[2],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x38++0x03
line.long 0x00 "CR[3],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3         ,External Match Control 3" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 8.--9. " EMC2         ,External Match Control 2" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 6.--7. " EMC1         ,External Match Control 1" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 4.--5. " EMC0         ,External Match Control 0" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 3. " EM3          ,External Match 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " EM2          ,External Match 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " EM1          ,External Match 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " EM0          ,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC        ,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,,"
textline "                 "
bitfld.long 0x00 4. " ENCC         ,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event sp.." "0,1"
textline "                 "
bitfld.long 0x00 2.--3. " CINSEL       ,Count Input Select When bits 1:0 in this register are not 00. these bits select which CAP pin is sam.." "0: CHANNEL_0,1: CHANNEL_1,2: CHANNEL_2,3: CHANNEL_3"
textline "                 "
bitfld.long 0x00 0.--1. " CTMODE       ,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescal.." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. " PWMEN3       ,PWM mode enable for channel3" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 2. " PWMEN2       ,PWM mode enable for channel2" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 1. " PWMEN1       ,PWM mode enable for channel1" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 0. " PWMEN0       ,PWM mode enable for channel0" "0: MATCH,1: PWM"
group.long 0x78++0x03
line.long 0x00 "MSR[0],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x7C++0x03
line.long 0x00 "MSR[1],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x80++0x03
line.long 0x00 "MSR[2],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x84++0x03
line.long 0x00 "MSR[3],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
width 0x0B
tree.end
tree "CTIMER2"
base ad:0x4002A000
width 8.
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. " CR3INT       ,Interrupt flag for capture channel 3 event" "0,1"
textline "                 "
bitfld.long 0x00 6. " CR2INT       ,Interrupt flag for capture channel 2 event" "0,1"
textline "                 "
bitfld.long 0x00 5. " CR1INT       ,Interrupt flag for capture channel 1 event" "0,1"
textline "                 "
bitfld.long 0x00 4. " CR0INT       ,Interrupt flag for capture channel 0 event" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR3INT       ,Interrupt flag for match channel 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR2INT       ,Interrupt flag for match channel 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR1INT       ,Interrupt flag for match channel 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0INT       ,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. " CRST         ,Counter reset" "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " CEN          ,Counter enable" "0: DISABLED,1: ENABLED"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. " TCVAL        ,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. " PRVAL        ,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. " PCVAL        ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. " MR3RL        ,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 26. " MR2RL        ,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 25. " MR1RL        ,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 24. " MR0RL        ,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 11. " MR3S         ,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 10. " MR3R         ,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
textline "                 "
bitfld.long 0x00 9. " MR3I         ,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 8. " MR2S         ,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 7. " MR2R         ,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
textline "                 "
bitfld.long 0x00 6. " MR2I         ,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 5. " MR1S         ,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 4. " MR1R         ,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR1I         ,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR0S         ,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR0R         ,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0I         ,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
group.long 0x18++0x03
line.long 0x00 "MR[0],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR[1],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR[2],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR[3],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. " CAP3I        ,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAP3FE       ,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 9. " CAP3RE       ,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 8. " CAP2I        ,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 7. " CAP2FE       ,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 6. " CAP2RE       ,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 5. " CAP1I        ,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 4. " CAP1FE       ,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 3. " CAP1RE       ,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 2. " CAP0I        ,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAP0FE       ,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 0. " CAP0RE       ,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents o.." "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "CR[0],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR[1],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR[2],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x38++0x03
line.long 0x00 "CR[3],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3         ,External Match Control 3" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 8.--9. " EMC2         ,External Match Control 2" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 6.--7. " EMC1         ,External Match Control 1" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 4.--5. " EMC0         ,External Match Control 0" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 3. " EM3          ,External Match 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " EM2          ,External Match 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " EM1          ,External Match 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " EM0          ,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC        ,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,,"
textline "                 "
bitfld.long 0x00 4. " ENCC         ,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event sp.." "0,1"
textline "                 "
bitfld.long 0x00 2.--3. " CINSEL       ,Count Input Select When bits 1:0 in this register are not 00. these bits select which CAP pin is sam.." "0: CHANNEL_0,1: CHANNEL_1,2: CHANNEL_2,3: CHANNEL_3"
textline "                 "
bitfld.long 0x00 0.--1. " CTMODE       ,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescal.." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. " PWMEN3       ,PWM mode enable for channel3" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 2. " PWMEN2       ,PWM mode enable for channel2" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 1. " PWMEN1       ,PWM mode enable for channel1" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 0. " PWMEN0       ,PWM mode enable for channel0" "0: MATCH,1: PWM"
group.long 0x78++0x03
line.long 0x00 "MSR[0],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x7C++0x03
line.long 0x00 "MSR[1],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x80++0x03
line.long 0x00 "MSR[2],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x84++0x03
line.long 0x00 "MSR[3],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
width 0x0B
tree.end
tree "CTIMER3"
base ad:0x4002B000
width 8.
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. " CR3INT       ,Interrupt flag for capture channel 3 event" "0,1"
textline "                 "
bitfld.long 0x00 6. " CR2INT       ,Interrupt flag for capture channel 2 event" "0,1"
textline "                 "
bitfld.long 0x00 5. " CR1INT       ,Interrupt flag for capture channel 1 event" "0,1"
textline "                 "
bitfld.long 0x00 4. " CR0INT       ,Interrupt flag for capture channel 0 event" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR3INT       ,Interrupt flag for match channel 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR2INT       ,Interrupt flag for match channel 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR1INT       ,Interrupt flag for match channel 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0INT       ,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. " CRST         ,Counter reset" "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " CEN          ,Counter enable" "0: DISABLED,1: ENABLED"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. " TCVAL        ,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. " PRVAL        ,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. " PCVAL        ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. " MR3RL        ,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 26. " MR2RL        ,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 25. " MR1RL        ,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 24. " MR0RL        ,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 11. " MR3S         ,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 10. " MR3R         ,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
textline "                 "
bitfld.long 0x00 9. " MR3I         ,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 8. " MR2S         ,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 7. " MR2R         ,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
textline "                 "
bitfld.long 0x00 6. " MR2I         ,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 5. " MR1S         ,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 4. " MR1R         ,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR1I         ,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR0S         ,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR0R         ,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0I         ,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
group.long 0x18++0x03
line.long 0x00 "MR[0],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR[1],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR[2],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR[3],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. " CAP3I        ,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAP3FE       ,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 9. " CAP3RE       ,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 8. " CAP2I        ,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 7. " CAP2FE       ,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 6. " CAP2RE       ,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 5. " CAP1I        ,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 4. " CAP1FE       ,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 3. " CAP1RE       ,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 2. " CAP0I        ,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAP0FE       ,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 0. " CAP0RE       ,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents o.." "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "CR[0],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR[1],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR[2],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x38++0x03
line.long 0x00 "CR[3],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3         ,External Match Control 3" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 8.--9. " EMC2         ,External Match Control 2" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 6.--7. " EMC1         ,External Match Control 1" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 4.--5. " EMC0         ,External Match Control 0" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 3. " EM3          ,External Match 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " EM2          ,External Match 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " EM1          ,External Match 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " EM0          ,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC        ,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,,"
textline "                 "
bitfld.long 0x00 4. " ENCC         ,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event sp.." "0,1"
textline "                 "
bitfld.long 0x00 2.--3. " CINSEL       ,Count Input Select When bits 1:0 in this register are not 00. these bits select which CAP pin is sam.." "0: CHANNEL_0,1: CHANNEL_1,2: CHANNEL_2,3: CHANNEL_3"
textline "                 "
bitfld.long 0x00 0.--1. " CTMODE       ,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescal.." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. " PWMEN3       ,PWM mode enable for channel3" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 2. " PWMEN2       ,PWM mode enable for channel2" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 1. " PWMEN1       ,PWM mode enable for channel1" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 0. " PWMEN0       ,PWM mode enable for channel0" "0: MATCH,1: PWM"
group.long 0x78++0x03
line.long 0x00 "MSR[0],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x7C++0x03
line.long 0x00 "MSR[1],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x80++0x03
line.long 0x00 "MSR[2],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x84++0x03
line.long 0x00 "MSR[3],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
width 0x0B
tree.end
tree "CTIMER4"
base ad:0x4002C000
width 8.
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. " CR3INT       ,Interrupt flag for capture channel 3 event" "0,1"
textline "                 "
bitfld.long 0x00 6. " CR2INT       ,Interrupt flag for capture channel 2 event" "0,1"
textline "                 "
bitfld.long 0x00 5. " CR1INT       ,Interrupt flag for capture channel 1 event" "0,1"
textline "                 "
bitfld.long 0x00 4. " CR0INT       ,Interrupt flag for capture channel 0 event" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR3INT       ,Interrupt flag for match channel 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR2INT       ,Interrupt flag for match channel 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR1INT       ,Interrupt flag for match channel 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0INT       ,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. " CRST         ,Counter reset" "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " CEN          ,Counter enable" "0: DISABLED,1: ENABLED"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. " TCVAL        ,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. " PRVAL        ,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. " PCVAL        ,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. " MR3RL        ,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 26. " MR2RL        ,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 25. " MR1RL        ,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 24. " MR0RL        ,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via.." "0,1"
textline "                 "
bitfld.long 0x00 11. " MR3S         ,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 10. " MR3R         ,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
textline "                 "
bitfld.long 0x00 9. " MR3I         ,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 8. " MR2S         ,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 7. " MR2R         ,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
textline "                 "
bitfld.long 0x00 6. " MR2I         ,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 5. " MR1S         ,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 4. " MR1R         ,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
textline "                 "
bitfld.long 0x00 3. " MR1I         ,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
textline "                 "
bitfld.long 0x00 2. " MR0S         ,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
textline "                 "
bitfld.long 0x00 1. " MR0R         ,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
textline "                 "
bitfld.long 0x00 0. " MR0I         ,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
group.long 0x18++0x03
line.long 0x00 "MR[0],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x1C++0x03
line.long 0x00 "MR[1],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x20++0x03
line.long 0x00 "MR[2],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x24++0x03
line.long 0x00 "MR[3],Match Register"
hexmask.long 0x00 0.--31. 1. " MATCH        ,Timer counter match value"
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. " CAP3I        ,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAP3FE       ,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 9. " CAP3RE       ,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 8. " CAP2I        ,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 7. " CAP2FE       ,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 6. " CAP2RE       ,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 5. " CAP1I        ,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 4. " CAP1FE       ,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 3. " CAP1RE       ,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents o.." "0,1"
textline "                 "
bitfld.long 0x00 2. " CAP0I        ,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAP0FE       ,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents .." "0,1"
textline "                 "
bitfld.long 0x00 0. " CAP0RE       ,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents o.." "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "CR[0],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x30++0x03
line.long 0x00 "CR[1],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x34++0x03
line.long 0x00 "CR[2],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
rgroup.long 0x38++0x03
line.long 0x00 "CR[3],Capture Register"
hexmask.long 0x00 0.--31. 1. " CAP          ,Timer counter capture value"
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. " EMC3         ,External Match Control 3" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 8.--9. " EMC2         ,External Match Control 2" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 6.--7. " EMC1         ,External Match Control 1" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 4.--5. " EMC0         ,External Match Control 0" "0: DO_NOTHING,1: CLEAR,2: SET,3: TOGGLE"
textline "                 "
bitfld.long 0x00 3. " EM3          ,External Match 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " EM2          ,External Match 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " EM1          ,External Match 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " EM0          ,External Match 0" "0,1"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. " SELCC        ,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,,"
textline "                 "
bitfld.long 0x00 4. " ENCC         ,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event sp.." "0,1"
textline "                 "
bitfld.long 0x00 2.--3. " CINSEL       ,Count Input Select When bits 1:0 in this register are not 00. these bits select which CAP pin is sam.." "0: CHANNEL_0,1: CHANNEL_1,2: CHANNEL_2,3: CHANNEL_3"
textline "                 "
bitfld.long 0x00 0.--1. " CTMODE       ,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescal.." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. " PWMEN3       ,PWM mode enable for channel3" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 2. " PWMEN2       ,PWM mode enable for channel2" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 1. " PWMEN1       ,PWM mode enable for channel1" "0: MATCH,1: PWM"
textline "                 "
bitfld.long 0x00 0. " PWMEN0       ,PWM mode enable for channel0" "0: MATCH,1: PWM"
group.long 0x78++0x03
line.long 0x00 "MSR[0],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x7C++0x03
line.long 0x00 "MSR[1],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x80++0x03
line.long 0x00 "MSR[2],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
group.long 0x84++0x03
line.long 0x00 "MSR[3],Match Shadow Register"
hexmask.long 0x00 0.--31. 1. " MATCH_Shadow ,Timer counter match value"
width 0x0B
tree.end
tree.end
tree "DMA"
tree "DMA0"
base ad:0x40104000
width 12.
group.long 0x00++0x03
line.long 0x00 "CTRL,DMA control"
bitfld.long 0x00 0. " ENABLE       ,DMA controller master enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x04++0x03
line.long 0x00 "INTSTAT,Interrupt status"
bitfld.long 0x00 2. " ACTIVEERRINT ,Summarizes whether any error interrupts are pending" "0: NOT_PENDING,1: PENDING"
textline "                     "
bitfld.long 0x00 1. " ACTIVEINT    ,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: NOT_PENDING,1: PENDING"
group.long 0x08++0x03
line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x00 9.--31. 1. " OFFSET       ,Address bits 31:9 of the beginning of the DMA descriptor table"
group.long 0x20++0x03
line.long 0x00 "ENABLESET0,Channel Enable read and Set for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ENA          ,Enable for DMA channel 0"
wgroup.long 0x28++0x03
line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. " CLR          ,Writing ones to this register clears the corresponding bits in ENABLESET0"
rgroup.long 0x30++0x03
line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ACT          ,Active flag for DMA channel 0"
rgroup.long 0x38++0x03
line.long 0x00 "BUSY0,Channel Busy status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " BSY          ,Busy flag for DMA channel 0"
group.long 0x40++0x03
line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ERR          ,Error Interrupt flag for DMA channel 0"
group.long 0x48++0x03
line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
hexmask.long 0x00 0.--31. 1. " INTEN        ,Interrupt Enable read and set for DMA channel 0"
wgroup.long 0x50++0x03
line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. " CLR          ,Writing ones to this register clears corresponding bits in the DMAIntEnSet0"
group.long 0x58++0x03
line.long 0x00 "INTA0,Interrupt A status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " IA           ,Interrupt A status for DMA channel 0"
group.long 0x60++0x03
line.long 0x00 "INTB0,Interrupt B status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " IB           ,Interrupt B status for DMA channel 0"
wgroup.long 0x68++0x03
line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels"
hexmask.long 0x00 0.--31. 1. " SV           ,SetValid control for DMA channel 0"
wgroup.long 0x70++0x03
line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels"
hexmask.long 0x00 0.--31. 1. " TRIG         ,Set Trigger control bit for DMA channel 0"
wgroup.long 0x78++0x03
line.long 0x00 "ABORT0,Channel Abort control for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ABORTCTRL    ,Abort control for DMA channel 0"
tree "CHANNEL[0]"
width 9.
group.long 0x400++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x404++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x408++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[1]"
width 9.
group.long 0x410++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x414++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x418++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[2]"
width 9.
group.long 0x420++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x424++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x428++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[3]"
width 9.
group.long 0x430++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x434++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x438++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[4]"
width 9.
group.long 0x440++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x444++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x448++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[5]"
width 9.
group.long 0x450++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x454++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x458++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[6]"
width 9.
group.long 0x460++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x464++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x468++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[7]"
width 9.
group.long 0x470++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x474++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x478++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[8]"
width 9.
group.long 0x480++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x484++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x488++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[9]"
width 9.
group.long 0x490++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x494++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x498++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[10]"
width 9.
group.long 0x4A0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4A4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4A8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[11]"
width 9.
group.long 0x4B0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4B4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4B8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[12]"
width 9.
group.long 0x4C0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4C4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4C8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[13]"
width 9.
group.long 0x4D0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4D4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4D8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[14]"
width 9.
group.long 0x4E0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4E4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4E8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[15]"
width 9.
group.long 0x4F0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4F4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4F8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[16]"
width 9.
group.long 0x500++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x504++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x508++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[17]"
width 9.
group.long 0x510++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x514++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x518++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[18]"
width 9.
group.long 0x520++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x524++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x528++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[19]"
width 9.
group.long 0x530++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x534++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x538++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[20]"
width 9.
group.long 0x540++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x544++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x548++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[21]"
width 9.
group.long 0x550++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x554++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x558++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[22]"
width 9.
group.long 0x560++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x564++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x568++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[23]"
width 9.
group.long 0x570++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x574++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x578++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[24]"
width 9.
group.long 0x580++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x584++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x588++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[25]"
width 9.
group.long 0x590++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x594++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x598++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[26]"
width 9.
group.long 0x5A0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5A4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5A8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[27]"
width 9.
group.long 0x5B0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5B4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5B8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[28]"
width 9.
group.long 0x5C0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5C4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5C8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[29]"
width 9.
group.long 0x5D0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5D4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5D8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[30]"
width 9.
group.long 0x5E0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5E4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5E8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[31]"
width 9.
group.long 0x5F0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5F4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5F8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
width 0x0B
tree.end
tree "DMA1"
base ad:0x40105000
width 12.
group.long 0x00++0x03
line.long 0x00 "CTRL,DMA control"
bitfld.long 0x00 0. " ENABLE       ,DMA controller master enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x04++0x03
line.long 0x00 "INTSTAT,Interrupt status"
bitfld.long 0x00 2. " ACTIVEERRINT ,Summarizes whether any error interrupts are pending" "0: NOT_PENDING,1: PENDING"
textline "                     "
bitfld.long 0x00 1. " ACTIVEINT    ,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: NOT_PENDING,1: PENDING"
group.long 0x08++0x03
line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x00 9.--31. 1. " OFFSET       ,Address bits 31:9 of the beginning of the DMA descriptor table"
group.long 0x20++0x03
line.long 0x00 "ENABLESET0,Channel Enable read and Set for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ENA          ,Enable for DMA channel 0"
wgroup.long 0x28++0x03
line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. " CLR          ,Writing ones to this register clears the corresponding bits in ENABLESET0"
rgroup.long 0x30++0x03
line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ACT          ,Active flag for DMA channel 0"
rgroup.long 0x38++0x03
line.long 0x00 "BUSY0,Channel Busy status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " BSY          ,Busy flag for DMA channel 0"
group.long 0x40++0x03
line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ERR          ,Error Interrupt flag for DMA channel 0"
group.long 0x48++0x03
line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
hexmask.long 0x00 0.--31. 1. " INTEN        ,Interrupt Enable read and set for DMA channel 0"
wgroup.long 0x50++0x03
line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. " CLR          ,Writing ones to this register clears corresponding bits in the DMAIntEnSet0"
group.long 0x58++0x03
line.long 0x00 "INTA0,Interrupt A status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " IA           ,Interrupt A status for DMA channel 0"
group.long 0x60++0x03
line.long 0x00 "INTB0,Interrupt B status for all DMA channels"
hexmask.long 0x00 0.--31. 1. " IB           ,Interrupt B status for DMA channel 0"
wgroup.long 0x68++0x03
line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels"
hexmask.long 0x00 0.--31. 1. " SV           ,SetValid control for DMA channel 0"
wgroup.long 0x70++0x03
line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels"
hexmask.long 0x00 0.--31. 1. " TRIG         ,Set Trigger control bit for DMA channel 0"
wgroup.long 0x78++0x03
line.long 0x00 "ABORT0,Channel Abort control for all DMA channels"
hexmask.long 0x00 0.--31. 1. " ABORTCTRL    ,Abort control for DMA channel 0"
tree "CHANNEL[0]"
width 9.
group.long 0x400++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x404++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x408++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[1]"
width 9.
group.long 0x410++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x414++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x418++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[2]"
width 9.
group.long 0x420++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x424++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x428++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[3]"
width 9.
group.long 0x430++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x434++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x438++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[4]"
width 9.
group.long 0x440++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x444++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x448++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[5]"
width 9.
group.long 0x450++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x454++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x458++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[6]"
width 9.
group.long 0x460++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x464++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x468++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[7]"
width 9.
group.long 0x470++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x474++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x478++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[8]"
width 9.
group.long 0x480++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x484++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x488++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[9]"
width 9.
group.long 0x490++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x494++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x498++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[10]"
width 9.
group.long 0x4A0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4A4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4A8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[11]"
width 9.
group.long 0x4B0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4B4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4B8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[12]"
width 9.
group.long 0x4C0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4C4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4C8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[13]"
width 9.
group.long 0x4D0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4D4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4D8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[14]"
width 9.
group.long 0x4E0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4E4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4E8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[15]"
width 9.
group.long 0x4F0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x4F4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x4F8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[16]"
width 9.
group.long 0x500++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x504++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x508++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[17]"
width 9.
group.long 0x510++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x514++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x518++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[18]"
width 9.
group.long 0x520++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x524++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x528++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[19]"
width 9.
group.long 0x530++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x534++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x538++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[20]"
width 9.
group.long 0x540++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x544++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x548++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[21]"
width 9.
group.long 0x550++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x554++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x558++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[22]"
width 9.
group.long 0x560++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x564++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x568++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[23]"
width 9.
group.long 0x570++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x574++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x578++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[24]"
width 9.
group.long 0x580++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x584++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x588++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[25]"
width 9.
group.long 0x590++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x594++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x598++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[26]"
width 9.
group.long 0x5A0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5A4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5A8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[27]"
width 9.
group.long 0x5B0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5B4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5B8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[28]"
width 9.
group.long 0x5C0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5C4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5C8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[29]"
width 9.
group.long 0x5D0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5D4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5D8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[30]"
width 9.
group.long 0x5E0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5E4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5E8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
tree "CHANNEL[31]"
width 9.
group.long 0x5F0++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. " CHPRIORITY   ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
textline "                  "
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 8.--11. " BURSTPOWER   ,Burst Power is used in two ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                  "
bitfld.long 0x00 6. " TRIGBURST    ,Trigger Burst" "0: Single transfer,1: Burst transfer"
textline "                  "
bitfld.long 0x00 5. " TRIGTYPE     ,Trigger Type" "0: EDGE,1: LEVEL"
textline "                  "
bitfld.long 0x00 4. " TRIGPOL      ,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
textline "                  "
bitfld.long 0x00 1. " HWTRIGEN     ,Hardware Triggering Enable for this channel" "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " PERIPHREQEN  ,Peripheral request Enable" "0: DISABLED,1: ENABLED"
rgroup.long 0x5F4++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. " TRIG         ,Trigger flag" "0: NOT_TRIGGERED,1: TRIGGERED"
textline "                  "
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "0: NO_EFFECT,1: VALID_PENDING"
group.long 0x5F8++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT    ,Total number of transfers to be performed. minus 1 encoded"
textline "                  "
bitfld.long 0x00 14.--15. " DSTINC       ,Determines whether the destination address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 12.--13. " SRCINC       ,Determines whether the source address is incremented for each DMA transfer" "0: NO_INCREMENT,1: WIDTH_X_1,2: WIDTH_X_2,3: WIDTH_X_4"
textline "                  "
bitfld.long 0x00 8.--9. " WIDTH        ,Transfer width used for this DMA channel" "0: BIT_8,1: BIT_16,2: BIT_32,"
textline "                  "
bitfld.long 0x00 5. " SETINTB      ,Set Interrupt flag B for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 4. " SETINTA      ,Set Interrupt flag A for this channel" "0: NO_EFFECT,1: SET"
textline "                  "
bitfld.long 0x00 3. " CLRTRIG      ,Clear Trigger" "0: NOT_CLEARED,1: CLEARED"
textline "                  "
bitfld.long 0x00 2. " SWTRIG       ,Software Trigger" "0: NOT_SET,1: SET"
textline "                  "
bitfld.long 0x00 1. " RELOAD       ,Indicates whether the channel's control structure will be reloaded when the current descriptor is ex.." "0: DISABLED,1: ENABLED"
textline "                  "
bitfld.long 0x00 0. " CFGVALID     ,Configuration Valid flag" "0: NOT_VALID,1: VALID"
tree.end
width 0x0B
tree.end
tree.end
tree "DMIC"
tree "DMIC0"
base ad:0x40121000
width 18.
group.long 0xF00++0x03
line.long 0x00 "CHANEN,Channel Enable register"
bitfld.long 0x00 7. " EN_CH7     ,Enable channel 7" "0,1"
textline "                           "
bitfld.long 0x00 6. " EN_CH6     ,Enable channel 6" "0,1"
textline "                           "
bitfld.long 0x00 5. " EN_CH5     ,Enable channel 5" "0,1"
textline "                           "
bitfld.long 0x00 4. " EN_CH4     ,Enable channel 4" "0,1"
textline "                           "
bitfld.long 0x00 3. " EN_CH3     ,Enable channel 3" "0,1"
textline "                           "
bitfld.long 0x00 2. " EN_CH2     ,Enable channel 2" "0,1"
textline "                           "
bitfld.long 0x00 1. " EN_CH1     ,Enable channel 1" "0,1"
textline "                           "
bitfld.long 0x00 0. " EN_CH0     ,Enable channel 0" "0,1"
group.long 0xF10++0x03
line.long 0x00 "USE2FS,Use 2FS register"
bitfld.long 0x00 0. " USE2FS     ,Use 2FS register" "0: Use 1FS output for PCM data,1: Use 2FS output for PCM data"
group.long 0xF14++0x03
line.long 0x00 "GLOBAL_SYNC_EN,global sync enable"
hexmask.long.byte 0x00 0.--7. 1. " CH_SYNC_EN ,Choose which channels to sync to global sync (7:0) corresponds to the 8 channels"
group.long 0xF18++0x03
line.long 0x00 "GLOBAL_COUNT_VAL,no description available"
hexmask.long 0x00 0.--31. 1. " CCOUNTVAL  ,32bit value. global sync counter will trigger a pulse whenever count reaches GCOUNTVAL"
group.long 0xF1C++0x03
line.long 0x00 "DECRESET,no description available"
hexmask.long.byte 0x00 0.--7. 1. " DECRESET   ,no description available"
group.long 0xF80++0x03
line.long 0x00 "HWVADGAIN,HWVAD input gain register"
bitfld.long 0x00 0.--3. " INPUTGAIN  ,Gain factor for input signal into HWVAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF84++0x03
line.long 0x00 "HWVADHPFS,HWVAD filter control register"
bitfld.long 0x00 0.--1. " HPFS       ,This field chooses the High Pass filter in first part of HWVAD" "0: First filter by-pass,1: High pass filter with -3dB cut-off at 1750Hz,2: High pass filter with -3dB cut-off at 215Hz,"
group.long 0xF88++0x03
line.long 0x00 "HWVADST10,HWVAD control register"
bitfld.long 0x00 0. " ST10       ,1' means enter stage 1 of VAD. ie a sound change has been detected and the HWVAD is being allowed to.." "0: Normal operation. waiting for HWVAD trigger event (stage 0),1: Reset internal interrupt flag by writing a '1' pulse"
group.long 0xF8C++0x03
line.long 0x00 "HWVADRSTT,HWVAD filter reset register"
bitfld.long 0x00 0. " RSTT       ,Reset HWVAD" "0,1"
group.long 0xF90++0x03
line.long 0x00 "HWVADTHGN,HWVAD noise estimator gain register"
bitfld.long 0x00 0.--3. " THGN       ,Gain Factor for Noise-floor - use a positive number to make average less sensitive to sudden changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF94++0x03
line.long 0x00 "HWVADTHGS,HWVAD signal estimator gain register"
bitfld.long 0x00 0.--3. " THGS       ,Signal Gain factor - use a postive number to make current signal stand out more over longer term ave.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF98++0x03
line.long 0x00 "HWVADLOWZ,HWVAD noise envelope estimator register"
hexmask.long.word 0x00 0.--15. 1. " LOWZ       ,Average noise-floor value"
tree "CHANNEL[0]"
width 14.
group.long 0x00++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x04++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x0C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x84++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x88++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x8C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x90++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[1]"
width 14.
group.long 0x100++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x104++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x108++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x10C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x110++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x180++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x184++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x188++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x18C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x190++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[2]"
width 14.
group.long 0x200++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x204++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x208++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x20C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x210++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x280++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x284++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x288++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x28C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x290++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[3]"
width 14.
group.long 0x300++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x304++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x308++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x30C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x310++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x380++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x384++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x388++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x38C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x390++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[4]"
width 14.
group.long 0x400++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x404++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x40C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x480++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x484++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x488++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x48C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x490++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[5]"
width 14.
group.long 0x500++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x504++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x508++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x50C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x510++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x580++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x584++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x588++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x58C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x590++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[6]"
width 14.
group.long 0x600++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x604++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x608++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x60C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x610++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x680++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x684++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x688++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x68C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x690++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
tree "CHANNEL[7]"
width 14.
group.long 0x700++0x03
line.long 0x00 "OSR,CIC Filter decimation rate"
hexmask.long.byte 0x00 0.--7. 1. " OSR             ,Selects the oversample rate for the related input channel"
group.long 0x704++0x03
line.long 0x00 "DIVHFCLK,Divider for generating PDM clock from DMIC clock input"
bitfld.long 0x00 0.--3. " PDMDIV          ,Divide by factor to create PDM Clock (enumerated type)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x708++0x03
line.long 0x00 "PREAC2FSCOEF,Compensation filter for 2FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x70C++0x03
line.long 0x00 "PREAC4FSCOEF,Compensation filter for 4FS"
bitfld.long 0x00 0.--1. " COMP            ,Co-efficient choice for CIC droop compensation droop filter" "0,1,2,3"
group.long 0x710++0x03
line.long 0x00 "GAINSHIFT,Decimator output gain adjustment"
bitfld.long 0x00 0.--5. " GAIN            ,Gain shift for decimator output (can be positive or negative number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x780++0x03
line.long 0x00 "FIFO_CTRL,FIFO Control"
bitfld.long 0x00 16.--20. " TRIGLVL         ,Trigger level for interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 3. " DMAEN           ,DMA enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled"
textline "                       "
bitfld.long 0x00 2. " INTEN           ,Interrupt enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled"
textline "                       "
bitfld.long 0x00 1. " RESETN          ,FIFO reset" "0: Reset the FIFO,1: Normal operation"
textline "                       "
bitfld.long 0x00 0. " ENABLE          ,FIFO enable" "0: FIFO is not enabled,1: FIFO is enabled"
group.long 0x784++0x03
line.long 0x00 "FIFO_STATUS,FIFO Status"
bitfld.long 0x00 2. " UNDERRUN        ,Underrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 1. " OVERRUN         ,Overrun Detected (write 1 to clear)" "0,1"
textline "                       "
bitfld.long 0x00 0. " INT             ,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long 0x788++0x03
line.long 0x00 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x00 0.--23. 1. " DATA            ,PCM Data"
group.long 0x78C++0x03
line.long 0x00 "PHY_CTRL,Phy Ctrl"
bitfld.long 0x00 1. " PHY_HALF        ,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling"
textline "                       "
bitfld.long 0x00 0. " PHY_FALL        ,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK"
group.long 0x790++0x03
line.long 0x00 "DC_CTRL,DC Filter Control"
bitfld.long 0x00 9. " SIGNEXTEND      ,Sign extend" "0: The top byte of the FIFODATA register is always 0,1: The top byte of the FIFODATA register is sign extended"
textline "                       "
bitfld.long 0x00 8. " SATURATEAT16BIT ,Selects 16-bit saturation" "0: Results roll over if out range and do not saturate,1: If the result overflows. it saturates at 0xFFFF for positive overflow and 0x8000 for negative overfl.."
textline "                       "
bitfld.long 0x00 4.--7. " DCGAIN          ,Fine gain adjustment in the form of a number of bits to downshift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--1. " DCPOLE          ,DC block filter" "0: Flat response. no filter,1: HZ_155,2: HZ_78,3: HZ_39"
tree.end
width 0x0B
tree.end
tree.end
tree "FLEXCOMM"
tree "FLEXCOMM0"
base ad:0x40106000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM1"
base ad:0x40107000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM2"
base ad:0x40108000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM3"
base ad:0x40109000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM4"
base ad:0x40122000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM5"
base ad:0x40123000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM6"
base ad:0x40124000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM7"
base ad:0x40125000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM14"
base ad:0x40126000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "FLEXCOMM15"
base ad:0x40127000
width 8.
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. " ID           ,Flexcomm ID"
textline "                 "
rbitfld.long 0x00 7. " I2SPRESENT   ,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
textline "                 "
rbitfld.long 0x00 6. " I2CPRESENT   ,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
textline "                 "
rbitfld.long 0x00 5. " SPIPRESENT   ,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
textline "                 "
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "0: This Flexcomm does not include the USART function,1: This Flexcomm includes the USART function"
textline "                 "
bitfld.long 0x00 3. " LOCK         ,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset"
textline "                 "
bitfld.long 0x00 0.--2. " PERSEL       ,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,,"
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID           ,Module identifier for the selected function"
textline "                 "
rbitfld.long 0x00 12.--15. " Major_Rev    ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
rbitfld.long 0x00 8.--11. " Minor_Rev    ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree.end
tree "FLEXSPI"
base ad:0x40134000
width 14.
group.long 0x00++0x03
line.long 0x00 "MCR0,Module Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. " AHBGRANTWAIT    ,Timeout wait cycle for AHB command grant"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " IPGRANTWAIT     ,Time out wait cycle for IP command grant"
textline "                       "
bitfld.long 0x00 15. " LEARNEN         ,This bit is used to enable/disable data learning feature" "0: LEARNEN_0,1: LEARNEN_1"
textline "                       "
bitfld.long 0x00 14. " SCKFREERUNEN    ,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
textline "                       "
bitfld.long 0x00 13. " COMBINATIONEN   ,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and .." "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
textline "                       "
bitfld.long 0x00 12. " DOZEEN          ,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
textline "                       "
bitfld.long 0x00 11. " HSEN            ,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for half speed commands,1: Enable divide by 2 of serial flash clock for half speed commands"
textline "                       "
bitfld.long 0x00 8.--10. " SERCLKDIV       ,The serial root clock could be divided inside FlexSPI wrapper" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
textline "                       "
bitfld.long 0x00 4.--5. " RXCLKSRC        ,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI Controller and loopback internally,1: Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad,,3: Flash provided Read strobe and input from DQS pad"
textline "                       "
bitfld.long 0x00 1. " MDIS            ,Module Disable" "0,1"
textline "                       "
bitfld.long 0x00 0. " SWRESET         ,Software Reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "MCR1,Module Control Register 1"
hexmask.long.word 0x00 16.--31. 1. " SEQWAIT         ,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " AHBBUSWAIT      ,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or d.."
group.long 0x08++0x03
line.long 0x00 "MCR2,Module Control Register 2"
hexmask.long.byte 0x00 24.--31. 1. " RESUMEWAIT      ,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
textline "                       "
bitfld.long 0x00 19. " SCKBDIFFOPT     ,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK)"
textline "                       "
bitfld.long 0x00 15. " SAMEDEVICEEN    ,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode. FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flas..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2"
textline "                       "
bitfld.long 0x00 14. " CLRLEARNPHASE   ,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
textline "                       "
bitfld.long 0x00 11. " CLRAHBBUFOPT    ,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexS.." "0: AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK,1: AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK"
group.long 0x0C++0x03
line.long 0x00 "AHBCR,AHB Bus Control Register"
bitfld.long 0x00 6. " READADDROPT     ,AHB Read Address option bit" "0: There is AHB read burst start address alignment limitation when flash is accessed in parallel mode o..,1: There is no AHB read burst start address alignment limitation"
textline "                       "
bitfld.long 0x00 5. " PREFETCHEN      ,AHB Read Prefetch Enable" "0,1"
textline "                       "
bitfld.long 0x00 4. " BUFFERABLEEN    ,Enable AHB bus bufferable write access support" "0: BUFFERABLEEN_0,1: BUFFERABLEEN_1"
textline "                       "
bitfld.long 0x00 3. " CACHABLEEN      ,Enable AHB bus cachable read access support" "0: CACHABLEEN_0,1: CACHABLEEN_1"
textline "                       "
bitfld.long 0x00 0. " APAREN          ,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
group.long 0x10++0x03
line.long 0x00 "INTEN,Interrupt Enable Register"
bitfld.long 0x00 11. " SEQTIMEOUTEN    ,Sequence execution timeout interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 10. " AHBBUSTIMEOUTEN ,AHB Bus timeout interrupt" "0,1"
textline "                       "
bitfld.long 0x00 9. " SCKSTOPBYWREN   ,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 8. " SCKSTOPBYRDEN   ,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 7. " DATALEARNFAILEN ,Data Learning failed interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 6. " IPTXWEEN        ,IP TX FIFO WaterMark empty interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 5. " IPRXWAEN        ,IP RX FIFO WaterMark available interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 4. " AHBCMDERREN     ,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 3. " IPCMDERREN      ,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 2. " AHBCMDGEEN      ,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 1. " IPCMDGEEN       ,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
textline "                       "
bitfld.long 0x00 0. " IPCMDDONEEN     ,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,Interrupt Register"
eventfld.long 0x00 11. " SEQTIMEOUT      ,Sequence execution timeout interrupt" "0,1"
textline "                       "
eventfld.long 0x00 10. " AHBBUSTIMEOUT   ,AHB Bus timeout interrupt" "0,1"
textline "                       "
eventfld.long 0x00 9. " SCKSTOPBYWR     ,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
textline "                       "
eventfld.long 0x00 8. " SCKSTOPBYRD     ,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
textline "                       "
eventfld.long 0x00 7. " DATALEARNFAIL   ,Data Learning failed interrupt" "0,1"
textline "                       "
eventfld.long 0x00 6. " IPTXWE          ,IP TX FIFO watermark empty interrupt" "0,1"
textline "                       "
eventfld.long 0x00 5. " IPRXWA          ,IP RX FIFO watermark available interrupt" "0,1"
textline "                       "
eventfld.long 0x00 4. " AHBCMDERR       ,AHB triggered Command Sequences Error Detected interrupt" "0,1"
textline "                       "
eventfld.long 0x00 3. " IPCMDERR        ,IP triggered Command Sequences Error Detected interrupt" "0,1"
textline "                       "
eventfld.long 0x00 2. " AHBCMDGE        ,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
textline "                       "
eventfld.long 0x00 1. " IPCMDGE         ,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
textline "                       "
eventfld.long 0x00 0. " IPCMDDONE       ,IP triggered Command Sequences Execution finished interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "LUTKEY,LUT Key Register"
hexmask.long 0x00 0.--31. 1. " KEY             ,The Key to lock or unlock LUT"
group.long 0x1C++0x03
line.long 0x00 "LUTCR,LUT Control Register"
bitfld.long 0x00 1. " UNLOCK          ,Unlock LUT" "0,1"
textline "                       "
bitfld.long 0x00 0. " LOCK            ,Lock LUT" "0,1"
group.long 0x20++0x03
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x24++0x03
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x28++0x03
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x2C++0x03
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x30++0x03
line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x34++0x03
line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x38++0x03
line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x3C++0x03
line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
bitfld.long 0x00 31. " PREFETCHEN      ,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
textline "                       "
bitfld.long 0x00 24.--26. " PRIORITY        ,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--19. " MSTRID          ,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " BUFSZ           ,AHB RX Buffer Size in 64 bits"
group.long 0x60++0x03
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ          ,Flash Size in KByte"
group.long 0x64++0x03
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ          ,Flash Size in KByte"
group.long 0x68++0x03
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ          ,Flash Size in KByte"
group.long 0x6C++0x03
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ          ,Flash Size in KByte"
group.long 0x70++0x03
line.long 0x00 "FLSHCR1A1,Flash Control Register 1"
hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL      ,This field is used to set the minimum interval between flash device Chip selection deassertion and f.."
textline "                       "
bitfld.long 0x00 15. " CSINTERVALUNIT  ,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
textline "                       "
bitfld.long 0x00 11.--14. " CAS             ,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 10. " WA              ,Word Addressable" "0,1"
textline "                       "
bitfld.long 0x00 5.--9. " TCSH            ,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 0.--4. " TCSS            ,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x74++0x03
line.long 0x00 "FLSHCR1A2,Flash Control Register 1"
hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL      ,This field is used to set the minimum interval between flash device Chip selection deassertion and f.."
textline "                       "
bitfld.long 0x00 15. " CSINTERVALUNIT  ,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
textline "                       "
bitfld.long 0x00 11.--14. " CAS             ,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 10. " WA              ,Word Addressable" "0,1"
textline "                       "
bitfld.long 0x00 5.--9. " TCSH            ,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 0.--4. " TCSS            ,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x78++0x03
line.long 0x00 "FLSHCR1B1,Flash Control Register 1"
hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL      ,This field is used to set the minimum interval between flash device Chip selection deassertion and f.."
textline "                       "
bitfld.long 0x00 15. " CSINTERVALUNIT  ,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
textline "                       "
bitfld.long 0x00 11.--14. " CAS             ,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 10. " WA              ,Word Addressable" "0,1"
textline "                       "
bitfld.long 0x00 5.--9. " TCSH            ,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 0.--4. " TCSS            ,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C++0x03
line.long 0x00 "FLSHCR1B2,Flash Control Register 1"
hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL      ,This field is used to set the minimum interval between flash device Chip selection deassertion and f.."
textline "                       "
bitfld.long 0x00 15. " CSINTERVALUNIT  ,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
textline "                       "
bitfld.long 0x00 11.--14. " CAS             ,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 10. " WA              ,Word Addressable" "0,1"
textline "                       "
bitfld.long 0x00 5.--9. " TCSH            ,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 0.--4. " TCSS            ,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x03
line.long 0x00 "FLSHCR2A1,Flash Control Register 2"
bitfld.long 0x00 31. " CLRINSTRPTR     ,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
textline "                       "
bitfld.long 0x00 28.--30. " AWRWAITUNIT     ,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
textline "                       "
hexmask.long.word 0x00 16.--27. 1. " AWRWAIT         ,For certain devices (such as FPGA). it need some time to write data into internal memory after the c.."
textline "                       "
bitfld.long 0x00 13.--15. " AWRSEQNUM       ,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 8.--12. " AWRSEQID        ,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 5.--7. " ARDSEQNUM       ,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 0.--4. " ARDSEQID        ,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "FLSHCR2A2,Flash Control Register 2"
bitfld.long 0x00 31. " CLRINSTRPTR     ,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
textline "                       "
bitfld.long 0x00 28.--30. " AWRWAITUNIT     ,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
textline "                       "
hexmask.long.word 0x00 16.--27. 1. " AWRWAIT         ,For certain devices (such as FPGA). it need some time to write data into internal memory after the c.."
textline "                       "
bitfld.long 0x00 13.--15. " AWRSEQNUM       ,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 8.--12. " AWRSEQID        ,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 5.--7. " ARDSEQNUM       ,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 0.--4. " ARDSEQID        ,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x88++0x03
line.long 0x00 "FLSHCR2B1,Flash Control Register 2"
bitfld.long 0x00 31. " CLRINSTRPTR     ,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
textline "                       "
bitfld.long 0x00 28.--30. " AWRWAITUNIT     ,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
textline "                       "
hexmask.long.word 0x00 16.--27. 1. " AWRWAIT         ,For certain devices (such as FPGA). it need some time to write data into internal memory after the c.."
textline "                       "
bitfld.long 0x00 13.--15. " AWRSEQNUM       ,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 8.--12. " AWRSEQID        ,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 5.--7. " ARDSEQNUM       ,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 0.--4. " ARDSEQID        ,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "FLSHCR2B2,Flash Control Register 2"
bitfld.long 0x00 31. " CLRINSTRPTR     ,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
textline "                       "
bitfld.long 0x00 28.--30. " AWRWAITUNIT     ,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
textline "                       "
hexmask.long.word 0x00 16.--27. 1. " AWRWAIT         ,For certain devices (such as FPGA). it need some time to write data into internal memory after the c.."
textline "                       "
bitfld.long 0x00 13.--15. " AWRSEQNUM       ,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 8.--12. " AWRSEQID        ,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 5.--7. " ARDSEQNUM       ,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 0.--4. " ARDSEQID        ,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x94++0x03
line.long 0x00 "FLSHCR4,Flash Control Register 4"
bitfld.long 0x00 3. " WMENB           ,Write mask enable bit for flash device on port B" "0: Write mask is disabled. DQS(RWDS) pin will be un-driven when writing to external device,1: Write mask is enabled. DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to .."
textline "                       "
bitfld.long 0x00 2. " WMENA           ,Write mask enable bit for flash device on port A" "0: Write mask is disabled. DQS(RWDS) pin will be un-driven when writing to external device,1: Write mask is enabled. DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to .."
textline "                       "
bitfld.long 0x00 0. " WMOPT1          ,Write mask option bit 1" "0: DQS pin will be used as Write Mask when writing to external device,1: DQS pin will not be used as Write Mask when writing to external device"
group.long 0xA0++0x03
line.long 0x00 "IPCR0,IP Control Register 0"
hexmask.long 0x00 0.--31. 1. " SFAR            ,Serial Flash Address for IP command"
group.long 0xA4++0x03
line.long 0x00 "IPCR1,IP Control Register 1"
bitfld.long 0x00 31. " IPAREN          ,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
textline "                       "
bitfld.long 0x00 24.--26. " ISEQNUM         ,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 16.--20. " ISEQID          ,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " IDATSZ          ,Flash Read/Program Data Size (in Bytes) for IP command"
group.long 0xB0++0x03
line.long 0x00 "IPCMD,IP Command Register"
bitfld.long 0x00 0. " TRG             ,Setting this bit will trigger an IP Command" "0,1"
group.long 0xB4++0x03
line.long 0x00 "DLPR,Data Learn Pattern Register"
hexmask.long 0x00 0.--31. 1. " DLP             ,Data Learning Pattern"
group.long 0xB8++0x03
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
bitfld.long 0x00 2.--7. " RXWMRK          ,Watermark level is (RXWMRK+1)*64 Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 1. " RXDMAEN         ,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
textline "                       "
bitfld.long 0x00 0. " CLRIPRXF        ,Clear all valid data entries in IP RX FIFO" "0,1"
group.long 0xBC++0x03
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. " TXWMRK          ,Watermark level is (TXWMRK+1)*64 Bits"
textline "                       "
bitfld.long 0x00 1. " TXDMAEN         ,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
textline "                       "
bitfld.long 0x00 0. " CLRIPTXF        ,Clear all valid data entries in IP TX FIFO" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DLLCRA,DLL Control Register 0"
bitfld.long 0x00 9.--14. " OVRDVAL         ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8. " OVRDEN          ,Slave clock delay line delay cell number selection override enable" "0,1"
textline "                       "
bitfld.long 0x00 3.--6. " SLVDLYTARGET    ,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " DLLRESET        ,Software could force a reset on DLL by setting this field to 0x1" "0,1"
textline "                       "
bitfld.long 0x00 0. " DLLEN           ,DLL calibration enable" "0,1"
group.long 0xC4++0x03
line.long 0x00 "DLLCRB,DLL Control Register 0"
bitfld.long 0x00 9.--14. " OVRDVAL         ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8. " OVRDEN          ,Slave clock delay line delay cell number selection override enable" "0,1"
textline "                       "
bitfld.long 0x00 3.--6. " SLVDLYTARGET    ,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " DLLRESET        ,Software could force a reset on DLL by setting this field to 0x1" "0,1"
textline "                       "
bitfld.long 0x00 0. " DLLEN           ,DLL calibration enable" "0,1"
rgroup.long 0xE0++0x03
line.long 0x00 "STS0,Status Register 0"
bitfld.long 0x00 8.--11. " DATALEARNPHASEB ,Indicate the sampling clock phase selection on Port B after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " DATALEARNPHASEA ,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 2.--3. " ARBCMDSRC       ,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by AHB read),1: Triggered by AHB write command (triggered by AHB Write),2: Triggered by IP command (triggered by setting register bit IPCMD,3: Triggered by suspended command (resumed)"
textline "                       "
bitfld.long 0x00 1. " ARBIDLE         ,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted.." "0,1"
textline "                       "
bitfld.long 0x00 0. " SEQIDLE         ,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executi.." "0,1"
rgroup.long 0xE4++0x03
line.long 0x00 "STS1,Status Register 1"
bitfld.long 0x00 24.--27. " IPCMDERRCODE    ,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,,2: IP command with JMP_ON_CS instruction used in the sequence,3: There is unknown instruction opcode in the sequence,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence,6: Flash access start address exceed the whole flash address range (A1/A2/B1/B2),,,,,,,,14: Sequence execution timeout,15: Flash boundary crossed"
textline "                       "
bitfld.long 0x00 16.--20. " IPCMDERRID      ,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
bitfld.long 0x00 8.--11. " AHBCMDERRCODE   ,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,,2: AHB Write command with JMP_ON_CS instruction used in the sequence,3: There is unknown instruction opcode in the sequence,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence,,,,,,,,,14: Sequence execution timeout,"
textline "                       "
bitfld.long 0x00 0.--4. " AHBCMDERRID     ,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xE8++0x03
line.long 0x00 "STS2,Status Register 2"
bitfld.long 0x00 24.--29. " BREFSEL         ,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 18.--23. " BSLVSEL         ,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 17. " BREFLOCK        ,Flash B sample clock reference delay line locked" "0,1"
textline "                       "
bitfld.long 0x00 16. " BSLVLOCK        ,Flash B sample clock slave delay line locked" "0,1"
textline "                       "
bitfld.long 0x00 8.--13. " AREFSEL         ,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 2.--7. " ASLVSEL         ,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 1. " AREFLOCK        ,Flash A sample clock reference delay line locked" "0,1"
textline "                       "
bitfld.long 0x00 0. " ASLVLOCK        ,Flash A sample clock slave delay line locked" "0,1"
rgroup.long 0xEC++0x03
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
hexmask.long.word 0x00 16.--31. 1. " DATLFT          ,Left Data size for suspended command sequence (in byte)"
textline "                       "
bitfld.long 0x00 1.--3. " BUFID           ,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
textline "                       "
bitfld.long 0x00 0. " ACTIVE          ,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. " RDCNTR          ,Total Read Data Counter: RDCNTR * 64 Bits"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " FILL            ,Fill level of IP RX FIFO"
rgroup.long 0xF4++0x03
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. " WRCNTR          ,Total Write Data Counter: WRCNTR * 64 Bits"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " FILL            ,Fill level of IP TX FIFO"
rgroup.long 0x100++0x03
line.long 0x00 "RFDR[0],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x104++0x03
line.long 0x00 "RFDR[1],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x108++0x03
line.long 0x00 "RFDR[2],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x10C++0x03
line.long 0x00 "RFDR[3],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x110++0x03
line.long 0x00 "RFDR[4],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x114++0x03
line.long 0x00 "RFDR[5],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x118++0x03
line.long 0x00 "RFDR[6],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x11C++0x03
line.long 0x00 "RFDR[7],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x120++0x03
line.long 0x00 "RFDR[8],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x124++0x03
line.long 0x00 "RFDR[9],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x128++0x03
line.long 0x00 "RFDR[10],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x12C++0x03
line.long 0x00 "RFDR[11],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x130++0x03
line.long 0x00 "RFDR[12],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x134++0x03
line.long 0x00 "RFDR[13],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x138++0x03
line.long 0x00 "RFDR[14],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x13C++0x03
line.long 0x00 "RFDR[15],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x140++0x03
line.long 0x00 "RFDR[16],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x144++0x03
line.long 0x00 "RFDR[17],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x148++0x03
line.long 0x00 "RFDR[18],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x14C++0x03
line.long 0x00 "RFDR[19],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x150++0x03
line.long 0x00 "RFDR[20],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x154++0x03
line.long 0x00 "RFDR[21],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x158++0x03
line.long 0x00 "RFDR[22],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x15C++0x03
line.long 0x00 "RFDR[23],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x160++0x03
line.long 0x00 "RFDR[24],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x164++0x03
line.long 0x00 "RFDR[25],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x168++0x03
line.long 0x00 "RFDR[26],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x16C++0x03
line.long 0x00 "RFDR[27],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x170++0x03
line.long 0x00 "RFDR[28],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x174++0x03
line.long 0x00 "RFDR[29],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x178++0x03
line.long 0x00 "RFDR[30],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
rgroup.long 0x17C++0x03
line.long 0x00 "RFDR[31],IP RX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " RXDATA          ,RX Data"
wgroup.long 0x180++0x03
line.long 0x00 "TFDR[0],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x184++0x03
line.long 0x00 "TFDR[1],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x188++0x03
line.long 0x00 "TFDR[2],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x18C++0x03
line.long 0x00 "TFDR[3],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x190++0x03
line.long 0x00 "TFDR[4],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x194++0x03
line.long 0x00 "TFDR[5],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x198++0x03
line.long 0x00 "TFDR[6],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x19C++0x03
line.long 0x00 "TFDR[7],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1A0++0x03
line.long 0x00 "TFDR[8],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1A4++0x03
line.long 0x00 "TFDR[9],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1A8++0x03
line.long 0x00 "TFDR[10],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1AC++0x03
line.long 0x00 "TFDR[11],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1B0++0x03
line.long 0x00 "TFDR[12],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1B4++0x03
line.long 0x00 "TFDR[13],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1B8++0x03
line.long 0x00 "TFDR[14],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1BC++0x03
line.long 0x00 "TFDR[15],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1C0++0x03
line.long 0x00 "TFDR[16],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1C4++0x03
line.long 0x00 "TFDR[17],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1C8++0x03
line.long 0x00 "TFDR[18],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1CC++0x03
line.long 0x00 "TFDR[19],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1D0++0x03
line.long 0x00 "TFDR[20],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1D4++0x03
line.long 0x00 "TFDR[21],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1D8++0x03
line.long 0x00 "TFDR[22],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1DC++0x03
line.long 0x00 "TFDR[23],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1E0++0x03
line.long 0x00 "TFDR[24],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1E4++0x03
line.long 0x00 "TFDR[25],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1E8++0x03
line.long 0x00 "TFDR[26],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1EC++0x03
line.long 0x00 "TFDR[27],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1F0++0x03
line.long 0x00 "TFDR[28],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1F4++0x03
line.long 0x00 "TFDR[29],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1F8++0x03
line.long 0x00 "TFDR[30],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
wgroup.long 0x1FC++0x03
line.long 0x00 "TFDR[31],IP TX FIFO Data Register 0"
hexmask.long 0x00 0.--31. 1. " TXDATA          ,TX Data"
group.long 0x200++0x03
line.long 0x00 "LUT[0],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x204++0x03
line.long 0x00 "LUT[1],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x208++0x03
line.long 0x00 "LUT[2],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x20C++0x03
line.long 0x00 "LUT[3],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x210++0x03
line.long 0x00 "LUT[4],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x214++0x03
line.long 0x00 "LUT[5],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x218++0x03
line.long 0x00 "LUT[6],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x21C++0x03
line.long 0x00 "LUT[7],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x220++0x03
line.long 0x00 "LUT[8],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x224++0x03
line.long 0x00 "LUT[9],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x228++0x03
line.long 0x00 "LUT[10],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x22C++0x03
line.long 0x00 "LUT[11],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x230++0x03
line.long 0x00 "LUT[12],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x234++0x03
line.long 0x00 "LUT[13],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x238++0x03
line.long 0x00 "LUT[14],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x23C++0x03
line.long 0x00 "LUT[15],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x240++0x03
line.long 0x00 "LUT[16],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x244++0x03
line.long 0x00 "LUT[17],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x248++0x03
line.long 0x00 "LUT[18],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x24C++0x03
line.long 0x00 "LUT[19],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x250++0x03
line.long 0x00 "LUT[20],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x254++0x03
line.long 0x00 "LUT[21],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x258++0x03
line.long 0x00 "LUT[22],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x25C++0x03
line.long 0x00 "LUT[23],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x260++0x03
line.long 0x00 "LUT[24],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x264++0x03
line.long 0x00 "LUT[25],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x268++0x03
line.long 0x00 "LUT[26],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x26C++0x03
line.long 0x00 "LUT[27],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x270++0x03
line.long 0x00 "LUT[28],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x274++0x03
line.long 0x00 "LUT[29],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x278++0x03
line.long 0x00 "LUT[30],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x27C++0x03
line.long 0x00 "LUT[31],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x280++0x03
line.long 0x00 "LUT[32],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x284++0x03
line.long 0x00 "LUT[33],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x288++0x03
line.long 0x00 "LUT[34],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x28C++0x03
line.long 0x00 "LUT[35],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x290++0x03
line.long 0x00 "LUT[36],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x294++0x03
line.long 0x00 "LUT[37],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x298++0x03
line.long 0x00 "LUT[38],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x29C++0x03
line.long 0x00 "LUT[39],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2A0++0x03
line.long 0x00 "LUT[40],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2A4++0x03
line.long 0x00 "LUT[41],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2A8++0x03
line.long 0x00 "LUT[42],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2AC++0x03
line.long 0x00 "LUT[43],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2B0++0x03
line.long 0x00 "LUT[44],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2B4++0x03
line.long 0x00 "LUT[45],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2B8++0x03
line.long 0x00 "LUT[46],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2BC++0x03
line.long 0x00 "LUT[47],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2C0++0x03
line.long 0x00 "LUT[48],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2C4++0x03
line.long 0x00 "LUT[49],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2C8++0x03
line.long 0x00 "LUT[50],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2CC++0x03
line.long 0x00 "LUT[51],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2D0++0x03
line.long 0x00 "LUT[52],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2D4++0x03
line.long 0x00 "LUT[53],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2D8++0x03
line.long 0x00 "LUT[54],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2DC++0x03
line.long 0x00 "LUT[55],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2E0++0x03
line.long 0x00 "LUT[56],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2E4++0x03
line.long 0x00 "LUT[57],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2E8++0x03
line.long 0x00 "LUT[58],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2EC++0x03
line.long 0x00 "LUT[59],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2F0++0x03
line.long 0x00 "LUT[60],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2F4++0x03
line.long 0x00 "LUT[61],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2F8++0x03
line.long 0x00 "LUT[62],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x2FC++0x03
line.long 0x00 "LUT[63],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x300++0x03
line.long 0x00 "LUT[64],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x304++0x03
line.long 0x00 "LUT[65],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x308++0x03
line.long 0x00 "LUT[66],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x30C++0x03
line.long 0x00 "LUT[67],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x310++0x03
line.long 0x00 "LUT[68],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x314++0x03
line.long 0x00 "LUT[69],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x318++0x03
line.long 0x00 "LUT[70],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x31C++0x03
line.long 0x00 "LUT[71],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x320++0x03
line.long 0x00 "LUT[72],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x324++0x03
line.long 0x00 "LUT[73],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x328++0x03
line.long 0x00 "LUT[74],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x32C++0x03
line.long 0x00 "LUT[75],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x330++0x03
line.long 0x00 "LUT[76],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x334++0x03
line.long 0x00 "LUT[77],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x338++0x03
line.long 0x00 "LUT[78],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x33C++0x03
line.long 0x00 "LUT[79],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x340++0x03
line.long 0x00 "LUT[80],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x344++0x03
line.long 0x00 "LUT[81],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x348++0x03
line.long 0x00 "LUT[82],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x34C++0x03
line.long 0x00 "LUT[83],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x350++0x03
line.long 0x00 "LUT[84],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x354++0x03
line.long 0x00 "LUT[85],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x358++0x03
line.long 0x00 "LUT[86],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x35C++0x03
line.long 0x00 "LUT[87],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x360++0x03
line.long 0x00 "LUT[88],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x364++0x03
line.long 0x00 "LUT[89],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x368++0x03
line.long 0x00 "LUT[90],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x36C++0x03
line.long 0x00 "LUT[91],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x370++0x03
line.long 0x00 "LUT[92],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x374++0x03
line.long 0x00 "LUT[93],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x378++0x03
line.long 0x00 "LUT[94],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x37C++0x03
line.long 0x00 "LUT[95],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x380++0x03
line.long 0x00 "LUT[96],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x384++0x03
line.long 0x00 "LUT[97],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x388++0x03
line.long 0x00 "LUT[98],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x38C++0x03
line.long 0x00 "LUT[99],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x390++0x03
line.long 0x00 "LUT[100],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x394++0x03
line.long 0x00 "LUT[101],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x398++0x03
line.long 0x00 "LUT[102],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x39C++0x03
line.long 0x00 "LUT[103],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3A0++0x03
line.long 0x00 "LUT[104],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3A4++0x03
line.long 0x00 "LUT[105],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3A8++0x03
line.long 0x00 "LUT[106],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3AC++0x03
line.long 0x00 "LUT[107],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3B0++0x03
line.long 0x00 "LUT[108],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3B4++0x03
line.long 0x00 "LUT[109],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3B8++0x03
line.long 0x00 "LUT[110],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3BC++0x03
line.long 0x00 "LUT[111],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3C0++0x03
line.long 0x00 "LUT[112],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3C4++0x03
line.long 0x00 "LUT[113],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3C8++0x03
line.long 0x00 "LUT[114],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3CC++0x03
line.long 0x00 "LUT[115],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3D0++0x03
line.long 0x00 "LUT[116],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3D4++0x03
line.long 0x00 "LUT[117],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3D8++0x03
line.long 0x00 "LUT[118],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3DC++0x03
line.long 0x00 "LUT[119],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3E0++0x03
line.long 0x00 "LUT[120],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3E4++0x03
line.long 0x00 "LUT[121],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3E8++0x03
line.long 0x00 "LUT[122],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3EC++0x03
line.long 0x00 "LUT[123],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3F0++0x03
line.long 0x00 "LUT[124],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3F4++0x03
line.long 0x00 "LUT[125],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3F8++0x03
line.long 0x00 "LUT[126],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
group.long 0x3FC++0x03
line.long 0x00 "LUT[127],LUT 0"
bitfld.long 0x00 26.--31. " OPCODE1         ,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 24.--25. " NUM_PADS1       ,NUM_PADS1" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " OPERAND1        ,OPERAND1"
textline "                       "
bitfld.long 0x00 10.--15. " OPCODE0         ,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                       "
bitfld.long 0x00 8.--9. " NUM_PADS0       ,NUM_PADS0" "0,1,2,3"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " OPERAND0        ,OPERAND0"
width 0x0B
tree.end
tree "FREQME"
base ad:0x4002F000
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "FREQMECTRL_R,Frequency Measurement (in Read mode)"
bitfld.long 0x00 31. " MEASURE_IN_PROGRESS ,Measure in Progress" "0: Process complete,1: IN_PROGRESS"
textline "                       "
hexmask.long 0x00 0.--30. 1. " RESULT              ,Result"
wgroup.long 0x00++0x03
line.long 0x00 "FREQMECTRL_W,Freqeuncy Measurement (in Write mode)"
bitfld.long 0x00 31. " MEASURE_IN_PROGRESS ,Measure in Progress" "0: FORCE_TERMINATE,1: Initiates Measurement Cycle"
textline "                       "
bitfld.long 0x00 9. " PULSE_POL           ,Pulse Polarity" "0: HIGH_PERIOD,1: LOW_PERIOD"
textline "                       "
bitfld.long 0x00 8. " PULSE_MODE          ,Pulse Width Measurement mode select" "0: Frequency Measurement Mode,1: Pulse Width Measurement mode"
textline "                       "
bitfld.long 0x00 0.--4. " REF_SCALE           ,Reference Clock Scaling Factor" "0: Count cycle = 2^0 = 1,1: Count cycle = 2^1 = 2,2: Count cycle = 2^4 = 4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,31: Count cycle = 2^31 = 2.147.483.648"
width 0x0B
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
tree "GPIO"
base ad:0x40100000
width 13.
group.long 0x2000++0x03
line.long 0x00 "DIR[0],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2004++0x03
line.long 0x00 "DIR[1],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2008++0x03
line.long 0x00 "DIR[2],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x200C++0x03
line.long 0x00 "DIR[3],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2010++0x03
line.long 0x00 "DIR[4],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2014++0x03
line.long 0x00 "DIR[5],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2018++0x03
line.long 0x00 "DIR[6],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x201C++0x03
line.long 0x00 "DIR[7],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2080++0x03
line.long 0x00 "MASK[0],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2084++0x03
line.long 0x00 "MASK[1],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2088++0x03
line.long 0x00 "MASK[2],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x208C++0x03
line.long 0x00 "MASK[3],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2090++0x03
line.long 0x00 "MASK[4],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2094++0x03
line.long 0x00 "MASK[5],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2098++0x03
line.long 0x00 "MASK[6],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x209C++0x03
line.long 0x00 "MASK[7],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2100++0x03
line.long 0x00 "PIN[0],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2104++0x03
line.long 0x00 "PIN[1],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2108++0x03
line.long 0x00 "PIN[2],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x210C++0x03
line.long 0x00 "PIN[3],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2110++0x03
line.long 0x00 "PIN[4],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2114++0x03
line.long 0x00 "PIN[5],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2118++0x03
line.long 0x00 "PIN[6],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x211C++0x03
line.long 0x00 "PIN[7],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2180++0x03
line.long 0x00 "MPIN[0],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2184++0x03
line.long 0x00 "MPIN[1],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2188++0x03
line.long 0x00 "MPIN[2],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x218C++0x03
line.long 0x00 "MPIN[3],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2190++0x03
line.long 0x00 "MPIN[4],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2194++0x03
line.long 0x00 "MPIN[5],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2198++0x03
line.long 0x00 "MPIN[6],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x219C++0x03
line.long 0x00 "MPIN[7],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2200++0x03
line.long 0x00 "SET[0],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2204++0x03
line.long 0x00 "SET[1],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2208++0x03
line.long 0x00 "SET[2],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x220C++0x03
line.long 0x00 "SET[3],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2210++0x03
line.long 0x00 "SET[4],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2214++0x03
line.long 0x00 "SET[5],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2218++0x03
line.long 0x00 "SET[6],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x221C++0x03
line.long 0x00 "SET[7],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2280++0x03
line.long 0x00 "CLR[0],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2284++0x03
line.long 0x00 "CLR[1],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2288++0x03
line.long 0x00 "CLR[2],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x228C++0x03
line.long 0x00 "CLR[3],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2290++0x03
line.long 0x00 "CLR[4],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2294++0x03
line.long 0x00 "CLR[5],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2298++0x03
line.long 0x00 "CLR[6],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x229C++0x03
line.long 0x00 "CLR[7],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2300++0x03
line.long 0x00 "NOT[0],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2304++0x03
line.long 0x00 "NOT[1],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2308++0x03
line.long 0x00 "NOT[2],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x230C++0x03
line.long 0x00 "NOT[3],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2310++0x03
line.long 0x00 "NOT[4],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2314++0x03
line.long 0x00 "NOT[5],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2318++0x03
line.long 0x00 "NOT[6],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x231C++0x03
line.long 0x00 "NOT[7],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2380++0x03
line.long 0x00 "DIRSET[0],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2384++0x03
line.long 0x00 "DIRSET[1],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2388++0x03
line.long 0x00 "DIRSET[2],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x238C++0x03
line.long 0x00 "DIRSET[3],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2390++0x03
line.long 0x00 "DIRSET[4],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2394++0x03
line.long 0x00 "DIRSET[5],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2398++0x03
line.long 0x00 "DIRSET[6],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x239C++0x03
line.long 0x00 "DIRSET[7],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2400++0x03
line.long 0x00 "DIRCLR[0],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2404++0x03
line.long 0x00 "DIRCLR[1],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2408++0x03
line.long 0x00 "DIRCLR[2],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x240C++0x03
line.long 0x00 "DIRCLR[3],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2410++0x03
line.long 0x00 "DIRCLR[4],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2414++0x03
line.long 0x00 "DIRCLR[5],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2418++0x03
line.long 0x00 "DIRCLR[6],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x241C++0x03
line.long 0x00 "DIRCLR[7],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2480++0x03
line.long 0x00 "DIRNOT[0],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2484++0x03
line.long 0x00 "DIRNOT[1],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2488++0x03
line.long 0x00 "DIRNOT[2],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x248C++0x03
line.long 0x00 "DIRNOT[3],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2490++0x03
line.long 0x00 "DIRNOT[4],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2494++0x03
line.long 0x00 "DIRNOT[5],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2498++0x03
line.long 0x00 "DIRNOT[6],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x249C++0x03
line.long 0x00 "DIRNOT[7],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2500++0x03
line.long 0x00 "INTENA[0],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2504++0x03
line.long 0x00 "INTENA[1],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2508++0x03
line.long 0x00 "INTENA[2],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x250C++0x03
line.long 0x00 "INTENA[3],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2510++0x03
line.long 0x00 "INTENA[4],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2514++0x03
line.long 0x00 "INTENA[5],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2518++0x03
line.long 0x00 "INTENA[6],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x251C++0x03
line.long 0x00 "INTENA[7],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2580++0x03
line.long 0x00 "INTENB[0],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2584++0x03
line.long 0x00 "INTENB[1],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2588++0x03
line.long 0x00 "INTENB[2],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x258C++0x03
line.long 0x00 "INTENB[3],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2590++0x03
line.long 0x00 "INTENB[4],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2594++0x03
line.long 0x00 "INTENB[5],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2598++0x03
line.long 0x00 "INTENB[6],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x259C++0x03
line.long 0x00 "INTENB[7],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2600++0x03
line.long 0x00 "INTPOL[0],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2604++0x03
line.long 0x00 "INTPOL[1],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2608++0x03
line.long 0x00 "INTPOL[2],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x260C++0x03
line.long 0x00 "INTPOL[3],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2610++0x03
line.long 0x00 "INTPOL[4],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2614++0x03
line.long 0x00 "INTPOL[5],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2618++0x03
line.long 0x00 "INTPOL[6],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x261C++0x03
line.long 0x00 "INTPOL[7],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2680++0x03
line.long 0x00 "INTEDG[0],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2684++0x03
line.long 0x00 "INTEDG[1],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2688++0x03
line.long 0x00 "INTEDG[2],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x268C++0x03
line.long 0x00 "INTEDG[3],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2690++0x03
line.long 0x00 "INTEDG[4],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2694++0x03
line.long 0x00 "INTEDG[5],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2698++0x03
line.long 0x00 "INTEDG[6],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x269C++0x03
line.long 0x00 "INTEDG[7],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2700++0x03
line.long 0x00 "INTSTATA[0],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2704++0x03
line.long 0x00 "INTSTATA[1],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2708++0x03
line.long 0x00 "INTSTATA[2],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x270C++0x03
line.long 0x00 "INTSTATA[3],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2710++0x03
line.long 0x00 "INTSTATA[4],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2714++0x03
line.long 0x00 "INTSTATA[5],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2718++0x03
line.long 0x00 "INTSTATA[6],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x271C++0x03
line.long 0x00 "INTSTATA[7],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2780++0x03
line.long 0x00 "INTSTATB[0],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2784++0x03
line.long 0x00 "INTSTATB[1],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2788++0x03
line.long 0x00 "INTSTATB[2],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x278C++0x03
line.long 0x00 "INTSTATB[3],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2790++0x03
line.long 0x00 "INTSTATB[4],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2794++0x03
line.long 0x00 "INTSTATB[5],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2798++0x03
line.long 0x00 "INTSTATB[6],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x279C++0x03
line.long 0x00 "INTSTATB[7],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
tree "B[0]"
width 8.
group.byte 0x00++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x01++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x02++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x03++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x04++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x05++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x06++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x07++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x08++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x09++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x10++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x11++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x12++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x13++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x14++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x15++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x16++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x17++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x18++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x19++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[1]"
width 8.
group.byte 0x20++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x21++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x22++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x23++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x24++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x25++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x26++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x27++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x28++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x29++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x30++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x31++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x32++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x33++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x34++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x35++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x36++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x37++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x38++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x39++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[2]"
width 8.
group.byte 0x40++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x41++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x42++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x43++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x44++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x45++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x46++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x47++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x48++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x49++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x50++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x51++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x52++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x53++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x54++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x55++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x56++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x57++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x58++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x59++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[3]"
width 8.
group.byte 0x60++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x61++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x62++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x63++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x64++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x65++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x66++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x67++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x68++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x69++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x70++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x71++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x72++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x73++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x74++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x75++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x76++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x77++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x78++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x79++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[4]"
width 8.
group.byte 0x80++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x81++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x82++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x83++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x84++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x85++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x86++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x87++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x88++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x89++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x90++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x91++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x92++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x93++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x94++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x95++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x96++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x97++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x98++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x99++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[5]"
width 8.
group.byte 0xA0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAD++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[6]"
width 8.
group.byte 0xC0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCD++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[7]"
width 8.
group.byte 0xE0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xED++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "W[0]"
width 8.
group.long 0x1000++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1004++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1008++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x100C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1010++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1014++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1018++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x101C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1020++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1024++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1028++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x102C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1030++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1034++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1038++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x103C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1040++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1044++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1048++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x104C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1050++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1054++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1058++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x105C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1060++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1064++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1068++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x106C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1070++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1074++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1078++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x107C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[1]"
width 8.
group.long 0x1080++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1084++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1088++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x108C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1090++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1094++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1098++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x109C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[2]"
width 8.
group.long 0x1100++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1104++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1108++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x110C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1110++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1114++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1118++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x111C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1120++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1124++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1128++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x112C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1130++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1134++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1138++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x113C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1140++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1144++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1148++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x114C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1150++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1154++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1158++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x115C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1160++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1164++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1168++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x116C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1170++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1174++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1178++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x117C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[3]"
width 8.
group.long 0x1180++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1184++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1188++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x118C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1190++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1194++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1198++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x119C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[4]"
width 8.
group.long 0x1200++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1204++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1208++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x120C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1210++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1214++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1218++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x121C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1220++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1224++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1228++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x122C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1230++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1234++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1238++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x123C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1240++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1244++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1248++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x124C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1250++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1254++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1258++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x125C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1260++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1264++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1268++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x126C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1270++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1274++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1278++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x127C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[5]"
width 8.
group.long 0x1280++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1284++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1288++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x128C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1290++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1294++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1298++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x129C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[6]"
width 8.
group.long 0x1300++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1304++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1308++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x130C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1310++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1314++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1318++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x131C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1320++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1324++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1328++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x132C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1330++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1334++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1338++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x133C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1340++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1344++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1348++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x134C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1350++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1354++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1358++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x135C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1360++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1364++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1368++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x136C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1370++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1374++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1378++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x137C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[7]"
width 8.
group.long 0x1380++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1384++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1388++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x138C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1390++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1394++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1398++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x139C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
width 0x0B
tree.end
tree "SECGPIO"
base ad:0x40154000
width 13.
group.long 0x2000++0x03
line.long 0x00 "DIR[0],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2004++0x03
line.long 0x00 "DIR[1],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2008++0x03
line.long 0x00 "DIR[2],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x200C++0x03
line.long 0x00 "DIR[3],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2010++0x03
line.long 0x00 "DIR[4],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2014++0x03
line.long 0x00 "DIR[5],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2018++0x03
line.long 0x00 "DIR[6],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x201C++0x03
line.long 0x00 "DIR[7],Direction registers"
hexmask.long 0x00 0.--31. 1. " DIRP    ,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2080++0x03
line.long 0x00 "MASK[0],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2084++0x03
line.long 0x00 "MASK[1],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2088++0x03
line.long 0x00 "MASK[2],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x208C++0x03
line.long 0x00 "MASK[3],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2090++0x03
line.long 0x00 "MASK[4],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2094++0x03
line.long 0x00 "MASK[5],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2098++0x03
line.long 0x00 "MASK[6],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x209C++0x03
line.long 0x00 "MASK[7],Mask register"
hexmask.long 0x00 0.--31. 1. " MASKP   ,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0. bit 1 .."
group.long 0x2100++0x03
line.long 0x00 "PIN[0],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2104++0x03
line.long 0x00 "PIN[1],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2108++0x03
line.long 0x00 "PIN[2],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x210C++0x03
line.long 0x00 "PIN[3],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2110++0x03
line.long 0x00 "PIN[4],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2114++0x03
line.long 0x00 "PIN[5],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2118++0x03
line.long 0x00 "PIN[6],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x211C++0x03
line.long 0x00 "PIN[7],Port pin register"
hexmask.long 0x00 0.--31. 1. " PORT    ,Reads pin states or loads output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2180++0x03
line.long 0x00 "MPIN[0],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2184++0x03
line.long 0x00 "MPIN[1],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2188++0x03
line.long 0x00 "MPIN[2],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x218C++0x03
line.long 0x00 "MPIN[3],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2190++0x03
line.long 0x00 "MPIN[4],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2194++0x03
line.long 0x00 "MPIN[5],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2198++0x03
line.long 0x00 "MPIN[6],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x219C++0x03
line.long 0x00 "MPIN[7],Masked port register"
hexmask.long 0x00 0.--31. 1. " MPORTP  ,Masked port register (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2200++0x03
line.long 0x00 "SET[0],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2204++0x03
line.long 0x00 "SET[1],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2208++0x03
line.long 0x00 "SET[2],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x220C++0x03
line.long 0x00 "SET[3],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2210++0x03
line.long 0x00 "SET[4],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2214++0x03
line.long 0x00 "SET[5],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2218++0x03
line.long 0x00 "SET[6],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x221C++0x03
line.long 0x00 "SET[7],Write: Set register for port Read: output bits for port"
hexmask.long 0x00 0.--31. 1. " SETP    ,Read or set output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2280++0x03
line.long 0x00 "CLR[0],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2284++0x03
line.long 0x00 "CLR[1],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2288++0x03
line.long 0x00 "CLR[2],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x228C++0x03
line.long 0x00 "CLR[3],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2290++0x03
line.long 0x00 "CLR[4],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2294++0x03
line.long 0x00 "CLR[5],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2298++0x03
line.long 0x00 "CLR[6],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x229C++0x03
line.long 0x00 "CLR[7],Clear port"
hexmask.long 0x00 0.--31. 1. " CLRP    ,Clear output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2300++0x03
line.long 0x00 "NOT[0],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2304++0x03
line.long 0x00 "NOT[1],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2308++0x03
line.long 0x00 "NOT[2],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x230C++0x03
line.long 0x00 "NOT[3],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2310++0x03
line.long 0x00 "NOT[4],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2314++0x03
line.long 0x00 "NOT[5],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2318++0x03
line.long 0x00 "NOT[6],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x231C++0x03
line.long 0x00 "NOT[7],Toggle port"
hexmask.long 0x00 0.--31. 1. " NOTP    ,Toggle output bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2380++0x03
line.long 0x00 "DIRSET[0],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2384++0x03
line.long 0x00 "DIRSET[1],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2388++0x03
line.long 0x00 "DIRSET[2],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x238C++0x03
line.long 0x00 "DIRSET[3],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2390++0x03
line.long 0x00 "DIRSET[4],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2394++0x03
line.long 0x00 "DIRSET[5],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2398++0x03
line.long 0x00 "DIRSET[6],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x239C++0x03
line.long 0x00 "DIRSET[7],Set pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRSETP ,Set direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2400++0x03
line.long 0x00 "DIRCLR[0],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2404++0x03
line.long 0x00 "DIRCLR[1],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2408++0x03
line.long 0x00 "DIRCLR[2],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x240C++0x03
line.long 0x00 "DIRCLR[3],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2410++0x03
line.long 0x00 "DIRCLR[4],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2414++0x03
line.long 0x00 "DIRCLR[5],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2418++0x03
line.long 0x00 "DIRCLR[6],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x241C++0x03
line.long 0x00 "DIRCLR[7],Clear pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRCLRP ,Clear direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2480++0x03
line.long 0x00 "DIRNOT[0],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2484++0x03
line.long 0x00 "DIRNOT[1],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2488++0x03
line.long 0x00 "DIRNOT[2],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x248C++0x03
line.long 0x00 "DIRNOT[3],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2490++0x03
line.long 0x00 "DIRNOT[4],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2494++0x03
line.long 0x00 "DIRNOT[5],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x2498++0x03
line.long 0x00 "DIRNOT[6],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
wgroup.long 0x249C++0x03
line.long 0x00 "DIRNOT[7],Toggle pin direction bits for port"
hexmask.long 0x00 0.--31. 1. " DIRNOTP ,Toggle direction bits (bit 0 = PIOn_0. bit 1 = PIOn_1. etc"
group.long 0x2500++0x03
line.long 0x00 "INTENA[0],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2504++0x03
line.long 0x00 "INTENA[1],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2508++0x03
line.long 0x00 "INTENA[2],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x250C++0x03
line.long 0x00 "INTENA[3],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2510++0x03
line.long 0x00 "INTENA[4],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2514++0x03
line.long 0x00 "INTENA[5],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2518++0x03
line.long 0x00 "INTENA[6],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x251C++0x03
line.long 0x00 "INTENA[7],interrupt A enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2580++0x03
line.long 0x00 "INTENB[0],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2584++0x03
line.long 0x00 "INTENB[1],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2588++0x03
line.long 0x00 "INTENB[2],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x258C++0x03
line.long 0x00 "INTENB[3],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2590++0x03
line.long 0x00 "INTENB[4],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2594++0x03
line.long 0x00 "INTENB[5],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2598++0x03
line.long 0x00 "INTENB[6],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x259C++0x03
line.long 0x00 "INTENB[7],interrupt B enable control register"
hexmask.long 0x00 0.--31. 1. " INT_EN  ,interrupt enable control for each pin(bit 0 for pion_0. bin 1 for pion_1. etc)"
group.long 0x2600++0x03
line.long 0x00 "INTPOL[0],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2604++0x03
line.long 0x00 "INTPOL[1],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2608++0x03
line.long 0x00 "INTPOL[2],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x260C++0x03
line.long 0x00 "INTPOL[3],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2610++0x03
line.long 0x00 "INTPOL[4],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2614++0x03
line.long 0x00 "INTPOL[5],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2618++0x03
line.long 0x00 "INTPOL[6],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x261C++0x03
line.long 0x00 "INTPOL[7],interupt polarity control register"
hexmask.long 0x00 0.--31. 1. " POL_CTL ,polarity control for each pin(bit 0 for pion_0. bit 1 for pion_1. etc"
group.long 0x2680++0x03
line.long 0x00 "INTEDG[0],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2684++0x03
line.long 0x00 "INTEDG[1],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2688++0x03
line.long 0x00 "INTEDG[2],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x268C++0x03
line.long 0x00 "INTEDG[3],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2690++0x03
line.long 0x00 "INTEDG[4],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2694++0x03
line.long 0x00 "INTEDG[5],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2698++0x03
line.long 0x00 "INTEDG[6],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x269C++0x03
line.long 0x00 "INTEDG[7],choose edge or level for interrupt"
hexmask.long 0x00 0.--31. 1. " EDGE    ,choose level or edge based detection for each pin(bit0 for pion_0. bit1 for pion_1. etc)"
group.long 0x2700++0x03
line.long 0x00 "INTSTATA[0],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2704++0x03
line.long 0x00 "INTSTATA[1],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2708++0x03
line.long 0x00 "INTSTATA[2],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x270C++0x03
line.long 0x00 "INTSTATA[3],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2710++0x03
line.long 0x00 "INTSTATA[4],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2714++0x03
line.long 0x00 "INTSTATA[5],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2718++0x03
line.long 0x00 "INTSTATA[6],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x271C++0x03
line.long 0x00 "INTSTATA[7],interrupt status for interrupt A"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2780++0x03
line.long 0x00 "INTSTATB[0],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2784++0x03
line.long 0x00 "INTSTATB[1],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2788++0x03
line.long 0x00 "INTSTATB[2],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x278C++0x03
line.long 0x00 "INTSTATB[3],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2790++0x03
line.long 0x00 "INTSTATB[4],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2794++0x03
line.long 0x00 "INTSTATB[5],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x2798++0x03
line.long 0x00 "INTSTATB[6],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
group.long 0x279C++0x03
line.long 0x00 "INTSTATB[7],interrupt status for interrupt B"
hexmask.long 0x00 0.--31. 1. " STATUS  ,interrupt status"
tree "B[0]"
width 8.
group.byte 0x00++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x01++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x02++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x03++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x04++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x05++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x06++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x07++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x08++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x09++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x0F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x10++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x11++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x12++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x13++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x14++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x15++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x16++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x17++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x18++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x19++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x1F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[1]"
width 8.
group.byte 0x20++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x21++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x22++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x23++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x24++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x25++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x26++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x27++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x28++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x29++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x2F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x30++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x31++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x32++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x33++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x34++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x35++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x36++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x37++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x38++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x39++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x3F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[2]"
width 8.
group.byte 0x40++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x41++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x42++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x43++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x44++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x45++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x46++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x47++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x48++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x49++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x4F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x50++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x51++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x52++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x53++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x54++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x55++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x56++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x57++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x58++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x59++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x5F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[3]"
width 8.
group.byte 0x60++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x61++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x62++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x63++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x64++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x65++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x66++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x67++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x68++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x69++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x6F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x70++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x71++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x72++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x73++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x74++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x75++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x76++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x77++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x78++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x79++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x7F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[4]"
width 8.
group.byte 0x80++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x81++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x82++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x83++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x84++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x85++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x86++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x87++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x88++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x89++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8A++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8B++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8C++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8D++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8E++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x8F++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x90++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x91++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x92++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x93++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x94++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x95++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x96++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x97++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x98++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x99++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9A++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9B++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9C++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9D++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9E++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0x9F++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[5]"
width 8.
group.byte 0xA0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xA9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAD++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xAF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xB9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xBF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[6]"
width 8.
group.byte 0xC0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xC9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCD++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xCF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xD9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xDF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "B[7]"
width 8.
group.byte 0xE0++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE1++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE2++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE3++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE4++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE5++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE6++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE7++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE8++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xE9++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEA++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEB++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEC++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xED++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEE++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xEF++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF0++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF1++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF2++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF3++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF4++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF5++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF6++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF7++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF8++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xF9++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFA++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFB++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFC++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFD++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFE++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
group.byte 0xFF++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port 0 and 1 GPIO pins"
bitfld.byte 0x00 0. " PBYTE ,Read: state of the pin PIOm_n. regardless of direction. masking. or alternate function. except that .." "0,1"
tree.end
tree "W[0]"
width 8.
group.long 0x1000++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1004++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1008++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x100C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1010++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1014++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1018++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x101C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1020++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1024++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1028++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x102C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1030++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1034++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1038++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x103C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1040++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1044++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1048++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x104C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1050++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1054++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1058++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x105C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1060++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1064++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1068++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x106C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1070++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1074++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1078++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x107C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[1]"
width 8.
group.long 0x1080++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1084++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1088++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x108C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1090++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1094++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1098++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x109C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x10FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[2]"
width 8.
group.long 0x1100++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1104++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1108++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x110C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1110++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1114++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1118++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x111C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1120++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1124++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1128++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x112C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1130++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1134++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1138++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x113C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1140++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1144++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1148++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x114C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1150++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1154++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1158++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x115C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1160++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1164++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1168++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x116C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1170++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1174++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1178++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x117C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[3]"
width 8.
group.long 0x1180++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1184++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1188++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x118C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1190++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1194++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1198++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x119C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x11FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[4]"
width 8.
group.long 0x1200++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1204++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1208++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x120C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1210++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1214++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1218++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x121C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1220++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1224++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1228++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x122C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1230++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1234++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1238++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x123C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1240++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1244++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1248++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x124C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1250++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1254++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1258++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x125C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1260++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1264++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1268++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x126C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1270++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1274++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1278++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x127C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[5]"
width 8.
group.long 0x1280++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1284++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1288++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x128C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1290++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1294++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1298++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x129C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x12FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[6]"
width 8.
group.long 0x1300++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1304++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1308++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x130C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1310++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1314++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1318++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x131C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1320++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1324++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1328++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x132C++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1330++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1334++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1338++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x133C++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1340++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1344++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1348++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x134C++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1350++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1354++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1358++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x135C++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1360++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1364++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1368++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x136C++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1370++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1374++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1378++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x137C++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
tree "W[7]"
width 8.
group.long 0x1380++0x03
line.long 0x00 "W_[0],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1384++0x03
line.long 0x00 "W_[1],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1388++0x03
line.long 0x00 "W_[2],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x138C++0x03
line.long 0x00 "W_[3],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1390++0x03
line.long 0x00 "W_[4],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1394++0x03
line.long 0x00 "W_[5],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x1398++0x03
line.long 0x00 "W_[6],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x139C++0x03
line.long 0x00 "W_[7],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A0++0x03
line.long 0x00 "W_[8],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A4++0x03
line.long 0x00 "W_[9],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13A8++0x03
line.long 0x00 "W_[10],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13AC++0x03
line.long 0x00 "W_[11],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B0++0x03
line.long 0x00 "W_[12],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B4++0x03
line.long 0x00 "W_[13],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13B8++0x03
line.long 0x00 "W_[14],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13BC++0x03
line.long 0x00 "W_[15],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C0++0x03
line.long 0x00 "W_[16],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C4++0x03
line.long 0x00 "W_[17],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13C8++0x03
line.long 0x00 "W_[18],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13CC++0x03
line.long 0x00 "W_[19],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D0++0x03
line.long 0x00 "W_[20],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D4++0x03
line.long 0x00 "W_[21],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13D8++0x03
line.long 0x00 "W_[22],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13DC++0x03
line.long 0x00 "W_[23],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E0++0x03
line.long 0x00 "W_[24],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E4++0x03
line.long 0x00 "W_[25],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13E8++0x03
line.long 0x00 "W_[26],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13EC++0x03
line.long 0x00 "W_[27],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F0++0x03
line.long 0x00 "W_[28],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F4++0x03
line.long 0x00 "W_[29],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13F8++0x03
line.long 0x00 "W_[30],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
group.long 0x13FC++0x03
line.long 0x00 "W_[31],Word pin registers for all port 0 and 1 GPIO pins"
hexmask.long 0x00 0.--31. 1. " PWORD ,Read 0: pin PIOm_n is LOW"
tree.end
width 0x0B
tree.end
tree.end
tree "HASHCRYPT"
base ad:0x40158000
width 12.
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register to enable and operate Hash and Crypto"
bitfld.long 0x00 12. " HASHSWPB   ,If 1. will swap bytes in the word for SHA hashing" "0,1"
textline "                     "
bitfld.long 0x00 9. " DMA_O      ,Written to 1 to use DMA to drain the digest/output" "0: DMA is not used,"
textline "                     "
bitfld.long 0x00 8. " DMA_I      ,Written with 1 to use DMA to fill INDATA" "0: DMA is not used,1: DMA will push in the data"
textline "                     "
bitfld.long 0x00 4. " New_Hash   ,Written with 1 when starting a new Hash/Crypto" ",1: Starts a new Hash/Crypto and initializes the Digest/Result"
textline "                     "
bitfld.long 0x00 0.--2. " Mode       ,The operational mode to use. or 0 if none" "0: DISABLED,1: SHA1 is enabled,2: SHA2-256 is enabled,,4: AES if available (see also CRYPTCFG register for more controls),5: ICB-AES if available (see also CRYPTCFG register for more controls),,"
group.long 0x04++0x03
line.long 0x00 "STATUS,Indicates status of Hash peripheral"
rbitfld.long 0x00 16.--21. " ICBIDX     ,If ICB-AES is selected. then reads as the ICB index count based on ICBSTRM (from CRYPTCFG)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                     "
rbitfld.long 0x00 5. " NEEDIV     ,Indicates the block wants an IV/NONE to be written in (set along with WAITING)" "0: No IV/Nonce is needed. either because written already or because not needed,1: IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce"
textline "                     "
rbitfld.long 0x00 4. " NEEDKEY    ,Indicates the block wants the key to be written in (set along with WAITING)" "0: No Key is needed and writes will not be treated as Key,1: Key is needed and INDATA/ALIAS will be accepted as Key"
textline "                     "
eventfld.long 0x00 2. " ERROR      ,If 1. an error occurred" "0: NO_ERROR,1: An error occurred since last cleared (written 1 to clear)"
textline "                     "
rbitfld.long 0x00 1. " DIGEST     ,For Hash. if 1 then a DIGEST is ready and waiting and there is no active next block already started" "0: No Digest is ready,1: Digest is ready"
textline "                     "
rbitfld.long 0x00 0. " WAITING    ,If 1. the block is waiting for more data to process" "0: Not waiting for data - may be disabled or may be busy,1: Waiting for data to be written in (16 words)"
group.long 0x08++0x03
line.long 0x00 "INTENSET,Write 1 to enable interrupts. reads back with which are set"
bitfld.long 0x00 2. " ERROR      ,Indicates if should interrupt on an ERROR (as defined in Status)" "0: Will not interrupt on Error,1: Will interrupt on Error (until cleared)"
textline "                     "
bitfld.long 0x00 1. " DIGEST     ,Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or complete.." "0: Will not interrupt when Digest is ready,1: Will interrupt when Digest is ready"
textline "                     "
bitfld.long 0x00 0. " WAITING    ,Indicates if should interrupt when waiting for data input" "0: Will not interrupt when waiting,1: Will interrupt when waiting"
group.long 0x0C++0x03
line.long 0x00 "INTENCLR,Write 1 to clear interrupts"
eventfld.long 0x00 2. " ERROR      ,Write 1 to clear mask" "0,1"
textline "                     "
eventfld.long 0x00 1. " DIGEST     ,Write 1 to clear mask" "0,1"
textline "                     "
eventfld.long 0x00 0. " WAITING    ,Write 1 to clear mask" "0,1"
group.long 0x10++0x03
line.long 0x00 "MEMCTRL,Setup Master to access memory (if available)"
hexmask.long.word 0x00 16.--26. 1. " COUNT      ,Number of 512-bit (128-bit if AES. except 1st block which may include key and IV) blocks to copy sta.."
textline "                     "
bitfld.long 0x00 0. " MASTER     ,Enables mastering" "0: Mastering is not used and the normal DMA or Interrupt based model is used with INDATA,1: Mastering is enabled and DMA and INDATA should not be used"
group.long 0x14++0x03
line.long 0x00 "MEMADDR,Address to start memory access from (if available)"
hexmask.long 0x00 0.--31. 1. " BASE       ,Address base to start copying from. word aligned (so bits 1:0 must be 0)"
wgroup.long 0x20++0x03
line.long 0x00 "INDATA,Input of 16 words at a time to load up buffer"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x24++0x03
line.long 0x00 "ALIAS[0],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x28++0x03
line.long 0x00 "ALIAS[1],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x2C++0x03
line.long 0x00 "ALIAS[2],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x30++0x03
line.long 0x00 "ALIAS[3],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x34++0x03
line.long 0x00 "ALIAS[4],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x38++0x03
line.long 0x00 "ALIAS[5],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
wgroup.long 0x3C++0x03
line.long 0x00 "ALIAS[6],no description available"
hexmask.long 0x00 0.--31. 1. " DATA       ,Write next word in little-endian form"
rgroup.long 0x40++0x03
line.long 0x00 "DIGEST0[0],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x44++0x03
line.long 0x00 "DIGEST0[1],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x48++0x03
line.long 0x00 "DIGEST0[2],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x4C++0x03
line.long 0x00 "DIGEST0[3],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x50++0x03
line.long 0x00 "DIGEST0[4],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x54++0x03
line.long 0x00 "DIGEST0[5],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x58++0x03
line.long 0x00 "DIGEST0[6],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
rgroup.long 0x5C++0x03
line.long 0x00 "DIGEST0[7],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,One word of the Digest or output"
group.long 0x80++0x03
line.long 0x00 "CRYPTCFG,Crypto settings for AES and Salsa and ChaCha"
bitfld.long 0x00 22.--23. " ICBSTRM    ,The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter st.." "0: BLOCKS_8,1: BLOCKS_16,2: BLOCKS_32,3: BLOCKS_64"
textline "                     "
bitfld.long 0x00 20.--21. " ICBSZ      ,This sets the ICB size between 32 and 128 bits. using the following rules" "0: 32 bits of the IV/ctr are used (from 127:96),1: 64 bits of the IV/ctr are used (from 127:64),2: 96 bits of the IV/ctr are used (from 127:32),3: All 128 bits of the IV/ctr are used"
textline "                     "
bitfld.long 0x00 16. " STREAMLAST ,Is 1 if last stream block" "0,1"
textline "                     "
bitfld.long 0x00 10.--12. " AESCTRPOS  ,Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha)" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 8.--9. " AESKEYSZ   ,Sets the AES key size" "0: 128 bit key,1: 192 bit key,2: 256 bit key,"
textline "                     "
bitfld.long 0x00 7. " AESSECRET  ,Selects the Hidden Secret key vs" "0: User key provided in normal way,1: Secret key provided in hidden way by HW"
textline "                     "
bitfld.long 0x00 6. " AESDECRYPT ,AES ECB direction" "0: ENCRYPT,1: DECRYPT"
textline "                     "
bitfld.long 0x00 4.--5. " AESMODE    ,AES Cipher mode to use if plain AES" "0: ECB - used as is,1: CBC mode (see details on IV/nonce),2: CTR mode (see details on IV/nonce),"
textline "                     "
bitfld.long 0x00 3. " MSW1ST     ,If 1. load of key. IV. and data is MSW 1st for AES" "0,1"
textline "                     "
bitfld.long 0x00 2. " SWAPDAT    ,If 1. will SWAP the data and IV inputs (bytes in each word)" "0,1"
textline "                     "
bitfld.long 0x00 1. " SWAPKEY    ,If 1. will Swap the key input (bytes in each word)" "0,1"
textline "                     "
bitfld.long 0x00 0. " MSW1ST_OUT ,If 1. OUTDATA0 will be read Most significant word 1st for AES" "0,1"
group.long 0x84++0x03
line.long 0x00 "CONFIG,Returns the configuration of this block in this chip - indicates what services are available"
rbitfld.long 0x00 11. " ICB        ,1 if ICB over AES included" "0,1"
textline "                     "
rbitfld.long 0x00 8. " SECRET     ,1 if AES Secret key available" "0,1"
textline "                     "
rbitfld.long 0x00 7. " AESKEY     ,1 if AES 192 and 256 also included" "0,1"
textline "                     "
rbitfld.long 0x00 6. " AES        ,1 if AES 128 included" "0,1"
textline "                     "
rbitfld.long 0x00 3. " AHB        ,1 if AHB Master is enabled" "0,1"
textline "                     "
rbitfld.long 0x00 1. " DMA        ,1 if DMA is connected" "0,1"
textline "                     "
rbitfld.long 0x00 0. " DUAL       ,1 if 2 x 512 bit buffers. 0 if only 1 x 512 bit" "0,1"
group.long 0x8C++0x03
line.long 0x00 "LOCK,Lock register allows locking to the current security level or unlocking by the lock holding level"
hexmask.long.word 0x00 4.--15. 1. " PATTERN    ,Must write 0xA75 to change lock state"
textline "                     "
bitfld.long 0x00 0.--1. " SECLOCK    ,Write 1 to secure-lock this block (if running in a security state)" "0: Unlocks. so block is open to all,1: Locks to the current security level,,"
wgroup.long 0x90++0x03
line.long 0x00 "MASK[0],no description available"
hexmask.long 0x00 0.--31. 1. " MASK       ,A random word"
wgroup.long 0x94++0x03
line.long 0x00 "MASK[1],no description available"
hexmask.long 0x00 0.--31. 1. " MASK       ,A random word"
wgroup.long 0x98++0x03
line.long 0x00 "MASK[2],no description available"
hexmask.long 0x00 0.--31. 1. " MASK       ,A random word"
wgroup.long 0x9C++0x03
line.long 0x00 "MASK[3],no description available"
hexmask.long 0x00 0.--31. 1. " MASK       ,A random word"
wgroup.long 0xA0++0x03
line.long 0x00 "RELOAD[0],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xA4++0x03
line.long 0x00 "RELOAD[1],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xA8++0x03
line.long 0x00 "RELOAD[2],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xAC++0x03
line.long 0x00 "RELOAD[3],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xB0++0x03
line.long 0x00 "RELOAD[4],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xB4++0x03
line.long 0x00 "RELOAD[5],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xB8++0x03
line.long 0x00 "RELOAD[6],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xBC++0x03
line.long 0x00 "RELOAD[7],no description available"
hexmask.long 0x00 0.--31. 1. " DIGEST     ,SHA Digest word to reload"
wgroup.long 0xD0++0x03
line.long 0x00 "PRNG_SEED,PRNG random seed input value used as an entropy source"
hexmask.long 0x00 0.--31. 1. " PRNG_SEED  ,Random input value used as an entropy source"
rgroup.long 0xD8++0x03
line.long 0x00 "PRNG_OUT,PRNG software-accessable random output value"
hexmask.long 0x00 0.--31. 1. " PRNG_OUT   ,Random output value from the PRNG"
width 0x0B
tree.end
tree "I2C (Inter-Integrated Circuit)"
tree "I2C0"
base ad:0x40106000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C1"
base ad:0x40107000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C2"
base ad:0x40108000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C3"
base ad:0x40109000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C4"
base ad:0x40122000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C5"
base ad:0x40123000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C6"
base ad:0x40124000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C7"
base ad:0x40125000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "I2C15"
base ad:0x40127000
width 11.
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. " HSCAPABLE       ,High-speed mode Capable enable" "0: FAST_MODE_PLUS,1: HIGH_SPEED"
textline "                    "
bitfld.long 0x00 4. " MONCLKSTR       ,Monitor function Clock Stretching" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 3. " TIMEOUTEN       ,I2C bus Time-out Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MONEN           ,Monitor Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVEN           ,Slave Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTEN           ,Master Enable" "0: DISABLED,1: ENABLED"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0: NOT_IDLE,1: IDLE"
textline "                    "
rbitfld.long 0x00 18. " MONACTIVE       ,Monitor Active flag" "0: INACTIVE,1: ACTIVE"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0: NO_OVERRUN,1: OVERRUN"
textline "                    "
rbitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0: NO_DATA,1: DATA_WAITING"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0: NOT_DESELECTED,1: DESELECTED"
textline "                    "
rbitfld.long 0x00 14. " SLVSEL          ,Slave selected flag" "0: NOT_SELECTED,1: SELECTED"
textline "                    "
rbitfld.long 0x00 12.--13. " SLVIDX          ,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
textline "                    "
rbitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching" "0: STRETCHING,1: NOT_STRETCHING"
textline "                    "
rbitfld.long 0x00 9.--10. " SLVSTATE        ,Slave State code" "0: SLAVE_ADDRESS,1: SLAVE_RECEIVE,2: SLAVE_TRANSMIT,"
textline "                    "
rbitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0: IN_PROGRESS,1: PENDING"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a Start/Stop Error"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: ARBITRATION_LOSS"
textline "                    "
rbitfld.long 0x00 1.--3. " MSTSTATE        ,Master State code" "0: IDLE,1: RECEIVE_READY,2: TRANSMIT_READY,3: NACK_ADDRESS,4: NACK_DATA,,,"
textline "                    "
rbitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0: IN_PROGRESS,1: PENDING"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. " SCLTIMEOUTEN    ,SCL time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTEN  ,Event time-out interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 19. " MONIDLEEN       ,Monitor Idle interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 17. " MONOVEN         ,Monitor Overrun interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 16. " MONRDYEN        ,Monitor data Ready interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 15. " SLVDESELEN      ,Slave Deselect interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTREN     ,Slave Not Stretching interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGEN    ,Slave Pending interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERREN   ,Master Start/Stop Error interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSEN    ,Master Arbitration Loss interrupt Enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGEN    ,Master Pending interrupt Enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. " SCLTIMEOUTCLR   ,SCL time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUTCLR ,Event time-out interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLECLR      ,Monitor Idle interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOVCLR        ,Monitor Overrun interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDYCLR       ,Monitor data Ready interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESELCLR     ,Slave Deselect interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTRCLR    ,Slave Not Stretching interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDINGCLR   ,Slave Pending interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERRCLR  ,Master Start/Stop Error interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSSCLR   ,Master Arbitration Loss interrupt clear" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDINGCLR   ,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
hexmask.long.word 0x00 4.--15. 1. " TO              ,Time-out time value"
textline "                    "
bitfld.long 0x00 0.--3. " TOMIN           ,Time-out time value. bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL          ,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal.."
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master. Slave. and Monitor functions"
bitfld.long 0x00 25. " SCLTIMEOUT      ,SCL time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 24. " EVENTTIMEOUT    ,Event time-out Interrupt flag" "0,1"
textline "                    "
bitfld.long 0x00 19. " MONIDLE         ,Monitor Idle flag" "0,1"
textline "                    "
bitfld.long 0x00 17. " MONOV           ,Monitor Overflow flag" "0,1"
textline "                    "
bitfld.long 0x00 16. " MONRDY          ,Monitor Ready" "0,1"
textline "                    "
bitfld.long 0x00 15. " SLVDESEL        ,Slave Deselected flag" "0,1"
textline "                    "
bitfld.long 0x00 11. " SLVNOTSTR       ,Slave Not Stretching status" "0,1"
textline "                    "
bitfld.long 0x00 8. " SLVPENDING      ,Slave Pending" "0,1"
textline "                    "
bitfld.long 0x00 6. " MSTSTSTPERR     ,Master Start/Stop Error flag" "0,1"
textline "                    "
bitfld.long 0x00 4. " MSTARBLOSS      ,Master Arbitration Loss flag" "0,1"
textline "                    "
bitfld.long 0x00 0. " MSTPENDING      ,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. " MSTDMA          ,Master DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 2. " MSTSTOP         ,Master Stop control" "0: NO_EFFECT,1: STOP"
textline "                    "
bitfld.long 0x00 1. " MSTSTART        ,Master Start control" "0: NO_EFFECT,1: START"
textline "                    "
bitfld.long 0x00 0. " MSTCONTINUE     ,Master Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. " MSTSCLHIGH      ,Master SCL High time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
textline "                    "
bitfld.long 0x00 0.--2. " MSTSCLLOW       ,Master SCL Low time" "0: CLOCKS_2,1: CLOCKS_3,2: CLOCKS_4,3: CLOCKS_5,4: CLOCKS_6,5: CLOCKS_7,6: CLOCKS_8,7: CLOCKS_9"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. " AUTOMATCHREAD   ,When AUTOACK is set. this bit controls whether it matches a read or write request on the next header.." "0: The expected next operation in Automatic Mode is an I2C write,1: The expected next operation in Automatic Mode is an I2C read"
textline "                    "
bitfld.long 0x00 8. " AUTOACK         ,Automatic Acknowledge" "0: Normal. non-automatic operation,1: A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediat.."
textline "                    "
bitfld.long 0x00 3. " SLVDMA          ,Slave DMA enable" "0: DISABLED,1: ENABLED"
textline "                    "
bitfld.long 0x00 1. " SLVNACK         ,Slave NACK" "0: NO_EFFECT,1: NACK"
textline "                    "
bitfld.long 0x00 0. " SLVCONTINUE     ,Slave Continue" "0: NO_EFFECT,1: CONTINUE"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. " DATA            ,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR[0],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x84C++0x03
line.long 0x00 "SLVADR[1],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x850++0x03
line.long 0x00 "SLVADR[2],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x854++0x03
line.long 0x00 "SLVADR[3],Slave address register"
bitfld.long 0x00 15. " AUTONACK        ,Automatic NACK operation" "0: Normal operation. matching I2C addresses are not ignored,1: Automatic-only mode"
textline "                    "
hexmask.long.byte 0x00 1.--7. 1. " SLVADR          ,Slave Address"
textline "                    "
bitfld.long 0x00 0. " SADISABLE       ,Slave Address n Disable" "0: ENABLED,1: Ignored Slave Address n is ignored"
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. " SLVQUAL0        ,Slave address Qualifier for address 0"
textline "                    "
bitfld.long 0x00 0. " QUALMODE0       ,Qualify mode for slave address 0" "0: MASK,1: EXTEND"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. " MONNACK         ,Monitor Received NACK" "0: ACKNOWLEDGED,1: NOT_ACKNOWLEDGED"
textline "                    "
bitfld.long 0x00 9. " MONRESTART      ,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
textline "                    "
bitfld.long 0x00 8. " MONSTART        ,Monitor Received Start" "0: NO_START_DETECTED,1: START_DETECTED"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT        ,Monitor function Receiver Data"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID              ,Module identifier for the selected function"
textline "                    "
bitfld.long 0x00 12.--15. " MAJOR_REV       ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 8.--11. " MINOR_REV       ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE        ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree.end
tree "I2S (Inter-Integrated Sound Bus Controller)"
tree "I2S0"
base ad:0x40106000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S1"
base ad:0x40107000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S2"
base ad:0x40108000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S3"
base ad:0x40109000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S4"
base ad:0x40122000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S5"
base ad:0x40123000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S6"
base ad:0x40124000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree "I2S7"
base ad:0x40125000
width 16.
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. " DATALEN    ,Data Length. minus 1 encoded. defines the number of data bits to be transmitted or received for all .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 13. " WS_POL     ,WS polarity" "0: Data frames begin at a falling edge of WS (standard for classic I2S),1: WS is inverted. resulting in a data frame beginning at a rising edge of WS (standard for most 'non-c.."
textline "                         "
bitfld.long 0x00 12. " SCK_POL    ,SCK polarity" "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S),1: Data is launched on SCK rising edges and sampled on SCK falling edges"
textline "                         "
bitfld.long 0x00 11. " PDMDATA    ,PDM Data selection" "0: Normal operation. data is transferred to or from the Flexcomm FIFO,1: The data source is the D-Mic subsystem"
textline "                         "
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0: I2S data for this channel pair is treated as left and right channels,1: I2S data for this channel pair is treated as a single channel. functionally the left channel for thi.."
textline "                         "
bitfld.long 0x00 9. " LEFTJUST   ,Left Justify data" "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified. i,1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified. i"
textline "                         "
bitfld.long 0x00 8. " RIGHTLOW   ,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part of the FIFO data,1: The right channel is taken from the low part of the FIFO data"
textline "                         "
bitfld.long 0x00 6.--7. " MODE       ,Selects the basic I2S operating mode" "0: CLASSIC_MODE,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse at the beginning of each data frame,3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame"
textline "                         "
bitfld.long 0x00 4.--5. " MSTSLVCFG  ,Master / slave configuration selection. determining how SCK and WS are used by all channel pairs in .." "0: Normal slave mode. the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
textline "                         "
bitfld.long 0x00 2.--3. " PAIRCOUNT  ,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may .." "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
textline "                         "
bitfld.long 0x00 1. " DATAPAUSE  ,Data flow Pause" "0: Normal operation. or resuming normal operation at the next frame if the I2S has already been paused,1: A pause in the data flow is being requested"
textline "                         "
bitfld.long 0x00 0. " MAINENABLE ,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines. counters. and ..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
hexmask.long.word 0x00 16.--26. 1. " POSITION   ,Data Position"
textline "                         "
hexmask.long.word 0x00 0.--10. 1. " FRAMELEN   ,Frame Length. minus 1 encoded. defines the number of clocks and data bits in the frames that this ch.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in force"
textline "                         "
rbitfld.long 0x00 2. " LR         ,Left/Right indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL"
textline "                         "
bitfld.long 0x00 1. " SLVFRMERR  ,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel pair that is operating in slave mode"
textline "                         "
rbitfld.long 0x00 0. " BUSY       ,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is currently idle,1: The transmitter/receiver for channel pair is currently processing data"
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider. used by all channel pairs"
hexmask.long.word 0x00 0.--11. 1. " DIV        ,This field controls how this I2S block uses the Flexcomm function clock"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX    ,Empty command for the receive FIFO" "0,1"
textline "                         "
bitfld.long 0x00 16. " EMPTYTX    ,Empty command for the transmit FIFO" "0,1"
textline "                         "
bitfld.long 0x00 15. " WAKERX     ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                         "
bitfld.long 0x00 14. " WAKETX     ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                         "
bitfld.long 0x00 13. " DMARX      ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                         "
bitfld.long 0x00 12. " DMATX      ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                         "
rbitfld.long 0x00 4.--5. " SIZE       ,FIFO size configuration" "0,1,2,3"
textline "                         "
bitfld.long 0x00 3. " PACK48     ,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all 24-bit values,1: 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values"
textline "                         "
bitfld.long 0x00 2. " TXI2SE0    ,Transmit I2S empty 0" "0: If the TX FIFO becomes empty. the last value is sent,1: If the TX FIFO becomes empty. 0 is sent"
textline "                         "
bitfld.long 0x00 1. " ENABLERX   ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                         "
bitfld.long 0x00 0. " ENABLETX   ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL      ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 8.--12. " TXLVL      ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
rbitfld.long 0x00 7. " RXFULL     ,Receive FIFO full" "0,1"
textline "                         "
rbitfld.long 0x00 6. " RXNOTEMPTY ,Receive FIFO not empty" "0,1"
textline "                         "
rbitfld.long 0x00 5. " TXNOTFULL  ,Transmit FIFO not full" "0,1"
textline "                         "
rbitfld.long 0x00 4. " TXEMPTY    ,Transmit FIFO empty" "0,1"
textline "                         "
rbitfld.long 0x00 3. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL      ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " TXLVL      ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 1. " RXLVLENA   ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                         "
bitfld.long 0x00 0. " TXLVLENA   ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT     ,Peripheral interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " RXLVL      ,Receive FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 2. " TXLVL      ,Transmit FIFO level interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " RXERR      ,RX FIFO error" "0,1"
textline "                         "
bitfld.long 0x00 0. " TXERR      ,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. " TXDATA     ,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " TXDATA     ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. " RXDATA     ,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA     ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE   ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. " ID         ,Unique module identifier for this IP block"
textline "                         "
bitfld.long 0x00 12.--15. " Major_Rev  ,Major revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 8.--11. " Minor_Rev  ,Minor revision of module implementation. starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " Aperture   ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
tree "SECCHANNEL[0]"
width 7.
group.long 0xC20++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC24++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC28++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[1]"
width 7.
group.long 0xC40++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC44++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC48++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
tree "SECCHANNEL[2]"
width 7.
group.long 0xC60++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. " ONECHANNEL ,Single channel mode" "0,1"
textline "                "
bitfld.long 0x00 0. " PAIRENABLE ,Enable for this channel pair" "0,1"
group.long 0xC64++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. " POSITION   ,Data Position"
group.long 0xC68++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. " DATAPAUSED ,Data Paused status flag" "0,1"
textline "                "
bitfld.long 0x00 2. " LR         ,Left/Right indication" "0,1"
textline "                "
bitfld.long 0x00 1. " SLVFRMERR  ,Save Frame Error flag" "0,1"
textline "                "
bitfld.long 0x00 0. " BUSY       ,Busy status for this channel pair" "0,1"
tree.end
width 0x0B
tree.end
tree.end
tree "I3C"
base ad:0x40036000
width 19.
group.long 0x00++0x03
line.long 0x00 "MCONFIG,Master Configuration Register"
bitfld.long 0x00 28.--31. " I2CBAUD    ,I2C baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 25.--27. " SKEW       ,Skew" "0,1,2,3,4,5,6,7"
textline "                            "
bitfld.long 0x00 24. " ODHPP      ,Open drain high push-pull" "0,1"
textline "                            "
hexmask.long.byte 0x00 16.--23. 1. " ODBAUD     ,Open drain baud rate"
textline "                            "
bitfld.long 0x00 12.--15. " PPLOW      ,Push-Pull low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 8.--11. " PPBAUD     ,Push-pull baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 6. " ODSTOP     ,Open drain stop" "0,1"
textline "                            "
bitfld.long 0x00 4.--5. " HKEEP      ,High-Keeper" "0: NONE: Use PUR (Pull-Up Resistor),1: WIRED_IN: Wired-in High Keeper controls. use pin_HK (High Keeper) controls,2: PASSIVE_SDA: Passive on SDA. can Hi-Z (high impedance) for Bus Free (IDLE) and hold,3: PASSIVE_ON_SDA_SCL: Passive on SDA and SCL. can Hi-Z (high impedance) both for Bus Free (IDLE). and .."
textline "                            "
bitfld.long 0x00 3. " DISTO      ,Disable Timeout" "0,1"
textline "                            "
bitfld.long 0x00 0.--1. " MSTENA     ,Master enable" "0: MASTER_OFF: Master is off (is not enabled),1: MASTER_ON: Master is on (is enabled),2: MASTER_CAPABLE: The I3C module is master-capable. however the module is operating as a slave now,"
group.long 0x04++0x03
line.long 0x00 "SCONFIG,Slave Configuration Register"
hexmask.long.byte 0x00 25.--31. 1. " SADDR      ,Static address"
textline "                            "
hexmask.long.byte 0x00 16.--23. 1. " BAMATCH    ,Bus available match"
textline "                            "
bitfld.long 0x00 9. " OFFLINE    ,Offline" "0,1"
textline "                            "
bitfld.long 0x00 8. " IDRAND     ,ID random" "0,1"
textline "                            "
bitfld.long 0x00 4. " DDROK      ,Double Data Rate OK" "0,1"
textline "                            "
bitfld.long 0x00 3. " S0IGNORE   ,S0/S1 errors ignore" "0,1"
textline "                            "
bitfld.long 0x00 2. " MATCHSS    ,Match START or STOP" "0,1"
textline "                            "
bitfld.long 0x00 1. " NACK       ,Not acknowledge" "0,1"
textline "                            "
bitfld.long 0x00 0. " SLVENA     ,Slave enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SSTATUS,Slave Status Register"
rbitfld.long 0x00 30.--31. " TIMECTRL   ,Time control" "0: NO_TIME_CONTROL: No time control is enabled,,2: ASYNC_MODE: Asynchronous standard mode (0) is enabled,"
textline "                            "
rbitfld.long 0x00 28.--29. " ACTSTATE   ,Activity state from Common Command Codes (CCC)" "0: NO_LATENCY: normal bus operations,1: LATENCY_1MS: 1 ms of latency,2: LATENCY_100MS: 100 ms of latency,3: LATENCY_10S: 10 seconds of latency"
textline "                            "
rbitfld.long 0x00 27. " HJDIS      ,Hot-Join is disabled" "0,1"
textline "                            "
rbitfld.long 0x00 25. " MRDIS      ,Master requests are disabled" "0,1"
textline "                            "
rbitfld.long 0x00 24. " IBIDIS     ,In-Band Interrupts are disabled" "0,1"
textline "                            "
rbitfld.long 0x00 20.--21. " EVDET      ,Event details" "0: NONE: no event or no pending event,1: NO_REQUEST: Request not sent yet,2: NACKED: Not acknowledged(Request sent and NACKed). the module will try again,3: ACKED: Acknowledged (Request sent and ACKed). so Done (unless the time control data is still being s.."
textline "                            "
bitfld.long 0x00 18. " EVENT      ,Event" "0,1"
textline "                            "
bitfld.long 0x00 17. " CHANDLED   ,Common-Command-Code handled" "0,1"
textline "                            "
bitfld.long 0x00 16. " HDRMATCH   ,High Data Rate command match" "0,1"
textline "                            "
rbitfld.long 0x00 15. " ERRWARN    ,Error warning" "0,1"
textline "                            "
bitfld.long 0x00 14. " CCC        ,Common Command Code" "0,1"
textline "                            "
bitfld.long 0x00 13. " DACHG      ,DACHG" "0,1"
textline "                            "
rbitfld.long 0x00 12. " TXNOTFULL  ,Transmit buffer is not full" "0,1"
textline "                            "
rbitfld.long 0x00 11. " RX_PEND    ,Received message pending" "0,1"
textline "                            "
bitfld.long 0x00 10. " STOP       ,Stop" "0,1"
textline "                            "
bitfld.long 0x00 9. " MATCHED    ,Matched" "0,1"
textline "                            "
bitfld.long 0x00 8. " START      ,Start" "0,1"
textline "                            "
rbitfld.long 0x00 6. " STHDR      ,Status High Data Rate" "0,1"
textline "                            "
rbitfld.long 0x00 5. " STDAA      ,Status Dynamic Address Assignment" "0,1"
textline "                            "
rbitfld.long 0x00 4. " STREQWR    ,Status request write" "0,1"
textline "                            "
rbitfld.long 0x00 3. " STREQRD    ,Status required" "0,1"
textline "                            "
rbitfld.long 0x00 2. " STCCCH     ,Status Common Command Code Handler" "0,1"
textline "                            "
rbitfld.long 0x00 1. " STMSG      ,Status message" "0,1"
textline "                            "
rbitfld.long 0x00 0. " STNOTSTOP  ,Status not stop" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SCTRL,Slave Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VENDINFO   ,Vendor information"
textline "                            "
bitfld.long 0x00 20.--21. " ACTSTATE   ,Activity state (of slave)" "0,1,2,3"
textline "                            "
bitfld.long 0x00 16.--19. " PENDINT    ,Pending interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.byte 0x00 8.--15. 1. " IBIDATA    ,In-Band Interrupt data"
textline "                            "
bitfld.long 0x00 0.--1. " EVENT      ,EVENT" "0: NORMAL_MODE: If EVENT is set to 0 after was a non-0 value. event processing will cancel if the event..,1: IBI: Start an In-Band Interrupt,2: MASTER_REQUEST: Start a Master-Request,3: HOT_JOIN_REQUEST: Start a Hot-Join request"
group.long 0x10++0x03
line.long 0x00 "SINTSET,Slave Interrupt Set Register"
bitfld.long 0x00 18. " EVENT      ,Event interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 17. " CHANDLED   ,Common Command Code (CCC) (that was handled by I3C module) interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 16. " DDRMATCHED ,Double Data Rate (DDR) interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 15. " ERRWARN    ,Error/warning interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 14. " CCC        ,Common Command Code (CCC) (that was not handled by I3C module) interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 13. " DACHG      ,Dynamic address change interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 12. " TXSEND     ,Transmit interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 11. " RXPEND     ,Receive interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 10. " STOP       ,Stop interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 9. " MATCHED    ,Match interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 8. " START      ,Start interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "SINTCLR,Slave Interrupt Clear Register"
eventfld.long 0x00 18. " EVENT      ,EVENT interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 17. " CHANDLED   ,CHANDLED interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 16. " DDRMATCHED ,DDRMATCHED interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 15. " ERRWARN    ,ERRWARN interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 14. " CCC        ,CCC interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 13. " DACHG      ,DACHG interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 12. " TXSEND     ,TXSEND interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 11. " RXPEND     ,RXPEND interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 10. " STOP       ,STOP interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 9. " MATCHED    ,MATCHED interrupt enable clear" "0,1"
textline "                            "
eventfld.long 0x00 8. " START      ,START interrupt enable clear" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "SINTMASKED,Slave Interrupt Mask Register"
bitfld.long 0x00 18. " EVENT      ,EVENT interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 17. " CHANDLED   ,CHANDLED interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 16. " DDRMATCHED ,DDRMATCHED interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 15. " ERRWARN    ,ERRWARN interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 14. " CCC        ,CCC interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 13. " DACHG      ,DACHG interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 12. " TXSEND     ,TXSEND interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 11. " RXPEND     ,RXPEND interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 10. " STOP       ,STOP interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 9. " MATCHED    ,MATCHED interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 8. " START      ,START interrupt mask" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SERRWARN,Slave Errors and Warnings Register"
bitfld.long 0x00 17. " OWRITE     ,Over-write error" "0,1"
textline "                            "
bitfld.long 0x00 16. " OREAD      ,Over-read error" "0,1"
textline "                            "
bitfld.long 0x00 11. " S0S1       ,S0 or S1 error" "0,1"
textline "                            "
bitfld.long 0x00 10. " HCRC       ,HDR-DDR CRC error" "0,1"
textline "                            "
bitfld.long 0x00 9. " HPAR       ,HDR parity error" "0,1"
textline "                            "
bitfld.long 0x00 8. " SPAR       ,SDR parity error" "0,1"
textline "                            "
bitfld.long 0x00 4. " INVSTART   ,Invalid start error" "0,1"
textline "                            "
bitfld.long 0x00 3. " TERM       ,Terminated error" "0,1"
textline "                            "
bitfld.long 0x00 2. " URUNNACK   ,Underrun and Not Acknowledged (NACKed) error" "0,1"
textline "                            "
bitfld.long 0x00 1. " URUN       ,Underrun error" "0,1"
textline "                            "
bitfld.long 0x00 0. " ORUN       ,Overrun error" "0,1"
group.long 0x20++0x03
line.long 0x00 "SDMACTRL,Slave DMA Control Register"
bitfld.long 0x00 4.--5. " DMAWIDTH   ,Width of DMA operations" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD: Half word (16 bits),"
textline "                            "
bitfld.long 0x00 2.--3. " DMATB      ,DMA Write (To-bus) trigger" "0: NOT_USED: DMA is not used,1: ENABLE_ONE_FRAME: DMA is enabled for 1 Frame (ended by DMA or terminated),2: ENABLE: DMA is enabled until turned off,"
textline "                            "
bitfld.long 0x00 0.--1. " DMAFB      ,DMA Read (From-bus) trigger" "0: DMA not used,1: DMA is enabled for 1 frame,2: DMA enable,"
group.long 0x2C++0x03
line.long 0x00 "SDATACTRL,Slave Data Control Register"
rbitfld.long 0x00 31. " RXEMPTY    ,RX is empty" "0: RX is not empty,1: RX is empty"
textline "                            "
rbitfld.long 0x00 30. " TXFULL     ,TX is full" "0: TX is not full,1: TX is full"
textline "                            "
rbitfld.long 0x00 24.--28. " RXCOUNT    ,Count of bytes in RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
rbitfld.long 0x00 16.--20. " TXCOUNT    ,Count of bytes in TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 6.--7. " RXTRIG     ,Trigger level for RX FIFO fullness" "0: Trigger on not empty,1: Trigger on or more full,2: Trigger on .5 or more full,3: Trigger on 3/4 or more full"
textline "                            "
bitfld.long 0x00 4.--5. " TXTRIG     ,Trigger level for TX FIFO emptiness" "0: Trigger on empty,1: Trigger on full or less,2: Trigger on .5 full or less,3: Trigger on 1 less than full or less (Default)"
textline "                            "
bitfld.long 0x00 3. " UNLOCK     ,Unlock" "0,1"
textline "                            "
bitfld.long 0x00 1. " FLUSHFB    ,Flushes the from-bus buffer/FIFO" "0,1"
textline "                            "
bitfld.long 0x00 0. " FLUSHTB    ,Flush the to-bus buffer/FIFO" "0,1"
group.long 0x30++0x03
line.long 0x00 "SWDATAB,Slave Write Data Byte Register"
bitfld.long 0x00 16. " END_ALSO   ,End also" "0,1"
textline "                            "
bitfld.long 0x00 8. " END        ,End" "0,1"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA       ,The data byte to send to the master"
group.long 0x34++0x03
line.long 0x00 "SWDATABE,Slave Write Data Byte End"
hexmask.long.byte 0x00 0.--7. 1. " DATA       ,The data byte to send to the master"
group.long 0x38++0x03
line.long 0x00 "SWDATAH,Slave Write Data Half-word Register"
bitfld.long 0x00 16. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.byte 0x00 8.--15. 1. " DATA1      ,The 2nd byte to send to the master"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA0      ,The 1st byte to send to the master"
group.long 0x3C++0x03
line.long 0x00 "SWDATAHE,Slave Write Data Half-word End Register"
hexmask.long.byte 0x00 8.--15. 1. " DATA1      ,The 2nd byte to send to the master"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA0      ,The 1st byte to send to the master"
rgroup.long 0x40++0x03
line.long 0x00 "SRDATAB,Slave Read Data Byte Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA0      ,Byte read from the master"
rgroup.long 0x48++0x03
line.long 0x00 "SRDATAH,Slave Read Data Half-word Register"
hexmask.long.byte 0x00 8.--15. 1. " MSB        ,The 2nd byte read from the slave"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " LSB        ,The 1st byte read from the slave"
rgroup.long 0x60++0x03
line.long 0x00 "SCAPABILITIES,Slave Capabilities Register"
bitfld.long 0x00 31. " DMA        ,DMA" "0: DMA is not supported,1: DMA is supported"
textline "                            "
bitfld.long 0x00 30. " INT        ,INT" "0: Interrupts are not supported,1: Interrupts are supported"
textline "                            "
bitfld.long 0x00 28.--29. " FIFORX     ,FIFO receive" "0: FIFO_2BYTE: 2 (or 3)-byte RX FIFO. the default FIFO receive value (FIFORX),1: FIFO_4BYTE: 4-byte RX FIFO,2: FIFO_8BYTE: 8-byte RX FIFO,3: FIFO_16BYTE: 16-byte RX FIFO"
textline "                            "
bitfld.long 0x00 26.--27. " FIFOTX     ,FIFO transmit" "0: FIFO_2BYTE: 2-byte TX FIFO. the default FIFO transmit value (FIFOTX),1: FIFO_4BYTE: 4-byte TX FIFO,2: FIFO_8BYTE: 8-byte TX FIFO,3: FIFO_16BYTE: 16-byte TX FIFO"
textline "                            "
bitfld.long 0x00 23.--25. " EXTFIFO    ,External FIFO" ",1: STD_EXT_FIFO: standard available/free external FIFO,,,,,,"
textline "                            "
bitfld.long 0x00 21. " TIMECTRL   ,Time control" "0: NO_TIME_CONTROL_TYPE: No time control is enabled,1: ATLEAST1_TIME_CONTROL: at least one time-control type is supported"
textline "                            "
bitfld.long 0x00 16.--20. " IBI_MR_HJ  ,In-Band Interrupts. Master Requests. Hot Join events" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 12.--15. " CCCHANDLE  ,Common Command Codes (CCC) handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 10.--11. " SADDR      ,Static address" "0: NO_STATIC: No static address,1: STATIC: Static address is fixed in hardware,2: HW_CONTROL: Hardware controls the static address dynamically (for example. from the pin strap),3: CONFIG: SCONFIG register supplies the static address"
textline "                            "
bitfld.long 0x00 9. " MASTER     ,Master" "0: MASTERNOTSUPPORTED: master capability is not supported,1: MASTERSUPPORTED: master capability is supported"
textline "                            "
bitfld.long 0x00 6.--8. " HDRSUPP    ,HDR support" "0,1,2,3,4,5,6,7"
textline "                            "
bitfld.long 0x00 2.--5. " IDREG      ,ID register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 0.--1. " IDENA      ,ID 48b handler" "0: APPLICATION: Application handles ID 48b,1: HW: Hardware handles ID 48b,2: HW_BUT: in hardware but the I3C module instance handles ID 48b,3: PARTNO: a part number register (PARTNO) handles ID 48b"
group.long 0x64++0x03
line.long 0x00 "SDYNADDR,Slave Dynamic Address Register"
hexmask.long.word 0x00 16.--31. 1. " KEY        ,Key"
textline "                            "
bitfld.long 0x00 12. " MAPSA      ,Map a Static Address" "0,1"
textline "                            "
bitfld.long 0x00 8.--11. " MAPIDX     ,Mapped Dynamic Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.byte 0x00 1.--7. 1. " DADDR      ,Dynamic address"
textline "                            "
bitfld.long 0x00 0. " DAVALID    ,DAVALID" "0: DANOTASSIGNED: a Dynamic Address is not assigned,1: DAASSIGNED: a Dynamic Address is assigned"
group.long 0x68++0x03
line.long 0x00 "SMAXLIMITS,Slave Maximum Limits Register"
hexmask.long.word 0x00 16.--27. 1. " MAXWR      ,Maximum write length"
textline "                            "
hexmask.long.word 0x00 0.--11. 1. " MAXRD      ,Maximum read length"
group.long 0x6C++0x03
line.long 0x00 "SIDPARTNO,Slave ID Part Number Register"
hexmask.long 0x00 0.--31. 1. " PARTNO     ,Part number"
group.long 0x70++0x03
line.long 0x00 "SIDEXT,Slave ID Extension Register"
hexmask.long.byte 0x00 16.--23. 1. " BCR        ,Bus Characteristics Register"
textline "                            "
hexmask.long.byte 0x00 8.--15. 1. " DCR        ,Device Characteristic Register"
group.long 0x74++0x03
line.long 0x00 "SVENDORID,Slave Vendor ID Register"
hexmask.long.word 0x00 0.--14. 1. " VID        ,Vendor ID"
group.long 0x78++0x03
line.long 0x00 "STCCLOCK,Slave Time Control Clock Register"
hexmask.long.byte 0x00 8.--15. 1. " FREQ       ,Clock frequency"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " ACCURACY   ,Clock accuracy"
rgroup.long 0x7C++0x03
line.long 0x00 "SMSGMAPADDR,Slave Message-Mapped Address Register"
bitfld.long 0x00 16.--19. " MAPLASTM2  ,Previous match index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 8.--11. " MAPLASTM1  ,Previous match index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
bitfld.long 0x00 0.--3. " MAPLAST    ,Matched address index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x84++0x03
line.long 0x00 "MCTRL,Master Main Control Register"
hexmask.long.byte 0x00 16.--23. 1. " RDTERM     ,Read terminate"
textline "                            "
hexmask.long.byte 0x00 9.--15. 1. " ADDR       ,ADDR"
textline "                            "
bitfld.long 0x00 8. " DIR        ,DIR" "0: DIRWRITE: Write,1: DIRREAD: Read"
textline "                            "
bitfld.long 0x00 6.--7. " IBIRESP    ,In-Band Interrupt (IBI) response" "0: ACK: Acknowledge,1: NACK: Not acknowledge,2: ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register),3: MANUAL: stop and wait for a decision using the IBIAckNack request"
textline "                            "
bitfld.long 0x00 4.--5. " TYPE       ,Bus type with START" "0: I3C: Normally the SDR mode of I3C,1: I2C: Normally the Standard I2C protocol,2: DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C,3: For ForcedExit. this is forced IBHR"
textline "                            "
bitfld.long 0x00 0.--2. " REQUEST    ,Request" "0: NONE: Returns to this when finished with any request,1: EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Sing..,2: EMITSTOP: Emit a STOP on bus,3: IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK),4: PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now. will issue START. 7E. ENTDAA. and t..,,6: FORCEEXIT and IBHR: Emit an Exit Pattern from any state. but end Double Data Rate (DDR) (including M..,7: AUTOIBI: Hold in a stopped state. but auto-emit START.7E when the slave is holding down SDA to get a.."
group.long 0x88++0x03
line.long 0x00 "MSTATUS,Master Status Register"
hexmask.long.byte 0x00 24.--30. 1. " IBIADDR    ,IBI address"
textline "                            "
bitfld.long 0x00 19. " NOWMASTER  ,Now master (now this module is a master)" "0,1"
textline "                            "
rbitfld.long 0x00 15. " ERRWARN    ,Error or warning" "0,1"
textline "                            "
bitfld.long 0x00 13. " IBIWON     ,In-Band Interrupt (IBI) won" "0,1"
textline "                            "
rbitfld.long 0x00 12. " TXNOTFULL  ,TX buffer/FIFO not yet full" "0,1"
textline "                            "
rbitfld.long 0x00 11. " RXPEND     ,RXPEND" "0,1"
textline "                            "
bitfld.long 0x00 10. " COMPLETE   ,COMPLETE" "0,1"
textline "                            "
bitfld.long 0x00 9. " MCTRLDONE  ,Master control done" "0,1"
textline "                            "
bitfld.long 0x00 8. " SLVSTART   ,Slave start" "0,1"
textline "                            "
rbitfld.long 0x00 6.--7. " IBITYPE    ,In-Band Interrupt (IBI) type" "0: NONE: cleared when IBI Won bit (MSTATUS,1: IBI: In-Band Interrupt,2: MR: Master Request,3: HJ: Hot-Join"
textline "                            "
rbitfld.long 0x00 5. " NACKED     ,Not acknowledged" "0,1"
textline "                            "
rbitfld.long 0x00 4. " BETWEEN    ,Between messages or Dynamic Address Assignments (DAA)" "0,1"
textline "                            "
rbitfld.long 0x00 0.--2. " STATE      ,State of the master" "0: IDLE: the bus has STOPped,1: SLVREQ: (Slave Request state) the bus has STOPped but a slave is holding SDA low,2: MSGSDR: in Single Data Rate (SDR) Message state (from using MWMSG_SDR),3: NORMACT: normal active Single Data Rate (SDR) state (from using MCTRL and MWDATAn and MRDATAn regist..,4: MSGDDR: in Double Data Rate (DDR) Message mode (from using MWMSG_DDR or using the normal method with..,5: DAA: in Enter Dynamic Address Assignment (ENTDAA) mode,6: IBIACK: waiting for an In-Band Interrupt (IBI) ACK/NACK decision,7: IBIRCV: Receiving an In-Band Interrupt (IBI). this IBIRCV state is used after IBI/MR/HJ has won the .."
group.long 0x8C++0x03
line.long 0x00 "MIBIRULES,Master In-band Interrupt Registry and Rules Register"
bitfld.long 0x00 31. " NOBYTE     ,No IBI byte" "0,1"
textline "                            "
bitfld.long 0x00 30. " MSB0       ,Set Most Significant address Bit to 0" "0,1"
textline "                            "
bitfld.long 0x00 24.--29. " ADDR4      ,ADDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                            "
bitfld.long 0x00 18.--23. " ADDR3      ,ADDR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                            "
bitfld.long 0x00 12.--17. " ADDR2      ,ADDR2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                            "
bitfld.long 0x00 6.--11. " ADDR1      ,ADDR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                            "
bitfld.long 0x00 0.--5. " ADDR0      ,ADDR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x90++0x03
line.long 0x00 "MINTSET,Master Interrupt Set Register"
bitfld.long 0x00 19. " NOWMASTER  ,Now master (now this I3C module is a master) interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 15. " ERRWARN    ,Error or warning (ERRWARN) interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 13. " IBIWON     ,In-Band Interrupt (IBI) won interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 12. " TXNOTFULL  ,TX buffer/FIFO is not full interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 11. " RXPEND     ,RX pending interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 10. " COMPLETE   ,Completed message interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 9. " MCTRLDONE  ,Master control done interrupt enable" "0,1"
textline "                            "
bitfld.long 0x00 8. " SLVSTART   ,Slave start interrupt enable" "0,1"
group.long 0x94++0x03
line.long 0x00 "MINTCLR,Master Interrupt Clear Register"
bitfld.long 0x00 19. " NOWMASTER  ,NOWMASTER interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 15. " ERRWARN    ,ERRWARN interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 13. " IBIWON     ,IBIWON interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 12. " TXNOTFULL  ,TXNOTFULL interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 11. " RXPEND     ,RXPEND interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 10. " COMPLETE   ,COMPLETE interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 9. " MCTRLDONE  ,MCTRLDONE interrupt enable clear" "0,1"
textline "                            "
bitfld.long 0x00 8. " SLVSTART   ,SLVSTART interrupt enable clear" "0,1"
rgroup.long 0x98++0x03
line.long 0x00 "MINTMASKED,Master Interrupt Mask Register"
bitfld.long 0x00 19. " NOWMASTER  ,NOWMASTER interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 15. " ERRWARN    ,ERRWARN interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 13. " IBIWON     ,IBIWON interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 12. " TXNOTFULL  ,TXNOTFULL interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 11. " RXPEND     ,RXPEND interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 10. " COMPLETE   ,COMPLETE interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 9. " MCTRLDONE  ,MCTRLDONE interrupt mask" "0,1"
textline "                            "
bitfld.long 0x00 8. " SLVSTART   ,SLVSTART interrupt mask" "0,1"
group.long 0x9C++0x03
line.long 0x00 "MERRWARN,Master Errors and Warnings Register"
bitfld.long 0x00 20. " TIMEOUT    ,TIMEOUT error" "0,1"
textline "                            "
bitfld.long 0x00 19. " INVREQ     ,Invalid request error" "0,1"
textline "                            "
bitfld.long 0x00 18. " MSGERR     ,Message error" "0,1"
textline "                            "
bitfld.long 0x00 17. " OWRITE     ,Over-write error" "0,1"
textline "                            "
bitfld.long 0x00 16. " OREAD      ,Over-read error" "0,1"
textline "                            "
bitfld.long 0x00 10. " HCRC       ,High data rate CRC error" "0,1"
textline "                            "
bitfld.long 0x00 9. " HPAR       ,High data rate parity" "0,1"
textline "                            "
bitfld.long 0x00 4. " TERM       ,Terminate error" "0,1"
textline "                            "
bitfld.long 0x00 3. " WRABT      ,WRABT (Write abort) error" "0,1"
textline "                            "
bitfld.long 0x00 2. " NACK       ,Not acknowledge (NACK) error" "0,1"
group.long 0xA0++0x03
line.long 0x00 "MDMACTRL,Master DMA Control Register"
bitfld.long 0x00 4.--5. " DMAWIDTH   ,DMA width" "0: BYTE,1: BYTE_AGAIN,2: HALF_WORD: Half-word (16 bits),"
textline "                            "
bitfld.long 0x00 2.--3. " DMATB      ,DMA to bus" "0: NOT_USED: DMA is not used,1: ENABLE_ONE_FRAME: DMA is enabled for 1 frame (ended by DMA or Terminated),2: ENABLE: DMA is enabled until DMA is turned off,"
textline "                            "
bitfld.long 0x00 0.--1. " DMAFB      ,DMA from bus" "0: NOT_USED: DMA is not used,1: ENABLE_ONE_FRAME: DMA is enabled for 1 frame,2: ENABLE: DMA is enabled until the DMA is turned off,"
group.long 0xAC++0x03
line.long 0x00 "MDATACTRL,Master Data Control Register"
rbitfld.long 0x00 31. " RXEMPTY    ,RX is empty" "0,1"
textline "                            "
rbitfld.long 0x00 30. " TXFULL     ,TX is full" "0,1"
textline "                            "
rbitfld.long 0x00 24.--28. " RXCOUNT    ,RX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
rbitfld.long 0x00 16.--20. " TXCOUNT    ,TX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 6.--7. " RXTRIG     ,RX trigger level" "0,1,2,3"
textline "                            "
bitfld.long 0x00 4.--5. " TXTRIG     ,TX trigger level" "0,1,2,3"
textline "                            "
bitfld.long 0x00 2. " UNLOCK     ,Unlock" "0,1"
textline "                            "
bitfld.long 0x00 1. " FLUSHFB    ,Flush from-bus buffer/FIFO" "0,1"
textline "                            "
bitfld.long 0x00 0. " FLUSHTB    ,Flush to-bus buffer/FIFO" "0,1"
group.long 0xB0++0x03
line.long 0x00 "MWDATAB,Master Write Data Byte Register"
bitfld.long 0x00 16. " END_ALSO   ,End of message also" "0,1"
textline "                            "
bitfld.long 0x00 8. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA       ,Data byte"
group.long 0xB4++0x03
line.long 0x00 "MWDATABE,Master Write Data Byte End Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA       ,Data"
group.long 0xB8++0x03
line.long 0x00 "MWDATAH,Master Write Data Half-word Register"
bitfld.long 0x00 16. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.byte 0x00 8.--15. 1. " DATA1      ,Data byte 1"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA0      ,Data byte 0"
group.long 0xBC++0x03
line.long 0x00 "MWDATAHE,Master Write Data Byte End Register"
hexmask.long.byte 0x00 8.--15. 1. " DATA1      ,DATA 1"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " DATA0      ,DATA 0"
rgroup.long 0xC0++0x03
line.long 0x00 "MRDATAB,Master Read Data Byte Register"
hexmask.long.byte 0x00 0.--7. 1. " VALUE      ,VALUE"
rgroup.long 0xC8++0x03
line.long 0x00 "MRDATAH,Master Read Data Half-word Register"
hexmask.long.byte 0x00 8.--15. 1. " MSB        ,MSB"
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " LSB        ,LSB"
group.long 0xD0++0x03
line.long 0x00 "MWMSG_SDR_CONTROL,Master Write Message in SDR mode"
bitfld.long 0x00 11.--15. " LEN        ,Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 10. " I2C        ,I2C" "0: I3C message,1: I2C message"
textline "                            "
bitfld.long 0x00 8. " END        ,End of SDR message" "0,1"
textline "                            "
hexmask.long.byte 0x00 1.--7. 1. " ADDR       ,Address to be written to"
textline "                            "
bitfld.long 0x00 0. " DIR        ,Direction" "0: WRITE,1: READ"
group.long 0xD0++0x03
line.long 0x00 "MWMSG_SDR_DATA,Master Write Message Data in SDR mode"
bitfld.long 0x00 16. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.word 0x00 0.--15. 1. " DATA16B    ,Data"
rgroup.long 0xD4++0x03
line.long 0x00 "MRMSG_SDR,Master Read Message in SDR mode"
hexmask.long.word 0x00 0.--15. 1. " DATA       ,Data"
group.long 0xD8++0x03
line.long 0x00 "MWMSG_DDR_CONTROL,Master Write Message in DDR mode"
bitfld.long 0x00 14. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " LEN        ,Length of message"
group.long 0xD8++0x03
line.long 0x00 "MWMSG_DDR_DATA,Master Write Message Data in DDR mode"
bitfld.long 0x00 16. " END        ,End of message" "0,1"
textline "                            "
hexmask.long.word 0x00 0.--15. 1. " DATA16B    ,Data"
group.long 0xDC++0x03
line.long 0x00 "MRMSG_DDR,Master Read Message in DDR mode"
hexmask.long.word 0x00 16.--25. 1. " CLEN       ,Current length"
textline "                            "
hexmask.long.word 0x00 0.--15. 1. " DATA       ,Data"
group.long 0xE4++0x03
line.long 0x00 "MDYNADDR,Master Dynamic Address Register"
hexmask.long.byte 0x00 1.--7. 1. " DADDR      ,Dynamic address"
textline "                            "
bitfld.long 0x00 0. " DAVALID    ,Dynamic address valid" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "SID,Slave Module ID Register"
hexmask.long 0x00 0.--31. 1. " ID         ,ID"
width 0x0B
tree.end
tree "INPUTMUX"
base ad:0x40026000
width 22.
group.long 0x00++0x03
line.long 0x00 "SCT0_IN_SEL0,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x04++0x03
line.long 0x00 "SCT0_IN_SEL1,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x08++0x03
line.long 0x00 "SCT0_IN_SEL2,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x0C++0x03
line.long 0x00 "SCT0_IN_SEL3,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x10++0x03
line.long 0x00 "SCT0_IN_SEL4,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x14++0x03
line.long 0x00 "SCT0_IN_SEL5,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x18++0x03
line.long 0x00 "SCT0_IN_SEL6,SCT Peripheral Input Multiplexers N"
bitfld.long 0x00 0.--4. " SCT_IN_SEL          ,SCT0 Input(n) Selection" "0: SCT0_PIN_INP0,1: SCT0_PIN_INP1,2: SCT0_PIN_INP2,3: SCT0_PIN_INP3,4: SCT0_PIN_INP4,5: SCT0_PIN_INP5,6: SCT0_PIN_INP6,7: SCT0_PIN_INP7,8: CT32BIT0_MAT0,9: CT32BIT1_MAT0,10: CT32BIT2_MAT0,11: CT32BIT3_MAT0,12: CT32BIT4_MAT0,13: ADCIRQ,14: GPIOINT_BMATCH,15: USB1_FRAME_TOGGLE,16: CMP0_OUT,17: SHARED_I2S0_SCLK,18: SHARED_I2S1_SCLK,19: SHARED_I2S0_WS,20: SHARED_I2S1_WS,21: MCLK,22: ARM_TXEV,23: DEBUG_HALTED,,,,,,,,"
group.long 0x100++0x03
line.long 0x00 "PINT_SEL0,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x104++0x03
line.long 0x00 "PINT_SEL1,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x108++0x03
line.long 0x00 "PINT_SEL2,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x10C++0x03
line.long 0x00 "PINT_SEL3,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x110++0x03
line.long 0x00 "PINT_SEL4,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x114++0x03
line.long 0x00 "PINT_SEL5,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x118++0x03
line.long 0x00 "PINT_SEL6,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x11C++0x03
line.long 0x00 "PINT_SEL7,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x00 0.--7. 1. " PINT_SEL            ,Port Input (PIOx"
group.long 0x140++0x03
line.long 0x00 "DSP_INT_SEL[0],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x144++0x03
line.long 0x00 "DSP_INT_SEL[1],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x148++0x03
line.long 0x00 "DSP_INT_SEL[2],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x14C++0x03
line.long 0x00 "DSP_INT_SEL[3],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x150++0x03
line.long 0x00 "DSP_INT_SEL[4],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x154++0x03
line.long 0x00 "DSP_INT_SEL[5],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x158++0x03
line.long 0x00 "DSP_INT_SEL[6],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x15C++0x03
line.long 0x00 "DSP_INT_SEL[7],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x160++0x03
line.long 0x00 "DSP_INT_SEL[8],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x164++0x03
line.long 0x00 "DSP_INT_SEL[9],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x168++0x03
line.long 0x00 "DSP_INT_SEL[10],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x16C++0x03
line.long 0x00 "DSP_INT_SEL[11],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x170++0x03
line.long 0x00 "DSP_INT_SEL[12],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x174++0x03
line.long 0x00 "DSP_INT_SEL[13],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x178++0x03
line.long 0x00 "DSP_INT_SEL[14],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x17C++0x03
line.long 0x00 "DSP_INT_SEL[15],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x180++0x03
line.long 0x00 "DSP_INT_SEL[16],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x184++0x03
line.long 0x00 "DSP_INT_SEL[17],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x188++0x03
line.long 0x00 "DSP_INT_SEL[18],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x18C++0x03
line.long 0x00 "DSP_INT_SEL[19],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x190++0x03
line.long 0x00 "DSP_INT_SEL[20],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x194++0x03
line.long 0x00 "DSP_INT_SEL[21],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x198++0x03
line.long 0x00 "DSP_INT_SEL[22],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x19C++0x03
line.long 0x00 "DSP_INT_SEL[23],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x1A0++0x03
line.long 0x00 "DSP_INT_SEL[24],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x1A4++0x03
line.long 0x00 "DSP_INT_SEL[25],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x1A8++0x03
line.long 0x00 "DSP_INT_SEL[26],DSP Interrupt Input Multiplexers N"
bitfld.long 0x00 0.--5. " DSP_INT_SEL         ,DSP Input(n) Selection" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7,8: GPIO_INT0_IRQ0,9: GPIO_INT0_IRQ1,10: GPIO_INT0_IRQ2,11: GPIO_INT0_IRQ3,12: GPIO_INT0_IRQ4,13: GPIO_INT0_IRQ5,14: GPIO_INT0_IRQ6,15: GPIO_INT0_IRQ7,16: NSHSGPIO_INT0,17: NSHSGPIO_INT1,18: WDT1,19: DMAC0,20: DMAC1,21: MU,22: UTICK0,23: MRT0,24: OS_EVENT_TIMER_or_OS_EVENT_WAKEUP,25: CT32BIT0,26: CT32BIT1,27: CT32BIT2,28: CT32BIT3,29: CT32BIT4,30: RTC_LITE0_ALARM_or_RTC_LITE0_WAKEUP,31: I3C0,32: DMIC0,33: HWVAD0,34: FLEXSPI,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x200++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[0],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x204++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[1],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x208++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[2],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x20C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[3],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x210++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[4],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x214++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[5],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x218++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[6],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x21C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[7],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x220++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[8],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x224++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[9],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x228++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[10],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x22C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[11],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x230++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[12],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x234++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[13],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x238++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[14],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x23C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[15],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x240++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[16],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x244++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[17],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x248++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[18],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x24C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[19],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x250++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[20],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x254++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[21],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x258++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[22],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x25C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[23],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x260++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[24],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x264++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[25],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x268++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[26],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x26C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[27],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x270++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[28],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x274++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[29],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x278++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[30],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x27C++0x03
line.long 0x00 "DMAC0_ITRIG_SEL[31],DMAC0 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA0_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC0_TRIGOUT_A,15: DMAC0_TRIGOUT_B,16: DMAC0_TRIGOUT_C,17: DMAC0_TRIGOUT_D,18: SCT0_DMA0,19: SCT0_DMA1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x300++0x03
line.long 0x00 "DMAC0_OTRIG_SEL0,DMAC0 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC0_OTRIG_SEL     ,DMAC0 Output Triggers Select for A. B. C. D IE" "0: DMAC0_OTRIG_CH0,1: DMAC0_OTRIG_CH1,2: DMAC0_OTRIG_CH2,3: DMAC0_OTRIG_CH3,4: DMAC0_OTRIG_CH4,5: DMAC0_OTRIG_CH5,6: DMAC0_OTRIG_CH6,7: DMAC0_OTRIG_CH7,8: DMAC0_OTRIG_CH8,9: DMAC0_OTRIG_CH9,10: DMAC0_OTRIG_CH10,11: DMAC0_OTRIG_CH11,12: DMAC0_OTRIG_CH12,13: DMAC0_OTRIG_CH13,14: DMAC0_OTRIG_CH14,15: DMAC0_OTRIG_CH15,16: DMAC0_OTRIG_CH16,17: DMAC0_OTRIG_CH17,18: DMAC0_OTRIG_CH18,19: DMAC0_OTRIG_CH19,20: DMAC0_OTRIG_CH20,21: DMAC0_OTRIG_CH21,22: DMAC0_OTRIG_CH22,23: DMAC0_OTRIG_CH23,24: DMAC0_OTRIG_CH24,25: DMAC0_OTRIG_CH25,26: DMAC0_OTRIG_CH26,27: DMAC0_OTRIG_CH27,28: DMAC0_OTRIG_CH28,29: DMAC0_OTRIG_CH29,30: DMAC0_OTRIG_CH30,31: DMAC0_OTRIG_CH31"
group.long 0x304++0x03
line.long 0x00 "DMAC0_OTRIG_SEL1,DMAC0 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC0_OTRIG_SEL     ,DMAC0 Output Triggers Select for A. B. C. D IE" "0: DMAC0_OTRIG_CH0,1: DMAC0_OTRIG_CH1,2: DMAC0_OTRIG_CH2,3: DMAC0_OTRIG_CH3,4: DMAC0_OTRIG_CH4,5: DMAC0_OTRIG_CH5,6: DMAC0_OTRIG_CH6,7: DMAC0_OTRIG_CH7,8: DMAC0_OTRIG_CH8,9: DMAC0_OTRIG_CH9,10: DMAC0_OTRIG_CH10,11: DMAC0_OTRIG_CH11,12: DMAC0_OTRIG_CH12,13: DMAC0_OTRIG_CH13,14: DMAC0_OTRIG_CH14,15: DMAC0_OTRIG_CH15,16: DMAC0_OTRIG_CH16,17: DMAC0_OTRIG_CH17,18: DMAC0_OTRIG_CH18,19: DMAC0_OTRIG_CH19,20: DMAC0_OTRIG_CH20,21: DMAC0_OTRIG_CH21,22: DMAC0_OTRIG_CH22,23: DMAC0_OTRIG_CH23,24: DMAC0_OTRIG_CH24,25: DMAC0_OTRIG_CH25,26: DMAC0_OTRIG_CH26,27: DMAC0_OTRIG_CH27,28: DMAC0_OTRIG_CH28,29: DMAC0_OTRIG_CH29,30: DMAC0_OTRIG_CH30,31: DMAC0_OTRIG_CH31"
group.long 0x308++0x03
line.long 0x00 "DMAC0_OTRIG_SEL2,DMAC0 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC0_OTRIG_SEL     ,DMAC0 Output Triggers Select for A. B. C. D IE" "0: DMAC0_OTRIG_CH0,1: DMAC0_OTRIG_CH1,2: DMAC0_OTRIG_CH2,3: DMAC0_OTRIG_CH3,4: DMAC0_OTRIG_CH4,5: DMAC0_OTRIG_CH5,6: DMAC0_OTRIG_CH6,7: DMAC0_OTRIG_CH7,8: DMAC0_OTRIG_CH8,9: DMAC0_OTRIG_CH9,10: DMAC0_OTRIG_CH10,11: DMAC0_OTRIG_CH11,12: DMAC0_OTRIG_CH12,13: DMAC0_OTRIG_CH13,14: DMAC0_OTRIG_CH14,15: DMAC0_OTRIG_CH15,16: DMAC0_OTRIG_CH16,17: DMAC0_OTRIG_CH17,18: DMAC0_OTRIG_CH18,19: DMAC0_OTRIG_CH19,20: DMAC0_OTRIG_CH20,21: DMAC0_OTRIG_CH21,22: DMAC0_OTRIG_CH22,23: DMAC0_OTRIG_CH23,24: DMAC0_OTRIG_CH24,25: DMAC0_OTRIG_CH25,26: DMAC0_OTRIG_CH26,27: DMAC0_OTRIG_CH27,28: DMAC0_OTRIG_CH28,29: DMAC0_OTRIG_CH29,30: DMAC0_OTRIG_CH30,31: DMAC0_OTRIG_CH31"
group.long 0x30C++0x03
line.long 0x00 "DMAC0_OTRIG_SEL3,DMAC0 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC0_OTRIG_SEL     ,DMAC0 Output Triggers Select for A. B. C. D IE" "0: DMAC0_OTRIG_CH0,1: DMAC0_OTRIG_CH1,2: DMAC0_OTRIG_CH2,3: DMAC0_OTRIG_CH3,4: DMAC0_OTRIG_CH4,5: DMAC0_OTRIG_CH5,6: DMAC0_OTRIG_CH6,7: DMAC0_OTRIG_CH7,8: DMAC0_OTRIG_CH8,9: DMAC0_OTRIG_CH9,10: DMAC0_OTRIG_CH10,11: DMAC0_OTRIG_CH11,12: DMAC0_OTRIG_CH12,13: DMAC0_OTRIG_CH13,14: DMAC0_OTRIG_CH14,15: DMAC0_OTRIG_CH15,16: DMAC0_OTRIG_CH16,17: DMAC0_OTRIG_CH17,18: DMAC0_OTRIG_CH18,19: DMAC0_OTRIG_CH19,20: DMAC0_OTRIG_CH20,21: DMAC0_OTRIG_CH21,22: DMAC0_OTRIG_CH22,23: DMAC0_OTRIG_CH23,24: DMAC0_OTRIG_CH24,25: DMAC0_OTRIG_CH25,26: DMAC0_OTRIG_CH26,27: DMAC0_OTRIG_CH27,28: DMAC0_OTRIG_CH28,29: DMAC0_OTRIG_CH29,30: DMAC0_OTRIG_CH30,31: DMAC0_OTRIG_CH31"
group.long 0x400++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[0],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x404++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[1],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x408++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[2],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x40C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[3],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x410++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[4],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x414++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[5],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x418++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[6],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x41C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[7],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x420++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[8],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x424++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[9],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x428++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[10],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x42C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[11],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x430++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[12],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x434++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[13],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x438++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[14],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x43C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[15],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x440++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[16],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x444++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[17],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x448++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[18],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x44C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[19],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x450++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[20],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x454++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[21],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x458++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[22],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x45C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[23],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x460++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[24],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x464++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[25],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x468++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[26],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x46C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[27],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x470++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[28],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x474++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[29],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x478++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[30],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x47C++0x03
line.long 0x00 "DMAC1_ITRIG_SEL[31],DMAC1 Input Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMA1_ITRIG_SEL      ,DMA Input Triggers(n) Selection" "0: NSGPIOPINT0_INT0,1: NSGPIOPINT0_INT1,2: NSGPIOPINT0_INT2,3: NSGPIOPINT0_INT3,4: CT32BIT0_DMAREQ_M0,5: CT32BIT0_DMAREQ_M1,6: CT32BIT1_DMAREQ_M0,7: CT32BIT1_DMAREQ_M1,8: CT32BIT2_DMAREQ_M0,9: CT32BIT2_DMAREQ_M1,10: CT32BIT3_DMAREQ_M0,11: CT32BIT3_DMAREQ_M1,12: CT32BIT4_DMAREQ_M0,13: CT32BIT4_DMAREQ_M1,14: DMAC1_TRIGOUT_A,15: DMAC1_TRIGOUT_B,16: DMAC1_TRIGOUT_C,17: DMAC1_TRIGOUT_D,18: SCT0_DMAC0,19: SCT0_DMAC1,20: HASHCRYPT_OUT_DMA,21: ACMP_DMA,,,24: ADC_DMAC,,,,28: FLEXSPI_RX,29: FLEXSPI_TX,,"
group.long 0x500++0x03
line.long 0x00 "DMAC1_OTRIG_SEL0,DMAC1 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC1_OTRIG_SEL     ,DMA1 Output Triggers Select for A. B. C. D IE" "0: DMAC1_OTRIG_CH0,1: DMAC1_OTRIG_CH1,2: DMAC1_OTRIG_CH2,3: DMAC1_OTRIG_CH3,4: DMAC1_OTRIG_CH4,5: DMAC1_OTRIG_CH5,6: DMAC1_OTRIG_CH6,7: DMAC1_OTRIG_CH7,8: DMAC1_OTRIG_CH8,9: DMAC1_OTRIG_CH9,10: DMAC1_OTRIG_CH10,11: DMAC1_OTRIG_CH11,12: DMAC1_OTRIG_CH12,13: DMAC1_OTRIG_CH13,14: DMAC1_OTRIG_CH14,15: DMAC1_OTRIG_CH15,16: DMAC1_OTRIG_CH16,17: DMAC1_OTRIG_CH17,18: DMAC1_OTRIG_CH18,19: DMAC1_OTRIG_CH19,20: DMAC1_OTRIG_CH20,21: DMAC1_OTRIG_CH21,22: DMAC1_OTRIG_CH22,23: DMAC1_OTRIG_CH23,24: DMAC1_OTRIG_CH24,25: DMAC1_OTRIG_CH25,26: DMAC1_OTRIG_CH26,27: DMAC1_OTRIG_CH27,28: DMAC1_OTRIG_CH28,29: DMAC1_OTRIG_CH29,30: DMAC1_OTRIG_CH30,31: DMAC1_OTRIG_CH31"
group.long 0x504++0x03
line.long 0x00 "DMAC1_OTRIG_SEL1,DMAC1 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC1_OTRIG_SEL     ,DMA1 Output Triggers Select for A. B. C. D IE" "0: DMAC1_OTRIG_CH0,1: DMAC1_OTRIG_CH1,2: DMAC1_OTRIG_CH2,3: DMAC1_OTRIG_CH3,4: DMAC1_OTRIG_CH4,5: DMAC1_OTRIG_CH5,6: DMAC1_OTRIG_CH6,7: DMAC1_OTRIG_CH7,8: DMAC1_OTRIG_CH8,9: DMAC1_OTRIG_CH9,10: DMAC1_OTRIG_CH10,11: DMAC1_OTRIG_CH11,12: DMAC1_OTRIG_CH12,13: DMAC1_OTRIG_CH13,14: DMAC1_OTRIG_CH14,15: DMAC1_OTRIG_CH15,16: DMAC1_OTRIG_CH16,17: DMAC1_OTRIG_CH17,18: DMAC1_OTRIG_CH18,19: DMAC1_OTRIG_CH19,20: DMAC1_OTRIG_CH20,21: DMAC1_OTRIG_CH21,22: DMAC1_OTRIG_CH22,23: DMAC1_OTRIG_CH23,24: DMAC1_OTRIG_CH24,25: DMAC1_OTRIG_CH25,26: DMAC1_OTRIG_CH26,27: DMAC1_OTRIG_CH27,28: DMAC1_OTRIG_CH28,29: DMAC1_OTRIG_CH29,30: DMAC1_OTRIG_CH30,31: DMAC1_OTRIG_CH31"
group.long 0x508++0x03
line.long 0x00 "DMAC1_OTRIG_SEL2,DMAC1 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC1_OTRIG_SEL     ,DMA1 Output Triggers Select for A. B. C. D IE" "0: DMAC1_OTRIG_CH0,1: DMAC1_OTRIG_CH1,2: DMAC1_OTRIG_CH2,3: DMAC1_OTRIG_CH3,4: DMAC1_OTRIG_CH4,5: DMAC1_OTRIG_CH5,6: DMAC1_OTRIG_CH6,7: DMAC1_OTRIG_CH7,8: DMAC1_OTRIG_CH8,9: DMAC1_OTRIG_CH9,10: DMAC1_OTRIG_CH10,11: DMAC1_OTRIG_CH11,12: DMAC1_OTRIG_CH12,13: DMAC1_OTRIG_CH13,14: DMAC1_OTRIG_CH14,15: DMAC1_OTRIG_CH15,16: DMAC1_OTRIG_CH16,17: DMAC1_OTRIG_CH17,18: DMAC1_OTRIG_CH18,19: DMAC1_OTRIG_CH19,20: DMAC1_OTRIG_CH20,21: DMAC1_OTRIG_CH21,22: DMAC1_OTRIG_CH22,23: DMAC1_OTRIG_CH23,24: DMAC1_OTRIG_CH24,25: DMAC1_OTRIG_CH25,26: DMAC1_OTRIG_CH26,27: DMAC1_OTRIG_CH27,28: DMAC1_OTRIG_CH28,29: DMAC1_OTRIG_CH29,30: DMAC1_OTRIG_CH30,31: DMAC1_OTRIG_CH31"
group.long 0x50C++0x03
line.long 0x00 "DMAC1_OTRIG_SEL3,DMAC1 Output Trigger Multiplexers N"
bitfld.long 0x00 0.--4. " DMAC1_OTRIG_SEL     ,DMA1 Output Triggers Select for A. B. C. D IE" "0: DMAC1_OTRIG_CH0,1: DMAC1_OTRIG_CH1,2: DMAC1_OTRIG_CH2,3: DMAC1_OTRIG_CH3,4: DMAC1_OTRIG_CH4,5: DMAC1_OTRIG_CH5,6: DMAC1_OTRIG_CH6,7: DMAC1_OTRIG_CH7,8: DMAC1_OTRIG_CH8,9: DMAC1_OTRIG_CH9,10: DMAC1_OTRIG_CH10,11: DMAC1_OTRIG_CH11,12: DMAC1_OTRIG_CH12,13: DMAC1_OTRIG_CH13,14: DMAC1_OTRIG_CH14,15: DMAC1_OTRIG_CH15,16: DMAC1_OTRIG_CH16,17: DMAC1_OTRIG_CH17,18: DMAC1_OTRIG_CH18,19: DMAC1_OTRIG_CH19,20: DMAC1_OTRIG_CH20,21: DMAC1_OTRIG_CH21,22: DMAC1_OTRIG_CH22,23: DMAC1_OTRIG_CH23,24: DMAC1_OTRIG_CH24,25: DMAC1_OTRIG_CH25,26: DMAC1_OTRIG_CH26,27: DMAC1_OTRIG_CH27,28: DMAC1_OTRIG_CH28,29: DMAC1_OTRIG_CH29,30: DMAC1_OTRIG_CH30,31: DMAC1_OTRIG_CH31"
group.long 0x700++0x03
line.long 0x00 "FMEASURE_CH_SEL0,Frequency Measurement Input Channel Multiplexers"
bitfld.long 0x00 0.--4. " FMEASURE_SEL        ,Frequency Measure Channel n Selection 7:1 Mux Select" "0: XTALIN,1: SFRO,2: FFRO,3: Low Power Oscillator Clock (LPOSC),4: RTC_32KHz_OSC,5: MAIN_SYS_CLOCK,6: FREQME_GPIO_CLK,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x704++0x03
line.long 0x00 "FMEASURE_CH_SEL1,Frequency Measurement Input Channel Multiplexers"
bitfld.long 0x00 0.--4. " FMEASURE_SEL        ,Frequency Measure Channel n Selection 7:1 Mux Select" "0: XTALIN,1: SFRO,2: FFRO,3: Low Power Oscillator Clock (LPOSC),4: RTC_32KHz_OSC,5: MAIN_SYS_CLOCK,6: FREQME_GPIO_CLK,,,,,,,,,,,,,,,,,,,,,,,,,"
group.long 0x740++0x03
line.long 0x00 "DMAC0_REQ_ENA0,DMAC0 request enable 0"
bitfld.long 0x00 30. " HASHCRYPT           ,hash enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM14 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable" "0: DISABLED,1: ENABLED"
group.long 0x748++0x03
line.long 0x00 "DMAC0_REQ_ENA0_SET,DMAC0 request enable set 0"
bitfld.long 0x00 30. " HASHCRYPT           ,Hash enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM15 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
group.long 0x750++0x03
line.long 0x00 "DMAC0_REQ_ENA0_CLR,DMAC0 request enable clear 0"
bitfld.long 0x00 30. " HASHCRYPT           ,Hash enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM14 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
group.long 0x760++0x03
line.long 0x00 "DMAC1_REQ_ENA0,DMAC1 request enable 0"
bitfld.long 0x00 30. " HASHCRYPT           ,hash enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM14 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable" "0: DISABLED,1: ENABLED"
group.long 0x768++0x03
line.long 0x00 "DMAC1_REQ_ENA0_SET,DMAC1 request enable set 0"
bitfld.long 0x00 30. " HASHCRYPT           ,Hash enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM15 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
group.long 0x770++0x03
line.long 0x00 "DMAC1_REQ_ENA0_CLR,DMAC1 request enable clear 0"
bitfld.long 0x00 30. " HASHCRYPT           ,Hash enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " FLEXSPI_TX          ,FLEXSPI TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " FLEXSPI_RX          ,FLEXSPI RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " FLEXCOMM14_TX       ,FLEXCOMM14 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " FLEXCOMM14_RX       ,FLEXCOMM14 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " I3C0_TX             ,I3C TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " I3C0_RX             ,I3C RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMIC0CH7            ,DMIC0 channel 7 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMIC0CH6            ,DMIC0 channel 6 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMIC0CH5            ,DMIC0 channel 5 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMIC0CH4            ,DMIC0 channel 4 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMIC0CH3            ,DMIC0 channel 3 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMIC0CH2            ,DMIC0 channel 2 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMIC0CH1            ,DMIC0 channel 1 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMIC0CH0            ,DMIC0 channel 0 enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " FLEXCOMM7_TX        ,FLEXCOMM7 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " FLEXCOMM7_RX        ,FLEXCOMM7 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " FLEXCOMM6_TX        ,FLEXCOMM6 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " FLEXCOMM6_RX        ,FLEXCOMM6 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " FLEXCOMM5_TX        ,FLEXCOMM5 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " FLEXCOMM5_RX        ,FLEXCOMM5 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " FLEXCOMM4_TX        ,FLEXCOMM4 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " FLEXCOMM4_RX        ,FLEXCOMM4 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " FLEXCOMM3_TX        ,FLEXCOMM3 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " FLEXCOMM3_RX        ,FLEXCOMM3 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " FLEXCOMM2_TX        ,FLEXCOMM2 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " FLEXCOMM2_RX        ,FLEXCOMM2 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " FLEXCOMM1_TX        ,FLEXCOMM1 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " FLEXCOMM1_RX        ,FLEXCOMM1 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 1. " FLEXCOMM0_TX        ,FLEXCOMM0 TX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " FLEXCOMM0_RX        ,FLEXCOMM0 RX enable clear" "0: NO_EFFECT,1: Clears the ENA0 Bit"
group.long 0x780++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0,DMAC0 input trigger enable 0"
bitfld.long 0x00 31. " DMAC0_ITRIG_INMUX31 ,DMAC0 input trigger inmux 31 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 30. " DMAC0_ITRIG_INMUX30 ,DMAC0 input trigger inmux 30 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 29. " DMAC0_ITRIG_INMUX29 ,DMAC0 input trigger inmux 29 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 28. " DMAC0_ITRIG_INMUX28 ,DMAC0 input trigger inmux 28 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 27. " DMAC0_ITRIG_INMUX27 ,DMAC0 input trigger inmux 27 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 26. " DMAC0_ITRIG_INMUX26 ,DMAC0 input trigger inmux 26 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 25. " DMAC0_ITRIG_INMUX25 ,DMAC0 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 24. " DMAC0_ITRIG_INMUX24 ,DMAC0 input trigger inmux 24 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 23. " DMAC0_ITRIG_INMUX23 ,DMAC0 input trigger inmux 23 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 22. " DMAC0_ITRIG_INMUX22 ,DMAC0 input trigger inmux 22 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 21. " DMAC0_ITRIG_INMUX21 ,DMAC0 input trigger inmux 21 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 20. " DMAC0_ITRIG_INMUX20 ,DMAC0 input trigger inmux 20 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 19. " DMAC0_ITRIG_INMUX19 ,DMAC0 input trigger inmux 19 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 18. " DMAC0_ITRIG_INMUX18 ,DMAC0 input trigger inmux 18 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 17. " DMAC0_ITRIG_INMUX17 ,DMAC0 input trigger inmux 17 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 16. " DMAC0_ITRIG_INMUX16 ,DMAC0 input trigger inmux 16 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 15. " DMAC0_ITRIG_INMUX15 ,DMAC0 input trigger inmux 15 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 14. " DMAC0_ITRIG_INMUX14 ,DMAC0 input trigger inmux 14 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 13. " DMAC0_ITRIG_INMUX13 ,DMAC0 input trigger inmux 13 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 12. " DMAC0_ITRIG_INMUX12 ,DMAC0 input trigger inmux 12 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 11. " DMAC0_ITRIG_INMUX11 ,DMAC0 input trigger inmux 11 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 10. " DMAC0_ITRIG_INMUX10 ,DMAC0 input trigger inmux 10 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 9. " DMAC0_ITRIG_INMUX9  ,DMAC0 input trigger inmux 9 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 8. " DMAC0_ITRIG_INMUX8  ,DMAC0 input trigger inmux 8 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 7. " DMAC0_ITRIG_INMUX7  ,DMAC0 input trigger inmux 7 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 6. " DMAC0_ITRIG_INMUX6  ,DMAC0 input trigger inmux 6 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 5. " DMAC0_ITRIG_INMUX5  ,DMAC0 input trigger inmux 5 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 4. " DMAC0_ITRIG_INMUX4  ,DMAC0 input trigger inmux 4 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 3. " DMAC0_ITRIG_INMUX3  ,DMAC0 input trigger inmux 3 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 2. " DMAC0_ITRIG_INMUX2  ,DMAC0 input trigger inmux 2 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 1. " DMAC0_ITRIG_INMUX1  ,DMAC0 input trigger inmux 1 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 0. " DMAC0_ITRIG_INMUX0  ,DMAC0 input trigger inmux 0 enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x788++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0_SET,DMAC0 input trigger enable set 0"
bitfld.long 0x00 31. " DMAC0_ITRIG_INMUX31 ,DMAC0 input trigger inmux 31 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 30. " DMAC0_ITRIG_INMUX30 ,DMAC0 input trigger inmux 30 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " DMAC0_ITRIG_INMUX29 ,DMAC0 input trigger inmux 29 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " DMAC0_ITRIG_INMUX28 ,DMAC0 input trigger inmux 28 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " DMAC0_ITRIG_INMUX27 ,DMAC0 input trigger inmux 27 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " DMAC0_ITRIG_INMUX26 ,DMAC0 input trigger inmux 26 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " DMAC0_ITRIG_INMUX25 ,DMAC0 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " DMAC0_ITRIG_INMUX24 ,DMAC0 input trigger inmux 24 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMAC0_ITRIG_INMUX23 ,DMAC0 input trigger inmux 23 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMAC0_ITRIG_INMUX22 ,DMAC0 input trigger inmux 22 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMAC0_ITRIG_INMUX21 ,DMAC0 input trigger inmux 21 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMAC0_ITRIG_INMUX20 ,DMAC0 input trigger inmux 20 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMAC0_ITRIG_INMUX19 ,DMAC0 input trigger inmux 19 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMAC0_ITRIG_INMUX18 ,DMAC0 input trigger inmux 18 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMAC0_ITRIG_INMUX17 ,DMAC0 input trigger inmux 17 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMAC0_ITRIG_INMUX16 ,DMAC0 input trigger inmux 16 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " DMAC0_ITRIG_INMUX15 ,DMAC0 input trigger inmux 15 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " DMAC0_ITRIG_INMUX14 ,DMAC0 input trigger inmux 14 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " DMAC0_ITRIG_INMUX13 ,DMAC0 input trigger inmux 13 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " DMAC0_ITRIG_INMUX12 ,DMAC0 input trigger inmux 12 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " DMAC0_ITRIG_INMUX11 ,DMAC0 input trigger inmux 11 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " DMAC0_ITRIG_INMUX10 ,DMAC0 input trigger inmux 10 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " DMAC0_ITRIG_INMUX9  ,DMAC0 input trigger inmux 9 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " DMAC0_ITRIG_INMUX8  ,DMAC0 input trigger inmux 8 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " DMAC0_ITRIG_INMUX7  ,DMAC0 input trigger inmux 7 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " DMAC0_ITRIG_INMUX6  ,DMAC0 input trigger inmux 6 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " DMAC0_ITRIG_INMUX5  ,DMAC0 input trigger inmux 5 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " DMAC0_ITRIG_INMUX4  ,DMAC0 input trigger inmux 4 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " DMAC0_ITRIG_INMUX3  ,DMAC0 input trigger inmux 3 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " DMAC0_ITRIG_INMUX2  ,DMAC0 input trigger inmux 2 enable set" "0,1"
textline "                               "
bitfld.long 0x00 1. " DMAC0_ITRIG_INMUX1  ,DMAC0 input trigger inmux 1 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " DMAC0_ITRIG_INMUX0  ,DMAC0 input trigger inmux 0 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
wgroup.long 0x790++0x03
line.long 0x00 "DMAC0_ITRIG_ENA0_CLR,DMAC0 input trigger enable clear 0"
bitfld.long 0x00 31. " DMAC0_ITRIG_INMUX31 ,DMAC0 input trigger inmux 31 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 30. " DMAC0_ITRIG_INMUX30 ,DMAC0 input trigger inmux 30 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " DMAC0_ITRIG_INMUX29 ,DMAC0 input trigger inmux 29 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " DMAC0_ITRIG_INMUX28 ,DMAC0 input trigger inmux 28 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " DMAC0_ITRIG_INMUX27 ,DMAC0 input trigger inmux 27 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " DMAC0_ITRIG_INMUX26 ,DMAC0 input trigger inmux 26 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " DMAC0_ITRIG_INMUX25 ,DMAC0 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " DMAC0_ITRIG_INMUX24 ,DMAC0 input trigger inmux 24 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMAC0_ITRIG_INMUX23 ,DMAC0 input trigger inmux 23 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMAC0_ITRIG_INMUX22 ,DMAC0 input trigger inmux 22 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMAC0_ITRIG_INMUX21 ,DMAC0 input trigger inmux 21 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMAC0_ITRIG_INMUX20 ,DMAC0 input trigger inmux 20 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMAC0_ITRIG_INMUX19 ,DMAC0 input trigger inmux 19 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMAC0_ITRIG_INMUX18 ,DMAC0 input trigger inmux 18 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMAC0_ITRIG_INMUX17 ,DMAC0 input trigger inmux 17 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMAC0_ITRIG_INMUX16 ,DMAC0 input trigger inmux 16 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " DMAC0_ITRIG_INMUX15 ,DMAC0 input trigger inmux 15 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " DMAC0_ITRIG_INMUX14 ,DMAC0 input trigger inmux 14 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " DMAC0_ITRIG_INMUX13 ,DMAC0 input trigger inmux 13 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " DMAC0_ITRIG_INMUX12 ,DMAC0 input trigger inmux 12 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " DMAC0_ITRIG_INMUX11 ,DMAC0 input trigger inmux 11 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " DMAC0_ITRIG_INMUX10 ,DMAC0 input trigger inmux 10 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " DMAC0_ITRIG_INMUX9  ,DMAC0 input trigger inmux 9 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " DMAC0_ITRIG_INMUX8  ,DMAC0 input trigger inmux 8 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " DMAC0_ITRIG_INMUX7  ,DMAC0 input trigger inmux 7 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " DMAC0_ITRIG_INMUX6  ,DMAC0 input trigger inmux 6 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " DMAC0_ITRIG_INMUX5  ,DMAC0 input trigger inmux 5 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " DMAC0_ITRIG_INMUX4  ,DMAC0 input trigger inmux 4 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " DMAC0_ITRIG_INMUX3  ,DMAC0 input trigger inmux 3 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " DMAC0_ITRIG_INMUX2  ,DMAC0 input trigger inmux 2 enable clear" "0,1"
textline "                               "
bitfld.long 0x00 1. " DMAC0_ITRIG_INMUX1  ,DMAC0 input trigger inmux 1 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " DMAC0_ITRIG_INMUX0  ,DMAC0 input trigger inmux 0 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
group.long 0x7A0++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0,DMAC1 input trigger enable 0"
bitfld.long 0x00 31. " DMAC1_ITRIG_INMUX31 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 30. " DMAC1_ITRIG_INMUX30 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 29. " DMAC1_ITRIG_INMUX29 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 28. " DMAC1_ITRIG_INMUX28 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 27. " DMAC1_ITRIG_INMUX27 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 26. " DMAC1_ITRIG_INMUX26 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 25. " DMAC1_ITRIG_INMUX25 ,DMAC1 input trigger inmux 25 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 24. " DMAC1_ITRIG_INMUX24 ,DMAC1 input trigger inmux 24 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 23. " DMAC1_ITRIG_INMUX23 ,DMAC1 input trigger inmux 23 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 22. " DMAC1_ITRIG_INMUX22 ,DMAC1 input trigger inmux 22 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 21. " DMAC1_ITRIG_INMUX21 ,DMAC1 input trigger inmux 21 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 20. " DMAC1_ITRIG_INMUX20 ,DMAC1 input trigger inmux 20 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 19. " DMAC1_ITRIG_INMUX19 ,DMAC1 input trigger inmux 19 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 18. " DMAC1_ITRIG_INMUX18 ,DMAC1 input trigger inmux 18 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 17. " DMAC1_ITRIG_INMUX17 ,DMAC1 input trigger inmux 17 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 16. " DMAC1_ITRIG_INMUX16 ,DMAC1 input trigger inmux 16 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 15. " DMAC1_ITRIG_INMUX15 ,DMAC1 input trigger inmux 15 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 14. " DMAC1_ITRIG_INMUX14 ,DMAC1 input trigger inmux 14 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 13. " DMAC1_ITRIG_INMUX13 ,DMAC1 input trigger inmux 13 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 12. " DMAC1_ITRIG_INMUX12 ,DMAC1 input trigger inmux 12 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 11. " DMAC1_ITRIG_INMUX11 ,DMAC1 input trigger inmux 11 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 10. " DMAC1_ITRIG_INMUX10 ,DMAC1 input trigger inmux 10 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 9. " DMAC1_ITRIG_INMUX9  ,DMAC1 input trigger inmux 9 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 8. " DMAC1_ITRIG_INMUX8  ,DMAC1 input trigger inmux 8 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 7. " DMAC1_ITRIG_INMUX7  ,DMAC1 input trigger inmux 7 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 6. " DMAC1_ITRIG_INMUX6  ,DMAC1 input trigger inmux 6 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 5. " DMAC1_ITRIG_INMUX5  ,DMAC1 input trigger inmux 5 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 4. " DMAC1_ITRIG_INMUX4  ,DMAC1 input trigger inmux 4 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 3. " DMAC1_ITRIG_INMUX3  ,DMAC1 input trigger inmux 3 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 2. " DMAC1_ITRIG_INMUX2  ,DMAC1 input trigger inmux 2 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 1. " DMAC1_ITRIG_INMUX1  ,DMAC1 input trigger inmux 1 enable" "0: DISABLED,1: ENABLED"
textline "                               "
bitfld.long 0x00 0. " DMAC1_ITRIG_INMUX0  ,DMAC1 input trigger inmux 0 enable" "0: DISABLED,1: ENABLED"
wgroup.long 0x7A8++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0_SET,DMAC1 input trigger enable set 0"
bitfld.long 0x00 31. " DMAC1_ITRIG_INMUX31 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 30. " DMAC1_ITRIG_INMUX30 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " DMAC1_ITRIG_INMUX29 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " DMAC1_ITRIG_INMUX28 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " DMAC1_ITRIG_INMUX27 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " DMAC1_ITRIG_INMUX26 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " DMAC1_ITRIG_INMUX25 ,DMAC1 input trigger inmux 25 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " DMAC1_ITRIG_INMUX24 ,DMAC1 input trigger inmux 24 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMAC1_ITRIG_INMUX23 ,DMAC1 input trigger inmux 23 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMAC1_ITRIG_INMUX22 ,DMAC1 input trigger inmux 22 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMAC1_ITRIG_INMUX21 ,DMAC1 input trigger inmux 21 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMAC1_ITRIG_INMUX20 ,DMAC1 input trigger inmux 20 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMAC1_ITRIG_INMUX19 ,DMAC1 input trigger inmux 19 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMAC1_ITRIG_INMUX18 ,DMAC1 input trigger inmux 18 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMAC1_ITRIG_INMUX17 ,DMAC1 input trigger inmux 17 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMAC1_ITRIG_INMUX16 ,DMAC1 input trigger inmux 16 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " DMAC1_ITRIG_INMUX15 ,DMAC1 input trigger inmux 15 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " DMAC1_ITRIG_INMUX14 ,DMAC1 input trigger inmux 14 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " DMAC1_ITRIG_INMUX13 ,DMAC1 input trigger inmux 13 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " DMAC1_ITRIG_INMUX12 ,DMAC1 input trigger inmux 12 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " DMAC1_ITRIG_INMUX11 ,DMAC1 input trigger inmux 11 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " DMAC1_ITRIG_INMUX10 ,DMAC1 input trigger inmux 10 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " DMAC1_ITRIG_INMUX9  ,DMAC1 input trigger inmux 9 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " DMAC1_ITRIG_INMUX8  ,DMAC1 input trigger inmux 8 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " DMAC1_ITRIG_INMUX7  ,DMAC1 input trigger inmux 7 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " DMAC1_ITRIG_INMUX6  ,DMAC1 input trigger inmux 6 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " DMAC1_ITRIG_INMUX5  ,DMAC1 input trigger inmux 5 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " DMAC1_ITRIG_INMUX4  ,DMAC1 input trigger inmux 4 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " DMAC1_ITRIG_INMUX3  ,DMAC1 input trigger inmux 3 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " DMAC1_ITRIG_INMUX2  ,DMAC1 input trigger inmux 2 enable set" "0,1"
textline "                               "
bitfld.long 0x00 1. " DMAC1_ITRIG_INMUX1  ,DMAC1 input trigger inmux 1 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " DMAC1_ITRIG_INMUX0  ,DMAC1 input trigger inmux 0 enable set" "0: NO_EFFECT,1: Sets the ENA0 Bit"
wgroup.long 0x7B0++0x03
line.long 0x00 "DMAC1_ITRIG_ENA0_CLR,DMAC1 input trigger enable clear 0"
bitfld.long 0x00 31. " DMAC1_ITRIG_INMUX31 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 30. " DMAC1_ITRIG_INMUX30 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 29. " DMAC1_ITRIG_INMUX29 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 28. " DMAC1_ITRIG_INMUX28 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 27. " DMAC1_ITRIG_INMUX27 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 26. " DMAC1_ITRIG_INMUX26 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 25. " DMAC1_ITRIG_INMUX25 ,DMAC1 input trigger inmux 25 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 24. " DMAC1_ITRIG_INMUX24 ,DMAC1 input trigger inmux 24 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 23. " DMAC1_ITRIG_INMUX23 ,DMAC1 input trigger inmux 23 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 22. " DMAC1_ITRIG_INMUX22 ,DMAC1 input trigger inmux 22 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 21. " DMAC1_ITRIG_INMUX21 ,DMAC1 input trigger inmux 21 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 20. " DMAC1_ITRIG_INMUX20 ,DMAC1 input trigger inmux 20 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 19. " DMAC1_ITRIG_INMUX19 ,DMAC1 input trigger inmux 19 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 18. " DMAC1_ITRIG_INMUX18 ,DMAC1 input trigger inmux 18 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 17. " DMAC1_ITRIG_INMUX17 ,DMAC1 input trigger inmux 17 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 16. " DMAC1_ITRIG_INMUX16 ,DMAC1 input trigger inmux 16 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 15. " DMAC1_ITRIG_INMUX15 ,DMAC1 input trigger inmux 15 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 14. " DMAC1_ITRIG_INMUX14 ,DMAC1 input trigger inmux 14 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 13. " DMAC1_ITRIG_INMUX13 ,DMAC1 input trigger inmux 13 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 12. " DMAC1_ITRIG_INMUX12 ,DMAC1 input trigger inmux 12 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 11. " DMAC1_ITRIG_INMUX11 ,DMAC1 input trigger inmux 11 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 10. " DMAC1_ITRIG_INMUX10 ,DMAC1 input trigger inmux 10 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 9. " DMAC1_ITRIG_INMUX9  ,DMAC1 input trigger inmux 9 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 8. " DMAC1_ITRIG_INMUX8  ,DMAC1 input trigger inmux 8 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 7. " DMAC1_ITRIG_INMUX7  ,DMAC1 input trigger inmux 7 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 6. " DMAC1_ITRIG_INMUX6  ,DMAC1 input trigger inmux 6 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 5. " DMAC1_ITRIG_INMUX5  ,DMAC1 input trigger inmux 5 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 4. " DMAC1_ITRIG_INMUX4  ,DMAC1 input trigger inmux 4 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 3. " DMAC1_ITRIG_INMUX3  ,DMAC1 input trigger inmux 3 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 2. " DMAC1_ITRIG_INMUX2  ,DMAC1 input trigger inmux 2 enable clear" "0,1"
textline "                               "
bitfld.long 0x00 1. " DMAC1_ITRIG_INMUX1  ,DMAC1 input trigger inmux 1 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
textline "                               "
bitfld.long 0x00 0. " DMAC1_ITRIG_INMUX0  ,DMAC1 input trigger inmux 0 enable clear" "0: NO_EFFECT,1: clears the ENA0 Bit"
tree "CT32BIT_CAP_SEL[0]"
width 18.
group.long 0x600++0x03
line.long 0x00 "CT32BIT_CAP_SEL0,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x604++0x03
line.long 0x00 "CT32BIT_CAP_SEL1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x608++0x03
line.long 0x00 "CT32BIT_CAP_SEL2,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x60C++0x03
line.long 0x00 "CT32BIT_CAP_SEL3,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
tree.end
tree "CT32BIT_CAP_SEL[1]"
width 18.
group.long 0x610++0x03
line.long 0x00 "CT32BIT_CAP_SEL0,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x614++0x03
line.long 0x00 "CT32BIT_CAP_SEL1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x618++0x03
line.long 0x00 "CT32BIT_CAP_SEL2,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x61C++0x03
line.long 0x00 "CT32BIT_CAP_SEL3,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
tree.end
tree "CT32BIT_CAP_SEL[2]"
width 18.
group.long 0x620++0x03
line.long 0x00 "CT32BIT_CAP_SEL0,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x624++0x03
line.long 0x00 "CT32BIT_CAP_SEL1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x628++0x03
line.long 0x00 "CT32BIT_CAP_SEL2,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x62C++0x03
line.long 0x00 "CT32BIT_CAP_SEL3,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
tree.end
tree "CT32BIT_CAP_SEL[3]"
width 18.
group.long 0x630++0x03
line.long 0x00 "CT32BIT_CAP_SEL0,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x634++0x03
line.long 0x00 "CT32BIT_CAP_SEL1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x638++0x03
line.long 0x00 "CT32BIT_CAP_SEL2,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x63C++0x03
line.long 0x00 "CT32BIT_CAP_SEL3,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
tree.end
tree "CT32BIT_CAP_SEL[4]"
width 18.
group.long 0x640++0x03
line.long 0x00 "CT32BIT_CAP_SEL0,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x644++0x03
line.long 0x00 "CT32BIT_CAP_SEL1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x648++0x03
line.long 0x00 "CT32BIT_CAP_SEL2,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
group.long 0x64C++0x03
line.long 0x00 "CT32BIT_CAP_SEL3,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
bitfld.long 0x00 0.--4. " CAPn_SEL ,Counter Timer m. Capture Port Input n 19:1 Mux Select" "0: CT_INP0,1: CT_INP1,2: CT_INP2,3: CT_INP3,4: CT_INP4,5: CT_INP5,6: CT_INP6,7: CT_INP7,8: CT_INP8,9: CT_INP9,10: CT_INP10,11: CT_INP11,12: CT_INP12,13: CT_INP13,14: CT_INP14,15: CT_INP15,16: SHARED_I2S0_WS,17: SHARED_I2S1_WS,18: USB1_FRAME_TOGGLE,,,,,,,,,,,,,"
tree.end
width 0x0B
tree.end
tree "IOPCTL"
base ad:0x40004000
width 14.
group.long 0x00++0x03
line.long 0x00 "PIO0_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x04++0x03
line.long 0x00 "PIO0_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x08++0x03
line.long 0x00 "PIO0_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x0C++0x03
line.long 0x00 "PIO0_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x10++0x03
line.long 0x00 "PIO0_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x14++0x03
line.long 0x00 "PIO0_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x18++0x03
line.long 0x00 "PIO0_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1C++0x03
line.long 0x00 "PIO0_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x20++0x03
line.long 0x00 "PIO0_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x24++0x03
line.long 0x00 "PIO0_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x28++0x03
line.long 0x00 "PIO0_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2C++0x03
line.long 0x00 "PIO0_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x30++0x03
line.long 0x00 "PIO0_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x34++0x03
line.long 0x00 "PIO0_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x38++0x03
line.long 0x00 "PIO0_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3C++0x03
line.long 0x00 "PIO0_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x40++0x03
line.long 0x00 "PIO0_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x44++0x03
line.long 0x00 "PIO0_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x48++0x03
line.long 0x00 "PIO0_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x4C++0x03
line.long 0x00 "PIO0_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x50++0x03
line.long 0x00 "PIO0_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x54++0x03
line.long 0x00 "PIO0_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x58++0x03
line.long 0x00 "PIO0_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x5C++0x03
line.long 0x00 "PIO0_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x60++0x03
line.long 0x00 "PIO0_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x64++0x03
line.long 0x00 "PIO0_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x68++0x03
line.long 0x00 "PIO0_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x6C++0x03
line.long 0x00 "PIO0_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x70++0x03
line.long 0x00 "PIO0_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x74++0x03
line.long 0x00 "PIO0_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x78++0x03
line.long 0x00 "PIO0_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x7C++0x03
line.long 0x00 "PIO0_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x80++0x03
line.long 0x00 "PIO1_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x84++0x03
line.long 0x00 "PIO1_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x88++0x03
line.long 0x00 "PIO1_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x8C++0x03
line.long 0x00 "PIO1_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x90++0x03
line.long 0x00 "PIO1_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x94++0x03
line.long 0x00 "PIO1_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x98++0x03
line.long 0x00 "PIO1_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x9C++0x03
line.long 0x00 "PIO1_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xA0++0x03
line.long 0x00 "PIO1_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xA4++0x03
line.long 0x00 "PIO1_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xA8++0x03
line.long 0x00 "PIO1_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xAC++0x03
line.long 0x00 "PIO1_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xB0++0x03
line.long 0x00 "PIO1_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xB4++0x03
line.long 0x00 "PIO1_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xB8++0x03
line.long 0x00 "PIO1_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xBC++0x03
line.long 0x00 "PIO1_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xC0++0x03
line.long 0x00 "PIO1_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xC4++0x03
line.long 0x00 "PIO1_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xC8++0x03
line.long 0x00 "PIO1_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xCC++0x03
line.long 0x00 "PIO1_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xD0++0x03
line.long 0x00 "PIO1_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xD4++0x03
line.long 0x00 "PIO1_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xD8++0x03
line.long 0x00 "PIO1_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xDC++0x03
line.long 0x00 "PIO1_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xE0++0x03
line.long 0x00 "PIO1_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xE4++0x03
line.long 0x00 "PIO1_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xE8++0x03
line.long 0x00 "PIO1_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xEC++0x03
line.long 0x00 "PIO1_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xF0++0x03
line.long 0x00 "PIO1_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xF4++0x03
line.long 0x00 "PIO1_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xF8++0x03
line.long 0x00 "PIO1_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0xFC++0x03
line.long 0x00 "PIO1_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x100++0x03
line.long 0x00 "PIO2_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x104++0x03
line.long 0x00 "PIO2_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x108++0x03
line.long 0x00 "PIO2_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x10C++0x03
line.long 0x00 "PIO2_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x110++0x03
line.long 0x00 "PIO2_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x114++0x03
line.long 0x00 "PIO2_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x118++0x03
line.long 0x00 "PIO2_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x11C++0x03
line.long 0x00 "PIO2_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x120++0x03
line.long 0x00 "PIO2_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x124++0x03
line.long 0x00 "PIO2_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x128++0x03
line.long 0x00 "PIO2_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x12C++0x03
line.long 0x00 "PIO2_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x130++0x03
line.long 0x00 "PIO2_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x134++0x03
line.long 0x00 "PIO2_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x138++0x03
line.long 0x00 "PIO2_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x13C++0x03
line.long 0x00 "PIO2_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x140++0x03
line.long 0x00 "PIO2_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x144++0x03
line.long 0x00 "PIO2_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x148++0x03
line.long 0x00 "PIO2_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x14C++0x03
line.long 0x00 "PIO2_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x150++0x03
line.long 0x00 "PIO2_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x154++0x03
line.long 0x00 "PIO2_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x158++0x03
line.long 0x00 "PIO2_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x15C++0x03
line.long 0x00 "PIO2_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x160++0x03
line.long 0x00 "PIO2_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x164++0x03
line.long 0x00 "PIO2_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x168++0x03
line.long 0x00 "PIO2_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x16C++0x03
line.long 0x00 "PIO2_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x170++0x03
line.long 0x00 "PIO2_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x174++0x03
line.long 0x00 "PIO2_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x178++0x03
line.long 0x00 "PIO2_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x17C++0x03
line.long 0x00 "PIO2_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x180++0x03
line.long 0x00 "PIO3_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x184++0x03
line.long 0x00 "PIO3_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x188++0x03
line.long 0x00 "PIO3_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x18C++0x03
line.long 0x00 "PIO3_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x190++0x03
line.long 0x00 "PIO3_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x194++0x03
line.long 0x00 "PIO3_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x198++0x03
line.long 0x00 "PIO3_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x19C++0x03
line.long 0x00 "PIO3_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1A0++0x03
line.long 0x00 "PIO3_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1A4++0x03
line.long 0x00 "PIO3_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1A8++0x03
line.long 0x00 "PIO3_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1AC++0x03
line.long 0x00 "PIO3_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1B0++0x03
line.long 0x00 "PIO3_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1B4++0x03
line.long 0x00 "PIO3_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1B8++0x03
line.long 0x00 "PIO3_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1BC++0x03
line.long 0x00 "PIO3_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1C0++0x03
line.long 0x00 "PIO3_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1C4++0x03
line.long 0x00 "PIO3_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1C8++0x03
line.long 0x00 "PIO3_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1CC++0x03
line.long 0x00 "PIO3_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1D0++0x03
line.long 0x00 "PIO3_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1D4++0x03
line.long 0x00 "PIO3_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1D8++0x03
line.long 0x00 "PIO3_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1DC++0x03
line.long 0x00 "PIO3_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1E0++0x03
line.long 0x00 "PIO3_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1E4++0x03
line.long 0x00 "PIO3_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1E8++0x03
line.long 0x00 "PIO3_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1EC++0x03
line.long 0x00 "PIO3_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1F0++0x03
line.long 0x00 "PIO3_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1F4++0x03
line.long 0x00 "PIO3_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1F8++0x03
line.long 0x00 "PIO3_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x1FC++0x03
line.long 0x00 "PIO3_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x200++0x03
line.long 0x00 "PIO4_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x204++0x03
line.long 0x00 "PIO4_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x208++0x03
line.long 0x00 "PIO4_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x20C++0x03
line.long 0x00 "PIO4_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x210++0x03
line.long 0x00 "PIO4_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x214++0x03
line.long 0x00 "PIO4_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x218++0x03
line.long 0x00 "PIO4_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x21C++0x03
line.long 0x00 "PIO4_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x220++0x03
line.long 0x00 "PIO4_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x224++0x03
line.long 0x00 "PIO4_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x228++0x03
line.long 0x00 "PIO4_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x22C++0x03
line.long 0x00 "PIO4_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x230++0x03
line.long 0x00 "PIO4_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x234++0x03
line.long 0x00 "PIO4_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x238++0x03
line.long 0x00 "PIO4_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x23C++0x03
line.long 0x00 "PIO4_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x240++0x03
line.long 0x00 "PIO4_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x244++0x03
line.long 0x00 "PIO4_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x248++0x03
line.long 0x00 "PIO4_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x24C++0x03
line.long 0x00 "PIO4_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x250++0x03
line.long 0x00 "PIO4_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x254++0x03
line.long 0x00 "PIO4_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x258++0x03
line.long 0x00 "PIO4_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x25C++0x03
line.long 0x00 "PIO4_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x260++0x03
line.long 0x00 "PIO4_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x264++0x03
line.long 0x00 "PIO4_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x268++0x03
line.long 0x00 "PIO4_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x26C++0x03
line.long 0x00 "PIO4_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x270++0x03
line.long 0x00 "PIO4_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x274++0x03
line.long 0x00 "PIO4_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x278++0x03
line.long 0x00 "PIO4_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x27C++0x03
line.long 0x00 "PIO4_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x280++0x03
line.long 0x00 "PIO5_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x284++0x03
line.long 0x00 "PIO5_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x288++0x03
line.long 0x00 "PIO5_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x28C++0x03
line.long 0x00 "PIO5_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x290++0x03
line.long 0x00 "PIO5_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x294++0x03
line.long 0x00 "PIO5_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x298++0x03
line.long 0x00 "PIO5_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x29C++0x03
line.long 0x00 "PIO5_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2A0++0x03
line.long 0x00 "PIO5_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2A4++0x03
line.long 0x00 "PIO5_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2A8++0x03
line.long 0x00 "PIO5_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2AC++0x03
line.long 0x00 "PIO5_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2B0++0x03
line.long 0x00 "PIO5_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2B4++0x03
line.long 0x00 "PIO5_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2B8++0x03
line.long 0x00 "PIO5_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2BC++0x03
line.long 0x00 "PIO5_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2C0++0x03
line.long 0x00 "PIO5_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2C4++0x03
line.long 0x00 "PIO5_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2C8++0x03
line.long 0x00 "PIO5_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2CC++0x03
line.long 0x00 "PIO5_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2D0++0x03
line.long 0x00 "PIO5_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2D4++0x03
line.long 0x00 "PIO5_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2D8++0x03
line.long 0x00 "PIO5_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2DC++0x03
line.long 0x00 "PIO5_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2E0++0x03
line.long 0x00 "PIO5_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2E4++0x03
line.long 0x00 "PIO5_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2E8++0x03
line.long 0x00 "PIO5_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2EC++0x03
line.long 0x00 "PIO5_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2F0++0x03
line.long 0x00 "PIO5_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2F4++0x03
line.long 0x00 "PIO5_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2F8++0x03
line.long 0x00 "PIO5_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x2FC++0x03
line.long 0x00 "PIO5_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x300++0x03
line.long 0x00 "PIO6_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x304++0x03
line.long 0x00 "PIO6_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x308++0x03
line.long 0x00 "PIO6_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x30C++0x03
line.long 0x00 "PIO6_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x310++0x03
line.long 0x00 "PIO6_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x314++0x03
line.long 0x00 "PIO6_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x318++0x03
line.long 0x00 "PIO6_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x31C++0x03
line.long 0x00 "PIO6_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x320++0x03
line.long 0x00 "PIO6_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x324++0x03
line.long 0x00 "PIO6_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x328++0x03
line.long 0x00 "PIO6_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x32C++0x03
line.long 0x00 "PIO6_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x330++0x03
line.long 0x00 "PIO6_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x334++0x03
line.long 0x00 "PIO6_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x338++0x03
line.long 0x00 "PIO6_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x33C++0x03
line.long 0x00 "PIO6_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x340++0x03
line.long 0x00 "PIO6_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x344++0x03
line.long 0x00 "PIO6_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x348++0x03
line.long 0x00 "PIO6_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x34C++0x03
line.long 0x00 "PIO6_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x350++0x03
line.long 0x00 "PIO6_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x354++0x03
line.long 0x00 "PIO6_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x358++0x03
line.long 0x00 "PIO6_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x35C++0x03
line.long 0x00 "PIO6_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x360++0x03
line.long 0x00 "PIO6_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x364++0x03
line.long 0x00 "PIO6_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x368++0x03
line.long 0x00 "PIO6_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x36C++0x03
line.long 0x00 "PIO6_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x370++0x03
line.long 0x00 "PIO6_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x374++0x03
line.long 0x00 "PIO6_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x378++0x03
line.long 0x00 "PIO6_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x37C++0x03
line.long 0x00 "PIO6_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x380++0x03
line.long 0x00 "PIO7_0,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x384++0x03
line.long 0x00 "PIO7_1,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x388++0x03
line.long 0x00 "PIO7_2,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x38C++0x03
line.long 0x00 "PIO7_3,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x390++0x03
line.long 0x00 "PIO7_4,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x394++0x03
line.long 0x00 "PIO7_5,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x398++0x03
line.long 0x00 "PIO7_6,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x39C++0x03
line.long 0x00 "PIO7_7,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3A0++0x03
line.long 0x00 "PIO7_8,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3A4++0x03
line.long 0x00 "PIO7_9,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3A8++0x03
line.long 0x00 "PIO7_10,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3AC++0x03
line.long 0x00 "PIO7_11,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3B0++0x03
line.long 0x00 "PIO7_12,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3B4++0x03
line.long 0x00 "PIO7_13,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3B8++0x03
line.long 0x00 "PIO7_14,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3BC++0x03
line.long 0x00 "PIO7_15,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3C0++0x03
line.long 0x00 "PIO7_16,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3C4++0x03
line.long 0x00 "PIO7_17,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3C8++0x03
line.long 0x00 "PIO7_18,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3CC++0x03
line.long 0x00 "PIO7_19,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3D0++0x03
line.long 0x00 "PIO7_20,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3D4++0x03
line.long 0x00 "PIO7_21,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3D8++0x03
line.long 0x00 "PIO7_22,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3DC++0x03
line.long 0x00 "PIO7_23,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3E0++0x03
line.long 0x00 "PIO7_24,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3E4++0x03
line.long 0x00 "PIO7_25,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3E8++0x03
line.long 0x00 "PIO7_26,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3EC++0x03
line.long 0x00 "PIO7_27,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3F0++0x03
line.long 0x00 "PIO7_28,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3F4++0x03
line.long 0x00 "PIO7_29,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3F8++0x03
line.long 0x00 "PIO7_30,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x3FC++0x03
line.long 0x00 "PIO7_31,iop pad control register for port0 to port5"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x400++0x03
line.long 0x00 "FC15_I2C_SCL,Special Registers (No GPIO Function)"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
group.long 0x404++0x03
line.long 0x00 "FC15_I2C_SDA,Special Registers (No GPIO Function)"
bitfld.long 0x00 11. " IIENA     ,Input Invert Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 10. " ODENA     ,Pseudo Output Drain Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " AMENA     ,Analog Mux Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 8. " FULLDRIVE ,Drive Selector" "0: NORMAL_DRIVE,1: FULL_DRIVE"
textline "                       "
bitfld.long 0x00 7. " SLEWRATE  ,Slew Rate Control" "0: Slew Rate is Normal,1: Slew Rate Slow"
textline "                       "
bitfld.long 0x00 6. " IBENA     ,Input Buffer Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " PUPDSEL   ,Pullup or Pulldown Selector" "0: PULL_DOWN,1: PULL_UP"
textline "                       "
bitfld.long 0x00 4. " PUPDENA   ,Pullup / Pulldown Enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 0.--3. " FSEL      ,Function Selector" "0: FUNCTION_0,1: FUNCTION_1,2: FUNCTION_2,3: FUNCTION_3,4: FUNCTION_4,5: FUNCTION_5,6: FUNCTION_6,7: FUNCTION_7,8: FUNCTION_8,9: FUNCTION_9,10: FUNCTION_10,11: FUNCTION_11,12: FUNCTION_12,13: FUNCTION_13,14: FUNCTION_14,15: FUNCTION_15"
width 0x0B
tree.end
tree "MRT"
tree "MRT0"
base ad:0x4002D000
width 10.
group.long 0xF0++0x03
line.long 0x00 "MODCFG,Module Configuration register"
bitfld.long 0x00 31. " MULTITASK ,Selects the operating mode for the INUSE flags and the IDLE_CH register" "0: HARDWARE_STATUS_MODE,1: MULTI_TASK_MODE"
textline "                   "
bitfld.long 0x00 4.--8. " NOB       ,Identifies the number of timer bits in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                   "
bitfld.long 0x00 0.--3. " NOC       ,Identifies the number of channels in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF4++0x03
line.long 0x00 "IDLE_CH,Idle channel register"
bitfld.long 0x00 4.--7. " CHAN      ,Idle channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF8++0x03
line.long 0x00 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x00 3. " GFLAG3    ,Monitors the interrupt flag of TIMER3" "0,1"
textline "                   "
bitfld.long 0x00 2. " GFLAG2    ,Monitors the interrupt flag of TIMER2" "0,1"
textline "                   "
bitfld.long 0x00 1. " GFLAG1    ,Monitors the interrupt flag of TIMER1" "0,1"
textline "                   "
bitfld.long 0x00 0. " GFLAG0    ,Monitors the interrupt flag of TIMER0" "0: NO_PENDING_INTERRUPT,1: PENDING_INTERRUPT"
tree "CHANNEL[0]"
width 8.
group.long 0x00++0x03
line.long 0x00 "INTVAL,MRT Time interval value register"
bitfld.long 0x00 31. " LOAD    ,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register" "0: NO_FORCE_LOAD,1: FORCE_LOAD"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE  ,Time interval load value"
rgroup.long 0x04++0x03
line.long 0x00 "TIMER,MRT Timer register"
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE   ,Holds the current timer value of the down-counter"
group.long 0x08++0x03
line.long 0x00 "CTRL,MRT Control register"
bitfld.long 0x00 1.--2. " MODE    ,Selects timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,"
textline "                 "
bitfld.long 0x00 0. " INTEN   ,Enable the TIMERn interrupt" "0: DISABLED,1: ENABLED"
group.long 0x0C++0x03
line.long 0x00 "STAT,MRT Status register"
bitfld.long 0x00 2. " INUSE   ,Channel In Use flag" "0: This channel is not in use,1: This channel is in use"
textline "                 "
bitfld.long 0x00 1. " RUN     ,Indicates the state of TIMERn" "0: IDLE_STATE,1: RUNNING"
textline "                 "
bitfld.long 0x00 0. " INTFLAG ,Monitors the interrupt flag" "0: NO_PENDING_INTERRUPT,1: PENDING_INTERRUPT"
tree.end
tree "CHANNEL[1]"
width 8.
group.long 0x10++0x03
line.long 0x00 "INTVAL,MRT Time interval value register"
bitfld.long 0x00 31. " LOAD    ,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register" "0: NO_FORCE_LOAD,1: FORCE_LOAD"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE  ,Time interval load value"
rgroup.long 0x14++0x03
line.long 0x00 "TIMER,MRT Timer register"
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE   ,Holds the current timer value of the down-counter"
group.long 0x18++0x03
line.long 0x00 "CTRL,MRT Control register"
bitfld.long 0x00 1.--2. " MODE    ,Selects timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,"
textline "                 "
bitfld.long 0x00 0. " INTEN   ,Enable the TIMERn interrupt" "0: DISABLED,1: ENABLED"
group.long 0x1C++0x03
line.long 0x00 "STAT,MRT Status register"
bitfld.long 0x00 2. " INUSE   ,Channel In Use flag" "0: This channel is not in use,1: This channel is in use"
textline "                 "
bitfld.long 0x00 1. " RUN     ,Indicates the state of TIMERn" "0: IDLE_STATE,1: RUNNING"
textline "                 "
bitfld.long 0x00 0. " INTFLAG ,Monitors the interrupt flag" "0: NO_PENDING_INTERRUPT,1: PENDING_INTERRUPT"
tree.end
tree "CHANNEL[2]"
width 8.
group.long 0x20++0x03
line.long 0x00 "INTVAL,MRT Time interval value register"
bitfld.long 0x00 31. " LOAD    ,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register" "0: NO_FORCE_LOAD,1: FORCE_LOAD"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE  ,Time interval load value"
rgroup.long 0x24++0x03
line.long 0x00 "TIMER,MRT Timer register"
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE   ,Holds the current timer value of the down-counter"
group.long 0x28++0x03
line.long 0x00 "CTRL,MRT Control register"
bitfld.long 0x00 1.--2. " MODE    ,Selects timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,"
textline "                 "
bitfld.long 0x00 0. " INTEN   ,Enable the TIMERn interrupt" "0: DISABLED,1: ENABLED"
group.long 0x2C++0x03
line.long 0x00 "STAT,MRT Status register"
bitfld.long 0x00 2. " INUSE   ,Channel In Use flag" "0: This channel is not in use,1: This channel is in use"
textline "                 "
bitfld.long 0x00 1. " RUN     ,Indicates the state of TIMERn" "0: IDLE_STATE,1: RUNNING"
textline "                 "
bitfld.long 0x00 0. " INTFLAG ,Monitors the interrupt flag" "0: NO_PENDING_INTERRUPT,1: PENDING_INTERRUPT"
tree.end
tree "CHANNEL[3]"
width 8.
group.long 0x30++0x03
line.long 0x00 "INTVAL,MRT Time interval value register"
bitfld.long 0x00 31. " LOAD    ,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register" "0: NO_FORCE_LOAD,1: FORCE_LOAD"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE  ,Time interval load value"
rgroup.long 0x34++0x03
line.long 0x00 "TIMER,MRT Timer register"
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE   ,Holds the current timer value of the down-counter"
group.long 0x38++0x03
line.long 0x00 "CTRL,MRT Control register"
bitfld.long 0x00 1.--2. " MODE    ,Selects timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,"
textline "                 "
bitfld.long 0x00 0. " INTEN   ,Enable the TIMERn interrupt" "0: DISABLED,1: ENABLED"
group.long 0x3C++0x03
line.long 0x00 "STAT,MRT Status register"
bitfld.long 0x00 2. " INUSE   ,Channel In Use flag" "0: This channel is not in use,1: This channel is in use"
textline "                 "
bitfld.long 0x00 1. " RUN     ,Indicates the state of TIMERn" "0: IDLE_STATE,1: RUNNING"
textline "                 "
bitfld.long 0x00 0. " INTFLAG ,Monitors the interrupt flag" "0: NO_PENDING_INTERRUPT,1: PENDING_INTERRUPT"
tree.end
width 0x0B
tree.end
tree.end
tree "MU"
tree "MUA"
base ad:0x40110000
width 7.
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. " MAJOR     ,Major Version Number"
textline "                "
hexmask.long.byte 0x00 16.--23. 1. " MINOR     ,Minor Version Number"
textline "                "
hexmask.long.word 0x00 0.--15. 1. " FEATURE   ,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Use Parameter register to determine the parameter settings of MUA"
hexmask.long 0x00 0.--31. 1. " PARAMETER ,no description available"
group.long 0x20++0x03
line.long 0x00 "TR[0],Transmit Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x24++0x03
line.long 0x00 "TR[1],Transmit Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x28++0x03
line.long 0x00 "TR[2],Transmit Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x2C++0x03
line.long 0x00 "TR[3],Transmit Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x40++0x03
line.long 0x00 "RR[0],Receive Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x44++0x03
line.long 0x00 "RR[1],Receive Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x48++0x03
line.long 0x00 "RR[2],Receive Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x4C++0x03
line.long 0x00 "RR[3],Receive Register"
hexmask.long 0x00 0.--31. 1. " DATA      ,DATA"
group.long 0x60++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 28.--31. " GIPn      ,GIPn" "0: MUA general purpose interrupt n is not pending,1: MUA general purpose interrupt n is pending,,,,,,,,,,,,,,"
textline "                "
rbitfld.long 0x00 24.--27. " RFn       ,RFn" "0: MUA RRn register is not full (default),1: MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA,,,,,,,,,,,,,,"
textline "                "
rbitfld.long 0x00 20.--23. " TEn       ,TEn" "0: MUA TRn register is not empty,1: MUA TRn register is empty (default),,,,,,,,,,,,,,"
textline "                "
bitfld.long 0x00 10. " RAIP      ,RAIP" "0: Processor B-side did not enter reset,1: Processor B-side entered reset"
textline "                "
bitfld.long 0x00 9. " RDIP      ,BRDIP" "0: Processor B-side did not exit reset,1: Processor B-side exited from reset"
textline "                "
rbitfld.long 0x00 8. " FUP       ,FUP" "0: No flags updated. initiated by the MUA. in progress (default),1: MUA initiated flags update. processing"
textline "                "
rbitfld.long 0x00 7. " RS        ,RS" "0: The MUB side of the MU is not in reset,1: The MUB side of the MU is in reset"
textline "                "
rbitfld.long 0x00 5.--6. " PM        ,PM" "0: The MUB processor is in Run Mode,1: The MUB processor is in WAIT Mode,,"
textline "                "
rbitfld.long 0x00 4. " EP        ,EP" "0: The MUA side event is not pending (default),1: The MUA side event is pending"
textline "                "
rbitfld.long 0x00 0.--2. " Fn        ,Fn" "0: Fn bit in the CR register is written 0 (default),1: Fn bit in the CR register is written 1,,,,,,"
group.long 0x64++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 28.--31. " GIEn      ,GIEn" "0: Disables MUA General Interrupt n,1: Enables MUA General Interrupt n,,,,,,,,,,,,,,"
textline "                "
bitfld.long 0x00 24.--27. " RIEn      ,RIEn" "0: Disables MUA Receive Interrupt n,1: Enables MUA Receive Interrupt n,,,,,,,,,,,,,,"
textline "                "
bitfld.long 0x00 20.--23. " TIEn      ,TIEn" "0: Disables MUA Transmit Interrupt n,1: Enables MUA Transmit Interrupt n,,,,,,,,,,,,,,"
textline "                "
bitfld.long 0x00 16.--19. " GIRn      ,GIRn" "0: MUA General Interrupt n is not requested to the MUB (default),1: MUA General Interrupt n is requested to the MUB,,,,,,,,,,,,,,"
textline "                "
bitfld.long 0x00 12. " RAIE      ,RAIE" "0: Disables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion,1: Enables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion"
textline "                "
bitfld.long 0x00 6. " RDIE      ,BRDIE" "0: Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion,1: Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion"
textline "                "
bitfld.long 0x00 5. " MUR       ,MUR" "0: MUR_0,1: Asserts the MU reset"
textline "                "
bitfld.long 0x00 0.--2. " Fn        ,Fn" "0: Clears the Fn bit in the SR register,1: Sets the Fn bit in the SR register,,,,,,"
width 0x0B
tree.end
tree.end
tree "OCOTP"
base ad:0x40130000
width 17.
group.long 0x00++0x03
line.long 0x00 "OTP_SHADOW[0],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x04++0x03
line.long 0x00 "OTP_SHADOW[1],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x08++0x03
line.long 0x00 "OTP_SHADOW[2],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x0C++0x03
line.long 0x00 "OTP_SHADOW[3],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x10++0x03
line.long 0x00 "OTP_SHADOW[4],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x14++0x03
line.long 0x00 "OTP_SHADOW[5],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x18++0x03
line.long 0x00 "OTP_SHADOW[6],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1C++0x03
line.long 0x00 "OTP_SHADOW[7],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x20++0x03
line.long 0x00 "OTP_SHADOW[8],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x24++0x03
line.long 0x00 "OTP_SHADOW[9],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x28++0x03
line.long 0x00 "OTP_SHADOW[10],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2C++0x03
line.long 0x00 "OTP_SHADOW[11],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x30++0x03
line.long 0x00 "OTP_SHADOW[12],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x34++0x03
line.long 0x00 "OTP_SHADOW[13],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x38++0x03
line.long 0x00 "OTP_SHADOW[14],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3C++0x03
line.long 0x00 "OTP_SHADOW[15],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x40++0x03
line.long 0x00 "OTP_SHADOW[16],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x44++0x03
line.long 0x00 "OTP_SHADOW[17],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x48++0x03
line.long 0x00 "OTP_SHADOW[18],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4C++0x03
line.long 0x00 "OTP_SHADOW[19],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x50++0x03
line.long 0x00 "OTP_SHADOW[20],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x54++0x03
line.long 0x00 "OTP_SHADOW[21],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x58++0x03
line.long 0x00 "OTP_SHADOW[22],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5C++0x03
line.long 0x00 "OTP_SHADOW[23],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x60++0x03
line.long 0x00 "OTP_SHADOW[24],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x64++0x03
line.long 0x00 "OTP_SHADOW[25],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x68++0x03
line.long 0x00 "OTP_SHADOW[26],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6C++0x03
line.long 0x00 "OTP_SHADOW[27],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x70++0x03
line.long 0x00 "OTP_SHADOW[28],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x74++0x03
line.long 0x00 "OTP_SHADOW[29],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x78++0x03
line.long 0x00 "OTP_SHADOW[30],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7C++0x03
line.long 0x00 "OTP_SHADOW[31],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x80++0x03
line.long 0x00 "OTP_SHADOW[32],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x84++0x03
line.long 0x00 "OTP_SHADOW[33],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x88++0x03
line.long 0x00 "OTP_SHADOW[34],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x8C++0x03
line.long 0x00 "OTP_SHADOW[35],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x90++0x03
line.long 0x00 "OTP_SHADOW[36],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x94++0x03
line.long 0x00 "OTP_SHADOW[37],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x98++0x03
line.long 0x00 "OTP_SHADOW[38],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x9C++0x03
line.long 0x00 "OTP_SHADOW[39],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xA0++0x03
line.long 0x00 "OTP_SHADOW[40],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xA4++0x03
line.long 0x00 "OTP_SHADOW[41],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xA8++0x03
line.long 0x00 "OTP_SHADOW[42],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xAC++0x03
line.long 0x00 "OTP_SHADOW[43],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xB0++0x03
line.long 0x00 "OTP_SHADOW[44],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xB4++0x03
line.long 0x00 "OTP_SHADOW[45],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xB8++0x03
line.long 0x00 "OTP_SHADOW[46],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xBC++0x03
line.long 0x00 "OTP_SHADOW[47],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xC0++0x03
line.long 0x00 "OTP_SHADOW[48],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xC4++0x03
line.long 0x00 "OTP_SHADOW[49],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xC8++0x03
line.long 0x00 "OTP_SHADOW[50],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xCC++0x03
line.long 0x00 "OTP_SHADOW[51],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xD0++0x03
line.long 0x00 "OTP_SHADOW[52],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xD4++0x03
line.long 0x00 "OTP_SHADOW[53],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xD8++0x03
line.long 0x00 "OTP_SHADOW[54],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xDC++0x03
line.long 0x00 "OTP_SHADOW[55],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xE0++0x03
line.long 0x00 "OTP_SHADOW[56],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xE4++0x03
line.long 0x00 "OTP_SHADOW[57],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xE8++0x03
line.long 0x00 "OTP_SHADOW[58],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xEC++0x03
line.long 0x00 "OTP_SHADOW[59],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xF0++0x03
line.long 0x00 "OTP_SHADOW[60],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xF4++0x03
line.long 0x00 "OTP_SHADOW[61],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xF8++0x03
line.long 0x00 "OTP_SHADOW[62],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0xFC++0x03
line.long 0x00 "OTP_SHADOW[63],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x100++0x03
line.long 0x00 "OTP_SHADOW[64],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x104++0x03
line.long 0x00 "OTP_SHADOW[65],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x108++0x03
line.long 0x00 "OTP_SHADOW[66],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x10C++0x03
line.long 0x00 "OTP_SHADOW[67],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x110++0x03
line.long 0x00 "OTP_SHADOW[68],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x114++0x03
line.long 0x00 "OTP_SHADOW[69],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x118++0x03
line.long 0x00 "OTP_SHADOW[70],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x11C++0x03
line.long 0x00 "OTP_SHADOW[71],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x120++0x03
line.long 0x00 "OTP_SHADOW[72],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x124++0x03
line.long 0x00 "OTP_SHADOW[73],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x128++0x03
line.long 0x00 "OTP_SHADOW[74],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x12C++0x03
line.long 0x00 "OTP_SHADOW[75],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x130++0x03
line.long 0x00 "OTP_SHADOW[76],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x134++0x03
line.long 0x00 "OTP_SHADOW[77],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x138++0x03
line.long 0x00 "OTP_SHADOW[78],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x13C++0x03
line.long 0x00 "OTP_SHADOW[79],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x140++0x03
line.long 0x00 "OTP_SHADOW[80],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x144++0x03
line.long 0x00 "OTP_SHADOW[81],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x148++0x03
line.long 0x00 "OTP_SHADOW[82],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x14C++0x03
line.long 0x00 "OTP_SHADOW[83],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x150++0x03
line.long 0x00 "OTP_SHADOW[84],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x154++0x03
line.long 0x00 "OTP_SHADOW[85],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x158++0x03
line.long 0x00 "OTP_SHADOW[86],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x15C++0x03
line.long 0x00 "OTP_SHADOW[87],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x160++0x03
line.long 0x00 "OTP_SHADOW[88],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x164++0x03
line.long 0x00 "OTP_SHADOW[89],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x168++0x03
line.long 0x00 "OTP_SHADOW[90],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x16C++0x03
line.long 0x00 "OTP_SHADOW[91],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x170++0x03
line.long 0x00 "OTP_SHADOW[92],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x174++0x03
line.long 0x00 "OTP_SHADOW[93],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x178++0x03
line.long 0x00 "OTP_SHADOW[94],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x17C++0x03
line.long 0x00 "OTP_SHADOW[95],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x180++0x03
line.long 0x00 "OTP_SHADOW[96],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x184++0x03
line.long 0x00 "OTP_SHADOW[97],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x188++0x03
line.long 0x00 "OTP_SHADOW[98],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x18C++0x03
line.long 0x00 "OTP_SHADOW[99],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x190++0x03
line.long 0x00 "OTP_SHADOW[100],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x194++0x03
line.long 0x00 "OTP_SHADOW[101],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x198++0x03
line.long 0x00 "OTP_SHADOW[102],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x19C++0x03
line.long 0x00 "OTP_SHADOW[103],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1A0++0x03
line.long 0x00 "OTP_SHADOW[104],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1A4++0x03
line.long 0x00 "OTP_SHADOW[105],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1A8++0x03
line.long 0x00 "OTP_SHADOW[106],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1AC++0x03
line.long 0x00 "OTP_SHADOW[107],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1B0++0x03
line.long 0x00 "OTP_SHADOW[108],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1B4++0x03
line.long 0x00 "OTP_SHADOW[109],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1B8++0x03
line.long 0x00 "OTP_SHADOW[110],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1BC++0x03
line.long 0x00 "OTP_SHADOW[111],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1C0++0x03
line.long 0x00 "OTP_SHADOW[112],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1C4++0x03
line.long 0x00 "OTP_SHADOW[113],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1C8++0x03
line.long 0x00 "OTP_SHADOW[114],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1CC++0x03
line.long 0x00 "OTP_SHADOW[115],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1D0++0x03
line.long 0x00 "OTP_SHADOW[116],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1D4++0x03
line.long 0x00 "OTP_SHADOW[117],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1D8++0x03
line.long 0x00 "OTP_SHADOW[118],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1DC++0x03
line.long 0x00 "OTP_SHADOW[119],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1E0++0x03
line.long 0x00 "OTP_SHADOW[120],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1E4++0x03
line.long 0x00 "OTP_SHADOW[121],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1E8++0x03
line.long 0x00 "OTP_SHADOW[122],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1EC++0x03
line.long 0x00 "OTP_SHADOW[123],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1F0++0x03
line.long 0x00 "OTP_SHADOW[124],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1F4++0x03
line.long 0x00 "OTP_SHADOW[125],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1F8++0x03
line.long 0x00 "OTP_SHADOW[126],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x1FC++0x03
line.long 0x00 "OTP_SHADOW[127],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x200++0x03
line.long 0x00 "OTP_SHADOW[128],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x204++0x03
line.long 0x00 "OTP_SHADOW[129],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x208++0x03
line.long 0x00 "OTP_SHADOW[130],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x20C++0x03
line.long 0x00 "OTP_SHADOW[131],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x210++0x03
line.long 0x00 "OTP_SHADOW[132],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x214++0x03
line.long 0x00 "OTP_SHADOW[133],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x218++0x03
line.long 0x00 "OTP_SHADOW[134],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x21C++0x03
line.long 0x00 "OTP_SHADOW[135],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x220++0x03
line.long 0x00 "OTP_SHADOW[136],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x224++0x03
line.long 0x00 "OTP_SHADOW[137],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x228++0x03
line.long 0x00 "OTP_SHADOW[138],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x22C++0x03
line.long 0x00 "OTP_SHADOW[139],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x230++0x03
line.long 0x00 "OTP_SHADOW[140],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x234++0x03
line.long 0x00 "OTP_SHADOW[141],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x238++0x03
line.long 0x00 "OTP_SHADOW[142],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x23C++0x03
line.long 0x00 "OTP_SHADOW[143],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x240++0x03
line.long 0x00 "OTP_SHADOW[144],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x244++0x03
line.long 0x00 "OTP_SHADOW[145],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x248++0x03
line.long 0x00 "OTP_SHADOW[146],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x24C++0x03
line.long 0x00 "OTP_SHADOW[147],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x250++0x03
line.long 0x00 "OTP_SHADOW[148],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x254++0x03
line.long 0x00 "OTP_SHADOW[149],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x258++0x03
line.long 0x00 "OTP_SHADOW[150],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x25C++0x03
line.long 0x00 "OTP_SHADOW[151],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x260++0x03
line.long 0x00 "OTP_SHADOW[152],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x264++0x03
line.long 0x00 "OTP_SHADOW[153],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x268++0x03
line.long 0x00 "OTP_SHADOW[154],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x26C++0x03
line.long 0x00 "OTP_SHADOW[155],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x270++0x03
line.long 0x00 "OTP_SHADOW[156],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x274++0x03
line.long 0x00 "OTP_SHADOW[157],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x278++0x03
line.long 0x00 "OTP_SHADOW[158],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x27C++0x03
line.long 0x00 "OTP_SHADOW[159],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x280++0x03
line.long 0x00 "OTP_SHADOW[160],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x284++0x03
line.long 0x00 "OTP_SHADOW[161],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x288++0x03
line.long 0x00 "OTP_SHADOW[162],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x28C++0x03
line.long 0x00 "OTP_SHADOW[163],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x290++0x03
line.long 0x00 "OTP_SHADOW[164],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x294++0x03
line.long 0x00 "OTP_SHADOW[165],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x298++0x03
line.long 0x00 "OTP_SHADOW[166],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x29C++0x03
line.long 0x00 "OTP_SHADOW[167],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2A0++0x03
line.long 0x00 "OTP_SHADOW[168],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2A4++0x03
line.long 0x00 "OTP_SHADOW[169],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2A8++0x03
line.long 0x00 "OTP_SHADOW[170],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2AC++0x03
line.long 0x00 "OTP_SHADOW[171],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2B0++0x03
line.long 0x00 "OTP_SHADOW[172],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2B4++0x03
line.long 0x00 "OTP_SHADOW[173],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2B8++0x03
line.long 0x00 "OTP_SHADOW[174],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2BC++0x03
line.long 0x00 "OTP_SHADOW[175],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2C0++0x03
line.long 0x00 "OTP_SHADOW[176],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2C4++0x03
line.long 0x00 "OTP_SHADOW[177],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2C8++0x03
line.long 0x00 "OTP_SHADOW[178],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2CC++0x03
line.long 0x00 "OTP_SHADOW[179],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2D0++0x03
line.long 0x00 "OTP_SHADOW[180],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2D4++0x03
line.long 0x00 "OTP_SHADOW[181],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2D8++0x03
line.long 0x00 "OTP_SHADOW[182],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2DC++0x03
line.long 0x00 "OTP_SHADOW[183],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2E0++0x03
line.long 0x00 "OTP_SHADOW[184],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2E4++0x03
line.long 0x00 "OTP_SHADOW[185],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2E8++0x03
line.long 0x00 "OTP_SHADOW[186],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2EC++0x03
line.long 0x00 "OTP_SHADOW[187],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2F0++0x03
line.long 0x00 "OTP_SHADOW[188],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2F4++0x03
line.long 0x00 "OTP_SHADOW[189],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2F8++0x03
line.long 0x00 "OTP_SHADOW[190],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x2FC++0x03
line.long 0x00 "OTP_SHADOW[191],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x300++0x03
line.long 0x00 "OTP_SHADOW[192],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x304++0x03
line.long 0x00 "OTP_SHADOW[193],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x308++0x03
line.long 0x00 "OTP_SHADOW[194],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x30C++0x03
line.long 0x00 "OTP_SHADOW[195],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x310++0x03
line.long 0x00 "OTP_SHADOW[196],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x314++0x03
line.long 0x00 "OTP_SHADOW[197],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x318++0x03
line.long 0x00 "OTP_SHADOW[198],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x31C++0x03
line.long 0x00 "OTP_SHADOW[199],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x320++0x03
line.long 0x00 "OTP_SHADOW[200],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x324++0x03
line.long 0x00 "OTP_SHADOW[201],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x328++0x03
line.long 0x00 "OTP_SHADOW[202],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x32C++0x03
line.long 0x00 "OTP_SHADOW[203],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x330++0x03
line.long 0x00 "OTP_SHADOW[204],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x334++0x03
line.long 0x00 "OTP_SHADOW[205],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x338++0x03
line.long 0x00 "OTP_SHADOW[206],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x33C++0x03
line.long 0x00 "OTP_SHADOW[207],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x340++0x03
line.long 0x00 "OTP_SHADOW[208],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x344++0x03
line.long 0x00 "OTP_SHADOW[209],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x348++0x03
line.long 0x00 "OTP_SHADOW[210],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x34C++0x03
line.long 0x00 "OTP_SHADOW[211],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x350++0x03
line.long 0x00 "OTP_SHADOW[212],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x354++0x03
line.long 0x00 "OTP_SHADOW[213],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x358++0x03
line.long 0x00 "OTP_SHADOW[214],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x35C++0x03
line.long 0x00 "OTP_SHADOW[215],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x360++0x03
line.long 0x00 "OTP_SHADOW[216],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x364++0x03
line.long 0x00 "OTP_SHADOW[217],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x368++0x03
line.long 0x00 "OTP_SHADOW[218],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x36C++0x03
line.long 0x00 "OTP_SHADOW[219],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x370++0x03
line.long 0x00 "OTP_SHADOW[220],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x374++0x03
line.long 0x00 "OTP_SHADOW[221],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x378++0x03
line.long 0x00 "OTP_SHADOW[222],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x37C++0x03
line.long 0x00 "OTP_SHADOW[223],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x380++0x03
line.long 0x00 "OTP_SHADOW[224],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x384++0x03
line.long 0x00 "OTP_SHADOW[225],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x388++0x03
line.long 0x00 "OTP_SHADOW[226],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x38C++0x03
line.long 0x00 "OTP_SHADOW[227],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x390++0x03
line.long 0x00 "OTP_SHADOW[228],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x394++0x03
line.long 0x00 "OTP_SHADOW[229],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x398++0x03
line.long 0x00 "OTP_SHADOW[230],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x39C++0x03
line.long 0x00 "OTP_SHADOW[231],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3A0++0x03
line.long 0x00 "OTP_SHADOW[232],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3A4++0x03
line.long 0x00 "OTP_SHADOW[233],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3A8++0x03
line.long 0x00 "OTP_SHADOW[234],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3AC++0x03
line.long 0x00 "OTP_SHADOW[235],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3B0++0x03
line.long 0x00 "OTP_SHADOW[236],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3B4++0x03
line.long 0x00 "OTP_SHADOW[237],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3B8++0x03
line.long 0x00 "OTP_SHADOW[238],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3BC++0x03
line.long 0x00 "OTP_SHADOW[239],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3C0++0x03
line.long 0x00 "OTP_SHADOW[240],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3C4++0x03
line.long 0x00 "OTP_SHADOW[241],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3C8++0x03
line.long 0x00 "OTP_SHADOW[242],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3CC++0x03
line.long 0x00 "OTP_SHADOW[243],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3D0++0x03
line.long 0x00 "OTP_SHADOW[244],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3D4++0x03
line.long 0x00 "OTP_SHADOW[245],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3D8++0x03
line.long 0x00 "OTP_SHADOW[246],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3DC++0x03
line.long 0x00 "OTP_SHADOW[247],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3E0++0x03
line.long 0x00 "OTP_SHADOW[248],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3E4++0x03
line.long 0x00 "OTP_SHADOW[249],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3E8++0x03
line.long 0x00 "OTP_SHADOW[250],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3EC++0x03
line.long 0x00 "OTP_SHADOW[251],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3F0++0x03
line.long 0x00 "OTP_SHADOW[252],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3F4++0x03
line.long 0x00 "OTP_SHADOW[253],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3F8++0x03
line.long 0x00 "OTP_SHADOW[254],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x3FC++0x03
line.long 0x00 "OTP_SHADOW[255],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x400++0x03
line.long 0x00 "OTP_SHADOW[256],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x404++0x03
line.long 0x00 "OTP_SHADOW[257],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x408++0x03
line.long 0x00 "OTP_SHADOW[258],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x40C++0x03
line.long 0x00 "OTP_SHADOW[259],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x410++0x03
line.long 0x00 "OTP_SHADOW[260],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x414++0x03
line.long 0x00 "OTP_SHADOW[261],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x418++0x03
line.long 0x00 "OTP_SHADOW[262],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x41C++0x03
line.long 0x00 "OTP_SHADOW[263],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x420++0x03
line.long 0x00 "OTP_SHADOW[264],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x424++0x03
line.long 0x00 "OTP_SHADOW[265],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x428++0x03
line.long 0x00 "OTP_SHADOW[266],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x42C++0x03
line.long 0x00 "OTP_SHADOW[267],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x430++0x03
line.long 0x00 "OTP_SHADOW[268],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x434++0x03
line.long 0x00 "OTP_SHADOW[269],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x438++0x03
line.long 0x00 "OTP_SHADOW[270],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x43C++0x03
line.long 0x00 "OTP_SHADOW[271],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x440++0x03
line.long 0x00 "OTP_SHADOW[272],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x444++0x03
line.long 0x00 "OTP_SHADOW[273],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x448++0x03
line.long 0x00 "OTP_SHADOW[274],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x44C++0x03
line.long 0x00 "OTP_SHADOW[275],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x450++0x03
line.long 0x00 "OTP_SHADOW[276],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x454++0x03
line.long 0x00 "OTP_SHADOW[277],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x458++0x03
line.long 0x00 "OTP_SHADOW[278],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x45C++0x03
line.long 0x00 "OTP_SHADOW[279],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x460++0x03
line.long 0x00 "OTP_SHADOW[280],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x464++0x03
line.long 0x00 "OTP_SHADOW[281],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x468++0x03
line.long 0x00 "OTP_SHADOW[282],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x46C++0x03
line.long 0x00 "OTP_SHADOW[283],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x470++0x03
line.long 0x00 "OTP_SHADOW[284],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x474++0x03
line.long 0x00 "OTP_SHADOW[285],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x478++0x03
line.long 0x00 "OTP_SHADOW[286],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x47C++0x03
line.long 0x00 "OTP_SHADOW[287],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x480++0x03
line.long 0x00 "OTP_SHADOW[288],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x484++0x03
line.long 0x00 "OTP_SHADOW[289],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x488++0x03
line.long 0x00 "OTP_SHADOW[290],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x48C++0x03
line.long 0x00 "OTP_SHADOW[291],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x490++0x03
line.long 0x00 "OTP_SHADOW[292],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x494++0x03
line.long 0x00 "OTP_SHADOW[293],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x498++0x03
line.long 0x00 "OTP_SHADOW[294],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x49C++0x03
line.long 0x00 "OTP_SHADOW[295],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4A0++0x03
line.long 0x00 "OTP_SHADOW[296],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4A4++0x03
line.long 0x00 "OTP_SHADOW[297],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4A8++0x03
line.long 0x00 "OTP_SHADOW[298],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4AC++0x03
line.long 0x00 "OTP_SHADOW[299],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4B0++0x03
line.long 0x00 "OTP_SHADOW[300],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4B4++0x03
line.long 0x00 "OTP_SHADOW[301],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4B8++0x03
line.long 0x00 "OTP_SHADOW[302],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4BC++0x03
line.long 0x00 "OTP_SHADOW[303],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4C0++0x03
line.long 0x00 "OTP_SHADOW[304],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4C4++0x03
line.long 0x00 "OTP_SHADOW[305],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4C8++0x03
line.long 0x00 "OTP_SHADOW[306],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4CC++0x03
line.long 0x00 "OTP_SHADOW[307],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4D0++0x03
line.long 0x00 "OTP_SHADOW[308],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4D4++0x03
line.long 0x00 "OTP_SHADOW[309],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4D8++0x03
line.long 0x00 "OTP_SHADOW[310],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4DC++0x03
line.long 0x00 "OTP_SHADOW[311],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4E0++0x03
line.long 0x00 "OTP_SHADOW[312],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4E4++0x03
line.long 0x00 "OTP_SHADOW[313],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4E8++0x03
line.long 0x00 "OTP_SHADOW[314],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4EC++0x03
line.long 0x00 "OTP_SHADOW[315],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4F0++0x03
line.long 0x00 "OTP_SHADOW[316],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4F4++0x03
line.long 0x00 "OTP_SHADOW[317],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4F8++0x03
line.long 0x00 "OTP_SHADOW[318],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x4FC++0x03
line.long 0x00 "OTP_SHADOW[319],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x500++0x03
line.long 0x00 "OTP_SHADOW[320],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x504++0x03
line.long 0x00 "OTP_SHADOW[321],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x508++0x03
line.long 0x00 "OTP_SHADOW[322],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x50C++0x03
line.long 0x00 "OTP_SHADOW[323],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x510++0x03
line.long 0x00 "OTP_SHADOW[324],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x514++0x03
line.long 0x00 "OTP_SHADOW[325],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x518++0x03
line.long 0x00 "OTP_SHADOW[326],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x51C++0x03
line.long 0x00 "OTP_SHADOW[327],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x520++0x03
line.long 0x00 "OTP_SHADOW[328],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x524++0x03
line.long 0x00 "OTP_SHADOW[329],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x528++0x03
line.long 0x00 "OTP_SHADOW[330],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x52C++0x03
line.long 0x00 "OTP_SHADOW[331],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x530++0x03
line.long 0x00 "OTP_SHADOW[332],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x534++0x03
line.long 0x00 "OTP_SHADOW[333],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x538++0x03
line.long 0x00 "OTP_SHADOW[334],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x53C++0x03
line.long 0x00 "OTP_SHADOW[335],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x540++0x03
line.long 0x00 "OTP_SHADOW[336],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x544++0x03
line.long 0x00 "OTP_SHADOW[337],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x548++0x03
line.long 0x00 "OTP_SHADOW[338],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x54C++0x03
line.long 0x00 "OTP_SHADOW[339],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x550++0x03
line.long 0x00 "OTP_SHADOW[340],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x554++0x03
line.long 0x00 "OTP_SHADOW[341],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x558++0x03
line.long 0x00 "OTP_SHADOW[342],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x55C++0x03
line.long 0x00 "OTP_SHADOW[343],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x560++0x03
line.long 0x00 "OTP_SHADOW[344],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x564++0x03
line.long 0x00 "OTP_SHADOW[345],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x568++0x03
line.long 0x00 "OTP_SHADOW[346],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x56C++0x03
line.long 0x00 "OTP_SHADOW[347],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x570++0x03
line.long 0x00 "OTP_SHADOW[348],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x574++0x03
line.long 0x00 "OTP_SHADOW[349],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x578++0x03
line.long 0x00 "OTP_SHADOW[350],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x57C++0x03
line.long 0x00 "OTP_SHADOW[351],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x580++0x03
line.long 0x00 "OTP_SHADOW[352],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x584++0x03
line.long 0x00 "OTP_SHADOW[353],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x588++0x03
line.long 0x00 "OTP_SHADOW[354],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x58C++0x03
line.long 0x00 "OTP_SHADOW[355],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x590++0x03
line.long 0x00 "OTP_SHADOW[356],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x594++0x03
line.long 0x00 "OTP_SHADOW[357],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x598++0x03
line.long 0x00 "OTP_SHADOW[358],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x59C++0x03
line.long 0x00 "OTP_SHADOW[359],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5A0++0x03
line.long 0x00 "OTP_SHADOW[360],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5A4++0x03
line.long 0x00 "OTP_SHADOW[361],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5A8++0x03
line.long 0x00 "OTP_SHADOW[362],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5AC++0x03
line.long 0x00 "OTP_SHADOW[363],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5B0++0x03
line.long 0x00 "OTP_SHADOW[364],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5B4++0x03
line.long 0x00 "OTP_SHADOW[365],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5B8++0x03
line.long 0x00 "OTP_SHADOW[366],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5BC++0x03
line.long 0x00 "OTP_SHADOW[367],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5C0++0x03
line.long 0x00 "OTP_SHADOW[368],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5C4++0x03
line.long 0x00 "OTP_SHADOW[369],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5C8++0x03
line.long 0x00 "OTP_SHADOW[370],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5CC++0x03
line.long 0x00 "OTP_SHADOW[371],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5D0++0x03
line.long 0x00 "OTP_SHADOW[372],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5D4++0x03
line.long 0x00 "OTP_SHADOW[373],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5D8++0x03
line.long 0x00 "OTP_SHADOW[374],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5DC++0x03
line.long 0x00 "OTP_SHADOW[375],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5E0++0x03
line.long 0x00 "OTP_SHADOW[376],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5E4++0x03
line.long 0x00 "OTP_SHADOW[377],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5E8++0x03
line.long 0x00 "OTP_SHADOW[378],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5EC++0x03
line.long 0x00 "OTP_SHADOW[379],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5F0++0x03
line.long 0x00 "OTP_SHADOW[380],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5F4++0x03
line.long 0x00 "OTP_SHADOW[381],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5F8++0x03
line.long 0x00 "OTP_SHADOW[382],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x5FC++0x03
line.long 0x00 "OTP_SHADOW[383],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x600++0x03
line.long 0x00 "OTP_SHADOW[384],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x604++0x03
line.long 0x00 "OTP_SHADOW[385],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x608++0x03
line.long 0x00 "OTP_SHADOW[386],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x60C++0x03
line.long 0x00 "OTP_SHADOW[387],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x610++0x03
line.long 0x00 "OTP_SHADOW[388],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x614++0x03
line.long 0x00 "OTP_SHADOW[389],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x618++0x03
line.long 0x00 "OTP_SHADOW[390],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x61C++0x03
line.long 0x00 "OTP_SHADOW[391],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x620++0x03
line.long 0x00 "OTP_SHADOW[392],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x624++0x03
line.long 0x00 "OTP_SHADOW[393],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x628++0x03
line.long 0x00 "OTP_SHADOW[394],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x62C++0x03
line.long 0x00 "OTP_SHADOW[395],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x630++0x03
line.long 0x00 "OTP_SHADOW[396],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x634++0x03
line.long 0x00 "OTP_SHADOW[397],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x638++0x03
line.long 0x00 "OTP_SHADOW[398],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x63C++0x03
line.long 0x00 "OTP_SHADOW[399],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x640++0x03
line.long 0x00 "OTP_SHADOW[400],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x644++0x03
line.long 0x00 "OTP_SHADOW[401],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x648++0x03
line.long 0x00 "OTP_SHADOW[402],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x64C++0x03
line.long 0x00 "OTP_SHADOW[403],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x650++0x03
line.long 0x00 "OTP_SHADOW[404],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x654++0x03
line.long 0x00 "OTP_SHADOW[405],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x658++0x03
line.long 0x00 "OTP_SHADOW[406],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x65C++0x03
line.long 0x00 "OTP_SHADOW[407],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x660++0x03
line.long 0x00 "OTP_SHADOW[408],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x664++0x03
line.long 0x00 "OTP_SHADOW[409],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x668++0x03
line.long 0x00 "OTP_SHADOW[410],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x66C++0x03
line.long 0x00 "OTP_SHADOW[411],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x670++0x03
line.long 0x00 "OTP_SHADOW[412],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x674++0x03
line.long 0x00 "OTP_SHADOW[413],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x678++0x03
line.long 0x00 "OTP_SHADOW[414],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x67C++0x03
line.long 0x00 "OTP_SHADOW[415],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x680++0x03
line.long 0x00 "OTP_SHADOW[416],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x684++0x03
line.long 0x00 "OTP_SHADOW[417],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x688++0x03
line.long 0x00 "OTP_SHADOW[418],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x68C++0x03
line.long 0x00 "OTP_SHADOW[419],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x690++0x03
line.long 0x00 "OTP_SHADOW[420],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x694++0x03
line.long 0x00 "OTP_SHADOW[421],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x698++0x03
line.long 0x00 "OTP_SHADOW[422],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x69C++0x03
line.long 0x00 "OTP_SHADOW[423],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6A0++0x03
line.long 0x00 "OTP_SHADOW[424],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6A4++0x03
line.long 0x00 "OTP_SHADOW[425],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6A8++0x03
line.long 0x00 "OTP_SHADOW[426],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6AC++0x03
line.long 0x00 "OTP_SHADOW[427],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6B0++0x03
line.long 0x00 "OTP_SHADOW[428],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6B4++0x03
line.long 0x00 "OTP_SHADOW[429],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6B8++0x03
line.long 0x00 "OTP_SHADOW[430],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6BC++0x03
line.long 0x00 "OTP_SHADOW[431],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6C0++0x03
line.long 0x00 "OTP_SHADOW[432],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6C4++0x03
line.long 0x00 "OTP_SHADOW[433],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6C8++0x03
line.long 0x00 "OTP_SHADOW[434],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6CC++0x03
line.long 0x00 "OTP_SHADOW[435],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6D0++0x03
line.long 0x00 "OTP_SHADOW[436],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6D4++0x03
line.long 0x00 "OTP_SHADOW[437],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6D8++0x03
line.long 0x00 "OTP_SHADOW[438],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6DC++0x03
line.long 0x00 "OTP_SHADOW[439],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6E0++0x03
line.long 0x00 "OTP_SHADOW[440],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6E4++0x03
line.long 0x00 "OTP_SHADOW[441],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6E8++0x03
line.long 0x00 "OTP_SHADOW[442],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6EC++0x03
line.long 0x00 "OTP_SHADOW[443],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6F0++0x03
line.long 0x00 "OTP_SHADOW[444],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6F4++0x03
line.long 0x00 "OTP_SHADOW[445],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6F8++0x03
line.long 0x00 "OTP_SHADOW[446],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x6FC++0x03
line.long 0x00 "OTP_SHADOW[447],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x700++0x03
line.long 0x00 "OTP_SHADOW[448],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x704++0x03
line.long 0x00 "OTP_SHADOW[449],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x708++0x03
line.long 0x00 "OTP_SHADOW[450],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x70C++0x03
line.long 0x00 "OTP_SHADOW[451],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x710++0x03
line.long 0x00 "OTP_SHADOW[452],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x714++0x03
line.long 0x00 "OTP_SHADOW[453],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x718++0x03
line.long 0x00 "OTP_SHADOW[454],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x71C++0x03
line.long 0x00 "OTP_SHADOW[455],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x720++0x03
line.long 0x00 "OTP_SHADOW[456],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x724++0x03
line.long 0x00 "OTP_SHADOW[457],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x728++0x03
line.long 0x00 "OTP_SHADOW[458],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x72C++0x03
line.long 0x00 "OTP_SHADOW[459],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x730++0x03
line.long 0x00 "OTP_SHADOW[460],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x734++0x03
line.long 0x00 "OTP_SHADOW[461],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x738++0x03
line.long 0x00 "OTP_SHADOW[462],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x73C++0x03
line.long 0x00 "OTP_SHADOW[463],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x740++0x03
line.long 0x00 "OTP_SHADOW[464],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x744++0x03
line.long 0x00 "OTP_SHADOW[465],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x748++0x03
line.long 0x00 "OTP_SHADOW[466],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x74C++0x03
line.long 0x00 "OTP_SHADOW[467],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x750++0x03
line.long 0x00 "OTP_SHADOW[468],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x754++0x03
line.long 0x00 "OTP_SHADOW[469],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x758++0x03
line.long 0x00 "OTP_SHADOW[470],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x75C++0x03
line.long 0x00 "OTP_SHADOW[471],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x760++0x03
line.long 0x00 "OTP_SHADOW[472],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x764++0x03
line.long 0x00 "OTP_SHADOW[473],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x768++0x03
line.long 0x00 "OTP_SHADOW[474],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x76C++0x03
line.long 0x00 "OTP_SHADOW[475],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x770++0x03
line.long 0x00 "OTP_SHADOW[476],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x774++0x03
line.long 0x00 "OTP_SHADOW[477],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x778++0x03
line.long 0x00 "OTP_SHADOW[478],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x77C++0x03
line.long 0x00 "OTP_SHADOW[479],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x780++0x03
line.long 0x00 "OTP_SHADOW[480],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x784++0x03
line.long 0x00 "OTP_SHADOW[481],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x788++0x03
line.long 0x00 "OTP_SHADOW[482],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x78C++0x03
line.long 0x00 "OTP_SHADOW[483],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x790++0x03
line.long 0x00 "OTP_SHADOW[484],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x794++0x03
line.long 0x00 "OTP_SHADOW[485],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x798++0x03
line.long 0x00 "OTP_SHADOW[486],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x79C++0x03
line.long 0x00 "OTP_SHADOW[487],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7A0++0x03
line.long 0x00 "OTP_SHADOW[488],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7A4++0x03
line.long 0x00 "OTP_SHADOW[489],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7A8++0x03
line.long 0x00 "OTP_SHADOW[490],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7AC++0x03
line.long 0x00 "OTP_SHADOW[491],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7B0++0x03
line.long 0x00 "OTP_SHADOW[492],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7B4++0x03
line.long 0x00 "OTP_SHADOW[493],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7B8++0x03
line.long 0x00 "OTP_SHADOW[494],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x7BC++0x03
line.long 0x00 "OTP_SHADOW[495],OTP shadow register N"
hexmask.long 0x00 0.--31. 1. " shadow         ,OTP shadow register"
group.long 0x800++0x03
line.long 0x00 "OTP_CTRL,Control/address register"
hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK      ,Write 0x3E77 to enable OTP write accesses"
textline "                          "
bitfld.long 0x00 15. " WORDLOCK       ,Set to write-lock the fuse word when it's being programming" "0,1"
textline "                          "
bitfld.long 0x00 12. " CRC_TEST       ,Set to start CRC calculation" "0,1"
textline "                          "
bitfld.long 0x00 11. " RELOAD_SHADOWS ,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
textline "                          "
hexmask.long.word 0x00 0.--8. 1. " ADDR           ,OTP word address for read/programming"
group.long 0x804++0x03
line.long 0x00 "OTP_PDN,Power-down register"
bitfld.long 0x00 0. " PDN            ,This bit indicates the PDN value of OTP memory" "0,1"
rgroup.long 0x808++0x03
line.long 0x00 "OTP_WRITE_DATA,OTP programming data register"
hexmask.long 0x00 0.--31. 1. " WRITE_DATA     ,Fuse word programming data"
group.long 0x80C++0x03
line.long 0x00 "OTP_READ_CTRL,OTP read start register"
bitfld.long 0x00 0. " READ           ,no description available" "0,1"
rgroup.long 0x810++0x03
line.long 0x00 "OTP_READ_DATA,OTP read data register"
hexmask.long 0x00 0.--31. 1. " READ_DATA      ,Fuse word read data from read operation"
group.long 0x814++0x03
line.long 0x00 "OTP_CLK_DIV,OTP clock divider register"
rbitfld.long 0x00 31. " REQFLAG        ,Divider status flag" "0,1"
textline "                          "
bitfld.long 0x00 30. " HALT           ,Halts the divider counter" "0,1"
textline "                          "
bitfld.long 0x00 29. " RESET          ,Resets the divider counter" "0,1"
textline "                          "
bitfld.long 0x00 0.--3. " DIV            ,Clock divider value by -1 encoding" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
group.long 0x81C++0x03
line.long 0x00 "OTP_CRC_ADDR,CRC address range register"
bitfld.long 0x00 24.--26. " CRC_REF_ADDR   ,Specify which of the 8 CRC reference value to use for CRC calculation" "0,1,2,3,4,5,6,7"
textline "                          "
hexmask.long.word 0x00 12.--20. 1. " CRC_END_ADDR   ,CRC ending fuse word address"
textline "                          "
hexmask.long.word 0x00 0.--8. 1. " CRC_START_ADDR ,CRC starting fuse word address"
group.long 0x820++0x03
line.long 0x00 "OTP_CRC_VALUE,CRC result register"
hexmask.long 0x00 0.--31. 1. " CRC_VALUE      ,The CRC result value"
group.long 0x824++0x03
line.long 0x00 "OTP_STATUS,Status register"
rbitfld.long 0x00 25. " FUSE_LATCHED   ,Indicate all shadows registers have been loaded with their corresponding fuse words when set by the .." "0,1"
textline "                          "
bitfld.long 0x00 24. " CRC_FAIL       ,CRC failed when set by hardware for CRC operation" "0,1"
textline "                          "
bitfld.long 0x00 23. " ERROR          ,Set by the controller when a read/write access to a locked region (OTP or shadow register) is reques.." "0,1"
textline "                          "
rbitfld.long 0x00 22. " BUSY           ,OTP controller status bit" "0,1"
textline "                          "
bitfld.long 0x00 21. " DED_RELOAD     ,OTP Double Error Detect status of ECC during reload process" "0,1"
textline "                          "
bitfld.long 0x00 20. " SEC_RELOAD     ,OTP Single Error Corrected status of ECC during reload process" "0,1"
textline "                          "
rbitfld.long 0x00 14. " PWOK           ,OTP Power OK status" "0,1"
textline "                          "
rbitfld.long 0x00 13. " ACK            ,OTP ACK value" "0,1"
textline "                          "
bitfld.long 0x00 12. " PROGFAIL       ,OTP PROGFAIL status" "0,1"
textline "                          "
bitfld.long 0x00 11. " LOCKED         ,OTP LOCKED status during read/write operation" "0,1"
textline "                          "
bitfld.long 0x00 10. " DED            ,OTP Double Error Detection status of ECC during read operation" "0,1"
textline "                          "
bitfld.long 0x00 9. " SEC            ,OTP Single Error Corrected status of ECC during read operation" "0,1"
rgroup.long 0x82C++0x03
line.long 0x00 "OTP_VERSION,VERSION ID register"
hexmask.long.byte 0x00 24.--31. 1. " MAJOR_VER      ,OTP controller major version"
textline "                          "
hexmask.long.byte 0x00 16.--23. 1. " MINOR_VER      ,OTP controller minor version"
textline "                          "
hexmask.long.word 0x00 0.--15. 1. " STEP_VER       ,OTP controller step version"
width 0x0B
tree.end
tree "OSTIMER"
tree "OSTIMER0"
base ad:0x40113000
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "EVTIMERL,EVTIMER Low Register"
hexmask.long 0x00 0.--31. 1. " EVTIMER_COUNT_VALUE ,A read reflects the current value of the lower 32 bits of the EVTIMER"
rgroup.long 0x04++0x03
line.long 0x00 "EVTIMERH,EVTIMER High Register"
hexmask.long 0x00 0.--31. 1. " EVTIMER_COUNT_VALUE ,A read reflects the current value of the upper 32 bits of the EVTIMER"
rgroup.long 0x08++0x03
line.long 0x00 "CAPTUREn_L,Local Capture Low Register for CPUn"
hexmask.long 0x00 0.--31. 1. " CAPTUREn_VALUE      ,A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture s.."
rgroup.long 0x0C++0x03
line.long 0x00 "CAPTUREn_H,Local Capture High Register for CPUn"
hexmask.long 0x00 0.--31. 1. " CAPTUREn_VALUE      ,A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture s.."
group.long 0x10++0x03
line.long 0x00 "MATCHn_L,Local Match Low Register for CPUn"
hexmask.long 0x00 0.--31. 1. " MATCHn_VALUE        ,The value written to the MATCH (L/H) register pair is compared against the central EVTIMER"
group.long 0x14++0x03
line.long 0x00 "MATCHn_H,Match High Register for CPUn"
hexmask.long 0x00 0.--31. 1. " MATCHn_VALUE        ,The value written to the MATCH (L/H) register pair is compared against the central EVTIMER"
group.long 0x1C++0x03
line.long 0x00 "OSEVENT_CTRL,OS_EVENT TIMER Control Register for CPUn"
bitfld.long 0x00 2. " MATCH_WR_RDYn       ,This bit will be low when it is safe to write to reload the Match Registers" "0,1"
textline "                       "
bitfld.long 0x00 1. " OSTIMER_INTENA      ,When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the .." "0,1"
textline "                       "
bitfld.long 0x00 0. " OSTIMER_INTRFLAG    ,This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in t.." "0,1"
width 0x0B
tree.end
tree.end
tree "OTFAD"
base ad:0x40134000
width 4.
group.long 0xC00++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 31. " GE    ,Global OTFAD Enable" "0: OTFAD has decryption disabled,1: OTFAD has decryption enabled. and processes data fetched by the FLEXSPI as defined by the hardware c.."
textline "             "
bitfld.long 0x00 7. " RRAE  ,Restricted Register Access Enable" "0: Register access is fully enabled,1: Register access is restricted and only the CR. SR and optional MDPC registers can be accessed. other.."
textline "             "
bitfld.long 0x00 3. " FLDM  ,Force Logically Disabled Mode" "0: No effect on the operating mode,1: Force entry into LDM after a write with this data bit set"
rgroup.long 0xC04++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 29. " GEM   ,Global Enable Mode" "0: OTFAD is disabled,1: OTFAD is enabled. and processes data fetched by the FLEXSPI as defined by the hardware configuration"
textline "             "
bitfld.long 0x00 28. " RRAM  ,Restricted Register Access Mode" "0: Register access is fully enabled,1: Register access is restricted and only the CR. SR and optional MDPC registers can be accessed. other.."
textline "             "
bitfld.long 0x00 24.--27. " HRL   ,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "             "
bitfld.long 0x00 4.--7. " NCTX  ,Number of Contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "             "
bitfld.long 0x00 2.--3. " MODE  ,Operating Mode" "0: Operating in Normal mode (NRM),1: Unused (reserved),2: Unused (reserved),3: Operating in Logically Disabled Mode (LDM)"
textline "             "
bitfld.long 0x00 1. " MDPCP ,MDPC Present" "0,1"
tree "CTX[0]"
width 12.
group.long 0xD00++0x03
line.long 0x00 "CTX_KEY0,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD04++0x03
line.long 0x00 "CTX_KEY1,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD08++0x03
line.long 0x00 "CTX_KEY2,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD0C++0x03
line.long 0x00 "CTX_KEY3,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD10++0x03
line.long 0x00 "CTX_CTR0,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD14++0x03
line.long 0x00 "CTX_CTR1,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD18++0x03
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
hexmask.long.tbyte 0x00 10.--31. 1. " SRTADDR ,Start Address"
group.long 0xD1C++0x03
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
hexmask.long.tbyte 0x00 10.--31. 1. " ENDADDR ,End Address"
textline "                     "
bitfld.long 0x00 2. " RO      ,Read-Only" "0: The context registers can be accessed normally (as defined by SR[RRAM]),1: The context registers are read-only and accesses may be further restricted based on SR[RRAM]"
textline "                     "
bitfld.long 0x00 1. " ADE     ,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the fetched data"
textline "                     "
bitfld.long 0x00 0. " VLD     ,Valid" "0: Context is invalid,1: Context is valid"
tree.end
tree "CTX[1]"
width 12.
group.long 0xD40++0x03
line.long 0x00 "CTX_KEY0,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD44++0x03
line.long 0x00 "CTX_KEY1,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD48++0x03
line.long 0x00 "CTX_KEY2,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD4C++0x03
line.long 0x00 "CTX_KEY3,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD50++0x03
line.long 0x00 "CTX_CTR0,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD54++0x03
line.long 0x00 "CTX_CTR1,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD58++0x03
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
hexmask.long.tbyte 0x00 10.--31. 1. " SRTADDR ,Start Address"
group.long 0xD5C++0x03
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
hexmask.long.tbyte 0x00 10.--31. 1. " ENDADDR ,End Address"
textline "                     "
bitfld.long 0x00 2. " RO      ,Read-Only" "0: The context registers can be accessed normally (as defined by SR[RRAM]),1: The context registers are read-only and accesses may be further restricted based on SR[RRAM]"
textline "                     "
bitfld.long 0x00 1. " ADE     ,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the fetched data"
textline "                     "
bitfld.long 0x00 0. " VLD     ,Valid" "0: Context is invalid,1: Context is valid"
tree.end
tree "CTX[2]"
width 12.
group.long 0xD80++0x03
line.long 0x00 "CTX_KEY0,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD84++0x03
line.long 0x00 "CTX_KEY1,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD88++0x03
line.long 0x00 "CTX_KEY2,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD8C++0x03
line.long 0x00 "CTX_KEY3,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xD90++0x03
line.long 0x00 "CTX_CTR0,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD94++0x03
line.long 0x00 "CTX_CTR1,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xD98++0x03
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
hexmask.long.tbyte 0x00 10.--31. 1. " SRTADDR ,Start Address"
group.long 0xD9C++0x03
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
hexmask.long.tbyte 0x00 10.--31. 1. " ENDADDR ,End Address"
textline "                     "
bitfld.long 0x00 2. " RO      ,Read-Only" "0: The context registers can be accessed normally (as defined by SR[RRAM]),1: The context registers are read-only and accesses may be further restricted based on SR[RRAM]"
textline "                     "
bitfld.long 0x00 1. " ADE     ,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the fetched data"
textline "                     "
bitfld.long 0x00 0. " VLD     ,Valid" "0: Context is invalid,1: Context is valid"
tree.end
tree "CTX[3]"
width 12.
group.long 0xDC0++0x03
line.long 0x00 "CTX_KEY0,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xDC4++0x03
line.long 0x00 "CTX_KEY1,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xDC8++0x03
line.long 0x00 "CTX_KEY2,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xDCC++0x03
line.long 0x00 "CTX_KEY3,AES Key Word"
hexmask.long 0x00 0.--31. 1. " KEY     ,AES Key"
group.long 0xDD0++0x03
line.long 0x00 "CTX_CTR0,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xDD4++0x03
line.long 0x00 "CTX_CTR1,AES Counter Word"
hexmask.long 0x00 0.--31. 1. " CTR     ,AES Counter"
group.long 0xDD8++0x03
line.long 0x00 "CTX_RGD_W0,AES Region Descriptor Word0"
hexmask.long.tbyte 0x00 10.--31. 1. " SRTADDR ,Start Address"
group.long 0xDDC++0x03
line.long 0x00 "CTX_RGD_W1,AES Region Descriptor Word1"
hexmask.long.tbyte 0x00 10.--31. 1. " ENDADDR ,End Address"
textline "                     "
bitfld.long 0x00 2. " RO      ,Read-Only" "0: The context registers can be accessed normally (as defined by SR[RRAM]),1: The context registers are read-only and accesses may be further restricted based on SR[RRAM]"
textline "                     "
bitfld.long 0x00 1. " ADE     ,AES Decryption Enable" "0: Bypass the fetched data,1: Perform the CTR-AES128 mode decryption on the fetched data"
textline "                     "
bitfld.long 0x00 0. " VLD     ,Valid" "0: Context is invalid,1: Context is valid"
tree.end
width 0x0B
tree.end
tree "PINT"
base ad:0x40025000
width 8.
group.long 0x00++0x03
line.long 0x00 "ISEL,Pin Interrupt Mode register"
hexmask.long.byte 0x00 0.--7. 1. " PMODE        ,Selects the interrupt mode for each pin interrupt"
group.long 0x04++0x03
line.long 0x00 "IENR,Pin interrupt level or rising edge interrupt enable register"
hexmask.long.byte 0x00 0.--7. 1. " ENRL         ,Enables the rising edge or level interrupt for each pin interrupt"
wgroup.long 0x08++0x03
line.long 0x00 "SIENR,Pin interrupt level or rising edge interrupt set register"
hexmask.long.byte 0x00 0.--7. 1. " SETENRL      ,Ones written to this address set bits in the IENR. thus enabling interrupts"
wgroup.long 0x0C++0x03
line.long 0x00 "CIENR,Pin interrupt level (rising edge interrupt) clear register"
hexmask.long.byte 0x00 0.--7. 1. " CENRL        ,Ones written to this address clear bits in the IENR. thus disabling the interrupts"
group.long 0x10++0x03
line.long 0x00 "IENF,Pin interrupt active level or falling edge interrupt enable register"
hexmask.long.byte 0x00 0.--7. 1. " ENAF         ,Enables the falling edge or configures the active level interrupt for each pin interrupt"
wgroup.long 0x14++0x03
line.long 0x00 "SIENF,Pin interrupt active level or falling edge interrupt set register"
hexmask.long.byte 0x00 0.--7. 1. " SETENAF      ,Ones written to this address set bits in the IENF. thus enabling interrupts"
wgroup.long 0x18++0x03
line.long 0x00 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
hexmask.long.byte 0x00 0.--7. 1. " CENAF        ,Ones written to this address clears bits in the IENF. thus disabling interrupts"
group.long 0x1C++0x03
line.long 0x00 "RISE,Pin interrupt rising edge register"
hexmask.long.byte 0x00 0.--7. 1. " RDET         ,Rising edge detect"
group.long 0x20++0x03
line.long 0x00 "FALL,Pin interrupt falling edge register"
hexmask.long.byte 0x00 0.--7. 1. " FDET         ,Falling edge detect"
group.long 0x24++0x03
line.long 0x00 "IST,Pin interrupt status register"
hexmask.long.byte 0x00 0.--7. 1. " PSTAT        ,Pin interrupt status"
group.long 0x28++0x03
line.long 0x00 "PMCTRL,Pattern match interrupt control register"
hexmask.long.byte 0x00 24.--31. 1. " PMAT         ,This field displays the current state of pattern matches"
textline "                 "
bitfld.long 0x00 1. " ENA_RXEV     ,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression eva.." "0: DISABLED,1: ENABLED"
textline "                 "
bitfld.long 0x00 0. " SEL_PMATCH   ,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the patter.." "0: PIN_INTERRUPT,1: PATTERN_MATCH"
group.long 0x2C++0x03
line.long 0x00 "PMSRC,Pattern match interrupt bit-slice source register"
bitfld.long 0x00 29.--31. " SRC7         ,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 26.--28. " SRC6         ,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 23.--25. " SRC5         ,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 20.--22. " SRC4         ,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 17.--19. " SRC3         ,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 14.--16. " SRC2         ,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 11.--13. " SRC1         ,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
textline "                 "
bitfld.long 0x00 8.--10. " SRC0         ,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
group.long 0x30++0x03
line.long 0x00 "PMCFG,Pattern match interrupt bit slice configuration register"
bitfld.long 0x00 29.--31. " CFG7         ,Specifies the match contribution condition for bit slice 7" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 26.--28. " CFG6         ,Specifies the match contribution condition for bit slice 6" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 23.--25. " CFG5         ,Specifies the match contribution condition for bit slice 5" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 20.--22. " CFG4         ,Specifies the match contribution condition for bit slice 4" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 17.--19. " CFG3         ,Specifies the match contribution condition for bit slice 3" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 14.--16. " CFG2         ,Specifies the match contribution condition for bit slice 2" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 11.--13. " CFG1         ,Specifies the match contribution condition for bit slice 1" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 8.--10. " CFG0         ,Specifies the match contribution condition for bit slice 0" "0: CONSTANT_HIGH,1: STICKY_RISING_EDGE,2: STICKY_FALLING_EDGE,3: Sticky rising or falling edge,4: HIGH_LEVEL,5: LOW_LEVEL,6: CONSTANT_ZERO,7: EVENT"
textline "                 "
bitfld.long 0x00 6. " PROD_ENDPTS6 ,Determines whether slice 6 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 5. " PROD_ENDPTS5 ,Determines whether slice 5 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 4. " PROD_ENDPTS4 ,Determines whether slice 4 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 3. " PROD_ENDPTS3 ,Determines whether slice 3 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 2. " PROD_ENDPTS2 ,Determines whether slice 2 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 1. " PROD_ENDPTS1 ,Determines whether slice 1 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
textline "                 "
bitfld.long 0x00 0. " PROD_ENDPTS0 ,Determines whether slice 0 is an endpoint" "0: NO_EFFECT,1: ENDPOINT"
width 0x0B
tree.end
tree "POWERQUAD"
base ad:0x40150000
width 12.
group.long 0x00++0x03
line.long 0x00 "OUTBASE,Base address register for output region"
hexmask.long 0x00 0.--31. 1. " outbase        ,Base address register for the output region"
group.long 0x04++0x03
line.long 0x00 "OUTFORMAT,Output format"
hexmask.long.byte 0x00 8.--15. 1. " out_scaler     ,Output Scaler value (for scaled 'q31' formats)"
textline "                     "
bitfld.long 0x00 4.--5. " out_formatext  ,Output External format (00: q15. 01:q31. 10:float)" "0,1,2,3"
textline "                     "
bitfld.long 0x00 0.--1. " out_formatint  ,Output Internal format (00: q15. 01:q31. 10:float)" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "TMPBASE,Base address register for temp region"
hexmask.long 0x00 0.--31. 1. " tmpbase        ,Base address register for the temporary region"
group.long 0x0C++0x03
line.long 0x00 "TMPFORMAT,Temp format"
hexmask.long.byte 0x00 8.--15. 1. " tmp_scaler     ,Temp Scaler value (for scaled 'q31' formats)"
textline "                     "
bitfld.long 0x00 4.--5. " tmp_formatext  ,Temp External format (00: q15. 01:q31. 10:float)" "0,1,2,3"
textline "                     "
bitfld.long 0x00 0.--1. " tmp_formatint  ,Temp Internal format (00: q15. 01:q31. 10:float)" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "INABASE,Base address register for input A region"
hexmask.long 0x00 0.--31. 1. " inabase        ,Base address register for the input A region"
group.long 0x14++0x03
line.long 0x00 "INAFORMAT,Input A format"
hexmask.long.byte 0x00 8.--15. 1. " ina_scaler     ,Input A Scaler value (for scaled 'q31' formats)"
textline "                     "
bitfld.long 0x00 4.--5. " ina_formatext  ,Input A External format (00: q15. 01:q31. 10:float)" "0,1,2,3"
textline "                     "
bitfld.long 0x00 0.--1. " ina_formatint  ,Input A Internal format (00: q15. 01:q31. 10:float)" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "INBBASE,Base address register for input B region"
hexmask.long 0x00 0.--31. 1. " inbbase        ,Base address register for the input B region"
group.long 0x1C++0x03
line.long 0x00 "INBFORMAT,Input B format"
hexmask.long.byte 0x00 8.--15. 1. " inb_scaler     ,Input B Scaler value (for scaled 'q31' formats)"
textline "                     "
bitfld.long 0x00 4.--5. " inb_formatext  ,Input B External format (00: q15. 01:q31. 10:float)" "0,1,2,3"
textline "                     "
bitfld.long 0x00 0.--1. " inb_formatint  ,Input B Internal format (00: q15. 01:q31. 10:float)" "0,1,2,3"
group.long 0x100++0x03
line.long 0x00 "CONTROL,PowerQuad Control register"
rbitfld.long 0x00 31. " inst_busy      ,Instruction busy signal when high indicates processing is on" "0,1"
textline "                     "
bitfld.long 0x00 4.--7. " decode_machine ,0 : Coprocessor . 1 : matrix . 2 : fft . 3 : fir . 4 : stat . 5 : cordic . 6 -15 : NA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 0.--3. " decode_opcode  ,opcode specific to decode_machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x03
line.long 0x00 "LENGTH,Length register"
hexmask.long 0x00 0.--31. 1. " inst_length    ,Length register"
group.long 0x108++0x03
line.long 0x00 "CPPRE,Pre-scale register"
bitfld.long 0x00 17. " cppre_sat8     ,0 = 8bits. 1 = 16bits" "0,1"
textline "                     "
bitfld.long 0x00 16. " cppre_sat      ,1 : forces sub-32 bit saturation" "0,1"
textline "                     "
hexmask.long.byte 0x00 8.--15. 1. " cppre_out      ,co-processor fixed point output"
textline "                     "
hexmask.long.byte 0x00 0.--7. 1. " cppre_in       ,co-processor scaling of input"
group.long 0x10C++0x03
line.long 0x00 "MISC,Misc register"
hexmask.long 0x00 0.--31. 1. " inst_misc      ,Misc register"
group.long 0x110++0x03
line.long 0x00 "CURSORY,Cursory register"
bitfld.long 0x00 0. " cursory        ,1 : Enable cursory mode" "0,1"
group.long 0x180++0x03
line.long 0x00 "CORDIC_X,Cordic input X register"
hexmask.long 0x00 0.--31. 1. " cordic_x       ,Cordic input x"
group.long 0x184++0x03
line.long 0x00 "CORDIC_Y,Cordic input Y register"
hexmask.long 0x00 0.--31. 1. " cordic_y       ,Cordic input y"
group.long 0x188++0x03
line.long 0x00 "CORDIC_Z,Cordic input Z register"
hexmask.long 0x00 0.--31. 1. " cordic_z       ,Cordic input z"
group.long 0x18C++0x03
line.long 0x00 "ERRSTAT,Read/Write register where error statuses are captured (sticky)"
bitfld.long 0x00 4. " BUSERROR       ,bus_error" "0,1"
textline "                     "
bitfld.long 0x00 3. " UNDERFLOW      ,underflow" "0,1"
textline "                     "
bitfld.long 0x00 2. " FIXEDOVERFLOW  ,fixed_pt_overflow" "0,1"
textline "                     "
bitfld.long 0x00 1. " NAN            ,nan" "0,1"
textline "                     "
bitfld.long 0x00 0. " OVERFLOW       ,overflow" "0,1"
group.long 0x190++0x03
line.long 0x00 "INTREN,INTERRUPT enable register"
bitfld.long 0x00 7. " intr_comp      ,1: Enable interrupt on instruction completion" "0,1"
textline "                     "
bitfld.long 0x00 4. " intr_berr      ,1: Enable interrupt on AHBM Buss Error" "0,1"
textline "                     "
bitfld.long 0x00 3. " intr_uflow     ,1 : Enable interrupt on Subnormal truncation" "0,1"
textline "                     "
bitfld.long 0x00 2. " intr_fixed     ,1: Enable interrupt on Fixed point Overflow" "0,1"
textline "                     "
bitfld.long 0x00 1. " intr_nan       ,1 : Enable interrupt on Floating point NaN" "0,1"
textline "                     "
bitfld.long 0x00 0. " intr_oflow     ,1 : Enable interrupt on Floating point overflow" "0,1"
group.long 0x194++0x03
line.long 0x00 "EVENTEN,Event Enable register"
bitfld.long 0x00 7. " event_comp     ,1: Enable event trigger on instruction completion" "0,1"
textline "                     "
bitfld.long 0x00 4. " event_berr     ,1: Enable event trigger on AHBM Buss Error" "0,1"
textline "                     "
bitfld.long 0x00 3. " event_uflow    ,1 : Enable event trigger on Subnormal truncation" "0,1"
textline "                     "
bitfld.long 0x00 2. " event_fixed    ,1: Enable event trigger on Fixed point Overflow" "0,1"
textline "                     "
bitfld.long 0x00 1. " event_nan      ,1 : Enable event trigger on Floating point NaN" "0,1"
textline "                     "
bitfld.long 0x00 0. " event_oflow    ,1 : Enable event trigger on Floating point overflow" "0,1"
group.long 0x198++0x03
line.long 0x00 "INTRSTAT,INTERRUPT STATUS register"
bitfld.long 0x00 0. " intr_stat      ,Intr status ( 1 bit to indicate interrupt captured. 0 means no new interrupt). write any value will .." "0,1"
group.long 0x200++0x03
line.long 0x00 "gpreg[0],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x204++0x03
line.long 0x00 "gpreg[1],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x208++0x03
line.long 0x00 "gpreg[2],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x20C++0x03
line.long 0x00 "gpreg[3],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x210++0x03
line.long 0x00 "gpreg[4],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x214++0x03
line.long 0x00 "gpreg[5],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x218++0x03
line.long 0x00 "gpreg[6],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x21C++0x03
line.long 0x00 "gpreg[7],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x220++0x03
line.long 0x00 "gpreg[8],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x224++0x03
line.long 0x00 "gpreg[9],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x228++0x03
line.long 0x00 "gpreg[10],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x22C++0x03
line.long 0x00 "gpreg[11],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x230++0x03
line.long 0x00 "gpreg[12],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x234++0x03
line.long 0x00 "gpreg[13],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x238++0x03
line.long 0x00 "gpreg[14],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x23C++0x03
line.long 0x00 "gpreg[15],General purpose register bank N"
hexmask.long 0x00 0.--31. 1. " gpreg          ,General purpose register bank"
group.long 0x240++0x03
line.long 0x00 "compreg[0],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x244++0x03
line.long 0x00 "compreg[1],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x248++0x03
line.long 0x00 "compreg[2],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x24C++0x03
line.long 0x00 "compreg[3],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x250++0x03
line.long 0x00 "compreg[4],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x254++0x03
line.long 0x00 "compreg[5],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x258++0x03
line.long 0x00 "compreg[6],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
group.long 0x25C++0x03
line.long 0x00 "compreg[7],Compute register bank"
hexmask.long 0x00 0.--31. 1. " compreg        ,Compute register bank"
width 0x0B
tree.end
tree "PUF"
base ad:0x40006000
width 13.
group.long 0x00++0x03
line.long 0x00 "CTRL,PUF Control"
bitfld.long 0x00 6. " GETKEY             ,Get Key" "0,1"
textline "                      "
bitfld.long 0x00 4. " SETKEY             ,Set Key" "0,1"
textline "                      "
bitfld.long 0x00 3. " GENERATEKEY        ,Set Intrinsic Key" "0,1"
textline "                      "
bitfld.long 0x00 2. " START              ,Start" "0,1"
textline "                      "
bitfld.long 0x00 1. " ENROLL             ,Enroll" "0,1"
textline "                      "
bitfld.long 0x00 0. " ZEROIZE            ,Zeroize" "0,1"
group.long 0x04++0x03
line.long 0x00 "KEYINDEX,PUF Key Index"
bitfld.long 0x00 0.--3. " KEYIDX             ,Key index for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "KEYSIZE,PUF Key Size"
bitfld.long 0x00 0.--5. " KEYSIZE            ,Key Size for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20++0x03
line.long 0x00 "STAT,PUF Status"
bitfld.long 0x00 7. " CODEOUTAVAIL       ,Code Out Available" "0,1"
textline "                      "
bitfld.long 0x00 6. " CODEINREQ          ,Code In Request" "0,1"
textline "                      "
bitfld.long 0x00 5. " KEYOUTAVAIL        ,Key Out Available" "0,1"
textline "                      "
bitfld.long 0x00 4. " KEYINREQ           ,Key In Request" "0,1"
textline "                      "
bitfld.long 0x00 2. " ERROR              ,Error" "0,1"
textline "                      "
bitfld.long 0x00 1. " SUCCESS            ,Success" "0,1"
textline "                      "
bitfld.long 0x00 0. " BUSY               ,Busy" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "ALLOW,PUF Allow"
bitfld.long 0x00 3. " ALLOWGETKEY        ,Allow Get Key" "0,1"
textline "                      "
bitfld.long 0x00 2. " ALLOWSETKEY        ,Allow Set Key" "0,1"
textline "                      "
bitfld.long 0x00 1. " ALLOWSTART         ,Allow Start" "0,1"
textline "                      "
bitfld.long 0x00 0. " ALLOWENROLL        ,Allow Enroll" "0,1"
wgroup.long 0x40++0x03
line.long 0x00 "KEYINPUT,PUF Key Input"
hexmask.long 0x00 0.--31. 1. " KEYIN              ,Key Input Data"
wgroup.long 0x44++0x03
line.long 0x00 "CODEINPUT,PUF Code Input"
hexmask.long 0x00 0.--31. 1. " CODEIN             ,AC/KC Input Data"
rgroup.long 0x48++0x03
line.long 0x00 "CODEOUTPUT,PUF Code Output"
hexmask.long 0x00 0.--31. 1. " CODEOUT            ,AC/KC Output Data"
rgroup.long 0x60++0x03
line.long 0x00 "KEYOUTINDEX,PUF Key Output Index"
bitfld.long 0x00 0.--3. " KEYOUTIDX          ,Key Output Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x64++0x03
line.long 0x00 "KEYOUTPUT,PUF Key Output"
hexmask.long 0x00 0.--31. 1. " KEYOUT             ,Key Output Data"
group.long 0xDC++0x03
line.long 0x00 "IFSTAT,PUF Interface Status and Clear"
eventfld.long 0x00 0. " ERROR              ,Error" "0,1"
rgroup.long 0xFC++0x03
line.long 0x00 "VERSION,PUF Version"
hexmask.long 0x00 0.--31. 1. " VERSION            ,Version"
group.long 0x100++0x03
line.long 0x00 "INTEN,PUF Interrupt Enable"
bitfld.long 0x00 7. " CODEOUTAVAILEN     ,Enable corresponding interrupt in STAT. which is next part of AC/KC is available" "0,1"
textline "                      "
bitfld.long 0x00 6. " CODEINREQEN        ,Enable corresponding interrupt in STAT. which is request for next part of AC/KC" "0,1"
textline "                      "
bitfld.long 0x00 5. " KEYOUTAVAILEN      ,Enable corresponding interrupt in STAT. which is next part of key is available" "0,1"
textline "                      "
bitfld.long 0x00 4. " KEYINREQEN         ,Enable corresponding interrupt in STAT. which is request for next part of key" "0,1"
textline "                      "
bitfld.long 0x00 2. " ERROREN            ,Enable corresponding interrupt in STAT. which indicates that PUF is in the error state and no operat.." "0,1"
textline "                      "
bitfld.long 0x00 1. " SUCCESEN           ,Enable corresponding interrupt in STAT. which indicates last operation was successful" "0,1"
textline "                      "
bitfld.long 0x00 0. " READYEN            ,Enable corresponding interrupt in STAT. which indicates that the initialization or a operation is co.." "0,1"
group.long 0x104++0x03
line.long 0x00 "INTSTAT,PUF Interrupt Status"
bitfld.long 0x00 7. " CODEOUTAVAIL       ,Code Out Available" "0,1"
textline "                      "
bitfld.long 0x00 6. " CODEINREQ          ,Code In Request" "0,1"
textline "                      "
bitfld.long 0x00 5. " KEYOUTAVAIL        ,Key Out Available" "0,1"
textline "                      "
bitfld.long 0x00 4. " KEYINREQ           ,Key In Request" "0,1"
textline "                      "
bitfld.long 0x00 2. " ERROR              ,Error" "0,1"
textline "                      "
bitfld.long 0x00 1. " SUCCESS            ,Success" "0,1"
textline "                      "
eventfld.long 0x00 0. " READY              ,Ready" "0,1"
group.long 0x108++0x03
line.long 0x00 "PWRCTRL,PUF Power Control"
bitfld.long 0x00 2. " CK_DIS             ,PUF Clock control" "0: PUF RAM clock is disabled,1: PUF RAM clock is enabled"
textline "                      "
bitfld.long 0x00 0. " RAM_ON             ,RAM Power On" "0: POWER_OFF,1: POWER_ON"
group.long 0x10C++0x03
line.long 0x00 "CFG,PUF Configuration"
bitfld.long 0x00 1. " BLOCKKEYOUTPUT     ,Block Key Output Data" "0: DISABLED,1: ENABLED"
textline "                      "
bitfld.long 0x00 0. " BLOCKENROLL_SETKEY ,Block Enroll and Set Key Operation" "0: DISABLED,1: ENABLED"
group.long 0x200++0x03
line.long 0x00 "KEYLOCK,Key Lock"
bitfld.long 0x00 6.--7. " KEY3               ,Key 3" "0: Write access to KEY3MASK. KEYENABLE[KEY3] and KEYRESET[KEY3] is NOT allowed,1: Write access to KEY3MASK. KEYENABLE[KEY3] and KEYRESET[KEY3] is NOT allowed,2: Write access to KEY3MASK. KEYENABLE[KEY3] and KEYRESET[KEY3] is allowed,3: Write access to KEY3MASK. KEYENABLE[KEY3] and KEYRESET[KEY3] is NOT allowed"
textline "                      "
bitfld.long 0x00 4.--5. " KEY2               ,Key 2" "0: Write access to KEY2MASK. KEYENABLE[KEY2] and KEYRESET[KEY2] is NOT allowed,1: Write access to KEY2MASK. KEYENABLE[KEY2] and KEYRESET[KEY2] is NOT allowed,2: Write access to KEY2MASK. KEYENABLE[KEY2] and KEYRESET[KEY2] is allowed,3: Write access to KEY2MASK. KEYENABLE[KEY2] and KEYRESET[KEY2] is NOT allowed"
textline "                      "
bitfld.long 0x00 2.--3. " KEY1               ,Key 1" "0: Write access to KEY1MASK. KEYENABLE[KEY1] and KEYRESET[KEY1] is NOT allowed,1: Write access to KEY1MASK. KEYENABLE[KEY1] and KEYRESET[KEY1] is NOT allowed,2: Write access to KEY1MASK. KEYENABLE[KEY1] and KEYRESET[KEY1] is allowed,3: Write access to KEY1MASK. KEYENABLE[KEY1] and KEYRESET[KEY1] is NOT allowed"
textline "                      "
bitfld.long 0x00 0.--1. " KEY0               ,Key 0" "0: Write access to KEY0MASK. KEYENABLE[KEY0] and KEYRESET[KEY0] is NOT allowed,1: Write access to KEY0MASK. KEYENABLE[KEY0] and KEYRESET[KEY0] is NOT allowed,2: Write access to KEY0MASK. KEYENABLE[KEY0] and KEYRESET[KEY0] is allowed,3: Write access to KEY0MASK. KEYENABLE[KEY0] and KEYRESET[KEY0] is NOT allowed"
group.long 0x204++0x03
line.long 0x00 "KEYENABLE,Key Enable"
bitfld.long 0x00 6.--7. " KEY3               ,Key 3" "0: Data coming from the PUF Index 0 interface are NOT shifted in the KEY3 register,1: Data coming from the PUF Index 0 interface are NOT shifted in the KEY3 register,2: Data coming from the PUF Index 0 interface are shifted in the KEY3 register,3: Data coming from the PUF Index 0 interface are NOT shifted in the KEY3 register"
textline "                      "
bitfld.long 0x00 4.--5. " KEY2               ,Key 2" "0: Data coming from the PUF Index 0 interface are NOT shifted in the KEY2 register,1: Data coming from the PUF Index 0 interface are NOT shifted in the KEY2 register,2: Data coming from the PUF Index 0 interface are shifted in the KEY2 register,3: Data coming from the PUF Index 0 interface are NOT shifted in the KEY2 register"
textline "                      "
bitfld.long 0x00 2.--3. " KEY1               ,Key 1" "0: Data coming from the PUF Index 0 interface are NOT shifted in the KEY1 register,1: Data coming from the PUF Index 0 interface are NOT shifted in the KEY1 register,2: Data coming from the PUF Index 0 interface are shifted in the KEY1 register,3: Data coming from the PUF Index 0 interface are NOT shifted in the KEY1 register"
textline "                      "
bitfld.long 0x00 0.--1. " KEY0               ,Key 0" "0: Data coming from the PUF Index 0 interface are NOT shifted in the KEY0 register,1: Data coming from the PUF Index 0 interface are NOT shifted in the KEY0 register,2: Data coming from the PUF Index 0 interface are shifted in the KEY0 register,3: Data coming from the PUF Index 0 interface are NOT shifted in the KEY0 register"
wgroup.long 0x208++0x03
line.long 0x00 "KEYRESET,Key Reset"
bitfld.long 0x00 6.--7. " KEY3               ,Key 3" ",,2: Reset KEY3 Hold register and SHIFT_STATUS[KEY3],"
textline "                      "
bitfld.long 0x00 4.--5. " KEY2               ,Key 2" ",,2: Reset KEY2 Hold register and SHIFT_STATUS[KEY2],"
textline "                      "
bitfld.long 0x00 2.--3. " KEY1               ,Key 1" ",,2: Reset KEY1 Hold register and SHIFT_STATUS[KEY1],"
textline "                      "
bitfld.long 0x00 0.--1. " KEY0               ,Key 0" ",,2: Reset KEY0 Hold register and SHIFT_STATUS[KEY0],"
group.long 0x20C++0x03
line.long 0x00 "IDXBLK_L,Index Block Low"
bitfld.long 0x00 30.--31. " LOCK_IDX           ,Lock Index" "0,1,2,3"
textline "                      "
bitfld.long 0x00 14.--15. " IDX7               ,Index 7" "0,1,2,3"
textline "                      "
bitfld.long 0x00 12.--13. " IDX6               ,Index 6" "0,1,2,3"
textline "                      "
bitfld.long 0x00 10.--11. " IDX5               ,Index 5" "0,1,2,3"
textline "                      "
bitfld.long 0x00 8.--9. " IDX4               ,Index 4" "0,1,2,3"
textline "                      "
bitfld.long 0x00 6.--7. " IDX3               ,Index 3" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4.--5. " IDX2               ,Index 2" "0,1,2,3"
textline "                      "
bitfld.long 0x00 2.--3. " IDX1               ,Index 1" "0,1,2,3"
group.long 0x210++0x03
line.long 0x00 "IDXBLK_H_DP,Index Block High Duplicate"
bitfld.long 0x00 14.--15. " IDX15              ,Index 15" "0,1,2,3"
textline "                      "
bitfld.long 0x00 12.--13. " IDX14              ,Index 14" "0,1,2,3"
textline "                      "
bitfld.long 0x00 10.--11. " IDX13              ,Index 13" "0,1,2,3"
textline "                      "
bitfld.long 0x00 8.--9. " IDX12              ,Index 12" "0,1,2,3"
textline "                      "
bitfld.long 0x00 6.--7. " IDX11              ,Index 11" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4.--5. " IDX10              ,Index 10" "0,1,2,3"
textline "                      "
bitfld.long 0x00 2.--3. " IDX9               ,Index 9" "0,1,2,3"
textline "                      "
bitfld.long 0x00 0.--1. " IDX8               ,Index 8" "0,1,2,3"
wgroup.long 0x214++0x03
line.long 0x00 "KEYMASK[0],Key Mask 0"
hexmask.long 0x00 0.--31. 1. " KEYMASK            ,Key a Mask"
wgroup.long 0x218++0x03
line.long 0x00 "KEYMASK[1],Key Mask 0"
hexmask.long 0x00 0.--31. 1. " KEYMASK            ,Key a Mask"
group.long 0x254++0x03
line.long 0x00 "IDXBLK_H,Index Block High"
bitfld.long 0x00 30.--31. " LOCK_IDX           ,Lock Index" "0,1,2,3"
textline "                      "
bitfld.long 0x00 14.--15. " IDX15              ,Index 15" "0,1,2,3"
textline "                      "
bitfld.long 0x00 12.--13. " IDX14              ,Index 14" "0,1,2,3"
textline "                      "
bitfld.long 0x00 10.--11. " IDX13              ,Index 13" "0,1,2,3"
textline "                      "
bitfld.long 0x00 8.--9. " IDX12              ,Index 12" "0,1,2,3"
textline "                      "
bitfld.long 0x00 6.--7. " IDX11              ,Index 11" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4.--5. " IDX10              ,Index 10" "0,1,2,3"
textline "                      "
bitfld.long 0x00 2.--3. " IDX9               ,Index 9" "0,1,2,3"
textline "                      "
bitfld.long 0x00 0.--1. " IDX8               ,Index 8" "0,1,2,3"
group.long 0x258++0x03
line.long 0x00 "IDXBLK_L_DP,Index Block Low Duplicate"
bitfld.long 0x00 14.--15. " IDX7               ,Index 7" "0,1,2,3"
textline "                      "
bitfld.long 0x00 12.--13. " IDX6               ,Index 6" "0,1,2,3"
textline "                      "
bitfld.long 0x00 10.--11. " IDX5               ,Index 5" "0,1,2,3"
textline "                      "
bitfld.long 0x00 8.--9. " IDX4               ,Index 4" "0,1,2,3"
textline "                      "
bitfld.long 0x00 6.--7. " IDX3               ,Index 3" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4.--5. " IDX2               ,Index 2" "0,1,2,3"
textline "                      "
bitfld.long 0x00 2.--3. " IDX1               ,Index 1" "0,1,2,3"
textline "                      "
bitfld.long 0x00 0.--1. " IDX0               ,Index 0" "0,1,2,3"
width 0x0B
tree.end
tree "RSTCTL0"
base ad:0x40000000
width 14.
group.long 0x00++0x03
line.long 0x00 "SYSRSTSTAT,system reset status register"
bitfld.long 0x00 7. " WDT1_RESET    ,WDT1 RESET Event Detected:" "0: NO_EVENT_DETECTED,1: WDT1 reset event detected"
textline "                       "
bitfld.long 0x00 6. " WDT0_RESET    ,WDT0 RESET Event Detected:" "0: NO_EVENT_DETECTED,1: WDT0 reset event detected"
textline "                       "
bitfld.long 0x00 5. " ARM_APD_RESET ,ARM RESET Event Detected:" "0: NO_EVENT_DETECTED,1: ARM reset event detected"
textline "                       "
bitfld.long 0x00 4. " PAD_RESET     ,PAD RESET Event Detected:" "0: NO_EVENT_DETECTED,1: RESET_DETECTED"
textline "                       "
bitfld.long 0x00 0. " VDD_POR       ,VDD POR Event Detected:" "0: NO_EVENT_DETECTED,1: VDD POR event detected"
group.long 0x10++0x03
line.long 0x00 "PRSTCTL0,peripheral reset control register 0"
bitfld.long 0x00 24. " SCT           ,SCT reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 23. " USBHS_SRAM    ,USBHS RAM reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 22. " USBHS_HOST    ,USB HOST reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 21. " USBHS_DEVICE  ,USB DEVICE reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 20. " USBHS_PHY     ,USB PHY reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 16. " FLEXSPI_OTFAD ,FLEXSPI reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 12. " RNG           ,RNG reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 11. " PUF           ,PUF reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 10. " HASHCRYPT     ,HASHCRYPT reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 9. " CASPER        ,CAPSER reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 8. " POWERQUAD     ,powerquad reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 1. " HIFI_DSP      ,HIFI DSP reset control" "0: CLEAR_RESET,1: SET_RESET"
group.long 0x14++0x03
line.long 0x00 "PRSTCTL1,peripheral reset control register 1"
bitfld.long 0x00 24. " SHSGPIO0      ,SHSGPIO0 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 16. " ADC0          ,ADC reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 15. " ACMP0         ,Analog comparator reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 3. " SDIO1         ,SDIO1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 2. " SDIO0         ,SDIO0 reset control" "0: CLEAR_RESET,1: SET_RESET"
group.long 0x18++0x03
line.long 0x00 "PRSTCTL2,peripheral reset control register 2"
bitfld.long 0x00 1. " WWDT0         ,wdt reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 0. " UTICK0        ,utick reset control" "0: CLEAR_RESET,1: SET_RESET"
group.long 0x40++0x03
line.long 0x00 "PRSTCTL0_SET,peripheral reset set register 0"
bitfld.long 0x00 24. " SCT           ,SCT reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 23. " USBHS_SRAM    ,USBHS RAM reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 22. " USBHS_HOST    ,USB HOST reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 21. " USBHS_DEVICE  ,USB DEVICE reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 20. " USBHS_PHY     ,USB PHY reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 16. " FLEXSPI_OTFAD ,FLEXSPI reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 12. " RNG           ,RNG reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 11. " PUF           ,PUF reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 10. " HASHCRYPT     ,HASHCRYPT reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 9. " CASPER        ,CAPSER reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 8. " POWERQUAD     ,powerquad reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 1. " HIFI_DSP      ,HIFI DSP reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
group.long 0x44++0x03
line.long 0x00 "PRSTCTL1_SET,peripheral reset set register 1"
bitfld.long 0x00 24. " SHSGPIO0      ,SHSGPIO0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 16. " ADC0          ,ADC reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 15. " ACMP0         ,Analog comparator reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 3. " SDIO1         ,SDIO1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 2. " SDIO0         ,SDIO0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
group.long 0x48++0x03
line.long 0x00 "PRSTCTL2_SET,peripheral reset set register 2"
bitfld.long 0x00 1. " WWDT0         ,wdt reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 0. " UTICK0        ,utick reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
group.long 0x70++0x03
line.long 0x00 "PRSTCTL0_CLR,peripheral reset clear register 0"
bitfld.long 0x00 24. " SCT           ,SCT reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 23. " USBHS_SRAM    ,USBHS RAM reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 22. " USBHS_HOST    ,USB HOST reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 21. " USBHS_DEVICE  ,USB DEVICE reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 20. " USBHS_PHY     ,USB PHY reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 16. " FLEXSPI_OTFAD ,FLEXSPI reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 12. " RNG           ,RNG reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 11. " PUF           ,PUF reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 10. " HASHCRYPT     ,HASHCRYPT reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 9. " CASPER        ,CAPSER reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 8. " POWERQUAD     ,powerquad reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 1. " HIFI_DSP      ,HIFI DSP reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL0 Bit"
group.long 0x74++0x03
line.long 0x00 "PRSTCTL1_CLR,peripheral reset clear register 1"
bitfld.long 0x00 24. " SHSGPIO0      ,SHSGPIO0 reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 16. " ADC0          ,ADC reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 15. " ACMP0         ,Analog comparator reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 3. " SDIO1         ,SDIO1 reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 2. " SDIO0         ,SDIO0 reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL1 Bit"
group.long 0x78++0x03
line.long 0x00 "PRSTCTL2_CLR,peripheral reset clear register 2"
bitfld.long 0x00 1. " WWDT0         ,wdt reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 0. " UTICK0        ,utick reset clear" "0: NO_EFFECT,1: Clears the PRSTCTL2 Bit"
width 0x0B
tree.end
tree "RSTCTL1"
base ad:0x40020000
width 14.
group.long 0x00++0x03
line.long 0x00 "SYSRSTSTAT,system reset status register"
bitfld.long 0x00 7. " WDT1_RESET             ,WDT1 RESET Event Detected:" "0: NO_EVENT_DETECTED,1: WDT1 reset event detected"
textline "                       "
bitfld.long 0x00 6. " WDT0_RESET             ,WDT0 RESET Event Detected:" "0: NO_EVENT_DETECTED,1: WDT0 reset event detected"
textline "                       "
bitfld.long 0x00 5. " ARM_APD_RESET          ,ARM RESET Event Detected:" "0: NO_EVENT_DETECTED,1: ARM reset event detected"
textline "                       "
bitfld.long 0x00 4. " PAD_RESET              ,PAD RESET Event Detected:" "0: NO_EVENT_DETECTED,1: RESET_DETECTED"
textline "                       "
bitfld.long 0x00 0. " VDD_POR                ,VDD POR Event Detected:" "0: No event detected,1: VDD POR event detected"
group.long 0x10++0x03
line.long 0x00 "PRSTCTL0,peripheral reset control register 0"
bitfld.long 0x00 27. " OSEVT_TIMER_RST        ,osevent timer reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 24. " DMIC0_RST              ,DMIC0 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 23. " FLEXCOMM15_I2C_RST     ,FLEXCOMM15 I2C reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 22. " FLEXCOMM14_SPI_RST     ,FLEXCOMM14 SPI reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 15. " FLEXCOMM7_RST          ,FLEXCOMM7 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 14. " FLEXCOMM6_RST          ,FLEXCOMM6 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 13. " FLEXCOMM5_RST          ,FLEXCOMM5 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 12. " FLEXCOMM4_RST          ,FLEXCOMM4 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 11. " FLEXCOMM3_RST          ,FLEXCOMM3 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 10. " FLEXCOMM2_RST          ,FLEXCOMM2 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 9. " FLEXCOMM1_RST          ,FLEXCOMM1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 8. " FLEXCOMM0_RST          ,FLEXCOMM0 reset control" "0: CLEAR_RESET,1: SET_RESET"
group.long 0x14++0x03
line.long 0x00 "PRSTCTL1,peripheral reset control register 1"
bitfld.long 0x00 31. " FREQME_RST             ,FREQME reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 29. " SEMA_RST               ,SEMA reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 28. " MU_RST                 ,MU reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 24. " DMAC1_RST              ,DMAC1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 23. " DMAC0_RST              ,DMAC0 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 16. " CRC_RST                ,CRC reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 7. " HSGPIO7_RST            ,HSGPIO7 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 6. " HSGPIO6_RST            ,HSGPIO6 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 5. " HSGPIO5_RST            ,HSGPIO5 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 4. " HSGPIO4_RST            ,HSGPIO4 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 3. " HSGPIO3_RST            ,HSGPIO3 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 2. " HSGPIO2_RST            ,HSGPIO2 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 1. " HSGPIO1_RST            ,HSGPIO1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 0. " HSGPIO0_RST            ,HSGPIO0 reset control" "0: CLEAR_RESET,1: SET_RESET"
group.long 0x18++0x03
line.long 0x00 "PRSTCTL2,peripheral reset control register 2"
bitfld.long 0x00 31. " PIMCTL_RST             ,PMC reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 30. " GPIOINTCTL_RST         ,GPIOINTCTL reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 16. " I3C0_RST               ,I3C0 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 10. " WWDT1_RST              ,WWDT1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 8. " MRT0_RST               ,MRT0 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 4. " CT32BIT4_RST           ,CT32BIT4 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 3. " CT32BIT3_RST           ,CT32BIT3 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 2. " CT32BIT2_RST           ,CT32BIT2 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 1. " CT32BIT1_RST           ,CT32BIT1 reset control" "0: CLEAR_RESET,1: SET_RESET"
textline "                       "
bitfld.long 0x00 0. " CT32BIT0_RST           ,CT32BIT0 reset control" "0: CLEAR_RESET,1: SET_RESET"
wgroup.long 0x40++0x03
line.long 0x00 "PRSTCTL0_SET,peripheral reset set register 0"
bitfld.long 0x00 27. " OSEVT_TIMER_RST_SET    ,osevent timer reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 24. " DMIC0_RST_SET          ,DMIC0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 23. " FLEXCOMM15_I2C_RST_SET ,FLEXCOMM15 I2C reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 22. " FLEXCOMM14_SPI_RST_SET ,FLEXCOMM14 SPI reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 15. " FLEXCOMM7_RST_SET      ,FLEXCOMM7 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 14. " FLEXCOMM6_RST_SET      ,FLEXCOMM6 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 13. " FLEXCOMM5_RST_SET      ,FLEXCOMM5 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 12. " FLEXCOMM4_RST_SET      ,FLEXCOMM4 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 11. " FLEXCOMM3_RST_SET      ,FLEXCOMM3 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 10. " FLEXCOMM2_RST_SET      ,FLEXCOMM2 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 9. " FLEXCOMM1_RST_SET      ,FLEXCOMM1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 8. " FLEXCOMM0_RST_SET      ,FLEXCOMM0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL0 Bit"
wgroup.long 0x44++0x03
line.long 0x00 "PRSTCTL1_SET,peripheral reset set register 1"
bitfld.long 0x00 31. " FREQME_RST_SET         ,FREQME reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 29. " SEMA_RST_SET           ,SEMA reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 28. " MU_RST_SET             ,MU reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 24. " DMAC1_RST_SET          ,DMAC1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 23. " DMAC0_RST_SET          ,DMAC0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 16. " CRC_RST_SET            ,CRC reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 7. " HSGPIO7_RST_SET        ,HSGPIO7 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 6. " HSGPIO6_RST_SET        ,HSGPIO6 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 5. " HSGPIO5_RST_SET        ,HSGPIO5 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 4. " HSGPIO4_RST_SET        ,HSGPIO4 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 3. " HSGPIO3_RST_SET        ,HSGPIO3 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 2. " HSGPIO2_RST_SET        ,HSGPIO2 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 1. " HSGPIO1_RST_SET        ,HSGPIO1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 0. " HSGPIO0_RST_SET        ,HSGPIO0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL1 Bit"
wgroup.long 0x48++0x03
line.long 0x00 "PRSTCTL2_SET,peripheral reset set register 2"
bitfld.long 0x00 31. " PIMCTL_RST_SET         ,PMC reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 30. " GPIOINTCTL_RST_SET     ,GPIOINTCTL reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 16. " I3C0_RST_SET           ,I3C0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 10. " WWDT1_RST_SET          ,WWDT1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 8. " MRT0_RST_SET           ,MRT0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 4. " CT32BIT4_RST_SET       ,CT32BIT4 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 3. " CT32BIT3_RST_SET       ,CT32BIT3 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 2. " CT32BIT2_RST_SET       ,CT32BIT2 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 1. " CT32BIT1_RST_SET       ,CT32BIT1 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 0. " CT32BIT0_RST_SET       ,CT32BIT0 reset set" "0: NO_EFFECT,1: Sets the PRSTCTL2 Bit"
wgroup.long 0x70++0x03
line.long 0x00 "PRSTCTL0_CLR,peripheral reset clear register 0"
bitfld.long 0x00 27. " OSEVT_TIMER_RST_CLR    ,osevent timer reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 24. " DMIC0_RST_CLR          ,DMIC0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 23. " FLEXCOMM15_I2C_RST_CLR ,FLEXCOMM15 I2C reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 22. " FLEXCOMM14_SPI_RST_CLR ,FLEXCOMM14 SPI reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 15. " FLEXCOMM7_RST_CLR      ,FLEXCOMM7 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 14. " FLEXCOMM6_RST_CLR      ,FLEXCOMM6 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 13. " FLEXCOMM5_RST_CLR      ,FLEXCOMM5 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 12. " FLEXCOMM4_RST_CLR      ,FLEXCOMM4 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 11. " FLEXCOMM3_RST_CLR      ,FLEXCOMM3 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 10. " FLEXCOMM2_RST_CLR      ,FLEXCOMM2 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 9. " FLEXCOMM1_RST_CLR      ,FLEXCOMM1 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
textline "                       "
bitfld.long 0x00 8. " FLEXCOMM0_RST_CLR      ,FLEXCOMM0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL0 Bit"
wgroup.long 0x74++0x03
line.long 0x00 "PRSTCTL1_CLR,peripheral reset clear register 1"
bitfld.long 0x00 31. " FREQME_RST_CLR         ,FREQME reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 29. " SEMA_RST_CLR           ,SEMA reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 28. " MU_RST_CLR             ,MU reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 24. " DMAC1_RST_CLR          ,DMAC1 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 23. " DMAC0_RST_CLR          ,DMAC0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 16. " CRC_RST_CLR            ,CRC reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 7. " HSGPIO7_RST_CLR        ,HSGPIO7 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 6. " HSGPIO6_RST_CLR        ,HSGPIO6 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 5. " HSGPIO5_RST_CLR        ,HSGPIO5 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 4. " HSGPIO4_RST_CLR        ,HSGPIO4 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 3. " HSGPIO3_RST_CLR        ,HSGPIO3 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 2. " HSGPIO2_RST_CLR        ,HSGPIO2 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 1. " HSGPIO1_RST_CLR        ,HSGPIO1 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
textline "                       "
bitfld.long 0x00 0. " HSGPIO0_RST_CLR        ,HSGPIO0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL1 Bit"
wgroup.long 0x78++0x03
line.long 0x00 "PRSTCTL2_CLR,peripheral reset clear register 2"
bitfld.long 0x00 31. " PIMCTL_RST_CLR         ,PMC reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 30. " GPIOINTCTL_RST_CLR     ,GPIOINTCTL reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 16. " I3C0_RST_CLR           ,I3C0 reset clear" ",1: Sets the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 10. " WWDT1_RST_CLR          ,WWDT1 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 8. " MRT0_RST_CLR           ,MRT0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 4. " CT32BIT4_RST_CLR       ,CT32BIT4 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 3. " CT32BIT3_RST_CLR       ,CT32BIT3 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 2. " CT32BIT2_RST_CLR       ,CT32BIT2 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 1. " CT32BIT1_RST_CLR       ,CT32BIT1 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
textline "                       "
bitfld.long 0x00 0. " CT32BIT0_RST_CLR       ,CT32BIT0 reset clear" "0: NO_EFFECT,1: clears the PRSTCTL2 Bit"
width 0x0B
tree.end
tree "RTC (Real-time Counter)"
tree "RTC"
base ad:0x40030000
width 10.
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC control register"
bitfld.long 0x00 28.--31. " RTC_OSC_loadcap ,capacitive load selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                   "
bitfld.long 0x00 10. " RTC_SUBSEC_ENA  ,The 32 KHz sub-second counter enable" "0: The sub-second counter (if implemented) is disabled,1: The 32 KHz sub-second counter is enabled (if implemented)"
textline "                   "
bitfld.long 0x00 8. " RTC_OSC_PD      ,The RTC oscillator enable" "0: The RTC oscillator is enabled,1: The RTC oscillator is shut-off to reserve power consumption"
textline "                   "
bitfld.long 0x00 7. " RTC_EN          ,RTC enable" "0: DISABLE,1: ENABLE"
textline "                   "
bitfld.long 0x00 6. " RTC1KHZ_EN      ,RTC 1 kHz clock enable" "0: DISABLE,1: ENABLE"
textline "                   "
bitfld.long 0x00 5. " WAKEDPD_EN      ,RTC 1 kHz timer wake-up enable for Deep power-down" "0: DISABLE,1: ENABLE"
textline "                   "
bitfld.long 0x00 4. " ALARMDPD_EN     ,RTC 1 Hz timer alarm enable for Deep power-down" "0: DISABLE,1: ENABLE"
textline "                   "
bitfld.long 0x00 3. " WAKE1KHZ        ,RTC 1 kHz timer wake-up flag status" "0: RUN,1: TIME_OUT"
textline "                   "
bitfld.long 0x00 2. " ALARM1HZ        ,RTC 1 Hz timer alarm flag status" "0: NO_MATCH,1: MATCH"
textline "                   "
bitfld.long 0x00 0. " SWRESET         ,Software reset control" "0: NOT_IN_RESET,1: IN_RESET"
group.long 0x04++0x03
line.long 0x00 "MATCH,RTC match register"
hexmask.long 0x00 0.--31. 1. " MATVAL          ,Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC.."
group.long 0x08++0x03
line.long 0x00 "COUNT,RTC counter register"
hexmask.long 0x00 0.--31. 1. " VAL             ,A read reflects the current value of the main. 1 Hz RTC timer"
group.long 0x0C++0x03
line.long 0x00 "WAKE,High-resolution/wake-up timer control register"
hexmask.long.word 0x00 0.--15. 1. " VAL             ,A read reflects the current value of the high-resolution/wake-up timer"
group.long 0x10++0x03
line.long 0x00 "SUBSEC,RTC Sub-second Counter register"
hexmask.long.word 0x00 0.--14. 1. " RTC_SUBSEC      ,A read reflects the current value of the 32Khz sub-second counter"
group.long 0x40++0x03
line.long 0x00 "GPREG[0],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x44++0x03
line.long 0x00 "GPREG[1],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x48++0x03
line.long 0x00 "GPREG[2],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x4C++0x03
line.long 0x00 "GPREG[3],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x50++0x03
line.long 0x00 "GPREG[4],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x54++0x03
line.long 0x00 "GPREG[5],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x58++0x03
line.long 0x00 "GPREG[6],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
group.long 0x5C++0x03
line.long 0x00 "GPREG[7],General Purpose register"
hexmask.long 0x00 0.--31. 1. " GPDATA          ,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
width 0x0B
tree.end
tree.end
tree "SCT"
tree "SCT0"
base ad:0x40146000
width 15.
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT configuration register"
bitfld.long 0x00 18. " AUTOLIMIT_H ,A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition.." "0,1"
textline "                        "
bitfld.long 0x00 17. " AUTOLIMIT_L ,A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition wit.." "0,1"
textline "                        "
bitfld.long 0x00 9.--12. " INSYNC      ,Synchronization for input N (bit 9 = input 0. bit 10 = input 1.. bit 12 = input 3). all other bits a.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 8. " NORELOAD_H  ,A 1 in this bit prevents the higher match registers from being reloaded from their respective reload.." "0,1"
textline "                        "
bitfld.long 0x00 7. " NORELOAD_L  ,A 1 in this bit prevents the lower match registers from being reloaded from their respective reload .." "0,1"
textline "                        "
bitfld.long 0x00 3.--6. " CKSEL       ,SCT clock select" "0: Rising edges on input 0,1: Falling edges on input 0,2: Rising edges on input 1,3: Falling edges on input 1,4: Rising edges on input 2,5: Falling edges on input 2,6: Rising edges on input 3,7: Falling edges on input 3,8: Rising edges on input 4,9: Falling edges on input 4,10: Rising edges on input 5,11: Falling edges on input 5,12: Rising edges on input 6,13: Falling edges on input 6,14: Rising edges on input 7,15: Falling edges on input 7"
textline "                        "
bitfld.long 0x00 1.--2. " CLKMODE     ,SCT clock mode" "0: SYSTEM_CLOCK_MODE,1: SAMPLED_SYSTEM_CLOCK_MODE,2: SCT_INPUT_CLOCK_MODE,3: ASYNCHRONOUS_MODE"
textline "                        "
bitfld.long 0x00 0. " UNIFY       ,SCT operation" "0: The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H,1: The SCT operates as a unified 32-bit counter"
group.long 0x04++0x03
line.long 0x00 "CTRL,SCT control register"
hexmask.long.byte 0x00 21.--28. 1. " PRE_H       ,Specifies the factor by which the SCT clock is prescaled to produce the H counter clock"
textline "                        "
bitfld.long 0x00 20. " BIDIR_H     ,Direction select" "0: The H counter counts up to its limit condition. then is cleared to zero,1: The H counter counts up to its limit. then counts down to a limit condition or to 0"
textline "                        "
bitfld.long 0x00 19. " CLRCTR_H    ,Writing a 1 to this bit clears the H counter" "0,1"
textline "                        "
bitfld.long 0x00 18. " HALT_H      ,When this bit is 1. the H counter does not run and no events can occur" "0,1"
textline "                        "
bitfld.long 0x00 17. " STOP_H      ,When this bit is 1 and HALT is 0. the H counter does not. run but I/O events related to the counter .." "0,1"
textline "                        "
bitfld.long 0x00 16. " DOWN_H      ,This bit is 1 when the H counter is counting down" "0,1"
textline "                        "
hexmask.long.byte 0x00 5.--12. 1. " PRE_L       ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
textline "                        "
bitfld.long 0x00 4. " BIDIR_L     ,L or unified counter direction select" "0: UP,1: UP_DOWN"
textline "                        "
bitfld.long 0x00 3. " CLRCTR_L    ,Writing a 1 to this bit clears the L or unified counter" "0,1"
textline "                        "
bitfld.long 0x00 2. " HALT_L      ,When this bit is 1. the L or unified counter does not run and no events can occur" "0,1"
textline "                        "
bitfld.long 0x00 1. " STOP_L      ,When this bit is 1 and HALT is 0. the L or unified counter does not run. but I/O events related to t.." "0,1"
textline "                        "
bitfld.long 0x00 0. " DOWN_L      ,This bit is 1 when the L or unified counter is counting down" "0,1"
group.long 0x08++0x03
line.long 0x00 "LIMIT,SCT limit event select register"
hexmask.long.word 0x00 16.--31. 1. " LIMMSK_H    ,If bit n is one. event n is used as a counter limit for the H counter (event 0 = bit 16. event 1 = b.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " LIMMSK_L    ,If bit n is one. event n is used as a counter limit for the L or unified counter (event 0 = bit 0. e.."
group.long 0x0C++0x03
line.long 0x00 "HALT,SCT halt event select register"
hexmask.long.word 0x00 16.--31. 1. " HALTMSK_H   ,If bit n is one. event n sets the HALT_H bit in the CTRL register (event 0 = bit 16. event 1 = bit 1.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " HALTMSK_L   ,If bit n is one. event n sets the HALT_L bit in the CTRL register (event 0 = bit 0. event 1 = bit 1..."
group.long 0x10++0x03
line.long 0x00 "STOP,SCT stop event select register"
hexmask.long.word 0x00 16.--31. 1. " STOPMSK_H   ,If bit n is one. event n sets the STOP_H bit in the CTRL register (event 0 = bit 16. event 1 = bit 1.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " STOPMSK_L   ,If bit n is one. event n sets the STOP_L bit in the CTRL register (event 0 = bit 0. event 1 = bit 1..."
group.long 0x14++0x03
line.long 0x00 "START,SCT start event select register"
hexmask.long.word 0x00 16.--31. 1. " STARTMSK_H  ,If bit n is one. event n clears the STOP_H bit in the CTRL register (event 0 = bit 16. event 1 = bit.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " STARTMSK_L  ,If bit n is one. event n clears the STOP_L bit in the CTRL register (event 0 = bit 0. event 1 = bit .."
group.long 0x40++0x03
line.long 0x00 "COUNT,SCT counter register"
hexmask.long.word 0x00 16.--31. 1. " CTR_H       ,When UNIFY = 0. read or write the 16-bit H counter value"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CTR_L       ,When UNIFY = 0. read or write the 16-bit L counter value"
group.long 0x44++0x03
line.long 0x00 "STATE,SCT state register"
bitfld.long 0x00 16.--20. " STATE_H     ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                        "
bitfld.long 0x00 0.--4. " STATE_L     ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x48++0x03
line.long 0x00 "INPUT,SCT input register"
bitfld.long 0x00 31. " SIN15       ,Input 15 state" "0,1"
textline "                        "
bitfld.long 0x00 30. " SIN14       ,Input 14 state" "0,1"
textline "                        "
bitfld.long 0x00 29. " SIN13       ,Input 13 state" "0,1"
textline "                        "
bitfld.long 0x00 28. " SIN12       ,Input 12 state" "0,1"
textline "                        "
bitfld.long 0x00 27. " SIN11       ,Input 11 state" "0,1"
textline "                        "
bitfld.long 0x00 26. " SIN10       ,Input 10 state" "0,1"
textline "                        "
bitfld.long 0x00 25. " SIN9        ,Input 9 state" "0,1"
textline "                        "
bitfld.long 0x00 24. " SIN8        ,Input 8 state" "0,1"
textline "                        "
bitfld.long 0x00 23. " SIN7        ,Input 7 state" "0,1"
textline "                        "
bitfld.long 0x00 22. " SIN6        ,Input 6 state" "0,1"
textline "                        "
bitfld.long 0x00 21. " SIN5        ,Input 5 state" "0,1"
textline "                        "
bitfld.long 0x00 20. " SIN4        ,Input 4 state" "0,1"
textline "                        "
bitfld.long 0x00 19. " SIN3        ,Input 3 state" "0,1"
textline "                        "
bitfld.long 0x00 18. " SIN2        ,Input 2 state" "0,1"
textline "                        "
bitfld.long 0x00 17. " SIN1        ,Input 1 state" "0,1"
textline "                        "
bitfld.long 0x00 16. " SIN0        ,Input 0 state" "0,1"
textline "                        "
bitfld.long 0x00 15. " AIN15       ,Input 15 state" "0,1"
textline "                        "
bitfld.long 0x00 14. " AIN14       ,Input 14 state" "0,1"
textline "                        "
bitfld.long 0x00 13. " AIN13       ,Input 13 state" "0,1"
textline "                        "
bitfld.long 0x00 12. " AIN12       ,Input 12 state" "0,1"
textline "                        "
bitfld.long 0x00 11. " AIN11       ,Input 11 state" "0,1"
textline "                        "
bitfld.long 0x00 10. " AIN10       ,Input 10 state" "0,1"
textline "                        "
bitfld.long 0x00 9. " AIN9        ,Input 9 state" "0,1"
textline "                        "
bitfld.long 0x00 8. " AIN8        ,Input 8 state" "0,1"
textline "                        "
bitfld.long 0x00 7. " AIN7        ,Input 7 state" "0,1"
textline "                        "
bitfld.long 0x00 6. " AIN6        ,Input 6 state" "0,1"
textline "                        "
bitfld.long 0x00 5. " AIN5        ,Input 5 state" "0,1"
textline "                        "
bitfld.long 0x00 4. " AIN4        ,Input 4 state" "0,1"
textline "                        "
bitfld.long 0x00 3. " AIN3        ,Input 3 state" "0,1"
textline "                        "
bitfld.long 0x00 2. " AIN2        ,Input 2 state" "0,1"
textline "                        "
bitfld.long 0x00 1. " AIN1        ,Input 1 state" "0,1"
textline "                        "
bitfld.long 0x00 0. " AIN0        ,Input 0 state" "0,1"
group.long 0x4C++0x03
line.long 0x00 "REGMODE,SCT match/capture mode register"
hexmask.long.word 0x00 16.--31. 1. " REGMOD_H    ,Each bit controls one match/capture register (register 0 = bit 16. register 1 = bit 17. etc"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " REGMOD_L    ,Each bit controls one match/capture register (register 0 = bit 0. register 1 = bit 1. etc"
group.long 0x50++0x03
line.long 0x00 "OUTPUT,SCT output register"
hexmask.long.word 0x00 0.--15. 1. " OUT         ,Writing a 1 to bit n forces the corresponding output HIGH"
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT output counter direction control register"
bitfld.long 0x00 30.--31. " SETCLR15    ,Set/clear operation on output 15" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 28.--29. " SETCLR14    ,Set/clear operation on output 14" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 26.--27. " SETCLR13    ,Set/clear operation on output 13" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 24.--25. " SETCLR12    ,Set/clear operation on output 12" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 22.--23. " SETCLR11    ,Set/clear operation on output 11" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 20.--21. " SETCLR10    ,Set/clear operation on output 10" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 18.--19. " SETCLR9     ,Set/clear operation on output 9" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 16.--17. " SETCLR8     ,Set/clear operation on output 8" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 14.--15. " SETCLR7     ,Set/clear operation on output 7" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 12.--13. " SETCLR6     ,Set/clear operation on output 6" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 10.--11. " SETCLR5     ,Set/clear operation on output 5" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 8.--9. " SETCLR4     ,Set/clear operation on output 4" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 6.--7. " SETCLR3     ,Set/clear operation on output 3" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 4.--5. " SETCLR2     ,Set/clear operation on output 2" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 2.--3. " SETCLR1     ,Set/clear operation on output 1" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
textline "                        "
bitfld.long 0x00 0.--1. " SETCLR0     ,Set/clear operation on output 0" "0: Set and clear do not depend on the direction of any counter,1: Set and clear are reversed when counter L or the unified counter is counting down,2: Set and clear are reversed when counter H is counting down,"
group.long 0x58++0x03
line.long 0x00 "RES,SCT conflict resolution register"
bitfld.long 0x00 30.--31. " O15RES      ,Effect of simultaneous set and clear on output 15" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR15 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 28.--29. " O14RES      ,Effect of simultaneous set and clear on output 14" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR14 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 26.--27. " O13RES      ,Effect of simultaneous set and clear on output 13" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR13 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 24.--25. " O12RES      ,Effect of simultaneous set and clear on output 12" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR12 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 22.--23. " O11RES      ,Effect of simultaneous set and clear on output 11" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR11 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 20.--21. " O10RES      ,Effect of simultaneous set and clear on output 10" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR10 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 18.--19. " O9RES       ,Effect of simultaneous set and clear on output 9" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR9 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 16.--17. " O8RES       ,Effect of simultaneous set and clear on output 8" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR8 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 14.--15. " O7RES       ,Effect of simultaneous set and clear on output 7" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register),2: Clear output n (or set based on the SETCLR7 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 12.--13. " O6RES       ,Effect of simultaneous set and clear on output 6" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR6 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 10.--11. " O5RES       ,Effect of simultaneous set and clear on output 5" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR5 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 8.--9. " O4RES       ,Effect of simultaneous set and clear on output 4" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR4 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 6.--7. " O3RES       ,Effect of simultaneous set and clear on output 3" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR3 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 4.--5. " O2RES       ,Effect of simultaneous set and clear on output 2" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register),2: Clear output n (or set based on the SETCLR2 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 2.--3. " O1RES       ,Effect of simultaneous set and clear on output 1" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR1 field),3: TOGGLE_OUTPUT"
textline "                        "
bitfld.long 0x00 0.--1. " O0RES       ,Effect of simultaneous set and clear on output 0" "0: NO_CHANGE,1: Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register),2: Clear output (or set based on the SETCLR0 field),3: TOGGLE_OUTPUT"
group.long 0x5C++0x03
line.long 0x00 "DMAREQ0,SCT DMA request 0 register"
bitfld.long 0x00 31. " DRQ0        ,This read-only bit indicates the state of DMA Request 0" "0,1"
textline "                        "
bitfld.long 0x00 30. " DRL0        ,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L.." "0,1"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " DEV_0       ,If bit n is one. event n triggers DMA request 0 (event 0 = bit 0. event 1 = bit 1. etc"
group.long 0x60++0x03
line.long 0x00 "DMAREQ1,SCT DMA request 1 register"
bitfld.long 0x00 31. " DRQ1        ,This read-only bit indicates the state of DMA Request 1" "0,1"
textline "                        "
bitfld.long 0x00 30. " DRL1        ,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L.." "0,1"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " DEV_1       ,If bit n is one. event n triggers DMA request 1 (event 0 = bit 0. event 1 = bit 1. etc"
group.long 0xF0++0x03
line.long 0x00 "EVEN,SCT event interrupt enable register"
hexmask.long.word 0x00 0.--15. 1. " IEN         ,The SCT requests an interrupt when bit n of this register and the event flag register are both one (.."
group.long 0xF4++0x03
line.long 0x00 "EVFLAG,SCT event flag register"
hexmask.long.word 0x00 0.--15. 1. " FLAG        ,Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit .."
group.long 0xF8++0x03
line.long 0x00 "CONEN,SCT conflict interrupt enable register"
hexmask.long.word 0x00 0.--15. 1. " NCEN        ,The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are bot.."
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT conflict flag register"
bitfld.long 0x00 31. " BUSERRH     ,The most recent bus error from this SCT involved writing CTR H. STATE H. MATCH H. or the Output regi.." "0,1"
textline "                        "
bitfld.long 0x00 30. " BUSERRL     ,The most recent bus error from this SCT involved writing CTR L/Unified. STATE L/Unified. MATCH L/Uni.." "0,1"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " NCFLAG      ,Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written .."
group.long 0x100++0x03
line.long 0x00 "CAP0,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x100++0x03
line.long 0x00 "MATCH0,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x104++0x03
line.long 0x00 "CAP1,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x104++0x03
line.long 0x00 "MATCH1,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x108++0x03
line.long 0x00 "CAP2,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x108++0x03
line.long 0x00 "MATCH2,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x10C++0x03
line.long 0x00 "CAP3,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x110++0x03
line.long 0x00 "CAP4,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x110++0x03
line.long 0x00 "MATCH4,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x114++0x03
line.long 0x00 "CAP5,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x114++0x03
line.long 0x00 "MATCH5,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x118++0x03
line.long 0x00 "CAP6,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x118++0x03
line.long 0x00 "MATCH6,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x11C++0x03
line.long 0x00 "CAP7,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x11C++0x03
line.long 0x00 "MATCH7,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x120++0x03
line.long 0x00 "CAP8,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x120++0x03
line.long 0x00 "MATCH8,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x124++0x03
line.long 0x00 "CAP9,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x124++0x03
line.long 0x00 "MATCH9,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x128++0x03
line.long 0x00 "CAP10,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x128++0x03
line.long 0x00 "MATCH10,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x12C++0x03
line.long 0x00 "CAP11,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x12C++0x03
line.long 0x00 "MATCH11,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x130++0x03
line.long 0x00 "CAP12,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x130++0x03
line.long 0x00 "MATCH12,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x134++0x03
line.long 0x00 "CAP13,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x134++0x03
line.long 0x00 "MATCH13,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x138++0x03
line.long 0x00 "CAP14,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x138++0x03
line.long 0x00 "MATCH14,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x13C++0x03
line.long 0x00 "CAP15,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. " CAPn_H      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPn_L      ,When UNIFY = 0. read the 16-bit counter value at which this register was last captured"
group.long 0x13C++0x03
line.long 0x00 "MATCH15,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. " MATCHn_H    ,When UNIFY = 0. read or write the 16-bit value to be compared to the H counter"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " MATCHn_L    ,When UNIFY = 0. read or write the 16-bit value to be compared to the L counter"
group.long 0x200++0x03
line.long 0x00 "CAPCTRL0,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x200++0x03
line.long 0x00 "MATCHREL0,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x204++0x03
line.long 0x00 "CAPCTRL1,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x204++0x03
line.long 0x00 "MATCHREL1,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x208++0x03
line.long 0x00 "CAPCTRL2,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x208++0x03
line.long 0x00 "MATCHREL2,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x20C++0x03
line.long 0x00 "CAPCTRL3,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x20C++0x03
line.long 0x00 "MATCHREL3,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x210++0x03
line.long 0x00 "CAPCTRL4,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x210++0x03
line.long 0x00 "MATCHREL4,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x214++0x03
line.long 0x00 "CAPCTRL5,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x214++0x03
line.long 0x00 "MATCHREL5,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x218++0x03
line.long 0x00 "CAPCTRL6,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x218++0x03
line.long 0x00 "MATCHREL6,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x21C++0x03
line.long 0x00 "CAPCTRL7,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x21C++0x03
line.long 0x00 "MATCHREL7,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x220++0x03
line.long 0x00 "CAPCTRL8,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x220++0x03
line.long 0x00 "MATCHREL8,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x224++0x03
line.long 0x00 "CAPCTRL9,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x224++0x03
line.long 0x00 "MATCHREL9,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x228++0x03
line.long 0x00 "CAPCTRL10,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x228++0x03
line.long 0x00 "MATCHREL10,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x22C++0x03
line.long 0x00 "CAPCTRL11,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x22C++0x03
line.long 0x00 "MATCHREL11,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x230++0x03
line.long 0x00 "CAPCTRL12,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x230++0x03
line.long 0x00 "MATCHREL12,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x234++0x03
line.long 0x00 "CAPCTRL13,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x234++0x03
line.long 0x00 "MATCHREL13,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x238++0x03
line.long 0x00 "CAPCTRL14,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x238++0x03
line.long 0x00 "MATCHREL14,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x23C++0x03
line.long 0x00 "CAPCTRL15,SCT capture control register"
hexmask.long.word 0x00 16.--31. 1. " CAPCONn_H   ,If bit m is one. event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16. even.."
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " CAPCONn_L   ,If bit m is one. event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded.."
group.long 0x23C++0x03
line.long 0x00 "MATCHREL15,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. " RELOADn_H   ,When UNIFY = 0. specifies the 16-bit to be loaded into the MATCHn_H register"
textline "                        "
hexmask.long.word 0x00 0.--15. 1. " RELOADn_L   ,When UNIFY = 0. specifies the 16-bit value to be loaded into the MATCHn_L register"
tree "EV[0]"
width 7.
group.long 0x300++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x304++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[1]"
width 7.
group.long 0x308++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x30C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[2]"
width 7.
group.long 0x310++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x314++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[3]"
width 7.
group.long 0x318++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x31C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[4]"
width 7.
group.long 0x320++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x324++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[5]"
width 7.
group.long 0x328++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x32C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[6]"
width 7.
group.long 0x330++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x334++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[7]"
width 7.
group.long 0x338++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x33C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[8]"
width 7.
group.long 0x340++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x344++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[9]"
width 7.
group.long 0x348++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x34C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[10]"
width 7.
group.long 0x350++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x354++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[11]"
width 7.
group.long 0x358++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x35C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[12]"
width 7.
group.long 0x360++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x364++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[13]"
width 7.
group.long 0x368++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x36C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[14]"
width 7.
group.long 0x370++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x374++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EV[15]"
width 7.
group.long 0x378++0x03
line.long 0x00 "STATE,SCT event state register 0"
hexmask.long.word 0x00 0.--15. 1. " STATEMSKn ,If bit m is one. event n happens in state m of the counter selected by the HEVENT bit (n = event num.."
group.long 0x37C++0x03
line.long 0x00 "CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "0: DIRECTION_INDEPENDENT,1: COUNTING_UP,2: COUNTING_DOWN,"
textline "                "
bitfld.long 0x00 20. " MATCHMEM  ,If this bit is one and the COMBMODE field specifies a match component to the triggering of this even.." "0,1"
textline "                "
bitfld.long 0x00 15.--19. " STATEV    ,This value is loaded into or added to the state selected by HEVENT. depending on STATELD. when this .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                "
bitfld.long 0x00 14. " STATELD   ,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the .." "0: STATEV value is added into STATE (the carry-out is ignored),1: STATEV value is loaded into STATE"
textline "                "
bitfld.long 0x00 12.--13. " COMBMODE  ,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
textline "                "
bitfld.long 0x00 10.--11. " IOCOND    ,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
textline "                "
bitfld.long 0x00 6.--9. " IOSEL     ,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                "
bitfld.long 0x00 5. " OUTSEL    ,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
textline "                "
bitfld.long 0x00 4. " HEVENT    ,Select L/H counter" "0: Selects the L state and the L match register selected by MATCHSEL,1: Selects the H state and the H match register selected by MATCHSEL"
textline "                "
bitfld.long 0x00 0.--3. " MATCHSEL  ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "OUT[0]"
width 5.
group.long 0x500++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x504++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[1]"
width 5.
group.long 0x508++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x50C++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[2]"
width 5.
group.long 0x510++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x514++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[3]"
width 5.
group.long 0x518++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x51C++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[4]"
width 5.
group.long 0x520++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x524++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[5]"
width 5.
group.long 0x528++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x52C++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[6]"
width 5.
group.long 0x530++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x534++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[7]"
width 5.
group.long 0x538++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x53C++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[8]"
width 5.
group.long 0x540++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x544++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
tree "OUT[9]"
width 5.
group.long 0x548++0x03
line.long 0x00 "SET,SCT output 0 set register"
hexmask.long.word 0x00 0.--15. 1. " SET ,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0..."
group.long 0x54C++0x03
line.long 0x00 "CLR,SCT output 0 clear register"
hexmask.long.word 0x00 0.--15. 1. " CLR ,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0. .."
tree.end
width 0x0B
tree.end
tree.end
tree "SEMA42"
base ad:0x40112000
width 9.
group.byte 0x00++0x00
line.byte 0x00 "GATE3,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x01++0x00
line.byte 0x00 "GATE2,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x02++0x00
line.byte 0x00 "GATE1,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x03++0x00
line.byte 0x00 "GATE0,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x04++0x00
line.byte 0x00 "GATE7,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x05++0x00
line.byte 0x00 "GATE6,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x06++0x00
line.byte 0x00 "GATE5,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x07++0x00
line.byte 0x00 "GATE4,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x08++0x00
line.byte 0x00 "GATE11,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x09++0x00
line.byte 0x00 "GATE10,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0A++0x00
line.byte 0x00 "GATE9,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0B++0x00
line.byte 0x00 "GATE8,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0C++0x00
line.byte 0x00 "GATE15,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0D++0x00
line.byte 0x00 "GATE14,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0E++0x00
line.byte 0x00 "GATE13,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
group.byte 0x0F++0x00
line.byte 0x00 "GATE12,Semphores2 Gate n"
bitfld.byte 0x00 0.--3. " GTFSM  ,ate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,,,,,,,,,,,,,"
rgroup.word 0x42++0x01
line.word 0x00 "RSTGT_R,Reset Gate Read"
bitfld.word 0x00 14.--15. " ROZ    ,ROZ" "0,1,2,3"
textline "              "
bitfld.word 0x00 12.--13. " RSTGSM ,RSTGSM" "0: Idle. waiting for the first data pattern write,1: Waiting for the second data pattern write,2: The 2-write sequence has completed,3: This state encoding is never used and therefore reserved"
textline "              "
bitfld.word 0x00 8.--11. " RSTGMS ,RSTGMS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "              "
hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,RSTGTN"
wgroup.word 0x42++0x01
line.word 0x00 "RSTGT_W,Reset Gate Write"
hexmask.word.byte 0x00 8.--15. 1. " RSTGDP ,RSTGDP"
textline "              "
hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,RSTGTN"
width 0x0B
tree.end
tree "SPI"
tree "SPI0"
base ad:0x40106000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI1"
base ad:0x40107000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI2"
base ad:0x40108000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI3"
base ad:0x40109000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI4"
base ad:0x40122000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI5"
base ad:0x40123000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI6"
base ad:0x40124000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI7"
base ad:0x40125000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "SPI14"
base ad:0x40126000
width 14.
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. " SPOL3          ,SSEL3 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 10. " SPOL2          ,SSEL2 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 9. " SPOL1          ,SSEL1 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 8. " SPOL0          ,SSEL0 Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 7. " LOOP           ,Loopback mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 5. " CPOL           ,Clock Polarity select" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 4. " CPHA           ,Clock Phase select" "0: CHANGE,1: CAPTURE"
textline "                       "
bitfld.long 0x00 3. " LSBF           ,LSB First mode enable" "0: STANDARD,1: REVERSE"
textline "                       "
bitfld.long 0x00 2. " MASTER         ,Master mode select" "0: SLAVE_MODE,1: MASTER_MODE"
textline "                       "
bitfld.long 0x00 0. " ENABLE         ,SPI enable" "0: DISABLED,1: ENABLED"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " FRAME_DELAY    ,If the EOF flag is set. controls the minimum amount of time between the current frame and the next f.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 4.--7. " POST_DELAY     ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 0.--3. " PRE_DELAY      ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. " MSTIDLE        ,Master idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 7. " ENDTRANSFER    ,End Transfer control bit" "0,1"
textline "                       "
rbitfld.long 0x00 6. " STALLED        ,Stalled status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. " MSTIDLEEN      ,Master idle interrupt enable" "0: No interrupt will be generated when the SPI master function is idle,1: An interrupt will be generated when the SPI master function is fully idle"
textline "                       "
bitfld.long 0x00 5. " SSDEN          ,Slave select deassert interrupt enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 4. " SSAEN          ,Slave select assert interrupt enable" "0: DISABLED,1: ENABLED"
group.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
eventfld.long 0x00 8. " MSTIDLE        ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 5. " SSDEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
eventfld.long 0x00 4. " SSAEN          ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. " DIVVAL         ,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. " MSTIDLE        ,Master Idle status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " SSD            ,Slave Select Deassert" "0,1"
textline "                       "
bitfld.long 0x00 4. " SSA            ,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX        ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX        ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX         ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX         ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX          ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX          ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE           ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX       ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX       ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL          ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL          ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL         ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY     ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL      ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY        ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL          ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL          ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA       ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA       ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT         ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL          ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL          ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR          ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR          ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. " LEN            ,Data Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 23. " TXIGNORE       ,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
textline "                       "
bitfld.long 0x00 22. " RXIGNORE       ,Receive Ignore" "0: Read received data,1: Ignore received data"
textline "                       "
bitfld.long 0x00 21. " EOF            ,End of frame" "0: Data not EOF,1: Data EOF"
textline "                       "
bitfld.long 0x00 20. " EOT            ,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
textline "                       "
bitfld.long 0x00 19. " TXSSEL3_N      ,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
textline "                       "
bitfld.long 0x00 18. " TXSSEL2_N      ,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
textline "                       "
bitfld.long 0x00 17. " TXSSEL1_N      ,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
textline "                       "
bitfld.long 0x00 16. " TXSSEL0_N      ,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " TXDATA         ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. " SOT            ,Start of Transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. " SOT            ,Start of transfer flag" "0,1"
textline "                       "
bitfld.long 0x00 19. " RXSSEL3_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 18. " RXSSEL2_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 17. " RXSSEL1_N      ,Slave Select for receive" "0,1"
textline "                       "
bitfld.long 0x00 16. " RXSSEL0_N      ,Slave Select for receive" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--15. 1. " RXDATA         ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE       ,the fifo size is equal to the template parameter _fifo_/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID             ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV      ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV      ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE       ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree.end
tree "SYSCTL0"
base ad:0x40002000
width 28.
group.long 0x0C++0x03
line.long 0x00 "DSPSTALL,DSP stall register"
bitfld.long 0x00 0. " DSPSTALL                   ,Run / Stall Register" "0: Run (Normal) Mode,1: STALL_MODE"
group.long 0x10++0x03
line.long 0x00 "AHBMATRIXPRIOR,AHB matrix priority"
bitfld.long 0x00 16.--17. " M8                         ,Master 8 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 14.--15. " M7                         ,Master 7 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 12.--13. " M6                         ,Master 6 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 10.--11. " M5                         ,Master 5 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 8.--9. " M4                         ,Master 4 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 6.--7. " M3                         ,Master 3 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 4.--5. " M2                         ,Master 2 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 2.--3. " M1                         ,Master 1 Priority" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--1. " M0                         ,Master 0 Priority" "0,1,2,3"
group.long 0x14++0x03
line.long 0x00 "PACKERENABLE,These registers are reset to the given value. however. if the OTP signature is valid and the BOOTROM.."
bitfld.long 0x00 2. " CPRENABLE                  ,Cache Power Reduction Enable" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 1. " RDPENABLE                  ,Read Packer Enable" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 0. " WRPENABLE                  ,Write Packer Enable" "0: DISABLED,1: ENABLED"
group.long 0x30++0x03
line.long 0x00 "M33NMISRCSEL,M33 nmi source selection"
bitfld.long 0x00 31. " NMIEN                      ,NMI interrupt enable" "0: Disable NMI Interrupt,1: Enable NMI Interrupt"
textline "                                     "
hexmask.long.byte 0x00 0.--6. 1. " NMISRCSEL                  ,Selects one of the M33 interrupt sources as the NMI source"
group.long 0x34++0x03
line.long 0x00 "SYSTEM_STICK_CALIB,system stick calibration"
hexmask.long 0x00 0.--25. 1. " SYSTEM_STICK_CALIB         ,Selects the system secure tick calibration value of the M33"
group.long 0x38++0x03
line.long 0x00 "SYSTEM_NSTICK_CALIB,system nstick calibration"
hexmask.long 0x00 0.--25. 1. " SYSTEM_NSTICK_CALIB        ,Selects the system non-secure tick calibration value of the M33"
rgroup.long 0x64++0x03
line.long 0x00 "SILICONREV_ID,SILICONREV ID"
bitfld.long 0x00 16.--19. " MAJOR                      ,Silicon revision major tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
bitfld.long 0x00 0.--3. " MINOR                      ,Silicon revision minor tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x68++0x03
line.long 0x00 "JTAG_ID,jtag ID"
bitfld.long 0x00 28.--31. " VERNUM                     ,JTAG IDCODE version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
hexmask.long.word 0x00 12.--27. 1. " PARTNUM                    ,JTAG IDCODE part number"
textline "                                     "
hexmask.long.word 0x00 1.--11. 1. " MANU                       ,JTAG IDCODE manufacturer identity"
textline "                                     "
bitfld.long 0x00 0. " FIXBIT                     ,JTAG IDCODE fix bit" "0,1"
group.long 0x80++0x03
line.long 0x00 "AUTOCLKGATEOVERRIDE0,auto clock gating override 0"
bitfld.long 0x00 5. " DMAC1                      ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 4. " DMAC0                      ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 3. " Casper                     ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 2. " CRC_Engine                 ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 1. " AHB2APB1                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 0. " AHB2APB0                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
group.long 0x84++0x03
line.long 0x00 "AUTOCLKGATEOVERRIDE1,auto clock gating override 1"
bitfld.long 0x00 29. " SRAM_IF29                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18                  ,auto clock gating enable" "0,1"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10                  ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0                   ,auto clock gating enable" "0: Enable Auto-Clk,1: Disable Auto-Clk"
group.long 0xA0++0x03
line.long 0x00 "CLKGATEOVERRIDE0,These registers are reset to a value of 0xFFFF FFFF. however. if the OTP signature is valid and the .."
bitfld.long 0x00 6. " PMC                        ,pmc clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 5. " ACMP                       ,acomparator clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 4. " MU                         ,mu clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 3. " ADC                        ,adc clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 2. " USBHSPHY                   ,usbhsphy clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 1. " SDIO_1                     ,sdio 1 clock override" "0: NO_EFFECT,1: OVERRIDE"
textline "                                     "
bitfld.long 0x00 0. " SDIO_0                     ,sdio 0 clock override" "0: NO_EFFECT,1: OVERRIDE"
group.long 0x100++0x03
line.long 0x00 "AHB_SRAM_ACCESS_DISABLE,Set bit to disable AHB bus access to corresponding SRAM partition"
bitfld.long 0x00 29. " SRAM29_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 28. " SRAM28_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 27. " SRAM27_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 26. " SRAM26_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 25. " SRAM25_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 24. " SRAM24_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 23. " SRAM23_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 22. " SRAM22_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 21. " SRAM21_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 20. " SRAM20_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 19. " SRAM19_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 18. " SRAM18_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 17. " SRAM17_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 16. " SRAM16_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 15. " SRAM15_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 14. " SRAM14_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 13. " SRAM13_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 12. " SRAM12_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 11. " SRAM11_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 10. " SRAM10_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 9. " SRAM09_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 8. " SRAM08_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 7. " SRAM07_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 6. " SRAM06_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 5. " SRAM05_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 4. " SRAM04_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 3. " SRAM03_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 2. " SRAM02_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 1. " SRAM01_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 0. " SRAM00_IF                  ,no description available" "0: ENABLED,1: DISABLED"
group.long 0x104++0x03
line.long 0x00 "DSP_SRAM_ACCESS_DISABLE,Set bit to disable DSP access to the corresponding SRAM partition"
bitfld.long 0x00 29. " SRAM29_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 28. " SRAM28_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 27. " SRAM27_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 26. " SRAM26_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 25. " SRAM25_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 24. " SRAM24_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 23. " SRAM23_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 22. " SRAM22_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 21. " SRAM21_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 20. " SRAM20_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 19. " SRAM19_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 18. " SRAM18_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 17. " SRAM17_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 16. " SRAM16_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 15. " SRAM15_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 14. " SRAM14_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 13. " SRAM13_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 12. " SRAM12_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 11. " SRAM11_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 10. " SRAM10_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 9. " SRAM09_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 8. " SRAM08_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 7. " SRAM07_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 6. " SRAM06_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 5. " SRAM05_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 4. " SRAM04_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 3. " SRAM03_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 2. " SRAM02_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 1. " SRAM01_IF                  ,no description available" "0: ENABLED,1: DISABLED"
textline "                                     "
bitfld.long 0x00 0. " SRAM00_IF                  ,no description available" "0: ENABLED,1: DISABLED"
group.long 0x138++0x03
line.long 0x00 "AHB_FLEXSPI_ACCESS_DISABLE,AHB Flexspi access control"
bitfld.long 0x00 0. " AHB_FLEXSPI_ACCESS_DISABLE ,no description available" "0: Enable AHB access to FLEXSPI,1: Disable AHB access to FLEXSPI"
group.long 0x13C++0x03
line.long 0x00 "DSP_FLEXSPI_ACCESS_DISABLE,DSP Flexspi access control"
bitfld.long 0x00 0. " DSP_FLEXSPI_ACCESS_DISABLE ,no description available" "0: Enable DSP access to FLEXSPI,1: Disable DSP access to FLEXSPI"
group.long 0x40C++0x03
line.long 0x00 "USBCLKCTRL,USB clock control"
bitfld.long 0x00 4. " HS_DEV_WAKEUP_N            ,External user wake-up signal for device mode. asserting this signal (active low) will result in exit.." "0: Forces USB0 PHY to wake-up,1: Normal USB0 PHY behavior"
textline "                                     "
bitfld.long 0x00 3. " POL_HOST_CLK               ,USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt" "0: Falling edge of host need_clock triggers wake-up,1: Rising edge of host need_clock triggers wake-up"
textline "                                     "
bitfld.long 0x00 2. " AP_HOST_CLK                ,USB0 Host need clock signal control" "0: Under hardware control,1: FORCED_HIGH"
textline "                                     "
bitfld.long 0x00 1. " POL_DEV_CLK                ,USB0 Device need clock polarity for triggering the USB1 wake-up interrupt" "0: Falling edge of device need_clock triggers wake-up,1: Rising edge of device need_clock triggers wake-up"
textline "                                     "
bitfld.long 0x00 0. " AP_DEV_CLK                 ,USB0 Device need clock signal control" "0: Under hardware control,1: FORCED_HIGH"
group.long 0x410++0x03
line.long 0x00 "USBCLKSTAT,USB clock status"
rbitfld.long 0x00 1. " HOST_NEED_CLKST            ,USB Device Host USB_NEEDCLK signal status:" "0: LOW,1: HIGH"
textline "                                     "
rbitfld.long 0x00 0. " DEV_NEED_CLKST             ,USB Device USB_NEEDCLK signal status:" "0: LOW,1: HIGH"
group.long 0x414++0x03
line.long 0x00 "USBPHYPLL0LOCKTIMEDIV2,This register is reset to a value of 0x0000 CAFE. however. if the OTP signature is valid and the BOO.."
hexmask.long.word 0x00 0.--15. 1. " LOCKTIMEDIV2               ,USBPHYPLL0 Lock Time: Programmed lock time is in uS (micro-seconds) and is programmed as half the ac.."
group.long 0x600++0x03
line.long 0x00 "PDSLEEPCFG0,no description available"
bitfld.long 0x00 29. " HSPAD2_REF_PD              ,no description available" "0: High Speed Pad VREF Enabled,1: High Speed Pad VREF in Power Down"
textline "                                     "
bitfld.long 0x00 28. " HSPAD2_VDET_LP             ,no description available" "0: High Speed Pad VDET in Normal Mode,1: High Speed Pad VDET in Sleep Mode"
textline "                                     "
bitfld.long 0x00 27. " HSPAD0_REF_PD              ,no description available" "0: High Speed Pad VREF Enabled,1: High Speed Pad VREF in Power Down"
textline "                                     "
bitfld.long 0x00 26. " HSPAD0_VDET_LP             ,no description available" "0: High Speed Pad VDET in Normal Mode,1: High Speed Pad VDET in Sleep Mode"
textline "                                     "
bitfld.long 0x00 25. " ACMP_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " ADCTEMPSNS_PD              ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " ADC_LP                     ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " ADC_PD                     ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " AUDPLLANA_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " AUDPLLLDO_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SYSPLLANA_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SYSPLLLDO_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " FFRO_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SFRO_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " LPOSC_PD                   ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SYSXTAL_PD                 ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 12. " FBB_PD                     ,Writes to this bit in PDRUNCFG. but not PDSLEEPCFG. can be disabled by an OTP bit" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " RBB_PD                     ,Writes to this bit in PDRUNCFG. but not PDSLEEPCFG. can be disabled by an OTP bit" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " HVDCORE_PD                 ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " LVDCORE_LP                 ,no description available" "0: LVD0V85 HP Mode,1: LVD0V85 LP Mode"
textline "                                     "
bitfld.long 0x00 8. " PORCORE_LP                 ,no description available" "0: LVD0V6 HP Mode,1: LVD0V6 LP Mode"
textline "                                     "
bitfld.long 0x00 7. " HVD1V8_PD                  ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " PMCREF_LP                  ,no description available" "0: PMCREF HP Mode,1: PMCREF LP Mode"
textline "                                     "
bitfld.long 0x00 4. " VDDCOREREG_LP              ,no description available" "0: VDDCOREREG HP Mode,1: LP_MODE"
textline "                                     "
bitfld.long 0x00 3. " DEEP_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " PMIC_MODE1                 ,no description available" "0: Set Mode1 to 0,1: Set Mode1 to 1"
textline "                                     "
bitfld.long 0x00 1. " PMIC_MODE0                 ,no description available" "0: Set Mode0 to '0',1: Set Mode0 to '1'"
textline "                                     "
bitfld.long 0x00 0. " MAINCLK_SHUTOFF            ,main clock shut off" "0: Clocks enabled,1: Clocks gated"
group.long 0x604++0x03
line.long 0x00 "PDSLEEPCFG1,no description available"
bitfld.long 0x00 31. " SRAM_SLEEP                 ,Needed when vddcore can be smaller than 0" "0: RAM Normal Mode,1: RAM Sleep Mode"
textline "                                     "
bitfld.long 0x00 28. " ROM_PD                     ,array power and periph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " DSPTCM_REGF_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " DSPTCM_REGF_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " DSPCACHE_REGF_PPD          ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " DSPCACHE_REGF_APD          ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " CASPER_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " CASPER_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " USDHC1_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " USDHC1_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " USDHC0_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " USDHC0_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " USBHS_SRAM_PPD             ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " USBHS_SRAM_APD             ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " FLEXSPI_SRAM_PPD           ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " FLEXSPI_SRAM_APD           ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " PQ_SRAM_PPD                ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " PQ_SRAM_APD                ,Array power" "0: ENABLED,1: POWER_DOWN"
group.long 0x608++0x03
line.long 0x00 "PDSLEEPCFG2,no description available"
bitfld.long 0x00 29. " SRAM_IF29_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
group.long 0x60C++0x03
line.long 0x00 "PDSLEEPCFG3,no description available"
bitfld.long 0x00 29. " SRAM_IF29_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
group.long 0x610++0x03
line.long 0x00 "PDRUNCFG0,no description available"
bitfld.long 0x00 29. " HSPAD2_REF_PD              ,High speed Pad vdde2 reference blocks" "0: High Speed Pad VREF Enabled,1: High Speed Pad VREF in Power Down"
textline "                                     "
bitfld.long 0x00 28. " HSPAD2_VDET_LP             ,High Speed Pad vdde2 voltage detect block" "0: High Speed Pad VDET in Normal Mode,1: High Speed Pad VDET in Sleep Mode"
textline "                                     "
bitfld.long 0x00 27. " HSPAD0_REF_PD              ,High speed Pad vdde0 reference blocks" "0: High Speed Pad VREF Enabled,1: High Speed Pad VREF in Power Down"
textline "                                     "
bitfld.long 0x00 26. " HSPAD0_VDET_LP             ,High Speed Pad vdde0 voltage detect block" "0: High Speed Pad VDET in Normal Mode,1: High Speed Pad VDET in Sleep Mode"
textline "                                     "
bitfld.long 0x00 25. " ACMP_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " ADCTEMPSNS_PD              ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " ADC_LP                     ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " ADC_PD                     ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " AUDPLLANA_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " AUDPLLLDO_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SYSPLLANA_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SYSPLLLDO_PD               ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " FFRO_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SFRO_PD                    ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " LPOSC_PD                   ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SYSXTAL_PD                 ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " HVDCORE_PD                 ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " LVDCORE_LP                 ,no description available" "0: LVD0V85 HP Mode,1: LVD0V85 LP Mode"
textline "                                     "
bitfld.long 0x00 8. " PORCORE_LP                 ,no description available" "0: LVD0V6 HP Mode,1: LVD0V6 LP Mode"
textline "                                     "
bitfld.long 0x00 7. " HVD1V8_PD                  ,no description available" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " PMCREF_LP                  ,no description available" "0: PMCREF HP Mode,1: PMCREF LP Mode"
textline "                                     "
bitfld.long 0x00 4. " VDDCOREREG_LP              ,no description available" "0: VDDCOREREG HP Mode,1: LP_MODE"
textline "                                     "
bitfld.long 0x00 2. " PMIC_MODE1                 ,no description available" "0: Set Mode1 to 0,1: Set Mode1 to 1"
textline "                                     "
bitfld.long 0x00 1. " PMIC_MODE0                 ,no description available" "0: Set Mode0 to 0,1: Set Mode0 to 1"
group.long 0x614++0x03
line.long 0x00 "PDRUNCFG1,no description available"
bitfld.long 0x00 31. " SRAM_SLEEP                 ,Needed when vddcore can be smaller than 0" "0: RAM Normal Mode,1: RAM Sleep Mode"
textline "                                     "
bitfld.long 0x00 28. " ROM_PD                     ,array power and periph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " DSPTCM_REGF_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " DSPTCM_REGF_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " DSPCACHE_REGF_PPD          ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " DSPCACHE_REGF_APD          ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " CASPER_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " CASPER_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " USDHC1_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " USDHC1_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " USDHC0_SRAM_PPD            ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " USDHC0_SRAM_APD            ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " USBHS_SRAM_PPD             ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " USBHS_SRAM_APD             ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " FLEXSPI_SRAM_PPD           ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " FLEXSPI_SRAM_APD           ,Array power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " PQ_SRAM_PPD                ,Peiph power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " PQ_SRAM_APD                ,Array power" "0: ENABLED,1: POWER_DOWN"
group.long 0x618++0x03
line.long 0x00 "PDRUNCFG2,no description available"
bitfld.long 0x00 29. " SRAM_IF29_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_APD              ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_APD               ,Array Power" "0: ENABLED,1: POWER_DOWN"
group.long 0x61C++0x03
line.long 0x00 "PDRUNCFG3,no description available"
bitfld.long 0x00 29. " SRAM_IF29_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_PPD              ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_PPD               ,Periph Power" "0: ENABLED,1: POWER_DOWN"
group.long 0x620++0x03
line.long 0x00 "PDRUNCFG0_SET,no description available"
bitfld.long 0x00 29. " HSPAD2_REF_PD              ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 28. " HSPAD2_VDET_LP             ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 27. " HSPAD0_REF_PD              ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 26. " HSPAD0_VDET_LP             ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 25. " ACMP_PD                    ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 23. " ADCTEMPSNS_PD              ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 22. " ADC_LP                     ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 21. " ADC_PD                     ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 20. " AUDPLLANA_PD               ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 19. " AUDPLLLDO_PD               ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 18. " SYSPLLANA_PD               ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 17. " SYSPLLLDO_PD               ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 16. " FFRO_PD                    ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 15. " SFRO_PD                    ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 14. " LPOSC_PD                   ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 13. " SYSXTAL_PD                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 12. " FBB_PD                     ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 11. " RBB_PD                     ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 10. " HVDCORE_PD                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 9. " LVDCORE_LP                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 8. " PORCORE_LP                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 7. " HVD1V8_PD                  ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 6. " PMCREF_LP                  ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 4. " VDDCOREREG_LP              ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 2. " PMIC_MODE1                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 1. " PMIC_MODE0                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG0 Bit"
group.long 0x624++0x03
line.long 0x00 "PDRUNCFG1_SET,no description available"
bitfld.long 0x00 31. " SRAM_SLEEP                 ,no description available" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 28. " ROM_PD                     ,array power and periph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 27. " DSPTCM_REGF_PPD            ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 26. " DSPTCM_REGF_APD            ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 25. " DSPCACHE_REGF_PPD          ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 24. " DSPCACHE_REGF_APD          ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 11. " CASPER_SRAM_PPD            ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 10. " CASPER_SRAM_APD            ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 9. " USDHC1_SRAM_PPD            ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 8. " USDHC1_SRAM_APD            ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 7. " USDHC0_SRAM_PPD            ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 6. " USDHC0_SRAM_APD            ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 5. " USBHS_SRAM_PPD             ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 4. " USBHS_SRAM_APD             ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 3. " FLEXSPI_SRAM_PPD           ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 2. " FLEXSPI_SRAM_APD           ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 1. " PQ_SRAM_PPD                ,Peiph power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 0. " PQ_SRAM_APD                ,Array power" "0: NO_EFFECT,1: Sets the PDRUNCFG1 Bit"
group.long 0x628++0x03
line.long 0x00 "PDRUNCFG2_SET,no description available"
bitfld.long 0x00 29. " SRAM_IF29_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_APD              ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_APD               ,Array Power" "0: NO_EFFECT,1: Sets the PDRUNCFG2 Bit"
group.long 0x62C++0x03
line.long 0x00 "PDRUNCFG3_SET,no description available"
bitfld.long 0x00 29. " SRAM_IF29_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_PPD              ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_PPD               ,Periph Power" "0: NO_EFFECT,1: Sets the PDRUNCFG3 Bit"
group.long 0x630++0x03
line.long 0x00 "PDRUNCFG0_CLR,no description available"
bitfld.long 0x00 29. " HSPAD2_REF_PD              ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 28. " HSPAD2_VDET_LP             ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 27. " HSPAD0_REF_PD              ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 26. " HSPAD0_VDET_LP             ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 25. " ACMP_PD                    ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 23. " ADCTEMPSNS_PD              ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 22. " ADC_LP                     ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 21. " ADC_PD                     ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 20. " AUDPLLANA_PD               ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 19. " AUDPLLLDO_PD               ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 18. " SYSPLLANA_PD               ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 17. " SYSPLLLDO_PD               ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 16. " FFRO_PD                    ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 15. " SFRO_PD                    ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 14. " LPOSC_PD                   ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 13. " SYSXTAL_PD                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 12. " FBB_PD                     ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 11. " RBB_PD                     ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 10. " HVDCORE_PD                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 9. " LVDCORE_LP                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 8. " PORCORE_LP                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 7. " HVD1V8_PD                  ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 6. " PMCREF_LP                  ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 4. " VDDCOREREG_LP              ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 2. " PMIC_MODE1                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
textline "                                     "
bitfld.long 0x00 1. " PMIC_MODE0                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG0 Bit"
group.long 0x634++0x03
line.long 0x00 "PDRUNCFG1_CLR,no description available"
bitfld.long 0x00 31. " SRAM_SLEEP                 ,no description available" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 28. " ROM_PD                     ,array power and periph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 27. " DSPTCM_REGF_PPD            ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 26. " DSPTCM_REGF_APD            ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 25. " DSPCACHE_REGF_PPD          ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 24. " DSPCACHE_REGF_APD          ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 11. " CASPER_SRAM_PPD            ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 10. " CASPER_SRAM_APD            ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 9. " USDHC1_SRAM_PPD            ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 8. " USDHC1_SRAM_APD            ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 7. " USDHC0_SRAM_PPD            ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 6. " USDHC0_SRAM_APD            ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 5. " USBHS_SRAM_PPD             ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 4. " USBHS_SRAM_APD             ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 3. " FLEXSPI_SRAM_PPD           ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 2. " FLEXSPI_SRAM_APD           ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 1. " PQ_SRAM_PPD                ,Peiph power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
textline "                                     "
bitfld.long 0x00 0. " PQ_SRAM_APD                ,Array power" "0: NO_EFFECT,1: Clears the PDRUNCFG1 Bit"
group.long 0x638++0x03
line.long 0x00 "PDRUNCFG2_CLR,no description available"
bitfld.long 0x00 29. " SRAM_IF29_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_APD              ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_APD               ,Array Power" "0: NO_EFFECT,1: Clears the PDRUNCFG2 Bit"
group.long 0x63C++0x03
line.long 0x00 "PDRUNCFG3_CLR,no description available"
bitfld.long 0x00 29. " SRAM_IF29_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 28. " SRAM_IF28_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 27. " SRAM_IF27_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 26. " SRAM_IF26_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 25. " SRAM_IF25_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 24. " SRAM_IF24_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 23. " SRAM_IF23_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 22. " SRAM_IF22_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 21. " SRAM_IF21_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 20. " SRAM_IF20_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 19. " SRAM_IF19_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 18. " SRAM_IF18_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 17. " SRAM_IF17_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 16. " SRAM_IF16_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 15. " SRAM_IF15_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 14. " SRAM_IF14_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 13. " SRAM_IF13_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 12. " SRAM_IF12_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 11. " SRAM_IF11_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 10. " SRAM_IF10_PPD              ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 9. " SRAM_IF9_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 8. " SRAM_IF8_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 7. " SRAM_IF7_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 6. " SRAM_IF6_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 5. " SRAM_IF5_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 4. " SRAM_IF4_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 3. " SRAM_IF3_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 2. " SRAM_IF2_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 1. " SRAM_IF1_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
textline "                                     "
bitfld.long 0x00 0. " SRAM_IF0_PPD               ,Periph Power" "0: NO_EFFECT,1: Clears the PDRUNCFG3 Bit"
group.long 0x680++0x03
line.long 0x00 "STARTEN0,no description available"
bitfld.long 0x00 31. " RNG                        ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 29. " HWVAD0                     ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 28. " SECUREVIOLATION            ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 27. " HYPERVISOR                 ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 25. " DMIC0                      ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 24. " ACMP                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 22. " ADC0                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 21. " FLEXCOMM15                 ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 20. " FLEXCOMM14                 ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 19. " FLEXCOMM5                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 18. " FLEXCOMM4                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 17. " FLEXCOMM3                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 16. " FLEXCOMM2                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 15. " FLEXCOMM1                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 14. " FLEXCOMM0                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 13. " CT32BIT3                   ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 12. " SCT0                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 11. " CT32BIT1                   ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 10. " CT32BIT0                   ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 9. " MRT0                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 8. " UTICK0                     ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 7. " GPIO_INT0_IRQ3             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ2             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ1             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ0             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 3. " NSHSGPIO_INT1              ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 2. " NSHSGPIO_INT0              ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 1. " DMAC0                      ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 0. " WDT0                       ,no description available" "0: DISABLED,1: ENABLED"
group.long 0x684++0x03
line.long 0x00 "STARTEN1,no description available"
bitfld.long 0x00 27. " SHA                        ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 26. " PMIC                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 25. " CASPER                     ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 24. " POWERQUAD                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 23. " PUF                        ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 22. " DMAC1                      ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 19. " USB_NEEDCLK                ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 18. " USB_IRQ                    ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 17. " I3C0                       ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 16. " SHSGPIO_INT1               ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 15. " SHSGPIO_INT0               ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 14. " SDIO1                      ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 13. " SDIO0                      ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 12. " FLEXCOMM7                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 11. " FLEXCOMM6                  ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 10. " FLEXSPI                    ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 9. " OS_EVENT_TIMER_WU          ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 8. " CT32BIT4                   ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 7. " CT32BIT2                   ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ7             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ6             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ5             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 3. " GPIO_INT0_IRQ4             ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 2. " MU                         ,no description available" "0: DISABLED,1: ENABLED"
textline "                                     "
bitfld.long 0x00 0. " RTC_LITE0_ALARM_or_WAKEUP  ,no description available" "0: DISABLED,1: ENABLED"
group.long 0x6A0++0x03
line.long 0x00 "STARTEN0_SET,no description available"
bitfld.long 0x00 31. " RNG                        ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 29. " HWVAD0                     ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 28. " SECUREVIOLATION            ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 27. " HYPERVISOR                 ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 25. " DMIC0                      ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 24. " ACMP                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 22. " ADC0                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 21. " FLEXCOMM15                 ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 20. " FLEXCOMM14                 ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 19. " FLEXCOMM5                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 18. " FLEXCOMM4                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 17. " FLEXCOMM3                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 16. " FLEXCOMM2                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 15. " FLEXCOMM1                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 14. " FLEXCOMM0                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 13. " CT32BIT3                   ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 12. " SCT0                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 11. " CT32BIT1                   ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 10. " CT32BIT0                   ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 9. " MRT0                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 8. " UTICK0                     ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 7. " GPIO_INT0_IRQ3             ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ2             ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ1             ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ0             ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 3. " NSHSGPIO_INT1              ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 2. " NSHSGPIO_INT0              ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 1. " DMAC0                      ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 0. " WDT0                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN0 Bit"
wgroup.long 0x6A4++0x03
line.long 0x00 "STARTEN1_SET,no description available"
bitfld.long 0x00 27. " SHA                        ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 26. " PMIC                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 25. " CASPER                     ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 24. " POWERQUAD                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 23. " PUF                        ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 22. " DMAC1                      ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 19. " USB_NEEDCLK                ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 18. " USB_IRQ                    ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 17. " I3C0                       ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 16. " SHSGPIO_INT1               ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 15. " SHSGPIO_INT0               ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 14. " SDIO1                      ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 13. " SDIO0                      ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 12. " FLEXCOMM7                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 11. " FLEXCOMM6                  ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 10. " FLEXSPI                    ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 9. " OS_EVENT_TIMER_WU          ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 8. " CT32BIT4                   ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 7. " CT32BIT2                   ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ7             ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ6             ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ5             ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 3. " GPIO_INT0_IRQ4             ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 2. " MU                         ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 0. " RTC_LITE0_ALARM_or_WAKEUP  ,no description available" "0: NO_EFFECT,1: Sets the START_EN1 Bit"
group.long 0x6C0++0x03
line.long 0x00 "STARTEN0_CLR,no description available"
bitfld.long 0x00 31. " RNG                        ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 29. " HWVAD0                     ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 28. " SECUREVIOLATION            ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 27. " HYPERVISOR                 ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 25. " DMIC0                      ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 24. " ACMP                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 22. " ADC0                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 21. " FLEXCOMM15                 ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 20. " FLEXCOMM14                 ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 19. " FLEXCOMM5                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 18. " FLEXCOMM4                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 17. " FLEXCOMM3                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 16. " FLEXCOMM2                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 15. " FLEXCOMM1                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 14. " FLEXCOMM0                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 13. " CT32BIT3                   ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 12. " SCT0                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 11. " CT32BIT1                   ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 10. " CT32BIT0                   ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 9. " MRT0                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 8. " UTICK0                     ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 7. " GPIO_INT0_IRQ3             ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ2             ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ1             ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ0             ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 3. " NSHSGPIO_INT1              ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 2. " NSHSGPIO_INT0              ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 1. " DMAC0                      ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
textline "                                     "
bitfld.long 0x00 0. " WDT0                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN0 Bit"
wgroup.long 0x6C4++0x03
line.long 0x00 "STARTEN1_CLR,no description available"
bitfld.long 0x00 27. " SHA                        ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 26. " PMIC                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 25. " CASPER                     ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 24. " POWERQUAD                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 23. " PUF                        ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 22. " DMAC1                      ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 19. " USB_NEEDCLK                ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 18. " USB_IRQ                    ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 17. " I3C0                       ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 16. " SHSGPIO_INT1               ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 15. " SHSGPIO_INT0               ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 14. " SDIO1                      ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 13. " SDIO0                      ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 12. " FLEXCOMM7                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 11. " FLEXCOMM6                  ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 10. " FLEXSPI                    ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 9. " OS_EVENT_TIMER_WU          ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 8. " CT32BIT4                   ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 7. " CT32BIT2                   ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 6. " GPIO_INT0_IRQ7             ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 5. " GPIO_INT0_IRQ6             ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 4. " GPIO_INT0_IRQ5             ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 3. " GPIO_INT0_IRQ4             ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 2. " MU                         ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
textline "                                     "
bitfld.long 0x00 0. " RTC_LITE0_ALARM_or_WAKEUP  ,no description available" "0: NO_EFFECT,1: Clears the START_EN1 Bit"
group.long 0x780++0x03
line.long 0x00 "HWWAKE,Hardware Wake-up control register"
bitfld.long 0x00 4. " DMAC1WAKE                  ,Wake for DMAC1" "0,1"
textline "                                     "
bitfld.long 0x00 3. " DMAC0WAKE                  ,Wake for DMAC0" "0,1"
textline "                                     "
bitfld.long 0x00 2. " DMICWAKE                   ,Wake for Digital Microphone" "0,1"
textline "                                     "
bitfld.long 0x00 1. " FCWAKE                     ,Wake for Flexcomm Interfaces" "0,1"
textline "                                     "
bitfld.long 0x00 0. " FORCEWAKE                  ,Force peripheral clocking to stay on during deep-sleep mode" "0,1"
group.long 0xE50++0x03
line.long 0x00 "BOOTSTATESEED0,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE54++0x03
line.long 0x00 "BOOTSTATESEED1,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE58++0x03
line.long 0x00 "BOOTSTATESEED2,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE5C++0x03
line.long 0x00 "BOOTSTATESEED3,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE60++0x03
line.long 0x00 "BOOTSTATESEED4,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE64++0x03
line.long 0x00 "BOOTSTATESEED5,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE68++0x03
line.long 0x00 "BOOTSTATESEED6,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE6C++0x03
line.long 0x00 "BOOTSTATESEED7,boot state seed register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATESEED              ,A 256-bit random number set by boot ROM on each restart"
group.long 0xE70++0x03
line.long 0x00 "BOOTSTATEHMAC0,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE74++0x03
line.long 0x00 "BOOTSTATEHMAC1,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE78++0x03
line.long 0x00 "BOOTSTATEHMAC2,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE7C++0x03
line.long 0x00 "BOOTSTATEHMAC3,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE80++0x03
line.long 0x00 "BOOTSTATEHMAC4,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE84++0x03
line.long 0x00 "BOOTSTATEHMAC5,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE88++0x03
line.long 0x00 "BOOTSTATEHMAC6,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xE8C++0x03
line.long 0x00 "BOOTSTATEHMAC7,boot state hmac register"
hexmask.long 0x00 0.--31. 1. " BOOTSTATEHMAC              ,HMAC of boot state used for attestation"
group.long 0xEF8++0x03
line.long 0x00 "FLEXSPIPADCTRL,FLEXSPI IO pads ctrl register"
rbitfld.long 0x00 24. " COMPOK                     ,FLEXSPI pad compensation circuit status" "0,1"
textline "                                     "
rbitfld.long 0x00 20.--23. " NASRCP                     ,FLEXSPI pad compensation circuit status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
rbitfld.long 0x00 16.--19. " NASRCN                     ,FLEXSPI pad compensation circuit status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
bitfld.long 0x00 11. " COMPEN                     ,Drive FLEXSPI pad compensation circuit" "0,1"
textline "                                     "
bitfld.long 0x00 10. " COMPTQ                     ,Drive FLEXSPI pad compensation circuit" "0,1"
textline "                                     "
bitfld.long 0x00 9. " FREEZE                     ,Drive FLEXSPI pad compensation circuit" "0,1"
textline "                                     "
bitfld.long 0x00 8. " FASTFRZ                    ,Drive FLEXSPI pad compensation circuit" "0,1"
textline "                                     "
bitfld.long 0x00 4.--7. " RASRCP                     ,Drive FLEXSPI pad compensation circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
bitfld.long 0x00 0.--3. " RASRCN                     ,Drive FLEXSPI pad compensation circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEFC++0x03
line.long 0x00 "SDIOPADCTL,sdio pad ctrl"
rbitfld.long 0x00 24. " COMPOK                     ,SDIO Pad Compensation Circuit Status" "0,1"
textline "                                     "
rbitfld.long 0x00 20.--23. " NASRCP                     ,SDIO Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
rbitfld.long 0x00 16.--19. " NASRCN                     ,SDIO Pad Compensation Circuit Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
bitfld.long 0x00 11. " COMPEN                     ,Drives SDIO Pad Compensation Circuit" "0,1"
textline "                                     "
bitfld.long 0x00 10. " COMPTQ                     ,Drives SDIO Pad Compensation Circuit" "0,1"
textline "                                     "
bitfld.long 0x00 9. " FREEZE                     ,Drives SDIO Pad Compensation Circuit" "0,1"
textline "                                     "
bitfld.long 0x00 8. " FASTFRZ                    ,Drives SDIO Pad Compensation Circuit" "0,1"
textline "                                     "
bitfld.long 0x00 4.--7. " RASRCP                     ,Drives SDIO Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                     "
bitfld.long 0x00 0.--3. " RASRCN                     ,Drives SDIO Pad Compensation Circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF00++0x03
line.long 0x00 "DICEHWREG[0],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF04++0x03
line.long 0x00 "DICEHWREG[1],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF08++0x03
line.long 0x00 "DICEHWREG[2],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF0C++0x03
line.long 0x00 "DICEHWREG[3],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF10++0x03
line.long 0x00 "DICEHWREG[4],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF14++0x03
line.long 0x00 "DICEHWREG[5],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF18++0x03
line.long 0x00 "DICEHWREG[6],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
group.long 0xF1C++0x03
line.long 0x00 "DICEHWREG[7],DICE General Purpose 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " DICEHWREG                  ,DICE General Purpose 32-Bit Data Register"
rgroup.long 0xF50++0x03
line.long 0x00 "UUID0,UUIDn 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " uuid                       ,no description available"
rgroup.long 0xF54++0x03
line.long 0x00 "UUID1,UUIDn 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " uuid                       ,no description available"
rgroup.long 0xF58++0x03
line.long 0x00 "UUID2,UUIDn 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " uuid                       ,no description available"
rgroup.long 0xF5C++0x03
line.long 0x00 "UUID3,UUIDn 32-Bit Data Register"
hexmask.long 0x00 0.--31. 1. " uuid                       ,no description available"
group.long 0xF80++0x03
line.long 0x00 "AESKEY_SRCSEL,no description available"
bitfld.long 0x00 0.--1. " AESKEY_SRCSEL              ,AES Key Source Select:" "0,1,2,3"
group.long 0xF84++0x03
line.long 0x00 "OTFADKEY_SRCSEL,no description available"
bitfld.long 0x00 0.--1. " OTFADKEY_SRCSEL            ,OTFAD Key Source Select:" "0,1,2,3"
group.long 0xF88++0x03
line.long 0x00 "HASHHWKEYDISABLE,This register is a write once only register. any write will lock the value until the next reset"
hexmask.long 0x00 0.--31. 1. " HASHHWKEYDISABLE           ,This register control the access to AES keys delivered through secret HW bus from PUF and OTP to AES.."
group.long 0xFA0++0x03
line.long 0x00 "DBG_LOCKEN,Debug Write Lock registers"
bitfld.long 0x00 0.--3. " DBG_LOCKEN                 ,Debug Write Lock the following registers: DBG_FEATURES DBG_FEATURES_DP CS_PROTTEST CS_PROTCPU0 CS_PR.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFA4++0x03
line.long 0x00 "DBG_FEATURES,The DBG_LOCKEN register is reset by POR and will disable the write capability to the DBG_FEATURES. D.."
bitfld.long 0x00 6.--7. " SPNIDEN                    ,CM33 SPNIDEN Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 4.--5. " SPIDEN                     ,CM33 SPID Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 2.--3. " NIDEN                      ,CM33 NID Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 0.--1. " DBGEN                      ,CM33 Debug Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
group.long 0xFA8++0x03
line.long 0x00 "DBG_FEATURES_DP,The DBG_LOCKEN register will disable the write capability to the DBG_FEATURES. DBG_FEATURES_DP. CS_P.."
bitfld.long 0x00 6.--7. " SPNIDEN                    ,CM33 SPNIDEN Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 4.--5. " SPIDEN                     ,CM33 SPID Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 2.--3. " NIDEN                      ,CM33 NID Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
textline "                                     "
bitfld.long 0x00 0.--1. " DBGEN                      ,CM33 Debug Enable Control" "0: ENABLED,1: DISBALED1,2: DISABLED2,3: DISABLED3"
group.long 0xFAC++0x03
line.long 0x00 "HWUNLOCK_DISABLE,The DBG_LOCKEN register is reset by POR and will disable the write capability to the DBG_FEATURES. D.."
bitfld.long 0x00 0.--3. " HWUNLOCK_DISABLE           ,HW Unlock / Disable: Disable the OTP unlock for test. Teal and DSP debug Write any value to disable .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFB4++0x03
line.long 0x00 "CS_PROTCPU0,The DBG_LOCKEN register is reset by POR and will disable the write capability to the DBG_FEATURES. D.."
hexmask.long 0x00 0.--31. 1. " CS_PROTCPU0                ,Controls M33 AP Enable"
group.long 0xFB8++0x03
line.long 0x00 "CS_PROTCPU1,The DBG_LOCKEN register is reset by POR and will disable the write capability to the DBG_FEATURES. D.."
hexmask.long 0x00 0.--31. 1. " CS_PROTCPU1                ,Controls HIFI4 AP Enable"
group.long 0xFC0++0x03
line.long 0x00 "DBG_AUTH_SCRATCH,The DBG_LOCKEN register is reset by POR and will disable the write capability to the DBG_FEATURES. D.."
hexmask.long 0x00 0.--31. 1. " DBG_AUTH_SCRATCH           ,Debug authorization scratch register for S/W"
group.long 0xFD0++0x03
line.long 0x00 "KEY_BLOCK,The KEY_BLOCK register is reset by POR and can be read at any time"
hexmask.long 0x00 0.--31. 1. " KEY_BLOCK                  ,key block register"
width 0x0B
tree.end
tree "SYSCTL1"
base ad:0x40022000
width 16.
group.long 0x10++0x03
line.long 0x00 "MCLKPINDIR,mclk direction control"
bitfld.long 0x00 0. " MCLKPINDIR    ,Selects one of the M33 interrupt sources" "0: MCLK is in input direction,1: MCLK is in the output direction"
group.long 0x30++0x03
line.long 0x00 "DSPNMISRCSEL,DSP NMI source selection"
bitfld.long 0x00 31. " NMIEN         ,NMI interrupt enable" "0: Disable NMI Interrupt,1: Enable NMI Interrupt"
textline "                         "
bitfld.long 0x00 0.--4. " NMISRCSEL     ,Selects one of the DSP interrupt sources as the NMI source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40++0x03
line.long 0x00 "FCCTRLSEL0,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x44++0x03
line.long 0x00 "FCCTRLSEL1,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x48++0x03
line.long 0x00 "FCCTRLSEL2,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x4C++0x03
line.long 0x00 "FCCTRLSEL3,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x50++0x03
line.long 0x00 "FCCTRLSEL4,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x54++0x03
line.long 0x00 "FCCTRLSEL5,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x58++0x03
line.long 0x00 "FCCTRLSEL6,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x5C++0x03
line.long 0x00 "FCCTRLSEL7,flexcomm control selection N"
bitfld.long 0x00 24.--25. " DATAOUTSEL    ,DATA OUT Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 16.--17. " DATAINSEL     ,DATA IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 8.--9. " WSINSEL       ,WS IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
textline "                         "
bitfld.long 0x00 0.--1. " SCKINSEL      ,SCK IN Select" "0: Original FLEXCOMM I2S signals,1: SHARED_SET0_I2S_SIGNALS,2: SHARED_SET1_I2S_SIGNALS,"
group.long 0x80++0x03
line.long 0x00 "SHAREDCTRLSET0,shared control set N"
bitfld.long 0x00 23. " FC7DATAOUTEN  ,FLEXCOMM7 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 22. " FC6DATAOUTEN  ,FLEXCOMM6 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 21. " FC5DATAOUTEN  ,FLEXCOMM5 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 20. " FC4DATAOUTEN  ,FLEXCOMM4 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 19. " FC3DATAOUTEN  ,FLEXCOMM3 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 18. " F20DATAOUTEN  ,FLEXCOMM2 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 17. " FC1DATAOUTEN  ,FLEXCOMM1 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 16. " FC0DATAOUTEN  ,FLEXCOMM0 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 8.--10. " SHAREDDATASEL ,Shared DATA Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
textline "                         "
bitfld.long 0x00 4.--6. " SHAREDWSSEL   ,Shared WS Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
textline "                         "
bitfld.long 0x00 0.--2. " SHAREDSCKSEL  ,Shared SCK Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
group.long 0x84++0x03
line.long 0x00 "SHAREDCTRLSET1,shared control set N"
bitfld.long 0x00 23. " FC7DATAOUTEN  ,FLEXCOMM7 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 22. " FC6DATAOUTEN  ,FLEXCOMM6 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 21. " FC5DATAOUTEN  ,FLEXCOMM5 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 20. " FC4DATAOUTEN  ,FLEXCOMM4 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 19. " FC3DATAOUTEN  ,FLEXCOMM3 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 18. " F20DATAOUTEN  ,FLEXCOMM2 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 17. " FC1DATAOUTEN  ,FLEXCOMM1 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 16. " FC0DATAOUTEN  ,FLEXCOMM0 DATAOUT OUTPUT ENABLE" "0: INPUT,1: OUTPUT"
textline "                         "
bitfld.long 0x00 8.--10. " SHAREDDATASEL ,Shared DATA Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
textline "                         "
bitfld.long 0x00 4.--6. " SHAREDWSSEL   ,Shared WS Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
textline "                         "
bitfld.long 0x00 0.--2. " SHAREDSCKSEL  ,Shared SCK Select" "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,4: FLEXCOMM4,5: FLEXCOMM5,6: FLEXCOMM6,7: FLEXCOMM7"
group.long 0x200++0x03
line.long 0x00 "RXEVPULSEGEN,RX Event Pulse Generator"
bitfld.long 0x00 0. " RXEVPULSEGEN  ,RX Event Pulse Generator" "0: NO_EFFECT,1: Pulse RXEV High for one PSCLK cycle"
width 0x0B
tree.end
tree "TRNG"
base ad:0x40138000
width 12.
group.long 0x00++0x03
line.long 0x00 "MCTL,Miscellaneous Control Register"
bitfld.long 0x00 16. " PRGM        ,Programming Mode Select" "0,1"
textline "                     "
rbitfld.long 0x00 13. " TSTOP_OK    ,TRNG_OK_TO_STOP" "0,1"
textline "                     "
eventfld.long 0x00 12. " ERR         ,Read: Error status" "0,1"
textline "                     "
rbitfld.long 0x00 11. " TST_OUT     ,Read only: Test point inside ring oscillator" "0,1"
textline "                     "
rbitfld.long 0x00 10. " ENT_VAL     ,Read only: Entropy Valid" "0,1"
textline "                     "
rbitfld.long 0x00 9. " FCT_VAL     ,Read only: Frequency Count Valid" "0,1"
textline "                     "
rbitfld.long 0x00 8. " FCT_FAIL    ,Read only: Frequency Count Fail" "0,1"
textline "                     "
bitfld.long 0x00 7. " FOR_SCLK    ,Force System Clock" "0,1"
textline "                     "
bitfld.long 0x00 6. " RST_DEF     ,Reset Defaults" "0,1"
textline "                     "
bitfld.long 0x00 5. " TRNG_ACC    ,TRNG Access Mode" "0,1"
textline "                     "
bitfld.long 0x00 2.--3. " OSC_DIV     ,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
textline "                     "
bitfld.long 0x00 0.--1. " SAMP_MODE   ,Sample Mode" "0: use Von Neumann data into both Entropy shifter and Statistical Checker,1: use raw data into both Entropy shifter and Statistical Checker,2: use Von Neumann data into Entropy shifter,3: undefined/reserved"
group.long 0x04++0x03
line.long 0x00 "SCMISC,Statistical Check Miscellaneous Register"
bitfld.long 0x00 16.--19. " RTY_CT      ,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX    ,LONG RUN MAX LIMIT"
group.long 0x08++0x03
line.long 0x00 "PKRRNG,Poker Range Register"
hexmask.long.word 0x00 0.--15. 1. " PKR_RNG     ,Poker Range"
group.long 0x0C++0x03
line.long 0x00 "PKRMAX,Poker Maximum Limit Register"
hexmask.long.tbyte 0x00 0.--23. 1. " PKR_MAX     ,Poker Maximum Limit"
rgroup.long 0x0C++0x03
line.long 0x00 "PKRSQ,Poker Square Calculation Result Register"
hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ      ,Poker Square Calculation Result"
group.long 0x10++0x03
line.long 0x00 "SDCTL,Seed Control Register"
hexmask.long.word 0x00 16.--31. 1. " ENT_DLY     ,Entropy Delay"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " SAMP_SIZE   ,Sample Size"
group.long 0x14++0x03
line.long 0x00 "SBLIM,Sparse Bit Limit Register"
hexmask.long.word 0x00 0.--9. 1. " SB_LIM      ,Sparse Bit Limit"
rgroup.long 0x14++0x03
line.long 0x00 "TOTSAM,Total Samples Register"
hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM     ,Total Samples"
group.long 0x18++0x03
line.long 0x00 "FRQMIN,Frequency Count Minimum Limit Register"
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_MIN     ,Frequency Count Minimum Limit"
rgroup.long 0x1C++0x03
line.long 0x00 "FRQCNT,Frequency Count Register"
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CT      ,Frequency Count"
group.long 0x1C++0x03
line.long 0x00 "FRQMAX,Frequency Count Maximum Limit Register"
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_MAX     ,Frequency Counter Maximum Limit"
rgroup.long 0x20++0x03
line.long 0x00 "SCMC,Statistical Check Monobit Count Register"
hexmask.long.word 0x00 0.--15. 1. " MONO_CT     ,Monobit Count"
group.long 0x20++0x03
line.long 0x00 "SCML,Statistical Check Monobit Limit Register"
hexmask.long.word 0x00 16.--31. 1. " MONO_RNG    ,Monobit Range"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " MONO_MAX    ,Monobit Maximum Limit"
rgroup.long 0x24++0x03
line.long 0x00 "SCR1C,Statistical Check Run Length 1 Count Register"
hexmask.long.word 0x00 16.--30. 1. " R1_1_CT     ,Runs of One. Length 1 Count"
textline "                     "
hexmask.long.word 0x00 0.--14. 1. " R1_0_CT     ,Runs of Zero. Length 1 Count"
group.long 0x24++0x03
line.long 0x00 "SCR1L,Statistical Check Run Length 1 Limit Register"
hexmask.long.word 0x00 16.--30. 1. " RUN1_RNG    ,Run Length 1 Range"
textline "                     "
hexmask.long.word 0x00 0.--14. 1. " RUN1_MAX    ,Run Length 1 Maximum Limit"
rgroup.long 0x28++0x03
line.long 0x00 "SCR2C,Statistical Check Run Length 2 Count Register"
hexmask.long.word 0x00 16.--29. 1. " R2_1_CT     ,Runs of One. Length 2 Count"
textline "                     "
hexmask.long.word 0x00 0.--13. 1. " R2_0_CT     ,Runs of Zero. Length 2 Count"
group.long 0x28++0x03
line.long 0x00 "SCR2L,Statistical Check Run Length 2 Limit Register"
hexmask.long.word 0x00 16.--29. 1. " RUN2_RNG    ,Run Length 2 Range"
textline "                     "
hexmask.long.word 0x00 0.--13. 1. " RUN2_MAX    ,Run Length 2 Maximum Limit"
rgroup.long 0x2C++0x03
line.long 0x00 "SCR3C,Statistical Check Run Length 3 Count Register"
hexmask.long.word 0x00 16.--28. 1. " R3_1_CT     ,Runs of Ones. Length 3 Count"
textline "                     "
hexmask.long.word 0x00 0.--12. 1. " R3_0_CT     ,Runs of Zeroes. Length 3 Count"
group.long 0x2C++0x03
line.long 0x00 "SCR3L,Statistical Check Run Length 3 Limit Register"
hexmask.long.word 0x00 16.--28. 1. " RUN3_RNG    ,Run Length 3 Range"
textline "                     "
hexmask.long.word 0x00 0.--12. 1. " RUN3_MAX    ,Run Length 3 Maximum Limit"
rgroup.long 0x30++0x03
line.long 0x00 "SCR4C,Statistical Check Run Length 4 Count Register"
hexmask.long.word 0x00 16.--27. 1. " R4_1_CT     ,Runs of One. Length 4 Count"
textline "                     "
hexmask.long.word 0x00 0.--11. 1. " R4_0_CT     ,Runs of Zero. Length 4 Count"
group.long 0x30++0x03
line.long 0x00 "SCR4L,Statistical Check Run Length 4 Limit Register"
hexmask.long.word 0x00 16.--27. 1. " RUN4_RNG    ,Run Length 4 Range"
textline "                     "
hexmask.long.word 0x00 0.--11. 1. " RUN4_MAX    ,Run Length 4 Maximum Limit"
rgroup.long 0x34++0x03
line.long 0x00 "SCR5C,Statistical Check Run Length 5 Count Register"
hexmask.long.word 0x00 16.--26. 1. " R5_1_CT     ,Runs of One. Length 5 Count"
textline "                     "
hexmask.long.word 0x00 0.--10. 1. " R5_0_CT     ,Runs of Zero. Length 5 Count"
group.long 0x34++0x03
line.long 0x00 "SCR5L,Statistical Check Run Length 5 Limit Register"
hexmask.long.word 0x00 16.--26. 1. " RUN5_RNG    ,Run Length 5 Range"
textline "                     "
hexmask.long.word 0x00 0.--10. 1. " RUN5_MAX    ,Run Length 5 Maximum Limit"
rgroup.long 0x38++0x03
line.long 0x00 "SCR6PC,Statistical Check Run Length 6+ Count Register"
hexmask.long.word 0x00 16.--26. 1. " R6P_1_CT    ,Runs of One. Length 6+ Count"
textline "                     "
hexmask.long.word 0x00 0.--10. 1. " R6P_0_CT    ,Runs of Zero. Length 6+ Count"
group.long 0x38++0x03
line.long 0x00 "SCR6PL,Statistical Check Run Length 6+ Limit Register"
hexmask.long.word 0x00 16.--26. 1. " RUN6P_RNG   ,Run Length 6+ Range"
textline "                     "
hexmask.long.word 0x00 0.--10. 1. " RUN6P_MAX   ,Run Length 6+ Maximum Limit"
rgroup.long 0x3C++0x03
line.long 0x00 "STATUS,Status Register"
bitfld.long 0x00 16.--19. " RETRY_CT    ,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 15. " TFMB        ,Test Fail. Mono Bit" "0,1"
textline "                     "
bitfld.long 0x00 14. " TFP         ,Test Fail. Poker" "0,1"
textline "                     "
bitfld.long 0x00 13. " TFLR        ,Test Fail. Long Run" "0,1"
textline "                     "
bitfld.long 0x00 12. " TFSB        ,Test Fail. Sparse Bit" "0,1"
textline "                     "
bitfld.long 0x00 11. " TF6PBR1     ,Test Fail. 6 Plus Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 10. " TF6PBR0     ,Test Fail. 6 Plus Bit Run. Sampling 0s" "0,1"
textline "                     "
bitfld.long 0x00 9. " TF5BR1      ,Test Fail. 5-Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 8. " TF5BR0      ,Test Fail. 5-Bit Run. Sampling 0s" "0,1"
textline "                     "
bitfld.long 0x00 7. " TF4BR1      ,Test Fail. 4-Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 6. " TF4BR0      ,Test Fail. 4-Bit Run. Sampling 0s" "0,1"
textline "                     "
bitfld.long 0x00 5. " TF3BR1      ,Test Fail. 3-Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 4. " TF3BR0      ,Test Fail. 3-Bit Run. Sampling 0s" "0,1"
textline "                     "
bitfld.long 0x00 3. " TF2BR1      ,Test Fail. 2-Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 2. " TF2BR0      ,Test Fail. 2-Bit Run. Sampling 0s" "0,1"
textline "                     "
bitfld.long 0x00 1. " TF1BR1      ,Test Fail. 1-Bit Run. Sampling 1s" "0,1"
textline "                     "
bitfld.long 0x00 0. " TF1BR0      ,Test Fail. 1-Bit Run. Sampling 0s" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "ENT[0],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x44++0x03
line.long 0x00 "ENT[1],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x48++0x03
line.long 0x00 "ENT[2],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x4C++0x03
line.long 0x00 "ENT[3],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x50++0x03
line.long 0x00 "ENT[4],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x54++0x03
line.long 0x00 "ENT[5],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x58++0x03
line.long 0x00 "ENT[6],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x5C++0x03
line.long 0x00 "ENT[7],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x60++0x03
line.long 0x00 "ENT[8],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x64++0x03
line.long 0x00 "ENT[9],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x68++0x03
line.long 0x00 "ENT[10],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x6C++0x03
line.long 0x00 "ENT[11],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x70++0x03
line.long 0x00 "ENT[12],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x74++0x03
line.long 0x00 "ENT[13],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x78++0x03
line.long 0x00 "ENT[14],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x7C++0x03
line.long 0x00 "ENT[15],Entropy Read Register"
hexmask.long 0x00 0.--31. 1. " ENT         ,Entropy Value"
rgroup.long 0x80++0x03
line.long 0x00 "PKRCNT10,Statistical Check Poker Count 1 and 0 Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT    ,Poker 1h Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT    ,Poker 0h Count"
rgroup.long 0x84++0x03
line.long 0x00 "PKRCNT32,Statistical Check Poker Count 3 and 2 Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT    ,Poker 3h Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT    ,Poker 2h Count"
rgroup.long 0x88++0x03
line.long 0x00 "PKRCNT54,Statistical Check Poker Count 5 and 4 Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT    ,Poker 5h Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT    ,Poker 4h Count"
rgroup.long 0x8C++0x03
line.long 0x00 "PKRCNT76,Statistical Check Poker Count 7 and 6 Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT    ,Poker 7h Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT    ,Poker 6h Count"
rgroup.long 0x90++0x03
line.long 0x00 "PKRCNT98,Statistical Check Poker Count 9 and 8 Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT    ,Poker 9h Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT    ,Poker 8h Count"
rgroup.long 0x94++0x03
line.long 0x00 "PKRCNTBA,Statistical Check Poker Count B and A Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT    ,Poker Bh Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT    ,Poker Ah Count"
rgroup.long 0x98++0x03
line.long 0x00 "PKRCNTDC,Statistical Check Poker Count D and C Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT    ,Poker Dh Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT    ,Poker Ch Count"
rgroup.long 0x9C++0x03
line.long 0x00 "PKRCNTFE,Statistical Check Poker Count F and E Register"
hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT    ,Poker Fh Count"
textline "                     "
hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT    ,Poker Eh Count"
group.long 0xA0++0x03
line.long 0x00 "SEC_CFG,Security Configuration Register"
bitfld.long 0x00 1. " NO_PRGM     ,If set. the TRNG registers cannot be programmed" "0: Programability of registers controlled only by the Miscellaneous Control Register's access mode bit,1: Overides Miscellaneous Control Register access mode and prevents TRNG register programming"
group.long 0xA4++0x03
line.long 0x00 "INT_CTRL,Interrupt Control Register"
bitfld.long 0x00 2. " FRQ_CT_FAIL ,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
textline "                     "
bitfld.long 0x00 1. " ENT_VAL     ,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
textline "                     "
bitfld.long 0x00 0. " HW_ERR      ,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding bit of INT_STATUS cleared,1: Corresponding bit of INT_STATUS active"
group.long 0xA8++0x03
line.long 0x00 "INT_MASK,Mask Register"
bitfld.long 0x00 2. " FRQ_CT_FAIL ,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
textline "                     "
bitfld.long 0x00 1. " ENT_VAL     ,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
textline "                     "
bitfld.long 0x00 0. " HW_ERR      ,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding interrupt of INT_STATUS is masked,1: Corresponding bit of INT_STATUS is active"
rgroup.long 0xAC++0x03
line.long 0x00 "INT_STATUS,Interrupt Status Register"
bitfld.long 0x00 2. " FRQ_CT_FAIL ,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors,1: The frequency counter has detected a failure"
textline "                     "
bitfld.long 0x00 1. " ENT_VAL     ,Read only: Entropy Valid" "0: Busy generation entropy,1: TRNG can be stopped and entropy is valid if read"
textline "                     "
bitfld.long 0x00 0. " HW_ERR      ,Read: Error status" "0: HW_ERR_0,1: error detected"
rgroup.long 0xF0++0x03
line.long 0x00 "VID1,Version ID Register (MS)"
hexmask.long.word 0x00 16.--31. 1. " IP_ID       ,Shows the IP ID"
textline "                     "
hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV     ,Shows the IP's Major revision of the TRNG"
textline "                     "
hexmask.long.byte 0x00 0.--7. 1. " MIN_REV     ,Shows the IP's Minor revision of the TRNG"
rgroup.long 0xF4++0x03
line.long 0x00 "VID2,Version ID Register (LS)"
hexmask.long.byte 0x00 24.--31. 1. " ERA         ,Shows the compile options for the TRNG"
textline "                     "
hexmask.long.byte 0x00 16.--23. 1. " INTG_OPT    ,Shows the integration options for the TRNG"
textline "                     "
hexmask.long.byte 0x00 8.--15. 1. " ECO_REV     ,Shows the IP's ECO revision of the TRNG"
textline "                     "
hexmask.long.byte 0x00 0.--7. 1. " CONFIG_OPT  ,Shows the IP's Configuaration options for the TRNG"
width 0x0B
tree.end
tree "USART"
tree "USART0"
base ad:0x40106000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART1"
base ad:0x40107000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART2"
base ad:0x40108000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART3"
base ad:0x40109000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART4"
base ad:0x40122000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART5"
base ad:0x40123000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART6"
base ad:0x40124000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree "USART7"
base ad:0x40125000
width 14.
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. " TXPOL         ,Transmit data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 22. " RXPOL         ,Receive data polarity" "0: STANDARD,1: INVERTED"
textline "                       "
bitfld.long 0x00 21. " OEPOL         ,Output Enable Polarity" "0: LOW,1: HIGH"
textline "                       "
bitfld.long 0x00 20. " OESEL         ,Output Enable Select" "0: STANDARD,1: RS_485"
textline "                       "
bitfld.long 0x00 19. " AUTOADDR      ,Automatic Address matching enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 18. " OETA          ,Output Enable Turnaround time enable for RS-485 operation" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 15. " LOOP          ,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
textline "                       "
bitfld.long 0x00 14. " SYNCMST       ,Synchronous mode Master select" "0: SLAVE,1: MASTER"
textline "                       "
bitfld.long 0x00 12. " CLKPOL        ,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: FALLING_EDGE,1: RISING_EDGE"
textline "                       "
bitfld.long 0x00 11. " SYNCEN        ,Selects synchronous or asynchronous operation" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE"
textline "                       "
bitfld.long 0x00 9. " CTSEN         ,CTS Enable" "0: No flow control,1: Flow control enabled"
textline "                       "
bitfld.long 0x00 8. " LINMODE       ,LIN break mode enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 7. " MODE32K       ,Selects standard or 32 kHz clocking mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 6. " STOPLEN       ,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
textline "                       "
bitfld.long 0x00 4.--5. " PARITYSEL     ,Selects what type of parity is used by the USART" "0: NO_PARITY,,2: EVEN_PARITY,3: ODD_PARITY"
textline "                       "
bitfld.long 0x00 2.--3. " DATALEN       ,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,"
textline "                       "
bitfld.long 0x00 0. " ENABLE        ,USART Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. " AUTOBAUD      ,Autobaud enable" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 9. " CLRCCONRX     ,Clear Continuous Clock" "0: NO_EFFECT,1: AUTO_CLEAR"
textline "                       "
bitfld.long 0x00 8. " CC            ,Continuous Clock generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock"
textline "                       "
bitfld.long 0x00 6. " TXDIS         ,Transmit Disable" "0: Not disabled,1: DISABLED"
textline "                       "
bitfld.long 0x00 2. " ADDRDET       ,Enable address detect mode" "0: DISABLED,1: ENABLED"
textline "                       "
bitfld.long 0x00 1. " TXBRKEN       ,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. " ABERR         ,Auto baud Error" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
rbitfld.long 0x00 10. " RXBRK         ,Received Break" "0,1"
textline "                       "
rbitfld.long 0x00 6. " TXDISSTAT     ,Transmitter Disabled Status flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
textline "                       "
rbitfld.long 0x00 4. " CTS           ,This bit reflects the current state of the CTS signal. regardless of the setting of the CTSEN bit in.." "0,1"
textline "                       "
rbitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle" "0,1"
textline "                       "
rbitfld.long 0x00 1. " RXIDLE        ,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. " ABERREN       ,When 1. enables an interrupt when an auto baud error occurs" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEEN     ,When 1. enables an interrupt when noise is detected" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERREN   ,When 1. enables an interrupt when a parity error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERREN     ,When 1. enables an interrupt when a framing error has been detected" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTEN       ,When 1. enables an interrupt when a received start bit has been detected" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKEN  ,When 1. enables an interrupt when a change of state has occurred in the detection of a received brea.." "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISEN       ,When 1. enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT fla.." "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSEN    ,When 1. enables an interrupt when there is a change in the state of the CTS input" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLEEN      ,When 1. enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. " ABERRCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISECLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRCLR  ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRCLR    ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 12. " STARTCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRKCLR ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISCLR      ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTSCLR   ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLECLR     ,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
hexmask.long.word 0x00 0.--15. 1. " BRGVAL        ,This value is used to divide the USART input clock to determine the baud rate. based on the input cl.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. " ABERRINT      ,Auto baud Error Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 15. " RXNOISEINT    ,Received Noise interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERRINT  ,Parity Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERRINT    ,Framing Error interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 12. " START         ,This bit is set when a start is detected on the receiver input" "0,1"
textline "                       "
bitfld.long 0x00 11. " DELTARXBRK    ,This bit is set when a change in the state of receiver break detection occurs" "0,1"
textline "                       "
bitfld.long 0x00 6. " TXDISINT      ,Transmitter Disabled Interrupt flag" "0,1"
textline "                       "
bitfld.long 0x00 5. " DELTACTS      ,This bit is set when a change in the state of the CTS input is detected" "0,1"
textline "                       "
bitfld.long 0x00 3. " TXIDLE        ,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. " OSRVAL        ,Oversample Selection Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS       ,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. " EMPTYRX       ,Empty command for the receive FIFO" "0,1"
textline "                       "
bitfld.long 0x00 16. " EMPTYTX       ,Empty command for the transmit FIFO" "0,1"
textline "                       "
bitfld.long 0x00 15. " WAKERX        ,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL i.."
textline "                       "
bitfld.long 0x00 14. " WAKETX        ,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the device form reduced power modes,1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL .."
textline "                       "
bitfld.long 0x00 13. " DMARX         ,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the FIFO is not empty"
textline "                       "
bitfld.long 0x00 12. " DMATX         ,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the FIFO is not full"
textline "                       "
rbitfld.long 0x00 4.--5. " SIZE          ,FIFO size configuration" "0,1,2,3"
textline "                       "
bitfld.long 0x00 1. " ENABLERX      ,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLETX      ,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. " RXLVL         ,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 8.--12. " TXLVL         ,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                       "
rbitfld.long 0x00 7. " RXFULL        ,Receive FIFO full" "0,1"
textline "                       "
rbitfld.long 0x00 6. " RXNOTEMPTY    ,Receive FIFO not empty" "0,1"
textline "                       "
rbitfld.long 0x00 5. " TXNOTFULL     ,Transmit FIFO not full" "0,1"
textline "                       "
rbitfld.long 0x00 4. " TXEMPTY       ,Transmit FIFO empty" "0,1"
textline "                       "
rbitfld.long 0x00 3. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. " RXLVL         ,Receive FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " TXLVL         ,Transmit FIFO level trigger point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 1. " RXLVLENA      ,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL fiel.."
textline "                       "
bitfld.long 0x00 0. " TXLVLENA      ,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO level trigger,1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL fie.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TX.." "0: No interrupt will be generated based on the RX FIFO level,1: If RXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the when the RX FIFO l.."
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the T.." "0: No interrupt will be generated based on the TX FIFO level,1: If TXLVLENA in the FIFOTRIG register = 1. an interrupt will be generated when the TX FIFO level decr.."
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Determines whether an interrupt occurs when a receive error occurs. based on the RXERR flag in the F.." "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive error occurs"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Determines whether an interrupt occurs when a transmit error occurs. based on the TXERR flag in the .." "0: No interrupt will be generated for a transmit error,1: An interrupt will be generated when a transmit error occurs"
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. " RXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. " PERINT        ,Peripheral interrupt" "0,1"
textline "                       "
bitfld.long 0x00 3. " RXLVL         ,Receive FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 2. " TXLVL         ,Transmit FIFO level interrupt" "0,1"
textline "                       "
bitfld.long 0x00 1. " RXERR         ,RX FIFO error" "0,1"
textline "                       "
bitfld.long 0x00 0. " TXERR         ,TX FIFO error" "0,1"
group.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. " TXDATA        ,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. " RXNOISE       ,Received Noise flag" "0,1"
textline "                       "
bitfld.long 0x00 14. " PARITYERR     ,Parity Error status flag" "0,1"
textline "                       "
bitfld.long 0x00 13. " FRAMERR       ,Framing Error status flag" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--8. 1. " RXDATA        ,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. " FIFOSIZE      ,the fifo size is equal to the template parameter _fifo_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. " ID            ,Module identifier for the selected function"
textline "                       "
bitfld.long 0x00 12.--15. " MAJOR_REV     ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
bitfld.long 0x00 8.--11. " MINOR_REV     ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.byte 0x00 0.--7. 1. " APERTURE      ,Aperture: encoded as (aperture size/4K) -1. so 0x00 means a 4K aperture"
width 0x0B
tree.end
tree.end
tree "USBHSD"
base ad:0x40144000
width 14.
group.long 0x00++0x03
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register"
bitfld.long 0x00 29.--31. " PHY_TEST_MODE  ,This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification" "0,1,2,3,4,5,6,7"
textline "                       "
rbitfld.long 0x00 28. " VBUS_DEBOUNCED ,This bit indicates if VBUS is detected or not" "0,1"
textline "                       "
bitfld.long 0x00 26. " DRES_C         ,Device status - reset change" "0,1"
textline "                       "
bitfld.long 0x00 25. " DSUS_C         ,Device status - suspend change" "0,1"
textline "                       "
bitfld.long 0x00 24. " DCON_C         ,Device status - connect change" "0,1"
textline "                       "
rbitfld.long 0x00 22.--23. " SPEED          ,This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high.." "0,1,2,3"
textline "                       "
rbitfld.long 0x00 20. " LPM_REWP       ,LPM Remote Wake-up Enabled by USB host" "0,1"
textline "                       "
bitfld.long 0x00 19. " LPM_SUS        ,Device status - LPM Suspend" "0,1"
textline "                       "
bitfld.long 0x00 17. " DSUS           ,Device status - suspend" "0,1"
textline "                       "
bitfld.long 0x00 16. " DCON           ,Device status - connect" "0,1"
textline "                       "
bitfld.long 0x00 15. " INTONNAK_CI    ,Interrupt on NAK for control IN EP:" "0,1"
textline "                       "
bitfld.long 0x00 14. " INTONNAK_CO    ,Interrupt on NAK for control OUT EP:" "0,1"
textline "                       "
bitfld.long 0x00 13. " INTONNAK_AI    ,Interrupt on NAK for interrupt and bulk IN EP:" "0,1"
textline "                       "
bitfld.long 0x00 12. " INTONNAK_AO    ,Interrupt on NAK for interrupt and bulk OUT EP:" "0,1"
textline "                       "
bitfld.long 0x00 11. " LPM_SUP        ,LPM Supported:" "0,1"
textline "                       "
bitfld.long 0x00 10. " FORCE_VBUS     ,If this bit is set to 1. the VBUS voltage indicators from the PHY are overruled" "0,1"
textline "                       "
bitfld.long 0x00 9. " FORCE_NEEDCLK  ,Forces the NEEDCLK output to always be on:" "0,1"
textline "                       "
bitfld.long 0x00 8. " SETUP          ,SETUP token received" "0,1"
textline "                       "
bitfld.long 0x00 7. " DEV_EN         ,USB device enable" "0,1"
textline "                       "
hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR       ,USB device address"
rgroup.long 0x04++0x03
line.long 0x00 "INFO,USB Info register"
hexmask.long.byte 0x00 24.--31. 1. " Majrev         ,Major revision"
textline "                       "
hexmask.long.byte 0x00 16.--23. 1. " Minrev         ,Minor revision"
textline "                       "
bitfld.long 0x00 11.--14. " ERR_CODE       ,The error code which last occurred:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
hexmask.long.word 0x00 0.--10. 1. " FRAME_NR       ,Frame number"
group.long 0x08++0x03
line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address"
hexmask.long.word 0x00 20.--31. 1. " EP_LIST_FIXED  ,Fixed portion of USB EP Command/Status List address"
textline "                       "
hexmask.long.word 0x00 8.--19. 1. " EP_LIST_PRG    ,Programmable portion of the USB EP Command/Status List address"
group.long 0x0C++0x03
line.long 0x00 "DATABUFSTART,USB Data buffer start address"
hexmask.long.word 0x00 18.--31. 1. " DA_BUF         ,Programmable portion of the data buffer start address"
textline "                       "
hexmask.long.tbyte 0x00 0.--17. 1. " DA_BUF_FIXED   ,The fixed portion of the data buffer start address"
group.long 0x10++0x03
line.long 0x00 "LPM,USB Link Power Management register"
bitfld.long 0x00 8. " DATA_PENDING   ,As long as this bit is set to one and LPM supported bit is set to one. HW will return a NYET handsha.." "0,1"
textline "                       "
bitfld.long 0x00 4.--7. " HIRD_SW        ,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                       "
rbitfld.long 0x00 0.--3. " HIRD_HW        ,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "EPSKIP,USB Endpoint skip"
hexmask.long.word 0x00 0.--11. 1. " SKIP           ,Endpoint skip: Writing 1 to one of these bits. will indicate to HW that it must deactivate the buffe.."
group.long 0x18++0x03
line.long 0x00 "EPINUSE,USB Endpoint Buffer in use"
hexmask.long.word 0x00 2.--11. 1. " BUF            ,Buffer in use: This register has one bit per physical endpoint"
group.long 0x1C++0x03
line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register"
hexmask.long.word 0x00 2.--11. 1. " BUF_SB         ,Buffer usage: This register has one bit per physical endpoint"
group.long 0x20++0x03
line.long 0x00 "INTSTAT,USB interrupt status register"
bitfld.long 0x00 31. " DEV_INT        ,Device status interrupt" "0,1"
textline "                       "
bitfld.long 0x00 30. " FRAME_INT      ,Frame interrupt" "0,1"
textline "                       "
bitfld.long 0x00 11. " EP5IN          ,Interrupt status register bit for the EP5 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 10. " EP5OUT         ,Interrupt status register bit for the EP5 OUT direction" "0,1"
textline "                       "
bitfld.long 0x00 9. " EP4IN          ,Interrupt status register bit for the EP4 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 8. " EP4OUT         ,Interrupt status register bit for the EP4 OUT direction" "0,1"
textline "                       "
bitfld.long 0x00 7. " EP3IN          ,Interrupt status register bit for the EP3 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 6. " EP3OUT         ,Interrupt status register bit for the EP3 OUT direction" "0,1"
textline "                       "
bitfld.long 0x00 5. " EP2IN          ,Interrupt status register bit for the EP2 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 4. " EP2OUT         ,Interrupt status register bit for the EP2 OUT direction" "0,1"
textline "                       "
bitfld.long 0x00 3. " EP1IN          ,Interrupt status register bit for the EP1 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 2. " EP1OUT         ,Interrupt status register bit for the EP1 OUT direction" "0,1"
textline "                       "
bitfld.long 0x00 1. " EP0IN          ,Interrupt status register bit for the Control EP0 IN direction" "0,1"
textline "                       "
bitfld.long 0x00 0. " EP0OUT         ,Interrupt status register bit for the Control EP0 OUT direction" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTEN,USB interrupt enable register"
bitfld.long 0x00 31. " DEV_INT_EN     ,If this bit is set and the corresponding USB interrupt status bit is set. a HW interrupt is generate.." "0,1"
textline "                       "
bitfld.long 0x00 30. " FRAME_INT_EN   ,If this bit is set and the corresponding USB interrupt status bit is set. a HW interrupt is generate.." "0,1"
textline "                       "
hexmask.long.word 0x00 0.--11. 1. " EP_INT_EN      ,If this bit is set and the corresponding USB interrupt status bit is set. a HW interrupt is generate.."
group.long 0x28++0x03
line.long 0x00 "INTSETSTAT,USB set interrupt status register"
bitfld.long 0x00 31. " DEV_SET_INT    ,If software writes a one to one of these bits. the corresponding USB interrupt status bit is set" "0,1"
textline "                       "
bitfld.long 0x00 30. " FRAME_SET_INT  ,If software writes a one to one of these bits. the corresponding USB interrupt status bit is set" "0,1"
textline "                       "
hexmask.long.word 0x00 0.--11. 1. " EP_SET_INT     ,If software writes a one to one of these bits. the corresponding USB interrupt status bit is set"
rgroup.long 0x34++0x03
line.long 0x00 "EPTOGGLE,USB Endpoint toggle register"
hexmask.long 0x00 0.--29. 1. " TOGGLE         ,Endpoint data toggle: This field indicates the current value of the data toggle for the correspondin.."
width 0x0B
tree.end
tree "USBHSDCD"
base ad:0x4013B800
width 17.
group.long 0x00++0x03
line.long 0x00 "CONTROL,Control register"
bitfld.long 0x00 25. " SR              ,Software Reset" "0: Do not perform a software reset,1: Perform a software reset"
textline "                          "
bitfld.long 0x00 24. " START           ,Start Change Detection Sequence" "0: Do not start the sequence,1: Initiate the charger detection sequence"
textline "                          "
bitfld.long 0x00 17. " BC12            ,BC12" "0: Compatible with BC1.1 (default),1: Compatible with BC1.2"
textline "                          "
bitfld.long 0x00 16. " IE              ,Interrupt Enable" "0: Disable interrupts to the system,1: Enable interrupts to the system"
textline "                          "
rbitfld.long 0x00 8. " IF              ,Interrupt Flag" "0: No interrupt is pending,1: An interrupt is pending"
textline "                          "
bitfld.long 0x00 0. " IACK            ,Interrupt Acknowledge" "0: Do not clear the interrupt,1: Clear the IF bit (interrupt flag)"
group.long 0x04++0x03
line.long 0x00 "CLOCK,Clock register"
hexmask.long.word 0x00 2.--11. 1. " CLOCK_SPEED     ,Numerical Value of Clock Speed in Binary"
textline "                          "
bitfld.long 0x00 0. " CLOCK_UNIT      ,Unit of Measurement Encoding for Clock Speed" "0: kHz Speed (between 1 kHz and 1023 kHz),1: MHz Speed (between 1 MHz and 1023 MHz)"
rgroup.long 0x08++0x03
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 22. " ACTIVE          ,Active Status Indicator" "0: The sequence is not running,1: The sequence is running"
textline "                          "
bitfld.long 0x00 21. " TO              ,Timeout Flag" "0: The detection sequence has not been running for over 1 s,1: It has been over 1 s since the data pin contact was detected and debounced"
textline "                          "
bitfld.long 0x00 20. " ERR             ,Error Flag" "0: No sequence errors,1: Error in the detection sequence"
textline "                          "
bitfld.long 0x00 18.--19. " SEQ_STAT        ,Charger Detection Sequence Status" "0: The module is either not enabled. or the module is enabled but the data pins have not yet been detec..,1: Data pin contact detection is complete,2: Charging port detection is complete,3: Charger type detection is complete"
textline "                          "
bitfld.long 0x00 16.--17. " SEQ_RES         ,Charger Detection Sequence Results" "0: No results to report,1: Attached to an SDP,2: Attached to a charging port,3: Attached to a DCP"
group.long 0x0C++0x03
line.long 0x00 "SIGNAL_OVERRIDE,Signal Override Register"
bitfld.long 0x00 0.--1. " PS              ,Phase Selection" "0: No overrides,,2: Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin,"
group.long 0x10++0x03
line.long 0x00 "TIMER0,TIMER0 register"
hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT       ,Sequence Initiation Time"
textline "                          "
hexmask.long.word 0x00 0.--11. 1. " TUNITCON        ,Unit Connection Timer Elapse (in ms)"
group.long 0x14++0x03
line.long 0x00 "TIMER1,TIMER1 register"
hexmask.long.word 0x00 16.--25. 1. " TDCD_DBNC       ,Time Period to Debounce D+ Signal"
textline "                          "
hexmask.long.word 0x00 0.--9. 1. " TVDPSRC_ON      ,Time Period Comparator Enabled"
group.long 0x18++0x03
line.long 0x00 "TIMER2_BC11,TIMER2_BC11 register"
hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON     ,Time Period Before Enabling D+ Pullup"
textline "                          "
bitfld.long 0x00 0.--3. " CHECK_DM        ,Time Before Check of D- Line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "TIMER2_BC12,TIMER2_BC12 register"
hexmask.long.word 0x00 16.--25. 1. " TWAIT_AFTER_PRD ,TWAIT_AFTER_PRD"
textline "                          "
hexmask.long.word 0x00 0.--9. 1. " TVDMSRC_ON      ,TVDMSRC_ON"
width 0x0B
tree.end
tree "USBHSH"
base ad:0x40145000
width 18.
rgroup.long 0x00++0x03
line.long 0x00 "CAPLENGTH_CHIPID,This register contains the offset value towards the start of the operational register space and the .."
hexmask.long.word 0x00 16.--31. 1. " CHIPID      ,Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] .."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH   ,Capability Length: This is used as an offset"
rgroup.long 0x04++0x03
line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters"
bitfld.long 0x00 16. " P_INDICATOR ,This bit indicates whether the ports support port indicator control" "0,1"
textline "                           "
bitfld.long 0x00 4. " PPC         ,This field indicates whether the host controller implementation includes port power control" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " N_PORTS     ,This register specifies the number of physical downstream ports implemented on this host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x08++0x03
line.long 0x00 "HCCPARAMS,Host Controller Capability Parameters"
bitfld.long 0x00 17. " LPMC        ,Link Power Management Capability" "0,1"
group.long 0x0C++0x03
line.long 0x00 "FLADJ_FRINDEX,Frame Length Adjustment"
hexmask.long.word 0x00 16.--29. 1. " FRINDEX     ,Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet"
textline "                           "
bitfld.long 0x00 0.--5. " FLADJ       ,Frame Length Timing Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "ATLPTD,Memory base address where ATL PTD0 is stored"
hexmask.long.tbyte 0x00 9.--31. 1. " ATL_BASE    ,Base address to be used by the hardware to find the start of the ATL list"
textline "                           "
bitfld.long 0x00 4.--8. " ATL_CUR     ,This indicates the current PTD that is used by the hardware when it is processing the ATL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "ISOPTD,Memory base address where ISO PTD0 is stored"
hexmask.long.tbyte 0x00 10.--31. 1. " ISO_BASE    ,Base address to be used by the hardware to find the start of the ISO list"
textline "                           "
bitfld.long 0x00 5.--9. " ISO_FIRST   ,This indicates the first PTD that is used by the hardware when it is processing the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "INTPTD,Memory base address where INT PTD0 is stored"
hexmask.long.tbyte 0x00 10.--31. 1. " INT_BASE    ,Base address to be used by the hardware to find the start of the INT list"
textline "                           "
bitfld.long 0x00 5.--9. " INT_FIRST   ,This indicates the first PTD that is used by the hardware when it is processing the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "DATAPAYLOAD,Memory base address that indicates the start of the data payload buffers"
hexmask.long.word 0x00 16.--31. 1. " DAT_BASE    ,Base address to be used by the hardware to find the start of the data payload section"
group.long 0x20++0x03
line.long 0x00 "USBCMD,USB Command register"
bitfld.long 0x00 24.--27. " HIRD        ,Host-Initiated Resume Duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 10. " INT_EN      ,INT List enabled" "0,1"
textline "                           "
bitfld.long 0x00 9. " ISO_EN      ,ISO List enabled" "0,1"
textline "                           "
bitfld.long 0x00 8. " ATL_EN      ,ATL List enabled" "0,1"
textline "                           "
bitfld.long 0x00 7. " LHCR        ,Light Host Controller Reset: This bit allows the driver software to reset the host controller withou.." "0,1"
textline "                           "
bitfld.long 0x00 2.--3. " FLS         ,Frame List Size: This field specifies the size of the frame list" "0,1,2,3"
textline "                           "
bitfld.long 0x00 1. " HCRESET     ,Host Controller Reset: This control bit is used by the software to reset the host controller" "0,1"
textline "                           "
bitfld.long 0x00 0. " RS          ,Run/Stop: 1b = Run" "0,1"
group.long 0x24++0x03
line.long 0x00 "USBSTS,USB Interrupt Status register"
bitfld.long 0x00 19. " SOF_IRQ     ,SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus. this bit is set" "0,1"
textline "                           "
bitfld.long 0x00 18. " INT_IRQ     ,INT IRQ: Indicates that an INT PTD (with I-bit set) was completed" "0,1"
textline "                           "
bitfld.long 0x00 17. " ISO_IRQ     ,ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed" "0,1"
textline "                           "
bitfld.long 0x00 16. " ATL_IRQ     ,ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed" "0,1"
textline "                           "
bitfld.long 0x00 3. " FLR         ,Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls ov.." "0,1"
textline "                           "
bitfld.long 0x00 2. " PCD         ,Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit tran.." "0,1"
group.long 0x28++0x03
line.long 0x00 "USBINTR,USB Interrupt Enable register"
bitfld.long 0x00 19. " SOF_E       ,SOF Interrupt Enable bit: 1: enable 0: disable" "0,1"
textline "                           "
bitfld.long 0x00 18. " INT_IRQ_E   ,INT IRQ Enable bit: 1: enable 0: disable" "0,1"
textline "                           "
bitfld.long 0x00 17. " ISO_IRQ_E   ,ISO IRQ Enable bit: 1: enable 0: disable" "0,1"
textline "                           "
bitfld.long 0x00 16. " ATL_IRQ_E   ,ATL IRQ Enable bit: 1: enable 0: disable" "0,1"
textline "                           "
bitfld.long 0x00 3. " FLRE        ,Frame List Rollover Interrupt Enable: 1: enable 0: disable" "0,1"
textline "                           "
bitfld.long 0x00 2. " PCDE        ,Port Change Detect Interrupt Enable: 1: enable 0: disable" "0,1"
group.long 0x2C++0x03
line.long 0x00 "PORTSC1,Port Status and Control register"
hexmask.long.byte 0x00 25.--31. 1. " DEV_ADD     ,Device Address for LPM tokens"
textline "                           "
bitfld.long 0x00 23.--24. " SUS_STAT    ,These two bits are used by software to determine whether the most recent L1 suspend request was succ.." "0,1,2,3"
textline "                           "
bitfld.long 0x00 22. " WOO         ,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurren.." "0,1"
textline "                           "
bitfld.long 0x00 20.--21. " PSPD        ,Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved" "0,1,2,3"
textline "                           "
bitfld.long 0x00 16.--19. " PTC         ,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicat.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 14.--15. " PIC         ,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS.." "0,1,2,3"
textline "                           "
bitfld.long 0x00 12. " PP          ,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the.." "0,1"
textline "                           "
rbitfld.long 0x00 10.--11. " LS          ,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signa.." "0,1,2,3"
textline "                           "
bitfld.long 0x00 9. " SUS_L1      ,Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-z.." "0,1"
textline "                           "
bitfld.long 0x00 8. " PR          ,Port Reset: Logic 1 means the port is in the reset state" "0,1"
textline "                           "
bitfld.long 0x00 7. " SUSP        ,Suspend: Logic 1 means port is in the suspend state" "0,1"
textline "                           "
bitfld.long 0x00 6. " FPR         ,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port" "0,1"
textline "                           "
bitfld.long 0x00 5. " OCC         ,Over-current change: Logic 1 means that the value of OCA has changed" "0,1"
textline "                           "
bitfld.long 0x00 4. " OCA         ,Over-current active: Logic 1 means that this port has an over-current condition" "0,1"
textline "                           "
bitfld.long 0x00 3. " PEDC        ,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed" "0,1"
textline "                           "
bitfld.long 0x00 2. " PED         ,Port Enabled/Disabled" "0,1"
textline "                           "
bitfld.long 0x00 1. " CSC         ,Connect Status Change: Logic 1 means that the value of CCS has changed" "0,1"
textline "                           "
bitfld.long 0x00 0. " CCS         ,Current Connect Status: Logic 1 indicates a device is present on the port" "0,1"
group.long 0x30++0x03
line.long 0x00 "ATLPTDD,Done map for each ATL PTD"
hexmask.long 0x00 0.--31. 1. " ATL_DONE    ,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is compl.."
group.long 0x34++0x03
line.long 0x00 "ATLPTDS,Skip map for each ATL PTD"
hexmask.long 0x00 0.--31. 1. " ATL_SKIP    ,When a bit in the PTD Skip Map is set to logic 1. the corresponding PTD will be skipped. independent.."
group.long 0x38++0x03
line.long 0x00 "ISOPTDD,Done map for each ISO PTD"
hexmask.long 0x00 0.--31. 1. " ISO_DONE    ,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is compl.."
group.long 0x3C++0x03
line.long 0x00 "ISOPTDS,Skip map for each ISO PTD"
hexmask.long 0x00 0.--31. 1. " ISO_SKIP    ,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is compl.."
group.long 0x40++0x03
line.long 0x00 "INTPTDD,Done map for each INT PTD"
hexmask.long 0x00 0.--31. 1. " INT_DONE    ,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is compl.."
group.long 0x44++0x03
line.long 0x00 "INTPTDS,Skip map for each INT PTD"
hexmask.long 0x00 0.--31. 1. " INT_SKIP    ,When a bit in the PTD Skip Map is set to logic 1. the corresponding PTD will be skipped. independent.."
group.long 0x48++0x03
line.long 0x00 "LASTPTD,Marks the last PTD in the list for ISO. INT and ATL"
bitfld.long 0x00 16.--20. " INT_LAST    ,This indicates the last PTD in the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 8.--12. " ISO_LAST    ,This indicates the last PTD in the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 0.--4. " ATL_LAST    ,If hardware has reached this PTD and the J bit is not set. it will go to PTD0 as the next PTD to be .." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x50++0x03
line.long 0x00 "PORTMODE,Controls the port if it is attached to the host block or the device block"
bitfld.long 0x00 16. " DEV_ENABLE  ,If this bit is set to one. the port will behave as a USB device" "0,1"
width 0x0B
tree.end
tree "USBPHY"
base ad:0x4013B000
width 27.
group.long 0x00++0x03
line.long 0x00 "PWD,USB PHY Power-Down Register"
bitfld.long 0x00 20. " RXPWDRX                       ,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is en.." "0: Normal operation,1: Power-down the entire USB PHY receiver block except for the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 19. " RXPWDDIFF                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed differential receive"
textline "                                    "
bitfld.long 0x00 18. " RXPWD1PT1                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 17. " RXPWDENV                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed receiver envelope detector (squelch signal)"
textline "                                    "
bitfld.long 0x00 12. " TXPWDV2I                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY transmit V-to-I converter and the current mirror"
textline "                                    "
bitfld.long 0x00 11. " TXPWDIBIAS                    ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY current bias block for the transmitter"
textline "                                    "
bitfld.long 0x00 10. " TXPWDFS                       ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x04++0x03
line.long 0x00 "PWD_SET,USB PHY Power-Down Register"
bitfld.long 0x00 20. " RXPWDRX                       ,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is en.." "0: Normal operation,1: Power-down the entire USB PHY receiver block except for the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 19. " RXPWDDIFF                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed differential receive"
textline "                                    "
bitfld.long 0x00 18. " RXPWD1PT1                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 17. " RXPWDENV                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed receiver envelope detector (squelch signal)"
textline "                                    "
bitfld.long 0x00 12. " TXPWDV2I                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY transmit V-to-I converter and the current mirror"
textline "                                    "
bitfld.long 0x00 11. " TXPWDIBIAS                    ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY current bias block for the transmitter"
textline "                                    "
bitfld.long 0x00 10. " TXPWDFS                       ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x08++0x03
line.long 0x00 "PWD_CLR,USB PHY Power-Down Register"
bitfld.long 0x00 20. " RXPWDRX                       ,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is en.." "0: Normal operation,1: Power-down the entire USB PHY receiver block except for the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 19. " RXPWDDIFF                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed differential receive"
textline "                                    "
bitfld.long 0x00 18. " RXPWD1PT1                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 17. " RXPWDENV                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed receiver envelope detector (squelch signal)"
textline "                                    "
bitfld.long 0x00 12. " TXPWDV2I                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY transmit V-to-I converter and the current mirror"
textline "                                    "
bitfld.long 0x00 11. " TXPWDIBIAS                    ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY current bias block for the transmitter"
textline "                                    "
bitfld.long 0x00 10. " TXPWDFS                       ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x0C++0x03
line.long 0x00 "PWD_TOG,USB PHY Power-Down Register"
bitfld.long 0x00 20. " RXPWDRX                       ,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is en.." "0: Normal operation,1: Power-down the entire USB PHY receiver block except for the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 19. " RXPWDDIFF                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed differential receive"
textline "                                    "
bitfld.long 0x00 18. " RXPWD1PT1                     ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 17. " RXPWDENV                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB high-speed receiver envelope detector (squelch signal)"
textline "                                    "
bitfld.long 0x00 12. " TXPWDV2I                      ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY transmit V-to-I converter and the current mirror"
textline "                                    "
bitfld.long 0x00 11. " TXPWDIBIAS                    ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB PHY current bias block for the transmitter"
textline "                                    "
bitfld.long 0x00 10. " TXPWDFS                       ,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of .." "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x10++0x03
line.long 0x00 "TX,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. " TXENCAL45DP                   ,Enable resistance calibration on DP" "0,1"
textline "                                    "
bitfld.long 0x00 16.--19. " TXCAL45DP                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 13. " TXENCAL45DN                   ,Enable resistance calibration on DN" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TXCAL45DM                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 0.--3. " D_CAL                         ,Decode to trim the nominal 17" "0: Maximum current. approximately 19% above nominal,,,,,,,7: D_CAL_7,,,,,,,,15: Minimum current. approximately 19% below nominal"
group.long 0x14++0x03
line.long 0x00 "TX_SET,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. " TXENCAL45DP                   ,Enable resistance calibration on DP" "0,1"
textline "                                    "
bitfld.long 0x00 16.--19. " TXCAL45DP                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 13. " TXENCAL45DN                   ,Enable resistance calibration on DN" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TXCAL45DM                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 0.--3. " D_CAL                         ,Decode to trim the nominal 17" "0: Maximum current. approximately 19% above nominal,,,,,,,7: D_CAL_7,,,,,,,,15: Minimum current. approximately 19% below nominal"
group.long 0x18++0x03
line.long 0x00 "TX_CLR,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. " TXENCAL45DP                   ,Enable resistance calibration on DP" "0,1"
textline "                                    "
bitfld.long 0x00 16.--19. " TXCAL45DP                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 13. " TXENCAL45DN                   ,Enable resistance calibration on DN" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TXCAL45DM                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 0.--3. " D_CAL                         ,Decode to trim the nominal 17" "0: Maximum current. approximately 19% above nominal,,,,,,,7: D_CAL_7,,,,,,,,15: Minimum current. approximately 19% below nominal"
group.long 0x1C++0x03
line.long 0x00 "TX_TOG,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. " TXENCAL45DP                   ,Enable resistance calibration on DP" "0,1"
textline "                                    "
bitfld.long 0x00 16.--19. " TXCAL45DP                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 13. " TXENCAL45DN                   ,Enable resistance calibration on DN" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TXCAL45DM                     ,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 0.--3. " D_CAL                         ,Decode to trim the nominal 17" "0: Maximum current. approximately 19% above nominal,,,,,,,7: D_CAL_7,,,,,,,,15: Minimum current. approximately 19% below nominal"
group.long 0x20++0x03
line.long 0x00 "RX,USB PHY Receiver Control Register"
bitfld.long 0x00 22. " RXDBYPASS                     ,This test mode is intended for lab use only. replace FS differential receiver with DP single ended r.." "0: Normal operation,1: Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 4.--6. " DISCONADJ                     ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,,,,"
textline "                                    "
bitfld.long 0x00 0.--2. " ENVADJ                        ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,,,,"
group.long 0x24++0x03
line.long 0x00 "RX_SET,USB PHY Receiver Control Register"
bitfld.long 0x00 22. " RXDBYPASS                     ,This test mode is intended for lab use only. replace FS differential receiver with DP single ended r.." "0: Normal operation,1: Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 4.--6. " DISCONADJ                     ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,,,,"
textline "                                    "
bitfld.long 0x00 0.--2. " ENVADJ                        ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,,,,"
group.long 0x28++0x03
line.long 0x00 "RX_CLR,USB PHY Receiver Control Register"
bitfld.long 0x00 22. " RXDBYPASS                     ,This test mode is intended for lab use only. replace FS differential receiver with DP single ended r.." "0: Normal operation,1: Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 4.--6. " DISCONADJ                     ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,,,,"
textline "                                    "
bitfld.long 0x00 0.--2. " ENVADJ                        ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,,,,"
group.long 0x2C++0x03
line.long 0x00 "RX_TOG,USB PHY Receiver Control Register"
bitfld.long 0x00 22. " RXDBYPASS                     ,This test mode is intended for lab use only. replace FS differential receiver with DP single ended r.." "0: Normal operation,1: Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver"
textline "                                    "
bitfld.long 0x00 4.--6. " DISCONADJ                     ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,,,,"
textline "                                    "
bitfld.long 0x00 0.--2. " ENVADJ                        ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,,,,"
group.long 0x30++0x03
line.long 0x00 "CTRL,USB PHY General Control Register"
bitfld.long 0x00 31. " SFTRST                        ,Writing a 1 to this bit will soft-reset the PWD. TX. RX. and CTRL registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " CLKGATE                       ,Gate UTMI Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " UTMI_SUSPENDM                 ,Used by the PHY to indicate a powered-down state" "0,1"
textline "                                    "
bitfld.long 0x00 28. " HOST_FORCE_LS_SE0             ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
textline "                                    "
bitfld.long 0x00 24. " FSDLL_RST_EN                  ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
textline "                                    "
bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD             ,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is.." "0,1"
textline "                                    "
bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE             ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
textline "                                    "
bitfld.long 0x00 18. " AUTORESUME_EN                 ,Enable the auto resume feature. when set. HW will use 32KHz clock to send Resume to respond to the d.." "0,1"
textline "                                    "
bitfld.long 0x00 15. " ENUTMILEVEL3                  ,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 14. " ENUTMILEVEL2                  ,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 12. " DEVPLUGIN_IRQ                 ,Indicates that the device is connected" "0,1"
textline "                                    "
bitfld.long 0x00 4. " ENDEVPLUGINDET                ,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 20.." "0: Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default),1: Enables 200kohm pullup resistors on USB_DP and USB_DM pins"
textline "                                    "
bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ          ,Indicates that the device has disconnected in High-Speed mode" "0,1"
textline "                                    "
bitfld.long 0x00 1. " ENHOSTDISCONDETECT            ,For host mode. enables high-speed disconnect detector" "0,1"
group.long 0x34++0x03
line.long 0x00 "CTRL_SET,USB PHY General Control Register"
bitfld.long 0x00 31. " SFTRST                        ,Writing a 1 to this bit will soft-reset the PWD. TX. RX. and CTRL registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " CLKGATE                       ,Gate UTMI Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " UTMI_SUSPENDM                 ,Used by the PHY to indicate a powered-down state" "0,1"
textline "                                    "
bitfld.long 0x00 28. " HOST_FORCE_LS_SE0             ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
textline "                                    "
bitfld.long 0x00 24. " FSDLL_RST_EN                  ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
textline "                                    "
bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD             ,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is.." "0,1"
textline "                                    "
bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE             ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
textline "                                    "
bitfld.long 0x00 18. " AUTORESUME_EN                 ,Enable the auto resume feature. when set. HW will use 32KHz clock to send Resume to respond to the d.." "0,1"
textline "                                    "
bitfld.long 0x00 15. " ENUTMILEVEL3                  ,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 14. " ENUTMILEVEL2                  ,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 12. " DEVPLUGIN_IRQ                 ,Indicates that the device is connected" "0,1"
textline "                                    "
bitfld.long 0x00 4. " ENDEVPLUGINDET                ,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 20.." "0: Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default),1: Enables 200kohm pullup resistors on USB_DP and USB_DM pins"
textline "                                    "
bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ          ,Indicates that the device has disconnected in High-Speed mode" "0,1"
textline "                                    "
bitfld.long 0x00 1. " ENHOSTDISCONDETECT            ,For host mode. enables high-speed disconnect detector" "0,1"
group.long 0x38++0x03
line.long 0x00 "CTRL_CLR,USB PHY General Control Register"
bitfld.long 0x00 31. " SFTRST                        ,Writing a 1 to this bit will soft-reset the PWD. TX. RX. and CTRL registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " CLKGATE                       ,Gate UTMI Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " UTMI_SUSPENDM                 ,Used by the PHY to indicate a powered-down state" "0,1"
textline "                                    "
bitfld.long 0x00 28. " HOST_FORCE_LS_SE0             ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
textline "                                    "
bitfld.long 0x00 24. " FSDLL_RST_EN                  ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
textline "                                    "
bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD             ,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is.." "0,1"
textline "                                    "
bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE             ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
textline "                                    "
bitfld.long 0x00 18. " AUTORESUME_EN                 ,Enable the auto resume feature. when set. HW will use 32KHz clock to send Resume to respond to the d.." "0,1"
textline "                                    "
bitfld.long 0x00 15. " ENUTMILEVEL3                  ,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 14. " ENUTMILEVEL2                  ,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 12. " DEVPLUGIN_IRQ                 ,Indicates that the device is connected" "0,1"
textline "                                    "
bitfld.long 0x00 4. " ENDEVPLUGINDET                ,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 20.." "0: Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default),1: Enables 200kohm pullup resistors on USB_DP and USB_DM pins"
textline "                                    "
bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ          ,Indicates that the device has disconnected in High-Speed mode" "0,1"
textline "                                    "
bitfld.long 0x00 1. " ENHOSTDISCONDETECT            ,For host mode. enables high-speed disconnect detector" "0,1"
group.long 0x3C++0x03
line.long 0x00 "CTRL_TOG,USB PHY General Control Register"
bitfld.long 0x00 31. " SFTRST                        ,Writing a 1 to this bit will soft-reset the PWD. TX. RX. and CTRL registers" "0,1"
textline "                                    "
bitfld.long 0x00 30. " CLKGATE                       ,Gate UTMI Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " UTMI_SUSPENDM                 ,Used by the PHY to indicate a powered-down state" "0,1"
textline "                                    "
bitfld.long 0x00 28. " HOST_FORCE_LS_SE0             ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
textline "                                    "
bitfld.long 0x00 24. " FSDLL_RST_EN                  ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
textline "                                    "
bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD             ,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is.." "0,1"
textline "                                    "
bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE             ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
textline "                                    "
bitfld.long 0x00 18. " AUTORESUME_EN                 ,Enable the auto resume feature. when set. HW will use 32KHz clock to send Resume to respond to the d.." "0,1"
textline "                                    "
bitfld.long 0x00 15. " ENUTMILEVEL3                  ,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 14. " ENUTMILEVEL2                  ,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
textline "                                    "
bitfld.long 0x00 12. " DEVPLUGIN_IRQ                 ,Indicates that the device is connected" "0,1"
textline "                                    "
bitfld.long 0x00 4. " ENDEVPLUGINDET                ,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 20.." "0: Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default),1: Enables 200kohm pullup resistors on USB_DP and USB_DM pins"
textline "                                    "
bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ          ,Indicates that the device has disconnected in High-Speed mode" "0,1"
textline "                                    "
bitfld.long 0x00 1. " ENHOSTDISCONDETECT            ,For host mode. enables high-speed disconnect detector" "0,1"
group.long 0x40++0x03
line.long 0x00 "STATUS,USB PHY Status Register"
bitfld.long 0x00 10. " RESUME_STATUS                 ,Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt" "0,1"
textline "                                    "
bitfld.long 0x00 6. " DEVPLUGIN_STATUS              ,Status indicator for non-standard resistive plugged-in detection Indicates that the device has been .." "0: No attachment to a USB host is detected,1: Cable attachment to a USB host is detected"
textline "                                    "
bitfld.long 0x00 3. " HOSTDISCONDETECT_STATUS       ,Indicates at the local host (downstream) port that the remote device has disconnected while in High-.." "0: USB cable disconnect has not been detected at the local host,1: USB cable disconnect has been detected at the local host"
group.long 0x50++0x03
line.long 0x00 "DEBUG0,USB PHY Debug Register 0"
bitfld.long 0x00 30. " CLKGATE                       ,Gate Test Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " HOST_RESUME_DEBUG             ,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
textline "                                    "
bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH            ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24. " ENSQUELCHRESET                ,Set bit to allow squelch to reset high-speed receive" "0,1"
textline "                                    "
bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT             ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 12. " ENTX2RXCOUNT                  ,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TX2RXCOUNT                    ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--5. " ENHSTPULLDOWN                 ,This bit field selects host pulldown overdrive mode" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 2.--3. " HSTPULLDOWN                   ,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corres.." "0,1,2,3"
textline "                                    "
bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD          ,Use holding registers to assist in timing for external UTMI interface" "0,1"
group.long 0x54++0x03
line.long 0x00 "DEBUG0_SET,USB PHY Debug Register 0"
bitfld.long 0x00 30. " CLKGATE                       ,Gate Test Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " HOST_RESUME_DEBUG             ,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
textline "                                    "
bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH            ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24. " ENSQUELCHRESET                ,Set bit to allow squelch to reset high-speed receive" "0,1"
textline "                                    "
bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT             ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 12. " ENTX2RXCOUNT                  ,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TX2RXCOUNT                    ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--5. " ENHSTPULLDOWN                 ,This bit field selects host pulldown overdrive mode" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 2.--3. " HSTPULLDOWN                   ,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corres.." "0,1,2,3"
textline "                                    "
bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD          ,Use holding registers to assist in timing for external UTMI interface" "0,1"
group.long 0x58++0x03
line.long 0x00 "DEBUG0_CLR,USB PHY Debug Register 0"
bitfld.long 0x00 30. " CLKGATE                       ,Gate Test Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " HOST_RESUME_DEBUG             ,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
textline "                                    "
bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH            ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24. " ENSQUELCHRESET                ,Set bit to allow squelch to reset high-speed receive" "0,1"
textline "                                    "
bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT             ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 12. " ENTX2RXCOUNT                  ,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TX2RXCOUNT                    ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--5. " ENHSTPULLDOWN                 ,This bit field selects host pulldown overdrive mode" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 2.--3. " HSTPULLDOWN                   ,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corres.." "0,1,2,3"
textline "                                    "
bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD          ,Use holding registers to assist in timing for external UTMI interface" "0,1"
group.long 0x5C++0x03
line.long 0x00 "DEBUG0_TOG,USB PHY Debug Register 0"
bitfld.long 0x00 30. " CLKGATE                       ,Gate Test Clocks" "0,1"
textline "                                    "
bitfld.long 0x00 29. " HOST_RESUME_DEBUG             ,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
textline "                                    "
bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH            ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24. " ENSQUELCHRESET                ,Set bit to allow squelch to reset high-speed receive" "0,1"
textline "                                    "
bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT             ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 12. " ENTX2RXCOUNT                  ,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
textline "                                    "
bitfld.long 0x00 8.--11. " TX2RXCOUNT                    ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 4.--5. " ENHSTPULLDOWN                 ,This bit field selects host pulldown overdrive mode" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 2.--3. " HSTPULLDOWN                   ,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corres.." "0,1,2,3"
textline "                                    "
bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD          ,Use holding registers to assist in timing for external UTMI interface" "0,1"
group.long 0x70++0x03
line.long 0x00 "DEBUG1,UTMI Debug Status Register 1"
bitfld.long 0x00 21.--22. " USB2_REFBIAS_TST              ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 18.--20. " USB2_REFBIAS_VBGADJ           ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " ENTAILADJVD                   ,Delay increment of the rise of squelch:" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
group.long 0x74++0x03
line.long 0x00 "DEBUG1_SET,UTMI Debug Status Register 1"
bitfld.long 0x00 21.--22. " USB2_REFBIAS_TST              ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 18.--20. " USB2_REFBIAS_VBGADJ           ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " ENTAILADJVD                   ,Delay increment of the rise of squelch:" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
group.long 0x78++0x03
line.long 0x00 "DEBUG1_CLR,UTMI Debug Status Register 1"
bitfld.long 0x00 21.--22. " USB2_REFBIAS_TST              ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 18.--20. " USB2_REFBIAS_VBGADJ           ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " ENTAILADJVD                   ,Delay increment of the rise of squelch:" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
group.long 0x7C++0x03
line.long 0x00 "DEBUG1_TOG,UTMI Debug Status Register 1"
bitfld.long 0x00 21.--22. " USB2_REFBIAS_TST              ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 18.--20. " USB2_REFBIAS_VBGADJ           ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " ENTAILADJVD                   ,Delay increment of the rise of squelch:" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
rgroup.long 0x80++0x03
line.long 0x00 "VERSION,UTMI RTL Version"
hexmask.long.byte 0x00 24.--31. 1. " MAJOR                         ,Fixed read-only value reflecting the MAJOR field of the RTL versio"
textline "                                    "
hexmask.long.byte 0x00 16.--23. 1. " MINOR                         ,Fixed read-only value reflecting the MINOR field of the RTL version"
textline "                                    "
hexmask.long.word 0x00 0.--15. 1. " STEP                          ,Fixed read-only value reflecting the stepping of the RTL version"
group.long 0xA0++0x03
line.long 0x00 "PLL_SIC,USB PHY PLL Control/Status Register"
bitfld.long 0x00 31. " PLL_LOCK                      ,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
textline "                                    "
bitfld.long 0x00 22.--24. " PLL_DIV_SEL                   ,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
textline "                                    "
bitfld.long 0x00 21. " PLL_REG_ENABLE                ,This field controls the USB PLL regulator. set to enable the regulator" "0,1"
textline "                                    "
bitfld.long 0x00 20. " REFBIAS_PWD                   ,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
textline "                                    "
bitfld.long 0x00 19. " REFBIAS_PWD_SEL               ,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference bias"
textline "                                    "
bitfld.long 0x00 16. " PLL_BYPASS                    ,Bypass the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PLL_ENABLE                    ,Enables the clock output from the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PLL_POWER                     ,Power up the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PLL_EN_USB_CLKS               ,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xA4++0x03
line.long 0x00 "PLL_SIC_SET,USB PHY PLL Control/Status Register"
bitfld.long 0x00 31. " PLL_LOCK                      ,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
textline "                                    "
bitfld.long 0x00 22.--24. " PLL_DIV_SEL                   ,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
textline "                                    "
bitfld.long 0x00 21. " PLL_REG_ENABLE                ,This field controls the USB PLL regulator. set to enable the regulator" "0,1"
textline "                                    "
bitfld.long 0x00 20. " REFBIAS_PWD                   ,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
textline "                                    "
bitfld.long 0x00 19. " REFBIAS_PWD_SEL               ,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference bias"
textline "                                    "
bitfld.long 0x00 16. " PLL_BYPASS                    ,Bypass the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PLL_ENABLE                    ,Enables the clock output from the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PLL_POWER                     ,Power up the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PLL_EN_USB_CLKS               ,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xA8++0x03
line.long 0x00 "PLL_SIC_CLR,USB PHY PLL Control/Status Register"
bitfld.long 0x00 31. " PLL_LOCK                      ,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
textline "                                    "
bitfld.long 0x00 22.--24. " PLL_DIV_SEL                   ,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
textline "                                    "
bitfld.long 0x00 21. " PLL_REG_ENABLE                ,This field controls the USB PLL regulator. set to enable the regulator" "0,1"
textline "                                    "
bitfld.long 0x00 20. " REFBIAS_PWD                   ,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
textline "                                    "
bitfld.long 0x00 19. " REFBIAS_PWD_SEL               ,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference bias"
textline "                                    "
bitfld.long 0x00 16. " PLL_BYPASS                    ,Bypass the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PLL_ENABLE                    ,Enables the clock output from the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PLL_POWER                     ,Power up the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PLL_EN_USB_CLKS               ,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xAC++0x03
line.long 0x00 "PLL_SIC_TOG,USB PHY PLL Control/Status Register"
bitfld.long 0x00 31. " PLL_LOCK                      ,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
textline "                                    "
bitfld.long 0x00 22.--24. " PLL_DIV_SEL                   ,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
textline "                                    "
bitfld.long 0x00 21. " PLL_REG_ENABLE                ,This field controls the USB PLL regulator. set to enable the regulator" "0,1"
textline "                                    "
bitfld.long 0x00 20. " REFBIAS_PWD                   ,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
textline "                                    "
bitfld.long 0x00 19. " REFBIAS_PWD_SEL               ,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference bias"
textline "                                    "
bitfld.long 0x00 16. " PLL_BYPASS                    ,Bypass the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 13. " PLL_ENABLE                    ,Enables the clock output from the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 12. " PLL_POWER                     ,Power up the USB PLL" "0,1"
textline "                                    "
bitfld.long 0x00 6. " PLL_EN_USB_CLKS               ,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xC0++0x03
line.long 0x00 "USB1_VBUS_DETECT,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 31. " EN_CHARGER_RESISTOR           ,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors on USB_DP and USB_DP,1: Enable resistive charger detection resistors on USB_DP and USB_DP"
textline "                                    "
bitfld.long 0x00 26. " DISCHARGE_VBUS                ,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_.." "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
textline "                                    "
bitfld.long 0x00 20. " PWRUP_CMPS                    ,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
textline "                                    "
bitfld.long 0x00 18. " VBUSVALID_TO_SESSVALID        ,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the.." "0: Use the VBUS_VALID comparator for VBUS_VALID results,1: Use the Session End comparator for VBUS_VALID results"
textline "                                    "
bitfld.long 0x00 9.--10. " VBUS_SOURCE_SEL               ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the Session Valid comparator results for signal reported to the USB controller,2: Use the Session Valid comparator results for signal reported to the USB controller,"
textline "                                    "
bitfld.long 0x00 8. " VBUSVALID_SEL                 ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the VBUS_VALID_3V detector results for signal reported to the USB controller"
textline "                                    "
bitfld.long 0x00 7. " VBUSVALID_OVERRIDE            ,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBU.." "0,1"
textline "                                    "
bitfld.long 0x00 6. " AVALID_OVERRIDE               ,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " BVALID_OVERRIDE               ,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1].." "0,1"
textline "                                    "
bitfld.long 0x00 4. " SESSEND_OVERRIDE              ,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DE.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " VBUS_OVERRIDE_EN              ,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID. AVALID. BVA..,1: Use the override values for VBUS_VALID. AVALID. BVALID. and SESSEND"
textline "                                    "
bitfld.long 0x00 0.--2. " VBUSVALID_THRESH              ,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
group.long 0xC4++0x03
line.long 0x00 "USB1_VBUS_DETECT_SET,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 31. " EN_CHARGER_RESISTOR           ,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors on USB_DP and USB_DP,1: Enable resistive charger detection resistors on USB_DP and USB_DP"
textline "                                    "
bitfld.long 0x00 26. " DISCHARGE_VBUS                ,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_.." "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
textline "                                    "
bitfld.long 0x00 20. " PWRUP_CMPS                    ,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
textline "                                    "
bitfld.long 0x00 18. " VBUSVALID_TO_SESSVALID        ,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the.." "0: Use the VBUS_VALID comparator for VBUS_VALID results,1: Use the Session End comparator for VBUS_VALID results"
textline "                                    "
bitfld.long 0x00 9.--10. " VBUS_SOURCE_SEL               ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the Session Valid comparator results for signal reported to the USB controller,2: Use the Session Valid comparator results for signal reported to the USB controller,"
textline "                                    "
bitfld.long 0x00 8. " VBUSVALID_SEL                 ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the VBUS_VALID_3V detector results for signal reported to the USB controller"
textline "                                    "
bitfld.long 0x00 7. " VBUSVALID_OVERRIDE            ,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBU.." "0,1"
textline "                                    "
bitfld.long 0x00 6. " AVALID_OVERRIDE               ,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " BVALID_OVERRIDE               ,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1].." "0,1"
textline "                                    "
bitfld.long 0x00 4. " SESSEND_OVERRIDE              ,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DE.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " VBUS_OVERRIDE_EN              ,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID. AVALID. BVA..,1: Use the override values for VBUS_VALID. AVALID. BVALID. and SESSEND"
textline "                                    "
bitfld.long 0x00 0.--2. " VBUSVALID_THRESH              ,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
group.long 0xC8++0x03
line.long 0x00 "USB1_VBUS_DETECT_CLR,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 31. " EN_CHARGER_RESISTOR           ,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors on USB_DP and USB_DP,1: Enable resistive charger detection resistors on USB_DP and USB_DP"
textline "                                    "
bitfld.long 0x00 26. " DISCHARGE_VBUS                ,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_.." "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
textline "                                    "
bitfld.long 0x00 20. " PWRUP_CMPS                    ,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
textline "                                    "
bitfld.long 0x00 18. " VBUSVALID_TO_SESSVALID        ,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the.." "0: Use the VBUS_VALID comparator for VBUS_VALID results,1: Use the Session End comparator for VBUS_VALID results"
textline "                                    "
bitfld.long 0x00 9.--10. " VBUS_SOURCE_SEL               ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the Session Valid comparator results for signal reported to the USB controller,2: Use the Session Valid comparator results for signal reported to the USB controller,"
textline "                                    "
bitfld.long 0x00 8. " VBUSVALID_SEL                 ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the VBUS_VALID_3V detector results for signal reported to the USB controller"
textline "                                    "
bitfld.long 0x00 7. " VBUSVALID_OVERRIDE            ,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBU.." "0,1"
textline "                                    "
bitfld.long 0x00 6. " AVALID_OVERRIDE               ,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " BVALID_OVERRIDE               ,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1].." "0,1"
textline "                                    "
bitfld.long 0x00 4. " SESSEND_OVERRIDE              ,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DE.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " VBUS_OVERRIDE_EN              ,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID. AVALID. BVA..,1: Use the override values for VBUS_VALID. AVALID. BVALID. and SESSEND"
textline "                                    "
bitfld.long 0x00 0.--2. " VBUSVALID_THRESH              ,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
group.long 0xCC++0x03
line.long 0x00 "USB1_VBUS_DETECT_TOG,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 31. " EN_CHARGER_RESISTOR           ,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors on USB_DP and USB_DP,1: Enable resistive charger detection resistors on USB_DP and USB_DP"
textline "                                    "
bitfld.long 0x00 26. " DISCHARGE_VBUS                ,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_.." "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
textline "                                    "
bitfld.long 0x00 20. " PWRUP_CMPS                    ,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
textline "                                    "
bitfld.long 0x00 18. " VBUSVALID_TO_SESSVALID        ,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the.." "0: Use the VBUS_VALID comparator for VBUS_VALID results,1: Use the Session End comparator for VBUS_VALID results"
textline "                                    "
bitfld.long 0x00 9.--10. " VBUS_SOURCE_SEL               ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the Session Valid comparator results for signal reported to the USB controller,2: Use the Session Valid comparator results for signal reported to the USB controller,"
textline "                                    "
bitfld.long 0x00 8. " VBUSVALID_SEL                 ,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fi.." "0: Use the VBUS_VALID comparator results for signal reported to the USB controller (Default),1: Use the VBUS_VALID_3V detector results for signal reported to the USB controller"
textline "                                    "
bitfld.long 0x00 7. " VBUSVALID_OVERRIDE            ,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBU.." "0,1"
textline "                                    "
bitfld.long 0x00 6. " AVALID_OVERRIDE               ,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " BVALID_OVERRIDE               ,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1].." "0,1"
textline "                                    "
bitfld.long 0x00 4. " SESSEND_OVERRIDE              ,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DE.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " VBUS_OVERRIDE_EN              ,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID. AVALID. BVA..,1: Use the override values for VBUS_VALID. AVALID. BVALID. and SESSEND"
textline "                                    "
bitfld.long 0x00 0.--2. " VBUSVALID_THRESH              ,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
rgroup.long 0xD0++0x03
line.long 0x00 "USB1_VBUS_DET_STAT,USB PHY VBUS Detector Status Register"
bitfld.long 0x00 4. " VBUS_VALID_3V                 ,VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on th.." "0: VBUS voltage is below VBUS_VALID_3V threshold,1: VBUS voltage is above VBUS_VALID_3V threshold"
textline "                                    "
bitfld.long 0x00 3. " VBUS_VALID                    ,VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin" "0: VBUS is below the comparator threshold,1: VBUS is above the comparator threshold"
textline "                                    "
bitfld.long 0x00 2. " AVALID                        ,A-Device Session Valid status A-Device Session Valid status. determined by the Session Valid compara.." "0: The VBUS voltage is below the Session Valid threshold,1: The VBUS voltage is above the Session Valid threshold"
textline "                                    "
bitfld.long 0x00 1. " BVALID                        ,B-Device Session Valid status B-Device Session Valid status. determined by the Session Valid compara.." "0: The VBUS voltage is below the Session Valid threshold,1: The VBUS voltage is above the Session Valid threshold"
textline "                                    "
bitfld.long 0x00 0. " SESSEND                       ,Session End indicator Session End status. value inverted from Session Valid comparator" "0: The VBUS voltage is above the Session Valid threshold,1: The VBUS voltage is below the Session Valid threshold"
group.long 0xE0++0x03
line.long 0x00 "USB1_CHRG_DETECT,USB PHY Charger Detect Control Register"
bitfld.long 0x00 23. " BGR_IBIAS                     ,USB charge detector bias current reference This bit determines the reference for the bias current of.." "0: Bias current is derived from the USB PHY internal current generator,1: Bias current is derived from the reference generator of the bandgap"
textline "                                    "
bitfld.long 0x00 2. " PULLUP_DP                     ,This bit is used to pull up DP. for digital charge detect" "0,1"
group.long 0xE4++0x03
line.long 0x00 "USB1_CHRG_DETECT_SET,USB PHY Charger Detect Control Register"
bitfld.long 0x00 23. " BGR_IBIAS                     ,USB charge detector bias current reference This bit determines the reference for the bias current of.." "0: Bias current is derived from the USB PHY internal current generator,1: Bias current is derived from the reference generator of the bandgap"
textline "                                    "
bitfld.long 0x00 2. " PULLUP_DP                     ,This bit is used to pull up DP. for digital charge detect" "0,1"
group.long 0xE8++0x03
line.long 0x00 "USB1_CHRG_DETECT_CLR,USB PHY Charger Detect Control Register"
bitfld.long 0x00 23. " BGR_IBIAS                     ,USB charge detector bias current reference This bit determines the reference for the bias current of.." "0: Bias current is derived from the USB PHY internal current generator,1: Bias current is derived from the reference generator of the bandgap"
textline "                                    "
bitfld.long 0x00 2. " PULLUP_DP                     ,This bit is used to pull up DP. for digital charge detect" "0,1"
group.long 0xEC++0x03
line.long 0x00 "USB1_CHRG_DETECT_TOG,USB PHY Charger Detect Control Register"
bitfld.long 0x00 23. " BGR_IBIAS                     ,USB charge detector bias current reference This bit determines the reference for the bias current of.." "0: Bias current is derived from the USB PHY internal current generator,1: Bias current is derived from the reference generator of the bandgap"
textline "                                    "
bitfld.long 0x00 2. " PULLUP_DP                     ,This bit is used to pull up DP. for digital charge detect" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "USB1_CHRG_DET_STAT,USB PHY Charger Detect Status Register"
bitfld.long 0x00 4. " SECDET_DCP                    ,Battery Charging Secondary Detection phase output During the USB Battery Charging Secondary Detectio.." "0: Charging Downstream Port (CDP) has been detected,1: Downstream Charging Port (DCP) has been detected"
textline "                                    "
bitfld.long 0x00 3. " DP_STATE                      ,Single ended receiver output for the USB_DP pin. from charger detection circuits" "0: USB_DP pin voltage is < 0.8V,1: USB_DP pin voltage is > 2.0V"
textline "                                    "
bitfld.long 0x00 2. " DM_STATE                      ,Single ended receiver output for the USB_DM pin. from charger detection circuits" "0: USB_DM pin voltage is < 0.8V,1: USB_DM pin voltage is > 2.0V"
textline "                                    "
bitfld.long 0x00 1. " CHRG_DETECTED                 ,Battery Charging Primary Detection phase output During the USB Battery Charging Primary Detection ph.." "0: Standard Downstream Port (SDP) has been detected,1: Charging Port has been detected"
textline "                                    "
bitfld.long 0x00 0. " PLUG_CONTACT                  ,Battery Charging Data Contact Detection phase output During the Data Contact Detection phase per the.." "0: No USB cable attachment has been detected,1: A USB cable attachment between the device and host has been detected"
group.long 0x100++0x03
line.long 0x00 "ANACTRL,USB PHY Analog Control Register"
bitfld.long 0x00 10. " DEV_PULLDOWN                  ,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode,1: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode"
group.long 0x104++0x03
line.long 0x00 "ANACTRL_SET,USB PHY Analog Control Register"
bitfld.long 0x00 10. " DEV_PULLDOWN                  ,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode,1: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode"
group.long 0x108++0x03
line.long 0x00 "ANACTRL_CLR,USB PHY Analog Control Register"
bitfld.long 0x00 10. " DEV_PULLDOWN                  ,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode,1: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode"
group.long 0x10C++0x03
line.long 0x00 "ANACTRL_TOG,USB PHY Analog Control Register"
bitfld.long 0x00 10. " DEV_PULLDOWN                  ,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode,1: The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode"
group.long 0x110++0x03
line.long 0x00 "USB1_LOOPBACK,USB PHY Loopback Control/Status Register"
hexmask.long.byte 0x00 16.--23. 1. " TSTPKT                        ,Selects the packet data byte used for USB loopback testing in Pulse mode"
textline "                                    "
bitfld.long 0x00 15. " TSTI_HSFS_MODE_EN             ,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet .." "0,1"
textline "                                    "
bitfld.long 0x00 8. " UTMO_DIG_TST1                 ,This read-only bit is a status bit for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 7. " UTMO_DIG_TST0                 ,This read-only bit is a status bit for USB loopback test results" "0,1"
textline "                                    "
bitfld.long 0x00 6. " TSTI_TX_HIZ                   ,Sets TX Hi-Z for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 5. " TSTI_TX_EN                    ,Enable TX for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TSTI_TX_LS_MODE               ,Set to value 1'b1 to choose LS for USB loopback testing. set to value 1'b0 to choose HS or FS mode w.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " TSTI_TX_HS_MODE               ,Select HS or FS mode for USB loopback testing" "0,1"
textline "                                    "
bitfld.long 0x00 2. " UTMI_DIG_TST1                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 1. " UTMI_DIG_TST0                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 0. " UTMI_TESTSTART                ,This bit enables the USB loopback test" "0,1"
group.long 0x114++0x03
line.long 0x00 "USB1_LOOPBACK_SET,USB PHY Loopback Control/Status Register"
hexmask.long.byte 0x00 16.--23. 1. " TSTPKT                        ,Selects the packet data byte used for USB loopback testing in Pulse mode"
textline "                                    "
bitfld.long 0x00 15. " TSTI_HSFS_MODE_EN             ,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet .." "0,1"
textline "                                    "
bitfld.long 0x00 8. " UTMO_DIG_TST1                 ,This read-only bit is a status bit for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 7. " UTMO_DIG_TST0                 ,This read-only bit is a status bit for USB loopback test results" "0,1"
textline "                                    "
bitfld.long 0x00 6. " TSTI_TX_HIZ                   ,Sets TX Hi-Z for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 5. " TSTI_TX_EN                    ,Enable TX for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TSTI_TX_LS_MODE               ,Set to value 1'b1 to choose LS for USB loopback testing. set to value 1'b0 to choose HS or FS mode w.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " TSTI_TX_HS_MODE               ,Select HS or FS mode for USB loopback testing" "0,1"
textline "                                    "
bitfld.long 0x00 2. " UTMI_DIG_TST1                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 1. " UTMI_DIG_TST0                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 0. " UTMI_TESTSTART                ,This bit enables the USB loopback test" "0,1"
group.long 0x118++0x03
line.long 0x00 "USB1_LOOPBACK_CLR,USB PHY Loopback Control/Status Register"
hexmask.long.byte 0x00 16.--23. 1. " TSTPKT                        ,Selects the packet data byte used for USB loopback testing in Pulse mode"
textline "                                    "
bitfld.long 0x00 15. " TSTI_HSFS_MODE_EN             ,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet .." "0,1"
textline "                                    "
bitfld.long 0x00 8. " UTMO_DIG_TST1                 ,This read-only bit is a status bit for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 7. " UTMO_DIG_TST0                 ,This read-only bit is a status bit for USB loopback test results" "0,1"
textline "                                    "
bitfld.long 0x00 6. " TSTI_TX_HIZ                   ,Sets TX Hi-Z for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 5. " TSTI_TX_EN                    ,Enable TX for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TSTI_TX_LS_MODE               ,Set to value 1'b1 to choose LS for USB loopback testing. set to value 1'b0 to choose HS or FS mode w.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " TSTI_TX_HS_MODE               ,Select HS or FS mode for USB loopback testing" "0,1"
textline "                                    "
bitfld.long 0x00 2. " UTMI_DIG_TST1                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 1. " UTMI_DIG_TST0                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 0. " UTMI_TESTSTART                ,This bit enables the USB loopback test" "0,1"
group.long 0x11C++0x03
line.long 0x00 "USB1_LOOPBACK_TOG,USB PHY Loopback Control/Status Register"
hexmask.long.byte 0x00 16.--23. 1. " TSTPKT                        ,Selects the packet data byte used for USB loopback testing in Pulse mode"
textline "                                    "
bitfld.long 0x00 15. " TSTI_HSFS_MODE_EN             ,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet .." "0,1"
textline "                                    "
bitfld.long 0x00 8. " UTMO_DIG_TST1                 ,This read-only bit is a status bit for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 7. " UTMO_DIG_TST0                 ,This read-only bit is a status bit for USB loopback test results" "0,1"
textline "                                    "
bitfld.long 0x00 6. " TSTI_TX_HIZ                   ,Sets TX Hi-Z for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 5. " TSTI_TX_EN                    ,Enable TX for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TSTI_TX_LS_MODE               ,Set to value 1'b1 to choose LS for USB loopback testing. set to value 1'b0 to choose HS or FS mode w.." "0,1"
textline "                                    "
bitfld.long 0x00 3. " TSTI_TX_HS_MODE               ,Select HS or FS mode for USB loopback testing" "0,1"
textline "                                    "
bitfld.long 0x00 2. " UTMI_DIG_TST1                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 1. " UTMI_DIG_TST0                 ,Mode control for USB loopback test" "0,1"
textline "                                    "
bitfld.long 0x00 0. " UTMI_TESTSTART                ,This bit enables the USB loopback test" "0,1"
group.long 0x120++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT,USB PHY Loopback Packet Number Select Register"
hexmask.long.word 0x00 16.--31. 1. " TSTI_FS_NUMBER                ,Full speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
textline "                                    "
hexmask.long.word 0x00 0.--15. 1. " TSTI_HS_NUMBER                ,High speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
group.long 0x124++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_SET,USB PHY Loopback Packet Number Select Register"
hexmask.long.word 0x00 16.--31. 1. " TSTI_FS_NUMBER                ,Full speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
textline "                                    "
hexmask.long.word 0x00 0.--15. 1. " TSTI_HS_NUMBER                ,High speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
group.long 0x128++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_CLR,USB PHY Loopback Packet Number Select Register"
hexmask.long.word 0x00 16.--31. 1. " TSTI_FS_NUMBER                ,Full speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
textline "                                    "
hexmask.long.word 0x00 0.--15. 1. " TSTI_HS_NUMBER                ,High speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
group.long 0x12C++0x03
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_TOG,USB PHY Loopback Packet Number Select Register"
hexmask.long.word 0x00 16.--31. 1. " TSTI_FS_NUMBER                ,Full speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
textline "                                    "
hexmask.long.word 0x00 0.--15. 1. " TSTI_HS_NUMBER                ,High speed packet number. used when USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
group.long 0x130++0x03
line.long 0x00 "TRIM_OVERRIDE_EN,USB PHY Trim Override Enable Register"
bitfld.long 0x00 28.--31. " TRIM_USBPHY_TX_CAL45DM        ,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24.--27. " TRIM_USBPHY_TX_CAL45DP        ,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 20.--23. " TRIM_USBPHY_TX_D_CAL          ,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 18.--19. " TRIM_USB_REG_ENV_TAIL_ADJ_VD  ,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 15.--17. " TRIM_PLL_CTRL0_DIV_SEL        ,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " TRIM_USB2_REFBIAS_TST         ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 10.--12. " TRIM_USB2_REFBIAS_VBGADJ      ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 6. " TRIM_REFBIAS_TST_OVERRIDE     ,Override enable for bias current control When this field is set. the register value in DEBUG1[22:21].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " TRIM_REFBIAS_VBGADJ_OVERRIDE  ,Override enable for bandgap adjustment" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TRIM_TX_CAL45DM_OVERRIDE      ,Override enable for TX_CAL45DM. when set. the register value in TX[11:8] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 3. " TRIM_TX_CAL45DP_OVERRIDE      ,Override enable for TX_CAL45DP. when set. the register value in TX[19:16] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 2. " TRIM_TX_D_CAL_OVERRIDE        ,Override enable for TX_D_CAL. when set. the register value in TX[3:0] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 1. " TRIM_ENV_TAIL_ADJ_VD_OVERRIDE ,Override enable for ENV_TAIL_ADJ. when set. the register value in DEBUG1[14:13] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 0. " TRIM_DIV_SEL_OVERRIDE         ,Override enable for PLL_DIV_SEL. when set. the register value in PLL_SIC[1:0] will be used" "0,1"
group.long 0x134++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_SET,USB PHY Trim Override Enable Register"
bitfld.long 0x00 28.--31. " TRIM_USBPHY_TX_CAL45DM        ,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24.--27. " TRIM_USBPHY_TX_CAL45DP        ,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 20.--23. " TRIM_USBPHY_TX_D_CAL          ,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 18.--19. " TRIM_USB_REG_ENV_TAIL_ADJ_VD  ,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 15.--17. " TRIM_PLL_CTRL0_DIV_SEL        ,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " TRIM_USB2_REFBIAS_TST         ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 10.--12. " TRIM_USB2_REFBIAS_VBGADJ      ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 6. " TRIM_REFBIAS_TST_OVERRIDE     ,Override enable for bias current control When this field is set. the register value in DEBUG1[22:21].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " TRIM_REFBIAS_VBGADJ_OVERRIDE  ,Override enable for bandgap adjustment" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TRIM_TX_CAL45DM_OVERRIDE      ,Override enable for TX_CAL45DM. when set. the register value in TX[11:8] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 3. " TRIM_TX_CAL45DP_OVERRIDE      ,Override enable for TX_CAL45DP. when set. the register value in TX[19:16] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 2. " TRIM_TX_D_CAL_OVERRIDE        ,Override enable for TX_D_CAL. when set. the register value in TX[3:0] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 1. " TRIM_ENV_TAIL_ADJ_VD_OVERRIDE ,Override enable for ENV_TAIL_ADJ. when set. the register value in DEBUG1[14:13] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 0. " TRIM_DIV_SEL_OVERRIDE         ,Override enable for PLL_DIV_SEL. when set. the register value in PLL_SIC[1:0] will be used" "0,1"
group.long 0x138++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_CLR,USB PHY Trim Override Enable Register"
bitfld.long 0x00 28.--31. " TRIM_USBPHY_TX_CAL45DM        ,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24.--27. " TRIM_USBPHY_TX_CAL45DP        ,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 20.--23. " TRIM_USBPHY_TX_D_CAL          ,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 18.--19. " TRIM_USB_REG_ENV_TAIL_ADJ_VD  ,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 15.--17. " TRIM_PLL_CTRL0_DIV_SEL        ,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " TRIM_USB2_REFBIAS_TST         ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 10.--12. " TRIM_USB2_REFBIAS_VBGADJ      ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 6. " TRIM_REFBIAS_TST_OVERRIDE     ,Override enable for bias current control When this field is set. the register value in DEBUG1[22:21].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " TRIM_REFBIAS_VBGADJ_OVERRIDE  ,Override enable for bandgap adjustment" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TRIM_TX_CAL45DM_OVERRIDE      ,Override enable for TX_CAL45DM. when set. the register value in TX[11:8] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 3. " TRIM_TX_CAL45DP_OVERRIDE      ,Override enable for TX_CAL45DP. when set. the register value in TX[19:16] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 2. " TRIM_TX_D_CAL_OVERRIDE        ,Override enable for TX_D_CAL. when set. the register value in TX[3:0] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 1. " TRIM_ENV_TAIL_ADJ_VD_OVERRIDE ,Override enable for ENV_TAIL_ADJ. when set. the register value in DEBUG1[14:13] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 0. " TRIM_DIV_SEL_OVERRIDE         ,Override enable for PLL_DIV_SEL. when set. the register value in PLL_SIC[1:0] will be used" "0,1"
group.long 0x13C++0x03
line.long 0x00 "TRIM_OVERRIDE_EN_TOG,USB PHY Trim Override Enable Register"
bitfld.long 0x00 28.--31. " TRIM_USBPHY_TX_CAL45DM        ,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 24.--27. " TRIM_USBPHY_TX_CAL45DP        ,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 20.--23. " TRIM_USBPHY_TX_D_CAL          ,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                    "
bitfld.long 0x00 18.--19. " TRIM_USB_REG_ENV_TAIL_ADJ_VD  ,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 15.--17. " TRIM_PLL_CTRL0_DIV_SEL        ,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 13.--14. " TRIM_USB2_REFBIAS_TST         ,Bias current control for usb2_phy" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 10.--12. " TRIM_USB2_REFBIAS_VBGADJ      ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
textline "                                    "
bitfld.long 0x00 6. " TRIM_REFBIAS_TST_OVERRIDE     ,Override enable for bias current control When this field is set. the register value in DEBUG1[22:21].." "0,1"
textline "                                    "
bitfld.long 0x00 5. " TRIM_REFBIAS_VBGADJ_OVERRIDE  ,Override enable for bandgap adjustment" "0,1"
textline "                                    "
bitfld.long 0x00 4. " TRIM_TX_CAL45DM_OVERRIDE      ,Override enable for TX_CAL45DM. when set. the register value in TX[11:8] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 3. " TRIM_TX_CAL45DP_OVERRIDE      ,Override enable for TX_CAL45DP. when set. the register value in TX[19:16] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 2. " TRIM_TX_D_CAL_OVERRIDE        ,Override enable for TX_D_CAL. when set. the register value in TX[3:0] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 1. " TRIM_ENV_TAIL_ADJ_VD_OVERRIDE ,Override enable for ENV_TAIL_ADJ. when set. the register value in DEBUG1[14:13] will be used" "0,1"
textline "                                    "
bitfld.long 0x00 0. " TRIM_DIV_SEL_OVERRIDE         ,Override enable for PLL_DIV_SEL. when set. the register value in PLL_SIC[1:0] will be used" "0,1"
width 0x0B
tree.end
tree "USDHC (Ultra Secured Digital Host Controller)"
tree "USDHC0"
base ad:0x40136000
width 22.
group.long 0x00++0x03
line.long 0x00 "DS_ADDR,DMA System Address"
hexmask.long 0x00 0.--31. 1. " DS_ADDR                          ,DS_ADDR"
group.long 0x04++0x03
line.long 0x00 "BLK_ATT,Block Attributes"
hexmask.long.word 0x00 16.--31. 1. " BLKCNT                           ,Block Count"
textline "                               "
hexmask.long.word 0x00 0.--12. 1. " BLKSIZE                          ,Block Size"
group.long 0x08++0x03
line.long 0x00 "CMD_ARG,Command Argument"
hexmask.long 0x00 0.--31. 1. " CMDARG                           ,Command Argument"
group.long 0x0C++0x03
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
bitfld.long 0x00 24.--29. " CMDINX                           ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                               "
bitfld.long 0x00 22.--23. " CMDTYP                           ,Command Type" "0: Normal Other commands,1: Suspend CMD52 for writing Bus Suspend in CCCR,2: Resume CMD52 for writing Function Select in CCCR,3: Abort CMD12. CMD52 for writing I/O Abort in CCCR"
textline "                               "
bitfld.long 0x00 21. " DPSEL                            ,Data Present Select" "0: No Data Present,1: Data Present"
textline "                               "
bitfld.long 0x00 20. " CICEN                            ,Command Index Check Enable" "0: CICEN_0,1: CICEN_1"
textline "                               "
bitfld.long 0x00 19. " CCCEN                            ,Command CRC Check Enable" "0: CCCEN_0,1: CCCEN_1"
textline "                               "
bitfld.long 0x00 16.--17. " RSPTYP                           ,Response Type Select" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48. check Busy after response"
rgroup.long 0x10++0x03
line.long 0x00 "CMD_RSP0,Command Response0"
hexmask.long 0x00 0.--31. 1. " CMDRSP0                          ,Command Response 0"
rgroup.long 0x14++0x03
line.long 0x00 "CMD_RSP1,Command Response1"
hexmask.long 0x00 0.--31. 1. " CMDRSP1                          ,Command Response 1"
rgroup.long 0x18++0x03
line.long 0x00 "CMD_RSP2,Command Response2"
hexmask.long 0x00 0.--31. 1. " CMDRSP2                          ,Command Response 2"
rgroup.long 0x1C++0x03
line.long 0x00 "CMD_RSP3,Command Response3"
hexmask.long 0x00 0.--31. 1. " CMDRSP3                          ,Command Response 3"
group.long 0x20++0x03
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
hexmask.long 0x00 0.--31. 1. " DATCONT                          ,Data Content"
rgroup.long 0x24++0x03
line.long 0x00 "PRES_STATE,Present State"
hexmask.long.byte 0x00 24.--31. 1. " DLSL                             ,DATA[7:0] Line Signal Level"
textline "                               "
bitfld.long 0x00 23. " CLSL                             ,CMD Line Signal Level" "0,1"
textline "                               "
bitfld.long 0x00 19. " WPSPL                            ,Write Protect Switch Pin Level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
textline "                               "
bitfld.long 0x00 18. " CDPL                             ,Card Detect Pin Level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
textline "                               "
bitfld.long 0x00 16. " CINST                            ,Card Inserted" "0: Power on Reset or No Card,1: Card Inserted"
textline "                               "
bitfld.long 0x00 15. " TSCD                             ,Tape Select Change Done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
textline "                               "
bitfld.long 0x00 12. " RTR                              ,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
textline "                               "
bitfld.long 0x00 11. " BREN                             ,Buffer Read Enable" "0: Read disable,1: Read enable"
textline "                               "
bitfld.long 0x00 10. " BWEN                             ,Buffer Write Enable" "0: Write disable,1: Write enable"
textline "                               "
bitfld.long 0x00 9. " RTA                              ,Read Transfer Active" "0: No valid data,1: Transferring data"
textline "                               "
bitfld.long 0x00 8. " WTA                              ,Write Transfer Active" "0: No valid data,1: Transferring data"
textline "                               "
bitfld.long 0x00 7. " SDOFF                            ,SD Clock Gated Off Internally" "0: SD Clock is active,1: SD Clock is gated off"
textline "                               "
bitfld.long 0x00 6. " PEROFF                           ,IPG_PERCLK Gated Off Internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
textline "                               "
bitfld.long 0x00 5. " HCKOFF                           ,HCLK Gated Off Internally" "0: HCLK is active,1: HCLK is gated off"
textline "                               "
bitfld.long 0x00 4. " IPGOFF                           ,IPG_CLK Gated Off Internally" "0: IPG_CLK is active,1: IPG_CLK is gated off"
textline "                               "
bitfld.long 0x00 3. " SDSTB                            ,SD Clock Stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
textline "                               "
bitfld.long 0x00 2. " DLA                              ,Data Line Active" "0: DATA Line Inactive,1: DATA Line Active"
textline "                               "
bitfld.long 0x00 1. " CDIHB                            ,Command Inhibit (DATA)" "0: Can issue command which uses the DATA line,1: Cannot issue command which uses the DATA line"
textline "                               "
bitfld.long 0x00 0. " CIHB                             ,Command Inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
group.long 0x28++0x03
line.long 0x00 "PROT_CTRL,Protocol Control"
bitfld.long 0x00 31. " RD_NO8CLK_EN                     ,RD_NO8CLK_EN" "0: Disable S/W RD_DONE_NO_8CLK. uSHDC determines if 8 clocks are needed automatically,1: S/W RD_DONE_NO_8CLK is enabled"
textline "                               "
bitfld.long 0x00 30. " NON_EXACT_BLK_RD                 ,NON_EXACT_BLK_RD" "0: The block read is exact block read,1: The block read is non-exact block read"
textline "                               "
bitfld.long 0x00 27.--29. " BURST_LEN_EN                     ,BURST length enable for INCR. INCR4 / INCR8 / INCR16. INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" ",1: Burst length is enabled for INCR,,3: Burst length is enabled for INCR,,5: Burst length is enabled for INCR,,7: Burst length is enabled for INCR"
textline "                               "
bitfld.long 0x00 26. " WECRM                            ,Wakeup Event Enable On SD Card Removal" "0: WECRM_0,1: WECRM_1"
textline "                               "
bitfld.long 0x00 25. " WECINS                           ,Wakeup Event Enable On SD Card Insertion" "0: WECINS_0,1: WECINS_1"
textline "                               "
bitfld.long 0x00 24. " WECINT                           ,Wakeup Event Enable On Card Interrupt" "0: WECINT_0,1: WECINT_1"
textline "                               "
bitfld.long 0x00 21.--23. " RD_WAIT_POINT                    ,Read wait point" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 20. " RD_DONE_NO_8CLK                  ,RD_DONE_NO_8CLK" "0,1"
textline "                               "
bitfld.long 0x00 19. " IABG                             ,Interrupt At Block Gap" "0: Disabled,1: Enabled"
textline "                               "
bitfld.long 0x00 18. " RWCTL                            ,Read Wait Control" "0: Disable Read Wait Control. and stop SD Clock at block gap when SABGREQ bit is set,1: Enable Read Wait Control. and assert Read Wait without stopping SD Clock at block gap when SABGREQ b.."
textline "                               "
bitfld.long 0x00 17. " CREQ                             ,Continue Request" "0: No effect,1: Restart"
textline "                               "
bitfld.long 0x00 16. " SABGREQ                          ,Stop At Block Gap Request" "0: SABGREQ_0,1: SABGREQ_1"
textline "                               "
bitfld.long 0x00 8.--9. " DMASEL                           ,DMA Select" "0: No DMA or Simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,"
textline "                               "
bitfld.long 0x00 7. " CDSS                             ,Card Detect Signal Selection" "0: Card Detection Level is selected (for normal purpose),1: Card Detection Test Level is selected (for test purpose)"
textline "                               "
bitfld.long 0x00 6. " CDTL                             ,Card Detect Test Level" "0: Card Detect Test Level is 0. no card inserted,1: Card Detect Test Level is 1. card inserted"
textline "                               "
bitfld.long 0x00 4.--5. " EMODE                            ,Endian Mode" "0: Big Endian Mode,1: Half Word Big Endian Mode,2: Little Endian Mode,"
textline "                               "
bitfld.long 0x00 3. " D3CD                             ,DATA3 as Card Detection Pin" "0: DATA3 does not monitor Card Insertion,1: DATA3 as Card Detection Pin"
textline "                               "
bitfld.long 0x00 1.--2. " DTW                              ,Data Transfer Width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,"
group.long 0x2C++0x03
line.long 0x00 "SYS_CTRL,System Control"
bitfld.long 0x00 28. " RSTT                             ,Reset Tuning" "0,1"
textline "                               "
bitfld.long 0x00 27. " INITA                            ,Initialization Active" "0,1"
textline "                               "
bitfld.long 0x00 26. " RSTD                             ,Software Reset For DATA Line" "0: No Reset,1: RSTD_1"
textline "                               "
bitfld.long 0x00 25. " RSTC                             ,Software Reset For CMD Line" "0: No Reset,1: RSTC_1"
textline "                               "
bitfld.long 0x00 24. " RSTA                             ,Software Reset For ALL" "0: No Reset,1: RSTA_1"
textline "                               "
bitfld.long 0x00 23. " IPP_RST_N                        ,IPP_RST_N" "0,1"
textline "                               "
bitfld.long 0x00 16.--19. " DTOCV                            ,Data Timeout Counter Value" "0: SDCLK x 2 14,1: SDCLK x 2 15,,,,,,,,,,,,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29"
textline "                               "
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS                          ,SDCLK Frequency Select"
textline "                               "
bitfld.long 0x00 4.--7. " DVS                              ,Divisor" "0: Divide-by-1,1: Divide-by-2,,,,,,,,,,,,,14: Divide-by-15,15: Divide-by-16"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
eventfld.long 0x00 28. " DMAE                             ,DMA Error" "0: No Error,1: DMAE_1"
textline "                               "
eventfld.long 0x00 26. " TNE                              ,Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
textline "                               "
eventfld.long 0x00 24. " AC12E                            ,Auto CMD12 Error" "0: No Error,1: AC12E_1"
textline "                               "
eventfld.long 0x00 22. " DEBE                             ,Data End Bit Error" "0: No Error,1: DEBE_1"
textline "                               "
eventfld.long 0x00 21. " DCE                              ,Data CRC Error" "0: No Error,1: DCE_1"
textline "                               "
eventfld.long 0x00 20. " DTOE                             ,Data Timeout Error" "0: No Error,1: Time out"
textline "                               "
eventfld.long 0x00 19. " CIE                              ,Command Index Error" "0: No Error,1: CIE_1"
textline "                               "
eventfld.long 0x00 18. " CEBE                             ,Command End Bit Error" "0: No Error,1: End Bit Error Generated"
textline "                               "
eventfld.long 0x00 17. " CCE                              ,Command CRC Error" "0: No Error,1: CRC Error Generated"
textline "                               "
eventfld.long 0x00 16. " CTOE                             ,Command Timeout Error" "0: No Error,1: Time out"
textline "                               "
eventfld.long 0x00 14. " TP                               ,Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
textline "                               "
eventfld.long 0x00 12. " RTE                              ,Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-Tuning is not required,1: Re-Tuning should be performed"
textline "                               "
eventfld.long 0x00 8. " CINT                             ,Card Interrupt" "0: No Card Interrupt,1: Generate Card Interrupt"
textline "                               "
eventfld.long 0x00 7. " CRM                              ,Card Removal" "0: Card state unstable or inserted,1: Card removed"
textline "                               "
eventfld.long 0x00 6. " CINS                             ,Card Insertion" "0: Card state unstable or removed,1: Card inserted"
textline "                               "
eventfld.long 0x00 5. " BRR                              ,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
textline "                               "
eventfld.long 0x00 4. " BWR                              ,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer:"
textline "                               "
eventfld.long 0x00 3. " DINT                             ,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
textline "                               "
eventfld.long 0x00 2. " BGE                              ,Block Gap Event" "0: No block gap event,1: Transaction stopped at block gap"
textline "                               "
eventfld.long 0x00 1. " TC                               ,Transfer Complete" "0: Transfer not complete,1: Transfer complete"
textline "                               "
eventfld.long 0x00 0. " CC                               ,Command Complete" "0: Command not complete,1: Command complete"
group.long 0x34++0x03
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
bitfld.long 0x00 28. " DMAESEN                          ,DMA Error Status Enable" "0: DMAESEN_0,1: DMAESEN_1"
textline "                               "
bitfld.long 0x00 26. " TNESEN                           ,Tuning Error Status Enable" "0: TNESEN_0,1: TNESEN_1"
textline "                               "
bitfld.long 0x00 24. " AC12ESEN                         ,Auto CMD12 Error Status Enable" "0: AC12ESEN_0,1: AC12ESEN_1"
textline "                               "
bitfld.long 0x00 22. " DEBESEN                          ,Data End Bit Error Status Enable" "0: DEBESEN_0,1: DEBESEN_1"
textline "                               "
bitfld.long 0x00 21. " DCESEN                           ,Data CRC Error Status Enable" "0: DCESEN_0,1: DCESEN_1"
textline "                               "
bitfld.long 0x00 20. " DTOESEN                          ,Data Timeout Error Status Enable" "0: DTOESEN_0,1: DTOESEN_1"
textline "                               "
bitfld.long 0x00 19. " CIESEN                           ,Command Index Error Status Enable" "0: CIESEN_0,1: CIESEN_1"
textline "                               "
bitfld.long 0x00 18. " CEBESEN                          ,Command End Bit Error Status Enable" "0: CEBESEN_0,1: CEBESEN_1"
textline "                               "
bitfld.long 0x00 17. " CCESEN                           ,Command CRC Error Status Enable" "0: CCESEN_0,1: CCESEN_1"
textline "                               "
bitfld.long 0x00 16. " CTOESEN                          ,Command Timeout Error Status Enable" "0: CTOESEN_0,1: CTOESEN_1"
textline "                               "
bitfld.long 0x00 14. " TPSEN                            ,Tuning Pass Status Enable" "0: TPSEN_0,1: TPSEN_1"
textline "                               "
bitfld.long 0x00 12. " RTESEN                           ,Re-Tuning Event Status Enable" "0: RTESEN_0,1: RTESEN_1"
textline "                               "
bitfld.long 0x00 8. " CINTSEN                          ,Card Interrupt Status Enable" "0: CINTSEN_0,1: CINTSEN_1"
textline "                               "
bitfld.long 0x00 7. " CRMSEN                           ,Card Removal Status Enable" "0: CRMSEN_0,1: CRMSEN_1"
textline "                               "
bitfld.long 0x00 6. " CINSSEN                          ,Card Insertion Status Enable" "0: CINSSEN_0,1: CINSSEN_1"
textline "                               "
bitfld.long 0x00 5. " BRRSEN                           ,Buffer Read Ready Status Enable" "0: BRRSEN_0,1: BRRSEN_1"
textline "                               "
bitfld.long 0x00 4. " BWRSEN                           ,Buffer Write Ready Status Enable" "0: BWRSEN_0,1: BWRSEN_1"
textline "                               "
bitfld.long 0x00 3. " DINTSEN                          ,DMA Interrupt Status Enable" "0: DINTSEN_0,1: DINTSEN_1"
textline "                               "
bitfld.long 0x00 2. " BGESEN                           ,Block Gap Event Status Enable" "0: BGESEN_0,1: BGESEN_1"
textline "                               "
bitfld.long 0x00 1. " TCSEN                            ,Transfer Complete Status Enable" "0: TCSEN_0,1: TCSEN_1"
textline "                               "
bitfld.long 0x00 0. " CCSEN                            ,Command Complete Status Enable" "0: CCSEN_0,1: CCSEN_1"
group.long 0x38++0x03
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
bitfld.long 0x00 28. " DMAEIEN                          ,DMA Error Interrupt Enable" "0: DMAEIEN_0,1: DMAEIEN_1"
textline "                               "
bitfld.long 0x00 26. " TNEIEN                           ,Tuning Error Interrupt Enable" "0: TNEIEN_0,1: TNEIEN_1"
textline "                               "
bitfld.long 0x00 24. " AC12EIEN                         ,Auto CMD12 Error Interrupt Enable" "0: AC12EIEN_0,1: AC12EIEN_1"
textline "                               "
bitfld.long 0x00 22. " DEBEIEN                          ,Data End Bit Error Interrupt Enable" "0: DEBEIEN_0,1: DEBEIEN_1"
textline "                               "
bitfld.long 0x00 21. " DCEIEN                           ,Data CRC Error Interrupt Enable" "0: DCEIEN_0,1: DCEIEN_1"
textline "                               "
bitfld.long 0x00 20. " DTOEIEN                          ,Data Timeout Error Interrupt Enable" "0: DTOEIEN_0,1: DTOEIEN_1"
textline "                               "
bitfld.long 0x00 19. " CIEIEN                           ,Command Index Error Interrupt Enable" "0: CIEIEN_0,1: CIEIEN_1"
textline "                               "
bitfld.long 0x00 18. " CEBEIEN                          ,Command End Bit Error Interrupt Enable" "0: CEBEIEN_0,1: CEBEIEN_1"
textline "                               "
bitfld.long 0x00 17. " CCEIEN                           ,Command CRC Error Interrupt Enable" "0: CCEIEN_0,1: CCEIEN_1"
textline "                               "
bitfld.long 0x00 16. " CTOEIEN                          ,Command Timeout Error Interrupt Enable" "0: CTOEIEN_0,1: CTOEIEN_1"
textline "                               "
bitfld.long 0x00 14. " TPIEN                            ,Tuning Pass Interrupt Enable" "0: TPIEN_0,1: TPIEN_1"
textline "                               "
bitfld.long 0x00 12. " RTEIEN                           ,Re-Tuning Event Interrupt Enable" "0: RTEIEN_0,1: RTEIEN_1"
textline "                               "
bitfld.long 0x00 8. " CINTIEN                          ,Card Interrupt Interrupt Enable" "0: CINTIEN_0,1: CINTIEN_1"
textline "                               "
bitfld.long 0x00 7. " CRMIEN                           ,Card Removal Interrupt Enable" "0: CRMIEN_0,1: CRMIEN_1"
textline "                               "
bitfld.long 0x00 6. " CINSIEN                          ,Card Insertion Interrupt Enable" "0: CINSIEN_0,1: CINSIEN_1"
textline "                               "
bitfld.long 0x00 5. " BRRIEN                           ,Buffer Read Ready Interrupt Enable" "0: BRRIEN_0,1: BRRIEN_1"
textline "                               "
bitfld.long 0x00 4. " BWRIEN                           ,Buffer Write Ready Interrupt Enable" "0: BWRIEN_0,1: BWRIEN_1"
textline "                               "
bitfld.long 0x00 3. " DINTIEN                          ,DMA Interrupt Enable" "0: DINTIEN_0,1: DINTIEN_1"
textline "                               "
bitfld.long 0x00 2. " BGEIEN                           ,Block Gap Event Interrupt Enable" "0: BGEIEN_0,1: BGEIEN_1"
textline "                               "
bitfld.long 0x00 1. " TCIEN                            ,Transfer Complete Interrupt Enable" "0: TCIEN_0,1: TCIEN_1"
textline "                               "
bitfld.long 0x00 0. " CCIEN                            ,Command Complete Interrupt Enable" "0: CCIEN_0,1: CCIEN_1"
group.long 0x3C++0x03
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
bitfld.long 0x00 23. " SMP_CLK_SEL                      ,Sample Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
textline "                               "
bitfld.long 0x00 22. " EXECUTE_TUNING                   ,Execute Tuning" "0,1"
textline "                               "
rbitfld.long 0x00 7. " CNIBAC12E                        ,Command Not Issued By Auto CMD12 Error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
textline "                               "
rbitfld.long 0x00 4. " AC12IE                           ,Auto CMD12 / 23 Index Error" "0: AC12IE_0,1: Error. the CMD index in response is not CMD12/23"
textline "                               "
rbitfld.long 0x00 3. " AC12CE                           ,Auto CMD12 / 23 CRC Error" "0: No CRC error,1: CRC Error Met in Auto CMD12/23 Response"
textline "                               "
rbitfld.long 0x00 2. " AC12EBE                          ,Auto CMD12 / 23 End Bit Error" "0: AC12EBE_0,1: End Bit Error Generated"
textline "                               "
rbitfld.long 0x00 1. " AC12TOE                          ,Auto CMD12 / 23 Timeout Error" "0: AC12TOE_0,1: AC12TOE_1"
textline "                               "
rbitfld.long 0x00 0. " AC12NE                           ,Auto CMD12 Not Executed" "0: AC12NE_0,1: Not executed"
group.long 0x40++0x03
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
rbitfld.long 0x00 26. " VS18                             ,Voltage Support 1.8 V" "0: 1.8V not supported,1: 1.8V supported"
textline "                               "
rbitfld.long 0x00 25. " VS30                             ,Voltage Support 3.0 V" "0: 3.0V not supported,1: 3.0V supported"
textline "                               "
rbitfld.long 0x00 24. " VS33                             ,Voltage Support 3.3V" "0: 3.3V not supported,1: 3.3V supported"
textline "                               "
rbitfld.long 0x00 23. " SRS                              ,Suspend / Resume Support" "0: Not supported,1: Supported"
textline "                               "
rbitfld.long 0x00 22. " DMAS                             ,DMA Support" "0: DMA not supported,1: DMA Supported"
textline "                               "
rbitfld.long 0x00 21. " HSS                              ,High Speed Support" "0: High Speed Not Supported,1: High Speed Supported"
textline "                               "
rbitfld.long 0x00 20. " ADMAS                            ,ADMA Support" "0: Advanced DMA Not supported,1: Advanced DMA Supported"
textline "                               "
rbitfld.long 0x00 16.--18. " MBL                              ,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,,,,"
textline "                               "
rbitfld.long 0x00 14.--15. " RETUNING_MODE                    ,Retuning Mode" "0: RETUNING_MODE_0,1: RETUNING_MODE_1,2: RETUNING_MODE_2,"
textline "                               "
bitfld.long 0x00 13. " USE_TUNING_SDR50                 ,Use Tuning for SDR50" "0: SDR does not require tuning,1: SDR50 requires tuning"
textline "                               "
bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING              ,Time Counter for Retuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 2. " DDR50_SUPPORT                    ,DDR50 support" "0,1"
textline "                               "
rbitfld.long 0x00 1. " SDR104_SUPPORT                   ,SDR104 support" "0,1"
textline "                               "
rbitfld.long 0x00 0. " SDR50_SUPPORT                    ,SDR50 support" "0,1"
group.long 0x44++0x03
line.long 0x00 "WTMK_LVL,Watermark Level"
bitfld.long 0x00 24.--28. " WR_BRST_LEN                      ,Write Burst Length Due to system restriction. the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                               "
hexmask.long.byte 0x00 16.--23. 1. " WR_WML                           ,Write Watermark Level"
textline "                               "
bitfld.long 0x00 8.--12. " RD_BRST_LEN                      ,Read Burst Length Due to system restriction. the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                               "
hexmask.long.byte 0x00 0.--7. 1. " RD_WML                           ,Read Watermark Level"
group.long 0x48++0x03
line.long 0x00 "MIX_CTRL,Mixer Control"
bitfld.long 0x00 26. " HS400_MODE                       ,Enable HS400 Mode" "0,1"
textline "                               "
bitfld.long 0x00 25. " FBCLK_SEL                        ,Feedback Clock Source Selection (Only used for SD3.0. SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
textline "                               "
bitfld.long 0x00 24. " AUTO_TUNE_EN                     ,Auto Tuning Enable (Only used for SD3.0. SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
textline "                               "
bitfld.long 0x00 23. " SMP_CLK_SEL                      ,SMP_CLK_SEL" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
textline "                               "
bitfld.long 0x00 22. " EXE_TUNE                         ,Execute Tuning: (Only used for SD3.0. SDR104 mode and EMMC HS200 mode)" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
textline "                               "
bitfld.long 0x00 7. " AC23EN                           ,Auto CMD23 Enable" "0,1"
textline "                               "
bitfld.long 0x00 6. " NIBBLE_POS                       ,NIBBLE_POS" "0,1"
textline "                               "
bitfld.long 0x00 5. " MSBSEL                           ,Multi / Single Block Select" "0: Single Block,1: Multiple Blocks"
textline "                               "
bitfld.long 0x00 4. " DTDSEL                           ,Data Transfer Direction Select" "0: Write (Host to Card),1: Read (Card to Host)"
textline "                               "
bitfld.long 0x00 3. " DDR_EN                           ,Dual Data Rate mode selection" "0,1"
textline "                               "
bitfld.long 0x00 2. " AC12EN                           ,Auto CMD12 Enable" "0: AC12EN_0,1: AC12EN_1"
textline "                               "
bitfld.long 0x00 1. " BCEN                             ,Block Count Enable" "0: Disable,1: BCEN_1"
textline "                               "
bitfld.long 0x00 0. " DMAEN                            ,DMA Enable" "0: DMAEN_0,1: DMAEN_1"
group.long 0x50++0x03
line.long 0x00 "FORCE_EVENT,Force Event"
bitfld.long 0x00 31. " FEVTCINT                         ,Force Event Card Interrupt" "0,1"
textline "                               "
bitfld.long 0x00 28. " FEVTDMAE                         ,Force Event DMA Error" "0,1"
textline "                               "
bitfld.long 0x00 26. " FEVTTNE                          ,Force Tuning Error" "0,1"
textline "                               "
bitfld.long 0x00 24. " FEVTAC12E                        ,Force Event Auto Command 12 Error" "0,1"
textline "                               "
bitfld.long 0x00 22. " FEVTDEBE                         ,Force Event Data End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 21. " FEVTDCE                          ,Force Event Data CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 20. " FEVTDTOE                         ,Force Event Data Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 19. " FEVTCIE                          ,Force Event Command Index Error" "0,1"
textline "                               "
bitfld.long 0x00 18. " FEVTCEBE                         ,Force Event Command End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 17. " FEVTCCE                          ,Force Event Command CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 16. " FEVTCTOE                         ,Force Event Command Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 7. " FEVTCNIBAC12E                    ,Force Event Command Not Executed By Auto Command 12 Error" "0,1"
textline "                               "
bitfld.long 0x00 4. " FEVTAC12IE                       ,Force Event Auto Command 12 Index Error" "0,1"
textline "                               "
bitfld.long 0x00 3. " FEVTAC12EBE                      ,Force Event Auto Command 12 End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 2. " FEVTAC12CE                       ,Force Event Auto Command 12 CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 1. " FEVTAC12TOE                      ,Force Event Auto Command 12 Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 0. " FEVTAC12NE                       ,Force Event Auto Command 12 Not Executed" "0,1"
rgroup.long 0x54++0x03
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register"
bitfld.long 0x00 3. " ADMADCE                          ,ADMA Descriptor Error" "0: ADMADCE_0,1: ADMADCE_1"
textline "                               "
bitfld.long 0x00 2. " ADMALME                          ,ADMA Length Mismatch Error" "0: ADMALME_0,1: ADMALME_1"
textline "                               "
bitfld.long 0x00 0.--1. " ADMAES                           ,ADMA Error State (when ADMA Error is occurred)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
hexmask.long 0x00 2.--31. 1. " ADS_ADDR                         ,ADMA System Address"
group.long 0x60++0x03
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT          ,DLL_CTRL_REF_UPDATE_INT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT          ,DLL_CTRL_SLV_UPDATE_INT"
textline "                               "
bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET1         ,DLL_CTRL_SLV_DLY_TARGET1" "0,1,2,3,4,5,6,7"
textline "                               "
hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL        ,DLL_CTRL_SLV_OVERRIDE_VAL"
textline "                               "
bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE            ,DLL_CTRL_SLV_OVERRIDE" "0,1"
textline "                               "
bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE             ,DLL_CTRL_GATE_UPDATE" "0,1"
textline "                               "
bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET0         ,DLL_CTRL_SLV_DLY_TARGET0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD           ,DLL_CTRL_SLV_FORCE_UPD" "0,1"
textline "                               "
bitfld.long 0x00 1. " DLL_CTRL_RESET                   ,DLL_CTRL_RESET" "0,1"
textline "                               "
bitfld.long 0x00 0. " DLL_CTRL_ENABLE                  ,DLL_CTRL_ENABLE" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "DLL_STATUS,DLL Status"
hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL                  ,DLL_STS_REF_SEL"
textline "                               "
hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL                  ,DLL_STS_SLV_SEL"
textline "                               "
bitfld.long 0x00 1. " DLL_STS_REF_LOCK                 ,DLL_STS_REF_LOCK" "0,1"
textline "                               "
bitfld.long 0x00 0. " DLL_STS_SLV_LOCK                 ,DLL_STS_SLV_LOCK" "0,1"
group.long 0x68++0x03
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
rbitfld.long 0x00 31. " PRE_ERR                          ,PRE_ERR" "0,1"
textline "                               "
hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE                      ,TAP_SEL_PRE"
textline "                               "
rbitfld.long 0x00 20.--23. " TAP_SEL_OUT                      ,TAP_SEL_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 16.--19. " TAP_SEL_POST                     ,TAP_SEL_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 15. " NXT_ERR                          ,NXT_ERR" "0,1"
textline "                               "
hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE                 ,DLY_CELL_SET_PRE"
textline "                               "
bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT                 ,DLY_CELL_SET_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST                ,DLY_CELL_SET_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control"
bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT   ,Strobe DLL Control Reference Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT   ,Strobe DLL Control Slave Update Interval"
textline "                               "
hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL Control Slave Override Value"
textline "                               "
bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE     ,Strobe DLL Control Slave Override" "0,1"
textline "                               "
bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1    ,Strobe DLL Control Gate Update" "0,1"
textline "                               "
bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0    ,Strobe DLL Control Gate Update" "0,1"
textline "                               "
bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET   ,Strobe DLL Control Slave Delay Target" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD    ,Strobe DLL Control Slave Force Updated" "0,1"
textline "                               "
bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET            ,Strobe DLL Control Reset" "0,1"
textline "                               "
bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE           ,Strobe DLL Control Enable" "0,1"
rgroup.long 0x74++0x03
line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status"
hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL           ,Strobe DLL Status Reference Select"
textline "                               "
hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL           ,Strobe DLL Status Slave Select"
textline "                               "
bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK          ,Strobe DLL Status Reference Lock" "0,1"
textline "                               "
bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK          ,Strobe DLL Status Slave Lock" "0,1"
group.long 0xC0++0x03
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
bitfld.long 0x00 31. " CMD_BYTE_EN                      ,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
textline "                               "
bitfld.long 0x00 15. " CRC_CHK_DIS                      ,CRC Check Disable" "0: Check CRC16 for every read data packet and check CRC bits for every write data packet,1: Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet"
textline "                               "
bitfld.long 0x00 8. " FRC_SDCLK_ON                     ,Force CLK" "0: CLK active or inactive is fully controlled by the hardware,1: Force CLK active"
textline "                               "
bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN               ,Check busy enable" "0: Do not check busy after auto CMD12 for write data packet,1: Check busy after auto CMD12 for write data packet"
textline "                               "
bitfld.long 0x00 1. " VSELECT                          ,Voltage selection" "0: Change the voltage to high voltage range. around 3.0 V,1: Change the voltage to low voltage range. around 1.8 V"
group.long 0xC4++0x03
line.long 0x00 "MMC_BOOT,MMC Boot Register"
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT                     ,BOOT_BLK_CNT"
textline "                               "
bitfld.long 0x00 8. " DISABLE_TIME_OUT                 ,Disable Time Out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
textline "                               "
bitfld.long 0x00 7. " AUTO_SABG_EN                     ,AUTO_SABG_EN" "0,1"
textline "                               "
bitfld.long 0x00 6. " BOOT_EN                          ,BOOT_EN" "0: Fast boot disable,1: Fast boot enable"
textline "                               "
bitfld.long 0x00 5. " BOOT_MODE                        ,BOOT_MODE" "0: BOOT_MODE_0,1: Alternative boot"
textline "                               "
bitfld.long 0x00 4. " BOOT_ACK                         ,BOOT_ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
textline "                               "
bitfld.long 0x00 0.--3. " DTOCV_ACK                        ,DTOCV_ACK" "0: SDCLK x 2^14,1: SDCLK x 2^15,2: SDCLK x 2^16,3: SDCLK x 2^17,4: SDCLK x 2^18,5: SDCLK x 2^19,6: SDCLK x 2^20,7: SDCLK x 2^21,,,,,,,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
group.long 0xC8++0x03
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
bitfld.long 0x00 14. " AHB_RST                          ,AHB BUS reset" "0,1"
textline "                               "
bitfld.long 0x00 12. " ACMD23_ARGU2_EN                  ,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing with SDMA system address register"
textline "                               "
bitfld.long 0x00 11. " HS400_RD_CLK_STOP_EN             ,HS400 Read Clock Stop Enable" "0,1"
textline "                               "
bitfld.long 0x00 10. " HS400_WR_CLK_STOP_EN             ,HS400 Write Clock Stop Enable" "0,1"
textline "                               "
bitfld.long 0x00 6. " TUNING_CMD_EN                    ,TUNING_CMD_EN" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
textline "                               "
bitfld.long 0x00 5. " TUNING_1bit_EN                   ,TUNING_1bit_EN" "0,1"
textline "                               "
bitfld.long 0x00 4. " TUNING_8bit_EN                   ,TUNING_8bit_EN" "0,1"
textline "                               "
bitfld.long 0x00 3. " CARD_INT_D3_TEST                 ,Card Interrupt Detection Test" "0: Check the card interrupt only when DATA3 is high,1: Check the card interrupt by ignoring the status of DATA3"
group.long 0xCC++0x03
line.long 0x00 "TUNING_CTRL,Tuning Control Register"
bitfld.long 0x00 24. " STD_TUNING_EN                    ,STD_TUNING_EN" "0,1"
textline "                               "
bitfld.long 0x00 20.--22. " TUNING_WINDOW                    ,TUNING_WINDOW" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 16.--18. " TUNING_STEP                      ,TUNING_STEP" "0,1,2,3,4,5,6,7"
textline "                               "
hexmask.long.byte 0x00 8.--15. 1. " TUNING_COUNTER                   ,TUNING_COUNTER"
textline "                               "
hexmask.long.byte 0x00 0.--7. 1. " TUNING_START_TAP                 ,TUNING_START_TAP"
width 0x0B
tree.end
tree "USDHC1"
base ad:0x40137000
width 22.
group.long 0x00++0x03
line.long 0x00 "DS_ADDR,DMA System Address"
hexmask.long 0x00 0.--31. 1. " DS_ADDR                          ,DS_ADDR"
group.long 0x04++0x03
line.long 0x00 "BLK_ATT,Block Attributes"
hexmask.long.word 0x00 16.--31. 1. " BLKCNT                           ,Block Count"
textline "                               "
hexmask.long.word 0x00 0.--12. 1. " BLKSIZE                          ,Block Size"
group.long 0x08++0x03
line.long 0x00 "CMD_ARG,Command Argument"
hexmask.long 0x00 0.--31. 1. " CMDARG                           ,Command Argument"
group.long 0x0C++0x03
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
bitfld.long 0x00 24.--29. " CMDINX                           ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                               "
bitfld.long 0x00 22.--23. " CMDTYP                           ,Command Type" "0: Normal Other commands,1: Suspend CMD52 for writing Bus Suspend in CCCR,2: Resume CMD52 for writing Function Select in CCCR,3: Abort CMD12. CMD52 for writing I/O Abort in CCCR"
textline "                               "
bitfld.long 0x00 21. " DPSEL                            ,Data Present Select" "0: No Data Present,1: Data Present"
textline "                               "
bitfld.long 0x00 20. " CICEN                            ,Command Index Check Enable" "0: CICEN_0,1: CICEN_1"
textline "                               "
bitfld.long 0x00 19. " CCCEN                            ,Command CRC Check Enable" "0: CCCEN_0,1: CCCEN_1"
textline "                               "
bitfld.long 0x00 16.--17. " RSPTYP                           ,Response Type Select" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48. check Busy after response"
rgroup.long 0x10++0x03
line.long 0x00 "CMD_RSP0,Command Response0"
hexmask.long 0x00 0.--31. 1. " CMDRSP0                          ,Command Response 0"
rgroup.long 0x14++0x03
line.long 0x00 "CMD_RSP1,Command Response1"
hexmask.long 0x00 0.--31. 1. " CMDRSP1                          ,Command Response 1"
rgroup.long 0x18++0x03
line.long 0x00 "CMD_RSP2,Command Response2"
hexmask.long 0x00 0.--31. 1. " CMDRSP2                          ,Command Response 2"
rgroup.long 0x1C++0x03
line.long 0x00 "CMD_RSP3,Command Response3"
hexmask.long 0x00 0.--31. 1. " CMDRSP3                          ,Command Response 3"
group.long 0x20++0x03
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
hexmask.long 0x00 0.--31. 1. " DATCONT                          ,Data Content"
rgroup.long 0x24++0x03
line.long 0x00 "PRES_STATE,Present State"
hexmask.long.byte 0x00 24.--31. 1. " DLSL                             ,DATA[7:0] Line Signal Level"
textline "                               "
bitfld.long 0x00 23. " CLSL                             ,CMD Line Signal Level" "0,1"
textline "                               "
bitfld.long 0x00 19. " WPSPL                            ,Write Protect Switch Pin Level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
textline "                               "
bitfld.long 0x00 18. " CDPL                             ,Card Detect Pin Level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
textline "                               "
bitfld.long 0x00 16. " CINST                            ,Card Inserted" "0: Power on Reset or No Card,1: Card Inserted"
textline "                               "
bitfld.long 0x00 15. " TSCD                             ,Tape Select Change Done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
textline "                               "
bitfld.long 0x00 12. " RTR                              ,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
textline "                               "
bitfld.long 0x00 11. " BREN                             ,Buffer Read Enable" "0: Read disable,1: Read enable"
textline "                               "
bitfld.long 0x00 10. " BWEN                             ,Buffer Write Enable" "0: Write disable,1: Write enable"
textline "                               "
bitfld.long 0x00 9. " RTA                              ,Read Transfer Active" "0: No valid data,1: Transferring data"
textline "                               "
bitfld.long 0x00 8. " WTA                              ,Write Transfer Active" "0: No valid data,1: Transferring data"
textline "                               "
bitfld.long 0x00 7. " SDOFF                            ,SD Clock Gated Off Internally" "0: SD Clock is active,1: SD Clock is gated off"
textline "                               "
bitfld.long 0x00 6. " PEROFF                           ,IPG_PERCLK Gated Off Internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
textline "                               "
bitfld.long 0x00 5. " HCKOFF                           ,HCLK Gated Off Internally" "0: HCLK is active,1: HCLK is gated off"
textline "                               "
bitfld.long 0x00 4. " IPGOFF                           ,IPG_CLK Gated Off Internally" "0: IPG_CLK is active,1: IPG_CLK is gated off"
textline "                               "
bitfld.long 0x00 3. " SDSTB                            ,SD Clock Stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
textline "                               "
bitfld.long 0x00 2. " DLA                              ,Data Line Active" "0: DATA Line Inactive,1: DATA Line Active"
textline "                               "
bitfld.long 0x00 1. " CDIHB                            ,Command Inhibit (DATA)" "0: Can issue command which uses the DATA line,1: Cannot issue command which uses the DATA line"
textline "                               "
bitfld.long 0x00 0. " CIHB                             ,Command Inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
group.long 0x28++0x03
line.long 0x00 "PROT_CTRL,Protocol Control"
bitfld.long 0x00 31. " RD_NO8CLK_EN                     ,RD_NO8CLK_EN" "0: Disable S/W RD_DONE_NO_8CLK. uSHDC determines if 8 clocks are needed automatically,1: S/W RD_DONE_NO_8CLK is enabled"
textline "                               "
bitfld.long 0x00 30. " NON_EXACT_BLK_RD                 ,NON_EXACT_BLK_RD" "0: The block read is exact block read,1: The block read is non-exact block read"
textline "                               "
bitfld.long 0x00 27.--29. " BURST_LEN_EN                     ,BURST length enable for INCR. INCR4 / INCR8 / INCR16. INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" ",1: Burst length is enabled for INCR,,3: Burst length is enabled for INCR,,5: Burst length is enabled for INCR,,7: Burst length is enabled for INCR"
textline "                               "
bitfld.long 0x00 26. " WECRM                            ,Wakeup Event Enable On SD Card Removal" "0: WECRM_0,1: WECRM_1"
textline "                               "
bitfld.long 0x00 25. " WECINS                           ,Wakeup Event Enable On SD Card Insertion" "0: WECINS_0,1: WECINS_1"
textline "                               "
bitfld.long 0x00 24. " WECINT                           ,Wakeup Event Enable On Card Interrupt" "0: WECINT_0,1: WECINT_1"
textline "                               "
bitfld.long 0x00 21.--23. " RD_WAIT_POINT                    ,Read wait point" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 20. " RD_DONE_NO_8CLK                  ,RD_DONE_NO_8CLK" "0,1"
textline "                               "
bitfld.long 0x00 19. " IABG                             ,Interrupt At Block Gap" "0: Disabled,1: Enabled"
textline "                               "
bitfld.long 0x00 18. " RWCTL                            ,Read Wait Control" "0: Disable Read Wait Control. and stop SD Clock at block gap when SABGREQ bit is set,1: Enable Read Wait Control. and assert Read Wait without stopping SD Clock at block gap when SABGREQ b.."
textline "                               "
bitfld.long 0x00 17. " CREQ                             ,Continue Request" "0: No effect,1: Restart"
textline "                               "
bitfld.long 0x00 16. " SABGREQ                          ,Stop At Block Gap Request" "0: SABGREQ_0,1: SABGREQ_1"
textline "                               "
bitfld.long 0x00 8.--9. " DMASEL                           ,DMA Select" "0: No DMA or Simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,"
textline "                               "
bitfld.long 0x00 7. " CDSS                             ,Card Detect Signal Selection" "0: Card Detection Level is selected (for normal purpose),1: Card Detection Test Level is selected (for test purpose)"
textline "                               "
bitfld.long 0x00 6. " CDTL                             ,Card Detect Test Level" "0: Card Detect Test Level is 0. no card inserted,1: Card Detect Test Level is 1. card inserted"
textline "                               "
bitfld.long 0x00 4.--5. " EMODE                            ,Endian Mode" "0: Big Endian Mode,1: Half Word Big Endian Mode,2: Little Endian Mode,"
textline "                               "
bitfld.long 0x00 3. " D3CD                             ,DATA3 as Card Detection Pin" "0: DATA3 does not monitor Card Insertion,1: DATA3 as Card Detection Pin"
textline "                               "
bitfld.long 0x00 1.--2. " DTW                              ,Data Transfer Width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,"
group.long 0x2C++0x03
line.long 0x00 "SYS_CTRL,System Control"
bitfld.long 0x00 28. " RSTT                             ,Reset Tuning" "0,1"
textline "                               "
bitfld.long 0x00 27. " INITA                            ,Initialization Active" "0,1"
textline "                               "
bitfld.long 0x00 26. " RSTD                             ,Software Reset For DATA Line" "0: No Reset,1: RSTD_1"
textline "                               "
bitfld.long 0x00 25. " RSTC                             ,Software Reset For CMD Line" "0: No Reset,1: RSTC_1"
textline "                               "
bitfld.long 0x00 24. " RSTA                             ,Software Reset For ALL" "0: No Reset,1: RSTA_1"
textline "                               "
bitfld.long 0x00 23. " IPP_RST_N                        ,IPP_RST_N" "0,1"
textline "                               "
bitfld.long 0x00 16.--19. " DTOCV                            ,Data Timeout Counter Value" "0: SDCLK x 2 14,1: SDCLK x 2 15,,,,,,,,,,,,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29"
textline "                               "
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS                          ,SDCLK Frequency Select"
textline "                               "
bitfld.long 0x00 4.--7. " DVS                              ,Divisor" "0: Divide-by-1,1: Divide-by-2,,,,,,,,,,,,,14: Divide-by-15,15: Divide-by-16"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
eventfld.long 0x00 28. " DMAE                             ,DMA Error" "0: No Error,1: DMAE_1"
textline "                               "
eventfld.long 0x00 26. " TNE                              ,Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
textline "                               "
eventfld.long 0x00 24. " AC12E                            ,Auto CMD12 Error" "0: No Error,1: AC12E_1"
textline "                               "
eventfld.long 0x00 22. " DEBE                             ,Data End Bit Error" "0: No Error,1: DEBE_1"
textline "                               "
eventfld.long 0x00 21. " DCE                              ,Data CRC Error" "0: No Error,1: DCE_1"
textline "                               "
eventfld.long 0x00 20. " DTOE                             ,Data Timeout Error" "0: No Error,1: Time out"
textline "                               "
eventfld.long 0x00 19. " CIE                              ,Command Index Error" "0: No Error,1: CIE_1"
textline "                               "
eventfld.long 0x00 18. " CEBE                             ,Command End Bit Error" "0: No Error,1: End Bit Error Generated"
textline "                               "
eventfld.long 0x00 17. " CCE                              ,Command CRC Error" "0: No Error,1: CRC Error Generated"
textline "                               "
eventfld.long 0x00 16. " CTOE                             ,Command Timeout Error" "0: No Error,1: Time out"
textline "                               "
eventfld.long 0x00 14. " TP                               ,Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
textline "                               "
eventfld.long 0x00 12. " RTE                              ,Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-Tuning is not required,1: Re-Tuning should be performed"
textline "                               "
eventfld.long 0x00 8. " CINT                             ,Card Interrupt" "0: No Card Interrupt,1: Generate Card Interrupt"
textline "                               "
eventfld.long 0x00 7. " CRM                              ,Card Removal" "0: Card state unstable or inserted,1: Card removed"
textline "                               "
eventfld.long 0x00 6. " CINS                             ,Card Insertion" "0: Card state unstable or removed,1: Card inserted"
textline "                               "
eventfld.long 0x00 5. " BRR                              ,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
textline "                               "
eventfld.long 0x00 4. " BWR                              ,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer:"
textline "                               "
eventfld.long 0x00 3. " DINT                             ,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
textline "                               "
eventfld.long 0x00 2. " BGE                              ,Block Gap Event" "0: No block gap event,1: Transaction stopped at block gap"
textline "                               "
eventfld.long 0x00 1. " TC                               ,Transfer Complete" "0: Transfer not complete,1: Transfer complete"
textline "                               "
eventfld.long 0x00 0. " CC                               ,Command Complete" "0: Command not complete,1: Command complete"
group.long 0x34++0x03
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
bitfld.long 0x00 28. " DMAESEN                          ,DMA Error Status Enable" "0: DMAESEN_0,1: DMAESEN_1"
textline "                               "
bitfld.long 0x00 26. " TNESEN                           ,Tuning Error Status Enable" "0: TNESEN_0,1: TNESEN_1"
textline "                               "
bitfld.long 0x00 24. " AC12ESEN                         ,Auto CMD12 Error Status Enable" "0: AC12ESEN_0,1: AC12ESEN_1"
textline "                               "
bitfld.long 0x00 22. " DEBESEN                          ,Data End Bit Error Status Enable" "0: DEBESEN_0,1: DEBESEN_1"
textline "                               "
bitfld.long 0x00 21. " DCESEN                           ,Data CRC Error Status Enable" "0: DCESEN_0,1: DCESEN_1"
textline "                               "
bitfld.long 0x00 20. " DTOESEN                          ,Data Timeout Error Status Enable" "0: DTOESEN_0,1: DTOESEN_1"
textline "                               "
bitfld.long 0x00 19. " CIESEN                           ,Command Index Error Status Enable" "0: CIESEN_0,1: CIESEN_1"
textline "                               "
bitfld.long 0x00 18. " CEBESEN                          ,Command End Bit Error Status Enable" "0: CEBESEN_0,1: CEBESEN_1"
textline "                               "
bitfld.long 0x00 17. " CCESEN                           ,Command CRC Error Status Enable" "0: CCESEN_0,1: CCESEN_1"
textline "                               "
bitfld.long 0x00 16. " CTOESEN                          ,Command Timeout Error Status Enable" "0: CTOESEN_0,1: CTOESEN_1"
textline "                               "
bitfld.long 0x00 14. " TPSEN                            ,Tuning Pass Status Enable" "0: TPSEN_0,1: TPSEN_1"
textline "                               "
bitfld.long 0x00 12. " RTESEN                           ,Re-Tuning Event Status Enable" "0: RTESEN_0,1: RTESEN_1"
textline "                               "
bitfld.long 0x00 8. " CINTSEN                          ,Card Interrupt Status Enable" "0: CINTSEN_0,1: CINTSEN_1"
textline "                               "
bitfld.long 0x00 7. " CRMSEN                           ,Card Removal Status Enable" "0: CRMSEN_0,1: CRMSEN_1"
textline "                               "
bitfld.long 0x00 6. " CINSSEN                          ,Card Insertion Status Enable" "0: CINSSEN_0,1: CINSSEN_1"
textline "                               "
bitfld.long 0x00 5. " BRRSEN                           ,Buffer Read Ready Status Enable" "0: BRRSEN_0,1: BRRSEN_1"
textline "                               "
bitfld.long 0x00 4. " BWRSEN                           ,Buffer Write Ready Status Enable" "0: BWRSEN_0,1: BWRSEN_1"
textline "                               "
bitfld.long 0x00 3. " DINTSEN                          ,DMA Interrupt Status Enable" "0: DINTSEN_0,1: DINTSEN_1"
textline "                               "
bitfld.long 0x00 2. " BGESEN                           ,Block Gap Event Status Enable" "0: BGESEN_0,1: BGESEN_1"
textline "                               "
bitfld.long 0x00 1. " TCSEN                            ,Transfer Complete Status Enable" "0: TCSEN_0,1: TCSEN_1"
textline "                               "
bitfld.long 0x00 0. " CCSEN                            ,Command Complete Status Enable" "0: CCSEN_0,1: CCSEN_1"
group.long 0x38++0x03
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
bitfld.long 0x00 28. " DMAEIEN                          ,DMA Error Interrupt Enable" "0: DMAEIEN_0,1: DMAEIEN_1"
textline "                               "
bitfld.long 0x00 26. " TNEIEN                           ,Tuning Error Interrupt Enable" "0: TNEIEN_0,1: TNEIEN_1"
textline "                               "
bitfld.long 0x00 24. " AC12EIEN                         ,Auto CMD12 Error Interrupt Enable" "0: AC12EIEN_0,1: AC12EIEN_1"
textline "                               "
bitfld.long 0x00 22. " DEBEIEN                          ,Data End Bit Error Interrupt Enable" "0: DEBEIEN_0,1: DEBEIEN_1"
textline "                               "
bitfld.long 0x00 21. " DCEIEN                           ,Data CRC Error Interrupt Enable" "0: DCEIEN_0,1: DCEIEN_1"
textline "                               "
bitfld.long 0x00 20. " DTOEIEN                          ,Data Timeout Error Interrupt Enable" "0: DTOEIEN_0,1: DTOEIEN_1"
textline "                               "
bitfld.long 0x00 19. " CIEIEN                           ,Command Index Error Interrupt Enable" "0: CIEIEN_0,1: CIEIEN_1"
textline "                               "
bitfld.long 0x00 18. " CEBEIEN                          ,Command End Bit Error Interrupt Enable" "0: CEBEIEN_0,1: CEBEIEN_1"
textline "                               "
bitfld.long 0x00 17. " CCEIEN                           ,Command CRC Error Interrupt Enable" "0: CCEIEN_0,1: CCEIEN_1"
textline "                               "
bitfld.long 0x00 16. " CTOEIEN                          ,Command Timeout Error Interrupt Enable" "0: CTOEIEN_0,1: CTOEIEN_1"
textline "                               "
bitfld.long 0x00 14. " TPIEN                            ,Tuning Pass Interrupt Enable" "0: TPIEN_0,1: TPIEN_1"
textline "                               "
bitfld.long 0x00 12. " RTEIEN                           ,Re-Tuning Event Interrupt Enable" "0: RTEIEN_0,1: RTEIEN_1"
textline "                               "
bitfld.long 0x00 8. " CINTIEN                          ,Card Interrupt Interrupt Enable" "0: CINTIEN_0,1: CINTIEN_1"
textline "                               "
bitfld.long 0x00 7. " CRMIEN                           ,Card Removal Interrupt Enable" "0: CRMIEN_0,1: CRMIEN_1"
textline "                               "
bitfld.long 0x00 6. " CINSIEN                          ,Card Insertion Interrupt Enable" "0: CINSIEN_0,1: CINSIEN_1"
textline "                               "
bitfld.long 0x00 5. " BRRIEN                           ,Buffer Read Ready Interrupt Enable" "0: BRRIEN_0,1: BRRIEN_1"
textline "                               "
bitfld.long 0x00 4. " BWRIEN                           ,Buffer Write Ready Interrupt Enable" "0: BWRIEN_0,1: BWRIEN_1"
textline "                               "
bitfld.long 0x00 3. " DINTIEN                          ,DMA Interrupt Enable" "0: DINTIEN_0,1: DINTIEN_1"
textline "                               "
bitfld.long 0x00 2. " BGEIEN                           ,Block Gap Event Interrupt Enable" "0: BGEIEN_0,1: BGEIEN_1"
textline "                               "
bitfld.long 0x00 1. " TCIEN                            ,Transfer Complete Interrupt Enable" "0: TCIEN_0,1: TCIEN_1"
textline "                               "
bitfld.long 0x00 0. " CCIEN                            ,Command Complete Interrupt Enable" "0: CCIEN_0,1: CCIEN_1"
group.long 0x3C++0x03
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
bitfld.long 0x00 23. " SMP_CLK_SEL                      ,Sample Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
textline "                               "
bitfld.long 0x00 22. " EXECUTE_TUNING                   ,Execute Tuning" "0,1"
textline "                               "
rbitfld.long 0x00 7. " CNIBAC12E                        ,Command Not Issued By Auto CMD12 Error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
textline "                               "
rbitfld.long 0x00 4. " AC12IE                           ,Auto CMD12 / 23 Index Error" "0: AC12IE_0,1: Error. the CMD index in response is not CMD12/23"
textline "                               "
rbitfld.long 0x00 3. " AC12CE                           ,Auto CMD12 / 23 CRC Error" "0: No CRC error,1: CRC Error Met in Auto CMD12/23 Response"
textline "                               "
rbitfld.long 0x00 2. " AC12EBE                          ,Auto CMD12 / 23 End Bit Error" "0: AC12EBE_0,1: End Bit Error Generated"
textline "                               "
rbitfld.long 0x00 1. " AC12TOE                          ,Auto CMD12 / 23 Timeout Error" "0: AC12TOE_0,1: AC12TOE_1"
textline "                               "
rbitfld.long 0x00 0. " AC12NE                           ,Auto CMD12 Not Executed" "0: AC12NE_0,1: Not executed"
group.long 0x40++0x03
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
rbitfld.long 0x00 26. " VS18                             ,Voltage Support 1.8 V" "0: 1.8V not supported,1: 1.8V supported"
textline "                               "
rbitfld.long 0x00 25. " VS30                             ,Voltage Support 3.0 V" "0: 3.0V not supported,1: 3.0V supported"
textline "                               "
rbitfld.long 0x00 24. " VS33                             ,Voltage Support 3.3V" "0: 3.3V not supported,1: 3.3V supported"
textline "                               "
rbitfld.long 0x00 23. " SRS                              ,Suspend / Resume Support" "0: Not supported,1: Supported"
textline "                               "
rbitfld.long 0x00 22. " DMAS                             ,DMA Support" "0: DMA not supported,1: DMA Supported"
textline "                               "
rbitfld.long 0x00 21. " HSS                              ,High Speed Support" "0: High Speed Not Supported,1: High Speed Supported"
textline "                               "
rbitfld.long 0x00 20. " ADMAS                            ,ADMA Support" "0: Advanced DMA Not supported,1: Advanced DMA Supported"
textline "                               "
rbitfld.long 0x00 16.--18. " MBL                              ,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,,,,"
textline "                               "
rbitfld.long 0x00 14.--15. " RETUNING_MODE                    ,Retuning Mode" "0: RETUNING_MODE_0,1: RETUNING_MODE_1,2: RETUNING_MODE_2,"
textline "                               "
bitfld.long 0x00 13. " USE_TUNING_SDR50                 ,Use Tuning for SDR50" "0: SDR does not require tuning,1: SDR50 requires tuning"
textline "                               "
bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING              ,Time Counter for Retuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 2. " DDR50_SUPPORT                    ,DDR50 support" "0,1"
textline "                               "
rbitfld.long 0x00 1. " SDR104_SUPPORT                   ,SDR104 support" "0,1"
textline "                               "
rbitfld.long 0x00 0. " SDR50_SUPPORT                    ,SDR50 support" "0,1"
group.long 0x44++0x03
line.long 0x00 "WTMK_LVL,Watermark Level"
bitfld.long 0x00 24.--28. " WR_BRST_LEN                      ,Write Burst Length Due to system restriction. the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                               "
hexmask.long.byte 0x00 16.--23. 1. " WR_WML                           ,Write Watermark Level"
textline "                               "
bitfld.long 0x00 8.--12. " RD_BRST_LEN                      ,Read Burst Length Due to system restriction. the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                               "
hexmask.long.byte 0x00 0.--7. 1. " RD_WML                           ,Read Watermark Level"
group.long 0x48++0x03
line.long 0x00 "MIX_CTRL,Mixer Control"
bitfld.long 0x00 26. " HS400_MODE                       ,Enable HS400 Mode" "0,1"
textline "                               "
bitfld.long 0x00 25. " FBCLK_SEL                        ,Feedback Clock Source Selection (Only used for SD3.0. SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
textline "                               "
bitfld.long 0x00 24. " AUTO_TUNE_EN                     ,Auto Tuning Enable (Only used for SD3.0. SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
textline "                               "
bitfld.long 0x00 23. " SMP_CLK_SEL                      ,SMP_CLK_SEL" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
textline "                               "
bitfld.long 0x00 22. " EXE_TUNE                         ,Execute Tuning: (Only used for SD3.0. SDR104 mode and EMMC HS200 mode)" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
textline "                               "
bitfld.long 0x00 7. " AC23EN                           ,Auto CMD23 Enable" "0,1"
textline "                               "
bitfld.long 0x00 6. " NIBBLE_POS                       ,NIBBLE_POS" "0,1"
textline "                               "
bitfld.long 0x00 5. " MSBSEL                           ,Multi / Single Block Select" "0: Single Block,1: Multiple Blocks"
textline "                               "
bitfld.long 0x00 4. " DTDSEL                           ,Data Transfer Direction Select" "0: Write (Host to Card),1: Read (Card to Host)"
textline "                               "
bitfld.long 0x00 3. " DDR_EN                           ,Dual Data Rate mode selection" "0,1"
textline "                               "
bitfld.long 0x00 2. " AC12EN                           ,Auto CMD12 Enable" "0: AC12EN_0,1: AC12EN_1"
textline "                               "
bitfld.long 0x00 1. " BCEN                             ,Block Count Enable" "0: Disable,1: BCEN_1"
textline "                               "
bitfld.long 0x00 0. " DMAEN                            ,DMA Enable" "0: DMAEN_0,1: DMAEN_1"
group.long 0x50++0x03
line.long 0x00 "FORCE_EVENT,Force Event"
bitfld.long 0x00 31. " FEVTCINT                         ,Force Event Card Interrupt" "0,1"
textline "                               "
bitfld.long 0x00 28. " FEVTDMAE                         ,Force Event DMA Error" "0,1"
textline "                               "
bitfld.long 0x00 26. " FEVTTNE                          ,Force Tuning Error" "0,1"
textline "                               "
bitfld.long 0x00 24. " FEVTAC12E                        ,Force Event Auto Command 12 Error" "0,1"
textline "                               "
bitfld.long 0x00 22. " FEVTDEBE                         ,Force Event Data End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 21. " FEVTDCE                          ,Force Event Data CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 20. " FEVTDTOE                         ,Force Event Data Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 19. " FEVTCIE                          ,Force Event Command Index Error" "0,1"
textline "                               "
bitfld.long 0x00 18. " FEVTCEBE                         ,Force Event Command End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 17. " FEVTCCE                          ,Force Event Command CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 16. " FEVTCTOE                         ,Force Event Command Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 7. " FEVTCNIBAC12E                    ,Force Event Command Not Executed By Auto Command 12 Error" "0,1"
textline "                               "
bitfld.long 0x00 4. " FEVTAC12IE                       ,Force Event Auto Command 12 Index Error" "0,1"
textline "                               "
bitfld.long 0x00 3. " FEVTAC12EBE                      ,Force Event Auto Command 12 End Bit Error" "0,1"
textline "                               "
bitfld.long 0x00 2. " FEVTAC12CE                       ,Force Event Auto Command 12 CRC Error" "0,1"
textline "                               "
bitfld.long 0x00 1. " FEVTAC12TOE                      ,Force Event Auto Command 12 Time Out Error" "0,1"
textline "                               "
bitfld.long 0x00 0. " FEVTAC12NE                       ,Force Event Auto Command 12 Not Executed" "0,1"
rgroup.long 0x54++0x03
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register"
bitfld.long 0x00 3. " ADMADCE                          ,ADMA Descriptor Error" "0: ADMADCE_0,1: ADMADCE_1"
textline "                               "
bitfld.long 0x00 2. " ADMALME                          ,ADMA Length Mismatch Error" "0: ADMALME_0,1: ADMALME_1"
textline "                               "
bitfld.long 0x00 0.--1. " ADMAES                           ,ADMA Error State (when ADMA Error is occurred)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
hexmask.long 0x00 2.--31. 1. " ADS_ADDR                         ,ADMA System Address"
group.long 0x60++0x03
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT          ,DLL_CTRL_REF_UPDATE_INT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT          ,DLL_CTRL_SLV_UPDATE_INT"
textline "                               "
bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET1         ,DLL_CTRL_SLV_DLY_TARGET1" "0,1,2,3,4,5,6,7"
textline "                               "
hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL        ,DLL_CTRL_SLV_OVERRIDE_VAL"
textline "                               "
bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE            ,DLL_CTRL_SLV_OVERRIDE" "0,1"
textline "                               "
bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE             ,DLL_CTRL_GATE_UPDATE" "0,1"
textline "                               "
bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET0         ,DLL_CTRL_SLV_DLY_TARGET0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD           ,DLL_CTRL_SLV_FORCE_UPD" "0,1"
textline "                               "
bitfld.long 0x00 1. " DLL_CTRL_RESET                   ,DLL_CTRL_RESET" "0,1"
textline "                               "
bitfld.long 0x00 0. " DLL_CTRL_ENABLE                  ,DLL_CTRL_ENABLE" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "DLL_STATUS,DLL Status"
hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL                  ,DLL_STS_REF_SEL"
textline "                               "
hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL                  ,DLL_STS_SLV_SEL"
textline "                               "
bitfld.long 0x00 1. " DLL_STS_REF_LOCK                 ,DLL_STS_REF_LOCK" "0,1"
textline "                               "
bitfld.long 0x00 0. " DLL_STS_SLV_LOCK                 ,DLL_STS_SLV_LOCK" "0,1"
group.long 0x68++0x03
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
rbitfld.long 0x00 31. " PRE_ERR                          ,PRE_ERR" "0,1"
textline "                               "
hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE                      ,TAP_SEL_PRE"
textline "                               "
rbitfld.long 0x00 20.--23. " TAP_SEL_OUT                      ,TAP_SEL_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 16.--19. " TAP_SEL_POST                     ,TAP_SEL_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
rbitfld.long 0x00 15. " NXT_ERR                          ,NXT_ERR" "0,1"
textline "                               "
hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE                 ,DLY_CELL_SET_PRE"
textline "                               "
bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT                 ,DLY_CELL_SET_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST                ,DLY_CELL_SET_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control"
bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT   ,Strobe DLL Control Reference Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT   ,Strobe DLL Control Slave Update Interval"
textline "                               "
hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL Control Slave Override Value"
textline "                               "
bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE     ,Strobe DLL Control Slave Override" "0,1"
textline "                               "
bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1    ,Strobe DLL Control Gate Update" "0,1"
textline "                               "
bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0    ,Strobe DLL Control Gate Update" "0,1"
textline "                               "
bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET   ,Strobe DLL Control Slave Delay Target" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD    ,Strobe DLL Control Slave Force Updated" "0,1"
textline "                               "
bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET            ,Strobe DLL Control Reset" "0,1"
textline "                               "
bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE           ,Strobe DLL Control Enable" "0,1"
rgroup.long 0x74++0x03
line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status"
hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL           ,Strobe DLL Status Reference Select"
textline "                               "
hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL           ,Strobe DLL Status Slave Select"
textline "                               "
bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK          ,Strobe DLL Status Reference Lock" "0,1"
textline "                               "
bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK          ,Strobe DLL Status Slave Lock" "0,1"
group.long 0xC0++0x03
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
bitfld.long 0x00 31. " CMD_BYTE_EN                      ,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
textline "                               "
bitfld.long 0x00 15. " CRC_CHK_DIS                      ,CRC Check Disable" "0: Check CRC16 for every read data packet and check CRC bits for every write data packet,1: Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet"
textline "                               "
bitfld.long 0x00 8. " FRC_SDCLK_ON                     ,Force CLK" "0: CLK active or inactive is fully controlled by the hardware,1: Force CLK active"
textline "                               "
bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN               ,Check busy enable" "0: Do not check busy after auto CMD12 for write data packet,1: Check busy after auto CMD12 for write data packet"
textline "                               "
bitfld.long 0x00 1. " VSELECT                          ,Voltage selection" "0: Change the voltage to high voltage range. around 3.0 V,1: Change the voltage to low voltage range. around 1.8 V"
group.long 0xC4++0x03
line.long 0x00 "MMC_BOOT,MMC Boot Register"
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT                     ,BOOT_BLK_CNT"
textline "                               "
bitfld.long 0x00 8. " DISABLE_TIME_OUT                 ,Disable Time Out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
textline "                               "
bitfld.long 0x00 7. " AUTO_SABG_EN                     ,AUTO_SABG_EN" "0,1"
textline "                               "
bitfld.long 0x00 6. " BOOT_EN                          ,BOOT_EN" "0: Fast boot disable,1: Fast boot enable"
textline "                               "
bitfld.long 0x00 5. " BOOT_MODE                        ,BOOT_MODE" "0: BOOT_MODE_0,1: Alternative boot"
textline "                               "
bitfld.long 0x00 4. " BOOT_ACK                         ,BOOT_ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
textline "                               "
bitfld.long 0x00 0.--3. " DTOCV_ACK                        ,DTOCV_ACK" "0: SDCLK x 2^14,1: SDCLK x 2^15,2: SDCLK x 2^16,3: SDCLK x 2^17,4: SDCLK x 2^18,5: SDCLK x 2^19,6: SDCLK x 2^20,7: SDCLK x 2^21,,,,,,,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
group.long 0xC8++0x03
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
bitfld.long 0x00 14. " AHB_RST                          ,AHB BUS reset" "0,1"
textline "                               "
bitfld.long 0x00 12. " ACMD23_ARGU2_EN                  ,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing with SDMA system address register"
textline "                               "
bitfld.long 0x00 11. " HS400_RD_CLK_STOP_EN             ,HS400 Read Clock Stop Enable" "0,1"
textline "                               "
bitfld.long 0x00 10. " HS400_WR_CLK_STOP_EN             ,HS400 Write Clock Stop Enable" "0,1"
textline "                               "
bitfld.long 0x00 6. " TUNING_CMD_EN                    ,TUNING_CMD_EN" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
textline "                               "
bitfld.long 0x00 5. " TUNING_1bit_EN                   ,TUNING_1bit_EN" "0,1"
textline "                               "
bitfld.long 0x00 4. " TUNING_8bit_EN                   ,TUNING_8bit_EN" "0,1"
textline "                               "
bitfld.long 0x00 3. " CARD_INT_D3_TEST                 ,Card Interrupt Detection Test" "0: Check the card interrupt only when DATA3 is high,1: Check the card interrupt by ignoring the status of DATA3"
group.long 0xCC++0x03
line.long 0x00 "TUNING_CTRL,Tuning Control Register"
bitfld.long 0x00 24. " STD_TUNING_EN                    ,STD_TUNING_EN" "0,1"
textline "                               "
bitfld.long 0x00 20.--22. " TUNING_WINDOW                    ,TUNING_WINDOW" "0,1,2,3,4,5,6,7"
textline "                               "
bitfld.long 0x00 16.--18. " TUNING_STEP                      ,TUNING_STEP" "0,1,2,3,4,5,6,7"
textline "                               "
hexmask.long.byte 0x00 8.--15. 1. " TUNING_COUNTER                   ,TUNING_COUNTER"
textline "                               "
hexmask.long.byte 0x00 0.--7. 1. " TUNING_START_TAP                 ,TUNING_START_TAP"
width 0x0B
tree.end
tree.end
tree "UTICK"
tree "UTICK0"
base ad:0x4000F000
width 8.
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register"
bitfld.long 0x00 31. " REPEAT    ,Repeat delay" "0,1"
textline "                 "
hexmask.long 0x00 0.--30. 1. " DELAYVAL  ,Tick interval value"
group.long 0x04++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 1. " ACTIVE    ,Active flag" "0,1"
textline "                 "
bitfld.long 0x00 0. " INTR      ,Interrupt flag" "0,1"
group.long 0x08++0x03
line.long 0x00 "CFG,Capture configuration register"
bitfld.long 0x00 11. " CAPPOL3   ,Capture Polarity 3" "0,1"
textline "                 "
bitfld.long 0x00 10. " CAPPOL2   ,Capture Polarity 2" "0,1"
textline "                 "
bitfld.long 0x00 9. " CAPPOL1   ,Capture Polarity 1" "0,1"
textline "                 "
bitfld.long 0x00 8. " CAPPOL0   ,Capture Polarity 0" "0,1"
textline "                 "
bitfld.long 0x00 3. " CAPEN3    ,Enable Capture 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " CAPEN2    ,Enable Capture 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAPEN1    ,Enable Capture 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " CAPEN0    ,Enable Capture 0" "0,1"
wgroup.long 0x0C++0x03
line.long 0x00 "CAPCLR,Capture clear register"
bitfld.long 0x00 3. " CAPCLR3   ,Clear capture 3" "0,1"
textline "                 "
bitfld.long 0x00 2. " CAPCLR2   ,Clear capture 2" "0,1"
textline "                 "
bitfld.long 0x00 1. " CAPCLR1   ,Clear capture 1" "0,1"
textline "                 "
bitfld.long 0x00 0. " CAPCLR0   ,Clear capture 0" "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "CAP[0],Capture register"
bitfld.long 0x00 31. " VALID     ,Capture Valid" "0,1"
textline "                 "
hexmask.long 0x00 0.--30. 1. " CAP_VALUE ,Capture value for the related capture event (UTICK_CAPn"
rgroup.long 0x14++0x03
line.long 0x00 "CAP[1],Capture register"
bitfld.long 0x00 31. " VALID     ,Capture Valid" "0,1"
textline "                 "
hexmask.long 0x00 0.--30. 1. " CAP_VALUE ,Capture value for the related capture event (UTICK_CAPn"
rgroup.long 0x18++0x03
line.long 0x00 "CAP[2],Capture register"
bitfld.long 0x00 31. " VALID     ,Capture Valid" "0,1"
textline "                 "
hexmask.long 0x00 0.--30. 1. " CAP_VALUE ,Capture value for the related capture event (UTICK_CAPn"
rgroup.long 0x1C++0x03
line.long 0x00 "CAP[3],Capture register"
bitfld.long 0x00 31. " VALID     ,Capture Valid" "0,1"
textline "                 "
hexmask.long 0x00 0.--30. 1. " CAP_VALUE ,Capture value for the related capture event (UTICK_CAPn"
width 0x0B
tree.end
tree.end
tree "WWDT"
tree "WWDT0"
base ad:0x4000E000
width 9.
group.long 0x00++0x03
line.long 0x00 "MOD,Watchdog mode register"
bitfld.long 0x00 5. " LOCK      ,Once this bit is set to one and a watchdog feed is performed. disabling or powering down the watchdo.." "0,1"
textline "                  "
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "0: FLEXIBLE,1: THRESHOLD"
textline "                  "
bitfld.long 0x00 3. " WDINT     ,Warning interrupt flag" "0,1"
textline "                  "
bitfld.long 0x00 2. " WDTOF     ,Watchdog time-out flag" "0,1"
textline "                  "
bitfld.long 0x00 1. " WDRESET   ,Watchdog reset enable bit" "0: INTERRUPT,1: RESET"
textline "                  "
bitfld.long 0x00 0. " WDEN      ,Watchdog enable bit" "0: STOP,1: RUN"
group.long 0x04++0x03
line.long 0x00 "TC,Watchdog timer constant register"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT     ,Watchdog time-out value"
wgroup.long 0x08++0x03
line.long 0x00 "FEED,Watchdog feed sequence register"
hexmask.long.byte 0x00 0.--7. 1. " FEED      ,Feed value should be 0xAA followed by 0x55"
rgroup.long 0x0C++0x03
line.long 0x00 "TV,Watchdog timer value register"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT     ,Counter timer value"
group.long 0x14++0x03
line.long 0x00 "WARNINT,Watchdog Warning Interrupt compare value"
hexmask.long.word 0x00 0.--9. 1. " WARNINT   ,Watchdog warning interrupt compare value"
group.long 0x18++0x03
line.long 0x00 "WINDOW,Watchdog Window compare value"
hexmask.long.tbyte 0x00 0.--23. 1. " WINDOW    ,Watchdog window value"
width 0x0B
tree.end
tree "WWDT1"
base ad:0x4002E000
width 9.
group.long 0x00++0x03
line.long 0x00 "MOD,Watchdog mode register"
bitfld.long 0x00 5. " LOCK      ,Once this bit is set to one and a watchdog feed is performed. disabling or powering down the watchdo.." "0,1"
textline "                  "
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "0: FLEXIBLE,1: THRESHOLD"
textline "                  "
bitfld.long 0x00 3. " WDINT     ,Warning interrupt flag" "0,1"
textline "                  "
bitfld.long 0x00 2. " WDTOF     ,Watchdog time-out flag" "0,1"
textline "                  "
bitfld.long 0x00 1. " WDRESET   ,Watchdog reset enable bit" "0: INTERRUPT,1: RESET"
textline "                  "
bitfld.long 0x00 0. " WDEN      ,Watchdog enable bit" "0: STOP,1: RUN"
group.long 0x04++0x03
line.long 0x00 "TC,Watchdog timer constant register"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT     ,Watchdog time-out value"
wgroup.long 0x08++0x03
line.long 0x00 "FEED,Watchdog feed sequence register"
hexmask.long.byte 0x00 0.--7. 1. " FEED      ,Feed value should be 0xAA followed by 0x55"
rgroup.long 0x0C++0x03
line.long 0x00 "TV,Watchdog timer value register"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT     ,Counter timer value"
group.long 0x14++0x03
line.long 0x00 "WARNINT,Watchdog Warning Interrupt compare value"
hexmask.long.word 0x00 0.--9. 1. " WARNINT   ,Watchdog warning interrupt compare value"
group.long 0x18++0x03
line.long 0x00 "WINDOW,Watchdog Window compare value"
hexmask.long.tbyte 0x00 0.--23. 1. " WINDOW    ,Watchdog window value"
width 0x0B
tree.end
tree.end
textline ""