; -------------------------------------------------------------------------------- ; @Title: DA1469x On-Chip Peripherals ; @Props: Released ; @Author: KOL ; @Changelog: 2019-03-07 KOL ; @Manufacturer: Dialog Semiconductor ; @Doc: DA1469x.xml ; @Core: Cortex-M33 ; @Chip: DA14691-CM33, DA14695-CM33, DA14697-CM33, DA14699-CM33 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perda1469x.per 12000 2020-06-02 09:45:16Z kwitkowski $ config 16. 8. tree.close "Core Registers (Cortex-M33F)" tree "System Control" base ad:0xE000E000 width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" textline " " bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes" group.long 0x0C++0x0F line.long 0x00 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted" line.long 0x04 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x08 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x0C "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure" rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" textline " " hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" line.long 0x14 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV" hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending" bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending" bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active" bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active" textline " " bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active" bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "UFSR,Usage Fault Status Register" eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error" textline " " eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error" textline " " eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x03 line.long 0x00 "HFSR,HardFault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" if PER.ADDRESS.isSECUREEX(ad:0xE000ED48) group.long 0xD8C++0x03 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled" bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled" bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled" bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled" bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled" bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled" bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled" else hgroup.long 0xD8C++0x03 hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)" endif wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended" tree "Memory System" width 10. rgroup.long 0xD78++0x0B line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest" bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..." textline " " bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..." bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." textline " " bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." if ((per.l(ad:0xE000E000+0xD7C)&0xE0000000)==0x80000000) rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." endif rgroup.long 0x80++0x03 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU" wgroup.long 0xF58++0x23 line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU" line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC" line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way" hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU" line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC" line.long 0x14 "DCCSW,D-Cache Clean by Set-Way" hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC" line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way" hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x20 "BPIALL,Branch Predictor Invalidate All" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..." rgroup.long 0xD4C++0x03 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..." rgroup.long 0xD54++0x03 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD5C++0x03 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..." rgroup.long 0xD60++0x03 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." rgroup.long 0xD64++0x03 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..." rgroup.long 0xD68++0x03 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..." textline " " bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..." rgroup.long 0xD6C++0x03 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..." textline " " bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..." rgroup.long 0xD70++0x07 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..." bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..." bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..." textline " " bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..." bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..." tree.end tree "CoreSight Identification Registers" base ad:0xE000E000 width 11. if (((per.l(ad:0xE000E000+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "DPIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DPIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DPIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DPIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DCIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DCIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DCIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DCIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0xB tree.end tree "Memory Protection Unit" base ad:0xE000ED00 width 15. rgroup.long 0x90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..." group.long 0x94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x0 group.long 0x9C++0x03 "Region 0" saveout 0x98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x0 line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 0 (not implemented)" saveout 0x98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x0 hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x1 group.long 0x9C++0x03 "Region 1" saveout 0x98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x1 line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 1 (not implemented)" saveout 0x98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x1 hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x2 group.long 0x9C++0x03 "Region 2" saveout 0x98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x2 line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 2 (not implemented)" saveout 0x98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x2 hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x3 group.long 0x9C++0x03 "Region 3" saveout 0x98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x3 line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 3 (not implemented)" saveout 0x98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x3 hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x4 group.long 0x9C++0x03 "Region 4" saveout 0x98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x4 line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 4 (not implemented)" saveout 0x98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x4 hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x5 group.long 0x9C++0x03 "Region 5" saveout 0x98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x5 line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 5 (not implemented)" saveout 0x98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x5 hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x6 group.long 0x9C++0x03 "Region 6" saveout 0x98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x6 line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 6 (not implemented)" saveout 0x98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x6 hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x7 group.long 0x9C++0x03 "Region 7" saveout 0x98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x7 line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 7 (not implemented)" saveout 0x98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x7 hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x8 group.long 0x9C++0x03 "Region 8" saveout 0x98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x8 line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 8 (not implemented)" saveout 0x98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x8 hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0x9 group.long 0x9C++0x03 "Region 9" saveout 0x98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0x9 line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 9 (not implemented)" saveout 0x98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0x9 hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xA group.long 0x9C++0x03 "Region 10" saveout 0x98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xA line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 10 (not implemented)" saveout 0x98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xA hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xB group.long 0x9C++0x03 "Region 11" saveout 0x98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xB line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 11 (not implemented)" saveout 0x98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xB hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xC group.long 0x9C++0x03 "Region 12" saveout 0x98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xC line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 12 (not implemented)" saveout 0x98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xC hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xD group.long 0x9C++0x03 "Region 13" saveout 0x98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xD line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 13 (not implemented)" saveout 0x98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xD hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xE group.long 0x9C++0x03 "Region 14" saveout 0x98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xE line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 14 (not implemented)" saveout 0x98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xE hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" endif if ((per.l(ad:0xE000ED90)&0xff00)>>8)>0xF group.long 0x9C++0x03 "Region 15" saveout 0x98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xA0++0x03 saveout 0x98 %l 0xF line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0x9C++0x03 "Region 15 (not implemented)" saveout 0x98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" textline " " hgroup.long 0xA0++0x03 saveout 0x98 %l 0xF hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" endif tree.end textline " " group.long 0xC0++0x07 line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1" hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0" line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1" hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7" hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6" hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5" hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4" width 0x0b tree.end tree "Security Attribution Unit" base ad:0xE000ED00 width 15. group.long 0xD0++0x03 line.long 0x00 "SAU_CTRL,SAU Control Register" bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure" bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled" rgroup.long 0xD4++0x03 line.long 0x00 "SAU_TYPE,SAU Type Register" bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD8++0x03 line.long 0x00 "SAU_RNR,SAU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR" tree.close "SAU regions" if PER.ADDRESS.isSECUREEX(ad:0xE000EDD0) if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x0 group.long 0xDC++0x03 "Region 0" saveout 0xD8 %l 0x0 line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x0 line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 0 (not implemented)" saveout 0xD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x1 group.long 0xDC++0x03 "Region 1" saveout 0xD8 %l 0x1 line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x1 line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 1 (not implemented)" saveout 0xD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x2 group.long 0xDC++0x03 "Region 2" saveout 0xD8 %l 0x2 line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x2 line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 2 (not implemented)" saveout 0xD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x3 group.long 0xDC++0x03 "Region 3" saveout 0xD8 %l 0x3 line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x3 line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 3 (not implemented)" saveout 0xD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x4 group.long 0xDC++0x03 "Region 4" saveout 0xD8 %l 0x4 line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x4 line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 4 (not implemented)" saveout 0xD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x5 group.long 0xDC++0x03 "Region 5" saveout 0xD8 %l 0x5 line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x5 line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 5 (not implemented)" saveout 0xD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x6 group.long 0xDC++0x03 "Region 6" saveout 0xD8 %l 0x6 line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x6 line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 6 (not implemented)" saveout 0xD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" endif if ((per.l(ad:0xE000EDD0+0x04)&0xFF))>0x7 group.long 0xDC++0x03 "Region 7" saveout 0xD8 %l 0x7 line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xE0++0x03 saveout 0xD8 %l 0x7 line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDC++0x03 "Region 7 (not implemented)" saveout 0xD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif else hgroup.long 0xDC++0x03 "Region 0 (not accessible)" saveout 0xD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hgroup.long 0xDC++0x03 "Region 1 (not accessible)" saveout 0xD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hgroup.long 0xDC++0x03 "Region 2 (not accessible)" saveout 0xD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hgroup.long 0xDC++0x03 "Region 3 (not accessible)" saveout 0xD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hgroup.long 0xDC++0x03 "Region 4 (not accessible)" saveout 0xD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hgroup.long 0xDC++0x03 "Region 5 (not accessible)" saveout 0xD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hgroup.long 0xDC++0x03 "Region 6 (not accessible)" saveout 0xD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hgroup.long 0xDC++0x03 "Region 7 (not accessible)" saveout 0xD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xE0++0x03 saveout 0xD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif tree.end group.long 0xE4++0x03 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred" bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid" bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred" bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred" bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred" bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred" group.long 0xE8++0x03 line.long 0x00 "SFAR,Secure Fault Address Register" width 0x0b tree.end tree "Nested Vectored Interrupt Controller" base ad:0xE000E000 width 6. group.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511" width 24. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01) group.long 0x104++0x03 line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x104++0x03 hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02) group.long 0x108++0x03 line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x108++0x03 hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03) group.long 0x10C++0x03 line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x10C++0x03 hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04) group.long 0x110++0x03 line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x110++0x03 hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05) group.long 0x114++0x03 line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x114++0x03 hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06) group.long 0x118++0x03 line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x118++0x03 hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07) group.long 0x11C++0x03 line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x11C++0x03 hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08) group.long 0x120++0x03 line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x120++0x03 hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09) group.long 0x124++0x03 line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x124++0x03 hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A) group.long 0x128++0x03 line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x128++0x03 hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B) group.long 0x12C++0x03 line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x12C++0x03 hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C) group.long 0x130++0x03 line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x130++0x03 hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D) group.long 0x134++0x03 line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x134++0x03 hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E) group.long 0x138++0x03 line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x138++0x03 hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F) group.long 0x13C++0x03 line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x13C++0x03 hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" endif tree.end width 24. tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01) group.long 0x204++0x03 line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x204++0x03 hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02) group.long 0x208++0x03 line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x208++0x03 hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03) group.long 0x20C++0x03 line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x20C++0x03 hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04) group.long 0x210++0x03 line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x210++0x03 hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05) group.long 0x214++0x03 line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x214++0x03 hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06) group.long 0x218++0x03 line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x218++0x03 hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07) group.long 0x21C++0x03 line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x21C++0x03 hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08) group.long 0x220++0x03 line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x220++0x03 hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09) group.long 0x224++0x03 line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x224++0x03 hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A) group.long 0x228++0x03 line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x228++0x03 hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B) group.long 0x22C++0x03 line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x22C++0x03 hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C) group.long 0x230++0x03 line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x230++0x03 hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D) group.long 0x234++0x03 line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x234++0x03 hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E) group.long 0x238++0x03 line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x238++0x03 hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F) group.long 0x23C++0x03 line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x23C++0x03 hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" endif tree.end width 11. tree "Interrupt Active Bit Registers" rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE0,Active Bit Register 0" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01) rgroup.long 0x304++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x304++0x03 hide.long 0x00 "ACTIVE1,Active Bit Register 1" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02) rgroup.long 0x308++0x03 line.long 0x00 "ACTIVE2,Active Bit Register 2" bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x308++0x03 hide.long 0x00 "ACTIVE2,Active Bit Register 2" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03) rgroup.long 0x30C++0x03 line.long 0x00 "ACTIVE3,Active Bit Register 3" bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x30C++0x03 hide.long 0x00 "ACTIVE3,Active Bit Register 3" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04) rgroup.long 0x310++0x03 line.long 0x00 "ACTIVE4,Active Bit Register 4" bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x310++0x03 hide.long 0x00 "ACTIVE4,Active Bit Register 4" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05) rgroup.long 0x314++0x03 line.long 0x00 "ACTIVE5,Active Bit Register 5" bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x314++0x03 hide.long 0x00 "ACTIVE5,Active Bit Register 5" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06) rgroup.long 0x318++0x03 line.long 0x00 "ACTIVE6,Active Bit Register 6" bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x318++0x03 hide.long 0x00 "ACTIVE6,Active Bit Register 6" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07) rgroup.long 0x31C++0x03 line.long 0x00 "ACTIVE7,Active Bit Register 7" bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x31C++0x03 hide.long 0x00 "ACTIVE7,Active Bit Register 7" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08) rgroup.long 0x320++0x03 line.long 0x00 "ACTIVE8,Active Bit Register 8" bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x320++0x03 hide.long 0x00 "ACTIVE8,Active Bit Register 8" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09) rgroup.long 0x324++0x03 line.long 0x00 "ACTIVE9,Active Bit Register 9" bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x324++0x03 hide.long 0x00 "ACTIVE9,Active Bit Register 9" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A) rgroup.long 0x328++0x03 line.long 0x00 "ACTIVE10,Active Bit Register 10" bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x328++0x03 hide.long 0x00 "ACTIVE10,Active Bit Register 10" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B) rgroup.long 0x32C++0x03 line.long 0x00 "ACTIVE11,Active Bit Register 11" bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x32C++0x03 hide.long 0x00 "ACTIVE11,Active Bit Register 11" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C) rgroup.long 0x330++0x03 line.long 0x00 "ACTIVE12,Active Bit Register 12" bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x330++0x03 hide.long 0x00 "ACTIVE12,Active Bit Register 12" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D) rgroup.long 0x334++0x03 line.long 0x00 "ACTIVE13,Active Bit Register 13" bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x334++0x03 hide.long 0x00 "ACTIVE13,Active Bit Register 13" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E) rgroup.long 0x338++0x03 line.long 0x00 "ACTIVE14,Active Bit Register 14" bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x338++0x03 hide.long 0x00 "ACTIVE14,Active Bit Register 14" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0F) rgroup.long 0x33C++0x03 line.long 0x00 "ACTIVE15,Active Bit Register 15" bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x33C++0x03 hide.long 0x00 "ACTIVE15,Active Bit Register 15" endif tree.end width 13. tree "Interrupt Target Non-Secure Registers" group.long 0x380++0x03 line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0" bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure" if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01) group.long 0x384++0x03 line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure" else hgroup.long 0x384++0x03 hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02) group.long 0x388++0x03 line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure" else hgroup.long 0x388++0x03 hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03) group.long 0x38C++0x03 line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure" else hgroup.long 0x38C++0x03 hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04) group.long 0x390++0x03 line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure" else hgroup.long 0x390++0x03 hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05) group.long 0x394++0x03 line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure" else hgroup.long 0x394++0x03 hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06) group.long 0x398++0x03 line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure" else hgroup.long 0x398++0x03 hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07) group.long 0x39C++0x03 line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure" else hgroup.long 0x39C++0x03 hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08) group.long 0x3A0++0x03 line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure" else hgroup.long 0x3A0++0x03 hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09) group.long 0x3A4++0x03 line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure" else hgroup.long 0x3A4++0x03 hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A) group.long 0x3A8++0x03 line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure" else hgroup.long 0x3A8++0x03 hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B) group.long 0x3AC++0x03 line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure" else hgroup.long 0x3AC++0x03 hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C) group.long 0x3B0++0x03 line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure" else hgroup.long 0x3B0++0x03 hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D) group.long 0x3B4++0x03 line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure" else hgroup.long 0x3B4++0x03 hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E) group.long 0x3B8++0x03 line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure" else hgroup.long 0x3B8++0x03 hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)==0x0F) group.long 0x3BC++0x03 line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure" else hgroup.long 0x3BC++0x03 hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" endif tree.end tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x01) group.long 0x420++0x1F line.long 0x0 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x4 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x8 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0xC "IPR11,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x10 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x14 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x18 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x1C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" else hgroup.long 0x420++0x1F hide.long 0x0 "IPR8,Interrupt Priority Register" hide.long 0x4 "IPR9,Interrupt Priority Register" hide.long 0x8 "IPR10,Interrupt Priority Register" hide.long 0xC "IPR11,Interrupt Priority Register" hide.long 0x10 "IPR12,Interrupt Priority Register" hide.long 0x14 "IPR13,Interrupt Priority Register" hide.long 0x18 "IPR14,Interrupt Priority Register" hide.long 0x1C "IPR15,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x02) group.long 0x440++0x1F line.long 0x0 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x4 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x8 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0xC "IPR19,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x10 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x14 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x18 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x1C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" else hgroup.long 0x440++0x1F hide.long 0x0 "IPR16,Interrupt Priority Register" hide.long 0x4 "IPR17,Interrupt Priority Register" hide.long 0x8 "IPR18,Interrupt Priority Register" hide.long 0xC "IPR19,Interrupt Priority Register" hide.long 0x10 "IPR20,Interrupt Priority Register" hide.long 0x14 "IPR21,Interrupt Priority Register" hide.long 0x18 "IPR22,Interrupt Priority Register" hide.long 0x1C "IPR23,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x03) group.long 0x460++0x1F line.long 0x0 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x4 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x8 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0xC "IPR27,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x10 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x14 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x18 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x1C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" else hgroup.long 0x460++0x1F hide.long 0x0 "IPR24,Interrupt Priority Register" hide.long 0x4 "IPR25,Interrupt Priority Register" hide.long 0x8 "IPR26,Interrupt Priority Register" hide.long 0xC "IPR27,Interrupt Priority Register" hide.long 0x10 "IPR28,Interrupt Priority Register" hide.long 0x14 "IPR29,Interrupt Priority Register" hide.long 0x18 "IPR30,Interrupt Priority Register" hide.long 0x1C "IPR31,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x04) group.long 0x480++0x1F line.long 0x0 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x4 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x8 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0xC "IPR35,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x10 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x14 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x18 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x1C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" else hgroup.long 0x480++0x1F hide.long 0x0 "IPR32,Interrupt Priority Register" hide.long 0x4 "IPR33,Interrupt Priority Register" hide.long 0x8 "IPR34,Interrupt Priority Register" hide.long 0xC "IPR35,Interrupt Priority Register" hide.long 0x10 "IPR36,Interrupt Priority Register" hide.long 0x14 "IPR37,Interrupt Priority Register" hide.long 0x18 "IPR38,Interrupt Priority Register" hide.long 0x1C "IPR39,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x05) group.long 0x4A0++0x1F line.long 0x0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0x4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0x8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0x10 "IPR44,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0x14 "IPR45,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0x18 "IPR46,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0x1C "IPR47,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" else hgroup.long 0x4A0++0x1F hide.long 0x0 "IPR40,Interrupt Priority Register" hide.long 0x4 "IPR41,Interrupt Priority Register" hide.long 0x8 "IPR42,Interrupt Priority Register" hide.long 0xC "IPR43,Interrupt Priority Register" hide.long 0x10 "IPR44,Interrupt Priority Register" hide.long 0x14 "IPR45,Interrupt Priority Register" hide.long 0x18 "IPR46,Interrupt Priority Register" hide.long 0x1C "IPR47,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x06) group.long 0x4C0++0x1F line.long 0x0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0x4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0x8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0x10 "IPR52,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0x14 "IPR53,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0x18 "IPR54,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0x1C "IPR55,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" else hgroup.long 0x4C0++0x1F hide.long 0x0 "IPR48,Interrupt Priority Register" hide.long 0x4 "IPR49,Interrupt Priority Register" hide.long 0x8 "IPR50,Interrupt Priority Register" hide.long 0xC "IPR51,Interrupt Priority Register" hide.long 0x10 "IPR52,Interrupt Priority Register" hide.long 0x14 "IPR53,Interrupt Priority Register" hide.long 0x18 "IPR54,Interrupt Priority Register" hide.long 0x1C "IPR55,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x07) group.long 0x4E0++0x1F line.long 0x0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0x4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0x8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" line.long 0x10 "IPR60,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority" line.long 0x14 "IPR61,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority" line.long 0x18 "IPR62,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority" line.long 0x1C "IPR63,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority" else hgroup.long 0x4E0++0x1F hide.long 0x0 "IPR56,Interrupt Priority Register" hide.long 0x4 "IPR57,Interrupt Priority Register" hide.long 0x8 "IPR58,Interrupt Priority Register" hide.long 0xC "IPR59,Interrupt Priority Register" hide.long 0x10 "IPR60,Interrupt Priority Register" hide.long 0x14 "IPR61,Interrupt Priority Register" hide.long 0x18 "IPR62,Interrupt Priority Register" hide.long 0x1C "IPR63,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x08) group.long 0x500++0x1F line.long 0x0 "IPR64,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority" line.long 0x4 "IPR65,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority" line.long 0x8 "IPR66,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority" line.long 0xC "IPR67,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority" line.long 0x10 "IPR68,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority" line.long 0x14 "IPR69,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority" line.long 0x18 "IPR70,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority" line.long 0x1C "IPR71,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority" else hgroup.long 0x500++0x1F hide.long 0x0 "IPR64,Interrupt Priority Register" hide.long 0x4 "IPR65,Interrupt Priority Register" hide.long 0x8 "IPR66,Interrupt Priority Register" hide.long 0xC "IPR67,Interrupt Priority Register" hide.long 0x10 "IPR68,Interrupt Priority Register" hide.long 0x14 "IPR69,Interrupt Priority Register" hide.long 0x18 "IPR70,Interrupt Priority Register" hide.long 0x1C "IPR71,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x09) group.long 0x520++0x1F line.long 0x0 "IPR72,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority" line.long 0x4 "IPR73,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority" line.long 0x8 "IPR74,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority" line.long 0xC "IPR75,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority" line.long 0x10 "IPR76,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority" line.long 0x14 "IPR77,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority" line.long 0x18 "IPR78,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority" line.long 0x1C "IPR79,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority" else hgroup.long 0x520++0x1F hide.long 0x0 "IPR72,Interrupt Priority Register" hide.long 0x4 "IPR73,Interrupt Priority Register" hide.long 0x8 "IPR74,Interrupt Priority Register" hide.long 0xC "IPR75,Interrupt Priority Register" hide.long 0x10 "IPR76,Interrupt Priority Register" hide.long 0x14 "IPR77,Interrupt Priority Register" hide.long 0x18 "IPR78,Interrupt Priority Register" hide.long 0x1C "IPR79,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0A) group.long 0x540++0x1F line.long 0x0 "IPR80,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority" line.long 0x4 "IPR81,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority" line.long 0x8 "IPR82,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority" line.long 0xC "IPR83,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority" line.long 0x10 "IPR84,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority" line.long 0x14 "IPR85,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority" line.long 0x18 "IPR86,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority" line.long 0x1C "IPR87,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority" else hgroup.long 0x540++0x1F hide.long 0x0 "IPR80,Interrupt Priority Register" hide.long 0x4 "IPR81,Interrupt Priority Register" hide.long 0x8 "IPR82,Interrupt Priority Register" hide.long 0xC "IPR83,Interrupt Priority Register" hide.long 0x10 "IPR84,Interrupt Priority Register" hide.long 0x14 "IPR85,Interrupt Priority Register" hide.long 0x18 "IPR86,Interrupt Priority Register" hide.long 0x1C "IPR87,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0B) group.long 0x560++0x1F line.long 0x0 "IPR88,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority" line.long 0x4 "IPR89,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority" line.long 0x8 "IPR90,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority" line.long 0xC "IPR91,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority" line.long 0x10 "IPR92,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority" line.long 0x14 "IPR93,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority" line.long 0x18 "IPR94,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority" line.long 0x1C "IPR95,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority" else hgroup.long 0x560++0x1F hide.long 0x0 "IPR88,Interrupt Priority Register" hide.long 0x4 "IPR89,Interrupt Priority Register" hide.long 0x8 "IPR90,Interrupt Priority Register" hide.long 0xC "IPR91,Interrupt Priority Register" hide.long 0x10 "IPR92,Interrupt Priority Register" hide.long 0x14 "IPR93,Interrupt Priority Register" hide.long 0x18 "IPR94,Interrupt Priority Register" hide.long 0x1C "IPR95,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0C) group.long 0x580++0x1F line.long 0x0 "IPR96,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority" line.long 0x4 "IPR97,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority" line.long 0x8 "IPR98,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority" line.long 0xC "IPR99,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority" line.long 0x10 "IPR100,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority" line.long 0x14 "IPR101,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority" line.long 0x18 "IPR102,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority" line.long 0x1C "IPR103,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority" else hgroup.long 0x580++0x1F hide.long 0x0 "IPR96,Interrupt Priority Register" hide.long 0x4 "IPR97,Interrupt Priority Register" hide.long 0x8 "IPR98,Interrupt Priority Register" hide.long 0xC "IPR99,Interrupt Priority Register" hide.long 0x10 "IPR100,Interrupt Priority Register" hide.long 0x14 "IPR101,Interrupt Priority Register" hide.long 0x18 "IPR102,Interrupt Priority Register" hide.long 0x1C "IPR103,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0D) group.long 0x5A0++0x1F line.long 0x0 "IPR104,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority" line.long 0x4 "IPR105,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority" line.long 0x8 "IPR106,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority" line.long 0xC "IPR107,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority" line.long 0x10 "IPR108,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority" line.long 0x14 "IPR109,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority" line.long 0x18 "IPR110,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority" line.long 0x1C "IPR111,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority" else hgroup.long 0x5A0++0x1F hide.long 0x0 "IPR104,Interrupt Priority Register" hide.long 0x4 "IPR105,Interrupt Priority Register" hide.long 0x8 "IPR106,Interrupt Priority Register" hide.long 0xC "IPR107,Interrupt Priority Register" hide.long 0x10 "IPR108,Interrupt Priority Register" hide.long 0x14 "IPR109,Interrupt Priority Register" hide.long 0x18 "IPR110,Interrupt Priority Register" hide.long 0x1C "IPR111,Interrupt Priority Register" endif if (((per.l(ad:0xE000E000+0x04))&0x0F)>=0x0E) group.long 0x5C0++0x1F line.long 0x0 "IPR112,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority" line.long 0x4 "IPR113,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority" line.long 0x8 "IPR114,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority" line.long 0xC "IPR115,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority" line.long 0x10 "IPR116,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority" line.long 0x14 "IPR117,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority" line.long 0x18 "IPR118,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority" line.long 0x1C "IPR119,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority" else hgroup.long 0x5C0++0x1F hide.long 0x0 "IPR112,Interrupt Priority Register" hide.long 0x4 "IPR113,Interrupt Priority Register" hide.long 0x8 "IPR114,Interrupt Priority Register" hide.long 0xC "IPR115,Interrupt Priority Register" hide.long 0x10 "IPR116,Interrupt Priority Register" hide.long 0x14 "IPR117,Interrupt Priority Register" hide.long 0x18 "IPR118,Interrupt Priority Register" hide.long 0x1C "IPR119,Interrupt Priority Register" endif tree.end width 0x0b tree.end sif CORENAME()=="CORTEXM33F" tree "Floating-point Unit (FPU)" base ad:0xE000EF34 width 8. group.long 0x00++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored" textline " " bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled" bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only" bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able" bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able" bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" textline " " bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure" textline " " bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0x0C++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." textline " " bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0xB tree.end endif tree "Debug" base ad:0xE000ED00 width 7. group.long 0x30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" textline " " eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" hgroup.long 0xF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in wgroup.long 0xF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(ad:0xE000ED00+0xFC))&0x10000)==0x10000) group.long 0xFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" textline " " bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" textline " " bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif textline " " width 13. group.long 0x104++0x07 line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register" bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN" bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN" textline " " line.long 0x04 "DSCSR,Debug Security Control and Status Register" bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure" bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure" bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled" rgroup.long 0x2B8++0x03 line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1" bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented" textline " " bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1" bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1" tree "Debug components" width 14. base ad:0xE00FF000 group.long 0x00++0x0F line.long 0x00 "SCS,System Control Space" line.long 0x04 "DWT,Data Watchpoint and Trace Unit" line.long 0x08 "FPB,Flash Patch and Breakpoint Unit" line.long 0x0C "ITM,Instrumentation Trace Macrocell" group.long 0x14++0x0B line.long 0x00 "ETM,Embedded Trace Macrocell" line.long 0x04 "CTI,Cross Trigger Interface" line.long 0x08 "MTB,Micro Trace Buffer" group.long 0xFCC++0x03 line.long 0x00 "MEMTYPE,MEMTYPE" bitfld.long 0x00 0. " MEMTYPE[0] ,Indicates that resources other than those listed in the ROM table are accessible in the same 32-bit address space using the DAP" "No,Yes" tree "Coresight identification Registers" width 6. rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFE0++0x1F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" line.long 0x10 "CID0,Component ID0 (Preamble)" line.long 0x14 "CID1,Component ID1" hexmask.long.byte 0x14 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x14 0.--3. 1. " Preamble ,Preamble" line.long 0x18 "CID2,Component ID2" line.long 0x1c "CID3,Component ID3" tree.end tree.end width 0x0b tree "Flash Patch and Breakpoint Unit (FPB)" base ad:0xE0002000 width 12. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline " " if (((per.l(ad:0xE0002000+0x04))&0x20000000)==0x20000000) rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address" else rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" endif if (((per.l(ad:0xE0002000+0x8))&0x01)==0x00) group.long 0x8++0x1F line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x8++0x1F line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0xC))&0x01)==0x00) group.long 0xC++0x1F line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0xC++0x1F line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x10))&0x01)==0x00) group.long 0x10++0x1F line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x10++0x1F line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x14))&0x01)==0x00) group.long 0x14++0x1F line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x14++0x1F line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x18))&0x01)==0x00) group.long 0x18++0x1F line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x18++0x1F line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x1C))&0x01)==0x00) group.long 0x1C++0x1F line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x1C++0x1F line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x20))&0x01)==0x00) group.long 0x20++0x1F line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x20++0x1F line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(ad:0xE0002000+0x24))&0x01)==0x00) group.long 0x24++0x1F line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x24++0x1F line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif tree "CoreSight Identification Registers" width 12. rgroup.long 0xFCC++0x03 line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" if (((per.l(ad:0xE0002000+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "FP_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "FP_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "FP_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "FP_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "FP_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "FP_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "FP_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b tree.end tree "Data Watchpoint and Trace Unit (DWT)" base ad:0xE0001000 width 16. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,?..." rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" textline " " rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" if ((per.l(ad:0xE0001000)&0x1000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,Cycle Count register" endif if ((per.l(ad:0xE0001000)&0x2000000)==0x0000000) group.long 0x08++0x17 line.long 0x00 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter" line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x10 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter" line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter" endif rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " if ((per.l(ad:0xE0001000+0x20+0x08)&0xF)==0x1) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0x4) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0xC) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x20+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x20+0x08)&0xF)<0xF) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" endif group.long (0x20+0x08)++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(ad:0xE0001000+0x30+0x08)&0xF)==0x1) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0x4) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0xC) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x30+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x30+0x08)&0xF)<0xF) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" endif group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(ad:0xE0001000+0x40+0x08)&0xF)==0x1) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0x4) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0xC) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x40+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x40+0x08)&0xF)<0xF) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" endif group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(ad:0xE0001000+0x50+0x08)&0xF)==0x1) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x2&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0x4) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x8&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0xC) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0x4&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0x8||(per.l(ad:0xE0001000+0x50+0x08)&0xF)>=0xC&&(per.l(ad:0xE0001000+0x50+0x08)&0xF)<0xF) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" endif group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" tree "CoreSight Identification Registers" width 13. if (((per.l(ad:0xE0001000+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFCC++0x03 line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" rgroup.long 0xFE0++0x0F line.long 0x00 "DWT_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DWT_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DWT_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DWT_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DWT_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DWT_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DWT_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b tree.end tree.end tree.end tree "NVIC" base ad:0xE000E100 width 6. group.long 0x0++0x3 line.long 0x00 "ISER,Interrupt set-enable register" bitfld.long 0x00 31. " RSVD__IRQ__N ,Rsvd__irq__n (Reserved)" "0,1" bitfld.long 0x00 30. " XTAL16RDY_IRQN ,XTAL16RDY_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 29. " DCDC_IRQN ,DCDC_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 28. " TRNG_IRQN ,TRNG_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 27. " RF_DIAG_IRQN ,RF_DIAG_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 26. " DMA_IRQN ,DMA_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 25. " VBUS_IRQN ,VBUS_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 24. " SRC_OUT_IRQN ,SRC_OUT_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 23. " SRC_IN_IRQN ,SRC_IN_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 22. " PCM_IRQN ,PCM_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 21. " USB_IRQN ,USB_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 20. " QUADEC_IRQN ,QUADEC_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 19. " SWTIM1_IRQN ,SWTIM1_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 18. " SWTIM0_IRQN ,SWTIM0_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 17. " WKUP_GPIO_IRQN ,WKUP_GPIO_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 16. " IRGEN_IRQN ,IRGEN_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 15. " KEYBRD_IRQN ,KEYBRD_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 14. " ADC_IRQN ,ADC_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 13. " SPI2_IRQN ,SPI2_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 12. " SPI_IRQN ,SPI_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 11. " I2C2_IRQN ,I2C2_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 10. " I2C_IRQN ,I2C_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 9. " UART2_IRQN ,UART2_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 8. " UART_IRQN ,UART_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 7. " MRM_IRQN ,MRM_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 6. " CRYPTO_IRQN ,CRYPTO_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 5. " COEX_IRQN ,COEX_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 4. " RFCAL_IRQN ,RFCAL_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 3. " FTDF_GEN_IRQN ,FTDF_GEN_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 2. " FTDF_WAKEUP_IRQN ,FTDF_WAKEUP_IRQn (Interrupt set-enable bit)" "0,1" textline " " bitfld.long 0x00 1. " BLE_GEN_IRQN ,BLE_GEN_IRQn (Interrupt set-enable bit)" "0,1" bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQN ,BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)" "0,1" group.long 0x80++0x3 line.long 0x00 "ICER,Interrupt clear-enable register" bitfld.long 0x00 31. " RSVD__IRQ__N ,Rsvd__irq__n (Reserved)" "0,1" bitfld.long 0x00 30. " XTAL16RDY_IRQN ,XTAL16RDY_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 29. " DCDC_IRQN ,DCDC_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 28. " TRNG_IRQN ,TRNG_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 27. " RF_DIAG_IRQN ,RF_DIAG_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 26. " DMA_IRQN ,DMA_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 25. " VBUS_IRQN ,VBUS_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 24. " SRC_OUT_IRQN ,SRC_OUT_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 23. " SRC_IN_IRQN ,SRC_IN_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 22. " PCM_IRQN ,PCM_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 21. " USB_IRQN ,USB_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 20. " QUADEC_IRQN ,QUADEC_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 19. " SWTIM1_IRQN ,SWTIM1_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 18. " SWTIM0_IRQN ,SWTIM0_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 17. " WKUP_GPIO_IRQN ,WKUP_GPIO_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 16. " IRGEN_IRQN ,IRGEN_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 15. " KEYBRD_IRQN ,KEYBRD_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 14. " ADC_IRQN ,ADC_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 13. " SPI2_IRQN ,SPI2_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 12. " SPI_IRQN ,SPI_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 11. " I2C2_IRQN ,I2C2_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 10. " I2C_IRQN ,I2C_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 9. " UART2_IRQN ,UART2_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 8. " UART_IRQN ,UART_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 7. " MRM_IRQN ,MRM_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 6. " CRYPTO_IRQN ,CRYPTO_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 5. " COEX_IRQN ,COEX_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 4. " RFCAL_IRQN ,RFCAL_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 3. " FTDF_GEN_IRQN ,FTDF_GEN_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 2. " FTDF_WAKEUP_IRQN ,FTDF_WAKEUP_IRQn (Interrupt clear-enable bit)" "0,1" textline " " bitfld.long 0x00 1. " BLE_GEN_IRQN ,BLE_GEN_IRQn (Interrupt clear-enable bit)" "0,1" bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQN ,BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)" "0,1" group.long 0x100++0x3 line.long 0x00 "ISPR,Interrupt set-pending register" bitfld.long 0x00 31. " RSVD__IRQ__N ,Rsvd__irq__n (Reserved)" "0,1" bitfld.long 0x00 30. " XTAL16RDY_IRQN ,XTAL16RDY_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 29. " DCDC_IRQN ,DCDC_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 28. " TRNG_IRQN ,TRNG_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 27. " RF_DIAG_IRQN ,RF_DIAG_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 26. " DMA_IRQN ,DMA_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 25. " VBUS_IRQN ,VBUS_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 24. " SRC_OUT_IRQN ,SRC_OUT_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 23. " SRC_IN_IRQN ,SRC_IN_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 22. " PCM_IRQN ,PCM_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 21. " USB_IRQN ,USB_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 20. " QUADEC_IRQN ,QUADEC_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 19. " SWTIM1_IRQN ,SWTIM1_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 18. " SWTIM0_IRQN ,SWTIM0_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 17. " WKUP_GPIO_IRQN ,WKUP_GPIO_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 16. " IRGEN_IRQN ,IRGEN_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 15. " KEYBRD_IRQN ,KEYBRD_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 14. " ADC_IRQN ,ADC_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 13. " SPI2_IRQN ,SPI2_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 12. " SPI_IRQN ,SPI_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 11. " I2C2_IRQN ,I2C2_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 10. " I2C_IRQN ,I2C_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 9. " UART2_IRQN ,UART2_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 8. " UART_IRQN ,UART_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 7. " MRM_IRQN ,MRM_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 6. " CRYPTO_IRQN ,CRYPTO_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 5. " COEX_IRQN ,COEX_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 4. " RFCAL_IRQN ,RFCAL_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 3. " FTDF_GEN_IRQN ,FTDF_GEN_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 2. " FTDF_WAKEUP_IRQN ,FTDF_WAKEUP_IRQn (Interrupt set-pending bit)" "0,1" textline " " bitfld.long 0x00 1. " BLE_GEN_IRQN ,BLE_GEN_IRQn (Interrupt set-pending bit)" "0,1" bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQN ,BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)" "0,1" group.long 0x180++0x3 line.long 0x00 "ICPR,Interrupt clear-pending register" bitfld.long 0x00 31. " RSVD__IRQ__N ,Rsvd__irq__n (Reserved)" "0,1" bitfld.long 0x00 30. " XTAL16RDY_IRQN ,XTAL16RDY_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 29. " DCDC_IRQN ,DCDC_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 28. " TRNG_IRQN ,TRNG_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 27. " RF_DIAG_IRQN ,RF_DIAG_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 26. " DMA_IRQN ,DMA_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 25. " VBUS_IRQN ,VBUS_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 24. " SRC_OUT_IRQN ,SRC_OUT_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 23. " SRC_IN_IRQN ,SRC_IN_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 22. " PCM_IRQN ,PCM_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 21. " USB_IRQN ,USB_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 20. " QUADEC_IRQN ,QUADEC_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 19. " SWTIM1_IRQN ,SWTIM1_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 18. " SWTIM0_IRQN ,SWTIM0_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 17. " WKUP_GPIO_IRQN ,WKUP_GPIO_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 16. " IRGEN_IRQN ,IRGEN_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 15. " KEYBRD_IRQN ,KEYBRD_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 14. " ADC_IRQN ,ADC_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 13. " SPI2_IRQN ,SPI2_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 12. " SPI_IRQN ,SPI_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 11. " I2C2_IRQN ,I2C2_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 10. " I2C_IRQN ,I2C_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 9. " UART2_IRQN ,UART2_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 8. " UART_IRQN ,UART_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 7. " MRM_IRQN ,MRM_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 6. " CRYPTO_IRQN ,CRYPTO_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 5. " COEX_IRQN ,COEX_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 4. " RFCAL_IRQN ,RFCAL_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 3. " FTDF_GEN_IRQN ,FTDF_GEN_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 2. " FTDF_WAKEUP_IRQN ,FTDF_WAKEUP_IRQn (Interrupt clear-pending bit)" "0,1" textline " " bitfld.long 0x00 1. " BLE_GEN_IRQN ,BLE_GEN_IRQn (Interrupt clear-pending bit)" "0,1" bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQN ,BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)" "0,1" group.long 0x300++0x3 line.long 0x00 "IPR0,Interrupt priority register 0" hexmask.long.byte 0x00 24.--31. 1. " FTDF_GEN_IRQN_PRIO ,FTDF_GEN_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " FTDF_WAKEUP_IRQN_PRIO ,FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " BLE_GEN_IRQN_PRIO ,BLE_GEN_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " BLE_WAKEUP_LP_IRQN_PRIO ,BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)" group.long 0x304++0x3 line.long 0x00 "IPR1,Interrupt priority register 1" hexmask.long.byte 0x00 24.--31. 1. " MRM_IRQN_PRIO ,MRM_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " CRYPTO_IRQN_PRIO ,CRYPTO_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " COEX_IRQN_PRIO ,COEX_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " RFCAL_IRQN_PRIO ,RFCAL_IRQn[7:0] bits (Interrupt priority)" group.long 0x308++0x3 line.long 0x00 "IPR2,Interrupt priority register 2" hexmask.long.byte 0x00 24.--31. 1. " I2C2_IRQN_PRIO ,I2C2_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " I2C_IRQN_PRIO ,I2C_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " UART2_IRQN_PRIO ,UART2_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " UART_IRQN_PRIO ,UART_IRQn[7:0] bits (Interrupt priority)" group.long 0x30C++0x3 line.long 0x00 "IPR3,Interrupt priority register 3" hexmask.long.byte 0x00 24.--31. 1. " KEYBRD_IRQN_PRIO ,KEYBRD_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " ADC_IRQN_PRIO ,ADC_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " SPI2_IRQN_PRIO ,SPI2_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SPI_IRQN_PRIO ,SPI_IRQn[7:0] bits (Interrupt priority)" group.long 0x310++0x3 line.long 0x00 "IPR4,Interrupt priority register 4" hexmask.long.byte 0x00 24.--31. 1. " SWTIM1_IRQN_PRIO ,SWTIM1_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " SWTIM0_IRQN_PRIO ,SWTIM0_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " WKUP_GPIO_IRQN_PRIO ,WKUP_GPIO_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " IRGEN_IRQN_PRIO ,IRGEN_IRQn[7:0] bits (Interrupt priority)" group.long 0x314++0x3 line.long 0x00 "IPR5,Interrupt priority register 5" hexmask.long.byte 0x00 24.--31. 1. " SRC_IN_IRQN_PRIO ,SRC_IN_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " PCM_IRQN_PRIO ,PCM_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " USB_IRQN_PRIO ,USB_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " QUADEC_IRQN_PRIO ,QUADEC_IRQn[7:0] bits (Interrupt priority)" group.long 0x318++0x3 line.long 0x00 "IPR6,Interrupt priority register 6" hexmask.long.byte 0x00 24.--31. 1. " RF_DIAG_IRQN_PRIO ,RF_DIAG_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 16.--23. 1. " DMA_IRQN_PRIO ,DMA_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " VBUS_IRQN_PRIO ,VBUS_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SRC_OUT_IRQN_PRIO ,SRC_OUT_IRQn[7:0] bits (Interrupt priority)" group.long 0x31C++0x3 line.long 0x00 "IPR7,Interrupt priority register 7" hexmask.long.byte 0x00 24.--31. 1. " RESERVED31_IRQN_DONT_USE ,RESERVED31_IRQn[7:0] bits (Reserved)" hexmask.long.byte 0x00 16.--23. 1. " XTAL16RDY_IRQN_PRIO ,XTAL16RDY_IRQn[7:0] bits (Interrupt priority)" hexmask.long.byte 0x00 8.--15. 1. " DCDC_IRQN_PRIO ,DCDC_IRQn[7:0] bits (Interrupt priority)" textline " " hexmask.long.byte 0x00 0.--7. 1. " TRNG_IRQN_PRIO ,TRNG_IRQn[7:0] bits (Interrupt priority)" width 0x0B tree.end tree "SCB" base ad:0xE000ED00 width 7. group.long 0x0++0x3 line.long 0x00 "CPUID,CPUID base register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,IMPLEMENTER[7:0] bits (Implementer code)" rbitfld.long 0x00 20.--23. " VARIANT ,VARIANT[3:0] bits (Variant number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " CONSTANT ,CONSTANT[3:0] bits (Reads as 0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,PARTNO[11:0] bits (Part number of the processor core)" rbitfld.long 0x00 0.--3. " REVISION ,REVISION[3:0] bits (Revision number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x3 line.long 0x00 "ICSR,Interrupt control and state register" bitfld.long 0x00 31. " NMIPENDSET ,NMI set-pending bit" "0,1" bitfld.long 0x00 28. " PENDSVSET ,PendSV set-pending bit" "0,1" bitfld.long 0x00 27. " PENDSVCLR ,PendSV clear-pending bit" "0,1" textline " " bitfld.long 0x00 26. " PENDSTSET ,SysTick exception set-pending bit" "0,1" bitfld.long 0x00 25. " PENDSTCLR ,SysTick exception clear-pending bit" "0,1" bitfld.long 0x00 22. " ISRPENDING ,Interrupt pending flag, excluding NMI and Faults" "0,1" textline " " bitfld.long 0x00 12.--17. " VECTPENDING ,VECTPENDING[5:0] bits (Pending vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VECTACTIVE ,VECTACTIVE[5:0] bits (Active vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC++0x3 line.long 0x00 "AIRCR,Application interrupt and reset control register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,VECTKEY[15:0] bits (Register key)" bitfld.long 0x00 15. " ENDIANESS ,Data endianness bit" "0,1" bitfld.long 0x00 2. " SYSRESETREQ ,System reset request" "0,1" textline " " bitfld.long 0x00 1. " VECTCLRACTIVE ,Reserved for Debug use" "0,1" bitfld.long 0x00 0. " VECTRESET ,Reserved for Debug use" "0,1" group.long 0x10++0x3 line.long 0x00 "SCR,System control register" bitfld.long 0x00 4. " SEVEONPEND ,Send event on pending bit" "0,1" bitfld.long 0x00 2. " SLEEPDEEP ,Controls whether the processor uses sleep or deep sleep" "0,1" bitfld.long 0x00 1. " SLEEPONEXIT ,Configures sleep-on-exit when returning from Handler mode to Thread mode" "0,1" group.long 0x14++0x3 line.long 0x00 "CCR,Configuration and control register" bitfld.long 0x00 9. " STKALIGN ,Configures stack alignment on exception entry" "0,1" bitfld.long 0x00 3. " UNALIGN_TRP ,Enables unaligned access traps" "0,1" group.long 0x1C++0x3 line.long 0x00 "SHPR2,System handler priority register 2" hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,PRI_11[7:0] bits (Priority of system handler 11, SVCall)" group.long 0x20++0x3 line.long 0x00 "SHPR3,System handler priority register 3" hexmask.long.byte 0x00 24.--31. 1. " PRI_15 ,PRI_15[7:0] bits (Priority of system handler 15, SysTick exception)" hexmask.long.byte 0x00 16.--23. 1. " PRI_14 ,PRI_14[7:0] bits (Priority of system handler 14, PendSV)" width 0x0B tree.end tree "SYSTICK" base ad:0xE000E010 width 7. group.long 0x0++0x3 line.long 0x00 "CTRL,SysTick Control and Status register" bitfld.long 0x00 16. " COUNTFLAG ,Timer counted to 0 since last time this was read" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Clock source selection" "0,1" bitfld.long 0x00 1. " TICKINT ,SysTick exception request enable" "0,1" textline " " bitfld.long 0x00 0. " ENABLE ,SysTick Counter enable" "0,1" group.long 0x4++0x3 line.long 0x00 "LOAD,SysTick Reload value register" hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,RELOAD[23:0] bits (Reload value)" group.long 0x8++0x3 line.long 0x00 "VAL,SysTick Current value register" hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT ,CURRENT[23:0] bits (Current counter value)" rgroup.long 0xC++0x3 line.long 0x00 "CALIB,SysTick Calibration value register" bitfld.long 0x00 31. " NOREF ,Indicates that a separate reference clock is provided" "0,1" bitfld.long 0x00 30. " SKEW ,Indicates whether the TENMS value is exact" "0,1" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,TENMS[23:0] bits (Calibration value)" width 0x0B tree.end tree.open "Peripheral_Registers" tree "ADPLL" base ad:0x40022000 width 29. group.long 0x64++0x3 line.long 0x00 "ADPLL_ACC_CTRL_REG," bitfld.long 0x00 31. " EN_CMF_AVG ,Enable CMF averaging._0: Disabled (default)_1: Enabled" "0,1" hexmask.long.word 0x00 16.--28. 1. " CLIP_MOD_TUNE_0_TX ,Clipping value for mod_tune 0 in TX mode" hexmask.long.word 0x00 0.--12. 1. " CLIP_MOD_TUNE_0_RX ,Clipping value for mod_tune 0 in RX mode" group.long 0x60++0x3 line.long 0x00 "ADPLL_ANATST_CTRL_REG," hexmask.long.word 0x00 16.--31. 1. " ANATSTSPARE ,Analog test spare outputs" hexmask.long.word 0x00 0.--15. 1. " ANATSTEN ,Analog test enable outputs" group.long 0x94++0x3 line.long 0x00 "ADPLL_ANATST_RD_REG," hexmask.long.word 0x00 0.--15. 1. " ANATSTSPARE_IN ,Ana test spare in" group.long 0x34++0x3 line.long 0x00 "ADPLL_ANA_CTRL_REG," bitfld.long 0x00 27.--28. " DTC_LDO_DMY ,Control signal for TDC/DTC/VPA LDO dummy loads" "0,1,2,3" bitfld.long 0x00 24.--25. " VPASETTLE ,Allow TDC after an edge on VPA en_00: No_01: Rising_10: Falling_11: Both edges" "0,1,2,3" bitfld.long 0x00 16.--21. " TDC_OFFSET ,TDC offset that is to be subtracted from the binary input to obtain the signed value (default 10.5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 15. " DTC_EN ,Enable DTC" "0,1" hexmask.long.byte 0x00 8.--14. 1. " DTCOFFSET ,Offset Added to DTC output_Only used for test purpose default = 0" bitfld.long 0x00 7. " TGLDETEN ,Enable PHV toggle and TDC Bubble detection" "0,1" textline " " bitfld.long 0x00 6. " EN_CKDCOMOD ,Enable clock registering the dcomod (default = 1)" "0,1" bitfld.long 0x00 5. " INV_CKDCOMOD ,Invert clock polarity of the clock registering the dcomod" "0,1" bitfld.long 0x00 4. " INV_CKPHV ,Invert clock polarity of the clock registering the variable phase accumulator" "0,1" textline " " bitfld.long 0x00 3. " INV_CKTDC ,Invert clock polarity of the clock registering the time to digital converter" "0,1" bitfld.long 0x00 2. " TDC_INV ,Invert sign of the time to digital converter output" "0,1" bitfld.long 0x00 1. " TDC_CKVIN_EN ,Enable ckv input of the TDC" "0,1" textline " " bitfld.long 0x00 0. " TDC_DTCIN_EN ," "0,1" group.long 0x0++0x3 line.long 0x00 "ADPLL_ATTR_CTRL_REG," bitfld.long 0x00 11. " OL_TX ,Enable open-loop mode for TX._0: Disabled (default)_1: Enabled" "0,1" bitfld.long 0x00 10. " OL_RX ,Enable open-loop mode for RX._0: Disabled (default)_1: Enabled" "0,1" bitfld.long 0x00 9. " PWR_MODE_TX ,Power mode option to be used in TX._0: Low power (default)_1: High performance" "0,1" textline " " bitfld.long 0x00 8. " PWR_MODE_RX ,Power mode option to be used in RX._0: Low power (default)_1: High performance" "0,1" bitfld.long 0x00 1. " IF_MODE_TX ,IF mode option to be used in TX._0: 1 Mbps (default)_1: 2 Mbps" "0,1" bitfld.long 0x00 0. " IF_MODE_RX ,IF mode option to be used in RX._0: 1 Mbps (default)_1: 2 Mbps" "0,1" group.long 0x4++0x3 line.long 0x00 "ADPLL_CN_CTRL_REG," hexmask.long.word 0x00 16.--28. 1. " CH0 ,Channel 0 frequency in MHz (CH0) (ufix13)_default: 2402" bitfld.long 0x00 15. " SGN ,Sign bit for the channel step_0: positive (default)_1: negative" "0,1" bitfld.long 0x00 8. " CS ,Channel spacing._0: 1 MHz spacing_1: 2 MHz spacing (default)" "0,1" textline " " hexmask.long.byte 0x00 0.--6. 1. " CN ,Channel number._Default: 0" group.long 0x20++0x3 line.long 0x00 "ADPLL_DCOAMP_CAL_CTRL_REG," bitfld.long 0x00 28.--31. " DCOAMPIC_LP_TX ,Initial condition for the DCO amplitude setting, for Low Power TX mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DCOAMPIC_LP_RX ,Initial condition for the DCO amplitude setting, for Low Power RX mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " DCOAMPIC_HP_TX ,Initial condition for the DCO amplitude setting, for High Performance TX mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " DCOAMPIC_HP_RX ,Initial condition for the DCO amplitude setting, for High Performance RX mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " DCOAMPTM ,Time spend to perform DCO amplitude calibration_0: 1 us_1: 2 us" "0,1" bitfld.long 0x00 6. " AMPCALEN ,Enable DCO amplitude calibration" "0,1" textline " " bitfld.long 0x00 3.--5. " KMEDIUM ,Proportional gain setting for medium tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " KCOARSE ,Proportional gain setting for coarse tuning" "0,1,2,3,4,5,6,7" group.long 0x80++0x3 line.long 0x00 "ADPLL_DCO_RD_REG," rbitfld.long 0x00 26.--29. " DCOAMP ,DCO amplitude setting._The read value is the output of adplldig (towards the analog). So, the read value is even after the overruling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 13.--25. 1. " DCOMOD ,Current state of the DCO mod capacitor bank_(signed)_The open-loop output (before the addition of modulated data). So, it is after averaging, before SDM and addition of the modulated data" rbitfld.long 0x00 7.--12. " DCOFINE ,Current state of the DCO fine capacitor bank_(signed)_ACC outputs are read (the averaged values.)_For CMF we are reading before bin2thm conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 4.--6. " DCOMEDIUM ,Current state of the DCO medium capacitor bank_(signed)_ACC outputs are read (the averaged values.)_For CMF we are reading before bin2thm conversion" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--3. " DCOCOARSE ,Current state of the DCO coarse capacitor bank_(signed)_ACC outputs are read (the averaged values.)_For CMF we are reading before bin2thm conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "ADPLL_DIV_CTRL_REG," hexmask.long.word 0x00 17.--25. 1. " TXDIV_TRIM ,Tx divider trim value" hexmask.long.word 0x00 8.--16. 1. " RXDIV_TRIM ,Rx divider trim value" bitfld.long 0x00 2. " RXDIV_FB_EN_TX ,Enable rxdiv for FB in TX mode._0: Disable (default)_1: Enable" "0,1" textline " " bitfld.long 0x00 1. " RXDIV_FB_EN_RX ,Enable rxdiv for FB in RX mode._0: Disable (default)_1: Enable" "0,1" bitfld.long 0x00 0. " FBDIV_EN ,Feedback divider enable_1: Enabled_0: Disabled.__If diabled both feedback and RF output clock will be disabled. This bit is intended for test purposes (not for normal usage)" "0,1" group.long 0x8++0x3 line.long 0x00 "ADPLL_FIF_CTRL1_REG," hexmask.long.word 0x00 16.--29. 1. " FIFRX_2M ,IF frequency (in MHz) used in 2 Mbps RX mode_sfix(14,10) - 1 bit sign, 3 bits integer, 10 bits fractional for MHz unit" hexmask.long.word 0x00 0.--13. 1. " FIFRX_1M ,IF frequency (in MHz) used in 1 Mbps RX mode_sfix(14,10) - 1 bit sign, 3 bits integer, 10 bits fractional for MHz unit" group.long 0xC++0x3 line.long 0x00 "ADPLL_FIF_CTRL2_REG," hexmask.long.word 0x00 16.--29. 1. " FIFTX ,IF frequency (in MHz) used in TX mode_sfix(14,10) - 1 bit sign, 3 bits integer, 10 bits fractional for MHz unit" hexmask.long.word 0x00 0.--13. 1. " FIFRX_OFFSET ,Offset for the IF frequency (in MHz) in RX mode._sfix(14,10) - 1 bit sign, 3 bits integer, 10 bits fractional for MHz unit" group.long 0x7C++0x3 line.long 0x00 "ADPLL_FREQMEAS_RD_REG," rbitfld.long 0x00 30. " DCOAMPDET_ASYNC ,DCO amplitude detector input (Used for amplitude calibration)" "0,1" rbitfld.long 0x00 29. " MEASDONE_OUT ,Signal indicating the state of the frequency counter_0: Measuring frequency_1: Measurement done" "0,1" rbitfld.long 0x00 26. " QUALMONDET ,Clock quality monitoring detector output" "0,1" textline " " rbitfld.long 0x00 25. " TDCBUB ,Detector output indicating a bubble error in the TDC input" "0,1" rbitfld.long 0x00 24. " PHVSA0 ,Detector output indicating a stuck-at 0 on the variable phase accumulator input" "0,1" rbitfld.long 0x00 23. " PHVSA1 ,Detector output indicating a stuck-at 1 on the variable phase accumulator input" "0,1" textline " " hexmask.long.tbyte 0x00 0.--22. 1. " FREQDIFF ,Measurend frequency difference (signed)" group.long 0x40++0x3 line.long 0x00 "ADPLL_FSM_CTRL_REG," bitfld.long 0x00 24.--29. " TVPASETTLE ,Settling time required after vpa disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--23. " TSETTLE ,Time spend waiting for settling_0 - 15: 0 - 7.5 us (t = TSETTLE/2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TPASETTLE ,Time spend waiting for PA to settle_0 - 15: 0 - 7.5 us (t = TPASETTLE/2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " TMOD ,Time spend for fine tuning_0 - 15: 0 - 15 us (t = TMOD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFINE ,Time spend for fine tuning_0 - 15: 0 - 15 us (t = TFINE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " TMEDIUM ,Time spend for medium tuning_0 - 15: 0 - 7.5 us (t = TMEDIUM/2)_If < 1 us and amplitude calibration is enabled TMEDIUM = 1 us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " TCOARSE ,Time spend for coarse tuning_0 - 15: 0 - 7.5 us (t = TCOARSE/2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "ADPLL_INIT_CTRL_REG," hexmask.long.word 0x00 16.--28. 1. " DCOMODIC ,Initial condition for fine cap bank._(signed)" bitfld.long 0x00 8.--13. " DCOFINEIC ,Initial condition for fine cap bank._(signed)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4.--6. " DCOMEDIUMIC ,Initial condition for medium cap bank._(signed)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " DCOCOARSEIC ,Initial condition for coarse cap bank._(signed)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "ADPLL_KDCO_CAL_CTRL1_REG," hexmask.long.byte 0x00 24.--31. 1. " KDCOLF_IN_2M ,Gain setting for the low frequency path in case of not using the calibrated KDCOHF for 2M mode (uint8)" hexmask.long.byte 0x00 16.--23. 1. " KDCOLF_IN_1M ,Gain setting for the low frequency path in case of not using the calibrated KDCOHF for 1M mode (uint8)" hexmask.long.byte 0x00 8.--15. 1. " KDCOHFIC_2M ,Initial gain setting for the high frequency path for 2M mode (uint8)" textline " " hexmask.long.byte 0x00 0.--7. 1. " KDCOHFIC_1M ,Initial gain setting for the high frequency path for 1M mode (uint8)" group.long 0x14++0x3 line.long 0x00 "ADPLL_KDCO_CAL_CTRL2_REG," bitfld.long 0x00 30.--31. " KDCOESTDEV ,Frequency deviation used for KDCO estimation:_0: 500 kHz_1: 250 kHz (default)_2: 125 kHz_3: 62.5 kHz" "0,1,2,3" bitfld.long 0x00 29. " KDCOCALTX ,Enable for KDCO calibration in transmit mode" "0,1" bitfld.long 0x00 28. " KDCOCALRX ,Enable for KDCO calibration in receive mode" "0,1" textline " " bitfld.long 0x00 27. " KDCOLFCALEN ,Enable the use of the (calibrated) value for KDCOHF for the low frequency path" "0,1" bitfld.long 0x00 24.--26. " TKDCOCAL ,Time spend for KDCO calibration settling:_0: 0.5 us 16_1: 1 us 32_2: 2 us 64_3: 4 us 128_4: 8 us" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--22. 1. " KDCOCN_IC ,Initial condition for channel number related to calibration result" textline " " bitfld.long 0x00 8.--12. " KMOD_ALPHA_2M ,KDCOHF channel dependent trimming constant for 2M mode._0: No trimming._>0: KDCOHF is modified with a factor: 1-SGNx(KMOD_ALPHA_2M)x(CN-CN_CAL_RD)/4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " KMOD_ALPHA_1M ,KDCOHF channel dependent trimming constant for 1M mode._0: No trimming._>0: KDCOHF is modified with a factor: 1-SGNx(KMOD_ALPHA_1M)x(CN-CN_CAL_RD)/4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x3 line.long 0x00 "ADPLL_KDCO_RD_REG," rbitfld.long 0x00 23. " CAL_KDCOCAL ,Calibration state of the KDCO calibration" "0,1" hexmask.long.byte 0x00 16.--22. 1. " KDCOCN ,Channel number related to calibration result" hexmask.long.byte 0x00 8.--15. 1. " KDCO_HF_OUT ,kmod_alpha compensated KDCO gain" textline " " hexmask.long.byte 0x00 0.--7. 1. " KDCO_HF_INT ,KDCO gain" group.long 0x18++0x3 line.long 0x00 "ADPLL_KDTCTDC_CAL_CTRL1_REG," hexmask.long.word 0x00 23.--31. 1. " KDTCIC ,Initial condition for the DTC gain correction" hexmask.long.byte 0x00 16.--22. 1. " KDTCCN_IC ,Initial condition for channel number related to calibration result" bitfld.long 0x00 15. " KDTC_PIPELINE_BYPASS ,Bypass the extra register on prv_phr" "0,1" textline " " hexmask.long.word 0x00 6.--14. 1. " KTDC_IN ,TDC gain setting in case of not using the calibrated gain setting" bitfld.long 0x00 0.--5. " KDTC_ALPHA ,KDTC channel dependent trimming constant._0: No trimming._>0: KDTC is modified with a factor: 1-SGNx(KDTC_ALPHA)x(CN-CN_CAL_RD)/16384" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "ADPLL_KDTCTDC_CAL_CTRL2_REG," bitfld.long 0x00 15. " PHRDLY_EXTRA ," "0,1" bitfld.long 0x00 11.--14. " TKDTCCAL ,Time spend waiting for DTC calibration (0-15) 0 - 15 us t = tkdtccal/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9.--10. " PHRDLY ,Delay phr used for kdtc calibration by 1-4 samples, default: 3 samples (2)" "0,1,2,3" textline " " bitfld.long 0x00 8. " KTDCCALEN ,Enable calibration of TDC via DTC calibration" "0,1" bitfld.long 0x00 4.--6. " KDTCCALLG ,Loopgain setting used for DTC calibration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " KDTCCAL_INV ,Invert sign of kdtc calibration loop (default: 0)" "0,1" textline " " bitfld.long 0x00 2. " KDTCCALMOD1P ,Chicken bit to change phase of KDTC cal mode 1 phase" "0,1" bitfld.long 0x00 1. " KDTCCALMOD ,Mode select for KDTC alogrithm:_0: Just-in-time algorithm (least intrusive)_1: Interger lock to Fref/2 and use second clock phase for calibration (no issue with local optimum)" "0,1" bitfld.long 0x00 0. " KDTCCALEN ,Enable DTC calibration" "0,1" group.long 0x88++0x3 line.long 0x00 "ADPLL_KDTC_RD_REG," rbitfld.long 0x00 25. " CAL_KDTCCAL ,Calibration state of the KDTC calibration" "0,1" hexmask.long.word 0x00 16.--24. 1. " KDTC_ALPHA_COMP ,KDTC_ALPHA compensated DTC gain setting. Used as TDC gain setting used to correct loopgain" hexmask.long.byte 0x00 9.--15. 1. " KDTCCN ,Channel number related to calibration result" textline " " hexmask.long.word 0x00 0.--8. 1. " KDTC_OUT ,DTC gain setting updated in tuning state 13. Used for register readback" group.long 0x2C++0x3 line.long 0x00 "ADPLL_LF_CTRL1_REG," bitfld.long 0x00 10.--15. " FINEKZ ,Corner frequency setting of the first order low-pass filter that is used for tuning the fine bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5.--9. " FINEK ,Loopfilter loopgain frequency during fine tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " FINETAU ,First order low-pass filter c.rst_ner frequency during fine tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "ADPLL_LF_CTRL2_REG," bitfld.long 0x00 30. " RST_TAU_EN ,Enable state machine to control reset of tau filter" "0,1" bitfld.long 0x00 24.--29. " MODKZ ,Loopgain setting of the loop-filter that is used for tuning the MOD bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " MODK ,Corner frequency setting of the zero filter that is used for tuning the MOD bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 12.--17. " MODTAU ,Corner frequency setting of the first order low-pass filter that is used for tuning the MOD bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " MODK_TUNE ,Loopfilter loopgain frequency during mod tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MODTAU_TUNE ,First order low-pass filter c.rst_ner frequency during mod tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x3 line.long 0x00 "ADPLL_MISC_CTRL_REG," hexmask.long.tbyte 0x00 8.--24. 1. " PHR_FRAC_PRESET_VAL ,Controls the set level of the DCO amplitude detector" bitfld.long 0x00 7. " ENFCWMOD ,Enable two point modulation" "0,1" bitfld.long 0x00 6. " ENRESIDUE ,Enable residue correction" "0,1" textline " " bitfld.long 0x00 4.--5. " MODDLY ,Delay modulation (injected at the capcitor bank) by 0-3 samples" "0,1,2,3" bitfld.long 0x00 2.--3. " RESDLY ,Delay residue by 0-3 samples" "0,1,2,3" bitfld.long 0x00 0.--1. " DLYFCWDT ,Delay reference path of the two point modulation" "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "ADPLL_MON_CTRL_REG," bitfld.long 0x00 30. " QUALMONFRCEN ,Force enable of the clock quality monitor" "0,1" bitfld.long 0x00 24.--29. " QUALMONTRHLD ,Clock quality monitoring threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " QUALMONWND ,Clock quality monitoring window length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 16.--17. " QUALMONMOD ,Clock quality monitoring mode:_0: Highpass output_1: TDC_2: Lowpass output_3: Loop filter output" "0,1,2,3" bitfld.long 0x00 8.--11. " HOLD_STATE ,Set a break point at which the tuning state machine will hold it's state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " RFMEAS_MODE ,RF measurement mode for the Divider calibrations._0 : Jerzy RF measurement._1 (default): RF measurement for divider calibration" "0,1" textline " " bitfld.long 0x00 6. " ENRFMEAS ,Enable open loop frequency measurement" "0,1" bitfld.long 0x00 5. " TMREN ,Enable timer for measuring PLL settling time" "0,1" bitfld.long 0x00 0.--4. " TFREQMEAS ,Frequency measurement time_Two lsb's form the linear part, the three MSB's are the exponent_Time [us] = 0.5+((4+lin)*(2^(exp-1)))_tfreqmeas Time [us]_0: 2.5_1: 3_2: 3.5_3: 4_4: 4.5_5: 5.5_6: 6.5_7: 7.5_8: 8.5_9: 10.5_10: 12.5_11: 14.5_12: 16.5_13: 20.5_14: 24.5_15: 28.5_16: 32.5_17: 40.5_18: 48.5_19: 56.5_20: 64.5_21: 80.5_22: 96.5_23: 112.5_24: 128.5_25: 160.5_26: 192.5_27: 224.5_28: 256.5_29: 320.5_30: 384.5_31: 448.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x3 line.long 0x00 "ADPLL_OL_CTRL_REG," rbitfld.long 0x00 31. " OL_RDY ,Read out openloop_rdy output before gating with rxbit status" "0,1" bitfld.long 0x00 27.--30. " NAVG_OL ,Averaging ratio. Division for averaging: 2NAVG_OL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 18.--26. 1. " TAVG_OL ,Number of dcomod samples to be averaged._TAVG_OL = 2NAVG_OL)" textline " " hexmask.long.word 0x00 8.--17. 1. " TSETTLE_OL ,Number of clocks cycles to wait for dcomod to settle, before starting averaging for open loop mode" bitfld.long 0x00 2. " TXDIV_EN_OL_RX ,txdiv_en value to be used in open loop mode when in RX" "0,1" bitfld.long 0x00 1. " FBDIV_EN_OL_RX ,fbdiv_en value to be used in open loop mode when in RX" "0,1" textline " " bitfld.long 0x00 0. " RXDIV_FB_EN_OL_RX ,rxdiv_fb_en value to be used in open loop mode when in RX" "0,1" group.long 0x50++0x3 line.long 0x00 "ADPLL_OVERRULE_CTRL1_REG," hexmask.long.byte 0x00 25.--31. 1. " OVR_DTC_OH_WR ,Overrule value (binary) for the dtc_oh" bitfld.long 0x00 24. " OVR_DTC_OH_SEL ,Overrule dtc_oh output._0: Normal function (default)_1: Overrule dtc_oh output by OVR_DTC_OH_WR" "0,1" bitfld.long 0x00 17.--20. " OVR_DCOAMP_WR ,Overrule value for the dcoamp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16. " OVR_DCOAMP_SEL ,Overrule dcoamp output._0: Normal function (default)_1: Overrule dcoamp output by OVR_DCOAMP_WR" "0,1" bitfld.long 0x00 13. " OVR_DCOAMPHOLD_WR ,Overrule value for the dcoamp_hold." "0,1" bitfld.long 0x00 12. " OVR_DCOAMPHOLD_SEL ,Overrule dcoamphold output._0: Normal function (default)_1: Overrule dcoamphold output by OVR_DCOAMPHOLD_WR" "0,1" textline " " bitfld.long 0x00 11. " OVR_RDYFORDIV_WR ,Overrule value for the rdy_for_div input" "0,1" bitfld.long 0x00 10. " OVR_RDYFORDIV_SEL ,Overrule rdy_for_div input._0: Normal function (default)_1: Overrule rdy_for_div input by OVR_RDYFORDIV_WR" "0,1" bitfld.long 0x00 9. " OVR_VPAEN_WR ,Overrule value for the vpa_en" "0,1" textline " " bitfld.long 0x00 8. " OVR_VPAEN_SEL ,Overrule vpaen._0: Normal function (default)_1: Overrule vpaen by OVR_VPAEN_WR" "0,1" bitfld.long 0x00 7. " OVR_SRESETN_WR ,Overrule value for the sreset_n" "0,1" bitfld.long 0x00 6. " OVR_SRESETN_SEL ,Overrule sreset_n of the modulator._0: Normal function (default)_1: Overrule sreset_n by OVR_SRESETN_WR" "0,1" textline " " bitfld.long 0x00 5. " OVR_ENPAIN_WR ,Overrule value for the enpain" "0,1" bitfld.long 0x00 4. " OVR_ENPAIN_SEL ,Overrule enpain input._0: Normal function (default)_1: Overrule enpain input by OVR_ENPAIN_WR" "0,1" bitfld.long 0x00 3. " OVR_RXBIT_WR ,Overrule value for the rxbit" "0,1" textline " " bitfld.long 0x00 2. " OVR_RXBIT_SEL ,Overrule rxbit input._0: Normal function (default)_1: Overrule rxbit input by OVR_RXBIT_WR" "0,1" bitfld.long 0x00 1. " OVR_ACTIVE_WR ,Overrule value for the active" "0,1" bitfld.long 0x00 0. " OVR_ACTIVE_SEL ,Overrule active input._0: Normal function (default)_1: Overrule active input by OVR_ACTIVE_WR" "0,1" group.long 0x54++0x3 line.long 0x00 "ADPLL_OVERRULE_CTRL2_REG," hexmask.long.byte 0x00 24.--31. 1. " OVR_DCOMOD_WR ,Overrule value (binary) for the internal dcomod" bitfld.long 0x00 23. " OVR_DCOMOD_SEL ,Overrule dcomod output._0: Normal function (default)_1: Overrule dcomod output by OVR_DCOMOD_WR" "0,1" bitfld.long 0x00 17.--22. " OVR_DCOFINE_WR ,Overrule value (binary) for the internal dcofine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 16. " OVR_DCOFINE_SEL ,Overrule dcomod output._0: Normal function (default)_1: Overrule dcomod output by OVR_DCOFINE_WR" "0,1" bitfld.long 0x00 9.--11. " OVR_DCOMEDIUM_WR ,Overrule value (binary) for the internal dcomedium" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8. " OVR_DCOMEDIUM_SEL ,Overrule dcomod output._0: Normal function (default)_1: Overrule dcomod output by OVR_DCOMEDIUM_WR" "0,1" textline " " bitfld.long 0x00 1.--4. " OVR_DCOCOARSE_WR ,Overrule value (binary) for the internal dcocoarse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OVR_DCOCOARSE_SEL ,Overrule dcomod output._0: Normal function (default)_1: Overrule dcomod output by OVR_DCOCOARSE_WR" "0,1" group.long 0x58++0x3 line.long 0x00 "ADPLL_OVERRULE_CTRL3_REG," bitfld.long 0x00 11. " OVR_OPENLOOP_RDY_INT_WR ,Overrule value for the internal openloop_rdy" "0,1" bitfld.long 0x00 10. " OVR_OPENLOOP_RDY_INT_SEL ,Overrule internal openloop_rdy._0: Normal function (default)_1: Overrule internal openloop_rdy by OVR_OPENLOOP_RDY_INT_WR" "0,1" bitfld.long 0x00 9. " OVR_OPENLOOP_RDY_WR ,Overrule value for the openloop_rdy output" "0,1" textline " " bitfld.long 0x00 8. " OVR_OPENLOOP_RDY_SEL ,Overrule openloop_rdy output._0: Normal function (default)_1: Overrule openloop_rdy output by OVR_OPENLOOP_RDY_WR" "0,1" bitfld.long 0x00 7. " OVR_RXDIV_FB_EN_WR ,Overrule value for the rxdiv_fb_en output" "0,1" bitfld.long 0x00 6. " OVR_RXDIV_FB_EN_SEL ,Overrule rxdiv_fb_en output._0: Normal function (default)_1: Overrule rxdiv_fb_en output by OVR_RXDIV_FB_EN_WR" "0,1" textline " " bitfld.long 0x00 5. " OVR_FBDIV_EN_WR ,Overrule value for the fbdiv_en output" "0,1" bitfld.long 0x00 4. " OVR_FBDIV_EN_SEL ,Overrule fbdiv_en output._0: Normal function (default)_1: Overrule fbdiv_en output by OVR_FBDIV_EN_WR" "0,1" bitfld.long 0x00 3. " OVR_TXDIV_EN_WR ,Overrule value for the txdiv_en output" "0,1" textline " " bitfld.long 0x00 2. " OVR_TXDIV_EN_SEL ,Overrule txdiv_en output._0: Normal function (default)_1: Overrule txdiv_en output by OVR_TXDIV_EN_WR" "0,1" bitfld.long 0x00 1. " OVR_RXDIV_EN_WR ,Overrule value for the rxdiv_en output" "0,1" bitfld.long 0x00 0. " OVR_RXDIV_EN_SEL ,Overrule rxdiv_en._0: Normal function (default)_1: Overrule rxdiv_en output by OVR_RXDIV_EN_WR" "0,1" group.long 0x90++0x3 line.long 0x00 "ADPLL_PLLFCWDT_RD_REG," hexmask.long.tbyte 0x00 0.--22. 1. " PLLFCWDT ,PLLFCWDT" group.long 0x5C++0x3 line.long 0x00 "ADPLL_RFPT_CTRL_REG," bitfld.long 0x00 5.--6. " RFPT_RATE ,RFPT rate setting_0: 32MSPS_1: 16 MSPS" "0,1,2,3" bitfld.long 0x00 4. " INV_CKRFPT ,Invert clock registering output of the RFPT interface.__Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" "0,1" bitfld.long 0x00 0.--3. " RFPT_MUX ,Multiplexer setting for RFPT interface output._The following data will be provided to the rfpt interface:_0: RFPT disabled (default)_1: {tdc_invert,tdc_b,tdc_t_reg}_2: {8'd0, dcocoarse, 1'd0,dcomedium, 2'd0,dcofine, dcomod_sdm}_3: {2'd0, phe_int, 1'd0,phv_int, 1'd0,phr_int0, phe_int_int}_4: {lfout_int,lfout_frac,int_state,lpout,kdtc_int}_5, ..., 15: Reserved.___Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "ADPLL_SDMOD_CTRL_REG," bitfld.long 0x00 8.--10. " SDMMODERX_OL ,Open Loop Sigma delta modulator mode :_0: Disabled_1: MASH I_3: MASH II_5: MASH I + with dithering_7: MASH II + with dithering" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " SDMMODETX ,Sigma delta modulator mode :_0: Disabled_1: MASH I_3: MASH II_5: MASH I + with dithering_7: MASH II + with dithering" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " SDMMODERX ,Sigma delta modulator mode :_0: Disabled_1: MASH I_3: MASH II_5: MASH I + with dithering_7: MASH II + with dithering" "0,1,2,3,4,5,6,7" group.long 0x8C++0x3 line.long 0x00 "ADPLL_TUNESTATE_RD_REG," hexmask.long.word 0x00 4.--13. 1. " TMRVAL ,Current timer value. Timer can be used to determine PLL settling time and is used for frequency measurement" rbitfld.long 0x00 0.--3. " TUNE_STATE ,Binary coded state of the tuning state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "ADPLL_TXMOD_CTRL_REG," bitfld.long 0x00 8. " INV_CKMODEXT ,Invert the clock, which captures the external modulated data" "0,1" bitfld.long 0x00 6.--7. " TX_MODE ,Two-point modulation MUX:_0,3: mod_hf = mod_in_mod_lf = mod_in_1: mod_hf = 0_mod_lf = mod_in_2: mod_hf = mod_in_mod_lf = 0" "0,1,2,3" bitfld.long 0x00 5. " MOD_EXT_SEL ,0: Normal operation_1: User externally provided value for the modulation" "0,1" textline " " bitfld.long 0x00 4. " EO_PACKET_DIS ,The block will normally detect the end of a data packet by the missing tx_data_en pulses._The outputs will be smoothly return to zero when an end of a data packet has been deteted._The end of a data packet detected can be disabled by setting eo_packet_dis = 1. This is_normally/never used and eo_packet_dis should always be set to zero" "0,1" bitfld.long 0x00 2.--3. " MOD_INDEX ,Modulation index selection:_0: h = 1/2 (dF = 250 kHz)_1 h = 1/4 (dF = 125 kHz):_2: h = 17/32 (dF = 266 kHz)_3: h = 35/64 (dF = 273 kHz)" "0,1,2,3" bitfld.long 0x00 1. " TX_DATA_INV ,Select polarity of the modulation prior to pulse shaping_0: Normal operation_1: Invert modulation signal" "0,1" textline " " bitfld.long 0x00 0. " BT_SEL ,The BT product for the Gaussian pulse can take the values 0.5 or 0.6._0: BT = 0.5_1: BT = 0.6" "0,1" width 0x0B tree.end tree "AES_HASH" base ad:0x30040000 width 23. group.long 0x18++0x3 line.long 0x00 "CRYPTO_CLRIRQ_REG,Crypto Clear interrupt request" bitfld.long 0x00 0. " CRYPTO_CLRIRQ ,Write 1 to clear a pending interrupt request" "0,1" group.long 0x0++0x3 line.long 0x00 "CRYPTO_CTRL_REG,Crypto Control register" bitfld.long 0x00 17. " CRYPTO_AES_KEXP ,It forces (active high) the execution of the key expansion process with the starting of the AES encryption/decryption process. The bit will be cleared automatically by the hardware, after the completion of the AES key expansion process" "0,1" bitfld.long 0x00 16. " CRYPTO_MORE_IN ,0 : Define that this is the last input block. When the current input is consumed by the crypto engine and the output data is written to the memory, the calculation ends (CRYPTO_INACTIVE goes to one)._1 : The current input data block is not the last. More input data will follow. When the current input is consumed, the engine stops and waits for more data (CRYPTO_WAIT_FOR_IN goes to one)" "0,1" bitfld.long 0x00 10.--15. " CRYPTO_HASH_OUT_LEN ,The number of bytes minus one of the hash result which will be saved at the memory by the DMA. In relation with the selected hash algorithm the accepted values are:_MD5: 0..15 -> 1-16 bytes_SHA-1: 0..19 -> 1-20 bytes_SHA-256: 0..31 -> 1 - 32 bytes_SHA-256/224: 0..27 -> 1- 28 bytes_SHA-384: 0..47 -> 1 - 48 bytes_SHA-512: 0..63 -> 1 - 64 bytes_SHA-512/224: 0..27 -> 1- 28 bytes_SHA-512/256: 0..31 -> 1 - 32 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 9. " CRYPTO_HASH_SEL ,Selects the type of the algorithm_0 : The encryption algorithm (AES)_1 : A hash algorithm._The exact algorithm is defined by the fileds CRYPTO_ALG and CRYPTO_ALG_MD" "0,1" bitfld.long 0x00 8. " CRYPTO_IRQ_EN ,Interrupt Request Enable_0 : The interrupt generation ability is disabled._1 : The interrupt generation ability is enabled. Generates an interrupt request at the end of operation" "0,1" bitfld.long 0x00 7. " CRYPTO_ENCDEC ,Encryption/Decryption_0 : Decryption_1 : Encryption" "0,1" textline " " bitfld.long 0x00 5.--6. " CRYPTO_AES_KEY_SZ ,The size of AES Key_0x0 : 128 bits AES Key_0x1 : 192 bits AES Key_0x2 : 256 bits AES Key_0x3 : 256 bits AES Key" "0,1,2,3" bitfld.long 0x00 4. " CRYPTO_OUT_MD ,Output Mode. This field makes sense only when the AES algorithm is selected (CRYPTO_HASH_SEL =0)_0 : Write back to memory all the resulting data_1 : Write back to memory only the final block of the resulting data" "0,1" bitfld.long 0x00 2.--3. " CRYPTO_ALG_MD ,It defines the mode of operation of the AES algorithm when the controller is configured for an encryption/decryption processing (CRYPTO_HASH_SEL = 0)._0x0 : ECB_0x1 : ECB_0x2 : CTR_0x3 : CBC__When the controller is configured to applies a HASH function, this field selects the desired HASH algorithm with the help of the CRYPTO_ALG.__0x0 : HASH algorithms that are based on 32 bits operations_0x1 : HASH algorithms that are based on 64 bits operations_0x2 : Reserved_0x3 : Reserved__See also the CRYPTO_ALG field" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " CRYPTO_ALG ,Algorithm selection. When CRYPTO_HASH_SEL = 0 the only available choice is the AES algorithm._0x0 : AES_0x1 : Reserved_0x2 : Reserved_0x3 : Reserved__When CRYPTO_HASH_SEL = 1, this field selects the desired hash algorithm, with the help of the CRYPTO_ALG_MD field.__If CRYPTO_ALG_MD = 0x0_0x0 : MD5_0x1 : SHA-1_0x2 : SHA-256/224_0x3 : SHA-256__If CRYPTO_ALG_MD = 0x1_0x0 : SHA-384_0x1 : SHA-512_0x2 : SHA-512/224_0x3 : SHA-512/256" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "CRYPTO_DEST_ADDR_REG,Crypto DMA destination memory" hexmask.long 0x00 0.--31. 1. " CRYPTO_DEST_ADDR ,Destination address at where the result of the processing is stored. The value of this register is updated as the calculation proceeds and the output data are written to the memory" group.long 0x8++0x3 line.long 0x00 "CRYPTO_FETCH_ADDR_REG,Crypto DMA fetch register" hexmask.long 0x00 0.--31. 1. " CRYPTO_FETCH_ADDR ,The memory address from where will be retrieved the data that will be processed. The value of this register is updated as the calculation proceeds and the output data are written to the memory" group.long 0x100++0x3 line.long 0x00 "CRYPTO_KEYS_START,Crypto First position of the AES keys storage memory" hexmask.long 0x00 0.--31. 1. " CRYPTO_KEY_X ,CRYPTO_KEY_(0-63)_This is the AES keys storage memory. This memory is accessible via AHB slave interface, only when the CRYPTO is inactive (CRYPTO_INACTIVE = 1)" group.long 0xC++0x3 line.long 0x00 "CRYPTO_LEN_REG,Crypto Length of the input block in bytes" hexmask.long.tbyte 0x00 0.--23. 1. " CRYPTO_LEN ,It contains the number of bytes of input data. If this number is not a multiple of a block size, the data is automatically extended with zeros. The value of this register is updated as the calculation proceeds and the output data are written to the memory" group.long 0x1C++0x3 line.long 0x00 "CRYPTO_MREG0_REG,Crypto Mode depended register 0" hexmask.long 0x00 0.--31. 1. " CRYPTO_MREG0 ,It contains information that are depended by the mode of operation, when is used the AES algorithm:_CBC - IV[31:0]_CTR - CTRBLK[31:0]. It is the initial value of the 32 bits counter._At any other mode, the contents of this register has no meaning" group.long 0x20++0x3 line.long 0x00 "CRYPTO_MREG1_REG,Crypto Mode depended register 1" hexmask.long 0x00 0.--31. 1. " CRYPTO_MREG1 ,It contains information that are depended by the mode of operation, when is used the AES algorithm:_CBC - IV[63:32]_CTR - CTRBLK[63:32]_At any other mode, the contents of this register has no meaning" group.long 0x24++0x3 line.long 0x00 "CRYPTO_MREG2_REG,Crypto Mode depended register 2" hexmask.long 0x00 0.--31. 1. " CRYPTO_MREG2 ,It contains information that are depended by the mode of operation, when is used the AES algorithm:_CBC - IV[95:64]_CTR - CTRBLK[95:64]_At any other mode, the contents of this register has no meaning" group.long 0x28++0x3 line.long 0x00 "CRYPTO_MREG3_REG,Crypto Mode depended register 3" hexmask.long 0x00 0.--31. 1. " CRYPTO_MREG3 ,It contains information that are depended by the mode of operation, when is used the AES algorithm:_CBC - IV[127:96]_CTR - CTRBLK[127:96]_At any other mode, the contents of this register has no meaning" group.long 0x4++0x3 line.long 0x00 "CRYPTO_START_REG,Crypto Start calculation" bitfld.long 0x00 0. " CRYPTO_START ,Write 1 to initiate the processing of the input data. This register is auto-cleared" "0,1" group.long 0x14++0x3 line.long 0x00 "CRYPTO_STATUS_REG,Crypto Status register" rbitfld.long 0x00 2. " CRYPTO_IRQ_ST ,The status of the interrupt request line of the CRYPTO block._0 : There is no active interrupt request._1 : An interrupt request is pending" "0,1" rbitfld.long 0x00 1. " CRYPTO_WAIT_FOR_IN ,Indicates the situation where the engine waits for more input data. This is applicable when the CRYPTO_MORE_IN= 1, so the input data are fragmented in the memory._0 : The crypto is not waiting for more input data._1 : The crypto waits for more input data._The CRYPTO_INACTIVE flag remains to zero to indicate that the calculation is not finished. The supervisor of the CRYPTO must program to the CRYPTO_FETCH_ADDR and CRYPTO_LEN a new input data fragment. The calculation will be continued as soon as the CRYPTO_START register will be written with 1. This action will clear the CRYPTO_WAIT_FOR_IN flag" "0,1" rbitfld.long 0x00 0. " CRYPTO_INACTIVE ,0 : The CRYPTO is active. The processing is in progress._1 : The CRYPTO is inactive. The processing has finished" "0,1" width 0x0B tree.end tree "ANAMISC" base ad:0x50030B00 width 17. group.long 0x0++0x3 line.long 0x00 "ANA_TEST_REG,Analog test registers" bitfld.long 0x00 0.--3. " TEST_STRUCTURE ,4 bits to select which test-structure is mapped on P1[7]_0 : open_1 : VDD (1.2V)_2 : 10uA into 66k = 5/3 x 40k (W/L=0.45/22.33)_3 : 1uA into 700k = 18.5 x 40k (W/L=0.45/22.33)_4 : 1uA(same as going into 700k)_5 : AVS (0V)_6 : 5uA into nMOST (svt) 2x1u/110n_7 : 5uA into nMOST (hvt) 2x1u/110n_8 : 5uA into nMOST (UD18) 2x1u/260n_9 : 5uA into nMOST (OD33) 2x1u/500n_a : 7.5uA into nMOST (na25) 4x1u/1.2u_b : 5uA into nMOST (0vt) 4x1u/300n_c : VDD - 5uA from pMOST (svt) 2x1u/110n_d : VDD - 5uA from pMOST (hvt) 2x1u/110n_e : VDD - 5uA from pMOST (OD33) 2x1u/400n_f : VDD - 5uA from pMOST (UD18) 2x1u/260n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x3 line.long 0x00 "CLK_REF_CNT_REG,Count value for oscillator calibration" hexmask.long.word 0x00 0.--15. 1. " REF_CNT_VAL ,Indicates the calibration time, with a decrement counter to 1." group.long 0x10++0x3 line.long 0x00 "CLK_REF_SEL_REG,Select clock for oscillator calibration" bitfld.long 0x00 5.--7. " CAL_CLK_SEL ,Select reference clock input to be used in calibration:_0x0 : DIVN clock_0x1 : RC32K_0x2 : RC32M_0x3 : XTAL32K_0x4 : RCOSC_0x5, 0x6, 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " EXT_CNT_EN_SEL ,0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL._1 : Enable XTAL_CNT counter from an external input" "0,1" bitfld.long 0x00 3. " REF_CAL_START ,Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready." "0,1" textline " " bitfld.long 0x00 0.--2. " REF_CLK_SEL ,Select clock input for calibration:_0x0 : RC32K_0x1 : RC32M_0x2 : XTAL32K_0x3 : RCX_0x4 : RCOSC" "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x00 "CLK_REF_VAL_REG,DIVN reference cycles, lower 16 bits" hexmask.long 0x00 0.--31. 1. " XTAL_CNT_VAL ,Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL" width 0x0B tree.end tree "APU" base ad:0x50030600 width 17. group.long 0x1C++0x3 line.long 0x00 "APU_MUX_REG,APU mux register" bitfld.long 0x00 6. " PDM1_MUX_IN ,PDM1 input mux_0 = SRC1_MUX_IN_1 = PDM input" "0,1" bitfld.long 0x00 3.--5. " PCM1_MUX_IN ,PCM1 input mux_0 = off_1 = SRC1 output_2 = PCM output registers" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " SRC1_MUX_IN ,SRC1 input mux_0 = off_1 = PCM output_2 = SRC1 input registers" "0,1,2,3,4,5,6,7" group.long 0x34++0x3 line.long 0x00 "COEF0A_SET1_REG,SRC coefficient 10 set 1" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF10 ,coefficient 10" group.long 0x20++0x3 line.long 0x00 "COEF10_SET1_REG,SRC coefficient 1,0 set 1" hexmask.long.word 0x00 16.--31. 1. " SRC_COEF1 ,coefficient 1" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF0 ,coefficient 0" group.long 0x24++0x3 line.long 0x00 "COEF32_SET1_REG,SRC coefficient 3,2 set 1" hexmask.long.word 0x00 16.--31. 1. " SRC_COEF3 ,coefficient 3" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF2 ,coefficient 2" group.long 0x28++0x3 line.long 0x00 "COEF54_SET1_REG,SRC coefficient 5,4 set 1" hexmask.long.word 0x00 16.--31. 1. " SRC_COEF5 ,coefficient 5" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF4 ,coefficient 4" group.long 0x2C++0x3 line.long 0x00 "COEF76_SET1_REG,SRC coefficient 7,6 set 1" hexmask.long.word 0x00 16.--31. 1. " SRC_COEF7 ,coefficient 7" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF6 ,coefficient 6" group.long 0x30++0x3 line.long 0x00 "COEF98_SET1_REG,SRC coefficient 9,8 set 1" hexmask.long.word 0x00 16.--31. 1. " SRC_COEF9 ,coefficient 9" hexmask.long.word 0x00 0.--15. 1. " SRC_COEF8 ,coefficient 8" group.long 0x100++0x3 line.long 0x00 "PCM1_CTRL_REG,PCM1 Control register" hexmask.long.word 0x00 20.--31. 1. " PCM_FSC_DIV ,PCM Framesync divider, Values 7-0xFFF. To divide by N, write N-1. (Minimum value N-1=7 for 8 bits PCM_FSC)_Note if PCM_CLK_BIT=1, N must always be even" bitfld.long 0x00 16. " PCM_FSC_EDGE ,0: shift channels 1, 2, 3, 4, 5, 6, 7, 8 after PCM_FSC edge_1: shift channels 1, 2, 3, 4 after PCM_FSC edge shift channels 5, 6, 7, 8 after opposite PCM_FSC edge" "0,1" bitfld.long 0x00 11.--15. " PCM_CH_DEL ,Channel delay in multiples of 8 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 10. " PCM_CLK_BIT ,0:One clock cycle per data bit_1:Two cloc cycles per data bit" "0,1" bitfld.long 0x00 9. " PCM_FSCINV ,0: PCM FSC_1: PCM FSC inverted" "0,1" bitfld.long 0x00 8. " PCM_CLKINV ,0:PCM CLK_1:PCM CLK inverted" "0,1" textline " " bitfld.long 0x00 7. " PCM_PPOD ,0:PCM DO push pull_1:PCM DO open drain" "0,1" bitfld.long 0x00 6. " PCM_FSCDEL ,0:PCM FSC starts one cycle before MSB bit_1:PCM FSC starts at the same time as MSB bit" "0,1" bitfld.long 0x00 2.--5. " PCM_FSCLEN ,0:PCM FSC length equal to 1 data bit_N:PCM FSC length equal to N*8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " PCM_MASTER ,0:PCM interface in slave mode_1:PCM interface in master mode" "0,1" bitfld.long 0x00 0. " PCM_EN ,0:PCM interface disabled_1:PCM interface enabled" "0,1" group.long 0x104++0x3 line.long 0x00 "PCM1_IN1_REG,PCM1 data in 1" hexmask.long 0x00 0.--31. 1. " PCM_IN ,PCM1_IN1 bits 31-0" group.long 0x108++0x3 line.long 0x00 "PCM1_IN2_REG,PCM1 data in 2" hexmask.long 0x00 0.--31. 1. " PCM_IN ,PCM1_IN2 bits 31-0" group.long 0x10C++0x3 line.long 0x00 "PCM1_OUT1_REG,PCM1 data out 1" hexmask.long 0x00 0.--31. 1. " PCM_OUT ,PCM1_OUT1 bits 31-0" group.long 0x110++0x3 line.long 0x00 "PCM1_OUT2_REG,PCM1 data out 2" hexmask.long 0x00 0.--31. 1. " PCM_OUT ,PCM1_OUT2 bits 31-0" group.long 0x0++0x3 line.long 0x00 "SRC1_CTRL_REG,SRC1 control register" bitfld.long 0x00 30.--31. " SRC_PDM_DO_DEL ,PDM_DO output delay line (typical)_0: no delay_1: 8 ns_2: 12 ns_3: 16 ns" "0,1,2,3" bitfld.long 0x00 28.--29. " SRC_PDM_MODE ,PDM Output mode selection on PDM_DO1_00: No output_01: Right channel (falling edge of PDM_CLK)_10: Left channel (rising edge of PDM_CLK)_11: Left and Right channel" "0,1,2,3" bitfld.long 0x00 26.--27. " SRC_PDM_DI_DEL ,PDM_DI input delay line (typical)_0: no delay_1: 4 ns_2: 8 ns_3: 12 ns" "0,1,2,3" textline " " bitfld.long 0x00 25. " SRC_OUT_FLOWCLR ,Writing a 1 clears the SRC1_OUT Overflow/underflow bits 23-22. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared" "0,1" bitfld.long 0x00 24. " SRC_IN_FLOWCLR ,Writing a 1 clears the SRC1_IN Overflow/underflow bits 21-20. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared" "0,1" rbitfld.long 0x00 23. " SRC_OUT_UNFLOW ,1 = SRC1_OUT Underflow occurred" "0,1" textline " " rbitfld.long 0x00 22. " SRC_OUT_OVFLOW ,1 = SRC1_OUT Overflow occurred" "0,1" rbitfld.long 0x00 21. " SRC_IN_UNFLOW ,1 = SRC1_IN Underflow occurred" "0,1" rbitfld.long 0x00 20. " SRC_IN_OVFLOW ,1 = SRC1_IN Overflow occurred" "0,1" textline " " bitfld.long 0x00 19. " SRC_RESYNC ,1 = SRC will restart synchronisation" "0,1" rbitfld.long 0x00 18. " SRC_OUT_OK ,SRC1_OUT Status_0: acquisition in progress_1: acquisition ready (In manual mode this bit is always 1)" "0,1" bitfld.long 0x00 16.--17. " SRC_OUT_US ,SRC1_OUT UpSampling IIR filters setting_00: for sample rates up-to 48kHz_01: for sample rates of 96kHz_10: reserved_11: for sample rates of 192kHz" "0,1,2,3" textline " " bitfld.long 0x00 14. " SRC_OUT_CAL_BYPASS ,SRC1_OUT1 upsampiling filter bypass_0:Do not bypass_1:Bypass filter" "0,1" bitfld.long 0x00 13. " SRC_OUT_AMODE ,SRC1_OUT1 Automatic Conversion mode_0:Manual mode_1:Automatic mode" "0,1" bitfld.long 0x00 12. " SRC_PDM_OUT_INV ,Swap the left and the right output PDM channel" "0,1" textline " " bitfld.long 0x00 11. " SRC_FIFO_DIRECTION ,0 = SRC fifo is used to store samples from memory to SRC_1 = SRC fifo is used to store sample from SRC to memory" "0,1" bitfld.long 0x00 10. " SRC_FIFO_ENABLE ,0 = fifo disable. On each src request, one sample is serviced_1 = fifo enable. Fifo is used to store samples from / to src" "0,1" bitfld.long 0x00 9. " SRC_OUT_DSD_MODE ,0 = SRC1 OUT PDM mode_1 = SRC1 OUT DSD mode" "0,1" textline " " bitfld.long 0x00 8. " SRC_IN_DSD_MODE ,0: SRC1 IN PDM mode_1: SRC1 IN DSD mode" "0,1" bitfld.long 0x00 7. " SRC_DITHER_DISABLE ,Dithering feature_0: Enable_1: Disable" "0,1" rbitfld.long 0x00 6. " SRC_IN_OK ,SRC1_IN status_0: Acquisition in progress_1: Acquisition ready" "0,1" textline " " bitfld.long 0x00 4.--5. " SRC_IN_DS ,SRC1_IN UpSampling IIR filters setting_00: for sample rates up-to 48kHz_01: for sample rates of 96kHz_10: reserved_11: for sample rates of 192kHz" "0,1,2,3" bitfld.long 0x00 3. " SRC_PDM_IN_INV ,Swap the left and the right input PDM channel" "0,1" bitfld.long 0x00 2. " SRC_IN_CAL_BYPASS ,SRC1_IN upsampeling filter bypass_0: Do not bypass_1: Bypass filter" "0,1" textline " " bitfld.long 0x00 1. " SRC_IN_AMODE ,SRC1_IN Automatic conversion mode_0: Manual mode_1: Automatic mode" "0,1" bitfld.long 0x00 0. " SRC_EN ,SRC1_IN and SRC1_OUT enable_0: disabled_1: enabled" "0,1" group.long 0xC++0x3 line.long 0x00 "SRC1_IN1_REG,SRC1 data in 1" hexmask.long 0x00 0.--31. 1. " SRC_IN ,SRC1_IN1" group.long 0x10++0x3 line.long 0x00 "SRC1_IN2_REG,SRC1 data in 2" hexmask.long 0x00 0.--31. 1. " SRC_IN ,SRC1_IN2" group.long 0x4++0x3 line.long 0x00 "SRC1_IN_FS_REG,SRC1 Sample input rate" hexmask.long.tbyte 0x00 0.--23. 1. " SRC_IN_FS ,SRC_IN Sample rate_SRC_IN_FS = SRC_DIV*4096*Sample_rate/100_Sample_rate upper limit is 192kHz. For 96kHz and 192kHz SRC_CTRLx_REG[SRC_IN_DS] must be set as shown below:_(for SRC_DIV=1)_Sample_rate SRC_IN_FS SRC_IN_DS Audio bandwidth_8000 Hz 0x050000 0 4000 Hz_11025 Hz 0x06E400 0 5512 Hz_16000 Hz 0x0A0000 0 8000 Hz_22050 Hz 0x0DC800 0 11025 Hz_32000 Hz 0x140000 0 16000 Hz_44100 Hz 0x1B9000 0 22050 Hz_48000 Hz 0x1E0000 0 24000 Hz_96000 Hz 0x1E0000 1 24000 Hz_192000 Hz 0x1E0000 3 24000 Hz__In manual SRC mode, SRC_IN_FS can be set and adjusted to the desired sample rate at any time._In automatic mode the SRC returns the final sample rate as soon as SRC_IN_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 and 192kHz" group.long 0x14++0x3 line.long 0x00 "SRC1_OUT1_REG,SRC1 data out 1" hexmask.long 0x00 0.--31. 1. " SRC_OUT ,SRC1_OUT1" group.long 0x18++0x3 line.long 0x00 "SRC1_OUT2_REG,SRC1 data out 2" hexmask.long 0x00 0.--31. 1. " SRC_OUT ,SRC1_OUT2" group.long 0x8++0x3 line.long 0x00 "SRC1_OUT_FS_REG,SRC1 Sample output rate" hexmask.long.tbyte 0x00 0.--23. 1. " SRC_OUT_FS ,SRC_OUT Sample rate_SRC_OUT_FS = SRC_DIV*4096*Sample_rate/100_Sample_rate upper limit is 192kHz. For 96kHz and 192kHz SRC_CTRLx_REG[SRC_DS] must be set as shown below:_(for SRC_DIV=1)_Sample_rate SRC_OUT_FS SRC_OUT_DS Audio bandwidth_8000 Hz 0x050000 0 4000 Hz_11025 Hz 0x06E400 0 5512 Hz_16000 Hz 0x0A0000 0 8000 Hz_22050 Hz 0x0DC800 0 11025 Hz_32000 Hz 0x140000 0 16000 Hz_44100 Hz 0x1B9000 0 22050 Hz_48000 Hz 0x1E0000 0 24000 Hz_96000 Hz 0x1E0000 1 24000 Hz_192000 Hz 0x1E0000 3 24000 Hz__In manual SRC mode, SRC_OUT_FS can be set and adjusted to the desired sample rate at any time._In automatic mode the SRC returns the final sample rate as soon as SRC_OUT_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 and 192kHz" width 0x0B tree.end tree "CACHE" base ad:0x100C0000 width 28. group.long 0x8++0x3 line.long 0x00 "CACHE_ASSOCCFG_REG,Cache associativity configuration register" bitfld.long 0x00 0.--1. " CACHE_ASSOC ,Cache associativity:_0: 1-way (direct mapped)_1: 2-way_2: 4-way_3: reserved" "0,1,2,3" group.long 0x60++0x3 line.long 0x00 "CACHE_CPU_M_HADDR_REG,Cache CPU Master address (RO) register" hexmask.long 0x00 0.--31. 1. " CACHE_CPU_M_HADDR ,Shows the CPU Master address (used in the Cache)._Note: Only used for debugging purposes." group.long 0x0++0x3 line.long 0x00 "CACHE_CTRL1_REG,Cache control register 1" bitfld.long 0x00 1. " CACHE_RES1 ,Reserved. Always keep 0" "0,1" bitfld.long 0x00 0. " CACHE_FLUSH ,Writing a '1' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory._The read of this bit is always '0'._Note: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB" "0,1" group.long 0x20++0x3 line.long 0x00 "CACHE_CTRL2_REG,Cache control register 2" bitfld.long 0x00 10. " CACHE_CGEN ,0: Cache controller clock gating is not enabled._1: Cache controller clock gating is enabled (enabling power saving)._Note: This bit must be set to '0' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached, e.g. from Booter or SYSRAM" "0,1" bitfld.long 0x00 9. " CACHE_WEN ,0: Cache Data and TAG memory read only._1: Cache Data and TAG memory read/write._The TAG and Data memory are only updated by the cache controller._There is no HW protection to prevent unauthorized access by the ARM._Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory" "0,1" hexmask.long.word 0x00 0.--8. 1. " CACHE_LEN ,Length of QSPI FLASH cacheable memory._N*64 KByte. N = 0 to 512 (max. of 32 Mbyte)._Setting CACHE_LEN=0 disables the cache._Note 1: The max. relevant CACHE_LEN setting depends on the chosen Flash region (program) size._Note 2: The first block (CACHE_LEN=1) includes the memory space specified by CACHE_FLASH_REG[FLASH_REGION_OFFSET]" group.long 0x24++0x3 line.long 0x00 "CACHE_CTRL3_REG,Cache control register 3 (for the Cache Controller configuration reset values)" bitfld.long 0x00 7. " CACHE_CONTROLLER_RESET ,0: De-activate the Reset of the Cache Controller._1: Reset the Cache Controller and take the new configuration reset values (when the reset is released again by changing this bit from '1' to '0')._Note: All CACHE_MRM_* registers are also reset" "0,1" bitfld.long 0x00 4.--6. " CACHE_RAM_SIZE_RESET_VALUE ,Cache DATA RAM size reset value:_0: reserved,_1: 8 KB,_2: 16 KB,_3-7: reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--3. " CACHE_LINE_SIZE_RESET_VALUE ,Cache line size reset value:_0: 8 bytes,_1: 16 bytes,_2: 32 bytes,_3: reserved" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " CACHE_ASSOCIATIVITY_RESET_VALUE ,Cache associativity reset value:_0: 1-way (direct mapped)_1: 2-way_2: 4-way_3: reserved" "0,1,2,3" group.long 0x68++0x3 line.long 0x00 "CACHE_CTRLR_M_HADDR_REG,Cache CTRLR Master address (RO) register" hexmask.long 0x00 0.--31. 1. " CACHE_CTRLR_M_HADDR ,Shows the Cache Controller Master (physical) QSPI Flash address (used in the Cache) corresponding with the last cache miss._Note: Only used for debugging purposes" group.long 0x40++0x3 line.long 0x00 "CACHE_FLASH_REG,Cache Flash program size and base address register" hexmask.long.word 0x00 16.--31. 1. " FLASH_REGION_BASE ,These bits corresponds with the Flash region base address bits [31:16]._Default value is '0x1600'._The Flash region base address bits [31:25] are fixed to '0x16' and bits [17:16] are fixed to '0x0'._These register bits are retained._Note 1: The updated value takes effect only after a software reset._Note 2 The Flash region base address setting depends on the chosen Flash region size" hexmask.long.word 0x00 4.--15. 1. " FLASH_REGION_OFFSET ,Flash region offset address (in words)._This value is added to the Flash (CPU) address bits [13:2]._These register bits are retained._Note 1: The updated value takes effect only after a software reset" bitfld.long 0x00 0.--2. " FLASH_REGION_SIZE ,Flash region size._Default value is '6' (0.5 MBytes)._0 = 32 MBytes,_1 = 16 MBytes,_2 = 8 MBytes,_3 = 4 MBytes,_4 = 2 MBytes,_5 = 1 MBytes,_6 = 0.5 MBytes,_7 = 0.25 MBytes._These register bits are retained._Note 1: The updated value takes effect only after a software reset._Note 2: See for the max. region (program) size the memory map" "0,1,2,3,4,5,6,7" group.long 0x4++0x3 line.long 0x00 "CACHE_LNSIZECFG_REG,Cache line size configuration register" bitfld.long 0x00 0.--1. " CACHE_LINE ,Cache line size:_0: 8 bytes,_1: 16 bytes,_2: 32 bytes,_3: reserved._Note: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value _01_ into the cache control register CACHE_CTRL1_REG just after the write of the value _00_ into the cache line size configuration register CACHE_LNSIZECFG_REG" "0,1,2,3" group.long 0x30++0x3 line.long 0x00 "CACHE_MRM_CTRL_REG,Cache MRM (Miss Rate Monitor) CONTROL register" bitfld.long 0x00 4. " MRM_IRQ_HITS_THRES_STATUS ,0: No interrupt is generated._1: Interrupt (pulse-sensitive) is generated because the number of cache hits reached the programmed threshold (threshold != 0)" "0,1" bitfld.long 0x00 3. " MRM_IRQ_MISSES_THRES_STATUS ,0: No interrupt is generated._1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0)" "0,1" bitfld.long 0x00 2. " MRM_IRQ_TINT_STATUS ,0: No interrupt is generated._1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0)" "0,1" textline " " bitfld.long 0x00 1. " MRM_IRQ_MASK ,0: Disables interrupt generation._1: Enables interrupt generation._Note: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor," "0,1" bitfld.long 0x00 0. " MRM_START ,0: Freeze the _misses/hits_ counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG._1: Enables the counters._Note: In case CACHE_MRM_CTRL_REG[MRM_START] is set to '1' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it's '0'. At that time CACHE_MRM_CTRL_REG[MRM_START] will be reset automatically to '0' by the MRM hardware and the MRM interrupt will be generated" "0,1" group.long 0x28++0x3 line.long 0x00 "CACHE_MRM_HITS_REG,Cache MRM (Miss Rate Monitor) HITS register" hexmask.long 0x00 0.--31. 1. " MRM_HITS ,Contains the amount of cache hits" group.long 0x3C++0x3 line.long 0x00 "CACHE_MRM_HITS_THRES_REG,Cache MRM (Miss Rate Monitor) HITS THRESHOLD register" hexmask.long 0x00 0.--31. 1. " MRM_HITS_THRES ,Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_HITS_THRES_STATUS]._Note: When MRM_HITS_THRES=0 (unrealistic value), no interrupt will be generated" group.long 0x2C++0x3 line.long 0x00 "CACHE_MRM_MISSES_REG,Cache MRM (Miss Rate Monitor) MISSES register" hexmask.long 0x00 0.--31. 1. " MRM_MISSES ,Contains the amount of cache misses" group.long 0x38++0x3 line.long 0x00 "CACHE_MRM_MISSES_THRES_REG,Cache MRM (Miss Rate Monitor) THRESHOLD register" hexmask.long 0x00 0.--31. 1. " MRM_MISSES_THRES ,Defines the misses threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_MISSES_THRES_STATUS]._Note: When MRM_MISSES_THRES=0 (unrealistic value), no interrupt will be generated" group.long 0x34++0x3 line.long 0x00 "CACHE_MRM_TINT_REG,Cache MRM (Miss Rate Monitor) TIME INTERVAL register" hexmask.long.tbyte 0x00 0.--18. 1. " MRM_TINT ,Defines the time interval for the monitoring in 32 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_TINT_STATUS]._Note: When MRM_TINT=0 (unrealistic value), no interrupt will be generated" group.long 0x64++0x3 line.long 0x00 "CACHE_M_HADDR_MAP0_REG,Cache Master Remapped address (RO) register" hexmask.long 0x00 0.--31. 1. " CACHE_M_HADDR_MAP0 ,Shows the Cache Master Remapped to 0x0 (physical) address (used in the Cache)._Note: Only used for debugging purposes" group.long 0x50++0x3 line.long 0x00 "SWD_RESET_REG,SWD HW reset control register" bitfld.long 0x00 0. " SWD_HW_RESET_REQ ,0: default._1: HW reset request (from the debugger tool). The register is automatically reset with a HW_RESET._This bit can only be accessed by the debugger software and not by the application" "0,1" width 0x0B tree.end sif !cpuis("DA14691-CM33") tree "CHARGER" base ad:0x50040400 width 32. group.long 0x1C++0x3 line.long 0x00 "CHARGER_CC_CHARGE_TIMER_REG,Maximum CC-charge time limit register" hexmask.long.word 0x00 16.--30. 1. " CC_CHARGE_TIMER ,Returns the current value of the CC-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the Pre-Charge and the CV-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_CC_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state" hexmask.long.word 0x00 0.--14. 1. " MAX_CC_CHARGE_TIME ,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CC (Constant Current) charging stage. If this is exceeded, a CC charge time-out error will be captured by the Charger's control unit and its FSM will move to the ERROR state. In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set._Note: The specific bit-field should be always set to a non-zero value" group.long 0x0++0x3 line.long 0x00 "CHARGER_CTRL_REG,Charger main control register" rbitfld.long 0x00 22.--27. " EOC_INTERVAL_CHECK_TIMER ,The specific bit-field determines the current state of the timer used to periodically check the End-of-Charge signal, as soon as the Charger's FSM is either in CC_CHARGE or CV_CHARGE state. Thus, as soon as the Charger's FSM enters the CC_CHARGE state:_ - The timer starts increasing when a positive edge detection on End-of-Charge signal occurs._ - It keeps increasing until reaching the programmed EOC_INTERVAL_CHECK_THRES value, if and only if there is no detection of a negative edge on End-of-Charge signal. If this happens, the timer resets and starts over with a new End-of-Charge positive edge._ - The timer also resets after having reached its programmed threshold or when the Charger's FSM next state is END_OF_CHARGE. This happens only after having found End-of-Charge signal asserted for 4 consecutive checks and provided that the specific signal has not de-asserted during the timer's interval._Note: It must be noted that out of these two states, the specific timer is kept to zero. It is also noted that this timer runs at the 1Mhz clock of the Charger's block and its value always ranges from 0 to the EOC_INTERVAL_CHECK_THRES value set in the respective bit-field of CHARGER_CTRL_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EOC_INTERVAL_CHECK_THRES ,This bit-field determines the periodic interval of checking the End-of-Charge signal, when the Charger's FSM is either in CC_CHARGE or in CV_CHARGE state. To implement this, a dedicated timer has been used, counting from zero up to the value programmed into this bit-field (see also EOC_INTERVAL_CHECK_TIMER field's description)._As soon as this timer reaches the programmed value, the End-of-Charge signal is sampled and depending on its status (high or low), another counter, keeping the number of consecutive End-of-Charge events, is increased or not. See also the description of the EOC_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG, for this counter._Note: The specific bit-field should always be programmed to a non-zero value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " REPLENISH_MODE ,When this bit-field is set and the Charger's FSM is in the BYPASSED state (thus, in Bypass mode), the internal multiplexer inside the digital part of the charger selects the Replenish, instead of the Pre-charge setting to be driven to the main Vbat comparator of the Charger's analogue circuitry. By this way, SW can read the respective analogue comparator's output in CHARGER_STATUS_REG (bit-field MAIN_VBAT_COMP_OUT), after the battery's volrtage has reached the End-of-Charge level, and determine if the battery voltage has dropped below the Replenish level, re-starting the battery charging accordingly._Note: When the Charger's FSM is active and operational, this bit-field is don't care and the FSM determines which level (Pre-charge or Replenish) will be selected and driven to the analogue, depending on the current state. It is also noted that the supported Pre-charge and Replenish levels can be viewed in the respective bit-fields defined in CHARGER_VOLTAGE_PARAM_REG register" "0,1" textline " " bitfld.long 0x00 14. " PRE_CHARGE_MODE ,When set, this bit-field enables a signal of the same name with the bit-field, driven from the Charger's digital part towards the analogue circuitry, in order to determine the current in Pre-Charge mode. If the Charger's FSM is active and operational, the specific bit-field is don't care. Hence, it is considered only when the Charger's FSM has reached the BYPASSED state (thus, in Bypass mode)._With the Charger's FSM being bypassed, SW should take over control and set the specific bit-field, in order to deliver the Pre-Charge instead of the normal Charge current to the Charger's analogue circuitry, during the Pre-Charge phase._Note: See also the description of CHARGER_CURRENT_PARAM_REG register for the Pre-Charge and normal Charge current levels supported" "0,1" bitfld.long 0x00 13. " CHARGE_LOOP_HOLD ,When set, this bit-field disables charging, provided that the Charger's FSM has switched to the BYPASSED state. This is possible only by setting the CHARGER_BYPASS bit-field of this register._Thus, as soon as the Charger's FSM is bypassed, the respective signal driven by the FSM is overruled by this bit-field, making the analogue part of the Charger controllable also in this mode. If the Charger's FSM is not bypassed, this bit-field is don't care" "0,1" bitfld.long 0x00 12. " JEITA_SUPPORT_DISABLED ,0 = Charger's JEITA FSM monitoring the battery temperature checks also if battery temperature is in the Warm or Cool zones._In that case, it updates accordingly all the Charger's voltage levels (Charge, Pre-Charge, Replenish and OVP) programmed in CHARGER_VOLTAGE_PARAM_REG, as well as the charge and pre-charge current settings of CHARGER_CURRENT_PARAM_REG, depending on the temperature zone determined by the analogue circuitry of the Charger (see also the JEITA registers of the Charger's register file for the Voltage/Current levels in Warm and Cool temperature zones)._1 = Charger's JEITA FSM monitoring the battery temperature checks only if battery temperature is either in the Hot or Cold zones. In that case, it notifies the main Charger FSM to stop charging automatically, when in Hot zone. The same will happen also for the case of Cold, unless the NTC_LOW_DISABLE bit-field of CHARGER_CTRL_REG is set._Note : It is not recommended to have the specific bit-field kept to '0' (and thus the JEITA support enabled), if at the same time the bit-field TBAT_PROT_ENABLE of the same register is also '0'. Thus, JEITA support should be coupled with the Battery's temperature protection" "0,1" textline " " bitfld.long 0x00 10.--11. " TBAT_MONITOR_MODE ,Battery temperature pack monitoring modes, according to the following encoding:_00 = Battery temperature state checked and updated once, as soon as the charger is powered-up and settled._01 = Battery temperature state checked periodically, depeding on TBAT_MON_TIMER_REG.TBAT_MON_INTERVAL and provided that Charger has been powered-up and charger's FSM is enabled._10 = Battery temperature state checked periodically depending on TBAT_MON_TIMER_REG.TBAT_MON_INTERVAL, provided that Charger is powered-up and regardless if the Charger's FSM is enabled or not. Hence, this mode can be effective regardless of the state of CHARGE_START bit-field of CHARGER_CTRL_REG._11 = When selected, it freezes the Battery temperature monitor FSM, as soon as the latter reaches the CHECK_IDLE state (see also CHARGER_STATUS_REG.CHARGER_JEITA_STATE bit-field's description for the states of this FSM). In this mode, the monitoring of Battery temperature is possible only by checking the status of TBAT_HOT_COMP_OUT and MAIN_TBAT_COMP_OUT bit-fields of CHARGER_STATUS_REG, thus by letting SW take over monitoring. This setting may be used in conjunction with Bypass mode (by setting CHARGER_BYPASS of CHARGER_CTRL_REG), so that both charging and battery temperature status monitoring are controlled by SW" "0,1,2,3" bitfld.long 0x00 9. " CHARGE_TIMERS_HALT_ENABLE ,0 = Charge timeout timers continue running when charging is disabled because of a Die or of a Battery temperature error._1 = Charge timeout timers are halted in case of a Die or of a Battery temperature error._In that case, the global charge timer is stopped as soon as the Charger's FSM moves to TDIE_PROT or TBAT_PROT state. Also, either the Pre-Charge, the CC_CHARGE or the CV_CHARGE timer is also stopped, depending on the charging state of the FSM when the Die/Battery temperature error has been detected." "0,1" bitfld.long 0x00 7. " NTC_LOW_DISABLE ,0 = Charging is disabled when the battery temperature is found to have reached the _COLD_ region. Therefore, the Charger's FSM moves directly to _TBAT_PROT_ error and generates an IRQ to notify the system accordingly, in case the respective IRQ mask bit of CHARGER_ERROR_IRQ_MASK_REG is set. Also, CHARGER_ERROR_IRQ_STATUS_REG. TBAT_ERROR_IRQ field is updated accordingly._1 = Charging is allowed to continue, even when the battery temperature pack reaches the _COLD_ region. Consequently, the FSM continues charging and no battery temperature error event is generated" "0,1" textline " " bitfld.long 0x00 6. " TBAT_PROT_ENABLE ,0 = Battery temperature protection disabled_1 = Battery temperature protection enabled._Charging will be stopped in case Battery temperature reaches _Hot_ zone. It will also be disabled when reaching _Cold_ zone, provided that CHARGER_CTRL_REG.NTC_LOW_DISABLE is not set. This is handled by the Charger's FSM, which moves directly to the respective error state (TBAT_PROT), also generating an Error IRQ if the respective IRQ mask bit is set (see also CHARGER_ERROR_IRQ_MASK_REG)" "0,1" bitfld.long 0x00 5. " TDIE_ERROR_RESUME ,0 = FSM will not resume from a Die temperature error. Consequently, its state will be staying to _TDIE_PROT_, for as long as this bit-field is kept low, regardless of the status of the die tempeture comparator. Also, disabling the specific bit-field will reset the Die temperature error debounce counter, when the Charger's FSM is in TDIE_PROT state (so when a Die temperature error has been already detected) and the specific counter will remain frozen to 0 until the TDIE_ERROR_RESUME bit-field is set (see also the TDIE_ERROR_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG)._1 = FSM will resume from a Die temperature error, as soon as the respective analogue compator confirms that die temperature is again below the maximum allowed level._It is noted that the maximum Die temperature level is programmable via the CHARGER_TEMPSET_PARAM_REG register's respective bit-field (T_DIE_MAX)" "0,1" bitfld.long 0x00 4. " TDIE_PROT_ENABLE ,0 = Die temperature protection is disabled, thus charging will not be disabled by the Charger's FSM in case of a Die temperature error._1 = Die temperature protection is enabled, thus the Charger's FSM will move to _TDIE_PROT_ state, disabling charging at the same time._It is noted that the Die temperature error event will be logged in the respective status bit of CHARGER_IRQ_ERROR_STATUS_REG and an IRQ will be generated, if and only if the corresponding mask bit of CHARGER_IRQ_MASK_REG is set." "0,1" textline " " bitfld.long 0x00 3. " CHARGER_RESUME ,0 = Charger's FSM is not enable to resume from a charge timeout error or a Vbat OVP (Over-Voltage Protection) error. Consequently, FSM stays in _ERROR_ state._1 = Charger's FSM will resume from a charge timeout or from an OVP error, thus its state will move from _ERROR_ to _DISABLED_ state, so that the charge cycle starts-over._It is noted that in the case of a Vbat OVP error, the FSM will leave _ERROR_ state, as soon as the Vbat comparator for the OVP level shows that Vbat is again OK (so lower than the OVP setting)" "0,1" bitfld.long 0x00 2. " CHARGER_BYPASS ,0 = Charger's FSM is active and running, notifying SW upon switching between its states_1 = Charger's FSM is bypassed, so its state stays to _BYPASS_, so SW should take over the monitoring of the battery voltage and control of the charger." "0,1" bitfld.long 0x00 1. " CHARGE_START ,0 = Charger's FSM is disabled, FSM stays at _DISABLED_ state_1 = Charger's FSM is enabled, so FSM's state can move from DISABLED to the actual charge states, starting from _PRE_CHARGE_" "0,1" textline " " bitfld.long 0x00 0. " CHARGER_ENABLE ,0 = Charger's analogue circuitry is powered-down_1 = Charger's analogue circuitry is being powered-up and will be available after a certain settling time (in ms)._As soon as this bit-field is set, the Charger's FSM waits for this settling time, before proceeding into DISABLED state, where it checks the Vbat level, as well as the Die temperature and the Battery temperature states. This is mandatory, before the actual charging begins, so before the FSM moves to PRE_CHARGE state._It is finally noted that the settling time is configurable via CHARGER_PWR_UP_TIMER_REG, counting with the 1Khz clock" "0,1" group.long 0x10++0x3 line.long 0x00 "CHARGER_CURRENT_PARAM_REG,Charger current settings register" bitfld.long 0x00 15. " I_EOC_DOUBLE_RANGE ,When set, the specific bit-field enables the doubling of the (%) range of End-of-Charge current setting. Consequently, the default lower and upper limits of 6% of I_CHARGE (value 0x0 of I_END_OF_CHARGE bit-field) and 20% (value 0x7 of the same bit-field) are increased to 12% and 40% respectively, as soon as the I_EOC_DOUBLE_RANGE field is set" "0,1" bitfld.long 0x00 12.--14. " I_END_OF_CHARGE ,End-of-Charge current setting, ranging from 6da1469x/charger.ph00_) to 20% (_111_) of the charge current set, with a step size of 2%, as follows:_000 : 6%_001 : 8%_010 : 10%_011 : 12%_100 : 14%_101 : 16%_110 : 18%_111 : 20%_Note: The aforementioned range of 6%-20% and the respective values of this bit-field are valid if the I_EOC_DOUBLE_RANGE field of this register is not set. Otherwise, the (%) range of Charge current determining the End-of-Charge current is doubled to 12%-40%, and consequently each of the values (0x0-0x7) listed above represents a doubled (%) percentage" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--11. " I_PRECHARGE ,This bit-field determines the Pre-Charge current, in mA, ranging from 0.5 to 56mA, according to the following encoding:_0 : 0.5 mA_1 : 1 mA_2 : 1.5mA_3 : 2 mA_4 : 2.5mA_5 : 3 mA_6 : 3.5mA_7 : 4 mA_8 : 4.5mA_9 : 5 mA_10 : 5.5mA_11 : 6 mA_12 : 6.5mA_13 : 7 mA_14 : 7.5mA_15 : 8 mA_16 : 9 mA_17 : 10 mA_18 : 11 mA_19 : 12 mA_20 : 13 mA_21 : 14 mA_22 : 15 mA_23 : 16 mA_24 : 17 mA_25 : 18 mA_26 : 19 mA_27 : 20 mA_28 : 21 mA_29 : 22 mA_30 : 23 mA_31 : 24 mA_32 : 26 mA_33 : 28 mA_34 : 30 mA_35 : 32 mA_36 : 34 mA_37 : 36 mA_38 : 38 mA_39 : 40 mA_40 : 42 mA_41 : 44 mA_42 : 46 mA_43 : 48 mA_44 : 50 mA_45 : 52 mA_46 : 54 mA_47 : 56 mA_48 : 56 mA_49 : 56 mA_50 : 56 mA_51 : 56 mA_52 : 56 mA_53 : 56 mA_54 : 56 mA_55 : 56 mA_56 : 56 mA_57 : 56 mA_58 : 56 mA_59 : 56 mA_60 : 56 mA_61 : 56 mA_62 : 56 mA_63 : 56 mA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " I_CHARGE ,This bit-field determines the charge current range, in mA. The range is from 5mA to 560mA, according to the following encoding:_0 : 5 mA_1 : 10 mA_2 : 15 mA_3 : 20 mA_4 : 25 mA_5 : 30 mA_6 : 35 mA_7 : 40 mA_8 : 45 mA_9 : 50 mA_10 : 55 mA_11 : 60 mA_12 : 65 mA_13 : 70 mA_14 : 75 mA_15 : 80 mA_16 : 90 mA_17 : 100 mA_18 : 110 mA_19 : 120 mA_20 : 130 mA_21 : 140 mA_22 : 150 mA_23 : 160 mA_24 : 170 mA_25 : 180 mA_26 : 190 mA_27 : 200 mA_28 : 210 mA_29 : 220 mA_30 : 230 mA_31 : 240 mA_32 : 260 mA_33 : 280 mA_34 : 300 mA_35 : 320 mA_36 : 340 mA_37 : 360 mA_38 : 380 mA_39 : 400 mA_40 : 420 mA_41 : 440 mA_42 : 460 mA_43 : 480 mA_44 : 500 mA_45 : 520 mA_46 : 540 mA_47 : 560 mA_48 : 560 mA_49 : 560 mA_50 : 560 mA_51 : 560 mA_52 : 560 mA_53 : 560 mA_54 : 560 mA_55 : 560 mA_56 : 560 mA_57 : 560 mA_58 : 560 mA_59 : 560 mA_60 : 560 mA_61 : 560 mA_62 : 560 mA_63 : 560 mA_Note: It has to be noted that the specific values correspond to the normal battery temperature zone. However, the specific register field may be updated by the JEITA FSM (which checks the battery temperature either once or periodically), in order to adapt the Charge current to the new battery temperature zone (see also CHARGER_CTRL_REG.TBAT_MONITOR_MODE field as well). This is valid also for the Pre-Charge current field of this register and provided that JEITA support is enabled in CHARGER_CTRL_REG._Consequently, in that case the register return the Charge current settings that abide to the JEITA requirements for the battery (either COOL, WARM or NORMAL)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x3 line.long 0x00 "CHARGER_CV_CHARGE_TIMER_REG,Maximum CV-charge time limit register" hexmask.long.word 0x00 16.--30. 1. " CV_CHARGE_TIMER ,Returns the current value of the CV-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the Pre-Charge and the CC-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_CV_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state" hexmask.long.word 0x00 0.--14. 1. " MAX_CV_CHARGE_TIME ,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CV (Constant Voltage) charging stage. If this is exceeded, a CV charge time-out error will be captured by the Charger's control unit and its FSM will move to the ERROR state. In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set._Note: The specific bit-field should be always set to a non-zero value" group.long 0x6C++0x3 line.long 0x00 "CHARGER_ERROR_IRQ_CLR_REG,Interrupt clear register of Charger Error IRQs" bitfld.long 0x00 6. " TBAT_ERROR_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 5. " TDIE_ERROR_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 4. " VBAT_OVP_ERROR_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 3. " TOTAL_CHARGE_TIMEOUT_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 2. " CV_CHARGE_TIMEOUT_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 1. " CC_CHARGE_TIMEOUT_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 0. " PRECHARGE_TIMEOUT_IRQ_CLR ,Writing a 1 will reset the respective Charger's Error IRQ ; writing a 0 will have no effect" "0,1" group.long 0x5C++0x3 line.long 0x00 "CHARGER_ERROR_IRQ_MASK_REG,Mask register of Charger Error IRQs" bitfld.long 0x00 6. " TBAT_ERROR_IRQ_EN ,When set, it enables the generation of Battery temperature IRQs.The IRQ is generated as soon as the JEITA FSM detects that the battery temperature is either in the _Hot_ or in the _Cold_ temperature region, by sampling the respective comparators' output" "0,1" bitfld.long 0x00 5. " TDIE_ERROR_IRQ_EN ,When set, it enables the generation of Die temperature error IRQs. The IRQ is generated as soon as a Die temperature error is captured, so as soon as the Charger's FSM moves to the TDIE_PROT state. For this to happen, the Die temperature comparator should indicate that Die temperature has exceeded the limit defined in CHARGER_TEMPSET_PARAM_REG.TDIE_MAX" "0,1" bitfld.long 0x00 4. " VBAT_OVP_ERROR_IRQ_EN ,When set, it enables the generation of VBAT_OVP IRQs. The IRQ is generated as soon as the dedicated Vbat comparator shows that Vbat has exceeded the OVP level and the Charger's FSM has switched to the respective error state (_ERROR_)" "0,1" textline " " bitfld.long 0x00 3. " TOTAL_CHARGE_TIMEOUT_IRQ_EN ,When set, it enables the total charge timeout IRQs. The IRQ is generated as soon as the Charger's global charge timer expires, reaching 0" "0,1" bitfld.long 0x00 2. " CV_CHARGE_TIMEOUT_IRQ_EN ,When set, it enables the CV charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer expires, reaching 0 when the FSM is in the CV_CHARGE state" "0,1" bitfld.long 0x00 1. " CC_CHARGE_TIMEOUT_IRQ_EN ,When set, it enables the CC charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer, expires, reaching 0" "0,1" textline " " bitfld.long 0x00 0. " PRECHARGE_TIMEOUT_IRQ_EN ,When set, it enables the Pre-Charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer expires, reaching 0" "0,1" group.long 0x64++0x3 line.long 0x00 "CHARGER_ERROR_IRQ_STATUS_REG,Status register of Charger Error IRQs" rbitfld.long 0x00 6. " TBAT_ERROR_IRQ ,0 = No Battery temperature error IRQ event is captured, so charging may continue_1 = A Battery temperature error IRQ event has been captured, declaring that the Charger's FSM has moved to the respective error state (TBAT_PROT)._Note : The status bit is updated automatically when the Battery temperature is detected to be either in the HOT or in the COLD zone, regardless of the state of the respective IRQ mask bit" "0,1" rbitfld.long 0x00 5. " TDIE_ERROR_IRQ ,0 = No Die temperature error IRQ events have been captured, so charging may continue_1 = A Die temperature error IRQ event is captured, declaring that the Charger's FSM has switched to the respective error state (TDIE_PROT) and charging will be automatically stopped._Note : The status bit is updated automatically when a Die temperature error is detected, thus when the die temperature is found to have exceeded the programmed level, regardless of the stae of the respective IRQ mask bit" "0,1" rbitfld.long 0x00 4. " VBAT_OVP_ERROR_IRQ ,0 = Vbat has not exceeded the Over-Voltage Protection (OVP) level, so charging may continue_1 = Vbat has exceeded the Over-Voltage level, thus an OVP error event has been captured. The Charger's FSM switches to the respective error state (ERROR) as soon as the OVP event is captured by the digital part of the Charger and charging will be automatically stopped" "0,1" textline " " rbitfld.long 0x00 3. " TOTAL_CHARGE_TIMEOUT_IRQ ,0 = Total charge time counter has not yet reached the maximum charge time (set in CHARGER_TOTAL_CHARGE_TIME_REG)_1 = Total charge time counter has reached the maximum charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured" "0,1" rbitfld.long 0x00 2. " CV_CHARGE_TIMEOUT_IRQ ,0 = State charge time counter has not yet reached the maximum CV charge time (set in CHARGER_CV_CHARGE_TIME_REG)_1 = Total charge time counter has reached the maximum CV charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured" "0,1" rbitfld.long 0x00 1. " CC_CHARGE_TIMEOUT_IRQ ,0 = State charge time counter has not yet reached the maximum CC charge time (set in CHARGER_CC_CHARGE_TIME_REG)_1 = Total charge time counter has reached the maximum CC charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured" "0,1" textline " " rbitfld.long 0x00 0. " PRECHARGE_TIMEOUT_IRQ ,0 = State charge time counter has not yet reached the maximum Pre-charge time (set in CHARGER_PRECHARGE_TIME_REG)_1 = Total charge time counter has reached the maximum Pre-charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured" "0,1" group.long 0x38++0x3 line.long 0x00 "CHARGER_JEITA_CURRENT_REG,JEITA-compliant current settings register" bitfld.long 0x00 18.--23. " I_PRECHARGE_TWARM ,Pre-Charge current setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of I_PRECHARGE field of CHARGER_CURRENT_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " I_PRECHARGE_TCOOL ,Pre-Charge current setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of I_PRECHARGE field of CHARGER_CURRENT_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " I_CHARGE_TWARM ,Charge current setting for the Warm battery temperature pack zone. Regarding the range of values of this bit-field, see also the description of I_CHARGE field of CHARGER_CURRENT_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " I_CHARGE_TCOOL ,Charge current setting for the _COOL_ battery temperature level. Regarding the range of values of this bit-field, see also the description of I_CHARGE field of CHARGER_CURRENT_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x28++0x3 line.long 0x00 "CHARGER_JEITA_V_CHARGE_REG,JEITA-compliant Charge voltage settings register" bitfld.long 0x00 6.--11. " V_CHARGE_TWARM ,Charge voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " V_CHARGE_TCOOL ,Charge voltage setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x34++0x3 line.long 0x00 "CHARGER_JEITA_V_OVP_REG,JEITA-compliant OVP settings register" bitfld.long 0x00 6.--11. " V_OVP_TWARM ,VBAT Over-voltage Protection (OVP) setting for the Warm battery temperature zone.Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " V_OVP_TCOOL ,VBAT Over-voltage Protection (OVP) setting for the Cool battery temperature zone.Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x3 line.long 0x00 "CHARGER_JEITA_V_PRECHARGE_REG,JEITA-compliant Pre-Charge voltage settings register" bitfld.long 0x00 6.--11. " V_PRECHARGE_TWARM ,Pre-Charge voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " V_PRECHARGE_TCOOL ,Pre-Charge current setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "CHARGER_JEITA_V_REPLENISH_REG,JEITA-compliant Replenish settings register" bitfld.long 0x00 6.--11. " V_REPLENISH_TWARM ,Replenish voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " V_REPLENISH_TCOOL ,Replenish voltage setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x18++0x3 line.long 0x00 "CHARGER_PRE_CHARGE_TIMER_REG,Maximum pre-charge time limit register" hexmask.long.word 0x00 16.--30. 1. " PRE_CHARGE_TIMER ,Returns the current value of the Pre-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the CC-Charge and the CV-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_PRE_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state" hexmask.long.word 0x00 0.--14. 1. " MAX_PRE_CHARGE_TIME ,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the Pre-Charge stage. If this is exceeded, a Pre-Charge time-out error will be captured by the Charger's control unit and its FSM will move to the respective state (ERROR). In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set._Note: The specific bit-field should be always set to a non-zero value" group.long 0x54++0x3 line.long 0x00 "CHARGER_PWR_UP_TIMER_REG,Charger power-up (settling) timer" hexmask.long.word 0x00 16.--25. 1. " CHARGER_PWR_UP_TIMER ,Returns the current value of the charger's power-up timer, running with the 1 Khz clock" hexmask.long.word 0x00 0.--9. 1. " CHARGER_PWR_UP_SETTLING ,This bit-field determines the charger's power-up (settling) time, required for the analogue circuitry of the charger. As soon as the charger is powered-on by setting the CHARGER_ENABLE bit-field of CHARGER_CTRL_REG, the charger's FSM loads a dedicated timer with this value and waits for this timer to expire, before proceeding to the next states._Note: The specific bit-field should be always set to a non-zero value" group.long 0x68++0x3 line.long 0x00 "CHARGER_STATE_IRQ_CLR_REG,Interrupt clear register of Charger FSM IRQs" bitfld.long 0x00 11. " CV_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 10. " CC_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 9. " CV_TO_CC_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 8. " TBAT_STATUS_UPDATE_IRQ_CLR ,Writing a 1 will reset the Battery temperature status update IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 7. " TBAT_PROT_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 6. " TDIE_PROT_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 5. " EOC_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 4. " CV_TO_EOC_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 3. " CC_TO_EOC_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 2. " CC_TO_CV_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 1. " PRECHARGE_TO_CC_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 0. " DISABLED_TO_PRECHARGE_IRQ_CLR ,Writing a 1 will reset the respective Charger's State IRQ ; writing a 0 will have no effect" "0,1" group.long 0x58++0x3 line.long 0x00 "CHARGER_STATE_IRQ_MASK_REG,Mask register of Charger FSM IRQs" bitfld.long 0x00 11. " CV_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to PRE_CHARGE state" "0,1" bitfld.long 0x00 10. " CC_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to PRE_CHARGE state" "0,1" bitfld.long 0x00 9. " CV_TO_CC_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to CC_CHARGE state" "0,1" textline " " bitfld.long 0x00 8. " TBAT_STATUS_UPDATE_IRQ_EN ,When set, this bit-field enables the generation of the Charger's state IRQ as soon as the battery temperature status is refreched by the Charger's Battery temperature monitor (JEITA) FSM. As soon as the specific FSM checks the current battery temperature level, it notifies the main Charger FSM that it has run and that the Battery temperature pack state is checked (and potentially refreshed with a new status)" "0,1" bitfld.long 0x00 7. " TBAT_PROT_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Battery temperature protection state (TBAT_PROT) to PRE_CHARGE, resuming charging" "0,1" bitfld.long 0x00 6. " TDIE_PROT_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Die temperature protection state (TDIE_PROT) to PRE_CHARGE, resuming charging" "0,1" textline " " bitfld.long 0x00 5. " EOC_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the Charger's State IRQ generation as soon as the Charger's FSM switches from END_OF_CHARGE again to PRE_CHARGE state. This happens when the Vbat voltage level is detected to be below the Replenish level set" "0,1" bitfld.long 0x00 4. " CV_TO_EOC_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to END_OF_CHARGE state" "0,1" bitfld.long 0x00 3. " CC_TO_EOC_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to END_OF_CHARGE state" "0,1" textline " " bitfld.long 0x00 2. " CC_TO_CV_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to CV_CHARGE state" "0,1" bitfld.long 0x00 1. " PRECHARGE_TO_CC_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from PRE_CHARGE to CC_CHARGE state." "0,1" bitfld.long 0x00 0. " DISABLED_TO_PRECHARGE_IRQ_EN ,When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from DISABLED to PRE_CHARGE state" "0,1" group.long 0x60++0x3 line.long 0x00 "CHARGER_STATE_IRQ_STATUS_REG,Status register of Charger FSM IRQs" rbitfld.long 0x00 11. " CV_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from CV_CHARGE to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from CV_CHARGE to PRE_CHARGE state" "0,1" rbitfld.long 0x00 10. " CC_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from CC_CHARGE to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from CC_CHARGE to PRE_CHARGE state" "0,1" rbitfld.long 0x00 9. " CV_TO_CC_IRQ ,0 = No transition of the Charger's FSM from CV_CHARGE to CC_CHARGE state has been captured_1 = Charger's FSM has switched from CV_CHARGE to CC_CHARGE state" "0,1" textline " " rbitfld.long 0x00 8. " TBAT_STATUS_UPDATE_IRQ ,0 = No battery temperature status update event has been captured_1 = Battery temperature pack's status has been checked and refreshed by the Charger's Battery temperature monitor FSM. Thus, the new status of the battery temperature should be checked by SW" "0,1" rbitfld.long 0x00 7. " TBAT_PROT_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from TBAT_PROT to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from TBAT_PROT to PRE_CHARGE state, resuming charging after having recovered from a battery temperature error" "0,1" rbitfld.long 0x00 6. " TDIE_PROT_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from TDIE_PROT to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from TDIE_PROT to PRE_CHARGE state, resuming charging after having recovered from a Die temperature error" "0,1" textline " " rbitfld.long 0x00 5. " EOC_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from END_OF_CHARGE to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from END_OF_CHARGE to PRE_CHARGE state" "0,1" rbitfld.long 0x00 4. " CV_TO_EOC_IRQ ,0 = No transition of the Charger's FSM from CV_CHARGE to END_OF_CHARGE state has been captured_1 = Charger's FSM has switched from CV_CHARGE to END_OF_CHARGE state" "0,1" rbitfld.long 0x00 3. " CC_TO_EOC_IRQ ,0 = No transition of the Charger's FSM from CC_CHARGE to END_OF_CHARGE state has been captured_1 = Charger's FSM has switched from CC_CHARGE to END_OF_CHARGE state" "0,1" textline " " rbitfld.long 0x00 2. " CC_TO_CV_IRQ ,0 = No transition of the Charger's FSM from CC_CHARGE to CV_CHARGE state has been captured_1 = Charger's FSM has switched from CC_CHARGE to CV_CHARGE state" "0,1" rbitfld.long 0x00 1. " PRECHARGE_TO_CC_IRQ ,0 = No transition of the Charger's FSM from PRE_CHARGE to CC_CHARGE state has been captured_1 = Charger's FSM has switched from PRE_CHARGE to CC_CHARGE state" "0,1" rbitfld.long 0x00 0. " DISABLED_TO_PRECHARGE_IRQ ,0 = No transition of the Charger's FSM from DISABLED to PRE_CHARGE state has been captured_1 = Charger's FSM has switched from DISABLED to PRE_CHARGE state" "0,1" group.long 0x8++0x3 line.long 0x00 "CHARGER_STATUS_REG,Charger main status register" rbitfld.long 0x00 27.--29. " OVP_EVENTS_DEBOUNCE_CNT ,The specific bit-field returns the consecutive number of times Vbat has exceeded the programmed Over-Voltage Protection (OVP) level. It is used to determine when the Charger's FSM will exit any of the charging states (PRE/CC/CV_CHARGE) and will switch to the ERROR state due to an OVP error. This will happen as soon as the respective counter of OVP events reaches or exceeds a fixed number (4), similar to the approach adopted in the End-of-Charge and Die Temperature debouncing mechanisms._The specific counter increases only while the Charger's FSM is in any of the three charging,states, the Vbat OVP interval check timer has reached the threshold set and when Vbat OVP comparator's output is asserted._Note 1 : By default, as soon as the counter reaches 4, the FSM will switch to the ERROR state and the counter will reset again. Thus, in that case the specific counter ranges from 0 to 4 and vice-versa. However, if the monitoring of Vbat OVP comparator's state is less frequent than 5 (4+1) times the CHARGER_OVP_COMP_TIMER_REG[OVP_INTERVAL_CHECK_THRES] and Vbat has exceeded the OVP voltage level based on the comparator's output signal, then this counter will exceed 4 and may overflow._This will not harm, however, the detection of the OVP event, as it only increases the number of OVP event occurrences by the debounce timer, until the OVP comparator timer's settling time has expired. Thus, the Charger FSM will again switch to ERROR when the counter has reached or exceeded 4 (bit [2] of OVP_EVENTS_DEBOUNCE_CNT is set) and the OVP comparator's timer has expired._Note 2: See also the OVP_INTERVAL_CHECK_TIMER, OVP_INTERVAL_CHECK_THRES of CHARGER_OVP_COMP_TIMER_REG, for the debouncing mechanism of the Vbat OVP comparator's output" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 24.--26. " EOC_EVENTS_DEBOUNCE_CNT ,The specific bit-field returns the number of times the End-of-Charge signal has been consecutively found to be high. It is used to determine when the Charger's FSM will switch from CV_CHARGE to END_OF_CHARGE state, implementing a debounce mechanism on End-of-Charge signal, coming from the analogue circuitry of the Charger towards the FSM._The specific counter, running with the Charger's 1Mhz clock:_ - Increases after detecting that the End-of-Charge signal is high when the respective interval for the End-of-Charge check expires. This actually happens after having detected a positive edge on End-of-Charge signal, since only after that is it possible for the interval timer to start ticking._ - Resets to zero when End-of-Charge is seen low when the interval timer has expired or when an End-of-Charge negative edge is seen before the timer's expiration, starting-over._ - Does not count if End-of-Charge signal is seen high and either the CV_MODE signal (also driven by the analogue circutry) or the End-of-Charge signal of the previous clock cycle is seen low._ - Is reset when the Charger's FSM is not in either the CC_CHARGE or the CV_CHARGE state or after having reached _100_(4). This is the threshold after which the End-of-Charge signal is considered stable by the Charger's FSM, to switch to the END_OF_CHARGE state. Thus, in practice, the specific counter (and bit-field) ranges between 0 and 4._Note: See also the EOC_INTERVAL_CHECK_TIMER/THRES bit-fields of CHARGER_CTRL_REG" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 21.--23. " TDIE_ERROR_DEBOUNCE_CNT ,The specific bit-field returns the consecutive number of times the Die temperature is seen either above (for the case of an error) or below (for the case of recovering from an error) the set Die temperature level.This is performed by a counter, which is increased:_- Each time the Die temperature comparator shows that Die temperature exceeds the set level, and while charging is active, provided that Die temperature protection is enabled. If, however, the CHARGER_CTRL_REG.TDIE_PROT_ENABLE bit-field is not set, the counter is reset and stays frozen to zero._- Each time the Die temperature comparator shows that Die temperature is again below the set level, and while the FSM is in the Die temperature protection error state (TDIE_PROT) and the TDIE_ERROR_RESUME bit-field of CHARGER_CTRL_REG is set. If the specific bit-field is not set, the debounce counter is reset to 0 and it is kept frozen until the FSM is again enabled to resume from Die temperature errors._If the Die temperature comparator of the Charger's analogue circuitry shows that temperature has exceeded the programmed level for four consecutive times and charging is active, the Charger's FSM considers this as a Die temperature error and moves to the TDIE_PROT state, resetting the timer at the same time and of course halting charging._To recover from this state and resume charging, the FSM needs to see that Die temperature is below the programmed level for four consecutive times, again, provided that the TDIE_ERROR_RESUME bit-field of CHARGER_CTRL_REG is set. As soon as this happens, the error counter is again reset and the Charger's FSM resumes, by moving to PRE_CHARGE state. Consequently, the counter's value always ranges from 0 to 4._Note: When the Charger's FSM is in BYPASSED state, then this bit-field is reset and kept frozen to zero. Consequently, the number of times Die temperature has exceeded the pre-programmed threshold should be determined by SW" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 18.--20. " CHARGER_JEITA_STATE ,Returns the state of the Charger's JEITA FSM. This FSM is used to update the state of the battery temperature pack, depending on the value programmed in CHARGER_CTRL_REG.TBAT_MONITOR_MODE bit-field. The encoding of the states is as follows:_0x0 = CHECK_IDLE_0x1 = CHECK_THOT_0x2 = CHECK_TCOLD_0x3 = CHECK_TWARM_0x4 = CHECK_TCOOL_0x5 = CHECK_TNORMAL_0x6 = UPDATE_TBAT_The FSM initially is in CHECK_IDLE state and starts checking the battery's temperature by visiting the states that check for the respective temperature area (Hot, Cold, Warm, Cool, Normal), in this order._If the battery temperature is found to be in one of the aforementioned zones, it directly moves to UPDATE_TBAT state, to update the battery temperature's state and notify the main FSM of the Charger about the battery temperature status, before returning to the CHECK_IDLE state. A Charger State IRQ will also be generated upon refreshing the battery temperature status (see also the description of CHARGER_STATE_IRQ_MASK_REG register)" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 14.--17. " CHARGER_STATE ,Indicating the state of the Charger's main FSM, based on the following encoding:_0x0 = POWER_UP (Charger's power-up not yet set)_0x1 = INIT (Charger is being power-up, FSM waiting for the analogue to settle)_0x2 = DISABLED (Charger powered-up but charging not yet started)_0x3 = PRE_CHARGE (Pre-Charge state)_0x4 = CC_CHARGE (Constant Current state)_0x5 = CV_CHARGE (Constant Voltage state)_0x6 = END_OF_CHARGE (End-of-Charge state)_0x7 = TDIE_PROT (Die temperature protection state, visited when Die temperature limit is exceeded)_0x8 = TBAT_PROT (Battery temperature protection state, visited when Battery temperature is either COLD or HOT)_0x9 = BYPASSED (Bypassed state, visited only when the FSM is bypassed and SW takes over control)_0xA = ERROR (Error state, visited when a charge time-out occurs or in the case of Vbat exceeding over-voltage level)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 9.--13. " TBAT_STATUS ,Battery pack temperature status, according to the following (_1-Hot_-like) encoding:_00001 : Battery temperature in COLD zone (default)_00010 : Battery temperature in COOL zone_00100 : Battery temperature in NORMAL zone (above COOL and below WARM zones)_01000 : Battery temperature in WARM zone_10000 : Battery temperature in HOT zone_It is noted that, according to the JEITA standard (supported if the JEITA_SUPPORT_ENABLED bit-field of CHARGER_CTRL_REG is not set) , if the battery pack temperature is in the _HOT_ zone, charging will always be stopped. The same will happen also for the case of the COLD zone, unless the _NTC_LOW_DISABLE_ bit-field of CHARGER_CTRL_REG is set. In that case, charging will continue._It is finally noted that only the aforementioned values are available for this bit-field, since it is 1-Hot encoding based. Not more than 1 bit can be high at the same time, since this would mean that battery temperature is at two different temperature zones concurrently" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 8. " MAIN_TBAT_COMP_OUT ,Returns the status of the main battery temperature comparator. This comparator by default checks if the battery temperature is in the Cold zone. However, if JEITA support is enabled and battery temperature is found to not be in either the Hot or the Cold zone, the same comparator is used to check for the Warm and Cool zones, as JEITA suggests._The specific bit-field is suggested to be used in bypass mode and when the JEITA support is disabled (so when the battery temperature is checked agains the Hot and the Cold zones). In that case, the comparator checks the battery temperature agains the Cold level and its status can be as follows:_0 = Battery temperature pack is found to be below the Cold level, so in the non-allowed Cold temperature zone. Thus, charging will be disabled, provided that the NTC_LOW_DISABLE bit-field of CHARGER_CTRL_REG is not set._1 = Battery temperature pack is found to be above the non-allowed Cold temperature zone. Thus, charging will be continued, provided that battery temperature will not be in the Hot zone as well._When the Charger's main FSM is active and JEITA is enabled, the Charger's digital block takes over and controls the respective comparator's output" "0,1" rbitfld.long 0x00 7. " TBAT_HOT_COMP_OUT ,Returns the status of the battery temperature comparator dedicated to the Hot temperature zone._0 = Battery temperature pack is found to be below the Hot zone_1 = Battery temperature pack is found to be in the non-allowed Hot temperature zone. Thus, charging will be disabled, provided that battery temperature protection is enabled" "0,1" rbitfld.long 0x00 6. " TDIE_COMP_OUT ,0 = Die temperature is found to be below the programmed level, set in CHARGER_TEMPSET_PARAM_REG.TDIE_SET level (normal operation)_1 = Die temperature is found to be above the set level._Charging will be disabled if Die temperature protection is enabled and the Die temperature is found to be above the set level four consecutive times (see also TDIE_ERROR_DEBOUNCE_CNT bit-field). In that case, the Charger's FSM will also move the respective error state (TDIE_PROT) and an IRQ may be generated, if the respective mask bit of CHARGER_ERROR_IRQ_MASK_REG is set" "0,1" textline " " rbitfld.long 0x00 5. " VBAT_OVP_COMP_OUT ,0 = Vbat has not exceeded the Over-Voltage Protection (OVP) voltage limit, according to the respective analogue comparator's output._1 = Vbat is found to have exceeded the OVP voltage setting, thus charging should be disabled._The OVP voltage settings are defined in CHARGER_VOLTAGE_PARAM_REG.V_OVP (for the Normal battery temperature zone), as well as in CHARGER_JEITA_V_OVP_REG (for Cool and Warm temperature zones, to comply with JEITA)." "0,1" rbitfld.long 0x00 4. " MAIN_VBAT_COMP_OUT ,This bit-field reflects the status of the main Vbat comparator residing in the analogue circuitry of the Charger._This comparator is used to check Vbat against either the Pre-Charge or the Replenish voltage level, depending on what is driven by the Charger's digital block._Thus, when the FSM is active, the comparator gets as reference the Replenish setting as soon as the FSM has reached the END_OF_CHARGE state. Otherwise,the Pre-Charge voltage setting is driven, including the Bypass mode._According to the above, the encoding is as follows for the case the comparator compares Vbat against the Pre-Charge level:_0 = Vbat has not exceeded the set Pre-Charge voltage level._1 = Vbat has reached or exceeded the set Pre-Charge voltage level._For the case the comparator compares agains the Replenish level (when the FSM has reached the END_OF_CHARGE state, so when the charging has been completed), the encoding is as follows:_0 = Vbat has dropped below the set Replenish level, so charging will re-start and the FSM will move to the PRE_CHARGE state._1 = Vbat is still greater or equal to the set Replenish level, thus charging remains in hold and the FSM in END_OF_CHARGE state" "0,1" rbitfld.long 0x00 3. " END_OF_CHARGE ,0 = Actual charge current is above the current level programmed in I_END_OF_CHARGE field of CHARGER_CURRENT_PARAM_REG (or charger is off)_1 = Actual charge current is below the current level programmed in I_END_OF_CHARGE bit-field of CHARGER_CURRENT_PARAM_REG" "0,1" textline " " rbitfld.long 0x00 2. " CHARGER_CV_MODE ,0 = Charger's voltage loop not in regulation (or Charger is off)_1 = Charger's Constant Voltage (CV) mode active, voltage loop in regulation" "0,1" rbitfld.long 0x00 1. " CHARGER_CC_MODE ,0 = Charger's Current loop not in regulation (or Charger is off)_1 = Charger's Constant Current (CC) mode active, current loop in regulation" "0,1" rbitfld.long 0x00 0. " CHARGER_IS_POWERED_UP ,0 = Charger is either off or it is being powered-on but the analogue ciruitry is not yet settled. The charger's main FSM is either in POWER_UP or INIT states._1 = Charger is powered-up, so its analogue ciruitry should now be settled. The Charger's FSM has left both power-up states (POWER_UP, INIT), so charging can start" "0,1" group.long 0x4C++0x3 line.long 0x00 "CHARGER_TBAT_COMP_TIMER_REG,Battery temperature (main) comparator timer" hexmask.long.word 0x00 16.--25. 1. " TBAT_COMP_TIMER ,Returns the main battery temperature comparator's timer, used for the latching of the comparator's output. The output of the comparator is used by the JEITA FSM, to determine the current battery temperature pack's status" hexmask.long.word 0x00 0.--9. 1. " TBAT_COMP_SETTLING ,Settling time (specified in us) for the main battery temperature comparator, checking for the _COOL_, _COLD_ and _WARM_ levels. The charger's digital block uses a dedicated timer to sample the specific comparator's output. The comparator's output is latched as soon as the timer expires, reaching 0. Then, the timer is reloaded with the settling time value and starts-over, down-counting to 0._Note: The specific bit-field should be always set to a non-zero value" group.long 0x48++0x3 line.long 0x00 "CHARGER_TBAT_MON_TIMER_REG,Battery temperature monitor interval timer" hexmask.long.word 0x00 16.--25. 1. " TBAT_MON_TIMER ,This is the battery temperature monitoring timer, counting with the Charger's 1KHz clock. If the battery monitor mode is accordingly set in the TBAT_MONITOR_MODE bit-field of CHARGER_CTRL_REG (so either to 0x1 or 0x2), this timer is initially loaded with the value set in TBAT_MON_INTERVAL bit-field in the subsequent 1khz cycles starts down-counting to 0. As soon as the specific timer expires,the JEITA FSM starts-over again, to refresh the battery temperature status" hexmask.long.word 0x00 0.--9. 1. " TBAT_MON_INTERVAL ,Timing interval (in ms) for the Battery temperature monitoring. This interval determines how often the JEITA FSM will be checking and potentially refreshing the Battery temperature status, by selecting accordingly the proper level (Hot, Cold, Warm, Cool or Normal), based on the feedback of the two battery temperature comparators being present in the Charger's analogue circuitry (one for the Hot level and one for Cold, Cool and Warm, to support JEITA)._Note: The specific bit-field should be always set to a non-zero value" group.long 0x44++0x3 line.long 0x00 "CHARGER_TDIE_COMP_TIMER_REG,Die temperature comparator timer register" hexmask.long.word 0x00 16.--25. 1. " TDIE_COMP_TIMER ,Returns the current value of the timer used to determine when the Die temperature comparator's output must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from TDIE_COMP_SETTLING) the comparator's output is latched by the Charger's digital block and used by the main FSM. After expiring, the timer starts-over again, down-counting, to enable the continuous monitoring of Die temperature by the digital._Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over, sampling the status of the TDIE_PROT_COMP_OUT bit-field of CHARGER_STATUS_REG to determine if the Die temperature limit has been exceeded" hexmask.long.word 0x00 0.--9. 1. " TDIE_COMP_SETTLING ,Settling time threshold (in us) for the Die temperature comparator." group.long 0x14++0x3 line.long 0x00 "CHARGER_TEMPSET_PARAM_REG,Charger battery temperature settings register" bitfld.long 0x00 24.--26. " TDIE_MAX ,This bit-field determines the maximum Die temperature level limit, ranging from 0C to 130C, according to the following encoding:_000: 0 C (mainly for test purposes)_001: 50 C_010: 80 C_011: 90 C_100: 100 C_101: 110 C_110: 120 C_111: 130 C" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--23. " TBAT_HOT ,This bit-field determines the battery temperature above which the charge current is zero, defining the _Hot_ battery temperature zone. It ranges from minus 10C to 53C. The range is the same with the one defined in detail in TBAT_COLD bit-field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " TBAT_WARM ,This bit-field determines the battery temperature above which the charge current is reduced, defining the _Warm_ temperature zone. It ranges from minus 10C to 53C. The range is the same with the one defined in detail in TBAT_COLD bit-field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--11. " TBAT_COOL ,This bit-field determines the battery temperature below which the charge current is reduced, defining the _Cool_ temperature zone. It ranges from minus 10C to 53C and the range is the same with the one defined in TBAT_COLD bit-field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TBAT_COLD ,This bit-field determines the battery temperature below which the charge current is zero, defining the _Cold_ temperature zone. It ranges from minus 10C to 53C, according to the following encoding:_0 : -10 C_1 : -9 C_2 : -8 C_3 : -7 C_4 : -6 C_5 : -5 C_6 : -4 C_7 : -3 C_8 : -2 C_9 : -1 C_10 : 0 C_11 : 1 C_12 : 2 C_13 : 3 C_14 : 4 C_15 : 5 C_16 : 6 C_17 : 7 C_18 : 8 C_19 : 9 C_20 : 10 C_21 : 11 C_22 : 12 C_23 : 13 C_24 : 14 C_25 : 15 C_26 : 16 C_27 : 17 C_28 : 18 C_29 : 19 C_30 : 20 C_31 : 21 C_32 : 22 C_33 : 23 C_34 : 24 C_35 : 25 C_36 : 26 C_37 : 27 C_38 : 28 C_39 : 29 C_40 : 30 C_41 : 31 C_42 : 32 C_43 : 33 C_44 : 34 C_45 : 35 C_46 : 36 C_47 : 37 C_48 : 38 C_49 : 39 C_50 : 40 C_51 : 41 C_52 : 42 C_53 : 43 C_54 : 44 C_55 : 45 C_56 : 46 C_57 : 47 C_58 : 48 C_59 : 49 C_60 : 50 C_61 : 51 C_62 : 52 C_63 : 53 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x3 line.long 0x00 "CHARGER_TEST_CTRL_REG,Charger test control register" bitfld.long 0x00 14.--16. " CHARGER_TEST ,The following analogue signals may be mapped onto P1_07 pin, according to the following encoding:_000: Normal mode (no test mode selected)_001: Vptat (temperature sensor output) [1.4V max]_010: Vbat_sense after divider [1.2V]_011: Current loop output [0 to v30]_100: Voltage loop output [0 to v30]_101: Iref for the CC loop_110: Icharge reduced by 20_111: Imeas from output device_Note : To enable this mapping, TEST_CTRL2_REG.ANA_TESTMUX_CTRL should be set to either 4,6 or 8 and TEST_CTRL5_REG[0] should be set to '0'. Both these two registers reside in the GPIO module. It is also noted that the specific pin (P1_07) should be configured as analogue pin, by setting P1_07_MODE_REG[PID] = FUNC_ADC (see also the description of P0_00_MODE_REG in the GPIO block, again)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--13. " CHARGER_IOTRIM ,do not change, for test purposes only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--8. " I_CHARGE_TRIM ,do not change, for test purposes only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--3. " V_CHARGE_TRIM ,do not change, for test purposes only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x00 "CHARGER_THOT_COMP_TIMER_REG,Battery temperature comparator timer for _Hot_ zone" hexmask.long.word 0x00 16.--25. 1. " THOT_COMP_TIMER ,Returns the battery temperature comparator's timer dedicated for the _Hot_ level" hexmask.long.word 0x00 0.--9. 1. " THOT_COMP_SETTLING ,Charger's battery temperature comparator settling time (specified in us), specifically for the Hot temperature zone. The charger's digital block uses a dedicated timer to sample the specific comparator's output. The comparator's output is latched as soon as the timer expires, reaching 0. Then, the timer is reloaded with the settling time value and starts-over again_Note: The specific bit-field should be always set to a non-zero value" group.long 0x24++0x3 line.long 0x00 "CHARGER_TOTAL_CHARGE_TIMER_REG,Maximum total charge time limit register" hexmask.long.word 0x00 16.--31. 1. " TOTAL_CHARGE_TIMER ,Returns the current value of the overall charge timeout counter, running at a 1Hz clock. This timer has been set to 16 bits, so that it can count up to 10.5 hours, and ranges from 0 to MAX_TOTAL_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state" hexmask.long.word 0x00 0.--15. 1. " MAX_TOTAL_CHARGE_TIME ,This bit-field determines the maximum overall charging time allowed (measured in ticks of the 1Hz clock). If this is exceeded, a total charge time-out error will be captured by the Charger's controller and its FSM will move to the ERROR state. An IRQ will be also generated if the respective IRQ mask bit of CHARGER_ERROR_IRQ_MASK_REG is already set. In order to to exit this state, the _CHARGER_RESUME_ bit-field of CHARGER_CTRL_REG must be set, to enable the Charger's FSM switch from ERROR to DISABLED state and start-over._Note: The specific bit-field should be always set to a non-zero value" group.long 0x3C++0x3 line.long 0x00 "CHARGER_VBAT_COMP_TIMER_REG,Main Vbat comparator timer register" hexmask.long.word 0x00 16.--25. 1. " VBAT_COMP_TIMER ,Returns the current value of the timer used to determine when the output of the Vbat comparator (checking Vbat vs Pre_Charge and Replenish levels) must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from the value set in VBAT_COMP_SETTLING), the comparator's output is latched by the Charger's digital block and used by the FSM._Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over. In this mode, the specific comparator checks the level of Vbat against the Pre-Charge level. Hence, SW can periodically sample the status of this comparator by reading the MAIN_VBAT_COMP_OUT bit-field of CHARGER_STATUS_REG, to determine if Vbat has exceeded the Pre-Charge level or not" hexmask.long.word 0x00 0.--9. 1. " VBAT_COMP_SETTLING ,Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Pre-Charge and Replenish levels. The settings (voltage levels) of the comparator are controlled by the digital block of the Charger and they are driven based on the state of the main FSM (PRE_CHARGE, END_OF_CHARGE)" group.long 0xC++0x3 line.long 0x00 "CHARGER_VOLTAGE_PARAM_REG,Charger voltage settings register" bitfld.long 0x00 18.--23. " V_OVP ,This bit-field determines the VBAT Over-voltage protection limit. This Over-voltage protection level is used by the Charger's analogue circuitry and specifically by a dedicated comparator, the output of which is sampled by the digital block of the Charger. As soon as VBAT is detected to have reached or exceeded this level, the Charger's FSM moves to ERROR state, interrupting charging. If the respective Error IRQ mask bit is set, an Error IRQ pulse will be also generated._Regarding the actual range of supported values for this bit-field, see the the description of V_CHARGE bit-field of this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " V_REPLENISH ,This bit-field determines the absolute value (in V) of the Replenish voltage threshold. As soon as charging has been completed and the Charger's FSM has reached the END_OF_CHARGE state, the respective analogue comparator of the Charger compares VBAT with the Replenish level. If VBAT is found to have dropped below this level, charging should start-over again and in that case, the FSM moves again to the PRE_CHARGE state._Regarding the supported Replenish voltage levels, see the description of V_CHARGE bit-field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " V_PRECHARGE ,This bit-field determines the voltage level at which the battery is considered as Pre-charged and therefore the Charger's FSM should move to the CC_CHARGE state, entering the Constant Current charging phase._Regarding the supported Pre-Charge voltage levels, see also the description of V_CHARGE bit-field of this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " V_CHARGE ,This bit-field determines the charge voltage levels supported. The supported levels are determined according to the following encoding:_0 : 2.80V_1 : 2.85V_2 : 2.90V_3 : 2.95V_4 : 3.00V_5 : 3.05V_6 : 3.10V_7 : 3.15V_8 : 3.20V_9 : 3.25V_10 : 3.30V_11 : 3.35V_12 : 3.40V_13 : 3.45V_14 : 3.50V_15 : 3.55V_16 : 3.60V_17 : 3.65V_18 : 3.70V_19 : 3.75V_20 : 3.80V_21 : 3.82V_22 : 3.84V_23 : 3.86V_24 : 3.88V_25 : 3.90V_26 : 3.92V_27 : 3.94V_28 : 3.96V_29 : 3.98V_30 : 4.00V_31 : 4.02V_32 : 4.04V_33 : 4.06V_34 : 4.08V_35 : 4.10V_36 : 4.12V_37 : 4.14V_38 : 4.16V_39 : 4.18V_40 : 4.20V_41 : 4.22V_42 : 4.24V_43 : 4.26V_44 : 4.28V_45 : 4.30V_46 : 4.32V_47 : 4.34V_48 : 4.36V_49 : 4.38V_50 : 4.40V_51 : 4.42V_52 : 4.44V_53 : 4.46V_54 : 4.48V_55 : 4.50V_56 : 4.52V_57 : 4.54V_58 : 4.56V_59 : 4.58V_60 : 4.60V_61 : 4.70V_62 : 4.80V_63 : 4.90V*_It has to be noted that the specific values correspond to the normal battery temperature zone. However, the specific register field may be updated by the JEITA FSM (which checks the battery temperature either once or periodically), in order to adapt the charge voltage to the battery temperature zone (see also CHARGER_CTRL_REG.TBAT_MONITOR_MODE field as well). This is valid also for the other three fields of the current register. Consequently, in that case the register returns the Charge voltage settings that abide to the JEITA requirements for the battery (either COOL, WARM or NORMAL)._Note: Option _63_ (4.90V) is not supported for V_CHARGE, V_PRECHARGE and V_REPLENISH bit-fields (and respective levels). It should be used only in the V_OVP bit-field, as the (maximum) Over-voltage protection level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x3 line.long 0x00 "CHARGER_VOVP_COMP_TIMER_REG,Vbat OVP comparator timer register" rbitfld.long 0x00 26.--31. " OVP_INTERVAL_CHECK_TIMER ,The specific bit-field determines the current state of the timer used to periodically check the output of the Over-Voltage Protection comparator's output signal, as soon as the Charger's FSM reaches any of the charging states (PRE/CC/CV_CHARGE)._When this happens, the timer starts ticking with the 1Mhz clock, ranging from 0 up to the programmed interval threshold (see also OVP_INTERVAL_CHECK_THRES field). As soon as this timer reaches the programmed threshold value, the Vbat OVP comparator's output is evaluated, increasing or not the counter keeping the consecutive OVP events. It is noted that out of the charging states, the specific timer is kept frozen to zero, not counting._Note : See also the OVP_OCCURRENCES_CNT bit-field of CHARGER_STATUS_REG for the consecutive OVP events counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. " VBAT_OVP_COMP_TIMER ,Returns the current value of the timer used to determine when the Vbat Over-Voltage protection (OVP) comparator's output must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from VBAT_OVP_COMP_SETTLING), the comparator's output is latched by the Charger's digital block and used by the main FSM._Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over, sampling the status of the VBAT_OVP_COMP_OUT bit-field of CHARGER_STATUS_REG to determine if the Vbat has exceeded the OVP limit" bitfld.long 0x00 10.--15. " OVP_INTERVAL_CHECK_THRES ,This bit-field determines the periodic interval of checking the dedicated Vbat OVP comparator's output, when the Charger's FSM is in any of the charging states (PRE/CC/CV_CHARGE). The implementation is based on a dedicated timer, counting from zero up to the value programmed into this bit-field (see also OVP_INTERVAL_CHECK_TIMER field's description) and only when the FSM is in any of the three charging states. Out of these states, the timer is kept frozen to zero._As soon as this timer reaches the programmed threshold, the Vbat OVP comparator's output is sampled and depending on its level, (high or low), another counter, keeping the number of consecutive OVP events, is increased or not. The programmed threshold value should always be non-zero._Note: See also the OVP_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG, for the consecutive OVP events counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x00 0.--9. 1. " VBAT_OVP_COMP_SETTLING ,Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Over-Voltage level" width 0x0B tree.end endif tree "CHIP_VERSION" base ad:0x50040200 width 19. group.long 0x0++0x3 line.long 0x00 "CHIP_ID1_REG,Chip identification register 1" hexmask.long.byte 0x00 0.--7. 1. " CHIP_ID1 ,First character of device type _2522_ in ASCII." group.long 0x4++0x3 line.long 0x00 "CHIP_ID2_REG,Chip identification register 2" hexmask.long.byte 0x00 0.--7. 1. " CHIP_ID2 ,Second character of device type _2522_ in ASCII." group.long 0x8++0x3 line.long 0x00 "CHIP_ID3_REG,Chip identification register 3" hexmask.long.byte 0x00 0.--7. 1. " CHIP_ID3 ,Third character of device type _2522_ in ASCII." group.long 0xC++0x3 line.long 0x00 "CHIP_ID4_REG,Chip identification register 4" hexmask.long.byte 0x00 0.--7. 1. " CHIP_ID4 ,Fourth character of device type _2522_ in ASCII" group.long 0x14++0x3 line.long 0x00 "CHIP_REVISION_REG,Chip revision register" hexmask.long.byte 0x00 0.--7. 1. " CHIP_REVISION ,Chip version, corresponds with type number in ASCII._0x41 = 'A', 0x42 = 'B'" group.long 0x10++0x3 line.long 0x00 "CHIP_SWC_REG,Software compatibility register" rbitfld.long 0x00 0.--3. " CHIP_SWC ,SoftWare Compatibility code._Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware._Can be used by software developers to write silicon revision dependent code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF8++0x3 line.long 0x00 "CHIP_TEST1_REG,Chip test register 1" hexmask.long.byte 0x00 0.--7. 1. " CHIP_LAYOUT_REVISION ,Chip layout revision, corresponds with type number in ASCII._0x41 = 'A', 0x42 = 'B'" group.long 0xFC++0x3 line.long 0x00 "CHIP_TEST2_REG,Chip test register 2" rbitfld.long 0x00 0.--3. " CHIP_METAL_OPTION ,Chip metal option value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "CMAC" base ad:0x40000000 width 23. group.long 0x2000++0x3 line.long 0x00 "CM_CTRL_SYS_REG,CMAC and System Control Register" rbitfld.long 0x00 31. " CMAC_CONST_1 ,Always read as _1_._Note: Creating an always non-zero register value, making easier a visual check of register when power domain is off" "0,1" rbitfld.long 0x00 15. " CMAC_LOCKUP_STATE ," "0,1" rbitfld.long 0x00 14. " CMAC_WDOG_EXPIRE_STATE ," "0,1" textline " " rbitfld.long 0x00 13. " CMAC_SYSMEMCTRL_ERROR_STATE ," "0,1" rbitfld.long 0x00 12. " CMAC_CPU_ERROR_STATE ," "0,1" rbitfld.long 0x00 11. " CMAC_BS_ERROR_STATE ," "0,1" textline " " rbitfld.long 0x00 10. " CMAC_FW_ERROR_STATE ," "0,1" rbitfld.long 0x00 9. " MCPU_SLEEPING_STATE ," "0,1" rbitfld.long 0x00 8. " CMAC_RST_MCPU_STATE ," "0,1" textline " " rbitfld.long 0x00 7. " CMAC_RST_BS_STATE ," "0,1" bitfld.long 0x00 1. " CMAC2SYS_IRQ_CLR ,Writing _0_ will have no effect._Writing _1_ will clear the CMAC2SYS_IRQ, a process that depends on the state of CMAC and the relationship of the PCLK and CMAC clocks._Reading will return _1_ as long as the clearing process is pending, otherwise it will return _0_" "0,1" rbitfld.long 0x00 0. " CMAC2SYS_IRQ_STATE ," "0,1" group.long 0x2104++0x3 line.long 0x00 "CM_DIAG_IRQ1_EDGE_REG,Diagnostic IRQ on Word1 - Edge Register" bitfld.long 0x00 7. " DIAG1_PHY_TX_EN_RFCU ," "0,1" bitfld.long 0x00 6. " DIAG1_PHY_RX_EN_RFCU ," "0,1" bitfld.long 0x00 5. " DIAG1_DCF_26 ," "0,1" textline " " bitfld.long 0x00 4. " DIAG1_DCF_25 ," "0,1" bitfld.long 0x00 3. " DIAG1_DCF_24 ," "0,1" bitfld.long 0x00 2. " DIAG1_DCF_23 ," "0,1" textline " " bitfld.long 0x00 1. " DIAG1_DCF_22 ," "0,1" bitfld.long 0x00 0. " DIAG1_DCF_21 ,0: The positive edge is selected to set the corresponding bit of CM_DIAG_IRQ1_STAT_REG._1: The negative edge is selected" "0,1" group.long 0x210C++0x3 line.long 0x00 "CM_DIAG_IRQ1_MASK_REG,Diagnostic IRQ on Word1 - Mask Register" bitfld.long 0x00 10. " DIAG1_SIGNAL_DETECTED ," "0,1" bitfld.long 0x00 9. " DIAG1_MATCH0101 ," "0,1" bitfld.long 0x00 8. " DIAG1_SYNC_FOUND ," "0,1" textline " " bitfld.long 0x00 7. " DIAG1_PHY_TX_EN_RFCU ," "0,1" bitfld.long 0x00 6. " DIAG1_PHY_RX_EN_RFCU ," "0,1" bitfld.long 0x00 5. " DIAG1_DCF_26 ," "0,1" textline " " bitfld.long 0x00 4. " DIAG1_DCF_25 ," "0,1" bitfld.long 0x00 3. " DIAG1_DCF_24 ," "0,1" bitfld.long 0x00 2. " DIAG1_DCF_23 ," "0,1" textline " " bitfld.long 0x00 1. " DIAG1_DCF_22 ," "0,1" bitfld.long 0x00 0. " DIAG1_DCF_21 ,1: Raise an DIAG_IRQ when the corresponding bit of CM_DIAG_IRQ1_STAT_REG is also _1_._0: Mask the state of the corresponding bit of CM_DIAG_IRQ1_STAT_REG in order to not trigger DIAG_IRQ" "0,1" group.long 0x2108++0x3 line.long 0x00 "CM_DIAG_IRQ1_STAT_REG,Diagnostic IRQ on Word1 - Status Register" bitfld.long 0x00 10. " DIAG1_SIGNAL_DETECTED ," "0,1" bitfld.long 0x00 9. " DIAG1_MATCH0101 ," "0,1" bitfld.long 0x00 8. " DIAG1_SYNC_FOUND ," "0,1" textline " " bitfld.long 0x00 7. " DIAG1_PHY_TX_EN_RFCU ," "0,1" bitfld.long 0x00 6. " DIAG1_PHY_RX_EN_RFCU ," "0,1" bitfld.long 0x00 5. " DIAG1_DCF_26 ," "0,1" textline " " bitfld.long 0x00 4. " DIAG1_DCF_25 ," "0,1" bitfld.long 0x00 3. " DIAG1_DCF_24 ," "0,1" bitfld.long 0x00 2. " DIAG1_DCF_23 ," "0,1" textline " " bitfld.long 0x00 1. " DIAG1_DCF_22 ," "0,1" bitfld.long 0x00 0. " DIAG1_DCF_21 ,1: the corresponding event is pending._0: the corresponding event is not pending._Writing a '1' will clear the corresponding bit._Writing a '0' into a bit will have no effect._Use this register to detect and acknowledge the source that triggers the DIAG_IRQ" "0,1" group.long 0x2100++0x3 line.long 0x00 "CM_DIAG_IRQ1_WORD_REG,Diagnostic IRQ on Word1 - Word1 Register" rbitfld.long 0x00 10. " DIAG1_SIGNAL_DETECTED ," "0,1" rbitfld.long 0x00 9. " DIAG1_MATCH0101 ," "0,1" rbitfld.long 0x00 8. " DIAG1_SYNC_FOUND ," "0,1" textline " " rbitfld.long 0x00 7. " DIAG1_PHY_TX_EN_RFCU ," "0,1" rbitfld.long 0x00 6. " DIAG1_PHY_RX_EN_RFCU ," "0,1" rbitfld.long 0x00 5. " DIAG1_DCF_26 ," "0,1" textline " " rbitfld.long 0x00 4. " DIAG1_DCF_25 ," "0,1" rbitfld.long 0x00 3. " DIAG1_DCF_24 ," "0,1" rbitfld.long 0x00 2. " DIAG1_DCF_23 ," "0,1" textline " " rbitfld.long 0x00 1. " DIAG1_DCF_22 ," "0,1" rbitfld.long 0x00 0. " DIAG1_DCF_21 ,Same signal as the one in CM_DIAG_WORD1_REG._Refer to CM_DIAG_WORD1_REG for signal description" "0,1" group.long 0x2004++0x3 line.long 0x00 "CM_WDOG_REG,CMAC Watch Dog Control Register" rbitfld.long 0x00 31. " SYS2CMAC_WDOG_FREEZE ,A read-only copy of SET_FREEZE_REG->FRZ_CMAC_WDOG value" "0,1" bitfld.long 0x00 30. " SYS2CMAC_WDOG_FREEZE_DIS ,Setting to '1' will mask the SYS2CMAC_WDOG_FREEZE, which is provided by SET_FREEZE_REG->FRZ_CMAC_WDOG._The field can be only set to '1', so it can be set during the initilization and it will not change during the reloadings._It can be reseted either via power cycling the Power Domain or via the CLK_RADIO_REG->CMAC_SYNCH_RESET" "0,1" bitfld.long 0x00 29. " CM_WDOG_EXPIRE ,This bit automatically is set to _1_ as soon as CM_WDOG_CNT=0, causing CM_WDOG_CNT to start counting again from the value of _16_ and also asserting CM_ERROR_REG->CM_WDOG_EXPIRE_ERR._If the SW will write CM_WDOG_EXPIRE = 0 and CM_WDOG_CNT=0, then at the next WDOG clock cycle the CM_WDOG_EXPIRE will automatically be set to to _1_._If the SW will write CM_WDOG_EXPIRE = 1 and CM_WDOG_CNT=0, then at the next WDOG clock cycle the CM_WDOG_SYS_RST_REQ will automatically be set to _1_._The CM_WDOG_SYS_RST_REQ will reset the system and will update the RESET_STAT_REG->CMAC_WDOGRESET_STAT._Refer also to CM_EXC_STAT_REG->EXC_WDOG_EARLY" "0,1" textline " " rbitfld.long 0x00 28. " CM_WDOG_SYS_RST_REQ ,Refer to CM_WDOG_EXPIRE" "0,1" bitfld.long 0x00 17.--18. " CM_WDOG_WRITE_VALID ,In order to allow a write of any of the remaining fields, this value must be also written simultaneously with the value _3_._Reading this field will return always '0'" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. " CM_WDOG_CNT ,Provides access to the counter, which counts down every 10.24 msec._FW should reload the WDOG counter by writing to CM_WDOG_REG the value (CM_WDOG_CNT | CM_WDOG_WRITE_VALID)._The counter will start counting immediately after the power up of the Power Domain" width 0x0B tree.end tree "CMAC_TIMER_SLP" base ad:0x50010400 width 18. group.long 0x4++0x3 line.long 0x00 "CM_SLP_CTRL2_REG,CMAC Sleep Control 2 (no RMW)" bitfld.long 0x00 8. " CMAC_WAKEUP_ON_SWD_STATE ,Provides the current state of CMAC_WAKEUP_ON_SWD._Writing '1' will clear this bit._Writing '0' has no effect._When CM_SLP_CTRL_REG->CMAC_WAKEUP_ON_SWD_EN=1 and the Radio Power Domain is down and SYS_CTRL_REG->CMAC_DEBUGGER_ENABLE=1 then any negative edge on SWDCLK pin will set the CMAC_WAKEUP_ON_SWD._The CMAC_WAKEUP_ON_SWD logically OR-ed with SLP_TIMER_IRQ is connected to PDC and thus it is able to wake up the CMAC, allowing the connection of CMAC Cortex with the debugger" "0,1" rbitfld.long 0x00 7. " SLP_TIMER_ACTIVE ,Refer to CM_SLP_CTRL_REG->SLP_TIMER_ACTIVE" "0,1" rbitfld.long 0x00 6. " LP_CLK_STATE ,Refer to CM_SLP_CTRL_REG->LP_CLK_STATE" "0,1" textline " " rbitfld.long 0x00 5. " SLP_TIMER_CNT_SIGN ,Provides the SLP_TIMER_CNT[32] bit, which corresponds to the sign bit" "0,1" bitfld.long 0x00 2. " SLP_TIMER_IRQ_SET ,Writing '1' will cause the IRQ to be set. This field remains to '1' until the IRQ is set._Writing '0' has no effect._System CPU SW may use this field to force CMAC to wakeup through SLP_TIMER._Note that typically SW wakes up CMAC through the SYS2CMAC_IRQ (via PDC)" "0,1" bitfld.long 0x00 1. " SLP_TIMER_IRQ_CLR ,Writing '1' will cause the IRQ to be cleared. This field remains to '1' until the IRQ is cleared._Writing '0' has no effect._Note that clearing the IRQ is not possible as long as the Timer is _1_, since the Expire event has higher priority" "0,1" textline " " rbitfld.long 0x00 0. " SLP_TIMER_IRQ_STATE ,Provides the current state of the CMAC Sleep Timer IRQ" "0,1" group.long 0x0++0x3 line.long 0x00 "CM_SLP_CTRL_REG,CMAC Sleep Control 1 (allowed to RMW)" bitfld.long 0x00 24. " CMAC_WAKEUP_ON_SWD_EN ,If '1' then enable the generation of CMAC_WAKEUP_ON_SWD" "0,1" bitfld.long 0x00 9. " TCLK_FROM_LPCLK ,The FW must be synchronized with LP_CLK negedge in order to change this bit" "0,1" bitfld.long 0x00 8. " TCLK_FROM_PCLK ,The FW must be synchronized with LP_CLK negedge in order to change this bit" "0,1" textline " " rbitfld.long 0x00 7. " SLP_TIMER_ACTIVE ," "0,1" rbitfld.long 0x00 6. " LP_CLK_STATE ,Current state of LP_CLK._Typically used only by System CPU._Refer also to CM_EV_LATCHED_REG->EV1C_LP_CLK_* and CM_SLP_CTRL2_REG->LP_CLK_STATE" "0,1" rbitfld.long 0x00 5. " SLP_TIMER_CNT_SIGN ,Refer to CM_SLP_CTRL2_REG->SLP_TIMER_CNT_SIGN" "0,1" textline " " bitfld.long 0x00 0. " SLP_TIMER_SW ,The FW must be synchronized with LP_CLK negedge in order to change this bit._If 1: Initiate the sequence of stop counting with LL_TIMERx and start counting with the Sleep Timer._If 0: Initiate the sequence of stop counting with Sleep Timer and start counting with the LL_TIMERx._Writing a _1_ will be effective only if SLP_TIMER_SEL_PCLK is written also with _0_, regardless of the previous state of SLP_TIMER_SEL_PCLK._Writing a _0_ will be effective only if SLP_TIMER_SEL_PCLK is written also with _1_, regardless of the previous state of SLP_TIMER_SEL_PCLK._The end of the sequence is reported via SLP_TIMER_ACTIVE" "0,1" group.long 0x8++0x3 line.long 0x00 "CM_SLP_TIMER_REG,CMAC Sleep Timer" hexmask.long 0x00 0.--31. 1. " CM_SLP_TIMER_VALUE ,The low 32 bits of the signed value of the 33 bit CMAC Sleep Timer._The sign bit 32 can be fetched via CM_SLP_CTRL_REG->SLP_TIMER_CNT_SIGN._It's possible to perform only 32-bit write access, while every write access will set the sign bit 32 to '0'._A read or write access with CM_SLP_CTRL_REG->TCLK_FROM_PCLK equal to 0 will cause a bus error._As long as the value is _1_ then the expiration and the IRQ signal are asserted." width 0x0B tree.end tree "CRG_COM" base ad:0x50020900 width 19. group.long 0x4++0x3 line.long 0x00 "CLK_COM_REG,Peripheral divider register" bitfld.long 0x00 16.--17. " LCD_EXT_CLK_SEL ,Select LCD external clock speed._0x0: 1 Hz_0x1: 62.5 Hz_0x2: 125 Hz_0x3: off" "0,1,2,3" bitfld.long 0x00 14.--15. " SNC_DIV ,Division factor for SNC, w.r.t. pclk setting_0x0 = divide by 1_0x1 = divide by 2_0x2 = divide by 4_0x3 = divide by 8" "0,1,2,3" bitfld.long 0x00 13. " SDADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 12. " I2C2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 11. " I2C2_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 10. " I2C_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 9. " I2C_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 8. " SPI2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 7. " SPI2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 6. " SPI_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 5. " SPI_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 4. " UART3_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 3. " UART3_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 2. " UART2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 1. " UART2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 0. " UART_ENABLE ,Enables the clock" "0,1" group.long 0xC++0x3 line.long 0x00 "RESET_CLK_COM_REG,Peripheral divider register RESET register. Reads back 0x0000" bitfld.long 0x00 16.--17. " LCD_EXT_CLK_SEL ,Select LCD external clock speed._0x0: 1 Hz_0x1: 62.5 Hz_0x2: 125 Hz_0x3: off" "0,1,2,3" bitfld.long 0x00 14.--15. " SNC_DIV ,Division factor for SNC, w.r.t. pclk setting_0x0 = divide by 1_0x1 = divide by 2_0x2 = divide by 4_0x3 = divide by 8" "0,1,2,3" bitfld.long 0x00 13. " SDADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 12. " I2C2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 11. " I2C2_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 10. " I2C_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 9. " I2C_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 8. " SPI2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 7. " SPI2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 6. " SPI_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 5. " SPI_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 4. " UART3_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 3. " UART3_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 2. " UART2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 1. " UART2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 0. " UART_ENABLE ,Enables the clock" "0,1" group.long 0x8++0x3 line.long 0x00 "SET_CLK_COM_REG,Peripheral divider register SET register. Reads back 0x0000" bitfld.long 0x00 16.--17. " LCD_EXT_CLK_SEL ,Select LCD external clock speed._0x0: 1 Hz_0x1: 62.5 Hz_0x2: 125 Hz_0x3: off" "0,1,2,3" bitfld.long 0x00 14.--15. " SNC_DIV ,Division factor for SNC, w.r.t. pclk setting_0x0 = divide by 1_0x1 = divide by 2_0x2 = divide by 4_0x3 = divide by 8" "0,1,2,3" bitfld.long 0x00 13. " SDADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 12. " I2C2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 11. " I2C2_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 10. " I2C_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 9. " I2C_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 8. " SPI2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 7. " SPI2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 6. " SPI_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 5. " SPI_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 4. " UART3_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 3. " UART3_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 2. " UART2_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 1. " UART2_ENABLE ,Enables the clock" "0,1" textline " " bitfld.long 0x00 0. " UART_ENABLE ,Enables the clock" "0,1" width 0x0B tree.end tree "CRG_PER" base ad:0x50030C00 width 19. group.long 0x4++0x3 line.long 0x00 "CLK_PER_REG,Peripheral divider register" bitfld.long 0x00 8.--12. " MC_TRIG_DIV ,Trigger divider for the motor controller_0x0: divide LP_CLK by 1_0x1: divide LP_CLK by 2_..._0x1F: divide LP_CLK by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3.--7. " MC_CLK_DIV ,Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider:_0x0: divide LP clock by 1_0x1: divide LP clock by 2_..._0x1F: divide LP clock by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " MC_CLK_EN ,Enables the clock" "0,1" textline " " bitfld.long 0x00 1. " LRA_CLK_EN ,Enables the clock" "0,1" bitfld.long 0x00 0. " GPADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock/ 2" "0,1" group.long 0x40++0x3 line.long 0x00 "PCM_DIV_REG,PCM divider and enables" bitfld.long 0x00 13. " PCM_SRC_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" bitfld.long 0x00 12. " CLK_PCM_EN ,Enable for the internally generated PCM clock_The PCM_DIV must be set before or together with CLK_PCM_EN" "0,1" hexmask.long.word 0x00 0.--11. 1. " PCM_DIV ,PCM clock divider" group.long 0x44++0x3 line.long 0x00 "PCM_FDIV_REG,PCM fractional division register" hexmask.long.word 0x00 0.--15. 1. " PCM_FDIV ,These bits define the fractional division part of the PCM clock. The left most '1' defines the denominator, the number of '1' bits define the numerator. E.g._0x0110 means 2/9, with a distribution of 1.0001.0000_0xfeee means 13/16, with a distribution of 1111.1110.1110.1110" group.long 0x48++0x3 line.long 0x00 "PDM_DIV_REG,PDM divider and enables" bitfld.long 0x00 9. " PDM_MASTER_MODE ,Master mode selection_0: slave mode_1: master mode" "0,1" bitfld.long 0x00 8. " CLK_PDM_EN ,Enable for the internally generated PDM clock_The PDM_DIV must be set before or together with CLK_PDM_EN" "0,1" hexmask.long.byte 0x00 0.--7. 1. " PDM_DIV ,PDM clock divider" group.long 0x50++0x3 line.long 0x00 "PERRAM_CONFIG_REG,Peripheral RAM configurations" bitfld.long 0x00 4. " MC_RAM_MSE ,Margin overrule enable" "0,1" bitfld.long 0x00 0.--3. " MC_RAM_MS ,Margin setting for RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "RESET_CLK_PER_REG,Peripheral divider register RESET register, reads 0x0000" bitfld.long 0x00 8.--12. " MC_TRIG_DIV ,Trigger divider for the motor controller_0x0: divide LP_CLK by 1_0x1: divide LP_CLK by 2_..._0x1F: divide LP_CLK by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3.--7. " MC_CLK_DIV ,Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider:_0x0: divide LP clock by 1_0x1: divide LP clock by 2_..._0x1F: divide LP clock by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " MC_CLK_EN ,Enables the clock" "0,1" textline " " bitfld.long 0x00 1. " LRA_CLK_EN ,Enables the clock" "0,1" bitfld.long 0x00 0. " GPADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock/ 2" "0,1" group.long 0x8++0x3 line.long 0x00 "SET_CLK_PER_REG,Peripheral divider register SET register, reads 0x0000" bitfld.long 0x00 8.--12. " MC_TRIG_DIV ,Trigger divider for the motor controller_0x0: divide LP_CLK by 1_0x1: divide LP_CLK by 2_..._0x1F: divide LP_CLK by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3.--7. " MC_CLK_DIV ,Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider:_0x0: divide LP clock by 1_0x1: divide LP clock by 2_..._0x1F: divide LP clock by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " MC_CLK_EN ,Enables the clock" "0,1" textline " " bitfld.long 0x00 1. " LRA_CLK_EN ,Enables the clock" "0,1" bitfld.long 0x00 0. " GPADC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock/ 2" "0,1" group.long 0x4C++0x3 line.long 0x00 "SRC_DIV_REG,SRC divider and enables" bitfld.long 0x00 8. " CLK_SRC_EN ,Enable for the internally generated SRC clock_The SRC_DIV must be set before or together with CLK_SRC_EN" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SRC_DIV ,SRC clock divider" width 0x0B tree.end tree "CRG_SYS" base ad:0x50040500 width 19. group.long 0x4++0x3 line.long 0x00 "BATCHECK_REG," bitfld.long 0x00 7. " BATCHECK_LOAD_ENABLE ,Enable a current load on the battery" "0,1" bitfld.long 0x00 4.--6. " BATCHECK_ILOAD ,Set the current load to (ILOAD+1) mA" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " BATCHECK_TRIM ,Trim the current load with steps of 2.7% from -19.1% to +19.1%._0: +0.0% , 8: -0%_1: +2.7% , 9: -2.7%_2: +5.5% , 10: -5.5%_3: +8.2% , 11: -8.2%_4: +10.9% , 12: -10.9%_5: +13.6% , 13: -13.6%_6: +16.4% , 14: -16.4%_7: +19.1% , 15: -19.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x0++0x3 line.long 0x00 "CLK_SYS_REG,Peripheral divider register" bitfld.long 0x00 5. " CLK_CHG_EN ,Enables the clocks for the charger FSM block" "0,1" bitfld.long 0x00 4. " LCD_RESET_REQ ,Generates a SW reset towards the LCD controller" "0,1" bitfld.long 0x00 1. " LCD_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 0. " LCD_ENABLE ,Enables the clock" "0,1" group.long 0x40++0x3 line.long 0x00 "SYSRAM_CONFIG_REG,System RAM configurations" bitfld.long 0x00 8. " CACHERAM_LPMX ,LPM Enable. Asynchronous. Active low. Asserting lpmx low will_enable the leakage reduction circuit to the memory cells." "0,1" bitfld.long 0x00 6.--7. " CACHERAM_MARGIN ,Margin Control. Asynchronous. Recommended setting is 2b10._These bits control the read and write margin. 2b00 provides the_highest margin (slowest). 2b11 provides the least margin (fastest)" "0,1,2,3" bitfld.long 0x00 5. " CACHERAM_DST ,Disable Self Time. Asynchronous. Active high. When asserted_high, dst overrides the self-timed circuitry and causes the read and_write margin to be fixed by the falling edge of clk. This mode is only_enabled if margin is set to 2b00 (slowest setting). dst should be_set low during normal operation" "0,1" textline " " bitfld.long 0x00 4. " M31RAM_MSE ,Margin overrule enable for CRYPTO, QSPIC and USB RAM" "0,1" bitfld.long 0x00 0.--3. " M31RAM_MS ,Margin setting for CRYPTO, QSPIC and USB RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "CRG_TOP" base ad:0x50000000 width 24. group.long 0xEC++0x3 line.long 0x00 "ANA_STATUS_REG," rbitfld.long 0x00 14. " COMP_VBUS_HIGH ," "0,1" rbitfld.long 0x00 13. " COMP_VBUS_LOW ," "0,1" rbitfld.long 0x00 12. " COMP_VBAT_HIGH ," "0,1" textline " " rbitfld.long 0x00 11. " COMP_VBAT_LOW ," "0,1" rbitfld.long 0x00 10. " COMP_VDD_OK ," "0,1" rbitfld.long 0x00 9. " VBUS_AVAILABLE ," "0,1" textline " " rbitfld.long 0x00 8. " BANDGAP_OK ," "0,1" rbitfld.long 0x00 7. " LDO_3V0_VBAT_OK ," "0,1" rbitfld.long 0x00 6. " LDO_3V0_VBUS_OK ," "0,1" textline " " rbitfld.long 0x00 5. " LDO_1V8P_OK ," "0,1" rbitfld.long 0x00 4. " LDO_1V8_OK ," "0,1" rbitfld.long 0x00 3. " LDO_RADIO_OK ," "0,1" textline " " rbitfld.long 0x00 2. " LDO_CORE_OK ," "0,1" rbitfld.long 0x00 1. " LDO_VDD_HIGH_OK ," "0,1" rbitfld.long 0x00 0. " BOD_VIN_NOK ," "0,1" group.long 0xC8++0x3 line.long 0x00 "AON_SPARE_REG,Spare register" bitfld.long 0x00 1. " KEEP_VDDNOTSLEEP_ON ,If this bit is set to '1', then the VDD_NOTSLEEP is not switched off during sleep._This means higher sleep leakage current" "0,1" bitfld.long 0x00 0. " POR_TST_DET_DISABLE ," "0,1" group.long 0x50++0x3 line.long 0x00 "BANDGAP_REG,bandgap trimming" bitfld.long 0x00 12. " BANDGAP_ENABLE_CLAMP ,Enables a supply clamp inside the bandgap that improves PSRR. Should be enabled by software after cold boot" "0,1" bitfld.long 0x00 6.--11. " BGR_ITRIM ,Current trimming for bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " BGR_TRIM ,Trim register for bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA4++0x3 line.long 0x00 "BIAS_VREF_SEL_REG," bitfld.long 0x00 4.--7. " BIAS_VREF_RF2_SEL ,same as BIAS_VREF_RF1_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " BIAS_VREF_RF1_SEL ,Vref_code | Vref_Voltage (mV)_0:900_1:930_2:960_3:990_4:1020_5:1050_6:1080_7:1110_8:1140_9:1170_10:1200_11:1230_12:1260_13:1290_14:1320_15:1350" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x60++0x3 line.long 0x00 "BOD_CTRL_REG,Brown Out Detection control register" bitfld.long 0x00 17. " BOD_TEST_ENABLE ," "0,1" bitfld.long 0x00 16. " BOD_V14_RST_EN ,If set, generate power-on reset on channel V14" "0,1" bitfld.long 0x00 15. " BOD_V18F_RST_EN ,If set, generate power-on reset on channel V18F" "0,1" textline " " bitfld.long 0x00 14. " BOD_VDD_RST_EN ,If set, generate power-on reset on channel VDD" "0,1" bitfld.long 0x00 13. " BOD_V18P_RST_EN ,If set, generate power-on reset on channel V18P" "0,1" bitfld.long 0x00 12. " BOD_V18_RST_EN ,If set, generate power-on reset on channel V18" "0,1" textline " " bitfld.long 0x00 11. " BOD_V30_RST_EN ,If set, generate power-on reset on channel V30" "0,1" bitfld.long 0x00 10. " BOD_VBAT_RST_EN ,If set, generate power-on reset on channel VBAT" "0,1" bitfld.long 0x00 9. " BOD_V14_EN ,Enable brown-out detection for channel V14" "0,1" textline " " bitfld.long 0x00 8. " BOD_V18F_EN ,Enable brown-out detection for channel V18F" "0,1" bitfld.long 0x00 7. " BOD_VDD_EN ,Enable brown-out detectionfor channel VDD" "0,1" bitfld.long 0x00 6. " BOD_V18P_EN ,Enable brown-out detectio for channel V18P" "0,1" textline " " bitfld.long 0x00 5. " BOD_V18_EN ,Enable brown-out detectionfor channel V18" "0,1" bitfld.long 0x00 4. " BOD_V30_EN ,Enable brown-out detection for channel V30" "0,1" bitfld.long 0x00 3. " BOD_VBAT_EN ,Enable brown-out detectionfor channel VBAT" "0,1" textline " " bitfld.long 0x00 2. " BOD_STATUS_CLEAR ,Clears the brownout status register" "0,1" bitfld.long 0x00 0.--1. " BOD_CLK_DIV ,Brown-out detector clock divider._0x0: BOD_CLK/1_0x1: BOD_CLK/2_0x2: BOD_CLK/4_0x3: BOD_CLK/8 (BOD_CLK = 1MHz)" "0,1,2,3" group.long 0x64++0x3 line.long 0x00 "BOD_LVL_CTRL0_REG," hexmask.long.word 0x00 18.--26. 1. " BOD_LVL_V18 ,Brown-out detection level for V18._VTH_BOD = 1.2 * (BOD_LVL+1)/192" hexmask.long.word 0x00 9.--17. 1. " BOD_LVL_V30 ,Brown-out detection level for V30._VTH_BOD = 1.2 * (BOD_LVL+1)/192" hexmask.long.word 0x00 0.--8. 1. " BOD_LVL_VBAT ,Brown-out detection level for VBAT.._VTH_BOD = 1.5*(1.2 * (BOD_LVL+1)/192)" group.long 0x68++0x3 line.long 0x00 "BOD_LVL_CTRL1_REG," hexmask.long.byte 0x00 17.--24. 1. " BOD_LVL_VDD_RET ,Brown-out detection level for VDD in sleep._VTH_BOD = 1.2 * (BOD_LVL+1)/192" hexmask.long.byte 0x00 9.--16. 1. " BOD_LVL_VDD_ON ,Brown-out detection level for VDD in active._VTH_BOD = 1.2 * (BOD_LVL+1)/192" hexmask.long.word 0x00 0.--8. 1. " BOD_LVL_V18P ,Brown-out detection level for V18P._VTH_BOD = 1.2 * (BOD_LVL+1)/192" group.long 0x6C++0x3 line.long 0x00 "BOD_LVL_CTRL2_REG," hexmask.long.word 0x00 9.--17. 1. " BOD_LVL_V14 ,Brown-out detection level for V14_VTH_BOD = 1.2 * (BOD_LVL+1)/192" hexmask.long.word 0x00 0.--8. 1. " BOD_LVL_V18F ,Brown-out detection level for V18F._VTH_BOD = 1.2 * (BOD_LVL+1)/192" group.long 0x90++0x3 line.long 0x00 "BOD_STATUS_REG," group.long 0x0++0x3 line.long 0x00 "CLK_AMBA_REG,HCLK, PCLK, divider and clock gates" bitfld.long 0x00 15. " QSPI2_ENABLE ,Clock enable for QSPI RAM controller" "0,1" bitfld.long 0x00 13.--14. " QSPI2_DIV ,QSPI divider_00 = divide by 1_01 = divide by 2_10 = divide by 4_11 = divide by 8" "0,1,2,3" bitfld.long 0x00 12. " QSPI_ENABLE ,Clock enable for QSPI controller" "0,1" textline " " bitfld.long 0x00 10.--11. " QSPI_DIV ,QSPI divider_00 = divide by 1_01 = divide by 2_10 = divide by 4_11 = divide by 8" "0,1,2,3" bitfld.long 0x00 9. " OTP_ENABLE ,Clock enable for OTP controller" "0,1" bitfld.long 0x00 8. " TRNG_CLK_ENABLE ,Clock enable for TRNG block" "0,1" textline " " bitfld.long 0x00 6. " AES_CLK_ENABLE ,Clock enable for AES crypto block" "0,1" bitfld.long 0x00 4.--5. " PCLK_DIV ,APB interface clock, Cascaded with HCLK:_00 = divide hclk by 1_01 = divide hclk by 2_10 = divide hclk by 4_11 = divide hclk by 8" "0,1,2,3" bitfld.long 0x00 0.--2. " HCLK_DIV ,AHB interface and microprocessor clock. Source clock divided by:_000 = divide hclk by 1_001 = divide hclk by 2_010 = divide hclk by 4_011 = divide hclk by 8_1xx = divide hclk by 16" "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x00 "CLK_CTRL_REG,Clock control register" rbitfld.long 0x00 15. " RUNNING_AT_PLL96M ,Indicates that the PLL96MHz clock is used as clock, and may not be switched off" "0,1" rbitfld.long 0x00 14. " RUNNING_AT_XTAL32M ,Indicates that the XTAL32M clock is used as clock, and may not be switched off" "0,1" rbitfld.long 0x00 13. " RUNNING_AT_RC32M ,Indicates that the RC32M clock is used as clock" "0,1" textline " " rbitfld.long 0x00 12. " RUNNING_AT_LP_CLK ,Indicates that either the LP_CLK is being used as clock" "0,1" bitfld.long 0x00 6. " CLK_WDOG_ENABLE ,Enables the CLOCK watchdog" "0,1" bitfld.long 0x00 4. " USB_CLK_SRC ,Selects the USB source clock_0 : PLL clock, divided by 2_1 : HCLK" "0,1" textline " " bitfld.long 0x00 2.--3. " LP_CLK_SEL ,Sets the clock source of the LowerPower clock_0x0: RC32K_0x1: RCX_0x2: XTAL32K through the oscillator with an external Crystal._0x3: XTAL32K through an external square wave generator (set PID of GPIO to FUNC_GPIO)" "0,1,2,3" bitfld.long 0x00 0.--1. " SYS_CLK_SEL ,Selects the clock source._0x0 : XTAL32M_0x1 : RC32M_0x2 : The Low Power clock is used_0x3 : The PLL96Mhz is used" "XTAL16M,RC16M,LP_CLK,PLL96M" group.long 0x10++0x3 line.long 0x00 "CLK_RADIO_REG,Radio PLL control register" bitfld.long 0x00 5. " RFCU_ENABLE ,Enable the RF control Unit clock" "0,1" bitfld.long 0x00 4. " CMAC_SYNCH_RESET ,Force synchronous reset to CMAC core and Sleep Timer. Its effective only when both Radio and Timer Power Domains are powered and the clocks are enabled._CMAC CPU and CMAC registers, including the retained ones, will be reset._The 1 should be kept for enough time to make sure that it will be captured by CMAC, Low Power and APB clocks._Should be kept to 1 at least until CM_SLP_SYS_REG->CMAC_RST_BS = 1._To avoid issues with CMAC CPU Debugger its recommended to keep the resetting period short" "0,1" bitfld.long 0x00 3. " CMAC_CLK_SEL ,Selects the clock source_1 = DIV1 clock_0 = DIVN clock" "0,1" textline " " bitfld.long 0x00 2. " CMAC_CLK_ENABLE ,Enables the clock" "0,1" bitfld.long 0x00 0.--1. " CMAC_DIV ,Division factor for CMAC_0x0 = divide by 1_0x1 = divide by 2_0x2 = divide by 4_0x3 = divide by 8" "0,1,2,3" group.long 0x3C++0x3 line.long 0x00 "CLK_RC32K_REG,32 kHz RC oscillator register" bitfld.long 0x00 1.--4. " RC32K_TRIM ,0000 = lowest frequency_0111 = default_1111 = highest frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " RC32K_ENABLE ,Enables the 32kHz RC oscillator" "0,1" group.long 0x44++0x3 line.long 0x00 "CLK_RC32M_REG,Fast RC control register" bitfld.long 0x00 25. " RC32M_STARTUP_DISABLE ,Gates the RC32 enable from the startup block._The enable from the clksel and CLK_RC32M_REG[0] are not gated by this bit" "0,1" bitfld.long 0x00 20.--21. " RC32M_INIT_RANGE ,Course frequency adjustment" "0,1,2,3" hexmask.long.byte 0x00 12.--19. 1. " RC32M_INIT_DEL ,Fine frequency adjustment" textline " " bitfld.long 0x00 9.--11. " RC32M_INIT_DTCF ,Fine duty-cycle adjustment._0x0: minimum_0x2: default_0x4: maximum" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--8. " RC32M_INIT_DTC ,Course duty-cycle adjustment._0x0: minimum_0x5: default_0xA: maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " RC32M_BIAS ,Bias adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0. " RC32M_ENABLE ,Enables the 32MHz RC oscillator" "0,1" group.long 0x48++0x3 line.long 0x00 "CLK_RCX_REG,RCX-oscillator control register" bitfld.long 0x00 8.--11. " RCX_BIAS ,LDO bias current._0x0: minimum_0xF: maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " RCX_C0 ,Add unit capacitance to RC-time delay" "0,1" bitfld.long 0x00 2.--6. " RCX_CADJUST ,Adjust capacitance part of RC-time delay._0x00: minimum capacitance_0x1F: maximum capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 1. " RCX_RADJUST ,Adjust resistance part of RC-time delay. Lower resistance increases power consumption._0x0: maximum resistance_0x1: minimum resistance" "0,1" bitfld.long 0x00 0. " RCX_ENABLE ,Enable the RCX oscillator" "0,1" group.long 0x4C++0x3 line.long 0x00 "CLK_RTCDIV_REG,Divisor for RTC 100Hz clock" bitfld.long 0x00 21. " RTC_RESET_REQ ,Reset request for the RTC module" "0,1" bitfld.long 0x00 20. " RTC_DIV_ENABLE ,Enable for the 100 Hz generation for the RTC block" "0,1" bitfld.long 0x00 19. " RTC_DIV_DENOM ,Selects the denominator for the fractional division:_0b0: 1000_0b1: 1024" "0,1" textline " " hexmask.long.word 0x00 10.--18. 1. " RTC_DIV_INT ,Integer divisor part for RTC 100Hz generation" hexmask.long.word 0x00 0.--9. 1. " RTC_DIV_FRAC ,Fractional divisor part for RTC 100Hz generation._if RTC_DIV_DENOM=1, out of 1024 cycles will divide by , the rest is _If RTC_DIV_DENOM=0, out of 1000 cycles will divide by , the rest is " group.long 0x1C++0x3 line.long 0x00 "CLK_SWITCH2XTAL_REG,Switches clock from RC32M to XTAL32M" bitfld.long 0x00 0. " SWITCH2XTAL ,When writing to this register, the clock switch will happen from RC32M to XTAL32M. If any other clock is selected than RC32M, the selection is discarded" "0,1" group.long 0x18++0x3 line.long 0x00 "CLK_TMR_REG,Clock control for the timers" bitfld.long 0x00 2. " TMR2_PWM_AON_MODE ,Maps Timer2_pwm onto P1_06._This state is preserved during deep sleep, to allow PWM output on the pad during deep sleep" "0,1" bitfld.long 0x00 1. " TMR_PWM_AON_MODE ,Maps Timer1_pwm onto P1_01_This state is preserved during deep sleep, to allow PWM output on the pad during deep sleep" "0,1" bitfld.long 0x00 0. " WAKEUPCT_ENABLE ,Enables the clock" "0,1" group.long 0x40++0x3 line.long 0x00 "CLK_XTAL32K_REG,32 kHz XTAL oscillator register" bitfld.long 0x00 9. " XTAL32K_DISABLE_OUTPUT ,Disables output buffer, test only" "0,1" bitfld.long 0x00 8. " XTAL32K_XTAL1_BIAS_DISABLE ,Disables the 1nA bias current through the pull down diode" "0,1" bitfld.long 0x00 7. " XTAL32K_DISABLE_AMPREG ,Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator._Set this bit to '1' for an external clock to XTAL32Kp_Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km" "0,1" textline " " bitfld.long 0x00 3.--6. " XTAL32K_CUR ,Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " XTAL32K_RBIAS ,Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog" "0,1,2,3" bitfld.long 0x00 0. " XTAL32K_ENABLE ,Enables the 32kHz XTAL oscillator" "0,1" group.long 0xD4++0x3 line.long 0x00 "DISCHARGE_RAIL_REG,Immediate rail resetting. There is no LDO/DCDC gating" bitfld.long 0x00 2. " RESET_V18P ,1: Enables immediate discharging of the V18P rail. Note that the source is not disabled._0: disable immediate discharging of the V18P rail._This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18P" "0,1" bitfld.long 0x00 1. " RESET_V18 ,1: Enables immediate discharging of the V18 rail. Note that the source is not disabled._0: disable immediate discharging of the V18 rail._This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18" "0,1" bitfld.long 0x00 0. " RESET_V14 ,1: Enables immediate discharging of the V14 rail. Note that the source is not disabled._0: disable immediate discharging of the V14 rail._This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V14" "0,1" group.long 0xB8++0x3 line.long 0x00 "HW_CONFIG_REG,Hardware configuration register" bitfld.long 0x00 11.--12. " REDUCE_RAM_SIZE ,0x0: no RAM reduction_0x1: remove the last 128 kByte, moving MTB down to RAM6_0x2, 0x3: remove the last 256 kByte, moving MTB down to RAM4" "0,1,2,3" bitfld.long 0x00 10. " DISABLE_MOTORC ,Permanently disable Motor Controller_Permanently disable the controller enable bit" "0,1" bitfld.long 0x00 9. " DISABLE_QSPIRAM ,Permanently disable QSPI RAM clocks" "0,1" textline " " bitfld.long 0x00 8. " DISABLE_PWM ,Permanently disable PWM clocks" "0,1" bitfld.long 0x00 7. " DISABLE_LRA ,Permanently disable LRA/ERM clocks_Permanently disable LRA/ERM clocks" "0,1" bitfld.long 0x00 6. " DISABLE_APU ,Permanently disable APU clocks_Permanently disable APU blocks" "0,1" textline " " bitfld.long 0x00 5. " DISABLE_USB ,Permanently disable the clock of the USB Controller._Permanently disable the charger detect circuit." "0,1" bitfld.long 0x00 4. " DISABLE_UART3 ,Permanently disable UART3 clock" "0,1" bitfld.long 0x00 3. " DISABLE_SDADC ,Permanently disable ADC2 LDO._Permanently disable ADC2 clock" "0,1" textline " " bitfld.long 0x00 2. " DISABLE_GPADC ,Permanently disable ADC LDO._Permanently disable ADC clock." "0,1" bitfld.long 0x00 1. " DISABLE_CHARGER ,Permanently disable the Charger digital FSM. Keep Analog loop in Hold" "0,1" bitfld.long 0x00 0. " DISABLE_LCD ,Permanently disable LCD Controller clock_Permanently disable LCD Controller block" "0,1" group.long 0xC4++0x3 line.long 0x00 "LDOS_DISABLE_REG,Force off all LDOs" bitfld.long 0x00 0. " LDOS_DISABLE ,If set to '1', the following LDOS are disabled:_LDO_SUPPLY_VBAT (V33)_LDO_SUPPLY_VBUS (V33)_LDO_VBAT_RET (V33)_LDO_1V8_PA_LDO_1V8_PA_RET_LDO_1V8_FLASH_LDO_1V8_FLASH_RET_LDO_CORE (VDD1V2)" "0,1" group.long 0xA0++0x3 line.long 0x00 "LDO_VDDD_HIGH_CTRL_REG,LDO control register" bitfld.long 0x00 3. " LDO_VDDD_HIGH_LOW_ZOUT_DISABLE ,Disables the low Zout switch. The low Zout switch pulls the output of the LDO to ground. When 0, the output of the LDO is pulled to ground when the LDO is disabled. When 1, the output of the LDO remains floating when the LDO is disabled" "0,1" bitfld.long 0x00 2. " LDO_VDDD_HIGH_STATIC_LOAD_ENABLE ,Enables a static load of approx. 10 uA at the output of the LDO VDDD_HIGH" "0,1" bitfld.long 0x00 1. " LDO_VDDD_HIGH_ENABLE ,0: LDO VDDD_HIGH off,_1: LDO VDDD_HIGH on" "0,1" textline " " bitfld.long 0x00 0. " LDO_VDDD_HIGH_VREF_HOLD ,0: Indicates that the reference input is tracked,_1: Indicates that the reference input is sampled" "0,1" group.long 0x70++0x3 line.long 0x00 "P0_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long 0x00 0.--31. 1. " P0_LATCH_EN ,Direct write to the specific pad_latch_enable signal" group.long 0x78++0x3 line.long 0x00 "P0_RESET_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long 0x00 0.--31. 1. " P0_RESET_LATCH_EN ,Direct Reset of the marked bits. Reading returns 0x0" group.long 0x74++0x3 line.long 0x00 "P0_SET_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long 0x00 0.--31. 1. " P0_SET_LATCH_EN ,Direct Set of the marked bits. Reading returns 0x0" group.long 0x7C++0x3 line.long 0x00 "P1_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long.tbyte 0x00 0.--22. 1. " P1_LATCH_EN ,Direct write to the specific pad_latch_enable signal" group.long 0x84++0x3 line.long 0x00 "P1_RESET_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long.tbyte 0x00 0.--22. 1. " P1_RESET_LATCH_EN ,Direct Reset of the marked bits. Reading returns 0x0" group.long 0x80++0x3 line.long 0x00 "P1_SET_PAD_LATCH_REG,Control the state retention of the GPIO ports" hexmask.long.tbyte 0x00 0.--22. 1. " P1_SET_LATCH_EN ,Direct Set of the marked bits. Reading returns 0x0" group.long 0x20++0x3 line.long 0x00 "PMU_CTRL_REG,Power Management Unit control register" bitfld.long 0x00 8. " ENABLE_CLKLESS ,Selects the clockless sleep mode. Wakeup is done asynchronously._When set to '1', the lp_clk is stopped during deep sleep, until a wakeup event (not debounced) is detected by the WAKUPCT block._When set to '0', the lp_clk continues running, so the MAC counters keep on running._This mode cannot be combined with regulated sleep, so keep SLEEP_TIMER=0 when using ENABLE_CLKLESS" "0,1" bitfld.long 0x00 7. " RETAIN_CACHE ,Selects the retainability of the cache block during deep sleep._'1' is retainable, '0' is power gated" "0,1" bitfld.long 0x00 6. " SYS_SLEEP ,Put the System powerdomain (PD_SYS) in powerdown._If this bit is '1', and there is no pending IRQ in the PDC for the M33, the PD_SYS will be switched off._Wakeup should be handled by the PDC" "0,1" textline " " bitfld.long 0x00 5. " RESET_ON_WAKEUP ,Perform a Hardware Reset after waking up. Booter will be started." "0,1" bitfld.long 0x00 4. " MAP_BANDGAP_EN ,Maps the bandgap_enable to P06" "0,1" bitfld.long 0x00 3. " COM_SLEEP ,Put the Communications powerdomain (PD_COM) in powerdown" "0,1" textline " " bitfld.long 0x00 2. " TIM_SLEEP ,Put the Timers Powerdomain (PD_TIM) in powerdown" "0,1" bitfld.long 0x00 1. " RADIO_SLEEP ,Put the digital part of the radio, including CMAC (PD_RAD) in powerdown" "0,1" bitfld.long 0x00 0. " PERIPH_SLEEP ,Put the peripherals power domain (PD_PER) in powerdown" "0,1" group.long 0xF4++0x3 line.long 0x00 "PMU_SLEEP_REG," bitfld.long 0x00 18. " CLAMP_VDD_WKUP_MAX ,Forces the VDD clamp voltage to its maximum value when waking up from sleep" "0,1" bitfld.long 0x00 17. " ULTRA_FAST_WAKEUP ,Allows the core to start running on the RC32M while the PMU is still waiting for supplies to settle to the final value. Only use in combination with FAST_WAKEUP and 0.9 V on VDD during sleep" "0,1" bitfld.long 0x00 16. " FAST_WAKEUP ,Speeds up the wakeup process by enabling all LDOs simultaneously instead of in staggered order. Only use if all voltages have been retained during sleep" "0,1" textline " " bitfld.long 0x00 12.--15. " BOD_SLEEP_INTERVAL ,This is a value defining the interval every which Brown Out Detection is activated to check on the power rails voltage. The value represents BG_REFRESH_INTERVALs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " BG_REFRESH_INTERVAL ,This is a value defining the interval every which the Bandgap will be activated for refresh. The value represents ticks of lp_clk/64 e.g. 30,5 us * 64 = 1,9 ms" group.long 0xF8++0x3 line.long 0x00 "PMU_TRIM_REG," bitfld.long 0x00 12.--15. " LDO_1V8_TRIM ,Trim setting for LDO_1V8_Unsigned binary notation, trim range ?10 %" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " LDO_1V8P_TRIM ,Trim setting for LDO_1V8P_Unsigned binary notation, trim range ?10 %" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " LDO_SUPPLY_VBAT_TRIM ,Trim setting for LDO_SUPPLY_VBUS_Sign-magnitude notation, trim range ?10 %" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " LDO_SUPPLY_VBUS_TRIM ,Trim setting for LDO_SUPPLY_VBAT_Sign-magnitude notation, trim range ?10 %" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x3 line.long 0x00 "POR_PIN_REG,Selects a GPIO pin for POR generation" bitfld.long 0x00 7. " POR_PIN_POLARITY ,0: Active Low_1: Active High_Note: This applies only for the GPIO pin. Reset pad is always active High" "0,1" bitfld.long 0x00 0.--5. " POR_PIN_SELECT ,0x00: P0_00_..._0x1f: P0_31_0x20: P1_00_..._0x36: P1_22_0x37 to 0x3E: reserved_0x3F: POR generation disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x9C++0x3 line.long 0x00 "POR_TIMER_REG,Time for POR to happen" hexmask.long.byte 0x00 0.--6. 1. " POR_TIME ,Time for the POReset to happen._Formula:_Time = POR_TIME x 4096 x RC32 clock period_Default value: ~3 seconds" group.long 0x94++0x3 line.long 0x00 "POR_VBAT_CTRL_REG,Controls the POR on VBAT" bitfld.long 0x00 13. " POR_VBAT_MASK_N ,Enables propagation of the generated POR" "0,1" bitfld.long 0x00 12. " POR_VBAT_ENABLE ,Enables generation of the POR" "0,1" bitfld.long 0x00 8.--11. " POR_VBAT_HYST_LOW ,Controls hysteresis of POR. 20mV per step. Must be set to 0x2 when thres_ctrl_low is set to 0xf" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " POR_VBAT_THRES_HIGH ,High-side (PTAT) threshold contribution:_Level --> Threshold_0x0 --> 1.25V_0x1 --> 1.27V_0x2 --> 1.29V_0x3 --> 1.31V_0x4 --> 1.44V_0x5 --> 1.49V_0x6 --> 1.53V_0x7 --> 1.58V_0x8 --> 1.63V_0x9 --> 1.68V_0xA --> 1.73V_0xB --> 1.78V0xC --> 1.83V0xD --> 1.87V0xE --> 1.92V_0xF --> 1.97V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " POR_VBAT_THRES_LOW ,Low-side (CTAT) threshold contribution_Level --> Threshold_0xC --> 1.25V_0xC --> 1.27V_0xC --> 1.29V_0xC --> 1.31V_0x0 --> 1.44V_0x1 --> 1.49V_0x2 --> 1.53V_0x3 --> 1.58V_0x4 --> 1.63V_0x5 --> 1.68V_0x6 --> 1.73V_0x7 --> 1.78V_0x8 --> 1.83V_0x9 --> 1.87V_0xA --> 1.92V_0xB --> 1.97V_0xF --> 1.63V; use only with POR_VBAT_THRES_LOW=0x6 and POR_VBAT_THRES_HYST=0x2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF0++0x3 line.long 0x00 "POWER_CTRL_REG," bitfld.long 0x00 29.--31. " VDD_SLEEP_LEVEL ,Level setting for VDD rail when using sleep LDO_0x0: 0.75 V_0x1: 0.80 V_0x2: 0.85 V_0x3: 0.90 V_0x4: 0.95 V_0x5: 1.00 V_0x6: N.A._0x7: N.A" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " VDD_CLAMP_LEVEL ,Level setting for VDD when using clamp_Typical output voltages (not regulated):_0x0: 1037 mV_0x1: 1005 mV_0x2: 978 mV_0x3: 946 mV_0x4: 1120 mV_0x5: 1089 mV_0x6: 1058 mV_0x7: 1030 mV_0x8: 952 mV_0x9: 918 mV_0xA: 889 mV_0xB: 861 mV_0xC: 862 mV_0xD: 828 mV_0xE: 798 mV_0xF: 706 mV ( changed to be lower than ldo_core_ret level)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " CLAMP_3V0_VBAT_ENABLE ,Enables (1) or disables (0) clamp that can supply V30 from VBAT" "0,1" textline " " bitfld.long 0x00 23. " V18_LEVEL ,Level setting for V18 rail_0x0: 1.2 V_0x1: 1.8 V" "0,1" bitfld.long 0x00 20.--22. " V14_LEVEL ,Level setting for V14 rail_0x0: 1.20 V_0x1: 1.25 V_0x2: 1.30 V_0x3: 1.35 V_0x4: 1.40 V_0x5: 1.45 V_0x6: 1.50 V_0x7: 1.55 V" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " V30_LEVEL ,Level setting for V30 rail_0x0: 3.0 V_0x1: 3.45 V_0x2: 3.3 V_0x3: 3.3 V" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " VDD_LEVEL ,Level setting for VDD rail_0x0: 0.9 V_0x1: 1.0 V_0x2: 1.1 V_0x3: 1.2 V" "0,1,2,3" bitfld.long 0x00 15. " LDO_3V0_REF ,Selects reference source for V30 LDOs_0x0: VDD rail_0x1: Bandgap output" "0,1" bitfld.long 0x00 14. " LDO_CORE_RET_ENABLE_SLEEP ,Enables (1) or disables (0) LDO_CORE_RET in sleep mode" "0,1" textline " " bitfld.long 0x00 13. " LDO_CORE_RET_ENABLE_ACTIVE ,Enables (1) or disables (0) LDO_CORE_RET in active mode" "0,1" bitfld.long 0x00 12. " LDO_CORE_ENABLE ,Enables (1) or disables (0) LDO_CORE" "0,1" bitfld.long 0x00 11. " LDO_3V0_RET_ENABLE_SLEEP ,Enables (1) or disables (0) LDO_3V0_RET in sleep mode" "0,1" textline " " bitfld.long 0x00 10. " LDO_3V0_RET_ENABLE_ACTIVE ,Enables (1) or disables (0) LDO_3V0_RET in active mode" "0,1" bitfld.long 0x00 8.--9. " LDO_3V0_MODE ,Controls for LDO_3V0_0x0: Disabled_0x1: LDO_VBAT enabled_0x2: LDO_VBUS enabled_0x3: Automatic selection of LDO_VBAT or LDO_VBUS" "0,1,2,3" bitfld.long 0x00 7. " LDO_RADIO_ENABLE ,Enables (1) or disables (0) LDO_RADIO" "0,1" textline " " bitfld.long 0x00 6. " LDO_1V8_RET_ENABLE_SLEEP ,Enables (1) or disables (0) LDO_1V8_RET in sleep mode" "0,1" bitfld.long 0x00 5. " LDO_1V8_RET_ENABLE_ACTIVE ,Enables (1) or disables (0) LDO_1V8_RET in active mode" "0,1" bitfld.long 0x00 4. " LDO_1V8_ENABLE ,Enables (1) or disables (0) LDO_1V8" "0,1" textline " " bitfld.long 0x00 3. " SW_1V8F_ENABLE_FORCE ,Forces switch between V18P and V18F rails on" "0,1" bitfld.long 0x00 2. " LDO_1V8P_RET_ENABLE_SLEEP ,Enables (1) or disables (0) LDO_1V8P_RET in sleep mode" "0,1" bitfld.long 0x00 1. " LDO_1V8P_RET_ENABLE_ACTIVE ,Enables (1) or disables (0) LDO_1V8P_RET in active mode" "0,1" textline " " bitfld.long 0x00 0. " LDO_1V8P_ENABLE ,Enables (1) or disables (0) LDO_1V8P" "0,1" group.long 0xC0++0x3 line.long 0x00 "RAM_PWR_CTRL_REG,Control power state of System RAMS" bitfld.long 0x00 14.--15. " RAM8_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" bitfld.long 0x00 12.--13. " RAM7_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" bitfld.long 0x00 10.--11. " RAM6_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " RAM5_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" bitfld.long 0x00 6.--7. " RAM4_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" bitfld.long 0x00 4.--5. " RAM3_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " RAM2_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3" bitfld.long 0x00 0.--1. " RAM1_PWR_CTRL ,Power state control of the individual RAMs._When PD_MEM_IS_UP:_0x0: Normal operation_0x1: Normal operation_0x2: Retained (no access possible)_0x3: Off (memory content corrupted)_When PD_MEM_IS_DOWN:_0x0: Retained_0x1: Off (memory content corrupted)_0x2: Retained_0x3: Off (memory content corrupted)" "0,1,2,3" group.long 0xBC++0x3 line.long 0x00 "RESET_STAT_REG,Reset status register" bitfld.long 0x00 5. " CMAC_WDOGRESET_STAT ,Indicates that a CMAC-Watchdog timeout has happened. Note that it is also set when a POReset has happened" "0,1" bitfld.long 0x00 4. " SWD_HWRESET_STAT ,Indicates that a write to SWD_RESET_REG has happened. Note that it is also set when a POReset has happened" "0,1" bitfld.long 0x00 3. " WDOGRESET_STAT ,Indicates that a Watchdog timeout has happened. Note that it is also set when a POReset has happened" "0,1" textline " " bitfld.long 0x00 2. " SWRESET_STAT ,Indicates that a SW Reset has happened" "0,1" bitfld.long 0x00 1. " HWRESET_STAT ,Indicates that a HW Reset has happened" "0,1" bitfld.long 0x00 0. " PORESET_STAT ,Indicates that a PowerOn Reset has happened._All bitfields of RESET_STAT_REG should be read (in order to check the source of reset) and then cleared to '0', allowing thus the HW to automatically set to '1' the proper bitfields during the next reset event" "0,1" group.long 0xCC++0x3 line.long 0x00 "SECURE_BOOT_REG,Controls secure booting" bitfld.long 0x00 7. " PROT_QSPI_KEY_READ ,This bit will permanently disable CPU read capability at OTP offset 0x00000B00 and for the complete segment" "0,1" bitfld.long 0x00 6. " PROT_QSPI_KEY_WRITE ,This bit will permanently disable ANY write capability at OTP offset 0x00000B00 and for the complete segment" "0,1" bitfld.long 0x00 5. " PROT_AES_KEY_READ ,This bit will permanently disable CPU read capability at OTP offset 0x00000A00 and for the complete segment" "0,1" textline " " bitfld.long 0x00 4. " PROT_AES_KEY_WRITE ,This bit will permanently disable ANY write capability at OTP offset 0x00000A00 and for the complete segment" "0,1" bitfld.long 0x00 3. " PROT_SIG_KEY_WRITE ,This bit will permanently disable ANY write capability at OTP offset 0x000008C0 and for the complete segment" "0,1" bitfld.long 0x00 2. " FORCE_CMAC_DEBUGGER_OFF ,This bit will permanently disable the CMAC debugger" "0,1" textline " " bitfld.long 0x00 1. " FORCE_DEBUGGER_OFF ,Follows the respective OTP flag value. Its value is updated by the BootROM code._1: The system debugger SWD is totally disabled._0: The system debugger is enabled with DEBUGGER_ENABLE" "0,1" bitfld.long 0x00 0. " SECURE_BOOT ,Follows the respective OTP flag value. Its value is updated by the BootROM code._1: system is a secure system supporting secure boot_0: system is not supporting secure boot" "0,1" group.long 0xFC++0x3 line.long 0x00 "STARTUP_STATUS_REG," rbitfld.long 0x00 16.--19. " WUP_FAIL_STATE ,Shows state of startup FSM at the moment force_running was asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " WUP_LDO_RADIO_OK ,LDO_RADIO_OK value at time of LDO_CORE_RADIO state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 14. " WUP_BANDGAP_OK ,BANDGAP_OK value at time of RAILS_OK state_Only set if force_running is asserted" "0,1" textline " " rbitfld.long 0x00 13. " WUP_COMP_VDD_OK ,COMP_VDD_OK value at time of LDO_CORE_RADIO state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 12. " WUP_COMP_VBAT_OK ,COMP_VBAT_LOW value at time of RAILS_OK state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 11. " WUP_COMP_VBUS_HIGH ,COMP_VBUS_HIGH value at time of RAILS_OK state_Only set if force_running is asserted" "0,1" textline " " rbitfld.long 0x00 10. " WUP_COMP_VBUS_LOW ,COMP_VBUS_LOW value at time of RAILS_OK state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 9. " WUP_VBUS_AVAILABLE ,VBUS_AVAILABLE value at time of LDO_3V0 state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 8. " WUP_LDO_CORE_OK ,LDO_CORE_OK value at time of LDO_CORE_RADIO state_Only set if force_running is asserted" "0,1" textline " " rbitfld.long 0x00 7. " WUP_LDO_1V8_OK ,LDO_1V8_OK value at time of LDO_1V8 state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 6. " WUP_LDO_1V8P_OK ,LDO_1V8P_OK value at time of LDO_1V8P state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 5. " WUP_LDO_3V0_VBUS_OK ,LDO_3V0_VBUS_OK value at time of LDO_3V0 state_Only set if force_running is asserted" "0,1" textline " " rbitfld.long 0x00 4. " WUP_LDO_3V0_VBAT_OK ,LDO_3V0_VBAT_OK value at time of LDO_3V0 state_Only set if force_running is asserted" "0,1" rbitfld.long 0x00 3. " WUP_RAILS_OK_TIMEOUT ,High if RAILS_OK state timed out, set when FSM reaches running state" "0,1" rbitfld.long 0x00 2. " WUP_LDO_1V8_TIMEOUT ,High if LDO_1V8 state timed out, set when FSM reaches running state" "0,1" textline " " rbitfld.long 0x00 1. " WUP_LDO_1V8P_TIMEOUT ,High if LDO_1V8P state timed out, set when FSM reaches running state" "0,1" rbitfld.long 0x00 0. " WUP_LDO_3V0_TIMEOUT ,High if LDO_3V0 state timed out, set when FSM reaches running state" "0,1" group.long 0x24++0x3 line.long 0x00 "SYS_CTRL_REG,System Control register" bitfld.long 0x00 15. " SW_RESET ,Writing a '1' to this bit will generate a SW_RESET" "0,1" bitfld.long 0x00 10. " CACHERAM_MUX ,Controls accessiblity of Cache RAM:_0: the cache controller is bypassed, the cacheRAM is visible in the memory space next to the DataRAMs_1: the cache controller is enabled, the cacheRAM is not visible anymore in the memory space" "0,1" bitfld.long 0x00 9. " TIMEOUT_DISABLE ,Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from_ANA_STATUS_REG" "0,1" textline " " bitfld.long 0x00 8. " DRA_OFF ,Disables the DRA mode, and released the ARM reset" "0,1" bitfld.long 0x00 7. " DEBUGGER_ENABLE ,Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports." "0,1" bitfld.long 0x00 6. " CMAC_DEBUGGER_ENABLE ,Enable the CMAC debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports." "0,1" textline " " bitfld.long 0x00 4. " QSPI_INIT ,Enables QSPI initialization after wakeup" "0,1" bitfld.long 0x00 3. " REMAP_INTVECT ,0: normal operation_1: If ARM is in address range 0 to 0x1FF then the address is remapped to SYS-RAM 0x07FC.0000 to 0x07FC.01FF. This allows to put the interrupt vector table to be placed in RAM while executing from QSPI" "0,1" bitfld.long 0x00 0.--2. " REMAP_ADR0 ,Controls which memory is located at address 0x0000 for execution._0x0: ROM_0x1: OTP un-cached_0x2: QSPI FLASH cached_0x3: RAMS un-cached_0x4: QSPI FLASH un-cached (for verification only)_0x5: Reserved_0x6: Cache Data RAM un-cached (CACHERAM_MUX=0, for testing purposes only)_Note 1: DWord (64 bits) access is not supported by the Cache Data RAM interface in mirrored mode (only 32, 16 and 8 bits)._Note 2: DMA access is not supported by the Cache Data RAM interface when REMAP_ADR0=0x6" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "SYS_STAT_REG,System status register" rbitfld.long 0x00 13. " POWER_IS_UP ,Indicates that the Startup statemachine is finished, and all power regulation is in order._In UltraFastWakeup mode, the SW needs to wait for this signal before starting any heavy traffic" "0,1" rbitfld.long 0x00 12. " DBG_IS_ACTIVE ,Indicates that a debugger is attached" "0,1" rbitfld.long 0x00 11. " COM_IS_UP ,Indicates that PD_COM is functional" "0,1" textline " " rbitfld.long 0x00 10. " COM_IS_DOWN ,Indicates that PD_COM is in power down" "0,1" rbitfld.long 0x00 9. " TIM_IS_UP ,Indicates that PD_TIM is functional" "0,1" rbitfld.long 0x00 8. " TIM_IS_DOWN ,Indicates that PD_TIM is in power down" "0,1" textline " " rbitfld.long 0x00 7. " MEM_IS_UP ,Indicates that PD_MEM is functional" "0,1" rbitfld.long 0x00 6. " MEM_IS_DOWN ,Indicates that PD_MEM is power down" "0,1" rbitfld.long 0x00 5. " SYS_IS_UP ,Indicates that PD_PER is functional" "0,1" textline " " rbitfld.long 0x00 4. " SYS_IS_DOWN ,Indicates that PD_PER is in power down" "0,1" rbitfld.long 0x00 3. " PER_IS_UP ,Indicates that PD_PER is functional" "0,1" rbitfld.long 0x00 2. " PER_IS_DOWN ,Indicates that PD_PER is in power down" "0,1" textline " " rbitfld.long 0x00 1. " RAD_IS_UP ,Indicates that PD_RAD is functional" "0,1" rbitfld.long 0x00 0. " RAD_IS_DOWN ,Indicates that PD_RAD is in power down" "0,1" group.long 0x58++0x3 line.long 0x00 "VBUS_IRQ_CLEAR_REG,Clear pending IRQ register" hexmask.long.word 0x00 0.--15. 1. " VBUS_IRQ_CLEAR ,Writing any value to this register will reset the VBUS_IRQ line" group.long 0x54++0x3 line.long 0x00 "VBUS_IRQ_MASK_REG,IRQ masking" bitfld.long 0x00 1. " VBUS_IRQ_EN_RISE ,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold" "0,1" bitfld.long 0x00 0. " VBUS_IRQ_EN_FALL ,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold" "0,1" width 0x0B tree.end tree "CRG_XTAL" base ad:0x50010000 width 20. group.long 0x0++0x3 line.long 0x00 "CLK_FREQ_TRIM_REG,Xtal frequency trimming register" hexmask.long.word 0x00 20.--29. 1. " XTAL32M_START ,Xtal frequency trimming register - START phase of startup_0x2BF = lowest frequency (high load capacitance)_0x000 = highest frequency (low load capacitance)_Cload = 2.25p + 6.2p * XTAL32M_TRIM/0x2BF" hexmask.long.word 0x00 10.--19. 1. " XTAL32M_RAMP ,Xtal frequency trimming register - RAMP phase of startup._0x2BF = lowest frequency (high load capacitance)_0x000 = highest frequency (low load capacitance)_Cload = 2.25p + 6.2p * XTAL32M_TRIM/0x2BF" hexmask.long.word 0x00 0.--9. 1. " XTAL32M_TRIM ,Xtal frequency trimming register._0x2BF = lowest frequency (high load capacitance)_0x000 = highest frequency (low load capacitance)_Cload = 2.25p + 6.2p * XTAL32M_TRIM/0x2BF" group.long 0x80++0x3 line.long 0x00 "PLL96M_CTRL1_REG,System PLL control register 2" bitfld.long 0x00 12. " PLL96M_SKIP_LIMIT_SEARCH ,Skip frequency locking at start-up._Default: 1" "0,1" bitfld.long 0x00 11. " PLL96M_SAVE_POWER ,Save power by stopping internal clocks and counters after the PLL has locked._Default :1" "0,1" bitfld.long 0x00 10. " PLL96M_OUTPUT_STREAMING ,Enable streaming of PLL status data for debugging._Default: 0" "0,1" textline " " bitfld.long 0x00 8.--9. " PLL96M_DELTA_COUNT ,Delta-delay during the limit-search phase_Default: 2" "0,1,2,3" bitfld.long 0x00 7. " PLL96M_PANIC_EN ,Allow panic mode (should not be needed)._Default: 0" "0,1" bitfld.long 0x00 6. " PLL96M_DELTA_SEARCH_MODE ,0: Linear delta search (Default)_1: Exponential delta search" "0,1" textline " " bitfld.long 0x00 4.--5. " PLL96M_DELTA_SEARCH ,Delta-delay steps during lock search phase._Default: 1" "0,1,2,3" bitfld.long 0x00 0. " PLL96M_ENABLE ,0: Power down_1: PLL on" "0,1" group.long 0x84++0x3 line.long 0x00 "PLL96M_CTRL2_REG,System PLL control register 1" hexmask.long.word 0x00 7.--15. 1. " PLL96M_INIT_DELAY ,Initial delay of the DCO timer._0: minimum_223: default_447: maximum" bitfld.long 0x00 1.--6. " PLL96M_INIT_DUTYCYCLE ,Initial duty-cycle adjustment value._0: 42.5%_32: 50%_63: 57.5%)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " PLL96M_EXTERN_CMD ,0: Normal operation, 1: Override DCO delay with PL96M_INIT_DELAY" "0,1" group.long 0x88++0x3 line.long 0x00 "PLL96M_CTRL3_REG,System PLL control register 3" bitfld.long 0x00 15. " PLL96M_TST_CLK_INV ,Invert test data clock polarity._Default: 0" "0,1" bitfld.long 0x00 12.--13. " PLL96M_CDEL1 ,Phase-detector digital delay correction._Default: 3" "0,1,2,3" bitfld.long 0x00 8.--11. " PLL96M_BIAS ,Bias adjustment._Default: 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " PLL96M_PHD_CD2 ,Phase-detector delay coefficient 2._Default: 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLL96M_PHD_CD1 ,Phase-detector delay coefficient 1._Default: 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C++0x3 line.long 0x00 "PLL96M_STATUS1_REG,System PLL status register 1" rbitfld.long 0x00 26. " PLL96M_OK ,1: The PLL is producing a valid 96MHz output clock" "0,1" rbitfld.long 0x00 25. " PLL96M_ERROR_LOSAT ,1: PLL out-of-range: low saturation error" "0,1" rbitfld.long 0x00 24. " PLL96M_ERROR_HISAT ,1: PLL out-of-range: high saturation error" "0,1" textline " " rbitfld.long 0x00 18.--23. " PLL96M_FINE_CNT ,Counts subsequent cycles that the controller is in fine-adjust algorithm (high number predicts low jitter)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 17. " PLL96M_TRIGGER ,Trigger output that can restart the RC oscillator" "0,1" hexmask.long.word 0x00 8.--16. 1. " PLL96M_EFF_DELAY ,Effective delay value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PLL96M_DELTA_DELAY ,Delta delay correction value" group.long 0x90++0x3 line.long 0x00 "PLL96M_STATUS2_REG,System PLL status register 2" rbitfld.long 0x00 5.--10. " PLL96M_CNT96 ,Number of internal oscillator pulses within 4 periods of the reference clock (should be 12)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0.--4. " PLL96M_PHD_OUT ,Phase-detector output vector._0x00: UP3 - Clock is too slow_0x01: UP2_0x03: UP1_0x07: DN1_0x0F: DN2_0x1F: DN3 - Clock is too fast" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x60++0x3 line.long 0x00 "PLL_SYS_CTRL1_REG,System PLL control register 1" bitfld.long 0x00 14. " PLL_SEL_MIN_CUR_INT ,0: VCO current read from min_current <5:0>,_1: VCO current is internally determined with a calibration algoritm" "0,1" bitfld.long 0x00 12.--13. " PLL_DEL_SEL ,PLL manual delay value for Phase Frequency Detector._0: 0.493_1: 0.814_2: 1.13 ns <- default_3: 1.44 ns" "0,1,2,3" bitfld.long 0x00 11. " PLL_PRE_DIV ,PLL input divider (1: Indicates divide by 2)" "0,1" textline " " hexmask.long.byte 0x00 4.--10. 1. " PLL_N_DIV ,PLL loop divider N (x means divide by x, 0 means divide by 1)" bitfld.long 0x00 3. " LDO_PLL_VREF_HOLD ,0: Indicates that the reference input is tracked,_1: Indicates that the reference input is sampled" "0,1" bitfld.long 0x00 2. " LDO_PLL_ENABLE ,0: LDO PLL off,_1: LDO PLL on" "0,1" textline " " bitfld.long 0x00 1. " PLL_EN ,0: Power down_1: PLL on" "0,1" group.long 0x64++0x3 line.long 0x00 "PLL_SYS_CTRL2_REG,System PLL control register 2" bitfld.long 0x00 15. " PLL_RECALIB ,Recalibrate" "0,1" bitfld.long 0x00 10.--14. " PLL_START_DEL ,Programmable delay time for the loop filter voltage preset value. After PLL_EN is set, the loopfilter precharge resistors are disabled after this delay time. One LSB is 48 ns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PLL_ICP_SEL ,PLL charge pump current select_One LSB is 5uA." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68++0x3 line.long 0x00 "PLL_SYS_CTRL3_REG,System PLL control register 3" bitfld.long 0x00 13.--15. " PLL_LOCK_DET_RES_CNT ,Lock measurement time in clock cycle of xx usec. After this period PLL_LOCK_FINE is calculated based on the difference of the M and N counted pulses in that period. If PLL_LOCK_FINE is still 0, the lock state machine restarts until PLL_LOCK_FINE gets 1_0: usec_7: usec" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10. " PLL_SEL_N_DIV_TEST ,Select test mode for loop divider N._Maps PLL_N_DIV input on pins and divider output on pin " "0,1" bitfld.long 0x00 9. " PLL_CHANGE ,0: normal value_1: reverse charge pump up/down signals" "0,1" textline " " bitfld.long 0x00 8. " PLL_OPEN_LOOP ,1: set to open loop to termine max frequency" "0,1" bitfld.long 0x00 7. " PLL_TEST_VCTR ,1: map loopfilter voltage on external pin " "0,1" bitfld.long 0x00 1.--6. " PLL_MIN_CURRENT ,VCO current trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0. " PLL_DIS_LOOPFILT ,1: disable PLL internal loop filter" "0,1" group.long 0x70++0x3 line.long 0x00 "PLL_SYS_STATUS_REG,System PLL status register" rbitfld.long 0x00 15. " LDO_PLL_OK ,1: Indicates that LDO PLL is in regulation" "0,1" rbitfld.long 0x00 11. " PLL_CALIBRATION_END ,Indicates that calibration has finished" "0,1" rbitfld.long 0x00 5.--10. " PLL_BEST_MIN_CUR ,Calibrated VCO current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 0. " PLL_LOCK_FINE ,1: PLL locked" "0,1" group.long 0x10++0x3 line.long 0x00 "TRIM_CTRL_REG,Control trimming of the XTAL32M" bitfld.long 0x00 8.--13. " XTAL_SETTLE_N ,Designates that the XTAL can be safely used as the CPU clock. When XTAL_CLK_CNT reases this value, the signal XTAL_SETTLE_READY will be set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--7. " XTAL_TRIM_SELECT ,Select which source controls the XTAL trimming_0b00: xtal counter. Starts XTAL32M_START_REG, after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG._0b01: xtal OK filter. Starts with XTAL32_START_REG, when xtal is ramping is changed to CLK_FREQ_TRIM_REG_0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG._0b11: xtal OK filter, 2 stage. Starts with XTAL32_START_REG switches to XTAL16M_RAMP_REG when sw1='1', and switches to CLK_FREQ_TRIM_REG when sw2='1'" "0,1,2,3" bitfld.long 0x00 0.--5. " XTAL_COUNT_N ,Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 32._0x01: 32_0x02: 64_0x3f:2016" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "XTAL32M_CTRL0_REG,Control register for XTAL32M" bitfld.long 0x00 31. " XTAL32M_VARICAP_CX_ENABLE ,Enables shunt-cap compensation capacitance (OSF BOOST)" "0,1" bitfld.long 0x00 30. " XTAL32M_DXTAL_SYSPLL_ENABLE ,Enables DXTAL for the system PLL" "0,1" bitfld.long 0x00 29. " XTAL32M_CORE_MAX_CURRENT ,Forces maximum current in output device" "0,1" textline " " bitfld.long 0x00 26.--28. " XTAL32M_SW_DELAY ,Set sw1 delay (sample output current comparator) and sw2 mask delay time._0x0: 128 us_0x1: 64 us_0x2: 32 us_0x3: 16 us_0x4: 8 us_0x5: 4 us_0x6: 2 us_0x7: 1 us" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25. " XTAL32M_CORE_AMPREG_SIG_SELECT ,1: Select xtal_n for amplitude control._0: Select xtal_p for amplitude control" "0,1" bitfld.long 0x00 22.--24. " XTAL32M_CORE_FREQ_TRIM_SW2_AMP ,Set threshold for amplitude control ok detection._0x0: Highest current delta_0x6: Lowest current delta_0x7: off" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 21. " XTAL32M_CORE_AMPL_CTRL_DISABLE ,Disable amplitude-control block" "0,1" bitfld.long 0x00 18.--20. " XTAL32M_CORE_AMPL_TRIM ,Core amplitude trim setting._0x0: min amplitude_..._..._0x5: max amplitude_0x6 & 0x7 are equal to 0x3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " XTAL32M_CORE_CUR_SET ,Core current trim setting._0x0: min current_..._0x3: default current_..._0x6 max amplitude_0x7 is equal to 0x3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14. " XTAL32M_CORE_GM_CURRENT ,Enables biassing of the main oscillator output device" "0,1" bitfld.long 0x00 13. " XTAL32M_RCOSC_SYNC_MODE_ENABLE ,Enable synchronization of the crystal startup" "0,1" bitfld.long 0x00 12. " XTAL32M_CORE_HOLD_AMPREG ,Put amplitude detector in HOLD mode" "0,1" textline " " bitfld.long 0x00 11. " XTAL32M_SPIKE_FLT_DISABLE ,Disable DXTAL spike filter" "0,1" bitfld.long 0x00 10. " XTAL32M_RFCLK_ENABLE ,If set, rfclk is allowed to be enabled" "0,1" bitfld.long 0x00 9. " XTAL32M_HOLD_AMPREG_RADIO_GATE ,Allow radio_enable to put amplitude detector in HOLD mode" "0,1" textline " " bitfld.long 0x00 8. " XTAL32M_DIFFBUF_BYPASS ,Bypass comparator to use external input" "0,1" bitfld.long 0x00 7. " XTAL32M_BIAS_SAH_RADIO_GATE ,Allow radio_enable to put the bias block in HOLD mode" "0,1" bitfld.long 0x00 6. " XTAL32M_BIAS_SAH_HOLD ,Put the bias block in HOLD mode" "0,1" textline " " bitfld.long 0x00 5. " XTAL32M_LDO_VREF_HOLD ,Put the LDO in HOLD mode" "0,1" bitfld.long 0x00 4. " XTAL32M_DCBLOCK_ENABLE ,Eable dcblock circuit" "0,1" bitfld.long 0x00 3. " XTAL32M_RCOSC_CALIBRATE ,Request an RC-oscillator calibration. If set, calibration will be started after xtal startup" "0,1" textline " " bitfld.long 0x00 2. " XTAL32M_DXTAL_ENABLE ,Enable DXTAL - signal is gated by state-machine. Bit should always be set" "0,1" bitfld.long 0x00 1. " XTAL32M_RCOSC_XTAL_DRIVE ,Enable drive of crystal by RCOSC, needed for fast startup" "0,1" bitfld.long 0x00 0. " XTAL32M_CXCOMP_ENABLE ,Enable the shunt-capacitance compensation amplifier circuit (OSF BOOST)" "0,1" group.long 0x34++0x3 line.long 0x00 "XTAL32M_CTRL1_REG,Control register for XTAL32M" bitfld.long 0x00 28.--30. " XTAL32M_STARTUP_TDISCHARGE ,Discharge time._0x0: disable_0x1: 8 us_0x2: 4 us_0x3: 2 us_0x4: 1 us_0x5: 1/2 us_0x6: 1/8 us_0x7: 1/32 us" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " XTAL32M_CORE_XTAL_DISCHARGE ,Software control mode: discharges the crystal" "0,1" bitfld.long 0x00 24.--26. " XTAL32M_STARTUP_TSETTLE ,Settle time._0x0: 16 us_0x1: 8 us_0x2: 4 us_0x3: 2 us_0x4: 1 us_0x5: 1/2 us_0x6: 1/4 us_0x7: 1/8 us" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 23. " XTAL32M_XTAL_ENABLE ,Enable xtal (startup) or enable xtal block (software control mode) - testing only, to enable xtal, use PDC" "0,1" hexmask.long.word 0x00 13.--22. 1. " XTAL32M_STARTUP_TDRIVE_LSB ,LSB part of the sequence drive time. From 0 to 32us with steps of 1/32us" bitfld.long 0x00 8.--12. " XTAL32M_DRIVE_CYCLES ,Number of sequences to drive at startup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--7. " XTAL32M_STARTUP_TDRIVE ,Drive time of the sequence._0x0: 32 us_0x1: 16 us_0x2: 8 us_0x3: 4 us_0x4: 2 us_0x5: 1 us_0x6: 1/2 us_0x7: 1/4 us" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " XTAL32M_RCOSC_SYNC_DELAY_TRIM ,Synchronization mode delay trim." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x3 line.long 0x00 "XTAL32M_CTRL2_REG,Control register for XTAL32M" hexmask.long.byte 0x00 24.--31. 1. " XTAL32M_FREQ_DET_OFFSET ,Add extra offset to the frequency-detector result to compensate for mismatch between actual startup and frequency-detector result" bitfld.long 0x00 22.--23. " XTAL32M_FREQ_DET_LEN ,Length of frequency detection, used during calibration of the RC-oscillator._0x0 :256us M=8k_0x1: 128us M=4k_0x2: 64us M=2k_0x3: 32us M=1k" "0,1,2,3" hexmask.long.byte 0x00 14.--21. 1. " XTAL32M_RCOSC_TRIM_SNS ,Trim sensitivity used during calibration of the RC-oscillator.set to 122*M/128" textline " " bitfld.long 0x00 12.--13. " XTAL32M_CXCOMP_PHI_TRIM ,Phase correction for cxcomp circuit" "0,1,2,3" hexmask.long.word 0x00 3.--11. 1. " XTAL32M_CXCOMP_TRIM_CAP ,Size of shunt capacitance compensation cap" bitfld.long 0x00 0.--2. " XTAL32M_CXCOMP_BIAS_TRIM ,Bias current of the cxcomp circuit._0x0: minimum current (disabled)_..._0x7: maximum current" "0,1,2,3,4,5,6,7" group.long 0x3C++0x3 line.long 0x00 "XTAL32M_CTRL3_REG,Control register for XTAL32M" bitfld.long 0x00 31. " XTAL32M_LDO_ENABLE ,Force enable LDO" "0,1" bitfld.long 0x00 30. " XTAL32M_RCOSC_TRIM_STROBE ,Force RC-oscillator trim setting" "0,1" bitfld.long 0x00 29. " XTAL32M_OSC_TRIM_CAP_BIAS ,0: Connect varicap bottom-plate to top-plate with resistor._1: Connect varicap bottom-plate to fixed bias voltage" "0,1" textline " " bitfld.long 0x00 28. " XTAL32M_SW1_OUT ,Software control mode: force SW1 signal (xtaltrim delay between RAMP and START)" "0,1" bitfld.long 0x00 27. " XTAL32M_DCBLOCK_LV_MODE ,Low-voltage cmp testmode" "0,1" bitfld.long 0x00 26. " XTAL32M_RCOSC2DXTAL ,Use RC-oscillator output for DXTAL" "0,1" textline " " bitfld.long 0x00 25. " XTAL32M_CORE_I2V_TO_TESTBUS_10X ,Increase the gain of the core amplifier testmode" "0,1" bitfld.long 0x00 24. " XTAL32M_CORE_I2V_TO_TESTBUS ,Enable the core amplifier testmode" "0,1" bitfld.long 0x00 23. " XTAL32M_OSC_TRIM_OPEN_DISABLE ,Varicap testmode, feedback resistors are disabled" "0,1" textline " " bitfld.long 0x00 22. " XTAL32M_FREQ_DET_START ,Force start frequency detector" "0,1" bitfld.long 0x00 21. " XTAL32M_RCOSC_ENABLE ,Force Enable RC-oscillator" "0,1" bitfld.long 0x00 20. " XTAL32M_RCOSC_SYNC_FORCE ,Force a the RCOSC synchronization: driver startst" "0,1" textline " " bitfld.long 0x00 19. " XTAL32M_RCOSC_SYNC_GATE ,Gate the RC-oscillator (and driver), when signal falls, the RC-oscillator will startup synchronized" "0,1" bitfld.long 0x00 18. " XTAL32M_SW_CTRL_MODE ,Enable all the software overrides, the state-machine will remain in IDLE" "0,1" bitfld.long 0x00 14.--17. " XTAL32M_RCOSC_BAND_SELECT ,Set RCOSC band select - apply with RCOSC_TRIM_STROBE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--13. 1. " XTAL32M_RCOSC_TRIM ,Set RCOSC trim (fine) - apply with RCOSC_TRIM_STROBE" bitfld.long 0x00 3. " XTAL32M_CORE_AMPREG_NULLBIAS ,Keep bias in ampdet alive, even when there is a large drive" "0,1" bitfld.long 0x00 2. " XTAL32M_CORE_FB_ENABLE ,Enable feedback resistors on core amplifier output" "0,1" textline " " bitfld.long 0x00 1. " XTAL32M_CORE_SAMPLE_AMPL_CTRL ,Software control mode: Sample voltage on amplitude detector" "0,1" bitfld.long 0x00 0. " XTAL32M_CORE_AMPREG_SIG_ENABLE ,Software override to enable amplitude detector input signal" "0,1" group.long 0x40++0x3 line.long 0x00 "XTAL32M_CTRL4_REG,Control register for XTAL32M" bitfld.long 0x00 23. " XTAL32M_CORE_CUR_PTAT ,Adds PTAT current contribution to the ampltude regulator (TEST ONLY)" "0,1" bitfld.long 0x00 22. " XTAL32M_CORE_CUR_NTAT_DIS ,Disables the (NTAT) current contribution in the ampltidue regulator" "0,1" bitfld.long 0x00 21. " XTAL32M_SYNC_DELAY_TEST_INT ,When in SYNC_DELAY_TESTMODE, use RCOSC output instead of DXTAL. This allows for the xtal pins not to be in the delay-loop (ATE test)" "0,1" textline " " bitfld.long 0x00 19.--20. " XTAL32M_TAMPDET_BLANK_SETTLE ,Amplitude regulator settling time - allows for amplitude regulator to settle to its value when drive sequence is completed" "0,1,2,3" bitfld.long 0x00 17.--18. " XTAL32M_TAMPDET_BLANK ,Blanking time for amplitude regulator when GM_CURRENT is set by state-machine" "0,1,2,3" bitfld.long 0x00 16. " XTAL32M_AMPDET_BLANK ,Enable blaning of the amplitude regulator - blanks glitch from the enabling of GM_CURRENT" "0,1" textline " " bitfld.long 0x00 15. " XTAL32M_CXCOMP_ENABLE_GATE ,Use CXCOMP circuit only at startup. Enable signal of CXCOMP circuit is gated with trim_ready signal" "0,1" bitfld.long 0x00 14. " XTAL32M_RST_N_XTAL ,Software control mode - releases reset of control logic in xtal" "0,1" bitfld.long 0x00 13. " XTAL32M_LDO_VREF_SELECT ,0: Select 1.2V reference input for the LDO._1: Select vref2 as reference input for the LDO" "0,1" textline " " bitfld.long 0x00 12. " XTAL32M_RFCLK_ADPLL_TO_GPIO ,Enable test output of rfclk_adpll to GPIO" "0,1" bitfld.long 0x00 11. " XTAL32M_RFCLK_ADC_TO_GPIO ,Enable test output of rfclk_adc to GPIO" "0,1" bitfld.long 0x00 10. " XTAL32M_CXCOMP_TEST_P_TO_TB ,Shuntcap measurement testmode: Put xtal_p on testbus<0>" "0,1" textline " " bitfld.long 0x00 9. " XTAL32M_CXCOMP_TEST_N_TO_TB ,Shuntcap measurement testmode: Put xtal_n on testbus<0>" "0,1" bitfld.long 0x00 5.--8. " XTAL32M_CXCOMP_TEST_CTRL ,Shuntcap measurement testmode: Control cxcomp test switches._Bit 0: x_lo - discharge nodes_Bit 1: p_hi - charge xtal_p to 1.2V_Bit 2: n_hi - charge xtal_n to 1.2V_Bit 3: cx_hi - charge CX node to 1.2V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " XTAL32M_SW2_MASK ,Software control mode: mask signal for sw2 (amplitude comparator output)" "0,1" textline " " bitfld.long 0x00 3. " XTAL32M_VARICAP_TEST_ENABLE ,Enable varicap test outputs to DCORE" "0,1" bitfld.long 0x00 2. " XTAL32M_CXCOMP_TEST ,Enable the testmode of the cxcomp circuit" "0,1" bitfld.long 0x00 1. " XTAL32M_LDO_TEST ,Put the LDO output voltage on testbus<0>" "0,1" textline " " bitfld.long 0x00 0. " XTAL32M_SYNC_DELAY_TEST ,Enable the calibration/testmode of the sync circuit" "0,1" group.long 0x50++0x3 line.long 0x00 "XTAL32M_STAT0_REG,Status register for XTAL32M" rbitfld.long 0x00 28.--31. " XTAL32M_RCOSC_BAND_SELECT_STAT ,Currently selected band" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 18.--27. 1. " XTAL32M_RCOSC_TRIM_STAT ,Current trim result" rbitfld.long 0x00 17. " XTAL32M_LDO_OK ,XTAL32M LDO output voltage is: 0: not OK, 1: OK" "0,1" textline " " rbitfld.long 0x00 16. " XTAL32M_SW2_IN ,Amplitude comparator output signal" "0,1" rbitfld.long 0x00 15. " XTAL32M_RCOSC_CALIBRATION_DONE ,Signals that the calibration phase has been completed" "0,1" rbitfld.long 0x00 14. " XTAL32M_FREQ_DET_END ,Signals that frequency detection has been completed" "0,1" textline " " hexmask.long.word 0x00 0.--13. 1. " XTAL32M_FREQ_DET_OUT ,Result of frequency detection" group.long 0x54++0x3 line.long 0x00 "XTAL32M_STAT1_REG,Status register for XTAL32M" rbitfld.long 0x00 26. " XTAL32M_XTAL_OVERLOAD ,Indicates xtal is (heavily) overloaded" "0,1" rbitfld.long 0x00 25. " XTAL32M_RCOSC_SYNC_FORCE_STAT ,Value of the synchronization force signal from the calibration or startup state-machine" "0,1" rbitfld.long 0x00 24. " XTAL32M_RCOSC_SYNC_GATE_STAT ,Value of the gate force signal from the calibration and startup state-machine" "0,1" textline " " rbitfld.long 0x00 23. " XTAL32M_RCOSC_XTAL_DRIVE_STAT ,Value of the XTAL drive signal from the startup state-machine" "0,1" hexmask.long.word 0x00 11.--22. 1. " XTAL32M_SM_TIMER ,Current value of the counter used for various timeouts" rbitfld.long 0x00 10. " XTAL32M_TRIM_READY ,Signals that the crystal-oscillator trimming has been completed" "0,1" textline " " rbitfld.long 0x00 9. " XTAL32M_SETTLE_READY ,Signals that the crystal has been settled" "0,1" rbitfld.long 0x00 8. " XTAL32M_SW2_OUT ,Masked sw2_in signal" "0,1" rbitfld.long 0x00 4.--7. " XTAL32M_CAL_STATE ,Current state of the calibration state-machine._0x0: CAL_DELAY - Delay for the biasing to settle_0x1: CAL_SYNC - Enables synchronization circuit_0x2: CAL_FREQDET - Enables the frequency detector_0x3: CAL_OFFSET - Evaluate OFFSET trimresult_0x4: CAL_MULT_SHIFT - Evaluate (delta) trimresult_0x5: CAL_TRIM - Generate new trimvalue_0x6: CAL_BAND_UPDWN - Delay after band change_0x7: CAL_END - Calibration ended_0x8: CAL_IDLE - Calibration IDLE (default state)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 0.--3. " XTAL32M_STATE ,Current state of the startup state-machine._0x0: XTAL_WAIT_LDO - Allow for setling of the biasing_0x1: XTAL_DRIVE - Crystal is driven by rcosc_0x2: XTAL_DISCHARGE - Discharge loadcaps_0x3: XTAL_SETTLE - Allows for settling of the xtal signal_0x4: XTAL_SYNC - Restart RCOSC, and synchronize_0x5: XTAL_OVERLOAD_DETECT - amplitude detection mode by overload bit_0x6: XTAL_OVERLOAD_BLANK_SETTLE - setling delay for amplitude regulator when drive ends_0x7: XTAL_OVERLOAD_BLANK - blank glitch from enabling gm_current_0x8: XTAL_RUN - Startup ended_0x9: XTAL_SAMPLE - Delay before sample amplitude control_0xa: XTAL_SW2_MASK - Delay for masked SW2_0xb: XTAL_IDLE - Idle state (default)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "XTAL32M_TRSTAT_REG,Read back value of current XTAL trimming" hexmask.long.word 0x00 0.--14. 1. " XTAL32M_TRSTAT ,Reads value of the current XTAL trimming" group.long 0x18++0x3 line.long 0x00 "XTALRDY_CTRL_REG,Control register for XTALRDY IRQ" bitfld.long 0x00 8. " XTALRDY_CLK_SEL ,XTALRDY IRQ timer clock selection:_0: 32KHz_1: 256kHz" "0,1" hexmask.long.byte 0x00 0.--7. 1. " XTALRDY_CNT ,Number of 32kHz or 256kHz cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. Frequency set by XTALRDY_CLK_SEL._0x00: no interrupt" group.long 0x1C++0x3 line.long 0x00 "XTALRDY_STAT_REG,Difference between XTAL_OK and XTALRDY_IRQ in LP clock cycles" hexmask.long.byte 0x00 8.--15. 1. " XTALRDY_COUNT ,Current value of IRQ counter" hexmask.long.byte 0x00 0.--7. 1. " XTALRDY_STAT ,Value of IRQ counter when trimming is switched from RAMP to TRIM" width 0x0B tree.end tree "DCDC" base ad:0x50000300 width 21. group.long 0x4++0x3 line.long 0x00 "DCDC_CTRL1_REG,DCDC First Control Register" bitfld.long 0x00 31. " DCDC_SH_ENABLE ,Enables sample and hold circuit in output comparators" "0,1" bitfld.long 0x00 26.--30. " DCDC_STARTUP_DELAY ,Delay between turning bias on and converter becoming active_0 - 31 us, 1 us step size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--25. " DCDC_IDLE_MAX_FAST_DOWNRAMP ,Maximum output idle time for fast current limit downramping._0 - 7875 ns, 125 ns step size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 15.--19. " DCDC_SW_TIMEOUT ,P and N switch timeout, if switch is closed longer than this a timeout is generated and the FSM is forced to the next state_Writing 0 disables timeout functionality_62.5 - 1937.5 ns, 62.5 ns step size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " DCDC_FAST_STARTUP ,Set current limit to maximum during initial startup" "0,1" bitfld.long 0x00 13. " DCDC_MAN_LV_MODE ,Manually activates low voltage settings" "0,1" textline " " bitfld.long 0x00 12. " DCDC_AUTO_LV_MODE ,Switches to low voltage settings when battery voltage drops below 2.5 V" "0,1" bitfld.long 0x00 10.--11. " DCDC_IDLE_CLK_DIV ,Idle Clock Divider_00 = 2_01 = 4_10 = 8_11 = 16" "0,1,2,3" hexmask.long.byte 0x00 2.--9. 1. " DCDC_PRIORITY ,Charge priority register (4x 2 bit ID)_Charge sequence is [1:0] > [3:2] > [5:4] > [7:6]_V14 = 00_V18 = 01_VDD = 10_V18P = 11" textline " " bitfld.long 0x00 1. " DCDC_FW_ENABLE ,Freewheel switch enable" "0,1" bitfld.long 0x00 0. " DCDC_ENABLE ,Enable setting for DCDC converter" "0,1" group.long 0x8++0x3 line.long 0x00 "DCDC_CTRL2_REG,DCDC Second Control Register" bitfld.long 0x00 24.--27. " DCDC_V_NOK_CNT_MAX ,Maximum number of V_NOK events on an output before V_AVAILABLE is reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22. " DCDC_N_COMP_TRIM_MAN ,Enables manual trimming for N side comparator" "0,1" bitfld.long 0x00 16.--21. " DCDC_N_COMP_TRIM_VAL ,Manual trim value for N side comparator_Signed magnitude representation_011111 = +13 mV_000000 = 100000 = -22 mV_111111 = -56 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 12.--15. " DCDC_TIMEOUT_IRQ_TRIG ,Number of timeout events before timeout interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DCDC_TIMEOUT_IRQ_RES ,Number of successive non-timed out charge events required to clear timeout event counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DCDC_SLOPE_CONTROL ,Sets strength of N and P switch drivers" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " DCDC_VBTSTRP_TRIM ,Trim bootstrap voltage_V = 1.6 V + 100 mV * N" "0,1,2,3" bitfld.long 0x00 2.--3. " DCDC_LSSUP_TRIM ,Trim low side supply voltage_V = 2 V + 300 mV * N" "0,1,2,3" bitfld.long 0x00 0.--1. " DCDC_HSGND_TRIM ,Trim high side ground_V = VBAT - (2 V + 400 mV * N)" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "DCDC_IRQ_CLEAR_REG,DCDC Interrupt Clear Register" bitfld.long 0x00 4. " DCDC_LOW_VBAT_IRQ_CLEAR ,Clear low VBAT interrupt" "0,1" bitfld.long 0x00 3. " DCDC_V18P_TIMEOUT_IRQ_CLEAR ,Clear V18P timeout interrupt" "0,1" bitfld.long 0x00 2. " DCDC_VDD_TIMEOUT_IRQ_CLEAR ,Clear VDD timeout interrupt" "0,1" textline " " bitfld.long 0x00 1. " DCDC_V18_TIMEOUT_IRQ_CLEAR ,Clear V18 timeout interrupt" "0,1" bitfld.long 0x00 0. " DCDC_V14_TIMEOUT_IRQ_CLEAR ,Clear V14 timeout interrupt" "0,1" group.long 0x38++0x3 line.long 0x00 "DCDC_IRQ_MASK_REG,DCDC Interrupt Clear Register" bitfld.long 0x00 4. " DCDC_LOW_VBAT_IRQ_MASK ,Mask low VBAT interrupt" "0,1" bitfld.long 0x00 3. " DCDC_V18P_TIMEOUT_IRQ_MASK ,Mask V18P timeout interrupt" "0,1" bitfld.long 0x00 2. " DCDC_VDD_TIMEOUT_IRQ_MASK ,Mask VDD timeout interrupt" "0,1" textline " " bitfld.long 0x00 1. " DCDC_V18_TIMEOUT_IRQ_MASK ,Mask V18 timeout interrupt" "0,1" bitfld.long 0x00 0. " DCDC_V14_TIMEOUT_IRQ_MASK ,Mask V14 timeout interrupt" "0,1" group.long 0x30++0x3 line.long 0x00 "DCDC_IRQ_STATUS_REG,DCDC Interrupt Status Register" rbitfld.long 0x00 4. " DCDC_LOW_VBAT_IRQ_STATUS ,Low VBAT detector triggered (battery voltage below 2.5 V)" "0,1" rbitfld.long 0x00 3. " DCDC_V18P_TIMEOUT_IRQ_STATUS ,Timeout occured on V18P output" "0,1" rbitfld.long 0x00 2. " DCDC_VDD_TIMEOUT_IRQ_STATUS ,Timeout occured on VDD output" "0,1" textline " " rbitfld.long 0x00 1. " DCDC_V18_TIMEOUT_IRQ_STATUS ,Timeout occured on V18 output" "0,1" rbitfld.long 0x00 0. " DCDC_V14_TIMEOUT_IRQ_STATUS ,Timeout occured on V14 output" "0,1" group.long 0x20++0x3 line.long 0x00 "DCDC_STATUS1_REG,DCDC First Status Register" rbitfld.long 0x00 27. " DCDC_V18P_AVAILABLE ,Indicates whether V18P is available_Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured" "0,1" rbitfld.long 0x00 26. " DCDC_VDD_AVAILABLE ,Indicates whether VDD is available_Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured" "0,1" rbitfld.long 0x00 25. " DCDC_V18_AVAILABLE ,Indicates whether V18 is available_Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured" "0,1" textline " " rbitfld.long 0x00 24. " DCDC_V14_AVAILABLE ,Indicates whether V14 is available_Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured" "0,1" rbitfld.long 0x00 23. " DCDC_V18P_COMP_OK ,OK output of V18P comparator" "0,1" rbitfld.long 0x00 22. " DCDC_VDD_COMP_OK ,OK output of VDD comparator" "0,1" textline " " rbitfld.long 0x00 21. " DCDC_V18_COMP_OK ,OK output of V18 comparator" "0,1" rbitfld.long 0x00 20. " DCDC_V14_COMP_OK ,OK output of V14 comparator" "0,1" rbitfld.long 0x00 19. " DCDC_V18P_COMP_NOK ,NOK output of V18P comparator" "0,1" textline " " rbitfld.long 0x00 18. " DCDC_VDD_COMP_NOK ,NOK output of VDD comparator" "0,1" rbitfld.long 0x00 17. " DCDC_V18_COMP_NOK ,NOK output of V18 comparator" "0,1" rbitfld.long 0x00 16. " DCDC_V14_COMP_NOK ,NOK output of V14 comparator" "0,1" textline " " rbitfld.long 0x00 11. " DCDC_N_COMP_P ,DCDC N side dynamic comparator P output" "0,1" rbitfld.long 0x00 10. " DCDC_N_COMP_N ,DCDC N side dynamic comparator N output" "0,1" rbitfld.long 0x00 9. " DCDC_P_COMP ,DCDC P side continuous time comparator output" "0,1" textline " " rbitfld.long 0x00 8. " DCDC_N_COMP ,DCDC N side continuous time comparator output" "0,1" rbitfld.long 0x00 7. " DCDC_LV_MODE ,Indicates if the converter is in low battery voltage mode" "0,1" rbitfld.long 0x00 6. " DCDC_V18P_SW_STATE ,DCDC state machine V18P output" "0,1" textline " " rbitfld.long 0x00 5. " DCDC_VDD_SW_STATE ,DCDC state machine VDD output" "0,1" rbitfld.long 0x00 4. " DCDC_V18_SW_STATE ,DCDC state machine V18 output" "0,1" rbitfld.long 0x00 3. " DCDC_V14_SW_STATE ,DCDC state machine V14 output" "0,1" textline " " rbitfld.long 0x00 2. " DCDC_N_SW_STATE ,DCDC state machine NSW output" "0,1" rbitfld.long 0x00 1. " DCDC_P_SW_STATE ,DCDC state machine PSW output" "0,1" rbitfld.long 0x00 0. " DCDC_STARTUP_COMPLETE ,Indicates if the converter is enabled and the startup counter has expired (internal biasing settled)" "0,1" group.long 0x24++0x3 line.long 0x00 "DCDC_STATUS2_REG,DCDC Second Status Register" rbitfld.long 0x00 21.--25. " DCDC_V18P_CUR_LIM ,Actual V18P current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DCDC_V18_CUR_LIM ,Actual V18 current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 5.--9. " DCDC_VDD_CUR_LIM ,Actual VDD current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 0.--4. " DCDC_V14_CUR_LIM ,Actual V14 current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "DCDC_STATUS3_REG,DCDC Third Status Register" rbitfld.long 0x00 22.--27. " DCDC_V18P_N_COMP_TRIM ,Actual V18P N side comparator trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--21. " DCDC_V18_N_COMP_TRIM ,Actual V18 N side comparator trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 6.--11. " DCDC_VDD_N_COMP_TRIM ,Actual VDD N side comparator trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 0.--5. " DCDC_V14_N_COMP_TRIM ,Actual V14 N side comparator trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x3 line.long 0x00 "DCDC_STATUS4_REG,DCDC Fourth Status Register" rbitfld.long 0x00 9.--11. " DCDC_CHARGE_REG_3 ,Charge register position 3" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 6.--8. " DCDC_CHARGE_REG_2 ,Charge register position 2" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 3.--5. " DCDC_CHARGE_REG_1 ,Charge register position 1" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x00 0.--2. " DCDC_CHARGE_REG_0 ,Charge register position 0" "0,1,2,3,4,5,6,7" group.long 0x1C++0x3 line.long 0x00 "DCDC_TEST_REG,DCDC Test Register" bitfld.long 0x00 25.--28. " DCDC_TEST_OUT ,Selects which register appears on the test mode pins_0 = None_1 = DCDC_STATUS_1 High Bits_2 = DCDC_STATUS_1 Low Bits_3 = DCDC_STATUS_2 High Bits_4 = DCDC_STATUS_2 Low Bits_5 = DCDC_STATUS_3 High Bits_6 = DCDC_STATUS_3 Low Bits_7 = DCDC_STATUS_4 Low Bits_8-F = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--24. " DCDC_FORCE_CUR_LIM_VAL ,Current limit setting when forced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " DCDC_FORCE_COMP_CLK_VAL ,Sets clock lines for the output comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 15. " DCDC_FORCE_CUR_LIM ,Force output current setting" "0,1" bitfld.long 0x00 14. " DCDC_FORCE_COMP_CLK ,Disables automatic comparator clock, clock lines values based on FORCE_COMP_CLK_VAL" "0,1" bitfld.long 0x00 11.--13. " DCDC_OUTPUT_MON ,Output monitor switch (connect to ADC)_000 = None_001 = VDD_010 = V18_011 = V14_100 = V18P_101 = V18F_110 = None_111 = None" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " DCDC_ANA_TEST ,Analog test bus_000 = None_001 = High side ground_010 = Low side supply_011 = Bootstrap voltage_100 = 1.0 V buffer output_101 = None_110 = None_111 = None" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. " DCDC_FORCE_IDLE ,Force idle mode" "0,1" bitfld.long 0x00 6. " DCDC_FORCE_V18P_SW ,Force V18P switch on" "0,1" textline " " bitfld.long 0x00 5. " DCDC_FORCE_VDD_SW ,Force VDD switch on" "0,1" bitfld.long 0x00 4. " DCDC_FORCE_V18_SW ,Force V18 switch on" "0,1" bitfld.long 0x00 3. " DCDC_FORCE_V14_SW ,Force V14 switch on" "0,1" textline " " bitfld.long 0x00 2. " DCDC_FORCE_FW_SW ,Force FW switch on" "0,1" bitfld.long 0x00 1. " DCDC_FORCE_N_SW ,Force N switch on" "0,1" bitfld.long 0x00 0. " DCDC_FORCE_P_SW ,Force P switch on" "0,1" group.long 0xC++0x3 line.long 0x00 "DCDC_V14_REG,DCDC V14 Control Register" bitfld.long 0x00 31. " DCDC_V14_FAST_RAMPING ,Fast current ramping (improves response time at the cost of more ripple)" "0,1" bitfld.long 0x00 27. " DCDC_V14_TRIM ,Output voltage trim_Steps of 25 mV" "0,1" bitfld.long 0x00 22.--26. " DCDC_V14_CUR_LIM_MAX_HV ,Mximum current limit (high battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17.--21. " DCDC_V14_CUR_LIM_MAX_LV ,Maximum current limit (low battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " DCDC_V14_CUR_LIM_MIN ,Minimum current limit_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--11. " DCDC_V14_IDLE_HYST ,Idle time hysteresis_0 - 3875 ns, 125 ns step size_IDLE_MAX = IDLE_MIN + IDLE_HYST_Maximum idle time before decreasing CUR_LIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2.--6. " DCDC_V14_IDLE_MIN ,Minimum idle time_0 - 3875 ns, 125 ns step size_Minimum idle time, CUR_LIM is increased if this limit is not reached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DCDC_V14_ENABLE_HV ,Output enable (high battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" bitfld.long 0x00 0. " DCDC_V14_ENABLE_LV ,Output enable (low battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" group.long 0x18++0x3 line.long 0x00 "DCDC_V18P_REG,DCDC V18P Control Register" bitfld.long 0x00 31. " DCDC_V18P_FAST_RAMPING ,Fast current ramping (improves response time at the cost of more ripple)" "0,1" bitfld.long 0x00 27.--30. " DCDC_V18P_TRIM ,Output voltage trim_Steps of 25 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--26. " DCDC_V18P_CUR_LIM_MAX_HV ,Maximum current limit (high battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17.--21. " DCDC_V18P_CUR_LIM_MAX_LV ,Maximum current limit (low battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " DCDC_V18P_CUR_LIM_MIN ,Minimum current limit_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--11. " DCDC_V18P_IDLE_HYST ,Idle time hysteresis_0 - 3875 ns, 125 ns step size_IDLE_MAX = IDLE_MIN + IDLE_HYST_Maximum idle time before decreasing CUR_LIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2.--6. " DCDC_V18P_IDLE_MIN ,Minimum idle time_0 - 3875 ns, 125 ns step size_Minimum idle time, CUR_LIM is increased if this limit is not reached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DCDC_V18P_ENABLE_HV ,Output enable (high battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" bitfld.long 0x00 0. " DCDC_V18P_ENABLE_LV ,Output enable (low battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" group.long 0x14++0x3 line.long 0x00 "DCDC_V18_REG,DCDC V18 Control Register" bitfld.long 0x00 31. " DCDC_V18_FAST_RAMPING ,Fast current ramping (improves response time at the cost of more ripple)" "0,1" bitfld.long 0x00 27.--30. " DCDC_V18_TRIM ,Output voltage trim_Steps of 25 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--26. " DCDC_V18_CUR_LIM_MAX_HV ,Maximum current limit (high battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17.--21. " DCDC_V18_CUR_LIM_MAX_LV ,Maximum current limit (low battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " DCDC_V18_CUR_LIM_MIN ,Minimum current limit_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--11. " DCDC_V18_IDLE_HYST ,Idle time hysteresis_0 - 3875 ns, 125 ns step size_IDLE_MAX = IDLE_MIN + IDLE_HYST_Maximum idle time before decreasing CUR_LIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2.--6. " DCDC_V18_IDLE_MIN ,Minimum idle time_0 - 3875 ns, 125 ns step size_Minimum idle time, CUR_LIM is increased if this limit is not reached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DCDC_V18_ENABLE_HV ,Output enable (high battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" bitfld.long 0x00 0. " DCDC_V18_ENABLE_LV ,Output enable (low battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" group.long 0x10++0x3 line.long 0x00 "DCDC_VDD_REG,DCDC VDD Control Register" bitfld.long 0x00 31. " DCDC_VDD_FAST_RAMPING ,Fast current ramping (improves response time at the cost of more ripple)" "0,1" bitfld.long 0x00 27.--29. " DCDC_VDD_TRIM ,Output voltage trim_Steps of 25 mV" "0,1,2,3,4,5,6,7" bitfld.long 0x00 22.--26. " DCDC_VDD_CUR_LIM_MAX_HV ,Maximum current limit (high battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17.--21. " DCDC_VDD_CUR_LIM_MAX_LV ,Maximum current limit (low battery voltage mode)_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " DCDC_VDD_CUR_LIM_MIN ,Minimum current limit_I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--11. " DCDC_VDD_IDLE_HYST ,Idle time hysteresis_0 - 3875 ns, 125 ns step size_IDLE_MAX = IDLE_MIN + IDLE_HYST_Maximum idle time before decreasing CUR_LIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2.--6. " DCDC_VDD_IDLE_MIN ,Minimum idle time_0 - 3875 ns, 125 ns step size_Minimum idle time, CUR_LIM is increased if this limit is not reached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DCDC_VDD_ENABLE_HV ,Output enable (high battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" bitfld.long 0x00 0. " DCDC_VDD_ENABLE_LV ,Output enable (low battery voltage mode)_0 = Disabled_1 = Enabled" "0,1" width 0x0B tree.end tree "DEM" base ad:0x40021000 width 28. group.long 0x20++0x3 line.long 0x00 "RF_AFC_CTRL_REG," bitfld.long 0x00 9. " AFC_SYNCF_DIRECT ,Allow the AFC state to directly transit from IDLE or PREAMBLE detection state to LOCKED state" "0,1" bitfld.long 0x00 6.--8. " APD_MODE ,Select the mode in the APD FSM:__xx1: Enable the transition from the ADDRESSDETECTION state to the IDLE state when the signal detection is low_x1x: Enable the reset of the AFC filter when the FSM is in the IDLE state_1xx: Enable the time out in the PREAMBLEDETECTION state. The FSM returns to the IDLE state after the time out" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--5. " PAD_MODE ,The PAD mode in BLE mode__00: No limits_01: Wrapping_10: Saturate to zero_11: 580 legacy mode" "0,1,2,3" textline " " bitfld.long 0x00 0.--3. " AFC_MODE ,Choose the method to use for AFC tracking during the slot_Description TBD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "RF_AGC_CTRL1_REG," bitfld.long 0x00 21.--22. " AGC_MODE ,Choose the method to use for AGC evaluation_Description TBD" "0,1,2,3" hexmask.long.byte 0x00 14.--20. 1. " AGC_TH2_HIGH ,AGC treshhold for FASTAGC mode... switch up number of steps defined by FASTAGC_STEPS" hexmask.long.byte 0x00 7.--13. 1. " AGC_TH_HIGH ,AGC hysteresis high threshold (switch up one AGC_SETTING_R step when exceeding this level)" textline " " hexmask.long.byte 0x00 0.--6. 1. " AGC_TH_LOW ,AGC hysteresis low threshold (switch down one AGC_SETTING_R step when dropping below this level)" group.long 0x1C++0x3 line.long 0x00 "RF_AGC_CTRL2_REG," bitfld.long 0x00 22. " EN_FRZ_GAIN ,'0': AGC always active_'1': Freeze gain after Access Address detection" "0,1" bitfld.long 0x00 18.--21. " AGCSETTING_WR ,Fixed AGC setting to be used to configure LNA, VGA1 and VGA2 when AGCSETTING_SEL = 1_0: Highest gain as configured in RF_AGC_LUT_01_REG_1: Lower gain as configured in RF_AGC_LUT_01_REG_2: Still lower gain as configured in RF_AGC_LUT_23_REG_..._9-F: Lowest gain as configured in RF_AGC_LUT_89_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " AGCSETTING_SEL ,LNA, VGA1 and VGA2 gains_'0': controlled by AGC_'1': provided manually through AGCSETTING_WR" "0,1" textline " " bitfld.long 0x00 9.--12. " AGC_MAX_SETTING ,Maximum AGC setting used from AGC LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--8. " AGCDEC_WAIT ,Wait time for settling after a single AGC step decrease (increasing gain)__0x0 - 1us_0x1 - 2us_0x2 - 3us_0x3 - 4us" "0,1,2,3" bitfld.long 0x00 5.--6. " AGCINC_WAIT ,Wait time for settling after a single AGC step increase (decreasing gain)__0x0 - 1us_0x1 - 2us_0x2 - 3us_0x3 - 4us" "0,1,2,3" textline " " bitfld.long 0x00 3.--4. " FASTAGC_WAIT ,Wait time for signal settling after fast AGC toggling__0x0 - 1us_0x1 - 2us_0x2 - 3us_0x3 - 4us" "0,1,2,3" bitfld.long 0x00 1.--2. " FASTAGC_STEPS ,Define the number of 6dB steps that is used when the RSSI level_is larger than AGC_TH2_HIGH__0x0 - 1 step_0x1 - 2 steps_0x2 - 3 steps_0x3 - 4 steps" "0,1,2,3" bitfld.long 0x00 0. " FASTAGC_EN ,Allow the AGC to decrease the gain by multiple steps of 6dB" "0,1" group.long 0x4++0x3 line.long 0x00 "RF_AGC_LUT_0123_REG," bitfld.long 0x00 29.--31. " LNA_GAIN3 ,LNA gain setting while in AGC setting 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " VGA1_GAIN3 ,VGA1 gain setting while in AGC setting 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. " VGA2_GAIN3 ,VGA2 gain setting while in AGC setting 3" "0,1,2,3" textline " " bitfld.long 0x00 21.--23. " LNA_GAIN2 ,LNA gain setting while in AGC setting 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VGA1_GAIN2 ,VGA1 gain setting while in AGC setting 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " VGA2_GAIN2 ,VGA2 gain setting while in AGC setting 2" "0,1,2,3" textline " " bitfld.long 0x00 13.--15. " LNA_GAIN1 ,LNA gain setting while in AGC setting 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " VGA1_GAIN1 ,VGA1 gain setting while in AGC setting 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. " VGA2_GAIN1 ,VGA2 gain setting while in AGC setting 1" "0,1,2,3" textline " " bitfld.long 0x00 5.--7. " LNA_GAIN0 ,LNA gain setting while in AGC setting 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " VGA1_GAIN0 ,VGA1 gain setting while in AGC setting 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " VGA2_GAIN0 ,VGA2 gain setting while in AGC setting 0" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "RF_AGC_LUT_4567_REG," bitfld.long 0x00 29.--31. " LNA_GAIN7 ,LNA gain setting while in AGC setting 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " VGA1_GAIN7 ,VGA1 gain setting while in AGC setting 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. " VGA2_GAIN7 ,VGA2 gain setting while in AGC setting 7" "0,1,2,3" textline " " bitfld.long 0x00 21.--23. " LNA_GAIN6 ,LNA gain setting while in AGC setting 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VGA1_GAIN6 ,VGA1 gain setting while in AGC setting 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " VGA2_GAIN6 ,VGA2 gain setting while in AGC setting 6" "0,1,2,3" textline " " bitfld.long 0x00 13.--15. " LNA_GAIN5 ,LNA gain setting while in AGC setting 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " VGA1_GAIN5 ,VGA1 gain setting while in AGC setting 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. " VGA2_GAIN5 ,VGA2 gain setting while in AGC setting 5" "0,1,2,3" textline " " bitfld.long 0x00 5.--7. " LNA_GAIN4 ,LNA gain setting while in AGC setting 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " VGA1_GAIN4 ,VGA1 gain setting while in AGC setting 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " VGA2_GAIN4 ,VGA2 gain setting while in AGC setting 4" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "RF_AGC_LUT_89AB_REG," bitfld.long 0x00 29.--31. " LNA_GAIN11 ,LNA gain setting while in AGC setting 11" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " VGA1_GAIN11 ,VGA1 gain setting while in AGC setting 11" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. " VGA2_GAIN11 ,VGA2 gain setting while in AGC setting 11" "0,1,2,3" textline " " bitfld.long 0x00 21.--23. " LNA_GAIN10 ,LNA gain setting while in AGC setting 10" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VGA1_GAIN10 ,VGA1 Gain setting while in AGC setting 10" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " VGA2_GAIN10 ,VGA2 gain setting while in AGC setting 10" "0,1,2,3" textline " " bitfld.long 0x00 13.--15. " LNA_GAIN9 ,LNA gain setting while in AGC setting 9" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " VGA1_GAIN9 ,VGA1 gain setting while in AGC setting 9" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. " VGA2_GAIN9 ,VGA2 gain setting while in AGC setting 9" "0,1,2,3" textline " " bitfld.long 0x00 5.--7. " LNA_GAIN8 ,LNA gain setting while in AGC setting 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " VGA1_GAIN8 ,VGA1 gain setting while in AGC setting 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " VGA2_GAIN8 ,VGA2 gain setting while in AGC setting 8" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "RF_AGC_LUT_CDEF_REG," bitfld.long 0x00 29.--31. " LNA_GAIN15 ,LNA gain setting while in AGC setting 15" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " VGA1_GAIN15 ,VGA1 gain setting while in AGC setting 15" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. " VGA2_GAIN15 ,VGA2 gain setting while in AGC setting 15" "0,1,2,3" textline " " bitfld.long 0x00 21.--23. " LNA_GAIN14 ,LNA gain setting while in AGC setting 14" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VGA1_GAIN14 ,VGA1 Gain setting while in AGC setting 14" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " VGA2_GAIN14 ,VGA2 gain setting while in AGC setting 14" "0,1,2,3" textline " " bitfld.long 0x00 13.--15. " LNA_GAIN13 ,LNA gain setting while in AGC setting 13" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " VGA1_GAIN13 ,VGA1 gain setting while in AGC setting 13" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. " VGA2_GAIN13 ,VGA2 gain setting while in AGC setting 13" "0,1,2,3" textline " " bitfld.long 0x00 5.--7. " LNA_GAIN12 ,LNA gain setting while in AGC setting 12" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " VGA1_GAIN12 ,VGA1 gain setting while in AGC setting 12" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " VGA2_GAIN12 ,VGA2 gain setting while in AGC setting 12" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "RF_AGC_RESULT_REG," rbitfld.long 0x00 8.--11. " AGCSETTING_RD ,AGC setting as automatically selected in receive mode to configure LNA, VGA1 and VGA2_0: Highest gain as configured in RF_AGC_LUT_01_REG_1: Lower gain as configured in RF_AGC_LUT_01_REG_2: Still lower gain as configured in RF_AGC_LUT_23_REG_..._9-F: Lowest gain as configured in RF_AGC_LUT_89_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " AFC_RD ,Frequency offset estimation (in 2s complement) with a resolution of approximately 5 kHz." group.long 0x24++0x3 line.long 0x00 "RF_DC_OFFSET_CTRL1_REG," hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_WR ,DC offset compensation value in Q channel valid when DCOFFSET_SEL = 1" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_WR ,DC offset compensation value in I channel valid when DCOFFSET_SEL = 1" group.long 0x28++0x3 line.long 0x00 "RF_DC_OFFSET_CTRL2_REG," bitfld.long 0x00 22.--23. " DCOC_RESULT_LNAGAIN345_LUT ,DCoffset result used for LNA gain settings 3 4 and 5." "0,1,2,3" bitfld.long 0x00 20.--21. " DCOC_RESULT_LNAGAIN2_LUT ,DCoffset result used for LNA gain setting 2" "0,1,2,3" bitfld.long 0x00 18.--19. " DCOC_RESULT_LNAGAIN1_LUT ,DCoffset result used for LNA gain setting 1" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " DCOC_RESULT_LNAGAIN0_LUT ,DCoffset result used for LNA gain setting 0" "0,1,2,3" bitfld.long 0x00 15. " DCPAR_DCF_EN ,Use a DCF to start the partial DC offset calibration." "0,1" bitfld.long 0x00 14. " DCPAR_MULT_STEPS_EN ,Enable the partial DCOC calibration with multiple gain settings._When not set, the partial calibration is the same as in 680BA." "0,1" textline " " bitfld.long 0x00 11.--13. " DCPARNGAIN ,Number of gain settings for the partial DC offset calibration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10. " DCVGA1SCALE_EN ,Enable the DC offset scaling with the VGA1 gain" "0,1" bitfld.long 0x00 8.--9. " DCPARCAL_INIT ,Select the inital value used for the partial DC offset calibration.__0: The DC offset from the previous packet_1: The DC offset found with the full DC offset calibration_2: Start from the mid value." "0,1,2,3" textline " " bitfld.long 0x00 5.--7. " DCFULLNGAIN ,Number of gain settings for the full DC offset calibration" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " DCNSTEP ,Number of the steps per.gain setting for the full or partial DC offset calibrations" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " DCPARCAL_EN ,Enable flag for the partial DC offset calibration The calbration is executed when the demodulator is enabled. _When the bit DCPAR_DCF_EN is set, the enabling is started by the DCF." "0,1" textline " " bitfld.long 0x00 0. " DCOFFSET_SEL ,'0': Normal operation_'1': Use the manual DC offset compensation values from RF_DC_OFFSET_CTRL1_REG" "0,1" group.long 0x2C++0x3 line.long 0x00 "RF_DC_OFFSET_CTRL3_REG," hexmask.long.byte 0x00 8.--15. 1. " DCBETA_Q ,Quadrature feedback gain for the DC offset calibration" hexmask.long.byte 0x00 0.--7. 1. " DCBETA_I ,Inphase feedback gain for the DC offset calibration" group.long 0x30++0x3 line.long 0x00 "RF_DC_OFFSET_CTRL4_REG," bitfld.long 0x00 12.--15. " DCAGCSETTING_FULL3 ,AGC setting for forth last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DCAGCSETTING_FULL2 ,AGC setting for third last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DCAGCSETTING_FULL1 ,AGC setting for second last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " DCAGCSETTING_FULL0 ,AGC setting for last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C++0x3 line.long 0x00 "RF_DC_OFFSET_FULL_RES_REG,Must be Retained" hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,Stored DC offset FULL calibration result value of the Q channel." hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,Stored DC offset FULL calibration result value of the Q channel." group.long 0x60++0x3 line.long 0x00 "RF_DC_OFFSET_MPAR_RES0_REG," hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,DC offset calibration result value of the last step of the multiple partial calibration. (Q channel)" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,DC offset calibration result value of the last step of the multiple partial calibration. (I channel)" group.long 0x64++0x3 line.long 0x00 "RF_DC_OFFSET_MPAR_RES1_REG," hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,DC offset calibration result value of the (last step -1) of the multiple partial calibration. (Q channel)" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,DC offset calibration result value of the (last step -1) of the multiple partial calibration. (I channel)" group.long 0x68++0x3 line.long 0x00 "RF_DC_OFFSET_MPAR_RES2_REG," hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,DC offset calibration result value of the (last step -2) of the multiple partial calibration. (Q channel)" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,DC offset calibration result value of the (last step-2) of the multiple partial calibration. (I channel)" group.long 0x6C++0x3 line.long 0x00 "RF_DC_OFFSET_MPAR_RES3_REG," hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,DC offset calibration result value of the (last step -3) of the multiple partial calibration. (Q channel)" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,DC offset calibration result value of the (last step-3) of the multiple partial calibration. (I channel)" group.long 0x58++0x3 line.long 0x00 "RF_DC_OFFSET_RESULT_REG,Must be Retained" hexmask.long.word 0x00 9.--17. 1. " DCOFFSET_Q_RD ,DC offset compensation value in Q channel valid when DCOFFSET_SEL = 0" hexmask.long.word 0x00 0.--8. 1. " DCOFFSET_I_RD ,DC offset compensation value in I channel valid when DCOFFSET_SEL = 0." group.long 0x3C++0x3 line.long 0x00 "RF_DEM_ATTR_REG," bitfld.long 0x00 24. " ADDR_TIMEOUT_X2 ,Program the Address Time Out when AFC is in MAC ADDRESS correlation state__0x0 - short time (32us in 2Mbit mode and 64us in 1Mbit mode)_0x1 - long time (64us in 2Mbit mode and 128us in 1Mbit mode)" "0,1" bitfld.long 0x00 22.--23. " RFADC_CLK_PHASE ,Select the phase of the RFADC clock" "0,1,2,3" bitfld.long 0x00 21. " DEM_16M_CLK_SET ,Sets the Demodulator clock speed. Automatically the RFADC speed is adjusted as well." "0,1" textline " " bitfld.long 0x00 15.--20. " RSSI_TH ,RSSI threshold for the packet detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--14. " DCPOLE ,Set the frequency of the DC offset highpass filter.__The frequency is different when the demodulator is used with 8MHz or 16MHz clock. __For 8MHz clock:__0x0 - 100kHz_0x1 - 50kHz_0x2 - 150kHz_0x3 - N/A" "0,1,2,3" bitfld.long 0x00 12. " DCOC_SPEED8M_EN ,Set the preferred Clock Speed for the DC Offset Block" "0,1" textline " " bitfld.long 0x00 11. " AGC_SPEED8M_EN ,Set the preferred clock speed for the AGC block" "0,1" bitfld.long 0x00 10. " DEM_SET_DEC2N ,Bit to select of the deimate by 2 is enabled.__0 - Decimation by 2 is enabled, use for 1Mbit mode with 16MHz clock_1 - Decimation by 2 disabled, use for 2Mbit mode with 16MHz clock or 1Mbit mode with 8MHz clock" "0,1" bitfld.long 0x00 6.--9. " MATCH0101_TH ,Threshold for the 0101 pattern matching" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 5. " DEM_HSI_POL ,Invert _frequency_ polarity of the demodulator" "0,1" bitfld.long 0x00 4. " RXDATA_INV ,'0': Normal operation_'1': Invert the polarity of the received bits" "0,1" bitfld.long 0x00 2.--3. " AFC_POLE2 ,Set the frequency of the AFC pole (Highpass filter) that is used before and after preamble detection._The absolute frequency is different for 1Mbit and 2Mbit mode.__3dB cut off frequency in 1Mbit mode.__0 - NA_1 - 78Hz_2 - 156Hz_3 - 311Hz__In 2Mbit mode, the frequency doubles." "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " AFC_POLE1 ,Set the frequency of the AFC pole (Highpass filter) that is used during preamble detection._The absolute frequency is different for 1Mbit and 2Mbit mode.__3dB cut off frequency in 1Mbit mode.__0 - NA_1 - 1.3kHz _2 - 2.5kHz_3 - 5.1kHz__In 2Mbit mode, the frequency doubles." "0,1,2,3" group.long 0x0++0x3 line.long 0x00 "RF_DEM_CTRL_REG," bitfld.long 0x00 5. " IQ_TO_GPIO_EN ,Enable the IQ data output for exposed radio mode." "0,1" bitfld.long 0x00 4. " AGC_USE_GPIO_IN ,Select to use the GPIO input as AGC setting._To be used with FPGA platform" "0,1" bitfld.long 0x00 3. " CIC_EN ,Enable the CIC filter in the decimator." "0,1" textline " " bitfld.long 0x00 2. " IQCORR_EN ,Enable the IQ mismatch correction__The correction coefficients are define in the RF_DEM_IQCORRECT_REG register" "0,1" bitfld.long 0x00 1. " BLE_DDC_EN ,Enable the digital conversion in BLE mode" "0,1" bitfld.long 0x00 0. " EQUAL_EN ,Enable the equalizer in the demodulator" "0,1" group.long 0x48++0x3 line.long 0x00 "RF_DEM_IQCORRECT_REG," hexmask.long.byte 0x00 8.--15. 1. " IQCORR_ALPHA ," hexmask.long.byte 0x00 0.--7. 1. " IQCORR_BETA ," group.long 0x44++0x3 line.long 0x00 "RF_DEM_TESTMODE_REG," hexmask.long.word 0x00 0.--9. 1. " DEM_TESTMODE ,Defines the demodulator test mode__DEM_TESTMODE[3:0] selects the data mapped on the testbus (see demodulator documentation for details.__The upper and lower 16-bits test data are swapped when DEM_TESTMODE[4] is set.__The lower 16-bits are assigned to the test bus when DEM_TESTMODE[5] is set. The input test bus is copied when DEM_TESTMODE[6] is reset.__The upper 16-bits are assigned to the test bus when DEM_TESTMODE[6] is set. The input test bus is copied with DEM_TESTMODE[7] is reset.__The trigger is slected with DEM_TESTMODE[8:7]_00: dem_en_01: Signal detected_10: Set with the rising edge of DEM_EN and reset with the rising edge of SYNC_FOUND_P_11: Set with the rising edge of SYNC_FOUND_P and reset with the falling edge of DEM_EN___DEM_TESTMODE[9] is reserved____Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" group.long 0x4C++0x3 line.long 0x00 "RF_PAD_CNT_CTRL_REG," bitfld.long 0x00 14. " PAD_CLEAR_COUNT ," "0,1" hexmask.long.byte 0x00 7.--13. 1. " PAD_NEG_LIMIT ," hexmask.long.byte 0x00 0.--6. 1. " PAD_POS_LIMIT ," group.long 0x50++0x3 line.long 0x00 "RF_PAD_CNT_RESULT_REG," hexmask.long.byte 0x00 8.--15. 1. " PAD_NEG_CNT_RD ," hexmask.long.byte 0x00 0.--7. 1. " PAD_POS_CNT_RD ," group.long 0x40++0x3 line.long 0x00 "RF_RSSI_COMP_CTRL_REG," bitfld.long 0x00 16.--19. " RSSI_COMP4 ,RSSI compensation value for LNA gain setting 3_Coding identical to RSSI_COMP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RSSI_COMP3 ,RSSI compensation value for LNA gain setting 3_Coding identical to RSSI_COMP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RSSI_COMP2 ,RSSI compensation value for LNA gain setting 2_Coding identical to RSSI_COMP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " RSSI_COMP1 ,RSSI compensation value for LNA gain setting 1_'0x0': -8_'0x1': -7_'0x2': -6_'0x3': -5_'0x4': -4_'0x5': -3_'0x6': -2_'0x7': -1_'0x8': 0 (reset)_'0x9': 1_'0xA': 2_'0xB': 3_'0xC': 4_'0xD': 5_'0xE': 6_'0xF': 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RSSI_COMP0 ,RSSI compensation value for LNA gain setting 00_'0x0': -8_'0x1': -7_'0x2': -6_'0x3': -5_'0x4': -4_'0x5': -3_'0x6': -2_'0x7': -1_'0x8': 0 (reset)_'0x9': 1_'0xA': 2_'0xB': 3_'0xC': 4_'0xD': 5_'0xE': 6_'0xF': 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "RF_RSSI_RESULT_REG," hexmask.long.word 0x00 10.--19. 1. " RSSI_AVG_RD ,RSSI value measured in averaging mode in continuous RX mode (used for LNA selectivity calibration)" hexmask.long.word 0x00 0.--9. 1. " RSSI_LATCHED_RD ,Averaged RSSI value latched with the Sync Found Pulse._Value is resetted when the demodulator is started and when stopped." width 0x0B tree.end tree "DMA" base ad:0x50040800 width 20. group.long 0x0++0x3 line.long 0x00 "DMA0_A_START_REG,Start address A of DMA channel 0" hexmask.long 0x00 0.--31. 1. " DMA0_A_START ,Source start address" group.long 0x4++0x3 line.long 0x00 "DMA0_B_START_REG,Start address B of DMA channel 0" hexmask.long 0x00 0.--31. 1. " DMA0_B_START ,Destination start address" group.long 0x10++0x3 line.long 0x00 "DMA0_CTRL_REG,Control register for the DMA channel 0" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0x14++0x3 line.long 0x00 "DMA0_IDX_REG,Index value of DMA channel 0" hexmask.long.word 0x00 0.--15. 1. " DMA0_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0x8++0x3 line.long 0x00 "DMA0_INT_REG,DMA receive interrupt register channel 0" hexmask.long.word 0x00 0.--15. 1. " DMA0_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0xC++0x3 line.long 0x00 "DMA0_LEN_REG,DMA receive length register channel 0" hexmask.long.word 0x00 0.--15. 1. " DMA0_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0x20++0x3 line.long 0x00 "DMA1_A_START_REG,Start address A of DMA channel 1" hexmask.long 0x00 0.--31. 1. " DMA1_A_START ,Source start address" group.long 0x24++0x3 line.long 0x00 "DMA1_B_START_REG,Start address B of DMA channel 1" hexmask.long 0x00 0.--31. 1. " DMA1_B_START ,Destination start address" group.long 0x30++0x3 line.long 0x00 "DMA1_CTRL_REG,Control register for the DMA channel 1" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA1_IDX_REG,Index value of DMA channel 1" hexmask.long.word 0x00 0.--15. 1. " DMA1_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0x28++0x3 line.long 0x00 "DMA1_INT_REG,DMA receive interrupt register channel 1" hexmask.long.word 0x00 0.--15. 1. " DMA1_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0x2C++0x3 line.long 0x00 "DMA1_LEN_REG,DMA receive length register channel 1" hexmask.long.word 0x00 0.--15. 1. " DMA1_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0x40++0x3 line.long 0x00 "DMA2_A_START_REG,Start address A of DMA channel 2" hexmask.long 0x00 0.--31. 1. " DMA2_A_START ,Source start address" group.long 0x44++0x3 line.long 0x00 "DMA2_B_START_REG,Start address B of DMA channel 2" hexmask.long 0x00 0.--31. 1. " DMA2_B_START ,Destination start address" group.long 0x50++0x3 line.long 0x00 "DMA2_CTRL_REG,Control register for the DMA channel 2" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address_0 = do not increment_1 = increment according value of BW" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0x54++0x3 line.long 0x00 "DMA2_IDX_REG,Index value of DMA channel 2" hexmask.long.word 0x00 0.--15. 1. " DMA2_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0x48++0x3 line.long 0x00 "DMA2_INT_REG,DMA receive interrupt register channel 2" hexmask.long.word 0x00 0.--15. 1. " DMA2_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0x4C++0x3 line.long 0x00 "DMA2_LEN_REG,DMA receive length register channel 2" hexmask.long.word 0x00 0.--15. 1. " DMA2_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0x60++0x3 line.long 0x00 "DMA3_A_START_REG,Start address A of DMA channel 3" hexmask.long 0x00 0.--31. 1. " DMA3_A_START ,Source start address" group.long 0x64++0x3 line.long 0x00 "DMA3_B_START_REG,Start address B of DMA channel 3" hexmask.long 0x00 0.--31. 1. " DMA3_B_START ,Destination start address" group.long 0x70++0x3 line.long 0x00 "DMA3_CTRL_REG,Control register for the DMA channel 3" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0x74++0x3 line.long 0x00 "DMA3_IDX_REG,Index value of DMA channel 3" hexmask.long.word 0x00 0.--15. 1. " DMA3_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0x68++0x3 line.long 0x00 "DMA3_INT_REG,DMA receive interrupt register channel 3" hexmask.long.word 0x00 0.--15. 1. " DMA3_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0x6C++0x3 line.long 0x00 "DMA3_LEN_REG,DMA receive length register channel 3" hexmask.long.word 0x00 0.--15. 1. " DMA3_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0x80++0x3 line.long 0x00 "DMA4_A_START_REG,Start address A of DMA channel 4" hexmask.long 0x00 0.--31. 1. " DMA4_A_START ,Source start address" group.long 0x84++0x3 line.long 0x00 "DMA4_B_START_REG,Start address B of DMA channel 4" hexmask.long 0x00 0.--31. 1. " DMA4_B_START ,Destination start address" group.long 0x90++0x3 line.long 0x00 "DMA4_CTRL_REG,Control register for the DMA channel 4" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0x94++0x3 line.long 0x00 "DMA4_IDX_REG,Index value of DMA channel 4" hexmask.long.word 0x00 0.--15. 1. " DMA4_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0x88++0x3 line.long 0x00 "DMA4_INT_REG,DMA receive interrupt register channel 4" hexmask.long.word 0x00 0.--15. 1. " DMA4_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0x8C++0x3 line.long 0x00 "DMA4_LEN_REG,DMA receive length register channel 4" hexmask.long.word 0x00 0.--15. 1. " DMA4_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0xA0++0x3 line.long 0x00 "DMA5_A_START_REG,Start address A of DMA channel 5" hexmask.long 0x00 0.--31. 1. " DMA5_A_START ,Source start address" group.long 0xA4++0x3 line.long 0x00 "DMA5_B_START_REG,Start address B of DMA channel 5" hexmask.long 0x00 0.--31. 1. " DMA5_B_START ,Destination start address" group.long 0xB0++0x3 line.long 0x00 "DMA5_CTRL_REG,Control register for the DMA channel 5" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0xB4++0x3 line.long 0x00 "DMA5_IDX_REG,Index value of DMA channel 5" hexmask.long.word 0x00 0.--15. 1. " DMA5_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0xA8++0x3 line.long 0x00 "DMA5_INT_REG,DMA receive interrupt register channel 5" hexmask.long.word 0x00 0.--15. 1. " DMA5_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0xAC++0x3 line.long 0x00 "DMA5_LEN_REG,DMA receive length register channel 5" hexmask.long.word 0x00 0.--15. 1. " DMA5_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0xC0++0x3 line.long 0x00 "DMA6_A_START_REG,Start address A of DMA channel 6" hexmask.long 0x00 0.--31. 1. " DMA6_A_START ,Source start address" group.long 0xC4++0x3 line.long 0x00 "DMA6_B_START_REG,Start address B of DMA channel 6" hexmask.long 0x00 0.--31. 1. " DMA6_B_START ,Destination start address" group.long 0xD0++0x3 line.long 0x00 "DMA6_CTRL_REG,Control register for the DMA channel 6" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically._It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0xD4++0x3 line.long 0x00 "DMA6_IDX_REG,Index value of DMA channel 6" hexmask.long.word 0x00 0.--15. 1. " DMA6_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0xC8++0x3 line.long 0x00 "DMA6_INT_REG,DMA receive interrupt register channel 6" hexmask.long.word 0x00 0.--15. 1. " DMA6_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0xCC++0x3 line.long 0x00 "DMA6_LEN_REG,DMA receive length register channel 6" hexmask.long.word 0x00 0.--15. 1. " DMA6_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0xE0++0x3 line.long 0x00 "DMA7_A_START_REG,Start address A of DMA channel 7" hexmask.long 0x00 0.--31. 1. " DMA7_A_START ,Source start address_NOTE: See also the DMA chapter of the Datasheet for the allowed range of the DMA7 channel's source address in Secure Boot mode" group.long 0xE4++0x3 line.long 0x00 "DMA7_B_START_REG,Start address B of DMA channel 7" hexmask.long 0x00 0.--31. 1. " DMA7_B_START ,Destination start address_NOTE: See also the DMA chapter of the Datasheet for the allowed range of the DMA7 channel's destination address in Secure Boot mode" group.long 0xF0++0x3 line.long 0x00 "DMA7_CTRL_REG,Control register for the DMA channel 7" bitfld.long 0x00 15. " BUS_ERROR_DETECT ,0 = Ignores bus error response from the AHB bus, so DMA continues normally._1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer._NOTE: In secure boot mode, the bus error detection mode of DMA7 channel is always enabled, overruling the specific bit-field's programmed value" "0,1" bitfld.long 0x00 13.--14. " BURST_MODE ,Enables the DMA read/write bursts, according to the following configuration:_00 = Bursts are disabled_01 = Bursts of 4 are enabled_10 = Bursts of 8 are enabled_11 = Reserved" "0,1,2,3" bitfld.long 0x00 12. " REQ_SENSE ,0 = DMA operates with level-sensitive peripheral requests (default)_1 = DMA operates with (positive) edge-sensitive peripheral requests" "0,1" textline " " bitfld.long 0x00 11. " DMA_INIT ,0 = DMA performs copy A1 to B1, A2 to B2, etc ..._1 = DMA performs copy of A1 to B1, B2, etc ..._This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'._NOTE: This bit-field is overruled to '0' when the DMA7 channel is configured as _trusted_ channel (in Secure Boot mode)" "0,1" bitfld.long 0x00 10. " DMA_IDLE ,0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority._1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care._*NOTE: This bit-field is overruled to '0' when the DMA7 channel is configured as _trusted_ channel (in Secure Boot mode)" "0,1" bitfld.long 0x00 7.--9. " DMA_PRIO ,The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific:_000 = lowest priority_111 = highest priority_If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6. " CIRCULAR ,0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed._1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer" "0,1" bitfld.long 0x00 5. " AINC ,Enable increment of source address._0 = do not increment (source address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" bitfld.long 0x00 4. " BINC ,Enable increment of destination address._0 = do not increment (destination address stays the same during the transfer)_1 = increment according to the value of BW bit-field (by 1, when BW=_00_ ; by 2, when BW=_01_ ; by 4, when BW=_10_)" "0,1" textline " " bitfld.long 0x00 3. " DREQ_MODE ,0 = DMA channel starts immediately_1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)_*NOTE: This bit-field is overruled to '0' when channel DMA7 is configured as _trusted_ channel (in Secure Boot mode)" "0,1" bitfld.long 0x00 1.--2. " BW ,Bus transfer width:_00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI)_01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI)_10 = 4 Bytes (suggested for Memory-to-Memory transfers)_11 = Reserved_NOTE: This bit-field is overruled to _10_ when channel DMA7 is configured as _trusted_ channel (in Secure Boot mode)" "0,1,2,3" bitfld.long 0x00 0. " DMA_ON ,0 = DMA channel is off, clocks are disabled_1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set._Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field" "0,1" group.long 0xF4++0x3 line.long 0x00 "DMA7_IDX_REG,Index value of DMA channel 7" hexmask.long.word 0x00 0.--15. 1. " DMA7_IDX ,This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on._When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again" group.long 0xE8++0x3 line.long 0x00 "DMA7_INT_REG,DMA receive interrupt register channel 7" hexmask.long.word 0x00 0.--15. 1. " DMA7_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt" group.long 0xEC++0x3 line.long 0x00 "DMA7_LEN_REG,DMA receive length register channel 7" hexmask.long.word 0x00 0.--15. 1. " DMA7_LEN ,DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, .." group.long 0x108++0x3 line.long 0x00 "DMA_CLEAR_INT_REG,DMA clear interrupt register" bitfld.long 0x00 7. " DMA_RST_IRQ_CH7 ,Writing a 1 will reset the IRQ of channel 7 ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 6. " DMA_RST_IRQ_CH6 ,Writing a 1 will reset the IRQ of channel 6 ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 5. " DMA_RST_IRQ_CH5 ,Writing a 1 will reset the IRQ of channel 5 ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 4. " DMA_RST_IRQ_CH4 ,Writing a 1 will reset the IRQ of channel 4 ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 3. " DMA_RST_IRQ_CH3 ,Writing a 1 will reset the IRQ of channel 3 ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 2. " DMA_RST_IRQ_CH2 ,Writing a 1 will reset the IRQ of channel 2 ; writing a 0 will have no effect" "0,1" textline " " bitfld.long 0x00 1. " DMA_RST_IRQ_CH1 ,Writing a 1 will reset the IRQ of channel 1 ; writing a 0 will have no effect" "0,1" bitfld.long 0x00 0. " DMA_RST_IRQ_CH0 ,Writing a 1 will reset the IRQ of channel 0 ; writing a 0 will have no effect" "0,1" group.long 0x10C++0x3 line.long 0x00 "DMA_INT_MASK_REG,DMA Interrupt mask register" bitfld.long 0x00 7. " DMA_IRQ_ENABLE7 ,0 = disable interrupts on channel 7_1 = enable interrupts on channel 7" "0,1" bitfld.long 0x00 6. " DMA_IRQ_ENABLE6 ,0 = disable interrupts on channel 6_1 = enable interrupts on channel 6" "0,1" bitfld.long 0x00 5. " DMA_IRQ_ENABLE5 ,0 = disable interrupts on channel 5_1 = enable interrupts on channel 5" "0,1" textline " " bitfld.long 0x00 4. " DMA_IRQ_ENABLE4 ,0 = disable interrupts on channel 4_1 = enable interrupts on channel 4" "0,1" bitfld.long 0x00 3. " DMA_IRQ_ENABLE3 ,0 = disable interrupts on channel 3_1 = enable interrupts on channel 3" "0,1" bitfld.long 0x00 2. " DMA_IRQ_ENABLE2 ,0 = disable interrupts on channel 2_1 = enable interrupts on channel 2" "0,1" textline " " bitfld.long 0x00 1. " DMA_IRQ_ENABLE1 ,0 = disable interrupts on channel 1_1 = enable interrupts on channel 1" "0,1" bitfld.long 0x00 0. " DMA_IRQ_ENABLE0 ,0 = disable interrupts on channel 0_1 = enable interrupts on channel 0" "0,1" group.long 0x104++0x3 line.long 0x00 "DMA_INT_STATUS_REG,DMA interrupt status register" rbitfld.long 0x00 15. " DMA_BUS_ERR7 ,0 = No bus error response is detected for channel 7_1 = Bus error response detected for channel 7_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.It is also noted that when the specific channel becomes secure (so when either of the PROT_AES_KEY_READ and PROT_QSPI_KEY_READ bits of SECURE_BOOT_REG is set), this bit-field is overruled to '0', masking the bus error status reporting to the user" "0,1" rbitfld.long 0x00 14. " DMA_BUS_ERR6 ,0 = No bus error response is detected for channel 6_1 = Bus error response detected for channel 6_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" rbitfld.long 0x00 13. " DMA_BUS_ERR5 ,0 = No bus error response is detected for channel 5_1 = Bus error response detected for channel 5_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" textline " " rbitfld.long 0x00 12. " DMA_BUS_ERR4 ,0 = No bus error response is detected for channel 4_1 = Bus error response detected for channel 4_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" rbitfld.long 0x00 11. " DMA_BUS_ERR3 ,0 = No bus error response is detected for channel 3_1 = Bus error response detected for channel 3_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" rbitfld.long 0x00 10. " DMA_BUS_ERR2 ,0 = No bus error response is detected for channel 2_1 = Bus error response detected for channel 2_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" textline " " rbitfld.long 0x00 9. " DMA_BUS_ERR1 ,0 = No bus error response is detected for channel 1_1 = Bus error response detected for channel 1_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" rbitfld.long 0x00 8. " DMA_BUS_ERR0 ,0 = No bus error response is detected for channel 0_1 = Bus error response detected for channel 0_NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started" "0,1" rbitfld.long 0x00 7. " DMA_IRQ_CH7 ,0 = IRQ on channel 7 is not set_1 = IRQ on channel 7 is set" "0,1" textline " " rbitfld.long 0x00 6. " DMA_IRQ_CH6 ,0 = IRQ on channel 6 is not set_1 = IRQ on channel 6 is set" "0,1" rbitfld.long 0x00 5. " DMA_IRQ_CH5 ,0 = IRQ on channel 5 is not set_1 = IRQ on channel 5 is set" "0,1" rbitfld.long 0x00 4. " DMA_IRQ_CH4 ,0 = IRQ on channel 4 is not set_1 = IRQ on channel 4 is set" "0,1" textline " " rbitfld.long 0x00 3. " DMA_IRQ_CH3 ,0 = IRQ on channel 3 is not set_1 = IRQ on channel 3 is set" "0,1" rbitfld.long 0x00 2. " DMA_IRQ_CH2 ,0 = IRQ on channel 2 is not set_1 = IRQ on channel 2 is set" "0,1" rbitfld.long 0x00 1. " DMA_IRQ_CH1 ,0 = IRQ on channel 1 is not set_1 = IRQ on channel 1 is set" "0,1" textline " " rbitfld.long 0x00 0. " DMA_IRQ_CH0 ,0 = IRQ on channel 0 is not set_1 = IRQ on channel 0 is set" "0,1" group.long 0x100++0x3 line.long 0x00 "DMA_REQ_MUX_REG,DMA channel assignments" bitfld.long 0x00 12.--15. " DMA67_SEL ,Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels._Here, the first DMA request is mapped on channel 6 and the second on channel 7._See DMA01_SEL for the peripheral mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DMA45_SEL ,Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels._Here, the first DMA request is mapped on channel 4 and the second on channel 5._See DMA01_SEL for the peripherals' mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DMA23_SEL ,Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels._Here, the first DMA request is mapped on channel 2 and the second on channel 3._See DMA01_SEL for the peripherals' mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " DMA01_SEL ,Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels._Here, the first DMA request is mapped on channel 0 and the second on channel 1._0x0: SPI_rx / SPI_tx_0x1: SPI2_rx / SPI2_tx_0x2: UART_rx / UART_tx_0x3: UART2_rx / UART2_tx_0x4: I2C_rx / I2C_tx_0x5: I2C2_rx / I2C2_tx_0x6: USB_rx / USB_tx_0x7: UART3_rx/UART3_tx_0x8: PCM_rx / PCM_tx_0x9: SRC_rx / SRC_tx (for all the supported conversions)_0xA: Reserved_0xB: Reserved_0xC: GP_ADC / -_0xD: SD_ADC / -_0xE: Reserved_0xF: None__Note: If any of the four available peripheral selector fields (DMA01_SEL, DMA23_SEL, DMA45_SEL, DMA67_SEL) have the same value, the lesser significant selector has higher priority and will control the DMA acknowledge signal driven to the selected peripheral. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will provide the Rx and Tx DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "DW" base ad:0x30020000 width 25. group.long 0x54++0x3 line.long 0x00 "AHB_DMA_CCLM1_REG,USB Master clock tokens (AHB DMA layer only)" hexmask.long.word 0x00 0.--15. 1. " AHB_DMA_CCLM ,Number of tokens (counted in AHB clock cycles) that a master can use on the bus before it has to arbitrate on a bus master with low priority and having tokens. Masters with tokens remaining have priority over masters that have used all of their tokens. User should configure all the token values ensuring that the sum does not exceeds the total allocated number of tokens. If a value of zero is configured, then the bus is deemed to have infinite tokens and will always operate in the upper-tier of arbitration" group.long 0x58++0x3 line.long 0x00 "AHB_DMA_CCLM2_REG,GenDMA Master clock tokens (AHB DMA layer only)" hexmask.long.word 0x00 0.--15. 1. " AHB_DMA_CCLM ,Refer to AHB_DMA_CCLM1_REG" group.long 0x5C++0x3 line.long 0x00 "AHB_DMA_CCLM3_REG,CRYPTO Master clock tokens (AHB DMA layer only)" hexmask.long.word 0x00 0.--15. 1. " AHB_DMA_CCLM ,AHB_DMA_CCLM1_REG" group.long 0x60++0x3 line.long 0x00 "AHB_DMA_CCLM4_REG,CRYPTO Master clock tokens (AHB DMA layer only)" hexmask.long.word 0x00 0.--15. 1. " AHB_DMA_CCLM ,AHB_DMA_CCLM1_REG" group.long 0x48++0x3 line.long 0x00 "AHB_DMA_DFLT_MASTER_REG,Default master ID number (AHB DMA layer only)" bitfld.long 0x00 0.--3. " AHB_DMA_DFLT_MASTER ,Default master ID number register. The default master is the master that is granted by the bus when no master has requested ownership._0: Dummy master_1: RFPT_2: LCD_3: GEN-DMA_3: CRYPTO-DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x0++0x3 line.long 0x00 "AHB_DMA_PL1_REG,AHB-DMA layer priority level for RFTP (AHB DMA layer only)" bitfld.long 0x00 0.--3. " AHB_DMA_PL1 ,Arbitration priority for master RFPT. 0: lowest, 15: highest" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x3 line.long 0x00 "AHB_DMA_PL2_REG,AHB-DMA layer priority level for LCD (AHB DMA layer only)" bitfld.long 0x00 0.--3. " AHB_DMA_PL2 ,Arbitration priority for master LCD. 0: lowest, 15: highest" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x3 line.long 0x00 "AHB_DMA_PL3_REG,AHB-DMA layer Priority level for GEN-DMA (AHB DMA layer only)" bitfld.long 0x00 0.--3. " AHB_DMA_PL3 ,Arbitration priority for master GEN-DMA. 0: lowest, 15: highest" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "AHB_DMA_PL4_REG,AHB-DMA layer Priority level for CRYPTO-DMA (AHB DMA layer only)" bitfld.long 0x00 0.--3. " AHB_DMA_PL4 ,Arbitration priority for master CRYPTO-DMA. 0: lowest, 15: highest" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x00 "AHB_DMA_TCL_REG,Master clock refresh period (AHB DMA layer only)" hexmask.long.word 0x00 0.--15. 1. " AHB_DMA_TCL ,Master clock refresh period, counting clock cycles. An arbitration period is defined over this number of tokens. When a new arbitration period starts, the master counters are reloaded. Recommended value is the sum of the AHB_DMA_CCLMx_REG valuesplus 2 tokens for each master, i.e. plus 6" group.long 0x90++0x3 line.long 0x00 "AHB_DMA_VERSION_REG,Version ID (AHB DMA layer only)" hexmask.long 0x00 0.--31. 1. " AHB_DMA_VERSION ," group.long 0x4C++0x3 line.long 0x00 "AHB_DMA_WTEN_REG,Weighted-Token Arbitration Scheme Enable (AHB DMA layer only)" bitfld.long 0x00 0. " AHB_DMA_WTEN ,Weighted-token arbitration scheme enable" "0,1" width 0x0B tree.end tree "GPADC" base ad:0x50030900 width 22. group.long 0x14++0x3 line.long 0x00 "GP_ADC_CLEAR_INT_REG,General Purpose ADC Clear Interrupt Register" hexmask.long.word 0x00 0.--15. 1. " GP_ADC_CLR_INT ,Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0." group.long 0x4++0x3 line.long 0x00 "GP_ADC_CTRL2_REG,General Purpose ADC Second Control Register" bitfld.long 0x00 12.--15. " GP_ADC_STORE_DEL ,0: Data is stored after handshake synchronisation_1: Data is stored two ADC_CLK cycles after internal start trigger_15: Data is stored sixteen ADC_CLK cycles after internal start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " GP_ADC_SMPL_TIME ,0: The sample time (switch is closed) is one ADC_CLK cycle_1: The sample time is 1*32 ADC_CLK cycles_2: The sample time is 2*32 ADC_CLK cycles_15: The sample time is 15*32 ADC_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--7. " GP_ADC_CONV_NRS ,0: 1 sample is taken or 2 in case ADC_CHOP is active._1: 2 samples are taken._2: 4 samples are taken._7: 128 samples are taken" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3. " GP_ADC_DMA_EN ,0: DMA functionality disabled_1: DMA functionality enabled" "0,1" bitfld.long 0x00 2. " GP_ADC_I20U ,1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC" "0,1" bitfld.long 0x00 1. " GP_ADC_IDYN ,1: Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC" "0,1" textline " " bitfld.long 0x00 0. " GP_ADC_ATTN3X ,0: Input voltages up to 1.2V allowed._1: Input voltages up to 3.6V allowed by enabling 3x attenuator. (if ADC_SEL=7 or 8, this bit is automatically set to 1) Enabling the attenuator requires a longer sampling time" "0,1" group.long 0x8++0x3 line.long 0x00 "GP_ADC_CTRL3_REG,General Purpose ADC Third Control Register" hexmask.long.byte 0x00 8.--15. 1. " GP_ADC_INTERVAL ,Defines the interval between two ADC conversions in case GP_ADC_CONT is set._0: No extra delay between two conversions._1: 1.024ms interval between two conversions._2: 2.048ms interval between two conversions._255: 261.12ms interval between two conversions" hexmask.long.byte 0x00 0.--7. 1. " GP_ADC_EN_DEL ,Defines the delay for enabling the ADC after enabling the LDO._0: Not allowed_1: 32x ADC_CLK period._n: n*32x ADC_CLK period" group.long 0x0++0x3 line.long 0x00 "GP_ADC_CTRL_REG,General Purpose ADC Control Register" bitfld.long 0x00 18. " GP_ADC_DIFF_TEMP_EN ,1: Enable the on-chip temperature sensors" "0,1" bitfld.long 0x00 16.--17. " GP_ADC_DIFF_TEMP_SEL ,0: Unused_1 to 3: Select sensor 1 to 3" "0,1,2,3" bitfld.long 0x00 15. " GP_ADC_LDO_ZERO ,1: Samples and disconnects VREF, should be refreshed frequently. Note that the LDO consumpes power when bit is set" "0,1" textline " " bitfld.long 0x00 14. " GP_ADC_CHOP ,0: Chopper mode off_1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC; Highly recommended for DC-measurements" "0,1" bitfld.long 0x00 13. " GP_ADC_SIGN ,0: Default_1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency" "0,1" bitfld.long 0x00 8.--12. " GP_ADC_SEL ,ADC input selection._If GP_ADC_SE = 1 (single ended mode):_0: P1[09]_1: P0[25]_2: P0[08]_3: P0[09]_4: VDD_HIGH_5: V33 (GP_ADC_ATTN3X scaler automatically selected)_6: V33 (GP_ADC_ATTN3X scaler automatically selected)_7: DCDC (GP_ADC_ATTN3X scaler automatically selected)_8: VBAT (5V to 1.2V scaler selected)_9: VSSA_16: P1[13]_17: P1[12]_18: P1[18]_19: P1[19]_20: Temperature sensor_All other combinations are reserved._If GP_ADC_SE = 0 (differential mode):_0: P1[09] vs P0[25]_All other combinations are P0[08] vs P0[09]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " GP_ADC_MUTE ,0: Normal operation_1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC)" "0,1" bitfld.long 0x00 6. " GP_ADC_SE ,0: Differential mode_1: Single ended mode" "0,1" bitfld.long 0x00 5. " GP_ADC_MINT ,0: Disable (mask) GP_ADC_INT._1: Enable GP_ADC_INT to ICU" "0,1" textline " " rbitfld.long 0x00 4. " GP_ADC_INT ,1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG" "0,1" bitfld.long 0x00 3. " GP_ADC_CLK_SEL ,0: Internal high-speed ADC clock used (recommended)._1: Digital clock used (ADC_CLK)" "0,1" bitfld.long 0x00 2. " GP_ADC_CONT ,0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit._1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL" "0,1" textline " " bitfld.long 0x00 1. " GP_ADC_START ,0: ADC conversion ready._1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero" "0,1" bitfld.long 0x00 0. " GP_ADC_EN ,0: LDO is off and ADC is disabled.._1: LDO is turned on and afterwards the ADC is enabled" "0,1" group.long 0x10++0x3 line.long 0x00 "GP_ADC_OFFN_REG,General Purpose ADC Negative Offset Register" hexmask.long.word 0x00 0.--9. 1. " GP_ADC_OFFN ,Offset adjust of 'negative' array of ADC-network (effective if _GP_ADC_SE=0_, or _GP_ADC_SE=1 AND GP_ADC_SIGN=1_)" group.long 0xC++0x3 line.long 0x00 "GP_ADC_OFFP_REG,General Purpose ADC Positive Offset Register" hexmask.long.word 0x00 0.--9. 1. " GP_ADC_OFFP ,Offset adjust of 'positive' array of ADC-network (effective if _GP_ADC_SE=0_, or _GP_ADC_SE=1 AND GP_ADC_SIGN=0_)" group.long 0x18++0x3 line.long 0x00 "GP_ADC_RESULT_REG,General Purpose ADC Result Register" hexmask.long.word 0x00 0.--15. 1. " GP_ADC_VAL ,Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits" width 0x0B tree.end tree "GPIO" base ad:0x50020A00 width 21. group.long 0x104++0x3 line.long 0x00 "BIST_CTRL_REG,Memory BIST Control Register" bitfld.long 0x00 6. " SYSRAMBIST_ENABLE ,Enable Memory Build In Self Test of all RAMs._Control of the MBIST is by means of a JTAG interface._0: mission mode._1: MBIST pinmapping:_GPIO_P0_24: JTAG_TRST_GPIO_P0_25: JTAG_TCK_GPIO_P0_26: JTAG_TMS_GPIO_P0_27: JTAG_TDI_GPIO_P0_28: MBIST_ON_GPIO_P0_29: MBIST_GO_GPIO_P0_30: MBIST_DONE_GPIO_P0_31: JTAG_TDO" "0,1" bitfld.long 0x00 4. " ROMBIST_ENABLE ,Enable the ROM bist" "0,1" bitfld.long 0x00 0.--1. " ROMBIST_CONFIG ,Bist configuration for ROMBIST:_00 = Perform all 2 phases_01 = Perform only phase 1_10 = Perform only phase 2_11 = Reserved" "0,1,2,3" group.long 0xFC++0x3 line.long 0x00 "GPIO_CLK_SEL_REG,Select which clock to map on ports P0/P1" bitfld.long 0x00 9. " DIVN_OUTPUT_EN ,DIVN output enable bit-field. When set, it enables the mapping of DIVN clock on dedicated GPIO (P0_15). The specific GPIO must be configured as GPIO output" "0,1" bitfld.long 0x00 8. " RC32M_OUTPUT_EN ,RC32M output enable bit-field. When set, it enables the mapping of RC32M clock on dedicated GPIO (P0_13). The specific GPIO must be configured as GPIO output" "0,1" bitfld.long 0x00 7. " XTAL32M_OUTPUT_EN ,XTALK32M output enable bit-field. When set, it enables the mapping of XTAL32M clock on dedicated GPIO (P0_12). The specific GPIO must be configured as GPIO output" "0,1" textline " " bitfld.long 0x00 6. " RCX_OUTPUT_EN ,RCX output enable bit-field. When set, it enables the mapping of RCX clock on dedicated GPIO (P0_16). The specific GPIO must be configured as GPIO output" "0,1" bitfld.long 0x00 5. " RC32K_OUTPUT_EN ,RC32K output enable bit-field. When set, it enables the mapping of RC32K clock on dedicated GPIO (P0_17). The specific GPIO must be configured as GPIO output" "0,1" bitfld.long 0x00 4. " XTAL32K_OUTPUT_EN ,XTALK32K output enable bit-field. When set, it enables the mapping of XTAL32K clock on dedicated GPIO (P0_14).The specific GPIO must be configured as GPIO output" "0,1" textline " " bitfld.long 0x00 3. " FUNC_CLOCK_EN ,If set, it enables the mapping of the selected clock signal, according to FUNC_CLOCK_SEL bit-field" "0,1" bitfld.long 0x00 0.--2. " FUNC_CLOCK_SEL ,Select which clock to map when PID = FUNC_CLOCK._0x0: XTAL32K_0x1: RC32K_0x2: RCX_0x3: XTAL32M_0x4: RC32M_0x5: DIVN_0x6: Reserved_0x7: Reserved" "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x00 "P0_00_MODE_REG,P0_00 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,Function of port:_0: GPIO (see also the PUPD bit-field)_1: UART_RX_2: UART_TX_3: UART2_RX_4: UART2_TX_5: UART2_CTSN_6: UART2_RTSN_7: UART3_RX_8: UART3_TX_9: UART3_CTSN_10: UART3_RTSN_11: ISO_CLK_12: ISO_DATA_13: SPI_DI_14: SPI_DO_15: SPI_CLK16: SPI_EN_17: SPI2_DI_18: SPI2_DO_19: SPI2_CLK_20: SPI2_EN_21: I2C_SCL_22: I2C_SDA_23: I2C2_SCL_24: I2C2_SDA_25: USB_SOF_26: ADC (dedicated pins)_27: USB (dedicated pins)_28: PCM_DI_29: PCM_DO_30: PCM_FSC_31: PCM_CLK_32: PDM_DATA_33: PDM_CLK_34: COEX_EXT_ACT0_35: COEX_SMART_ACT_36: COEX_SMART_PRI_37: PORT0_DCF_38: PORT1_DCF_39: PORT2_DCF_40: PORT3_DCF_41: PORT4_DCF_42: CLOCK (dedicated pins, see also GPIO_CLK_SEL_REG)_43: PG (dedicated pins)_44: LCD (dedicated pins)_45: LCD_SPI_DC_46: LCD_SPI_DO_47: LCD_SPI_CLK_48: LCD_SPI_EN_49: TIM_PWM_50: TIM2_PWM_51: TIM_1SHOT_52: TIM2_1SHOT_53: TIM3_PWM_54: TIM4_PWM_55: Reserved_56: CMAC_DIAG0_57: CMAC_DIAG1_58: CMAC_DIAG2_59: CMAC_DIAGX (dedicated pins)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "P0_01_MODE_REG,P0_01 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x3 line.long 0x00 "P0_02_MODE_REG,P0_02 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x24++0x3 line.long 0x00 "P0_03_MODE_REG,P0_03 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x28++0x3 line.long 0x00 "P0_04_MODE_REG,P0_04 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x3 line.long 0x00 "P0_05_MODE_REG,P0_05 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "P0_06_MODE_REG,P0_06 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x34++0x3 line.long 0x00 "P0_07_MODE_REG,P0_07 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x3 line.long 0x00 "P0_08_MODE_REG,P0_08 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x3C++0x3 line.long 0x00 "P0_09_MODE_REG,P0_09 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x3 line.long 0x00 "P0_10_MODE_REG,P0_10 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "P0_11_MODE_REG,P0_11 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x3 line.long 0x00 "P0_12_MODE_REG,P0_12 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4C++0x3 line.long 0x00 "P0_13_MODE_REG,P0_13 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x3 line.long 0x00 "P0_14_MODE_REG,P0_14 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x3 line.long 0x00 "P0_15_MODE_REG,P0_15 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x58++0x3 line.long 0x00 "P0_16_MODE_REG,P0_16 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x5C++0x3 line.long 0x00 "P0_17_MODE_REG,P0_17 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x3 line.long 0x00 "P0_18_MODE_REG,P0_18 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x3 line.long 0x00 "P0_19_MODE_REG,P0_19 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x68++0x3 line.long 0x00 "P0_20_MODE_REG,P0_20 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x6C++0x3 line.long 0x00 "P0_21_MODE_REG,P0_21 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x70++0x3 line.long 0x00 "P0_22_MODE_REG,P0_22 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x74++0x3 line.long 0x00 "P0_23_MODE_REG,P0_23 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x78++0x3 line.long 0x00 "P0_24_MODE_REG,P0_24 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x7C++0x3 line.long 0x00 "P0_25_MODE_REG,P0_25 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x80++0x3 line.long 0x00 "P0_26_MODE_REG,P0_26 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84++0x3 line.long 0x00 "P0_27_MODE_REG,P0_27 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88++0x3 line.long 0x00 "P0_28_MODE_REG,P0_28 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x3 line.long 0x00 "P0_29_MODE_REG,P0_29 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x90++0x3 line.long 0x00 "P0_30_MODE_REG,P0_30 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x94++0x3 line.long 0x00 "P0_31_MODE_REG,P0_31 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x0++0x3 line.long 0x00 "P0_DATA_REG,P0 Data input / output Register" hexmask.long 0x00 0.--31. 1. " P0_DATA ,Set P0 output register when written; Returns the value of P0 port when read" group.long 0xF4++0x3 line.long 0x00 "P0_PADPWR_CTRL_REG,P0 Output Power Control Register" hexmask.long 0x00 6.--31. 1. " P0_OUT_CTRL ,0 = P0_x port output is powered by the V30 rail (default)_1 = P0_x port output is powered by the 1V8P rail_bit x controls the power supply of P0[x]" group.long 0x10++0x3 line.long 0x00 "P0_RESET_DATA_REG,P0 Reset port pins Register" hexmask.long 0x00 0.--31. 1. " P0_RESET ,Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded;_Reading returns 0" group.long 0x8++0x3 line.long 0x00 "P0_SET_DATA_REG,P0 Set port pins Register" hexmask.long 0x00 0.--31. 1. " P0_SET ,Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded;_Reading returns 0" group.long 0x98++0x3 line.long 0x00 "P1_00_MODE_REG,P1_00 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x9C++0x3 line.long 0x00 "P1_01_MODE_REG,P1_01 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA0++0x3 line.long 0x00 "P1_02_MODE_REG,P1_02 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA4++0x3 line.long 0x00 "P1_03_MODE_REG,P1_03 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x3 line.long 0x00 "P1_04_MODE_REG,P1_04 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x3 line.long 0x00 "P1_05_MODE_REG,P1_05 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB0++0x3 line.long 0x00 "P1_06_MODE_REG,P1_06 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB4++0x3 line.long 0x00 "P1_07_MODE_REG,P1_07 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x3 line.long 0x00 "P1_08_MODE_REG,P1_08 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x3 line.long 0x00 "P1_09_MODE_REG,P1_09 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x3 line.long 0x00 "P1_10_MODE_REG,P1_10 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC4++0x3 line.long 0x00 "P1_11_MODE_REG,P1_11 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("DA14691-CM33")&&!cpuis("DA14695-CM33") group.long 0xC8++0x3 line.long 0x00 "P1_12_MODE_REG,P1_12 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xCC++0x3 line.long 0x00 "P1_13_MODE_REG,P1_13 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD0++0x3 line.long 0x00 "P1_14_MODE_REG,P1_14 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD4++0x3 line.long 0x00 "P1_15_MODE_REG,P1_15 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x3 line.long 0x00 "P1_16_MODE_REG,P1_16 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xDC++0x3 line.long 0x00 "P1_17_MODE_REG,P1_17 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE0++0x3 line.long 0x00 "P1_18_MODE_REG,P1_18 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE4++0x3 line.long 0x00 "P1_19_MODE_REG,P1_19 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x3 line.long 0x00 "P1_20_MODE_REG,P1_20 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xEC++0x3 line.long 0x00 "P1_21_MODE_REG,P1_21 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF0++0x3 line.long 0x00 "P1_22_MODE_REG,P1_22 Mode Register" bitfld.long 0x00 10. " PPOD ,0: Push pull_1: Open drain" "0,1" bitfld.long 0x00 8.--9. " PUPD ,00 = Input, no resistors selected_01 = Input, pull-up selected_10 = Input, pull-down selected_11 = Output, no resistors selected_In ADC mode, these bits are don't care" "0,1,2,3" bitfld.long 0x00 0.--5. " PID ,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x4++0x3 line.long 0x00 "P1_DATA_REG,P1 Data input / output Register" hexmask.long.tbyte 0x00 0.--22. 1. " P1_DATA ,Set P1 output register when written; Returns the value of P1 port when read" group.long 0xF8++0x3 line.long 0x00 "P1_PADPWR_CTRL_REG,P1 Output Power Control Register" hexmask.long.tbyte 0x00 0.--22. 1. " P1_OUT_CTRL ,0 = P1_x port output is powered by the V30 rail (default)_1 = P1_x port output is powered by the 1V8P rail_bit x controls the power supply of P1[x]" group.long 0x14++0x3 line.long 0x00 "P1_RESET_DATA_REG,P1 Reset port pins Register" hexmask.long.tbyte 0x00 0.--22. 1. " P1_RESET ,Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded;_Reading returns 0" group.long 0xC++0x3 line.long 0x00 "P1_SET_DATA_REG,P1 Set port pins Register" hexmask.long.tbyte 0x00 0.--22. 1. " P1_SET ,Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded;_Reading returns 0" group.long 0x100++0x3 line.long 0x00 "PAD_WEAK_CTRL_REG,Weak Pads Control Register" bitfld.long 0x00 12. " P1_09_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P1_09 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 11. " P1_06_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P1_06 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 10. " P1_02_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P1_02 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG)" "0,1" textline " " bitfld.long 0x00 9. " P1_01_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P1_01 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 8. " P1_00_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P1_00 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 7. " P0_27_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_27 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" textline " " bitfld.long 0x00 6. " P0_26_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_26 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 5. " P0_25_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_25 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 4. " P0_18_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_18 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" textline " " bitfld.long 0x00 3. " P0_17_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_17 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 2. " P0_16_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_16 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" bitfld.long 0x00 1. " P0_07_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_07 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" textline " " bitfld.long 0x00 0. " P0_06_LOWDRV ,0 = Normal operation_1 = Reduces the driving strength of P0_06 pad_Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG)" "0,1" group.long 0x108++0x3 line.long 0x00 "RAMBIST_STATUS1_REG,RAM BIST Status Register" rbitfld.long 0x00 15. " ROM_BIST_BUSY ,status of internal signal _busy_ of rom bist" "0,1" group.long 0x10C++0x3 line.long 0x00 "RAMBIST_STATUS2_REG,RAM BIST Status Register 2" group.long 0x110++0x3 line.long 0x00 "RAMBIST_STATUS3_REG,RAM BIST Status Register 3" group.long 0x118++0x3 line.long 0x00 "ROMBIST_RESULTH_REG,ROM BIST Status Register - 16 MSBs" hexmask.long.word 0x00 0.--15. 1. " ROMBIST_RESULTH ,Read version of bist status, result[31:16]" group.long 0x114++0x3 line.long 0x00 "ROMBIST_RESULTL_REG,ROM BIST Status Register - 16 LSBs" hexmask.long.word 0x00 0.--15. 1. " ROMBIST_RESULTL ,Read version of bist status, result[15:0]" group.long 0x120++0x3 line.long 0x00 "TEST_CTRL2_REG,Test Control Register 2" bitfld.long 0x00 8.--9. " RF_IN_TESTMUX_CTRL ,Connect the RF input testbus to pins:_Switch 1 (bit 8) connects T0 of the radio test input bus to pin P1_6_Switch 2 (bit 9) connects T1 of the radio test input bus to pin P1_9_If this bit is 0, the switch is open (not conducting)" "0,1,2,3" bitfld.long 0x00 0.--3. " ANA_TESTMUX_CTRL ,Control of analog test bus switches:_Switch 1 connects T0 of the radio test output bus to P1_10_Switch 2 connects T1 of the radio test output bus to P1_7_Switch 3 connects T0 of the analog test output bus to P1_10_Switch 4 connects T1 of the analog test output bus to P1_7__0: all switches open_1: only switch 1 closed_2: only switch 2 closed_3: only switch 3 closed_4: only switch 4 closed_5: switches 1 & 2 closed_6: switches 1 & 4 closed_7: switches 2 & 3 closed_8: switches 3 & 4 closed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x3 line.long 0x00 "TEST_CTRL3_REG,Test Control Register 3" hexmask.long.byte 0x00 8.--15. 1. " RF_TEST_OUT_PARAM ,Select which test will be enabled on the block selected by the RF output testbus (see" bitfld.long 0x00 6. " VBUS_COMPARATOR_TEST ,Control for the testability of VBUS input on V33 comparator" "0,1" bitfld.long 0x00 0.--5. " RF_TEST_OUT_SEL ,Select a radio block to have its testbus connected to P1[1] and P1[2]. See_Table 7_for more information._NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x128++0x3 line.long 0x00 "TEST_CTRL4_REG,Test Control Register 4" hexmask.long.byte 0x00 8.--15. 1. " RF_TEST_IN_PARAM ,Select which test will be enabled on the block selected by the RF output testbus (see" bitfld.long 0x00 0.--2. " RF_TEST_IN_SEL ,Select an RF block to have its test input connected to the input testbus at pins P0[0] and P0[3]. NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses." "0,1,2,3,4,5,6,7" group.long 0x12C++0x3 line.long 0x00 "TEST_CTRL5_REG,Test Control Register 5" bitfld.long 0x00 31. " LDO_RET_FORCE_HOLD ," "0,1" bitfld.long 0x00 30. " POR_VBAT_FORCE_ON ," "0,1" bitfld.long 0x00 29. " POR_VBAT_FORCE_OFF ," "0,1" textline " " bitfld.long 0x00 28. " POR_VBAT_FORCE_MASK ," "0,1" bitfld.long 0x00 26. " TEST_VCAP_PRECHARGE ," "0,1" bitfld.long 0x00 25. " LDO_CORE_BOOST_VDD ," "0,1" textline " " bitfld.long 0x00 24. " BGR_BOOST_VREF ," "0,1" bitfld.long 0x00 20.--23. " TEST_BANDGAP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " TEST_BANDGAP_I_TEST ," "0,1" textline " " bitfld.long 0x00 18. " TEST_PLL ," "0,1" bitfld.long 0x00 17. " TEST_LRA_ADC ," "0,1" bitfld.long 0x00 16. " TEST_POR_VBAT ," "0,1" textline " " bitfld.long 0x00 15. " TEST_FORCE_RUNNING ," "0,1" bitfld.long 0x00 14. " TEST_DIFFTEMP ," "0,1" bitfld.long 0x00 13. " TEST_VCONT ," "0,1" textline " " bitfld.long 0x00 12. " TEST_SIMO_BUCK ," "0,1" bitfld.long 0x00 11. " TEST_VDDX_ADPLL ," "0,1" bitfld.long 0x00 10. " TEST_VDDX_RCX ," "0,1" textline " " bitfld.long 0x00 9. " TEST_VDDX_OSC32M ," "0,1" bitfld.long 0x00 8. " TEST_VDDD_NOTSLEEP ," "0,1" bitfld.long 0x00 7. " TEST_LDO_VDDHIGH ," "0,1" textline " " bitfld.long 0x00 6. " TEST_LDO_PLL ," "0,1" bitfld.long 0x00 5. " TEST_LDO_ADC ," "0,1" bitfld.long 0x00 4. " TEST_LDO_1V8P ," "0,1" textline " " bitfld.long 0x00 3. " TEST_LDO_CORE ," "0,1" bitfld.long 0x00 2. " TEST_LDO_1V8 ," "0,1" bitfld.long 0x00 1. " TEST_LDO_1V4 ," "0,1" textline " " bitfld.long 0x00 0. " TEST_BUS_TO_AVS ," "0,1" group.long 0x11C++0x3 line.long 0x00 "TEST_CTRL_REG,Test Control Register" bitfld.long 0x00 17.--22. " PM_MON_CTRL ,PM control bus ([7:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16. " LED1_PWM_DISABLE ,Disable PWM on LED1 driver, dutycycle LED1=100%" "0,1" bitfld.long 0x00 15. " LED0_PWM_DISABLE ,Disable PWM on LED0 driver, dutycycle LED0=100%" "0,1" textline " " bitfld.long 0x00 14. " XTAL32M_TRIM_TEST_EN ,0: normal port function, 1: shows xtal32m_trim_sw2_isolated onto pin P1_6" "0,1" bitfld.long 0x00 12. " SDADC_TEST_OUT_EN ,0: Normal operation, 1: Maps the Sigma-Delta ADC bitstream signal onto the P1_8 pin" "0,1" bitfld.long 0x00 11. " RADIO_ONLY_MODE_EN ,0: Normal operation,_1: Enables the Exposed Radio mode (Radio-only mode)" "0,1" textline " " bitfld.long 0x00 8.--10. " SHOW_PWR_TST_OUT ,0: Normal operation_1: P1[7:1] = ldo_1v8_flash_ret_enable, ldo_supply_vbat_ok, ldo_supply_usb_ok, ldo_1v8_pa_ret_enable, bandgap_bgr_ok, 0, ldo_vbat_ret_enable_2: P1[7:1] = ldo_vbat_ret_vref_hold, ldo_core_ok, pll_status_reg_isolated_1, ldo_radio_ok,ldo_1v8_pa_ok, ldo_1v8_flash_ok, ldo_supply_usb_enable_3: P1[7:1] = ldo_1v8_flash_ret_vref_hold, vbus_available, newbat, clear_newbat, ldo_1v8_pa_ret_vref_hold, 0, power_on_reset_4: P1[7:1] = comp_v18_pa_high, comp_v18_flash_high, comp_vdd_high, comp_vbus_low, comp_vbus_high, comp_v33_high, comp_vbat_ok_5: P1[7:1] = charge_gate_enable, bod_v18_pa_low, bod_v33_low, bod_v18_flash_low, bod_vdd_low, bod_vbat_low, bod_clk" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. " PM_MON_EN ,0: Normal operation_1: Shows the PM_MON[3:0] bus on pins P0[25:22]" "0,1" bitfld.long 0x00 6. " ADPLL_SCAN_TEST_EN ,0: Normal operation_1: Enables the ADPLL scan test signal, activating the respective scan mode" "0,1" textline " " bitfld.long 0x00 5. " SHOW_IF_RO ,0: Normal Port function._1: Show IF filter Reference Oscillator I and Q signals._P10 = iff_ro_out_i_P06 = iff_ro_out_q" "0,1" bitfld.long 0x00 4. " XTAL32M_CAP_TEST_EN ,0: Normal Port function._1: Shows xtal16m_cap_test_out output onto pins P1[3:2]_Notes:_- The control signal should go to the radio to enable this test mode._- This register should be zero during scan test!" "0,1" bitfld.long 0x00 3. " SHOW_DCDC_TESTBUS ,0: normal port function_1: map the DCDC testbus [11:0] on the following GPIO's (MSB first): P23,P21,P20,P1[7:0],P07" "0,1" textline " " bitfld.long 0x00 2. " SHOW_PLL_TEST_OUT ,0: normal port function_1: map pll_out_div_test_out on P06 and pll_loop_div_test_out on P10" "0,1" bitfld.long 0x00 1. " ENABLE_RFPT ,0: normal port function_1: enable the RF Production Test Unit. Used to store RX ADC samples or PLL TDC samples in SRAM._See RFPT_CTRL_REG, RFPT_ADDR_REG and RFPT_LEN_REG for details." "0,1" bitfld.long 0x00 0. " SHOW_CLOCKS ,0: normal port function_1: show DIVN clock on P10" "0,1" width 0x0B tree.end tree "GPREG" base ad:0x50040300 width 18. group.long 0x8++0x3 line.long 0x00 "DEBUG_REG,Various debug information register" bitfld.long 0x00 8. " CROSS_CPU_HALT_SENSITIVITY ,Select the cross CPU halt sensitivity._0: Level triggered,_1: Pulse triggered._Note: This bit is retained" "0,1" bitfld.long 0x00 7. " SYS_CPUWAIT_ON_JTAG ,1: Stall the processor core out of reset (only after a wake-up from JTAG). Debugger access continue when the core is stalled. When set to '0' again the core resumes instruction execution._This feature is independent of the PDC (Power Domain Controller) settings. If this bit is set and there is SW/JTAG activity during deep sleep, the SYS CPU is stalled after the wake-up._Note: This bit is retained" "0,1" bitfld.long 0x00 6. " SYS_CPUWAIT ,1: Stall the processor core out of reset (always after a wake-up). Debugger access continue when the core is stalled. When set to '0' again the core resumes instruction execution._Note: This bit is retained" "0,1" textline " " rbitfld.long 0x00 5. " CMAC_CPU_IS_HALTED ,1: CMAC CPU is halted" "0,1" rbitfld.long 0x00 4. " SYS_CPU_IS_HALTED ,1: SYS CPU (ARM CM33) is halted" "0,1" bitfld.long 0x00 3. " HALT_CMAC_SYS_CPU_EN ,1: Enable CMAC CPU halting to the SYS CPU (ARM CM33)._Note: This bit is retained" "0,1" textline " " bitfld.long 0x00 2. " HALT_SYS_CMAC_CPU_EN ,1: Enable SYS CPU (ARM CM33) halting to the CMAC CPU._Note: This bit is retained" "0,1" bitfld.long 0x00 1. " CMAC_CPU_FREEZE_EN ,1: Enable Freezing peripherals by the CMAC CPU._Note: This bit is retained" "0,1" bitfld.long 0x00 0. " SYS_CPU_FREEZE_EN ,1: Enable Freezing peripherals by the SYS CPU (ARM CM33)._Default '1', freezing of the on-chip timers is enabled when the Cortex-M33 is halted in DEBUG State._If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M33 is halted in DEBUG State except the system watchdog timer. The system watchdog timer is always frozen when the Cortex-M33 is halted in DEBUG State._Note: This bit is retained" "0,1" group.long 0x10++0x3 line.long 0x00 "GP_CONTROL_REG,General purpose system control register" bitfld.long 0x00 1. " CMAC_H2H_BRIDGE_BYPASS ,If '1', the AHB-to-AHB bridge is bypassed, reducing the wait cycles needed to access the CMAC Register File, only when the system clock source is the XTAL and both hclk and cmac_hclk are running at 32 MHz, i.e. at the XTAL clock rate" "0,1" group.long 0xC++0x3 line.long 0x00 "GP_STATUS_REG,General purpose system status register" bitfld.long 0x00 0. " CAL_PHASE ,If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured." "0,1" group.long 0x4++0x3 line.long 0x00 "RESET_FREEZE_REG,Controls unfreezing of various timers/counters (incl. DMA and USB)" bitfld.long 0x00 10. " FRZ_CMAC_WDOG ,If '1', the CMAC SW Watchdog Timer continues, '0' is discarded." "0,1" bitfld.long 0x00 9. " FRZ_SWTIM4 ,If '1', the SW Timer4 continues, '0' is discarded." "0,1" bitfld.long 0x00 8. " FRZ_SWTIM3 ,If '1', the SW Timer3 continues, '0' is discarded." "0,1" textline " " bitfld.long 0x00 7. " FRZ_PWMLED ,If '1', the PWM LED continues, '0' is discarded." "0,1" bitfld.long 0x00 6. " FRZ_SWTIM2 ,If '1', the SW Timer2 continues, '0' is discarded." "0,1" bitfld.long 0x00 5. " FRZ_DMA ,If '1', the DMA continues, '0' is discarded." "0,1" textline " " bitfld.long 0x00 4. " FRZ_USB ,If '1', the USB continues, '0' is discarded." "0,1" bitfld.long 0x00 3. " FRZ_SYS_WDOG ,If '1', the SYS SW Watchdog Timer continues, '0' is discarded." "0,1" bitfld.long 0x00 2. " FRZ_RESERVED ," "0,1" textline " " bitfld.long 0x00 1. " FRZ_SWTIM ,If '1', the SW Timer continues, '0' is discarded." "0,1" bitfld.long 0x00 0. " FRZ_WKUPTIM ,If '1', the Wake Up Timer continues, '0' is discarded." "0,1" group.long 0x0++0x3 line.long 0x00 "SET_FREEZE_REG,Controls freezing of various timers/counters (incl. DMA and USB)" bitfld.long 0x00 10. " FRZ_CMAC_WDOG ,If '1', the CMAC SW Watchdog Timer is frozen, '0' is discarded." "0,1" bitfld.long 0x00 9. " FRZ_SWTIM4 ,If '1', the SW Timer4 is frozen, '0' is discarded." "0,1" bitfld.long 0x00 8. " FRZ_SWTIM3 ,If '1', the SW Timer3 is frozen, '0' is discarded." "0,1" textline " " bitfld.long 0x00 7. " FRZ_PWMLED ,If '1', the PWM LED is frozen, '0' is discarded." "0,1" bitfld.long 0x00 6. " FRZ_SWTIM2 ,If '1', the SW Timer2 is frozen, '0' is discarded." "0,1" bitfld.long 0x00 5. " FRZ_DMA ,If '1', the DMA is frozen, '0' is discarded." "0,1" textline " " bitfld.long 0x00 4. " FRZ_USB ,If '1', the USB is frozen, '0' is discarded." "0,1" bitfld.long 0x00 3. " FRZ_SYS_WDOG ,If '1', the SYS SW Watchdog Timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function." "0,1" bitfld.long 0x00 2. " FRZ_RESERVED ," "0,1" textline " " bitfld.long 0x00 1. " FRZ_SWTIM ,If '1', the SW Timer is frozen, '0' is discarded." "0,1" bitfld.long 0x00 0. " FRZ_WKUPTIM ,If '1', the Wake Up Timer is frozen, '0' is discarded." "0,1" group.long 0x18++0x3 line.long 0x00 "USBPAD_REG,USB pads control register" bitfld.long 0x00 2. " USBPHY_FORCE_SW2_ON ,0: Pull up resistor SW2 is controlled by the USB controller. It is off when the USB is not enabled._1: Force the pull up resistor on USBP to be 2.3Kohm" "0,1" bitfld.long 0x00 1. " USBPHY_FORCE_SW1_OFF ,0: Pull up resistor SW1 is controlled by the USB controller. It is off when the USB is not enabled._1: Force the pull up resistor on USBP to be switched off" "0,1" bitfld.long 0x00 0. " USBPAD_EN ,0: The power for the USB PHY and USB pads is switched on when the USB is enabled._1: The power for the USB PHY and USB pads is forced on" "0,1" width 0x0B tree.end tree "I2C" base ad:0x50020600 width 26. group.long 0x98++0x3 line.long 0x00 "I2C_ACK_GENERAL_CALL_REG,I2C ACK General Call Register" bitfld.long 0x00 0. " ACK_GEN_CALL ,ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts._1 = Generate ACK for a General Call_0 = Generate NACK for General Call" "0,1" group.long 0x5C++0x3 line.long 0x00 "I2C_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register" rbitfld.long 0x00 0. " CLR_ACTIVITY ,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register" "0,1" group.long 0x68++0x3 line.long 0x00 "I2C_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register" rbitfld.long 0x00 0. " CLR_GEN_CALL ,Read this register to clear the GEN_CALL interrupt (bit 11) of_I2C_RAW_INTR_STAT register." "0,1" group.long 0x40++0x3 line.long 0x00 "I2C_CLR_INTR_REG,Clear Combined and Individual Interrupt Register" rbitfld.long 0x00 0. " CLR_INTR ,Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE" "0,1" group.long 0x50++0x3 line.long 0x00 "I2C_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register" rbitfld.long 0x00 0. " CLR_RD_REQ ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register." "0,1" group.long 0x58++0x3 line.long 0x00 "I2C_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_DONE ,Read this register to clear the RX_DONE interrupt (bit 7) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x48++0x3 line.long 0x00 "I2C_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_OVER ,Read this register to clear the RX_OVER interrupt (bit 1) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x44++0x3 line.long 0x00 "I2C_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_UNDER ,Read this register to clear the RX_UNDER interrupt (bit 0) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x64++0x3 line.long 0x00 "I2C_CLR_START_DET_REG,Clear START_DET Interrupt Register" rbitfld.long 0x00 0. " CLR_START_DET ,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register." "0,1" group.long 0x60++0x3 line.long 0x00 "I2C_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register" rbitfld.long 0x00 0. " CLR_ACTIVITY ,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register." "0,1" group.long 0x54++0x3 line.long 0x00 "I2C_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register" rbitfld.long 0x00 0. " CLR_TX_ABRT ,Read this register to clear the TX_ABRT interrupt (bit 6) of the_IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE." "0,1" group.long 0x4C++0x3 line.long 0x00 "I2C_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register" rbitfld.long 0x00 0. " CLR_TX_OVER ,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register." "0,1" group.long 0xF4++0x3 line.long 0x00 "I2C_COMP_PARAM1_REG,Component Parameter Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_PARAM1 ,This is a constant read-only register that contains encoded information about the component's parameter settings" group.long 0xFC++0x3 line.long 0x00 "I2C_COMP_TYPE_REG,I2C Component Type Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_TYPE ," group.long 0xF8++0x3 line.long 0x00 "I2C_COMP_VERSION_REG,I2C Component Version Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_VERSION ," group.long 0x0++0x3 line.long 0x00 "I2C_CON_REG,I2C Control Register" rbitfld.long 0x00 10. " I2C_STOP_DET_IF_MASTER_ACTIVE ,In Master mode:_1 = issues the STOP_DET interrupt only when master is active._0 = issues the STOP_DET irrespective of whether master is active or not." "0,1" bitfld.long 0x00 9. " I2C_RX_FIFO_FULL_HLD_CTRL ,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH_1 = Hold bus when RX_FIFO is full_0 = Overflow when RX_FIFO is full" "0,1" bitfld.long 0x00 8. " I2C_TX_EMPTY_CTRL ,This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register._1 = Controlled generation of TX_EMPTY interrupt_0 = Default behaviour of TX_EMPTY interrupt" "0,1" textline " " bitfld.long 0x00 7. " I2C_STOP_DET_IFADDRESSED ,1 = slave issues STOP_DET intr only if addressed_0 = slave issues STOP_DET intr always_During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)" "0,1" bitfld.long 0x00 6. " I2C_SLAVE_DISABLE ,Slave enabled or disabled after reset is applied, which means software does not have to configure the slave._0=slave is enabled_1=slave is disabled_Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'." "0,1" bitfld.long 0x00 5. " I2C_RESTART_EN ,Determines whether RESTART conditions may be sent when acting as a master_0= disable_1=enable" "0,1" textline " " bitfld.long 0x00 4. " I2C_10BITADDR_MASTER ,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master._0= 7-bit addressing_1= 10-bit addressing" "0,1" bitfld.long 0x00 3. " I2C_10BITADDR_SLAVE ,When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses._0= 7-bit addressing_1= 10-bit addressing" "0,1" bitfld.long 0x00 1.--2. " I2C_SPEED ,These bits control at which speed the controller operates._1= standard mode (100 kbit/s)_2= fast mode (400 kbit/s)_3= high speed mode" "0,1,2,3" textline " " bitfld.long 0x00 0. " I2C_MASTER_MODE ,This bit controls whether the controller master is enabled._0= master disabled_1= master enabled_Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'." "0,1" group.long 0x10++0x3 line.long 0x00 "I2C_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register" bitfld.long 0x00 10. " I2C_RESTART ,This bit controls whether a RESTART is issued before the byte is sent or received. _1 = If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead._0 = If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead" "0,1" bitfld.long 0x00 9. " I2C_STOP ,This bit controls whether a STOP is issued after the byte is sent or received._1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus._0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO." "0,1" bitfld.long 0x00 8. " I2C_CMD ,This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master._1 = Read_0 = Write_When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a _don't care_ because writes to this register are not required. In slave-transmitter mode, a _0_ indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared._If a _1_ is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs._NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " I2C_DAT ,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface." group.long 0x88++0x3 line.long 0x00 "I2C_DMA_CR_REG,DMA Control Register" bitfld.long 0x00 1. " TDMAE ,Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel._0 = Transmit DMA disabled_1 = Transmit DMA enabled" "0,1" bitfld.long 0x00 0. " RDMAE ,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel._0 = Receive DMA disabled_1 = Receive DMA enabled" "0,1" group.long 0x90++0x3 line.long 0x00 "I2C_DMA_RDLR_REG,I2C Receive Data Level Register" bitfld.long 0x00 0.--4. " DMARDL ,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x3 line.long 0x00 "I2C_DMA_TDLR_REG,DMA Transmit Data Level Register" bitfld.long 0x00 0.--4. " DMATDL ,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6C++0x3 line.long 0x00 "I2C_ENABLE_REG,I2C Enable Register" bitfld.long 0x00 2. " I2C_TX_CMD_BLOCK ,In Master mode:_1 = Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit._0.= The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO." "0,1" bitfld.long 0x00 1. " I2C_ABORT ,The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation." "0,1" bitfld.long 0x00 0. " I2C_EN ,Controls whether the controller is enabled._0 = Disables the controller (TX and RX FIFOs are held in an erased state)_1 = Enables the controller_Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs:_* The TX FIFO and RX FIFO get flushed._* Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state._If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer._There is a two ic_clk delay when enabling or disabling the controller" "0,1" group.long 0x9C++0x3 line.long 0x00 "I2C_ENABLE_STATUS_REG,I2C Enable Status Register" rbitfld.long 0x00 2. " SLV_RX_DATA_LOST ,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer._NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0._1 = Slave RX Data is lost_0 = Slave RX Data is not lost" "0,1" rbitfld.long 0x00 1. " SLV_DISABLED_WHILE_BUSY ,Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:_(a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master; OR,_(b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect._NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1._When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle._NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0._1 =Slave is disabled when it is active_0 =Slave is disabled when it is idle" "0,1" rbitfld.long 0x00 0. " IC_EN ,ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state._When read as 0, the controller is deemed completely inactive._NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1)._1 = I2C enabled_0 =I2C disabled" "0,1" group.long 0x1C++0x3 line.long 0x00 "I2C_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_FS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set." group.long 0x20++0x3 line.long 0x00 "I2C_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_FS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed." group.long 0xC++0x3 line.long 0x00 "I2C_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register" bitfld.long 0x00 0.--2. " I2C_IC_HS_MAR ,This bit field holds the value of the I2C HS mode master code. HS-mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code; up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect" "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "I2C_HS_SCL_HCNT_REG,High Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_HS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high period count for high speed.refer to _IC_CLK Frequency Configuration_._The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time is 60ns; for 400pF loading, the SCL High time is 120ns. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE != high._This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed." group.long 0x28++0x3 line.long 0x00 "I2C_HS_SCL_LCNT_REG,High Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_HS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for high speed. For more information, refer to _IC_CLK Frequency Configuration_._The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160ns; for 400pF loading, the SCL low time is 320ns. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE != high._This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8." group.long 0xA0++0x3 line.long 0x00 "I2C_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size" hexmask.long.byte 0x00 0.--7. 1. " I2C_FS_SPKLEN ,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set." group.long 0xA4++0x3 line.long 0x00 "I2C_IC_HS_SPKLEN_REG,I2C HS spike suppression limit Size" hexmask.long.byte 0x00 0.--7. 1. " I2C_HS_SPKLEN ,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set" group.long 0x30++0x3 line.long 0x00 "I2C_INTR_MASK_REG,I2C Interrupt Mask Register" rbitfld.long 0x00 14. " M_SCL_STUCK_AT_LOW ,M_SCL_STUCK_AT_LOW Register field Reserved bits" "0,1" bitfld.long 0x00 13. " M_MASTER_ON_HOLD ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1" bitfld.long 0x00 12. " M_RESTART_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1" textline " " bitfld.long 0x00 11. " M_GEN_CALL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 10. " M_START_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 9. " M_STOP_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 8. " M_ACTIVITY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 7. " M_RX_DONE ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 6. " M_TX_ABRT ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 5. " M_RD_REQ ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 4. " M_TX_EMPTY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 3. " M_TX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 2. " M_RX_FULL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 1. " M_RX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 0. " M_RX_UNDER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" group.long 0x2C++0x3 line.long 0x00 "I2C_INTR_STAT_REG,I2C Interrupt Status Register" rbitfld.long 0x00 14. " R_SCL_STUCK_AT_LOW ,1 = R_SCL_STUCK_AT_LOW interrupt is active_0 = R_SCL_STUCK_AT_LOW interrupt is inactive" "0,1" rbitfld.long 0x00 13. " R_MASTER_ON_HOLD ,Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1." "0,1" rbitfld.long 0x00 12. " R_RESTART_DET ,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed._Enabled only when IC_SLV_RESTART_DET_EN=1._Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt." "0,1" textline " " rbitfld.long 0x00 11. " R_GEN_CALL ,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer." "0,1" rbitfld.long 0x00 10. " R_START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" rbitfld.long 0x00 9. " R_STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" textline " " rbitfld.long 0x00 8. " R_ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it:_=> Disabling the I2C Ctrl_=> Reading the IC_CLR_ACTIVITY register_=> Reading the IC_CLR_INTR register_=> System reset_Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus." "0,1" rbitfld.long 0x00 7. " R_RX_DONE ,When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done." "0,1" rbitfld.long 0x00 6. " R_TX_ABRT ,This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a _transmit abort_._When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places._NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface." "0,1" textline " " rbitfld.long 0x00 5. " R_RD_REQ ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register" "0,1" rbitfld.long 0x00 4. " R_TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0." "0,1" rbitfld.long 0x00 3. " R_TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared" "0,1" textline " " rbitfld.long 0x00 2. " R_RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues." "0,1" rbitfld.long 0x00 1. " R_RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" rbitfld.long 0x00 0. " R_RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" group.long 0x34++0x3 line.long 0x00 "I2C_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register" rbitfld.long 0x00 14. " SCL_STUCK_AT_LOW ,CL_STUCK_AT_LOW Register field Reserved bits" "0,1" rbitfld.long 0x00 13. " MASTER_ON_HOLD ,ndicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1." "0,1" rbitfld.long 0x00 12. " RESTART_DET ,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed._Enabled only when IC_SLV_RESTART_DET_EN=1._Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt." "0,1" textline " " rbitfld.long 0x00 11. " GEN_CALL ,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer." "0,1" rbitfld.long 0x00 10. " START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" rbitfld.long 0x00 9. " STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" textline " " rbitfld.long 0x00 8. " ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it:_=> Disabling the I2C Ctrl_=> Reading the IC_CLR_ACTIVITY register_=> Reading the IC_CLR_INTR register_=> System reset_Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus." "0,1" rbitfld.long 0x00 7. " RX_DONE ,When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done." "0,1" rbitfld.long 0x00 6. " TX_ABRT ,This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a _transmit abort_._When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places._NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface." "0,1" textline " " rbitfld.long 0x00 5. " RD_REQ ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register" "0,1" rbitfld.long 0x00 4. " TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0." "0,1" rbitfld.long 0x00 3. " TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared" "0,1" textline " " rbitfld.long 0x00 2. " RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues." "0,1" rbitfld.long 0x00 1. " RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" rbitfld.long 0x00 0. " RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" group.long 0x78++0x3 line.long 0x00 "I2C_RXFLR_REG,I2C Receive FIFO Level Register" rbitfld.long 0x00 0.--5. " RXFLR ,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x3 line.long 0x00 "I2C_RX_TL_REG,I2C Receive FIFO Threshold Register" bitfld.long 0x00 0.--4. " RX_TL ,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8++0x3 line.long 0x00 "I2C_SAR_REG,I2C Slave Address Register" hexmask.long.word 0x00 0.--9. 1. " IC_SAR ,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect." group.long 0x7C++0x3 line.long 0x00 "I2C_SDA_HOLD_REG,I2C SDA Hold Time Length Register" hexmask.long.byte 0x00 16.--23. 1. " I2C_SDA_RX_HOLD ,Sets the required SDA hold time in units of ic_clk period, when receiver." hexmask.long.word 0x00 0.--15. 1. " I2C_SDA_TX_HOLD ,Sets the required SDA hold time in units of ic_clk period, when transmitter." group.long 0x94++0x3 line.long 0x00 "I2C_SDA_SETUP_REG,I2C SDA Setup Register" hexmask.long.byte 0x00 0.--7. 1. " SDA_SETUP ,SDA Setup._This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2._It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0" group.long 0x14++0x3 line.long 0x00 "I2C_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_SS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other_times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set._NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10." group.long 0x18++0x3 line.long 0x00 "I2C_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_SS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed._This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set." group.long 0x70++0x3 line.long 0x00 "I2C_STATUS_REG,I2C Status Register" rbitfld.long 0x00 10. " LV_HOLD_RX_FIFO_FULL ,This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received_1 = Slave holds the bus due to Rx FIFO is full_0 = Slave is not holding the bus or Bus hold is not due to Rx FIFO is full" "0,1" rbitfld.long 0x00 9. " SLV_HOLD_TX_FIFO_EMPTY ,This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. The Bus is in hold until the Tx FIFO has data to Transmit for the read request._1 = Slave holds the bus due to Tx FIFO is empty_0 = Slave is not holding the bus or Bus hold is not due to Tx FIFO is empty" "0,1" rbitfld.long 0x00 8. " MST_HOLD_RX_FIFO_FULL ,This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received_1 = Master holds the bus due to Rx FIFO is full_0 = Master is not holding the bus or Bus hold is not due to Rx FIFO is full" "0,1" textline " " rbitfld.long 0x00 7. " MST_HOLD_TX_FIFO_EMPTY ,the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. This bit indicates the BUS hold when the master holds the bus because of the Tx FIFO being empty, and the the previous transferred command does not have the Stop bit set._1 =Master holds the bus due to Tx FIFO is empty_0 =Master is not holding the bus or Bus hold is not due to Tx FIFO is empty" "0,1" rbitfld.long 0x00 6. " SLV_ACTIVITY ,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set._0 = Slave FSM is in IDLE state so the Slave part of the controller is not Active_1 = Slave FSM is not in IDLE state so the Slave part of the controller is Active" "0,1" rbitfld.long 0x00 5. " MST_ACTIVITY ,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set._0 = Master FSM is in IDLE state so the Master part of the controller is not Active_1 = Master FSM is not in IDLE state so the Master part of the controller is Active" "0,1" textline " " rbitfld.long 0x00 4. " RFF ,Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared._0 = Receive FIFO is not full_1 = Receive FIFO is full" "0,1" rbitfld.long 0x00 3. " RFNE ,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty._0 = Receive FIFO is empty_1 = Receive FIFO is not empty" "0,1" rbitfld.long 0x00 2. " TFE ,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt._0 = Transmit FIFO is not empty_1 = Transmit FIFO is empty" "0,1" textline " " rbitfld.long 0x00 1. " TFNF ,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full._0 = Transmit FIFO is full_1 = Transmit FIFO is not full" "0,1" rbitfld.long 0x00 0. " I2C_ACTIVITY ,I2C Activity Status." "0,1" group.long 0x4++0x3 line.long 0x00 "I2C_TAR_REG,I2C Target Address Register" bitfld.long 0x00 11. " SPECIAL ,On read_This bit indicates whether software performs a General Call or START BYTE command._0 = ignore bit 10 GC_OR_START and use IC_TAR normally_1 = perform special I2C command as specified in GC_OR_START_bit_On write_1 = Enables programming of GENERAL_CALL or START_BYTE transmission_0 = Disables programming of GENERAL_CALL or START_BYTE transmission" "0,1" bitfld.long 0x00 10. " GC_OR_START ,On read_If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller._0 = General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared._1 = START BYTE_On write_1 = START byte transmission_0 = GENERAL_CALL byte transmission" "0,1" hexmask.long.word 0x00 0.--9. 1. " IC_TAR ,This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits._Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave" group.long 0x74++0x3 line.long 0x00 "I2C_TXFLR_REG,I2C Transmit FIFO Level Register" rbitfld.long 0x00 0.--5. " TXFLR ,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x80++0x3 line.long 0x00 "I2C_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register" rbitfld.long 0x00 16. " ABRT_USER_ABRT ,Master-Transmitter : This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])" "0,1" rbitfld.long 0x00 15. " ABRT_SLVRD_INTX ,Slave-Transmitter : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register_1 = Slave trying to transmit to remote master in read mode_0 = Slave trying to transmit to remote master in read mode- scenario not present" "0,1" rbitfld.long 0x00 14. " ABRT_SLV_ARBLOST ,Slave-Transmitter : Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never _owns_ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus._1 = Slave lost arbitration to remote master_0 = Slave lost arbitration to remote master- scenario not present" "0,1" textline " " rbitfld.long 0x00 13. " ABRT_SLVFLUSH_TXFIFO ,Slave-Transmitter : Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO._1 = Slave flushes existing data in TX-FIFO upon getting read command_0 = Slave flushes existing data in TX-FIFO upon getting read command- scenario not present" "0,1" rbitfld.long 0x00 12. " ARB_LOST ,Master-Transmitter or Slave-Transmitter : Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time._1 = Master or Slave-Transmitter lost arbitration_0 = Master or Slave-Transmitter lost arbitration- scenario not present" "0,1" rbitfld.long 0x00 11. " ABRT_MASTER_DIS ,Master-Transmitter or Master-Receiver : User tries to initiate a Master operation with the Master mode disabled._1 = User intitating master operation when MASTER disable_0 = User initiating master operation when MASTER disabled- scenario not present" "0,1" textline " " rbitfld.long 0x00 10. " ABRT_10B_RD_NORSTRT ,Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode._1 =Master trying to read in 10Bit addressing mode when RESTART disabled_0 =Master not trying to read in 10Bit addressing mode when RESTART disabled" "0,1" rbitfld.long 0x00 9. " ABRT_SBYTE_NORSTRT ,Master : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. _1 = User trying to send START byte when RESTART disabled_0 = User trying to send START byte when RESTART disabled- scenario not present" "0,1" rbitfld.long 0x00 8. " ABRT_HS_NORSTRT ,Master-Transmitter or Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode_1 = User trying to switch Master to HS mode when RESTART disabled_0 = User trying to switch Master to HS mode when RESTART disabled- scenario not present" "0,1" textline " " rbitfld.long 0x00 7. " ABRT_SBYTE_ACKDET ,Master : Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). _1 = ACK detected for START byte_0 = ACK detected for START byte- scenario not present" "0,1" rbitfld.long 0x00 6. " ABRT_HS_ACKDET ,Master : Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)._1 = HS Master code ACKed in HS Mode_0 = HS Master code ACKed in HS Mode- scenario not present" "0,1" rbitfld.long 0x00 5. " ABRT_GCALL_READ ,Master-Transmitter : The controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)._1 = GCALL is followed by read from bus_0 = GCALL is followed by read from bus-scenario not present" "0,1" textline " " rbitfld.long 0x00 4. " ABRT_GCALL_NOACK ,Master-Transmitter : the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call._1 = GCALL not ACKed by any slave_0 = GCALL not ACKed by any slave-scenario not present" "0,1" rbitfld.long 0x00 3. " ABRT_TXDATA_NOACK ,Master-Transmitter : This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)._1 = Transmitted data not ACKed by addressed slave_0 = Transmitted data non-ACKed by addressed slave-scenario not present" "0,1" rbitfld.long 0x00 2. " ABRT_10ADDR2_NOACK ,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave._1= Byte 2 of 10Bit Address not ACKed by any slave_0 = This abort is not generated" "0,1" textline " " rbitfld.long 0x00 1. " ABRT_10ADDR1_NOACK ,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave._1 =Byte 1 of 10Bit Address not ACKed by any slave_0 =This abort is not generated" "0,1" rbitfld.long 0x00 0. " ABRT_7B_ADDR_NOACK ,Master-Transmitter or Master-Receiver : Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave._1 =This abort is generated because of NOACK for 7-bit address_0 =This abort is not generated" "0,1" group.long 0x3C++0x3 line.long 0x00 "I2C_TX_TL_REG,I2C Transmit FIFO Threshold Register" bitfld.long 0x00 0.--4. " TX_TL ,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "I2C2" base ad:0x50020700 width 27. group.long 0x98++0x3 line.long 0x00 "I2C2_ACK_GENERAL_CALL_REG,I2C ACK General Call Register" bitfld.long 0x00 0. " ACK_GEN_CALL ,ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts._1 = Generate ACK for a General Call_0 = Generate NACK for General Call" "0,1" group.long 0x5C++0x3 line.long 0x00 "I2C2_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register" rbitfld.long 0x00 0. " CLR_ACTIVITY ,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register" "0,1" group.long 0x68++0x3 line.long 0x00 "I2C2_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register" rbitfld.long 0x00 0. " CLR_GEN_CALL ,Read this register to clear the GEN_CALL interrupt (bit 11) of_I2C_RAW_INTR_STAT register." "0,1" group.long 0x40++0x3 line.long 0x00 "I2C2_CLR_INTR_REG,Clear Combined and Individual Interrupt Register" rbitfld.long 0x00 0. " CLR_INTR ,Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE" "0,1" group.long 0x50++0x3 line.long 0x00 "I2C2_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register" rbitfld.long 0x00 0. " CLR_RD_REQ ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register." "0,1" group.long 0x58++0x3 line.long 0x00 "I2C2_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_DONE ,Read this register to clear the RX_DONE interrupt (bit 7) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x48++0x3 line.long 0x00 "I2C2_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_OVER ,Read this register to clear the RX_OVER interrupt (bit 1) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x44++0x3 line.long 0x00 "I2C2_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register" rbitfld.long 0x00 0. " CLR_RX_UNDER ,Read this register to clear the RX_UNDER interrupt (bit 0) of the_I2C_RAW_INTR_STAT register." "0,1" group.long 0x64++0x3 line.long 0x00 "I2C2_CLR_START_DET_REG,Clear START_DET Interrupt Register" rbitfld.long 0x00 0. " CLR_START_DET ,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register." "0,1" group.long 0x60++0x3 line.long 0x00 "I2C2_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register" rbitfld.long 0x00 0. " CLR_ACTIVITY ,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register." "0,1" group.long 0x54++0x3 line.long 0x00 "I2C2_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register" rbitfld.long 0x00 0. " CLR_TX_ABRT ,Read this register to clear the TX_ABRT interrupt (bit 6) of the_IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE." "0,1" group.long 0x4C++0x3 line.long 0x00 "I2C2_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register" rbitfld.long 0x00 0. " CLR_TX_OVER ,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register." "0,1" group.long 0xF4++0x3 line.long 0x00 "I2C2_COMP_PARAM1_REG,Component Parameter Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_PARAM1 ,This is a constant read-only register that contains encoded information about the component's parameter settings" group.long 0xFC++0x3 line.long 0x00 "I2C2_COMP_TYPE_REG,I2C Component Type Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_TYPE ," group.long 0xF8++0x3 line.long 0x00 "I2C2_COMP_VERSION_REG,I2C Component Version Register" hexmask.long 0x00 0.--31. 1. " IC_COMP_VERSION ," group.long 0x0++0x3 line.long 0x00 "I2C2_CON_REG,I2C Control Register" rbitfld.long 0x00 10. " I2C_STOP_DET_IF_MASTER_ACTIVE ,In Master mode:_1 = issues the STOP_DET interrupt only when master is active._0 = issues the STOP_DET irrespective of whether master is active or not." "0,1" bitfld.long 0x00 9. " I2C_RX_FIFO_FULL_HLD_CTRL ,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH_1 = Hold bus when RX_FIFO is full_0 = Overflow when RX_FIFO is full" "0,1" bitfld.long 0x00 8. " I2C_TX_EMPTY_CTRL ,This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register._1 = Controlled generation of TX_EMPTY interrupt_0 = Default behaviour of TX_EMPTY interrupt" "0,1" textline " " bitfld.long 0x00 7. " I2C_STOP_DET_IFADDRESSED ,1 = slave issues STOP_DET intr only if addressed_0 = slave issues STOP_DET intr always_During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)" "0,1" bitfld.long 0x00 6. " I2C_SLAVE_DISABLE ,Slave enabled or disabled after reset is applied, which means software does not have to configure the slave._0=slave is enabled_1=slave is disabled_Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'." "0,1" bitfld.long 0x00 5. " I2C_RESTART_EN ,Determines whether RESTART conditions may be sent when acting as a master_0= disable_1=enable" "0,1" textline " " bitfld.long 0x00 4. " I2C_10BITADDR_MASTER ,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master._0= 7-bit addressing_1= 10-bit addressing" "0,1" bitfld.long 0x00 3. " I2C_10BITADDR_SLAVE ,When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses._0= 7-bit addressing_1= 10-bit addressing" "0,1" bitfld.long 0x00 1.--2. " I2C_SPEED ,These bits control at which speed the controller operates._1= standard mode (100 kbit/s)_2= fast mode (400 kbit/s)_3= high speed mode" "0,1,2,3" textline " " bitfld.long 0x00 0. " I2C_MASTER_MODE ,This bit controls whether the controller master is enabled._0= master disabled_1= master enabled_Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'." "0,1" group.long 0x10++0x3 line.long 0x00 "I2C2_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register" bitfld.long 0x00 10. " I2C_RESTART ,This bit controls whether a RESTART is issued before the byte is sent or received. _1 = If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead._0 = If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead" "0,1" bitfld.long 0x00 9. " I2C_STOP ,This bit controls whether a STOP is issued after the byte is sent or received._1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus._0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO." "0,1" bitfld.long 0x00 8. " I2C_CMD ,This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master._1 = Read_0 = Write_When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a _don't care_ because writes to this register are not required. In slave-transmitter mode, a _0_ indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared._If a _1_ is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs._NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " I2C_DAT ,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface." group.long 0x88++0x3 line.long 0x00 "I2C2_DMA_CR_REG,DMA Control Register" bitfld.long 0x00 1. " TDMAE ,Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel._0 = Transmit DMA disabled_1 = Transmit DMA enabled" "0,1" bitfld.long 0x00 0. " RDMAE ,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel._0 = Receive DMA disabled_1 = Receive DMA enabled" "0,1" group.long 0x90++0x3 line.long 0x00 "I2C2_DMA_RDLR_REG,I2C Receive Data Level Register" bitfld.long 0x00 0.--4. " DMARDL ,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x3 line.long 0x00 "I2C2_DMA_TDLR_REG,DMA Transmit Data Level Register" bitfld.long 0x00 0.--4. " DMATDL ,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6C++0x3 line.long 0x00 "I2C2_ENABLE_REG,I2C Enable Register" bitfld.long 0x00 2. " I2C_TX_CMD_BLOCK ,In Master mode:_1 = Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit._0.= The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO." "0,1" bitfld.long 0x00 1. " I2C_ABORT ,The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation." "0,1" bitfld.long 0x00 0. " I2C_EN ,Controls whether the controller is enabled._0 = Disables the controller (TX and RX FIFOs are held in an erased state)_1 = Enables the controller_Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs:_* The TX FIFO and RX FIFO get flushed._* Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state._If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer._There is a two ic_clk delay when enabling or disabling the controller" "0,1" group.long 0x9C++0x3 line.long 0x00 "I2C2_ENABLE_STATUS_REG,I2C Enable Status Register" rbitfld.long 0x00 2. " SLV_RX_DATA_LOST ,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer._NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0._1 = Slave RX Data is lost_0 = Slave RX Data is not lost" "0,1" rbitfld.long 0x00 1. " SLV_DISABLED_WHILE_BUSY ,Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:_(a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master; OR,_(b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect._NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1._When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle._NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0._1 =Slave is disabled when it is active_0 =Slave is disabled when it is idle" "0,1" rbitfld.long 0x00 0. " IC_EN ,ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state._When read as 0, the controller is deemed completely inactive._NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1)._1 = I2C enabled_0 =I2C disabled" "0,1" group.long 0x1C++0x3 line.long 0x00 "I2C2_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_FS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set." group.long 0x20++0x3 line.long 0x00 "I2C2_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_FS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed." group.long 0xC++0x3 line.long 0x00 "I2C2_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register" bitfld.long 0x00 0.--2. " I2C_IC_HS_MAR ,This bit field holds the value of the I2C HS mode master code. HS-mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code; up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect" "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "I2C2_HS_SCL_HCNT_REG,High Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_HS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high period count for high speed.refer to _IC_CLK Frequency Configuration_._The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time is 60ns; for 400pF loading, the SCL High time is 120ns. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE != high._This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed." group.long 0x28++0x3 line.long 0x00 "I2C2_HS_SCL_LCNT_REG,High Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_HS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for high speed. For more information, refer to _IC_CLK Frequency Configuration_._The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160ns; for 400pF loading, the SCL low time is 320ns. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE != high._This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8." group.long 0xA0++0x3 line.long 0x00 "I2C2_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size" hexmask.long.byte 0x00 0.--7. 1. " I2C_FS_SPKLEN ,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set." group.long 0xA4++0x3 line.long 0x00 "I2C2_IC_HS_SPKLEN_REG,I2C HS spike suppression limit Size" hexmask.long.byte 0x00 0.--7. 1. " I2C_HS_SPKLEN ,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect._The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set" group.long 0x30++0x3 line.long 0x00 "I2C2_INTR_MASK_REG,I2C Interrupt Mask Register" rbitfld.long 0x00 14. " M_SCL_STUCK_AT_LOW ,M_SCL_STUCK_AT_LOW Register field Reserved bits" "0,1" bitfld.long 0x00 13. " M_MASTER_ON_HOLD ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1" bitfld.long 0x00 12. " M_RESTART_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1" textline " " bitfld.long 0x00 11. " M_GEN_CALL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 10. " M_START_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 9. " M_STOP_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 8. " M_ACTIVITY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 7. " M_RX_DONE ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 6. " M_TX_ABRT ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 5. " M_RD_REQ ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 4. " M_TX_EMPTY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 3. " M_TX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" textline " " bitfld.long 0x00 2. " M_RX_FULL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 1. " M_RX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" bitfld.long 0x00 0. " M_RX_UNDER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register." "0,1" group.long 0x2C++0x3 line.long 0x00 "I2C2_INTR_STAT_REG,I2C Interrupt Status Register" rbitfld.long 0x00 14. " R_SCL_STUCK_AT_LOW ,1 = R_SCL_STUCK_AT_LOW interrupt is active_0 = R_SCL_STUCK_AT_LOW interrupt is inactive" "0,1" rbitfld.long 0x00 13. " R_MASTER_ON_HOLD ,Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1." "0,1" rbitfld.long 0x00 12. " R_RESTART_DET ,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed._Enabled only when IC_SLV_RESTART_DET_EN=1._Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt." "0,1" textline " " rbitfld.long 0x00 11. " R_GEN_CALL ,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer." "0,1" rbitfld.long 0x00 10. " R_START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" rbitfld.long 0x00 9. " R_STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" textline " " rbitfld.long 0x00 8. " R_ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it:_=> Disabling the I2C Ctrl_=> Reading the IC_CLR_ACTIVITY register_=> Reading the IC_CLR_INTR register_=> System reset_Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus." "0,1" rbitfld.long 0x00 7. " R_RX_DONE ,When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done." "0,1" rbitfld.long 0x00 6. " R_TX_ABRT ,This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a _transmit abort_._When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places._NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface." "0,1" textline " " rbitfld.long 0x00 5. " R_RD_REQ ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register" "0,1" rbitfld.long 0x00 4. " R_TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0." "0,1" rbitfld.long 0x00 3. " R_TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared" "0,1" textline " " rbitfld.long 0x00 2. " R_RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues." "0,1" rbitfld.long 0x00 1. " R_RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" rbitfld.long 0x00 0. " R_RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" group.long 0x34++0x3 line.long 0x00 "I2C2_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register" rbitfld.long 0x00 14. " SCL_STUCK_AT_LOW ,CL_STUCK_AT_LOW Register field Reserved bits" "0,1" rbitfld.long 0x00 13. " MASTER_ON_HOLD ,ndicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1." "0,1" rbitfld.long 0x00 12. " RESTART_DET ,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed._Enabled only when IC_SLV_RESTART_DET_EN=1._Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt." "0,1" textline " " rbitfld.long 0x00 11. " GEN_CALL ,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer." "0,1" rbitfld.long 0x00 10. " START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" rbitfld.long 0x00 9. " STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode." "0,1" textline " " rbitfld.long 0x00 8. " ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it:_=> Disabling the I2C Ctrl_=> Reading the IC_CLR_ACTIVITY register_=> Reading the IC_CLR_INTR register_=> System reset_Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus." "0,1" rbitfld.long 0x00 7. " RX_DONE ,When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done." "0,1" rbitfld.long 0x00 6. " TX_ABRT ,This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a _transmit abort_._When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places._NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface." "0,1" textline " " rbitfld.long 0x00 5. " RD_REQ ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register" "0,1" rbitfld.long 0x00 4. " TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0." "0,1" rbitfld.long 0x00 3. " TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared" "0,1" textline " " rbitfld.long 0x00 2. " RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues." "0,1" rbitfld.long 0x00 1. " RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" rbitfld.long 0x00 0. " RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared." "0,1" group.long 0x78++0x3 line.long 0x00 "I2C2_RXFLR_REG,I2C Receive FIFO Level Register" rbitfld.long 0x00 0.--5. " RXFLR ,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x3 line.long 0x00 "I2C2_RX_TL_REG,I2C Receive FIFO Threshold Register" bitfld.long 0x00 0.--4. " RX_TL ,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8++0x3 line.long 0x00 "I2C2_SAR_REG,I2C Slave Address Register" hexmask.long.word 0x00 0.--9. 1. " IC_SAR ,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect." group.long 0x7C++0x3 line.long 0x00 "I2C2_SDA_HOLD_REG,I2C SDA Hold Time Length Register" hexmask.long.byte 0x00 16.--23. 1. " I2C_SDA_RX_HOLD ,Sets the required SDA hold time in units of ic_clk period, when receiver." hexmask.long.word 0x00 0.--15. 1. " I2C_SDA_TX_HOLD ,Sets the required SDA hold time in units of ic_clk period, when transmitter." group.long 0x94++0x3 line.long 0x00 "I2C2_SDA_SETUP_REG,I2C SDA Setup Register" hexmask.long.byte 0x00 0.--7. 1. " SDA_SETUP ,SDA Setup._This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2._It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0" group.long 0x14++0x3 line.long 0x00 "I2C2_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_SS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other_times have no effect._The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set._NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10." group.long 0x18++0x3 line.long 0x00 "I2C2_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. " IC_SS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed._This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect._The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set." group.long 0x70++0x3 line.long 0x00 "I2C2_STATUS_REG,I2C Status Register" rbitfld.long 0x00 10. " LV_HOLD_RX_FIFO_FULL ,This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received_1 = Slave holds the bus due to Rx FIFO is full_0 = Slave is not holding the bus or Bus hold is not due to Rx FIFO is full" "0,1" rbitfld.long 0x00 9. " SLV_HOLD_TX_FIFO_EMPTY ,This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. The Bus is in hold until the Tx FIFO has data to Transmit for the read request._1 = Slave holds the bus due to Tx FIFO is empty_0 = Slave is not holding the bus or Bus hold is not due to Tx FIFO is empty" "0,1" rbitfld.long 0x00 8. " MST_HOLD_RX_FIFO_FULL ,This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received_1 = Master holds the bus due to Rx FIFO is full_0 = Master is not holding the bus or Bus hold is not due to Rx FIFO is full" "0,1" textline " " rbitfld.long 0x00 7. " MST_HOLD_TX_FIFO_EMPTY ,the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. This bit indicates the BUS hold when the master holds the bus because of the Tx FIFO being empty, and the the previous transferred command does not have the Stop bit set._1 =Master holds the bus due to Tx FIFO is empty_0 =Master is not holding the bus or Bus hold is not due to Tx FIFO is empty" "0,1" rbitfld.long 0x00 6. " SLV_ACTIVITY ,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set._0 = Slave FSM is in IDLE state so the Slave part of the controller is not Active_1 = Slave FSM is not in IDLE state so the Slave part of the controller is Active" "0,1" rbitfld.long 0x00 5. " MST_ACTIVITY ,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set._0 = Master FSM is in IDLE state so the Master part of the controller is not Active_1 = Master FSM is not in IDLE state so the Master part of the controller is Active" "0,1" textline " " rbitfld.long 0x00 4. " RFF ,Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared._0 = Receive FIFO is not full_1 = Receive FIFO is full" "0,1" rbitfld.long 0x00 3. " RFNE ,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty._0 = Receive FIFO is empty_1 = Receive FIFO is not empty" "0,1" rbitfld.long 0x00 2. " TFE ,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt._0 = Transmit FIFO is not empty_1 = Transmit FIFO is empty" "0,1" textline " " rbitfld.long 0x00 1. " TFNF ,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full._0 = Transmit FIFO is full_1 = Transmit FIFO is not full" "0,1" rbitfld.long 0x00 0. " I2C_ACTIVITY ,I2C Activity Status." "0,1" group.long 0x4++0x3 line.long 0x00 "I2C2_TAR_REG,I2C Target Address Register" bitfld.long 0x00 11. " SPECIAL ,On read_This bit indicates whether software performs a General Call or START BYTE command._0 = ignore bit 10 GC_OR_START and use IC_TAR normally_1 = perform special I2C command as specified in GC_OR_START_bit_On write_1 = Enables programming of GENERAL_CALL or START_BYTE transmission_0 = Disables programming of GENERAL_CALL or START_BYTE transmission" "0,1" bitfld.long 0x00 10. " GC_OR_START ,On read_If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller._0 = General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared._1 = START BYTE_On write_1 = START byte transmission_0 = GENERAL_CALL byte transmission" "0,1" hexmask.long.word 0x00 0.--9. 1. " IC_TAR ,This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits._Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave" group.long 0x74++0x3 line.long 0x00 "I2C2_TXFLR_REG,I2C Transmit FIFO Level Register" rbitfld.long 0x00 0.--5. " TXFLR ,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x80++0x3 line.long 0x00 "I2C2_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register" rbitfld.long 0x00 16. " ABRT_USER_ABRT ,Master-Transmitter : This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])" "0,1" rbitfld.long 0x00 15. " ABRT_SLVRD_INTX ,Slave-Transmitter : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register_1 = Slave trying to transmit to remote master in read mode_0 = Slave trying to transmit to remote master in read mode- scenario not present" "0,1" rbitfld.long 0x00 14. " ABRT_SLV_ARBLOST ,Slave-Transmitter : Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never _owns_ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus._1 = Slave lost arbitration to remote master_0 = Slave lost arbitration to remote master- scenario not present" "0,1" textline " " rbitfld.long 0x00 13. " ABRT_SLVFLUSH_TXFIFO ,Slave-Transmitter : Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO._1 = Slave flushes existing data in TX-FIFO upon getting read command_0 = Slave flushes existing data in TX-FIFO upon getting read command- scenario not present" "0,1" rbitfld.long 0x00 12. " ARB_LOST ,Master-Transmitter or Slave-Transmitter : Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time._1 = Master or Slave-Transmitter lost arbitration_0 = Master or Slave-Transmitter lost arbitration- scenario not present" "0,1" rbitfld.long 0x00 11. " ABRT_MASTER_DIS ,Master-Transmitter or Master-Receiver : User tries to initiate a Master operation with the Master mode disabled._1 = User intitating master operation when MASTER disable_0 = User initiating master operation when MASTER disabled- scenario not present" "0,1" textline " " rbitfld.long 0x00 10. " ABRT_10B_RD_NORSTRT ,Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode._1 =Master trying to read in 10Bit addressing mode when RESTART disabled_0 =Master not trying to read in 10Bit addressing mode when RESTART disabled" "0,1" rbitfld.long 0x00 9. " ABRT_SBYTE_NORSTRT ,Master : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. _1 = User trying to send START byte when RESTART disabled_0 = User trying to send START byte when RESTART disabled- scenario not present" "0,1" rbitfld.long 0x00 8. " ABRT_HS_NORSTRT ,Master-Transmitter or Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode_1 = User trying to switch Master to HS mode when RESTART disabled_0 = User trying to switch Master to HS mode when RESTART disabled- scenario not present" "0,1" textline " " rbitfld.long 0x00 7. " ABRT_SBYTE_ACKDET ,Master : Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). _1 = ACK detected for START byte_0 = ACK detected for START byte- scenario not present" "0,1" rbitfld.long 0x00 6. " ABRT_HS_ACKDET ,Master : Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)._1 = HS Master code ACKed in HS Mode_0 = HS Master code ACKed in HS Mode- scenario not present" "0,1" rbitfld.long 0x00 5. " ABRT_GCALL_READ ,Master-Transmitter : The controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)._1 = GCALL is followed by read from bus_0 = GCALL is followed by read from bus-scenario not present" "0,1" textline " " rbitfld.long 0x00 4. " ABRT_GCALL_NOACK ,Master-Transmitter : the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call._1 = GCALL not ACKed by any slave_0 = GCALL not ACKed by any slave-scenario not present" "0,1" rbitfld.long 0x00 3. " ABRT_TXDATA_NOACK ,Master-Transmitter : This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)._1 = Transmitted data not ACKed by addressed slave_0 = Transmitted data non-ACKed by addressed slave-scenario not present" "0,1" rbitfld.long 0x00 2. " ABRT_10ADDR2_NOACK ,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave._1= Byte 2 of 10Bit Address not ACKed by any slave_0 = This abort is not generated" "0,1" textline " " rbitfld.long 0x00 1. " ABRT_10ADDR1_NOACK ,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave._1 =Byte 1 of 10Bit Address not ACKed by any slave_0 =This abort is not generated" "0,1" rbitfld.long 0x00 0. " ABRT_7B_ADDR_NOACK ,Master-Transmitter or Master-Receiver : Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave._1 =This abort is generated because of NOACK for 7-bit address_0 =This abort is not generated" "0,1" group.long 0x3C++0x3 line.long 0x00 "I2C2_TX_TL_REG,I2C Transmit FIFO Threshold Register" bitfld.long 0x00 0.--4. " TX_TL ,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end sif !cpuis("DA14691-CM33") tree "LCDC" base ad:0x30030000 width 30. group.long 0x1C++0x3 line.long 0x00 "LCDC_BACKPORCHXY_REG,Back Porch X and Y" hexmask.long.word 0x00 16.--31. 1. " LCDC_BPORCH_X ,Back porch X (lines)" hexmask.long.word 0x00 0.--15. 1. " LCDC_BPORCH_Y ,Back porch Y (pixel clocks)" group.long 0x8++0x3 line.long 0x00 "LCDC_BGCOLOR_REG,Background Color" hexmask.long.byte 0x00 24.--31. 1. " LCDC_BG_RED ,Red color used as background" hexmask.long.byte 0x00 16.--23. 1. " LCDC_BG_GREEN ,Green color used as background" hexmask.long.byte 0x00 8.--15. 1. " LCDC_BG_BLUE ,Blue color used as background" textline " " hexmask.long.byte 0x00 0.--7. 1. " LCDC_BG_ALPHA ,Alpha color used as background" group.long 0x18++0x3 line.long 0x00 "LCDC_BLANKINGXY_REG,Blanking X and Y" hexmask.long.word 0x00 16.--31. 1. " LCDC_BLANKING_X ,Blanking period X (VSYNC lines)" hexmask.long.word 0x00 0.--15. 1. " LCDC_BLANKING_Y ,Blanking period Y (HSYNC pulse length)" group.long 0x4++0x3 line.long 0x00 "LCDC_CLKCTRL_REG,Clock Divider" bitfld.long 0x00 27.--31. " LCDC_SEC_CLK_DIV ,Secondary clock divider that generates the format pipeline clock. Source clock of this divider is the main clock of LCD controller. The period of the generated clock is defined as : (LCDC_SEC_CLK_DIV + 1) x period_of_main_clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " LCDC_DMA_HOLD ,Hold time before DMA activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LCDC_CLK_DIV ,Clock divider that generates the pixel pipeline clock. Source clock of this divider is the format pipeline clock (see also LCDC_SEC_CLK_DIV). The period of the generated clock is defines as : LCDC_CLK_DIV x period_of_format_clk. A zero value gives division by one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x184++0x3 line.long 0x00 "LCDC_CRC_REG,CRC check" hexmask.long 0x00 0.--31. 1. " LCDC_CRC ,CRC check" group.long 0x28++0x3 line.long 0x00 "LCDC_DBIB_CFG_REG,MIPI Config Register" bitfld.long 0x00 31. " LCDC_DBIB_TE_DIS ,Disable the sampling of the tearing effect signal, which is provided by the LCD device._0: the tearing effect signal is sampled_1: the tearing effect signal is not sampled" "0,1" bitfld.long 0x00 30. " LCDC_DBIB_CSX_FORCE ,Forces the DBIB CSX value. When is enabled the DBIB CSX takes the value of the LCDC_DBIB_CSX_FORCE_VAL._0 : disable_1 : enable" "0,1" bitfld.long 0x00 29. " LCDC_DBIB_CSX_FORCE_VAL ,Value of DBIB CSX to be forced, if bit 30 is set. Defines also the active level of the DBIB CSX even if the bit 30 is not set" "0,1" textline " " bitfld.long 0x00 28. " LCDC_DBIB_SPI_PAD ,Data padding :_0 : disable_1 : enable" "0,1" bitfld.long 0x00 25. " LCDC_DBIB_RESX ,DBIB RESX, reset signal for MIPI DBIB display" "0,1" bitfld.long 0x00 24. " LCDC_DBIB_DMA_EN ,Send pixels from DMA to DBIB display._0 : disable_1 : enable" "0,1" textline " " bitfld.long 0x00 23. " LCDC_DBIB_SPI3_EN ,Enable SPI3 interface._0 : disable_1 : enable" "0,1" bitfld.long 0x00 22. " LCDC_DBIB_SPI4_EN ,Enable SPI4 interface._0 : disable_1 : enable" "0,1" bitfld.long 0x00 20. " LCDC_DBIB_SPI_CPHA ,Sets the data phase for the SPI interface" "0,1" textline " " bitfld.long 0x00 19. " LCDC_DBIB_SPI_CPOL ,Sets the polarity of the clock (SCL)" "0,1" bitfld.long 0x00 18. " LCDC_DBIB_SPI_JDI ,Enables the line addressing between the horizontal lines (JDI SPI output format)._0 : disable_1 : enable" "0,1" bitfld.long 0x00 17. " LCDC_DBIB_SPI_HOLD ,Enables the command HOLD mode of operation. Commands and data transmissions binding._0 : disable_1 : enable" "0,1" textline " " bitfld.long 0x00 16. " LCDC_DBIB_SPI_INV_ADDR ,Enables horizontal line address inversion._0 : disable_1 : enable" "0,1" bitfld.long 0x00 15. " LCDC_DBIB_INV_DATA ,Data inversion_0 : disable_1 : enable" "0,1" bitfld.long 0x00 14. " LCDC_DBIB_JDI_INV_PIX ,MSB-LSB bit selection for JDI parallel interface_0 : disable (MSB - LSB)_1 : enable (LSB -MSB)" "0,1" textline " " bitfld.long 0x00 13. " LCDC_DBIB_JDI_SOFT_RST ,JDI timing generation soft reset._0 : disable_1 : enable" "0,1" bitfld.long 0x00 0.--4. " LCDC_DBIB_FMT ,Defines the output format and depends of the type of the output interface. For the SPI3 and the SPI4 are supported the following formats:_0x10 : RGB332_0x11 : RGB444_0x12 : RGB565_0x13 : RGB666_0x14 : RGB888__For the SPI4 only are supported additionally the following formats:_0x06 : RGB111-1 {2b00, R(n), G(n), B(n), R(n+1), G(n+1), B(n+1)}_0x07 : RGB111-2 {R(n), G(n), B(n), 1b0, R(n+1), G(n+1), B(n+1), 1b0}_0x08 : RGB111-3 {R(n), G(n), B(n), R(n+1), G(n+1), B(n+1), R(n+2), G(n+2), B(n+2),... }_0x09 : RGB111-4 {D(n), D(n+1), D(n+2),...}__For the JDI parallel interface should be used the format :_0x0A : RGB222" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE8++0x3 line.long 0x00 "LCDC_DBIB_CMD_REG,MIPI DBIB Command Register" bitfld.long 0x00 30. " LCDC_DBIB_CMD_SEND ,Send command to the DBI interface" "0,1" bitfld.long 0x00 27. " LCDC_DBIB_CMD_STORE ,This bit has meaning only when LCDC_DBIB_CFG_REG[LCDC_DBIB_SPI_JDI] = 1. When is enabled, stores the LCDC_DBIB_CMD_VAL to the register that keeps the Y position." "0,1" hexmask.long.word 0x00 0.--15. 1. " LCDC_DBIB_CMD_VAL ,Data to send to the DBI interface" group.long 0x14++0x3 line.long 0x00 "LCDC_FRONTPORCHXY_REG,Front Porch X and Y" hexmask.long.word 0x00 16.--31. 1. " LCDC_FPORCH_X ,Front porch X (lines)" hexmask.long.word 0x00 0.--15. 1. " LCDC_FPORCH_Y ,Front porch Y (pixel clocks)" group.long 0x2C++0x3 line.long 0x00 "LCDC_GPIO_REG,General Purpose IO (2-bits)" bitfld.long 0x00 1. " LCDC_TE_INV ,Applies an inversion on the TE (tearing effect) signal._0 : the inversion is not applied on the TE signal_1 : the inversion is applied on TE signal" "0,1" bitfld.long 0x00 0. " LCDC_PARIF_SEL ,Selection of the parallel interface type that is forwarded to the gpio pins._0 : JDI interface signals_1 : Clasic parallel interface" "0,1" group.long 0xF4++0x3 line.long 0x00 "LCDC_IDREG_REG,Identification Register" hexmask.long 0x00 0.--31. 1. " LCDC_ID ,Identification register" group.long 0xF8++0x3 line.long 0x00 "LCDC_INTERRUPT_REG,Interrupt Register" bitfld.long 0x00 31. " LCDC_IRQ_TRIGGER_SEL ,IRQ trigger control_0: Level triggering_1: Edge triggering_In the case of the level triggering, the request remains active in the LCDC until to be cleared. The request can be cleared by performing a write access in the LCDC_INTERRUPT_REG. This is not required in the case of the edge triggering" "0,1" bitfld.long 0x00 5. " LCDC_FRAME_END_IRQ_EN ,Continuous mode: frame end. Single mode: frame end or idle" "0,1" bitfld.long 0x00 3. " LCDC_TE_IRQ_EN ,TE interrupt enable. See also the configuration bit LCDC_DBIB_CFG_REG[LCDC_DBIB_TE_DIS]" "0,1" textline " " bitfld.long 0x00 1. " LCDC_HSYNC_IRQ_EN ,HSYNC interrupt enabled" "0,1" bitfld.long 0x00 0. " LCDC_VSYNC_IRQ_EN ,VSYNC or TE interrupt enabled. See also the configuration bit LCDC_DBIB_CFG_REG[LCDC_DBIB_TE_DIS] for the TE signal" "0,1" group.long 0xBC++0x3 line.long 0x00 "LCDC_JDI_ENB_END_HLINE_REG,ENB end horizontal line" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_ENB_END_HLINE ,The number of the last horizontal line where the ENB signal is asserted" group.long 0xC0++0x3 line.long 0x00 "LCDC_JDI_ENB_START_CLK_REG,ENB start delay" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_ENB_START_CLK ,Defines the number of the HCK half periods that should take place after a transtion in the VCK and before to be enabled of the ENB." group.long 0xB8++0x3 line.long 0x00 "LCDC_JDI_ENB_START_HLINE_REG,ENB start horizontal line" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_ENB_START_HLINE ,The number of the first horizontal line where the ENB signal is asserted" group.long 0xC4++0x3 line.long 0x00 "LCDC_JDI_ENB_WIDTH_CLK_REG,ENB width" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_ENB_WIDTH_CLK ,ENB (high) width in HCK half periods" group.long 0x94++0x3 line.long 0x00 "LCDC_JDI_FBX_BLANKING_REG,Horizontal front/back blanking (hck half periods)" hexmask.long.word 0x00 16.--31. 1. " LCDC_JDI_FXBLANKING ,Horizontal front blanking as a number of hck half periods" hexmask.long.word 0x00 0.--15. 1. " LCDC_JDI_BXBLANKING ,Horizontal back blanking as a number of hck half periods" group.long 0x98++0x3 line.long 0x00 "LCDC_JDI_FBY_BLANKING_REG,Vertical front/back blanking (vck half periods)" hexmask.long.word 0x00 16.--31. 1. " LCDC_JDI_FYBLANKING ,Vertical front blanking as a number of vck half periods" hexmask.long.word 0x00 0.--15. 1. " LCDC_JDI_BYBLANKING ,Vertical back blanking as a number of vck half periods" group.long 0x9C++0x3 line.long 0x00 "LCDC_JDI_HCK_WIDTH_REG,HCK high/low width" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_HCK_WIDTH ,Number of formal pipeline clock cycles that define the half period of the of the HCK (high and low width). The minimum allowed value is 2" group.long 0xB0++0x3 line.long 0x00 "LCDC_JDI_HST_DELAY_REG,VCK-to-HST delay" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_HST_DELAY ,VCK-to-HST delay in format pipeline clock cycles" group.long 0xB4++0x3 line.long 0x00 "LCDC_JDI_HST_WIDTH_REG,HST width" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_HST_WIDTH ,HST width in format pipeline clock cycles" group.long 0x90++0x3 line.long 0x00 "LCDC_JDI_RESXY_REG,Resolution XY for the JDI parallel I/F" hexmask.long.word 0x00 16.--31. 1. " LCDC_JDI_RES_X ,Number of horizontal transfers. Should be equal to the half of the horizontal resolution (in pixels)" hexmask.long.word 0x00 0.--15. 1. " LCDC_JDI_RES_Y ,Number of vertical transfers. Should be equal to the double of the vertical resolution (in lines)." group.long 0xAC++0x3 line.long 0x00 "LCDC_JDI_VCK_DELAY_REG,XRST-to-VCK delay" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_VCK_DELAY ,XRST-to-VCK delay in format pipeline clock cycles" group.long 0xA4++0x3 line.long 0x00 "LCDC_JDI_VST_DELAY_REG,XRST-to-VST delay" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_VST_DELAY ,XRST-to-VST delay in format pipeline clock cycles" group.long 0xA8++0x3 line.long 0x00 "LCDC_JDI_VST_WIDTH_REG,VST width" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_VST_WIDTH ,VST width in format pipeline clock cycles" group.long 0xA0++0x3 line.long 0x00 "LCDC_JDI_XRST_WIDTH_REG,XRST width" hexmask.long 0x00 0.--31. 1. " LCDC_JDI_XRST_WIDTH ,Number of format pipeline clock cycles of XRST width" group.long 0x3C++0x3 line.long 0x00 "LCDC_LAYER0_BASEADDR_REG,Layer0 Base Addr" hexmask.long 0x00 0.--31. 1. " LCDC_L0_FB_ADDR ,Base Address of the frame buffer" group.long 0x30++0x3 line.long 0x00 "LCDC_LAYER0_MODE_REG,Layer0 Mode" bitfld.long 0x00 31. " LCDC_L0_EN ,Enable layer._0 : disable_1 : enable" "0,1" bitfld.long 0x00 0.--4. " LCDC_L0_COLOUR_MODE ,Colour Mode:_00001: 16-bit RGBX5551 color format,_00010: 32-bit RGBX8888 color format,_00100: 8-bit RGB332 color format,_00101: 16-bit RGB565 color format,_00110: 32-bit XRGB8888,_00111: L8 Grayscale/Palette format,_01000: L1 Grayscale/Palette format,_01001: L4 Grayscale/Palette format,_01101: ABGR8888,_01110: BGRA8888" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x188++0x3 line.long 0x00 "LCDC_LAYER0_OFFSETX_REG,Layer0 OffsetX and DMA prefetch" hexmask.long.word 0x00 16.--31. 1. " LCDC_L0_DMA_PREFETCH ,DMA fifo prefetch level (range: 0-4)_0x0 : Prefetch mechanism is disabled_0x1 : Prefetch at least 44 bytes_0x2 : Prefetch at least 84 bytes_0x3 : Prefetch at least 116 bytes_0x4 : Prefetch at least 108 bytes_Any other value : Reserved" hexmask.long.word 0x00 0.--15. 1. " LCDC_L0_OFFSETX ,Offset X (negative) of X start pixel (range [n-1,0], n : pixels /8)" group.long 0x44++0x3 line.long 0x00 "LCDC_LAYER0_RESXY_REG,Layer0 Res XY" hexmask.long.word 0x00 16.--31. 1. " LCDC_L0_RES_X ,Resolution X (Resolution of layer in pixels)" hexmask.long.word 0x00 0.--15. 1. " LCDC_L0_RES_Y ,Resolution Y (Resolution of layer in pixels)" group.long 0x38++0x3 line.long 0x00 "LCDC_LAYER0_SIZEXY_REG,Layer0 Size XY" hexmask.long.word 0x00 16.--31. 1. " LCDC_L0_SIZE_X ,Size X (Size of layer in pixels)" hexmask.long.word 0x00 0.--15. 1. " LCDC_L0_SIZE_Y ,Size Y (Size of layer in pixels)" group.long 0x34++0x3 line.long 0x00 "LCDC_LAYER0_STARTXY_REG,Layer0 Start XY" hexmask.long.word 0x00 16.--31. 1. " LCDC_L0_START_X ,Start X (offset pixels)" hexmask.long.word 0x00 0.--15. 1. " LCDC_L0_START_Y ,Start Y (offset pixels)" group.long 0x40++0x3 line.long 0x00 "LCDC_LAYER0_STRIDE_REG,Layer0 Stride" bitfld.long 0x00 19.--20. " LCDC_L0_FIFO_THR ,Layer dma fifo threshold burst start_00: half fifo (default)_01: 2 burst size_10: 4 burst size_11: 8 burst size" "0,1,2,3" bitfld.long 0x00 16.--18. " LCDC_L0_BURST_LEN ,Layer burst length_000: 16-beats (default)_001: 2-beats_010: 4-beats_011: 8-beats_100: 16-beats" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. " LCDC_L0_STRIDE ,Layer Stride (distance from line to line in bytes)" group.long 0x0++0x3 line.long 0x00 "LCDC_MODE_REG,Display Mode" bitfld.long 0x00 31. " LCDC_MODE_EN ,Mode register._0 : disable_1 : enable" "0,1" bitfld.long 0x00 28. " LCDC_VSYNC_POL ,VSYNC polarity._0: positive_1: negative" "0,1" bitfld.long 0x00 27. " LCDC_HSYNC_POL ,HSYNC polarity._0: positive_1: negative" "0,1" textline " " bitfld.long 0x00 26. " LCDC_DE_POL ,DE polarity._0: positive_1: negative" "0,1" bitfld.long 0x00 23. " LCDC_VSYNC_SCPL ,Set VSYNC for a single cycle per line._0: disable_1: enable" "0,1" bitfld.long 0x00 22. " LCDC_PIXCLKOUT_POL ,Pixel clock out polarity._0: positive_1: negative" "0,1" textline " " bitfld.long 0x00 19. " LCDC_FORCE_BLANK ,Forces output to blank._0: disable_1: enable" "0,1" bitfld.long 0x00 17. " LCDC_SFRAME_UPD ,Single frame update._0: disable_1: enable" "0,1" bitfld.long 0x00 11. " LCDC_PIXCLKOUT_SEL ,Selects the pixel out clock for the display._0: based on the pixel pipeline clock_1: based on the format pipeline clock_See also the LCDC_CLKCTRL_REG" "0,1" textline " " bitfld.long 0x00 5.--8. " LCDC_OUT_MODE ,Selection of the output mode_0000: Parallel RGB_1000: JDI MIP_All the other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " LCDC_MIPI_OFF ,MIPI off._0: disabled_1: enabled" "0,1" bitfld.long 0x00 3. " LCDC_FORM_OFF ,Formating off_0: disabled_1: enabled" "0,1" textline " " bitfld.long 0x00 1. " LCDC_DSCAN ,Double horizontal scan_0: disabled_1: enabled" "0,1" bitfld.long 0x00 0. " LCDC_TMODE ,Test mode_0: disabled_1: enabled" "0,1" group.long 0xC++0x3 line.long 0x00 "LCDC_RESXY_REG,Resolution X,Y" hexmask.long.word 0x00 16.--31. 1. " LCDC_RES_X ,Resolution X in pixels" hexmask.long.word 0x00 0.--15. 1. " LCDC_RES_Y ,Resolution Y in pixels" group.long 0xFC++0x3 line.long 0x00 "LCDC_STATUS_REG,Status Register" rbitfld.long 0x00 15. " LCDC_JDI_TIM_SW_RST ,JDI timing generation soft reset (active high)" "0,1" rbitfld.long 0x00 14. " LCDC_FRAME_START ,Frame start (active high)" "0,1" rbitfld.long 0x00 13. " LCDC_FRAME_END ,Frame end (active high)" "0,1" textline " " rbitfld.long 0x00 12. " LCDC_DBIB_CMD_PENDING ,Transferring of command in progress._0: idle_1: in progress" "0,1" rbitfld.long 0x00 11. " LCDC_DBIB_CMD_FIFO_FULL ,Command fifo full indication._0: is not full_1: is full" "0,1" rbitfld.long 0x00 10. " LCDC_DBIB_CMD_FIFO_EMPTY_N ,Command fifo empty indication (negative)_0: the fifo is empty_1: the fifo is not empty" "0,1" textline " " rbitfld.long 0x00 8. " LCDC_DBIB_TE ,The DBIB tearing effect signal" "0,1" rbitfld.long 0x00 7. " LCDC_STICKY_UNDERFLOW ,Sticky underflow(clear with write in the LCDC_INTERRUPT_REG)_0: There is no underflow_1: Underflow has been detected.Remains high until to be cleared by performing a write access on the register LCDC_INTERRUPT_REG" "0,1" rbitfld.long 0x00 6. " LCDC_UNDERFLOW ,Underflow on the current transfer._0: There is no underflow_1: Underflow has been detected." "0,1" textline " " rbitfld.long 0x00 5. " LCDC_LAST_ROW ,Last row (Last row is currently displayed)" "0,1" rbitfld.long 0x00 4. " LCDC_STAT_CSYNC ,CSYNC signal level" "0,1" rbitfld.long 0x00 3. " LCDC_STAT_VSYNC ,VSYNC signal level" "0,1" textline " " rbitfld.long 0x00 2. " LCDC_STAT_HSYNC ,HSYNC signal level" "0,1" rbitfld.long 0x00 1. " LCDC_FRAMEGEN_BUSY ,The frame generator is busy (active high)" "0,1" rbitfld.long 0x00 0. " LCDC_STAT_ACTIVE ,Active (When not in vertical blanking)" "0,1" width 0x0B tree.end endif sif !cpuis("DA14691-CM33")&&!cpuis("DA14695-CM33") tree "LRA" base ad:0x50030A00 width 20. group.long 0x44++0x3 line.long 0x00 "LRA_ADC_CTRL1_REG,General Purpose ADC Control Register" rbitfld.long 0x00 31. " LRA_ADC_BUSY ,0:ADC conversion ready._1:ADC conversion in progress" "0,1" hexmask.long.byte 0x00 9.--16. 1. " LRA_ADC_OFFSET ,ADC offset signed value" bitfld.long 0x00 8. " LRA_ADC_TEST_PARAM ,Select which inputs will be enabled on the ADC._0,1 = normal inputs (i.e. both I and Q inputs connected to LRA-current-sense voltage source)_2 = I channel connected to the analog input testbus on PORTS TBD, Q channel is muted._3 =QI channel connected to the analog input testbus on PORTS TBD, I channel is muted._Note: The LRA_ADC_CTRL1_REG[ADC_MUTE] field takes precedence over this test functionality." "0,1" textline " " bitfld.long 0x00 7. " LRA_ADC_TEST_IN_SEL ,Select analog testbus on ADC input" "0,1" bitfld.long 0x00 3.--6. " LRA_ADC_FREQ ,ADC clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " LRA_ADC_SIGN ,Change polarity of ADC input" "0,1" textline " " bitfld.long 0x00 1. " LRA_ADC_MUTE ,0: Normal operation_1: Short the inputs of the ADC (used for DC offset cal)" "0,1" bitfld.long 0x00 0. " LRA_ADC_START ,0: ADC conversion ready._1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero." "0,1" group.long 0x48++0x3 line.long 0x00 "LRA_ADC_CTRL2_REG,Haptic Feedback Driver Current Sense ADC Control Register 2" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_I_WR ,External value for the DC offset compensation in the I path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR." hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_I_WR ,External value for the DC offset compensation in the I path positive side." group.long 0x4C++0x3 line.long 0x00 "LRA_ADC_CTRL3_REG,Haptic Feedback Driver Current Sense ADC Control Register 3" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_Q_WR ,External value for the DC offset compensation in the Q path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR." hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_Q_WR ,External value for the DC offset compensation in the Q path positive side." group.long 0x50++0x3 line.long 0x00 "LRA_ADC_RESULT_REG,General Purpose ADC Result Register" hexmask.long.word 0x00 16.--31. 1. " MAN_FLT_IN ,Manual value to replace the ADC output. Select its use by FLT_IN_SEL" hexmask.long.word 0x00 0.--15. 1. " GP_ADC_VAL ,Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits" group.long 0x3C++0x3 line.long 0x00 "LRA_BRD_HS_REG,LRA Bridge Register" bitfld.long 0x00 11.--14. " TRIM_GAIN ,Current-sensing amplifier gain settings:_0001: x6_0010: x8_0100: x10_1000: x12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " HSGND_TRIM ,HS gnd trim" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--7. " SCP_HS_TRIM ,HS short-circuit protection limit trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 3. " SCP_HS_EN ,HS short-circuit protection enable" "0,1" bitfld.long 0x00 1.--2. " ERC_HS_TRIM ,HS edge-rate control trimming. Lowto-High switching slewing:_00: 25 MV/s_01: 50 MV/s_10: 75 MV/s_11: 100 MV/s" "0,1,2,3" bitfld.long 0x00 0. " ERC_HS_EN ,HS edge-rate control enable" "0,1" group.long 0x38++0x3 line.long 0x00 "LRA_BRD_LS_REG,LRA Bridge Register" bitfld.long 0x00 8.--11. " SCP_LS_TRIM_N ,LSN short-circuit protection limit trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SCP_LS_TRIM_P ,LSP short-circuit protection limit trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " SCP_LS_EN ,LS short-circuit protection enable" "0,1" textline " " bitfld.long 0x00 1.--2. " ERC_LS_TRIM ,LS edge-rate control trimming. High-to-Low switching slewing:_00: 25 MV/s_01: 50 MV/s_10: 75 MV/s_11: 100 MV/s" "0,1,2,3" bitfld.long 0x00 0. " ERC_LS_EN ,LS edge-rate control enable" "0,1" group.long 0x40++0x3 line.long 0x00 "LRA_BRD_STAT_REG,LRA Bridge Staus Register" rbitfld.long 0x00 13. " SCP_HS_OUT ,HS short circuit comparator output" "0,1" rbitfld.long 0x00 12. " SCP_LS_COMP_OUT_N ,LSN short circuit comparator output" "0,1" rbitfld.long 0x00 11. " SCP_LS_COMP_OUT_P ,LSP short circuit comparator output" "0,1" textline " " rbitfld.long 0x00 10. " SC_EVENT_LS ,1: LS short-circuit event detected_0: no LS short-circuit event detected" "0,1" rbitfld.long 0x00 9. " SC_EVENT_HS ,1: HS short-circuit event detected_0: no HS short-circuit event detected" "0,1" rbitfld.long 0x00 8. " LOOP_STAT ,1: Loop saturation detected_0: Loop not saturated" "0,1" textline " " rbitfld.long 0x00 7. " LSN_ON ,LSN control status" "0,1" rbitfld.long 0x00 6. " LSP_ON ,LSP control status" "0,1" rbitfld.long 0x00 5. " HSN_ON ,HSN control status" "0,1" textline " " rbitfld.long 0x00 4. " HSP_ON ,HSP control status" "0,1" rbitfld.long 0x00 3. " LSN_STAT ,LSN power FET gate actual status" "0,1" rbitfld.long 0x00 2. " LSP_STAT ,LSP power FET gate actual status" "0,1" textline " " rbitfld.long 0x00 1. " HSN_STAT ,HSN power FET gate actual status" "0,1" rbitfld.long 0x00 0. " HSP_STAT ,HSP power FET gate actual status" "0,1" group.long 0x0++0x3 line.long 0x00 "LRA_CTRL1_REG,General Purpose LRA Control Register" rbitfld.long 0x00 24.--27. " SMP_IDX ,Current bin index (0-15). Check if equal to IRQ_IDX before and/or after updating HALF_PERIOD with ISR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " IRQ_SCP_EVENT_EN ,0 = interrupt scp event disabled_1 = interupt scp event enabled" "0,1" bitfld.long 0x00 17. " IRQ_ADC_EN ,0 = interrupt adc disabled_1 = interupt adc enabled" "0,1" textline " " bitfld.long 0x00 16. " IRQ_CTRL_EN ,0 = interrupt controller disabled_1 = interupt controller enabled" "0,1" bitfld.long 0x00 12.--15. " IRQ_IDX ,At which sample index an IRQ will be generated (0-15). When IRQ_IDX < 8, IRQs are generated at both half cycles (IRQ_IDX and IRQ_IDX+8), otherwise only in the second half cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " IRQ_DIV ,Divider value of the interrupt request. Number of LRA/ERM periods, between successive IRQs. 0,1=every (half) cycle, depending on IRQ_IDX; 2=every second cycle, IRQ at the end of first or both half cycles (based on IRQ_IDX), etc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SMP_SEL ,Select which samples to store for the resonance control algorithm._0=Sense voltage after down-sampling_1=Error voltage (after subtraction of VREF and down-sampled sense voltgae input)_2=Duty cycle signal after loop-filter_3=Duty cycle signal after summation with DREF" "0,1,2,3" bitfld.long 0x00 5. " PULLDOWN_EN ,LXP and LXN node pull down enbale, when SC_EVENT=0 && LOOP_EN=0" "0,1" bitfld.long 0x00 4. " LOOP_EN ,0=disable loop_1=enable loop" "0,1" textline " " bitfld.long 0x00 3. " LDO_EN ,0=lra ldo disabled_1=lra ldo enabled" "0,1" bitfld.long 0x00 2. " ADC_EN ,0=lra adc disabled_1=lra adc enabled" "0,1" bitfld.long 0x00 1. " HBRIDGE_EN ,0=hbridge disabled_1=hbridge enabled" "0,1" textline " " bitfld.long 0x00 0. " LRA_EN ,0=lra controller disabled_1=lra controller enabled" "0,1" group.long 0x4++0x3 line.long 0x00 "LRA_CTRL2_REG,General Purpose LRA Control Register" hexmask.long.word 0x00 16.--31. 1. " HALF_PERIOD ,Half of the LRA period, in units of 4 ms (= 125 kHz divided by the resonant frequency of the LRA)" bitfld.long 0x00 5. " AUTO_MODE ,Automatic frequency control (0=disabled;, 1=enabled, not yet implemented)" "0,1" bitfld.long 0x00 4. " SMP_MODE ,Sampling mode for data aiding automatic resonance control (0=averaging, 1=last sample)" "0,1" textline " " bitfld.long 0x00 3. " POLARITY ,Polarity of the square wave (0=normal; 1=inverted); Use for rapid stop" "0,1" bitfld.long 0x00 2. " FLT_IN_SEL ,0 = normal operation_1 = ADC output overruled by register value TBD" "0,1" bitfld.long 0x00 0.--1. " PWM_MODE ,PWM pulse placement: 0=middle, 1=left, 2=right, 3=alternate" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "LRA_CTRL3_REG,General Purpose LRA Control Register" hexmask.long.word 0x00 16.--31. 1. " VREF ,Voltage reference for haptic feedback driver (1 bit sign + 7 bits integer + 8 bits fractional. (range -128 ... +127.99)._The voltage is computed based on the desired reference current (IREF) that flows into the haptic device._VREF = IREF*TRIM_GAIN*128/2.4, with IREF in Amperes and TRIM_GAIN = 6, 8 (default), 10 or 12 as defined in LRA_BRD_HS_REG" hexmask.long.word 0x00 0.--15. 1. " DREF ,Duty cycle reference, start value from which the current control loop settles (1 sign bit, 7 integer bits, 8 fractional bits, -128 ... +127.99). Valid settings 5% through 95% (0x0666 - 0x799A)" group.long 0x58++0x3 line.long 0x00 "LRA_DFT_REG,LRA test Register" bitfld.long 0x00 29.--31. " SPARE ,spare registers bits , currently not used" "0,1,2,3,4,5,6,7" bitfld.long 0x00 28. " SWM_SEL ,0=use SWM from controller_1=use SWM_MAN" "0,1" bitfld.long 0x00 27. " SWM_MAN ,swm manual" "0,1" textline " " bitfld.long 0x00 26. " PWM_SEL ,0=use PWM from controller_1=use PWM_MAN" "0,1" bitfld.long 0x00 25. " PWM_MAN ,pwm manual" "0,1" bitfld.long 0x00 23.--24. " TIMER_TRIM ,20ns unit delay cell trimming bits" "0,1,2,3" textline " " bitfld.long 0x00 21.--22. " TIMER_SCALE_TRIM ,Selection of delay of MAG and DEMAG signal:_00: 60ns_01: 80ns_10: 100ns_11: 120ns" "0,1,2,3" bitfld.long 0x00 20. " DFT_SEL ," "0,1" bitfld.long 0x00 19. " DFT_FORCE_HSPN ,Force HSP and HSN power FETs on:_0: not actived_1: HSP and HSN are forced on" "0,1" textline " " bitfld.long 0x00 18. " DFT_EN_TIMER ,Enable for the timer trimming" "0,1" bitfld.long 0x00 16.--17. " DFT_STALL ,Force state machine in a certain state:_00: No test_01: High-Z_10: Mag_11: Demag" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DFT_CTRL ,Selection of test bus connection" group.long 0x2C++0x3 line.long 0x00 "LRA_FLT_COEF1_REG,LRA Filter Coefficient Register" hexmask.long.word 0x00 16.--31. 1. " FLT_COEF_01 ,Loop filter state-space coefficient a12 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" hexmask.long.word 0x00 0.--15. 1. " FLT_COEF_00 ,Loop filter state-space coefficient a11 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" group.long 0x30++0x3 line.long 0x00 "LRA_FLT_COEF2_REG,LRA Filter Coefficient Register" hexmask.long.word 0x00 16.--31. 1. " FLT_COEF_10 ,Loop filter state-space coefficient a21 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" hexmask.long.word 0x00 0.--15. 1. " FLT_COEF_02 ,Loop filter state-space coefficient b1 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" group.long 0x34++0x3 line.long 0x00 "LRA_FLT_COEF3_REG,LRA Filter Coefficient Register" hexmask.long.word 0x00 16.--31. 1. " FLT_COEF_12 ,Loop filter state-space coefficient b2 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" hexmask.long.word 0x00 0.--15. 1. " FLT_COEF_11 ,Loop filter state-space coefficient a22 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999)" group.long 0xC++0x3 line.long 0x00 "LRA_FLT_SMP1_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_2 ,Second sample in first half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_1 ,First sample in first half-cycle used for resonance control algorithm" group.long 0x10++0x3 line.long 0x00 "LRA_FLT_SMP2_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_4 ,Fourth sample in first half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_3 ,Third sample in first half-cycle used for resonance control algorithm" group.long 0x14++0x3 line.long 0x00 "LRA_FLT_SMP3_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_6 ,Sixth sample in first half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_5 ,Fifth sample in first half-cycle used for resonance control algorithm" group.long 0x18++0x3 line.long 0x00 "LRA_FLT_SMP4_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_8 ,Eighth sample in first half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_7 ,Seventh sample in first half-cycle used for resonance control algorithm" group.long 0x1C++0x3 line.long 0x00 "LRA_FLT_SMP5_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_10 ,Second sample in second half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_9 ,First sample in second half-cycle used for resonance control algorithm" group.long 0x20++0x3 line.long 0x00 "LRA_FLT_SMP6_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_12 ,Fourth sample in second half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_11 ,Third sample in second half-cycle used for resonance control algorithm" group.long 0x24++0x3 line.long 0x00 "LRA_FLT_SMP7_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_14 ,Sixth sample in second half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_13 ,Fifth sample in second half-cycle used for resonance control algorithm" group.long 0x28++0x3 line.long 0x00 "LRA_FLT_SMP8_REG,LRA Sample Register" hexmask.long.word 0x00 16.--31. 1. " LRA_SMP_16 ,Eighth sample in second half-cycle used for resonance control algorithm" hexmask.long.word 0x00 0.--15. 1. " LRA_SMP_15 ,Seventh sample in second half-cycle used for resonance control algorithm" group.long 0x54++0x3 line.long 0x00 "LRA_LDO_REG,LRA LDO Regsiter" rbitfld.long 0x00 31. " LDO_OK ,0: LDO not yet ok_1: LDO voltage is ready" "0,1" bitfld.long 0x00 1. " LDO_TST ,When set to 1, LDO output is connected to the testbus through a test switch" "0,1" bitfld.long 0x00 0. " LDO_VREF_HOLD ,0: Indicates that the reference input is tracked,_1: Indicates that the reference input is sampled" "0,1" width 0x0B tree.end endif tree "MEMCTRL" base ad:0x50050000 width 21. group.long 0x78++0x3 line.long 0x00 "BUSY_RESET_REG," bitfld.long 0x00 30.--31. " BUSY_SPARE ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 28.--29. " BUSY_MOTOR ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 26.--27. " BUSY_TIMER2 ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " BUSY_TIMER ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 22.--23. " BUSY_UART3 ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 20.--21. " BUSY_GPADC ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " BUSY_PDM ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 16.--17. " BUSY_SRC ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 14.--15. " BUSY_PCM ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BUSY_SDADC ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 10.--11. " BUSY_I2C2 ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 8.--9. " BUSY_I2C ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " BUSY_SPI2 ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 4.--5. " BUSY_SPI ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 2.--3. " BUSY_UART2 ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " BUSY_UART ,Clear the BUSY bitfield, by writing the master code which has claimed to this field_Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" group.long 0x74++0x3 line.long 0x00 "BUSY_SET_REG," bitfld.long 0x00 30.--31. " BUSY_SPARE ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 28.--29. " BUSY_MOTOR ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 26.--27. " BUSY_TIMER2 ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " BUSY_TIMER ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 22.--23. " BUSY_UART3 ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 20.--21. " BUSY_GPADC ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " BUSY_PDM ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 16.--17. " BUSY_SRC ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 14.--15. " BUSY_PCM ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BUSY_SDADC ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 10.--11. " BUSY_I2C2 ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 8.--9. " BUSY_I2C ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " BUSY_SPI2 ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 4.--5. " BUSY_SPI ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" bitfld.long 0x00 2.--3. " BUSY_UART2 ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " BUSY_UART ,Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0)._Reading returns 0 to allow read/modify/write to the register" "0,1,2,3" group.long 0x7C++0x3 line.long 0x00 "BUSY_STAT_REG," rbitfld.long 0x00 30.--31. " BUSY_SPARE ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 28.--29. " BUSY_MOTOR ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 26.--27. " BUSY_TIMER2 ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" textline " " rbitfld.long 0x00 24.--25. " BUSY_TIMER ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 22.--23. " BUSY_UART3 ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 20.--21. " BUSY_GPADC ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" textline " " rbitfld.long 0x00 18.--19. " BUSY_PDM ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 16.--17. " BUSY_SRC ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 14.--15. " BUSY_PCM ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" textline " " rbitfld.long 0x00 12.--13. " BUSY_SDADC ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 10.--11. " BUSY_I2C2 ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 8.--9. " BUSY_I2C ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" textline " " rbitfld.long 0x00 6.--7. " BUSY_SPI2 ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 4.--5. " BUSY_SPI ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" rbitfld.long 0x00 2.--3. " BUSY_UART2 ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" textline " " rbitfld.long 0x00 0.--1. " BUSY_UART ,A non-zero value indicates the resource is busy. The value represents which master is using it" "0,1,2,3" group.long 0x20++0x3 line.long 0x00 "CMI_CODE_BASE_REG," hexmask.long.word 0x00 10.--18. 1. " CMI_CODE_BASE_ADDR ,Base address for CMAC code with steps of 1 kB._0x001: 1 kB base address_0x010: 16 kB base address_0x100: 256 kB base address" group.long 0x24++0x3 line.long 0x00 "CMI_DATA_BASE_REG," hexmask.long.tbyte 0x00 2.--18. 1. " CMI_DATA_BASE_ADDR ,Base address for CMAC data with steps of 4 bytes._0x00001: 4 byte base address_0x00010: 64 byte base address_0x00100: 1 kB base address_0x01000: 16 kB base address_0x10000: 256 kB base address" group.long 0x2C++0x3 line.long 0x00 "CMI_END_REG," hexmask.long.word 0x00 10.--18. 1. " CMI_END_ADDR ,End address for CMAC code and data accesses with steps of 1 kB._0x000: accesses up to 1kB are allowed_0x001: accesses up to 2kB are allowed_0x01F: accesses up to 32kB are allowed_0x1FF: accesses up to 512kB are allowed" group.long 0x28++0x3 line.long 0x00 "CMI_SHARED_BASE_REG," hexmask.long.word 0x00 10.--18. 1. " CMI_SHARED_BASE_ADDR ,Base address for CMAC shared data with steps of 1 kB._0x001: 1 kB base address_0x010: 16 kB base address_0x100: 256 kB base address" group.long 0x0++0x3 line.long 0x00 "MEM_CTRL_REG," bitfld.long 0x00 8. " ROM_MARGIN_EN ,ROM read and write margin enable" "0,1" bitfld.long 0x00 4.--7. " ROM_MARGIN_CTRL ,ROM read and write margin control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " RAM_DST ,RAM Disable-Self-Time. When asserted high, overrides the self-timed circuitry and causes the read margin to be controlled by the falling clock edge. Requires RAM_MARGIN to be set to _00_" "0,1" textline " " bitfld.long 0x00 2. " RAM_LPMX ,RAM Transparent Light Sleep (TLS) Core Enable. Assert low to enable the TLS core feature, which will result in lower leakage current._It is required to power-on with this pin high (disabled) until the VDD supply is stable._In case VDD is lowered below nominal-10%, it may be necessary to hold this pin high to maintain data retention" "0,1" bitfld.long 0x00 0.--1. " RAM_MARGIN ,RAM read and write margin control. Setting _10_ is recommended._00: Provides the most margin (slowest speed)._11: Provides the least margin (fastest speed)" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "MEM_PRIO_REG," bitfld.long 0x00 4.--5. " AHB_PRIO ," "0,1,2,3" bitfld.long 0x00 2.--3. " AHB2_PRIO ," "0,1,2,3" bitfld.long 0x00 0.--1. " SNC_PRIO ," "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "MEM_STALL_REG," bitfld.long 0x00 8.--11. " AHB_MAX_STALL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " AHB2_MAX_STALL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SNC_MAX_STALL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "MEM_STATUS2_REG," bitfld.long 0x00 7. " RAM8_OFF_BUT_ACCESS ," "0,1" bitfld.long 0x00 6. " RAM7_OFF_BUT_ACCESS ," "0,1" bitfld.long 0x00 5. " RAM6_OFF_BUT_ACCESS ," "0,1" textline " " bitfld.long 0x00 4. " RAM5_OFF_BUT_ACCESS ," "0,1" bitfld.long 0x00 3. " RAM4_OFF_BUT_ACCESS ," "0,1" bitfld.long 0x00 2. " RAM3_OFF_BUT_ACCESS ," "0,1" textline " " bitfld.long 0x00 1. " RAM2_OFF_BUT_ACCESS ," "0,1" bitfld.long 0x00 0. " RAM1_OFF_BUT_ACCESS ," "0,1" group.long 0xC++0x3 line.long 0x00 "MEM_STATUS_REG," bitfld.long 0x00 13. " CMI_CLEAR_READY ," "0,1" rbitfld.long 0x00 12. " CMI_NOT_READY ," "0,1" rbitfld.long 0x00 8.--11. " AHB2_WR_BUFF_CNT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " AHB_WR_BUFF_CNT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " AHB2_CLR_WR_BUFF ," "0,1" bitfld.long 0x00 2. " AHB_CLR_WR_BUFF ," "0,1" textline " " rbitfld.long 0x00 1. " AHB2_WRITE_BUFF ," "0,1" rbitfld.long 0x00 0. " AHB_WRITE_BUFF ," "0,1" group.long 0x30++0x3 line.long 0x00 "SNC_BASE_REG," hexmask.long.tbyte 0x00 2.--18. 1. " SNC_BASE_ADDRESS ,Base address for SNC interface with steps of 4 bytes._0x00001: 4 byte base address_0x00010: 64 byte base address_0x00100: 1 kB base address_0x01000: 16 kB base address_0x10000: 256 kB base address" width 0x0B tree.end tree "OTPC" base ad:0x30070000 width 16. group.long 0x0++0x3 line.long 0x00 "OTPC_MODE_REG,Mode register" bitfld.long 0x00 6.--7. " OTPC_MODE_PRG_SEL ,Defines the part of the OTP cell that is programmed by the controller during the PROG mode, for each program request that is applied._0x0 : Both normal and redundancy arrays are programmed. This is the normal way of programming._0x1 : Only the normal array is programmed._0x2 : Only the redundancy array is programmed._0x3 : Reserved_The value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The setting will take effect when will be enabled again the PROG mode" "0,1,2,3" bitfld.long 0x00 5. " OTPC_MODE_HT_MARG_EN ,Defines the temperature condition under which is performed a margin read. It affects only the initial margin read (RINI mode) and the programming verification margin read (PVFY)._0 : Regular temperature condition_1 : High temperature condition_The value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The selection will take effect at the next PVFY or RINI mode that will be enabled. The READ mode is not affected by the setting of this configuration bit" "0,1" bitfld.long 0x00 4. " OTPC_MODE_USE_TST_ROW ,Selects the memory area of the OTP cell that will be used._0 - Uses the main memory area of the OTP cell_1 - Uses the test row of the OTP cell_The value of this configuration field can be modified only when the controller is in an inactive mode (PDOWN, DSTBY, STBY). The selection will take effect at the next programming or reading mode that will be enabled" "0,1" textline " " bitfld.long 0x00 0.--2. " OTPC_MODE_MODE ,Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows:_0x0: PDOWN. The power supply of the OTP memory is OFF._0x1: DSTBY. The OTP memory is in deep standby mode (power supply ON and internal LDO OFF)._0x2: STBY. The OTP memory is powered (power supply ON and internal LDO ON, but is not selected._0x3: READ. The OTP memory is in the normal read mode._0x4: PROG. The OTP memory is in programming mode._0x5: PVFY. The OTP memory is in programming verification mode (margin read after programming)._0x6: RINI. The OTP memory is in initial read mode (initial margin read)._0x7: Reserved.__Whenever the OTPC_MODE_REG[MODE] is changing, the status bit OTPC_STAT_REG[OTPC_STAT_MRDY] gets the value zero. The new mode will be ready for use when the OTPC_STAT_MRDY become again 1. During the mode transition the OTPC_MODE_REG[MODE] become read only. Do not try to use or change any function of the controller until the OTPC_STAT_MRDY bit to become equal to 1" "0,1,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x00 "OTPC_PADDR_REG,The address of the word that will be programmed, when the PROG mode is used" hexmask.long.word 0x00 0.--9. 1. " OTPC_PADDR ,The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory._The OTPC_PADDR_REG refers to a word address. The OTPC_PADDR_REG has to be writen after the OTP_PWORD_REG and only if the OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0). A writting to the OTPC_PADDR_REG triggers the controller to start the programming procedure (only if the PROG mode is active)" group.long 0xC++0x3 line.long 0x00 "OTPC_PWORD_REG,The 32-bit word that will be programmed, when the PROG mode is used" hexmask.long 0x00 0.--31. 1. " OTPC_PWORD ,The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP memory, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory._The OTP_PWORD_REG must be written before the OTPC_PADDR_REG and only if OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] = 1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0)." group.long 0x4++0x3 line.long 0x00 "OTPC_STAT_REG,Status register" rbitfld.long 0x00 2. " OTPC_STAT_MRDY ,Indicates the progress of the transition from a mode of operation to a new mode of operation._0 : There is a transition in progress in a new mode of operation . Wait until the transition to be completed._1 : The transition to the new mode of operation has been completed. The function that has been enabled by the new mode can be used. A new mode can be applied._This status bit gets the value zero every time where the OTPC_MODE_REG[MODE] is changing. Do not try to use or change any function of the controller until this status bit to becomes equal to 1" "0,1" rbitfld.long 0x00 1. " OTPC_STAT_PBUF_EMPTY ,Indicates the status of the programming buffer (PBUF)._0 : The PBUF contains the address and the data of a programming request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should not be written as long as this status bit is zero._1 : The PBUF is empty and a new programming request can be registered in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG registers._This status bit gets the value zero every time where a progrmaming is triggered by the OTPC_PADDR_REG (only if the PROG mode is active)" "0,1" rbitfld.long 0x00 0. " OTPC_STAT_PRDY ,Indicates the state of the programming process._0: The controller is busy. A programming is in progress._1: The logic which performs programming is idle" "0,1" group.long 0x10++0x3 line.long 0x00 "OTPC_TIM1_REG,Various timing parameters of the OTP cell" hexmask.long.byte 0x00 24.--30. 1. " OTPC_TIM1_US_T_CSP ,The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for programming. It must be :_- at least 10us_- no more than 100us" bitfld.long 0x00 20.--23. " OTPC_TIM1_US_T_CS ,The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for any kind of read. It must be at least 10us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " OTPC_TIM1_US_T_PL ,The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP. It must be at least 10us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--14. " OTPC_TIM1_CC_T_RD ,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns. This timing parameter refers to the access time of the OTP memory" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. " OTPC_TIM1_CC_T_20NS ,The number of hclk_c clock periods (minus one) that give a time interval that is at least higher than 20 ns" "0,1,2,3" hexmask.long.byte 0x00 0.--6. 1. " OTPC_TIM1_CC_T_1US ,The number of hclk_c clock periods (minus one) that give a time interval equal to 1us. This setting affects all the timing parameters that refer to microseconds, due to that defines the correspondence of a microsecond to a number of hclk_c clock cycles" group.long 0x14++0x3 line.long 0x00 "OTPC_TIM2_REG,Various timing parameters of the OTP cell" bitfld.long 0x00 31. " OTPC_TIM2_US_ADD_CC_EN ,Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds._0 : The extra hclk_c clock cycle is not applied_1 : The extra hclk_c clock cycle is applied" "0,1" bitfld.long 0x00 29.--30. " OTPC_TIM2_US_T_SAS ,The number of microseconds (minus one) that are required after the exit from the deep sleep standby mode and before to become ready to enter in an active mode (reading or programming). It must be at least 2us" "0,1,2,3" bitfld.long 0x00 24.--28. " OTPC_TIM2_US_T_PPH ,The number of microseconds (minus one) that are required after the last programming pulse and before to be disabled the programming mode in the OTP memory. It must be:_- at least 5us_- no more than 20us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 21.--23. " OTPC_TIM2_US_T_VDS ,The number of microseconds (minus one) that are required after the enabling of the power supply of the OTP memory and before to become ready for the enabling of the internal LDO. It must be at least 1us" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " OTPC_TIM2_US_T_PPS ,The number of microseconds (minus one) that are required after the enabling of the programming in the OTP memory and before to be applied the first programming pulse. It must be :_- at least 5us_- no more than 20us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--14. 1. " OTPC_TIM2_US_T_PPR ,The number of microseconds (minus one) for recovery after a programming sequence. It must be :_- at least 5us_- no more than 100us" textline " " bitfld.long 0x00 5.--7. " OTPC_TIM2_US_T_PWI ,The number of microseconds (minus one) between two consecutive programming pulses. It must be :_- at least 1us_- no more than 5us" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " OTPC_TIM2_US_T_PW ,The number of microseconds (minus one) that lasts the programming of each bit. It must be :_- at least 10us_- no more than 20us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PATCH" base ad:0x30090000 width 18. group.long 0x20++0x3 line.long 0x00 "PATCH_ADDR0_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x70++0x3 line.long 0x00 "PATCH_ADDR10_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x78++0x3 line.long 0x00 "PATCH_ADDR11_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x80++0x3 line.long 0x00 "PATCH_ADDR12_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x88++0x3 line.long 0x00 "PATCH_ADDR13_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x90++0x3 line.long 0x00 "PATCH_ADDR14_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x98++0x3 line.long 0x00 "PATCH_ADDR15_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xA0++0x3 line.long 0x00 "PATCH_ADDR16_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xA8++0x3 line.long 0x00 "PATCH_ADDR17_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xB0++0x3 line.long 0x00 "PATCH_ADDR18_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xB8++0x3 line.long 0x00 "PATCH_ADDR19_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x28++0x3 line.long 0x00 "PATCH_ADDR1_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xC0++0x3 line.long 0x00 "PATCH_ADDR20_REG,Patch Address field" hexmask.long.word 0x00 2.--16. 1. " PATCH_ADDR_D ,The value which will be compared with the address on the AHB. If a match occurs, the reading data bus willl be replaced by the value of the corresponding PATCH_DATAx_REG" group.long 0xC8++0x3 line.long 0x00 "PATCH_ADDR21_REG,Patch Address field" hexmask.long.word 0x00 2.--16. 1. " PATCH_ADDR_D ,The value which will be compared with the address on the AHB. If a match occurs, the reading data bus willl be replaced by the value of the corresponding PATCH_DATAx_REG" group.long 0x30++0x3 line.long 0x00 "PATCH_ADDR2_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x38++0x3 line.long 0x00 "PATCH_ADDR3_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x40++0x3 line.long 0x00 "PATCH_ADDR4_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x48++0x3 line.long 0x00 "PATCH_ADDR5_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x50++0x3 line.long 0x00 "PATCH_ADDR6_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x58++0x3 line.long 0x00 "PATCH_ADDR7_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x60++0x3 line.long 0x00 "PATCH_ADDR8_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0x68++0x3 line.long 0x00 "PATCH_ADDR9_REG,Patch Address field" hexmask.long.word 0x00 1.--16. 1. " PATCH_ADDR_C ,The value which will be compared with the address on the AHB. If a match occurs then it is considered as the base address of a function" group.long 0xC4++0x3 line.long 0x00 "PATCH_DATA20_REG,Patch Data field" hexmask.long 0x00 0.--31. 1. " PATCH_DATA ,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG" group.long 0xCC++0x3 line.long 0x00 "PATCH_DATA21_REG,Patch Data field" hexmask.long 0x00 0.--31. 1. " PATCH_DATA ,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG" group.long 0x0++0x3 line.long 0x00 "PATCH_VALID_REG,Validity Control Register" hexmask.long.tbyte 0x00 0.--21. 1. " PATCH_VALID ,Indicates which patch entry is valid. For example, when bit x is high it indicates that entry x is valid, i.e. the values of PATCH_ADDRx_REG / PATCH_DATAx_REG, are effective." width 0x0B tree.end tree "PDC" base ad:0x50000200 width 22. group.long 0x80++0x3 line.long 0x00 "PDC_ACKNOWLEDGE_REG,Clear a pending PDC bit" bitfld.long 0x00 0.--4. " PDC_ACKNOWLEDGE ,Writing to this field acknowledges the PDC IRQ request._The data controls which request is acknowledged" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0++0x3 line.long 0x00 "PDC_CTRL0_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,Selects which individual bit from the selected bank is used for wakup._For the peripheral banks, selected with TRIG_SELECT = 0x2 or 0x3, only the lower 4 bits are considered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,Selects which bank is used as wakeup trigger_When TRIG_SELECT is 0x0, selects GPIO port0 through the WAKEUP block._When TRIG_SELECT is 0x1, selects GPIO port1 through the WAKEUP block._When TRIG_SELECT is 0x2 or 0x3, selects the peripheral IRQ.__peripheral IRQ table:_0x0: Timer_0x1: Timer2_0x2: Timer3_0x3: Timer4_0x4: RTC Alarm/Rollover_0x5: RTC Timer_0x6: CMAC Timer OR wake up from CMAC debugger_0x7: Motor Controller_0x8: XTAL32MRDY_IRQ_0x9: RFDIAG_IRQ_0xA: CMAC2SYS_IRQ OR VBUS Present IRQ OR JTAG present OR Debounced IO_0xB: Sensor Node Controller_0xC to 0xE: reserved_0xF: Software trigger only" "0,1,2,3" group.long 0x28++0x3 line.long 0x00 "PDC_CTRL10_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x2C++0x3 line.long 0x00 "PDC_CTRL11_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x30++0x3 line.long 0x00 "PDC_CTRL12_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PDC_CTRL13_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x38++0x3 line.long 0x00 "PDC_CTRL14_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x3C++0x3 line.long 0x00 "PDC_CTRL15_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "PDC_CTRL1_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "PDC_CTRL2_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,IIf set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "PDC_CTRL3_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "PDC_CTRL4_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "PDC_CTRL5_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x18++0x3 line.long 0x00 "PDC_CTRL6_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "PDC_CTRL7_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x20++0x3 line.long 0x00 "PDC_CTRL8_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x24++0x3 line.long 0x00 "PDC_CTRL9_REG,PDC control register" bitfld.long 0x00 11.--12. " PDC_MASTER ,Chooses which master is triggered when waking up_0x0: entry is disabled._0x1: PD_SYS is woken up and CM33 is triggered_0x2: PD_RAD is woken up and CMAC is triggered_0x3: PD_COM is woken up and SNC is triggered" "0,1,2,3" bitfld.long 0x00 10. " EN_COM ,If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC" "0,1" bitfld.long 0x00 9. " EN_PER ,If set, enables PD_PER" "0,1" textline " " bitfld.long 0x00 8. " EN_TMR ,If set, enables PD_TMR" "0,1" bitfld.long 0x00 7. " EN_XTAL ,If set, the XTAL32M will be started" "0,1" bitfld.long 0x00 2.--6. " TRIG_ID ,For description, see PDC_CTRL0_REG.TRIG_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--1. " TRIG_SELECT ,For description, see PDC_CTRL0_REG.TRIG_SELECT" "0,1,2,3" group.long 0x8C++0x3 line.long 0x00 "PDC_PENDING_CM33_REG,Shows any pending IRQ to CM33" hexmask.long.word 0x00 0.--15. 1. " PDC_PENDING ,Indicates which IRQ ids are pending towards the CM33" group.long 0x90++0x3 line.long 0x00 "PDC_PENDING_CMAC_REG,Shows any pending IRQ to CM33" hexmask.long.word 0x00 0.--15. 1. " PDC_PENDING ,Indicates which IRQ ids are pending towards the CMAC" group.long 0x84++0x3 line.long 0x00 "PDC_PENDING_REG,Shows any pending wakup event" hexmask.long.word 0x00 0.--15. 1. " PDC_PENDING ,Indicates which IRQ ids are pending" group.long 0x88++0x3 line.long 0x00 "PDC_PENDING_SNC_REG,Shows any pending IRQ to SNC" hexmask.long.word 0x00 0.--15. 1. " PDC_PENDING ,Indicates which IRQ ids are pending towards the SensorNodeController" group.long 0x94++0x3 line.long 0x00 "PDC_SET_PENDING_REG,Set a pending PDC bit" bitfld.long 0x00 0.--4. " PDC_SET_PENDING ,Writing to this field sets the PDC wakeup request and IRQ._The data controls which request is acknowledged" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end sif !cpuis("DA14691-CM33")&&!cpuis("DA14695-CM33") tree "PWMLED" base ad:0x50030500 width 28. group.long 0xC++0x3 line.long 0x00 "PWMLED_CTRL_REG,PWM Control register" bitfld.long 0x00 11.--13. " LED2_LOAD_SEL ,Defines LED2 output current: 2.5mA + (LED2_LOAD_SEL*2.5mA). Max = 20mA" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " LED1_LOAD_SEL ,Defines LED1 output current: 2.5mA + (LED1_LOAD_SEL*2.5mA). Max = 20mA" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. " LED2_EN ,0 = LED2 disabled_1 = LED2 enabled" "0,1" textline " " bitfld.long 0x00 6. " LED1_EN ,0 = LED1 disabled_1 = LED1 enabled" "0,1" bitfld.long 0x00 2.--5. " LED_TRIM ,LED current trimming bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " SW_PAUSE_EN ,0 = PWM are not blocked by SW_1 = PWM 1 and 2 are paused" "0,1" textline " " bitfld.long 0x00 0. " PWM_ENABLE ,0 = PWM 1,2 are disabled_1 = PWM 1,2 are enabled" "0,1" group.long 0x0++0x3 line.long 0x00 "PWMLED_DUTY_CYCLE_LED1_REG,Defines duty cycle for PWM1" hexmask.long.byte 0x00 8.--15. 1. " LED1_PWM_START_CYCLE ,Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0" hexmask.long.byte 0x00 0.--7. 1. " LED1_PWM_END_CYCLE ,Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1" group.long 0x4++0x3 line.long 0x00 "PWMLED_DUTY_CYCLE_LED2_REG,Defines duty cycle for PWM2" hexmask.long.byte 0x00 8.--15. 1. " LED2_PWM_START_CYCLE ,Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0" hexmask.long.byte 0x00 0.--7. 1. " LED2_PWM_END_CYCLE ,Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1" group.long 0x8++0x3 line.long 0x00 "PWMLED_FREQUENCY_REG,Defines the PWM frequecny" hexmask.long.byte 0x00 0.--7. 1. " LED_PWM_FREQUENCY ,Defines the frequency of PWM 1 2, period = PWM_CLK * ( FREQ+1)" width 0x0B tree.end endif tree "QSPIC" base ad:0x38000000 width 25. group.long 0x30++0x3 line.long 0x00 "QSPIC_BURSTBRK_REG,Read break sequence in Auto mode" bitfld.long 0x00 20. " QSPIC_SEC_HF_DS ,Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0]). Setting this bit is only useful if QSPIC_BRK_EN =1 and QSPIC_BRK_SZ= 1._0: The controller drives the QSPI bus during the transmission of the QSPIC_BRK_WRD[3:0]._1: The controller leaves the QSPI bus in Hi-Z during the transmission of the QSPIC_BRK_WORD[3:0]" "0,1" bitfld.long 0x00 18.--19. " QSPIC_BRK_TX_MD ,The mode of the QSPI Bus during the transmission of the burst break sequence._0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 17. " QSPIC_BRK_SZ ,The size of Burst Break Sequence_0: One byte (Send QSPIC_BRK_WRD[15:8])_1: Two bytes (Send QSPIC_BRK_WRD[15:0])" "0,1" textline " " bitfld.long 0x00 16. " QSPIC_BRK_EN ,Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode._0: The special command is not applied_1: The special command is applied__This special command is applied by the controller to the external device under the following conditions:_- the controller is in Auto mode_- the QSPIC_INST_MD = 1_- the previous command that has been applied in the external device was read_- the controller want to apply to the external device a command different than the read" "0,1" hexmask.long.word 0x00 0.--15. 1. " QSPIC_BRK_WRD ,This is the value of a special command (read burst break sequence) that is applied by the controller to the external memory device, in order to force the memory device to abandon the continuous read mode" group.long 0xC++0x3 line.long 0x00 "QSPIC_BURSTCMDA_REG,The way of reading in Auto mode (command register A)" bitfld.long 0x00 30.--31. " QSPIC_DMY_TX_MD ,It describes the mode of the SPI bus during the Dummy bytes phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 28.--29. " QSPIC_EXT_TX_MD ,It describes the mode of the SPI bus during the Extra Byte phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 26.--27. " QSPIC_ADR_TX_MD ,It describes the mode of the SPI bus during the address phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " QSPIC_INST_TX_MD ,It describes the mode of the SPI bus during the instruction phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " QSPIC_EXT_BYTE ,The value of an extra byte which will be transferred after address (only if QSPIC_EXT_BYTE_EN= 1). Usually this is the Mode Bits in Dual/Quad SPI I/O instructions" hexmask.long.byte 0x00 8.--15. 1. " QSPIC_INST_WB ,IInstruction Value for Wrapping Burst. This value is the selected instruction when QSPIC_WRAP_MD is equal to 1 and the access is a wrapping burst of length and size described by the bit fields QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_INST ,Instruction Value for Incremental Burst or Single read access. This value is the selected instruction at the cases of incremental burst or single read access. Also this value is used when a wrapping burst is not supported (QSPIC_WRAP_MD)" group.long 0x10++0x3 line.long 0x00 "QSPIC_BURSTCMDB_REG,The way of reading in Auto mode (command register B)" bitfld.long 0x00 15. " QSPIC_DMY_FORCE ,By setting this bit, the number of dummy bytes is forced to be equal to 3. In this case the QSPIC_DMY_NUM field is overruled and has no function._0: The number of dummy bytes is controlled by the QSPIC_DMY_NUM field_1: Three dummy bytes are used. The QSPIC_DMY_NUM is overruled" "0,1" bitfld.long 0x00 12.--14. " QSPIC_CS_HIGH_MIN ,Between the transmissions of two different instructions to the flash memory, the SPI bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles. See the QSPIC_ERS_CS_HI register for some exceptions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " QSPIC_WRAP_SIZE ,It describes the selected data size of a wrapping burst (QSPIC_WRAP_MD)._0x0: byte access (8-bits)_0x1: half word access (16 bits)_0x2: word access (32-bits)_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " QSPIC_WRAP_LEN ,It describes the selected length of a wrapping burst (QSPIC_WRAP_MD)._0x0: 4 beat wrapping burst_0x1: 8 beat wrapping burst_0x2: 16 beat wrapping burst_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 7. " QSPIC_WRAP_MD ,Wrap mode_0: The QSPIC_INST is the selected instruction at any access._1: The QSPIC_INST_WB is the selected instruction at any wrapping burst access of length and size described by the registers QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. In all other cases the QSPIC_INST is the selected instruction. Use this feature only when the serial FLASH memory supports a special instruction for wrapping burst access" "0,1" bitfld.long 0x00 6. " QSPIC_INST_MD ,Instruction mode_0: Transmit instruction at any burst access._1: Transmit instruction only in the first access after the selection of Auto Mode" "0,1" textline " " bitfld.long 0x00 4.--5. " QSPIC_DMY_NUM ,Number of Dummy Bytes__0x0: Zero Dummy Bytes (Don't Send Dummy Bytes)_0x1: Send 1 Dummy Byte_0x2: Send 2 Dummy Bytes_0x3: Send 4 Dummy Bytes__When QSPIC_DMY_FORCE is enabled, the QSPIC_DMY_NUM is overruled. In this case the number of dummy bytes is defined by the QSPIC_DMY_FORCE and is equal to 3, independent of the value of the QSPIC_DMY_NUM" "0,1,2,3" bitfld.long 0x00 3. " QSPIC_EXT_HF_DS ,Extra Half Disable Output_0: if QSPIC_EXT_BYTE_EN=1, is transmitted the complete QSPIC_EXT_BYTE_1: if QSPIC_EXT_BYTE_EN=1, the output is disabled (hi-z) during the transmission of bits [3:0] of QSPIC_EXT_BYTE" "0,1" bitfld.long 0x00 2. " QSPIC_EXT_BYTE_EN ,Extra Byte Enable_0: Don't Send QSPIC_EXT_BYTE_1: Send QSPIC_EXT_BYTE" "0,1" textline " " bitfld.long 0x00 0.--1. " QSPIC_DAT_RX_MD ,It describes the mode of the SPI bus during the data phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" group.long 0x38++0x3 line.long 0x00 "QSPIC_CHCKERASE_REG,Check erase progress in Auto mode" hexmask.long 0x00 0.--31. 1. " QSPIC_CHCKERASE ,Writing any value to this register during erasing, forces the controller to read the flash memory status register. Depending on the value of the Busy bit, it updates the QSPIC_ERASE_EN" group.long 0x0++0x3 line.long 0x00 "QSPIC_CTRLBUS_REG,SPI Bus control register for the Manual mode" bitfld.long 0x00 4. " QSPIC_DIS_CS ,Write 1 to disable the chip select (active low) when the controller is in Manual mode" "0,1" bitfld.long 0x00 3. " QSPIC_EN_CS ,Write 1 to enable the chip select (active low) when the controller is in Manual mode." "0,1" bitfld.long 0x00 2. " QSPIC_SET_QUAD ,Write 1 to set the bus mode in Quad mode when the controller is in Manual mode" "0,1" textline " " bitfld.long 0x00 1. " QSPIC_SET_DUAL ,Write 1 to set the bus mode in Dual mode when the controller is in Manual mode" "0,1" bitfld.long 0x00 0. " QSPIC_SET_SINGLE ,Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode" "0,1" group.long 0x4++0x3 line.long 0x00 "QSPIC_CTRLMODE_REG,Mode Control register" bitfld.long 0x00 13. " QSPIC_USE_32BA ,Controls the length of the address that the external memory device uses._0: The external memory device uses 24 bits address._1: The external memory device uses 32 bits address._The controller uses this bit in order to decide the number of the address bytes that has to transfer to the external device during Auto mode" "0,1" bitfld.long 0x00 12. " QSPIC_BUF_LIM_EN ,This bit has meaning only for the read in auto mode. Defines the behavior of the controller when the internal buffer is full and there are more data to be retrieved for the current burst._0: The access in the flash device is not terminated when the internal buffer has no empty space. In this case the QSPI_SCK clock is blocked until to free space in the internal buffer._1: The access in the flash device is terminated when the internal buffer has no empty space. A new access in the flash device will be initiated when will be requested addresses that are not present in the internal buffer._In both cases the access in the flash device is terminated when there is no any read request" "0,1" bitfld.long 0x00 9.--11. " QSPIC_PCLK_MD ,Read pipe clock delay relative to the falling edge of QSPI_SCK._Refer to QSPI Timing for timing parameters and recommended values: 0 to 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8. " QSPIC_RPIPE_EN ,Controls the use of the data read pipe._0: The read pipe is disabled; the sampling clock is defined according to the QSPIC_RXD_NEG setting._1: The read pipe is enabled. The delay of the sampling clock is defined according to the QSPI_PCLK_MD setting. (Recommended)" "0,1" bitfld.long 0x00 7. " QSPIC_RXD_NEG ,Defines the clock edge that is used for the capturing of the received data, when the read pipe is not active (QSPIC_RPIPE_EN = 0).__0: Sampling of the received data with the positive edge of the QSPI_SCK_1: Sampling of the received data with the negative edge of the QSPI_SCK__The internal QSPI_SCK clock that is used by the controller for the capturing of the received data has a skew in respect of the QSPI_SCK that is received by the external memory device. In order to be improved the timing requirements of the read path, the controller supports a read pipe register with programmable clock delay. See also the QSPIC_RPIPE_EN register" "0,1" bitfld.long 0x00 6. " QSPIC_HRDY_MD ,This configuration bit is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus, in order to not locks the AMBA bus for a long time.__0: Adds wait states via hready signal when an access is performed on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. It is not needed to checked the QSPIC_BUSY of the QSPIC_STATUS_REG._1: The controller don't adds wait states via the hready signal, when is performed access on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. The QSPIC_BUSY bit of the QSPIC_STATUS_REG must be checked in order to be detected the completion of the requested access.__It is applicable only when the controller is in Manual mode. In the case of the Auto mode, the controller always adds wait states via the hready signal" "0,1" textline " " bitfld.long 0x00 5. " QSPIC_IO3_DAT ,The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1" "0,1" bitfld.long 0x00 4. " QSPIC_IO2_DAT ,The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1" "0,1" bitfld.long 0x00 3. " QSPIC_IO3_OEN ,QSPI_IO3 output enable. Use this only in SPI or Dual SPI mode to control /HOLD signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero._0: The QSPI_IO3 pad is input._1: The QSPI_IO3 pad is output" "0,1" textline " " bitfld.long 0x00 2. " QSPIC_IO2_OEN ,QSPI_IO2 output enable. Use this only in SPI or Dual SPI mode to control /WP signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero._0: The QSPI_IO2 pad is input._1: The QSPI_IO2 pad is output" "0,1" bitfld.long 0x00 1. " QSPIC_CLK_MD ,Mode of the generated QSPI_SCK clock_0: Use Mode 0 for the QSPI_CLK. The QSPI_SCK is low when QSPI_CS is high._1: Use Mode 3 for the QSPI_CLK. The QSPI_SCK is high when QSPI_CS is high" "0,1" bitfld.long 0x00 0. " QSPIC_AUTO_MD ,Mode of operation_0: The Manual Mode is selected._1: The Auto Mode is selected._During an erasing the QSPIC_AUTO_MD goes in read only mode (see QSPIC_ERASE_EN)" "0,1" group.long 0x80++0x3 line.long 0x00 "QSPIC_CTR_CTRL_REG,Control register for the decryption engine of the QSPIC" bitfld.long 0x00 0. " QSPIC_CTR_EN ,Controls the AES-CTR decryption feature of the QSPIC, which enables the decryption (on-the-fly) of the data that are retrieved from the flash memory device._0: The AES-CTR decryption is disabled._1: The controller will decrypt the content of the flash memory device that is placed in the address space that is defined by the QSPIC_CTR_SADDR_REG and QSPIC_CTR_EADDR_REG registers. The data that are placed outside the previous space are not decrypted by the QSPIC. The decryption is performed by using the AES-CTR algorithm. The AES key is defined by the QSPIC_CTR_KEY_x_y_REG registers and the nonce value by the QSPIC_CTR_NONCE_x_y_REG registers._This configuration bit has meaning only while the controller is in Auto mode. The on-the-fly decryption is not provided in Manual mode" "0,1" group.long 0x88++0x3 line.long 0x00 "QSPIC_CTR_EADDR_REG,End address of the encrypted content in the QSPI flash" hexmask.long.tbyte 0x00 10.--31. 1. " QSPIC_CTR_EADDR ,Defines the bits [31:10] of the end address in the flash memory, where an encrypted image is placed. The bits [9:0] are considered always as 0x3ff. This has meaning only when the decryption is active. See also the register QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN]" group.long 0x94++0x3 line.long 0x00 "QSPIC_CTR_KEY_0_3_REG,Key bytes 0 to 3 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_0_3 ,Defines the key that is used by the AES-CTR algorithm, when the on-the-fly decryption is enabled ( QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1 ). The size of the decryption key is 256bits or 32 bytes :__K0 K1 K2 K3...K30 K31.__The mapping of the bytes to the corresponding QSPIC_CTR_KEY_X_Y_REG regisers is the following :__{K0, K1, K2, K3} = QSPIC_CTR_KEY_0_3_REG[31:0]_{K4, K5, K6, K7} = QSPIC_CTR_KEY_4_7_REG[31:0]_{K8, K9, K10, K11} = QSPIC_CTR_KEY_8_11_REG[31:0]_{K12, K13, K14, K15} = QSPIC_CTR_KEY_12_15_REG[31:0]_{K16, K17, K18, K19} = QSPIC_CTR_KEY_16_19_REG[31:0]_{K20, K21, K22, K23} = QSPIC_CTR_KEY_20_23_REG[31:0]_{K24, K25, K26, K27} = QSPIC_CTR_KEY_24_27_REG[31:0]_{K28, K29, K30, K31} = QSPIC_CTR_KEY_28_31_REG[31:0]__All these registers make sense only when QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1. Do not perform access to an encrypted address range while the updating process of the decryption key is in progress" group.long 0xA0++0x3 line.long 0x00 "QSPIC_CTR_KEY_12_15_REG,Key bytes 12 to 15 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_12_15 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0xA4++0x3 line.long 0x00 "QSPIC_CTR_KEY_16_19_REG,Key bytes 16 to 19 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_16_19 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0xA8++0x3 line.long 0x00 "QSPIC_CTR_KEY_20_23_REG,Key bytes 20 to 23 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_20_23 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0xAC++0x3 line.long 0x00 "QSPIC_CTR_KEY_24_27_REG,Key bytes 24 to 27 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_24_27 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0xB0++0x3 line.long 0x00 "QSPIC_CTR_KEY_28_31_REG,Key bytes 28 to 31 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_28_31 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0x98++0x3 line.long 0x00 "QSPIC_CTR_KEY_4_7_REG,Key bytes 4 to 7 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_4_7 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0x9C++0x3 line.long 0x00 "QSPIC_CTR_KEY_8_11_REG,Key bytes 8 to 11 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_KEY_8_11 ,See the description in the QSPIC_CTR_KEY_0_3" group.long 0x8C++0x3 line.long 0x00 "QSPIC_CTR_NONCE_0_3_REG,Nonce bytes 0 to 3 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_NONCE_0_3 ,Defines the 8 bytes of the nonce value (N0 - N7) that is used by the AES-CTR algorithm in order to be constructed the counter block (CTRB). The total size of the counter block is 128 bits or 16 bytes :__CTRB0 CTRB1 CTRB2 CTRB3...CTRB14 CTRB15.__The first 8 bytes (CTRB0 - CTRB7) of the counter block consisted by the nonce value._The next 8 bytes of the counter block (CTRB8-CTRB15), are produced automatically by the hardware based on the address offset inside the encrypted image, from where are retrieved the requested data._The mapping of the nonce bytes to the corresponding QSPIC_NONCE_X_Y_REG registers is the following :__{CTRB0, CTRB1, CTRB2, CTRB3} = {N0, N1, N2, N3} = QSPIC_NONCE_0_3_REG[31:0]_{CTRB4, CTRB5, CTRB6, CTRB7} = {N4, N5, N6, N7} = QSPIC_NONCE_4_7_REG[31:0]__All these registers make sense only when QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1.Do not perform access to an encrypted address range while the updating process of the nonce value is in progress" group.long 0x90++0x3 line.long 0x00 "QSPIC_CTR_NONCE_4_7_REG,Nonce bytes 4 to 7 for the AES-CTR algorithm" hexmask.long 0x00 0.--31. 1. " QSPIC_CTR_NONCE_4_7 ,See the description in the QSPIC_NONCE_0_3" group.long 0x84++0x3 line.long 0x00 "QSPIC_CTR_SADDR_REG,Start address of the encrypted content in the QSPI flash" hexmask.long.tbyte 0x00 10.--31. 1. " QSPIC_CTR_SADDR ,Defines the bits [31:10] of the start address in the flash memory, where an encrypted image is placed. The bits [9:0] are considered always as zero. This has meaning only when the decryption is active. See also the register QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN]" group.long 0x20++0x3 line.long 0x00 "QSPIC_DUMMYDATA_REG,Send dummy clocks to SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_DUMMYDATA ,Writing to this register generates a number of clock pulses to the SPI bus. During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The data size of the access to this register can be 32-bits / 16-bits/ 8-bits. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus is equal to 1, 2 or 4 for Single, Dual or Quad SPI mode respectively._This register has meaning only when the controller is in Manual mode" group.long 0x28++0x3 line.long 0x00 "QSPIC_ERASECMDA_REG,The way of erasing in Auto mode (command register A)" hexmask.long.byte 0x00 24.--31. 1. " QSPIC_RES_INST ,The code value of the erase resume instruction" hexmask.long.byte 0x00 16.--23. 1. " QSPIC_SUS_INST ,The code value of the erase suspend instruction" hexmask.long.byte 0x00 8.--15. 1. " QSPIC_WEN_INST ,The code value of the write enable instruction" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_ERS_INST ,The code value of the erase instruction" group.long 0x2C++0x3 line.long 0x00 "QSPIC_ERASECMDB_REG,The way of erasing in Auto mode (command register B)" bitfld.long 0x00 24.--29. " QSPIC_RESSUS_DLY ,Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command)._0: Dont wait. The controller starts immediately to suspend the erase procedure._1..63: The controller waits for at least this number of 222kHz clock cycles before the suspension of erasing. Time starts counting after the end of the previous erase resume command (or the initial erase command)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--19. " QSPIC_ERSRES_HLD ,The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles, before to perform the command of erase or erase resume_15 - 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. " QSPIC_ERS_CS_HI ,After the execution of instructions: write enable, erase, erase suspend and erase resume, the QSPI_CS remains high for at least this number of qspi bus clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--9. " QSPIC_EAD_TX_MD ,The mode of the QSPI Bus during the address phase of the erase instruction_0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 6.--7. " QSPIC_RES_TX_MD ,The mode of the QSPI Bus during the transmission of the resume instruction_0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 4.--5. " QSPIC_SUS_TX_MD ,The mode of the QSPI Bus during the transmission of the suspend instruction._0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " QSPIC_WEN_TX_MD ,The mode of the QSPI Bus during the transmission of the write enable instruction._0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 0.--1. " QSPIC_ERS_TX_MD ,The mode of the QSPI Bus during the instruction phase of the erase instruction_0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" group.long 0x24++0x3 line.long 0x00 "QSPIC_ERASECTRL_REG,QSPI Erase control register" rbitfld.long 0x00 25.--27. " QSPIC_ERS_STATE ,It shows the progress of sector/block erasing (read only)._0x0: No Erase._0x1: Pending erase request_0x2: Erase procedure is running_0x3: Suspended Erase procedure_0x4: Finishing the Erase procedure_0x5..0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " QSPIC_ERASE_EN ,During Manual mode (QSPIC_AUTO_MD = 0). This bit is in read only mode._During Auto mode (QSPIC_AUTO_MD = 1). To request the erasing of the block/sector (QSPIC_ERS_ADDR, 12'b0) write 1 to this bit. This bit is cleared automatically with the end of the erasing. Until the end of erasing the QSPIC_ERASE_EN remains in read only mode. During the same period of time the controller remains in Auto Mode (QSPIC_AUTO_MD goes in read only mode)" "0,1" hexmask.long.tbyte 0x00 4.--23. 1. " QSPIC_ERS_ADDR ,Defines the address of the block/sector that is requested to be erased._If QSPIC_USE_32BA = 0 (24 bits addressing), bits QSPIC_ERASECTRL_REG[23-12] determine the block/ sector address bits [23-12]._QSPIC_ERASECTRL_REG[11-4] are ignored by the controller._If QSPIC_USE_32BA = 1 (32 bits addressing) bits QSPIC_ERASECTRL_REG[23-4] determine the block / sectors address bits [31:12]" group.long 0x3C++0x3 line.long 0x00 "QSPIC_GP_REG,QSPI General Purpose control register" bitfld.long 0x00 3.--4. " QSPIC_PADS_SLEW ,QSPI pads slew rate control. Indicative values under certain conditions:_0: Rise=1.7 V/ns, Fall=1.9 V/ns (weak)_1: Rise=2.0 V/ns, Fall=2.3 V/ns_2: Rise=2.3 V/ns, Fall=2.6 V/ns_3: Rise=2.4 V/ns, Fall=2.7 V/ns (strong)_Conditions: FLASH pin capacitance 6 pF, Vcc=1.8V, T=25C and Idrive=16mA" "0,1,2,3" bitfld.long 0x00 1.--2. " QSPIC_PADS_DRV ,QSPI pads drive current_0: 4 mA_1: 8 mA_2: 12 mA_3: 16 mA" "0,1,2,3" group.long 0x1C++0x3 line.long 0x00 "QSPIC_READDATA_REG,Read data from SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_READDATA ,A read access at this register generates a data transfer from the external memory device to the QSPIC controller. The data is transferred using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits / 8-bits and is equal to the number of the transferred bits._This register has meaning only when the controller is in Manual mode" group.long 0x8++0x3 line.long 0x00 "QSPIC_RECVDATA_REG,Received data for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_RECVDATA ,This register contains the received data when the QSPIC_READDATA_REG register is used in Manual mode, in order to be retrieved data from the external memory device and QSPIC_HRDY_MD=1 && QSPIC_BUSY=0" group.long 0x34++0x3 line.long 0x00 "QSPIC_STATUSCMD_REG,The way of reading the status of external device in Auto mode" bitfld.long 0x00 22. " QSPIC_STSDLY_SEL ,Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register, after an erase or an erase resume command._0: The delay is controlled by the QSPIC_RESSTS_DLY which counts on the qspi clock._1: The delay is controlled by the QSPIC_RESSUS_DLY which counts on the 222 kHz clock" "0,1" bitfld.long 0x00 16.--21. " QSPIC_RESSTS_DLY ,Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction._0: Dont wait. The controller starts to reading the Flash memory status register immediately._1..63: The controller waits for at least this number of QSPI_CLK cycles and afterwards it starts to reading the Flash memory status register. The timer starts to count after the end of the previous erase or erase resume command.__The actual timer that will be used by the controller before the reading of the Flash memory status register is defined by the QSPIC_STSDLY_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " QSPIC_BUSY_VAL ,Defines the value of the Busy bit which means that the flash is busy._0: The flash is busy when the Busy bit is equal to 0._1: The flash is busy when the Busy bit is equal to 1" "0,1" textline " " bitfld.long 0x00 12.--14. " QSPIC_BUSY_POS ,It describes who from the bits of status represents the Busy bit (7 - 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " QSPIC_RSTAT_RX_MD ,The mode of the QSPI Bus during the receive status phase of the read status instruction_0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 8.--9. " QSPIC_RSTAT_TX_MD ,The mode of the QSPI Bus during the instruction phase of the read status instruction._0x0: Single_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_RSTAT_INST ,The code value of the read status instruction._It is transmitted during the instruction phase of the read status instruction" group.long 0x14++0x3 line.long 0x00 "QSPIC_STATUS_REG,The status register of the QSPI controller" rbitfld.long 0x00 0. " QSPIC_BUSY ,The status of the SPI Bus.__0: The SPI Bus is idle_1: The SPI Bus is active. Read data, write data or dummy data activity is in progress.__Has meaning only in Manual mode and only when QSPIC_HRDY_MD = 1" "0,1" group.long 0x40++0x3 line.long 0x00 "QSPIC_UCODE_START,QSPIC uCode memory" hexmask.long 0x00 0.--31. 1. " QSPIC_UCODE_X ,The controller has a dedicated memory cell of 16 words x 32 bits that is used for the storing of the microcode that describes the initialization process of the external flash device. The first word (word 0) of this memory can be accessed by accessing the QSPIC_UCODE_START register. The next words can be accessed by accessing the QSPIC_UCODE_START + 4*X (X=1 .. 15)" group.long 0x18++0x3 line.long 0x00 "QSPIC_WRITEDATA_REG,Write data to SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_WRITEDATA ,Writing to this register is generating a data transfer from the controller to the external memory device. The data written in this register, is then transferred to the memory using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits/ 8-bits and is equal to the number of the transferred bits._This register has meaning only when the controller is in Manual mode" width 0x0B tree.end sif !cpuis("DA14691-CM33") tree "QSPIC2" base ad:0x34000000 width 22. group.long 0x40++0x3 line.long 0x00 "QSPIC2_AWRITECMD_REG,The way of writing in Auto mode when the external device is a serial SRAM" bitfld.long 0x00 14.--18. " QSPIC_WR_CS_HIGH_MIN ,After the execution of the write command, the QSPI_CS remains high for at least this number of QSPI_SCK clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--13. " QSPIC_WR_DAT_TX_MD ,The mode of the SPI Bus during the data phase of the write command._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 10.--11. " QSPIC_WR_ADR_TX_MD ,The mode of the SPI Bus during the adress phase of the write command._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " QSPIC_WR_INST_TX_MD ,The mode of the SPI Bus during the instruction phase of the write command._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. " QSPIC_WR_INST ,This is the value of the instruction that is used, in order to be programmed the external SRAM device" group.long 0x30++0x3 line.long 0x00 "QSPIC2_BURSTBRK_REG,Read break sequence in Auto mode" bitfld.long 0x00 20. " QSPIC_SEC_HF_DS ,Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0]). Setting this bit is only useful if QSPIC_BRK_EN =1 and QSPIC_BRK_SZ= 1._0: The controller drives the SPI bus during the transmission of the QSPIC_BRK_WRD[3:0]._1: The controller leaves the SPI bus in Hi-Z during the transmission of the QSPIC_BRK_WORD[3:0]" "0,1" bitfld.long 0x00 18.--19. " QSPIC_BRK_TX_MD ,The mode of the SPI Bus during the transmission of the read break sequence._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 17. " QSPIC_BRK_SZ ,The size of the read break sequence._0: One byte (Send QSPIC_BRK_WRD[15:8])_1: Two bytes (Send QSPIC_BRK_WRD[15:0])" "0,1" textline " " bitfld.long 0x00 16. " QSPIC_BRK_EN ,Controls the application of a special command (read break sequence) that is used in order to force the device to abandon the continuous read mode._0: The special command is not applied_1: The special command is applied__This special command is applied by the controller to the external device under the following conditions:_- the controller is in Auto mode_- the QSPIC_INST_MD = 1_- the previous command that has been applied in the external device was read_- the controller want to apply to the external device a command different than the read" "0,1" hexmask.long.word 0x00 0.--15. 1. " QSPIC_BRK_WRD ,This is the value of a special command (read break sequence) that is applied by the controller to the external memory device, in order to force the memory device to abandon the continuous read mode" group.long 0xC++0x3 line.long 0x00 "QSPIC2_BURSTCMDA_REG,The way of reading in Auto mode (command register A)" bitfld.long 0x00 30.--31. " QSPIC_DMY_TX_MD ,It describes the mode of the SPI bus during the Dummy bytes phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 28.--29. " QSPIC_EXT_TX_MD ,It describes the mode of the SPI bus during the Extra Byte phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 26.--27. " QSPIC_ADR_TX_MD ,It describes the mode of the SPI bus during the address phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " QSPIC_INST_TX_MD ,It describes the mode of the SPI bus during the instruction phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " QSPIC_EXT_BYTE ,The value of an extra byte which will be transferred after address (only if QSPIC_EXT_BYTE_EN= 1). Usually this is the Mode Bits in Dual/Quad SPI I/O instructions" hexmask.long.byte 0x00 8.--15. 1. " QSPIC_INST_WB ,Instruction Value for Wrapping Burst. This value is the selected instruction when QSPIC_WRAP_MD is equal to 1 and the access is a wrapping burst of length and size described by the bit fields QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_INST ,Instruction Value for Incremental Burst or Single read access. This value is the selected instruction at the cases of incremental burst or single read access. Also this value is used when a wrapping burst is not supported (QSPIC_WRAP_MD)" group.long 0x10++0x3 line.long 0x00 "QSPIC2_BURSTCMDB_REG,The way of reading in Auto mode (command register B)" bitfld.long 0x00 15. " QSPIC_DMY_FORCE ,By setting this bit, the number of dummy bytes is forced to be equal to 3. In this case the QSPIC_DMY_NUM field is overruled and has no function._0: The number of dummy bytes is controlled by the QSPIC_DMY_NUM field_1: Three dummy bytes are used. The QSPIC_DMY_NUM is overruled." "0,1" bitfld.long 0x00 12.--14. " QSPIC_CS_HIGH_MIN ,Between the transmission of two different instructions to the flash memory, the qspi bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles. See the QSPIC_ERS_CS_HI and the QSPIC_WR_CS_HIGH_MIN registers for some exceptions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " QSPIC_WRAP_SIZE ,It describes the selected data size of a wrapping burst (QSPIC_WRAP_MD)._0x0: Byte access (8-bits)_0x1: Half word access (16 bits)_0x2: Word access (32-bits)_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " QSPIC_WRAP_LEN ,It describes the selected length of a wrapping burst (QSPIC_WRAP_MD)._0x0: 4 beat wrapping burst_0x1: 8 beat wrapping burst_0x2: 16 beat wrapping burst_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 7. " QSPIC_WRAP_MD ,Wrap mode_0: The QSPIC_INST is the selected instruction at any access._1: The QSPIC_INST_WB is the selected instruction at any wrapping burst access of length and size described by the registers QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. In all other cases the QSPIC_INST is the selected instruction. Use this feature only when the serial FLASH memory supports a special instruction for wrapping burst access" "0,1" bitfld.long 0x00 6. " QSPIC_INST_MD ,Instruction mode_0: Transmit instruction at any burst access._1: Transmit instruction only in the first access after the selection of Auto Mode" "0,1" textline " " bitfld.long 0x00 4.--5. " QSPIC_DMY_NUM ,Number of Dummy Bytes__0x0: Zero Dummy Bytes (Don't Send Dummy Bytes)_0x1: Send 1 Dummy Byte_0x2: Send 2 Dummy Bytes_0x3: Send 4 Dummy Bytes__When QSPIC_DMY_FORCE is enabled, the QSPIC_DMY_NUM is overruled. In this case the number of dummy bytes is defined by the QSPIC_DMY_FORCE and is equal to 3, independent of the value of the QSPIC_DMY_NUM." "0,1,2,3" bitfld.long 0x00 3. " QSPIC_EXT_HF_DS ,Extra Half Disable Output_0: if QSPIC_EXT_BYTE_EN=1 then transmit the complete QSPIC_EXT_BYTE_1: if QSPIC_EXT_BYTE_EN=1 then disable (hi-z) output during the transmission of bits [3:0] of QSPIC_EXT_BYTE" "0,1" bitfld.long 0x00 2. " QSPIC_EXT_BYTE_EN ,Extra Byte Enable_0: Don't Send QSPIC_EXT_BYTE_1: Send QSPIC_EXT_BYTE" "0,1" textline " " bitfld.long 0x00 0.--1. " QSPIC_DAT_RX_MD ,It describes the mode of the SPI bus during the data phase._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" group.long 0x38++0x3 line.long 0x00 "QSPIC2_CHCKERASE_REG,Check erase progress in Auto mode" hexmask.long 0x00 0.--31. 1. " QSPIC_CHCKERASE ,Writing any value to this register during erasing, forces the controller to read the flash memory status register. Depending on the value of the Busy bit, it updates the QSPIC_ERASE_EN._This register has meaning only when the controller is in Auto mode and there is an erase in progress (QSPIC_ERASE_EN =1). It has no meaning when the external device is a serial SRAM" group.long 0x0++0x3 line.long 0x00 "QSPIC2_CTRLBUS_REG,SPI Bus control register for the Manual mode" bitfld.long 0x00 4. " QSPIC_DIS_CS ,Write 1 to disable the chip select (active low) when the controller is in Manual mode" "0,1" bitfld.long 0x00 3. " QSPIC_EN_CS ,Write 1 to enable the chip select (active low) when the controller is in Manual mode." "0,1" bitfld.long 0x00 2. " QSPIC_SET_QUAD ,Write 1 to set the bus mode in Quad mode when the controller is in Manual mode" "0,1" textline " " bitfld.long 0x00 1. " QSPIC_SET_DUAL ,Write 1 to set the bus mode in Dual mode when the controller is in Manual mode" "0,1" bitfld.long 0x00 0. " QSPIC_SET_SINGLE ,Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode" "0,1" group.long 0x4++0x3 line.long 0x00 "QSPIC2_CTRLMODE_REG,Mode control register" bitfld.long 0x00 16. " QSPIC_CLK_FREE_EN ,Controls the behavior of the QSPI_SCK when the QSPI_CS is high and the QSPIC_CS_MD=1._0: Is produced one QSPI_SCK clock pulse after each 0 to 1 transition in the QSPI_CS._1: The QSPI_SCK clock remains always active, while the QSPI_CS is inactive.__This setting has meaning only when the QSPIC_CS_MD=1" "0,1" bitfld.long 0x00 15. " QSPIC_CS_MD ,Controls the clock edge with which is produced the QSPI_CS signal._0: The QSPI_CS is produced with the rising edge of the QSPI_SCK. The QSPI_SCK is always inactive while the QSPI_CS is high._1: The QSPI_CS is produced with the falling edge of the QSPI_SCK. The behavior of the QSPI_SCK while the QSPI_CS is high, is controlled by the QSPIC_CLK_FREE_EN" "0,1" bitfld.long 0x00 14. " QSPIC_SRAM_EN ,Defines the type of the external device that is connected on the QSPIC controller_0: The external memory device is a serial Flash_1: The external memory device is a serial SRAM__When the external device is a serial SRAM, the erase suspend/ resume functionality of the controller is disabled. In this case the writing of the QSPIC_ERASECTRL_REG[QSPIC_ERASE_EN] bit has no effect. Also, the memory space where the external device is mapped, is considered as writable" "0,1" textline " " bitfld.long 0x00 13. " QSPIC_USE_32BA ,Controls the length of the address that the external memory device uses._0: The external memory device uses 24 bits address._1: The external memory device uses 32 bits address._The controller uses this bit in order to decide the number of the address bytes that has to transfer to the external device during Auto mode" "0,1" bitfld.long 0x00 12. " QSPIC_FORCENSEQ_EN ,Controls the way with which is addressed by the QSPI controller a burst request from the AMBA bus.__0: The controller translates a burst access on the AMBA bus as a burst access on the QSPI bus. That results to the minimum number of command/address phases._1: The controller will split a burst access on the AMBA bus into a number of single accesses on the QSPI bus. That results to a separate command for each beat of the burst. E.g a 4-beat word incremental AMBA read access will be split into 4 different sequences on the QSPI bus: command/address/extra clock/read data. The QSPI_CS will be low only for the time that is needed for each of these single access.__This configuration bit is usefull when the clock frequency of the QSPI bus is much higher than the clock of the AMBA bus. In this case the interval for which the CS remains low is minimized, achieving lower power dissipation with respect of the case where the QSPIC_FORCENSEQ_EN=0, at cost of performance" "0,1" bitfld.long 0x00 9.--11. " QSPIC_PCLK_MD ,Controls the read pipe clock delay relative to the falling edge of QSPI_SCK. Refer to QSPI Timing for timing parameters" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8. " QSPIC_RPIPE_EN ,Controls the use of the data read pipe._0: The read pipe is disabled, the sampling clock is defined according to the QSPIC_RXD_NEG setting._1: The read pipe is enabled. The delay of the sampling clock is defined according to the QSPI_PCLK_MD setting. (Recommended)" "0,1" bitfld.long 0x00 7. " QSPIC_RXD_NEG ,Defines the clock edge that is used for the capturing of the received data, when the read pipe is not active (QSPIC_RPIPE_EN = 0).__0: Sampling of the received data with the positive edge of the QSPI_SCK_1: Sampling of the received data with the negative edge of the QSPI_SCK__The internal QSPI_SCK clock that is used by the controller for the capturing of the received data has a skew in respect of the QSPI_SCK that is received by the external memory device. In order to be improved the timing requirements of the read path, the controller supports a read pipe register with programmable clock delay. See also the QSPIC_RPIPE_EN register" "0,1" bitfld.long 0x00 6. " QSPIC_HRDY_MD ,This configuration bit is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus, in order to not locks the AMBA bus for a long time.__0: Adds wait states via hready signal when an access is performed on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. It is not needed to checked the QSPIC_BUSY of the QSPIC_STATUS_REG._1: The controller don't adds wait states via the hready signal, when is performed access on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. The QSPIC_BUSY bit of the QSPIC_STATUS_REG must be checked in order to be detected the completion of the requested access.__It is applicable only when the controller is in Manual mode. In the case of the Auto mode, the controller always adds wait states via the hready signal" "0,1" textline " " bitfld.long 0x00 5. " QSPIC_IO3_DAT ,The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1" "0,1" bitfld.long 0x00 4. " QSPIC_IO2_DAT ,The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1" "0,1" bitfld.long 0x00 3. " QSPIC_IO3_OEN ,QSPI_IO3 output enable. Use this only in SPI or Dual SPI mode to control /HOLD signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero._0: The QSPI_IO3 pad is input._1: The QSPI_IO3 pad is output" "0,1" textline " " bitfld.long 0x00 2. " QSPIC_IO2_OEN ,QSPI_IO2 output enable. Use this only in SPI or Dual SPI mode to control /WP signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero._0: The QSPI_IO2 pad is input._1: The QSPI_IO2 pad is output" "0,1" bitfld.long 0x00 1. " QSPIC_CLK_MD ,Mode of the generated QSPI_SCK clock__0: Use Mode 0 for the QSPI_CLK. The QSPI_SCK is low when QSPI_CS is high._1: Use Mode 3 for the QSPI_CLK. The QSPI_SCK is high when QSPI_CS is high.__See also the register QSPIC_CS_MD and the QSPIC_CLK_FREE_EN" "0,1" bitfld.long 0x00 0. " QSPIC_AUTO_MD ,Mode of operation_0: The Manual Mode is selected._1: The Auto Mode is selected._During an erasing the QSPIC_AUTO_MD goes in read only mode (see QSPIC_ERASE_EN)" "0,1" group.long 0x20++0x3 line.long 0x00 "QSPIC2_DUMMYDATA_REG,Send dummy clocks to SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_DUMMYDATA ,Writing to this register generates a number of clock pulses to the SPI bus. During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The data size of the access to this register can be 32-bits / 16-bits/ 8-bits. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus is equal to 1, 2 or 4 for Single, Dual or Quad SPI mode respectively._This register has meaning only when the controller is in Manual mode" group.long 0x28++0x3 line.long 0x00 "QSPIC2_ERASECMDA_REG,The way of erasing in Auto mode (command register A)" hexmask.long.byte 0x00 24.--31. 1. " QSPIC_RES_INST ,The code value of the erase resume instruction" hexmask.long.byte 0x00 16.--23. 1. " QSPIC_SUS_INST ,The code value of the erase suspend instruction" hexmask.long.byte 0x00 8.--15. 1. " QSPIC_WEN_INST ,The code value of the write enable instruction" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_ERS_INST ,The code value of the erase instruction" group.long 0x2C++0x3 line.long 0x00 "QSPIC2_ERASECMDB_REG,The way of erasing in Auto mode (command register B)" bitfld.long 0x00 24.--29. " QSPIC_RESSUS_DLY ,Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command)._0x00: Dont wait. The controller starts immediately to suspend the erase procedure._0x01..0x3F: The controller waits for at least this number of 288 KHz clock cycles before the suspension of erasing. Time starts counting after the end of the previous erase resume command (or the initial erase command)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--19. " QSPIC_ERSRES_HLD ,The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles, before to perform the command of erase or erase resume. Allowable range : 0xF - 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. " QSPIC_ERS_CS_HI ,After the execution of instructions: write enable, erase, erase suspend and erase resume, the QSPI_CS remains high for at least this number of QSPI_SCK clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--9. " QSPIC_EAD_TX_MD ,The mode of the SPI Bus during the address phase of the erase instruction_0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 6.--7. " QSPIC_RES_TX_MD ,The mode of the SPI Bus during the transmission of the resume instruction_0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 4.--5. " QSPIC_SUS_TX_MD ,The mode of the SPI Bus during the transmission of the suspend instruction._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " QSPIC_WEN_TX_MD ,The mode of the SPI Bus during the transmission of the write enable instruction._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 0.--1. " QSPIC_ERS_TX_MD ,The mode of the SPI Bus during the instruction phase of the erase instruction_0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" group.long 0x24++0x3 line.long 0x00 "QSPIC2_ERASECTRL_REG,Erase control register" rbitfld.long 0x00 25.--27. " QSPIC_ERS_STATE ,It shows the progress of sector/block erasing (read only)._0x0: No Erase._0x1: Pending erase request_0x2: Erase procedure is running_0x3: Suspended Erase procedure_0x4: Finishing the Erase procedure_0x5..0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " QSPIC_ERASE_EN ,This bit has meaning only when the external device is a serial FLASH (QSPIC_SRAM_EN=0). __During Manual mode (QSPIC_AUTO_MD = 0) : This bit is in read only mode._During Auto mode (QSPIC_AUTO_MD = 1). To request the erasing of the block/sector (QSPIC_ERS_ADDR, 12'b0) write 1 to this bit. This bit is cleared automatically with the end of the erasing. Until the end of erasing the QSPIC_ERASE_EN remains in read only mode. During the same period of time the controller remains in Auto Mode (QSPIC_AUTO_MD goes in read only mode).__In the case where the external device is a serial SRAM (QSPIC_SRAM_EN=1) this bit is in read only mode" "0,1" hexmask.long.tbyte 0x00 4.--23. 1. " QSPIC_ERS_ADDR ,Defines the address of the block/sector that is requested to be erased._If QSPIC_USE_32BA = 0 (24 bits addressing), bits QSPIC_ERASECTRL_REG[23-12] determine the block/ sector address bits [23-12]._QSPIC_ERASECTRL_REG[11-4] are ignored by the controller._If QSPIC_USE_32BA = 1 (32 bits addressing) bits QSPIC_ERASECTRL_REG[23-4] determine the block / sectors address bits [31:12]" group.long 0x3C++0x3 line.long 0x00 "QSPIC2_GP_REG,General purpose QSPIC2 register" bitfld.long 0x00 3.--4. " QSPIC_PADS_SLEW ,QSPI pads slew rate control. Indicative values under certain conditions:_0x0 : Rise=1.7 V/ns, Fall=1.9 V/ns (weak)_0x1 : Rise=2.0 V/ns, Fall=2.3 V/ns_0x2 : Rise=2.3 V/ns, Fall=2.6 V/ns_0x3 : Rise=2.4 V/ns, Fall=2.7 V/ns (strong)_Conditions: FLASH pin capacitance 6pF, Vcc=1.8V, T=25C and Idrive=16mA" "0,1,2,3" bitfld.long 0x00 1.--2. " QSPIC_PADS_DRV ,QSPI pads drive current_0x0 : 4 mA_0x1 : 8 mA_0x2 : 12 mA_0x3 : 16 mA" "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "QSPIC2_MEMBLEN_REG,External memory burst length configuration" hexmask.long.word 0x00 4.--13. 1. " QSPIC_T_CEM_CC ,Defines the maximum allowed time tCEM for which the QSPIC_CS can stay active (QSPI_CS=0). It has meaning only when QSPIC_T_CEM_EN is equal to 1. See also the description of the QSPI_T_CEM_EN for more details.__The tCEM is expressed in number of qspi clock cycles and can be calculated as follows :__tCEM / (qspi_clock_period)__If the result of the above equation is higher than 0x3FF, use the value 0x3FF" bitfld.long 0x00 3. " QSPIC_T_CEM_EN ,This bit enables the controlling of the maximum time tCEM for which the QSPI_CS remains active. It has meaning only when the Auto mode is active (QSPIC_AUTO_MD=1) and the external device is a serial SRAM (QSPIC_SRAM_EN=1). In the case where the external device is a serial Flash (QSPIC_SRAM_EN=0) or the controller is in Manual mode (QSPIC_AUTO_MD=0), this field has no any effect.__This feature is usefull in the case where the external serial device is a dynamic RAM that requires refresh. If the refresh is applied only when the device is in the idle state (QSPI_CS = 1), the time for which the device remains in the active state (QSPI_CS = 0) should be limited by a maximum threshold.__0:There is no any constraint regarding the maximum allowed time for which the QSPI_CS can stay active. This is the case also when QSPIC_SRAM_EN=0 or QSPIC_AUTO_MD=0._1:There is a maximum allowed time interval tCEM for which the QSPI_CS can stay active during a burst access (for reading or writting of data). For the controller this is considered as equal to QSPIC_T_CEM_CC x qspi_clock_period. In the case where the data transfer requires the QSPI_CS to stays active for more than QSPIC_T_CEM_CC qspi clock cycles, the QSPI controller splits the access on the SPI bus in more than one bursts, by inserting inactive periods (QSPI_CS = 0) between them. This will cost extra clock cycles for the realization of the original acceess, due to the additional commands that are required in the SPI bus.__The value in the QSPIC_T_CEM_CC should be updated every time where the frequency of the qspi clock is modified. The qspi clock frequency should not be decreased more than a lowest frequency. This is the lowest frequency that enables the be performed a 32-bit word read and write access, without violating the tCEM timing requirement (the QSPI controller allows to be performed at least the transferring of one beat of the requested burst, independent of the QSPIC_T_CEM_CC limit)" "0,1" bitfld.long 0x00 0.--2. " QSPIC_MEMBLEN ,In this register is defined the expected behavior of the external memory device regarding the length of a burst operation :__0x0: The external memory device is capable to implement incremental burst of unspecified length._0x1: The external memory device implements a wrapping burst of length 4 bytes._0x2: The external memory device implements a wrapping burst of length 8 bytes._0x3: The external memory device implements a wrapping burst of length 16 bytes._0x4: The external memory device implements a wrapping burst of length 32 bytes._0x5: The external memory device implements a wrapping burst of length 64 bytes._0x6 - 0x7 : Reserved__This setting is used by the QSPI controller when the Auto mode is enabled (QSPIC_AUTO_MD=1), in order to handle the various burst requests of the AHB bus, in respect of the requirements of the external memory device._The external memory device may need to be configured by applying special instruction, in order to be defined the kind of the burst operation. This can be implemented by applying this special instruction with the QSPI controller in Manual mode (QSPIC_AUTO_MD=1). Refer to the datasheet of the external device for more information" "0,1,2,3,4,5,6,7" group.long 0x1C++0x3 line.long 0x00 "QSPIC2_READDATA_REG,Read data from SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_READDATA ,A read access at this register generates a data transfer from the external memory device to the QSPIC controller. The data is transferred using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits / 8-bits and is equal to the number of the transferred bits._This register has meaning only when the controller is in Manual mode" group.long 0x8++0x3 line.long 0x00 "QSPIC2_RECVDATA_REG,Received data for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_RECVDATA ,This register contains the received data when the QSPIC_READDATA_REG register is used in Manual mode, in order to be retrieved data from the external memory device and QSPIC_HRDY_MD=1 && QSPIC_BUSY=0" group.long 0x34++0x3 line.long 0x00 "QSPIC2_STATUSCMD_REG,The way of reading the status of external device in Auto mode" bitfld.long 0x00 22. " QSPIC_STSDLY_SEL ,Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register, after an erase or an erase resume command._0: The delay is controlled by the QSPIC_RESSTS_DLY which counts on the qspi clock._1: The delay is controlled by the QSPIC_RESSUS_DLY which counts on the 288 kHz clock" "0,1" bitfld.long 0x00 16.--21. " QSPIC_RESSTS_DLY ,Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction._0x00: Dont wait. The controller starts to reading the Flash memory status register immediately._0x01..0x3F: The controller waits for at least this number of QSPI_CLK cycles and afterwards it starts to reading the Flash memory status register. The timer starts to count after the end of the previous erase or erase resume command.__The actual timer that will be used by the controller before the reading of the Flash memory status register is defined by the QSPIC_STSDLY_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " QSPIC_BUSY_VAL ,Defines the value of the Busy bit which means that the flash is busy._0: The flash is busy when the Busy bit is equal to 0._1: The flash is busy when the Busy bit is equal to 1" "0,1" textline " " bitfld.long 0x00 12.--14. " QSPIC_BUSY_POS ,Defines the bit of the Flash status register which represents the Busy bit (0x7 - 0x0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " QSPIC_RSTAT_RX_MD ,The mode of the SPI Bus during the reception phase of the read status instruction, where the value of status register is retrieved._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" bitfld.long 0x00 8.--9. " QSPIC_RSTAT_TX_MD ,The mode of the SPI Bus during the instruction phase of the read status instruction._0x0: Single SPI_0x1: Dual_0x2: Quad_0x3: Reserved" "0,1,2,3" textline " " hexmask.long.byte 0x00 0.--7. 1. " QSPIC_RSTAT_INST ,The code value of the read status instruction._It is transmitted during the instruction phase of the read status instruction" group.long 0x14++0x3 line.long 0x00 "QSPIC2_STATUS_REG,The status register of the QSPI controller" rbitfld.long 0x00 0. " QSPIC_BUSY ,The status of the SPI Bus.__0: The SPI Bus is idle_1: The SPI Bus is active. Read data, write data or dummy data activity is in progress.__Has meaning only in Manual mode and only when QSPIC_HRDY_MD = 1" "0,1" group.long 0x18++0x3 line.long 0x00 "QSPIC2_WRITEDATA_REG,Write data to SPI Bus for the Manual mode" hexmask.long 0x00 0.--31. 1. " QSPIC_WRITEDATA ,Writing to this register is generating a data transfer from the controller to the external memory device. The data written in this register, is then transferred to the memory using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits/ 8-bits and is equal to the number of the transferred bits._This register has meaning only when the controller is in Manual mode" width 0x0B tree.end endif tree "RFCU" base ad:0x40020000 width 28. group.long 0x28++0x3 line.long 0x00 "RF_ADCI_DC_OFFSET_REG,Must be Retained" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_I_RD ,DC offset compensation in the I path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)" hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_I_RD ,DC offset compensation in the I path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)" group.long 0x2C++0x3 line.long 0x00 "RF_ADCQ_DC_OFFSET_REG,Must be Retained" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_Q_RD ,DC offset compensation in the Q path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)" hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_Q_RD ,DC offset compensation in the Q path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)" group.long 0x40++0x3 line.long 0x00 "RF_ADC_CTRL1_REG,ADC control register" bitfld.long 0x00 14. " ADC_SIGN ,Change polarity of ADC input." "0,1" bitfld.long 0x00 13. " ADC_MUTE ,0: Normal operation_1: Short the inputs of the ADC (used for DC offset cal)" "0,1" bitfld.long 0x00 0. " ADC_DC_OFFSET_SEL ,0: Normal operation (i.e. Use automatically calibrated value)_1: Use ADC_OFFx_y_WR to set the DC offset compensation values in the ADC (x = N or P, y = I or Q" "0,1" group.long 0x44++0x3 line.long 0x00 "RF_ADC_CTRL2_REG,ADC control register" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_I_WR ,External value for the DC offset compensation in the I path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR." hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_I_WR ,External value for the DC offset compensation in the I path positive side." group.long 0x48++0x3 line.long 0x00 "RF_ADC_CTRL3_REG,ADC control register" hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_Q_WR ,External value for the DC offset compensation in the Q path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR." hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_Q_WR ,External value for the DC offset compensation in the Q path positive side." group.long 0xC++0x3 line.long 0x00 "RF_ADPLLDIG_CTRL_REG,Adplldig specific settings register" bitfld.long 0x00 1. " OPENLOOP_RDY_WR ,Overrule value for the openloop_rdy" "0,1" bitfld.long 0x00 0. " OPENLOOP_RDY_SEL ,Overrule the openloop_rdy from adplldig._0: Normal function (default)_1: Overrule the openloop_rdy by OPENLOOP_RDY_WR" "0,1" group.long 0xA0++0x3 line.long 0x00 "RF_ADPLLDIG_RFMON_CTRL_REG,Settings for the ADPLLDIG RFMON block" bitfld.long 0x00 1.--3. " ADPLLDIG_RFMON_MUX_SEL ,Mux select for the RFMON data_'b00x: dem_rfmon_data[31:0]_'b010: {dem_rfmon_data[31:16], adplldig_rfmon_data[15:0]}_'b011: {dem_rfmon_data[31:16], adplldig_rfmon_data[31:16]}_'b100: {adplldig_rfmon_data[31:16], dem_rfmon_data[15:0]}_'b101: {adplldig_rfmon_data[15:0], dem_rfmon_data[15:0]}_'b110: adplldig_rfmon_data_'b111: {adplldig_rfmon_data[15:0], adplldig_rfmon_data[31:16]}___Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " ADPLLDIG_SYNC_CLK_INV ,Invert the clock capturing adplldig_rfmon data_0: Do not invert (default)_1: Invert___Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" "0,1" group.long 0x10++0x3 line.long 0x00 "RF_AGC_EXT_LUT_REG,AGC_LUT register" hexmask.long.word 0x00 0.--9. 1. " AGC_EXT_LUT ,LUT for the AGC value, to be selected by dem_agc from the demodulator._Gain settings 10, 11, 12 (so the last 3) use the value of gain setting 9" group.long 0x0++0x3 line.long 0x00 "RF_ATTR_REG,Radio attributes register" bitfld.long 0x00 24.--27. " PA_POWER_SETTING ,Dynamic setting to control the PA power by enabling units_1 : minimum power__15: maximum power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " IFF_BIAS ,Tuning of the IFF bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--15. " TIA_BIAS ,Tuning of the TIA bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " MIX_BIAS ,Tuning of the Mixer bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " LNA_PWR_MODE ,LNA power mode_0: Low power (default)_1: High performance" "0,1" bitfld.long 0x00 3. " IFF_POLARITY ," "0,1" textline " " bitfld.long 0x00 1. " IFF_IF_MODE ,IFF IF mode_0: 1 Mbps (default)_1: 2 Mbps" "0,1" bitfld.long 0x00 0. " TIA_IF_MODE ,TIA IF mode_0: 1 Mbps (default)_1: 2 Mbps" "0,1" group.long 0x14++0x3 line.long 0x00 "RF_CALSTATE_REG,cal_state read-out register" rbitfld.long 0x00 0.--3. " CALSTATE ,Value of the calstate state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "RF_CAL_CTRL_REG,Calibration FSM control" bitfld.long 0x00 4. " DC_OFFSET_CAL_DIS ,Do not calibrate the VGA2 Offset during Cal cycle" "0,1" bitfld.long 0x00 3. " IFF_CAL_DIS ,Do not calibrate the IFF center frequency during Cal cycle" "0,1" rbitfld.long 0x00 1. " EO_CAL ,End of calibration trigger._Reading returns the eo_cal status signal which can be cleared by writing to RF_IRQ_CTRL_REG.EO_CAL_CLEAR" "0,1" textline " " bitfld.long 0x00 0. " SO_CAL ,Start of calibration trigger.Writing a 1 starts calibration.1Reading returns the calibration status (1 = busy calibrating)." "0,1" group.long 0x98++0x3 line.long 0x00 "RF_IFF_CAL_CAP_STAT_REG,Current CAL_CAP value applied to the IF" rbitfld.long 0x00 0.--3. " IF_CAL_CAP_RD ,Reset value is equal to the reset value of RF_IFF_RESULT_REG[IF_CAL_CAP_RD]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x3 line.long 0x00 "RF_IFF_CC_SET_REG,Must be retained" bitfld.long 0x00 24.--27. " IF_CAL_CAP_2M_SET2 ,Retained WRITE value._The result of the IF_CAL_CAP calibration should be copied from RF_IFF_RESULT_REG to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " IF_CAL_CAP_2M_SET1 ,Retained WRITE value._The result of the IF_CAL_CAP calibration should be copied from RF_IFF_RESULT_REG to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " IF_CAL_CAP_1M_SET2 ,Retained WRITE value._The result of the IF_CAL_CAP calibration should be copied from RF_IFF_RESULT_REG to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " IF_CAL_CAP_1M_SET1 ,Retained WRITE value._The result of the IF_CAL_CAP calibration should be copied from RF_IFF_RESULT_REG to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "RF_IFF_CTRL_REG,IFF control register" bitfld.long 0x00 13.--14. " IFF_DCOC_DAC_REFCUR_CTRL ," "0,1,2,3" bitfld.long 0x00 12. " IFF_COMPLEX_DIS ,Put IF-filter in lowpass configuration" "0,1" bitfld.long 0x00 11. " IF_SELECT_FSM ,'0': use one of the IFF_CC_1M/2M_SET1/2, depending on IFF_IF_MODE and IF_SELSET_GT_'1': use the value from the calibration FSM" "0,1" textline " " bitfld.long 0x00 7.--10. " IF_SEL_SET2_GT ,Setting to control when IF_CAL_CAP_1M/2M_SET2 is used._If AGC > IF_SEL_SET2_GT, SET2 is used.Else, SET1 is used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " RO_TO_PINS ,'0': normal operation;_'1': Enable reference oscillator." "0,1" bitfld.long 0x00 5. " IFF_DCOC_DAC_DIS ,Disable the DC offset current DAC" "0,1" textline " " bitfld.long 0x00 4. " IF_MUTE ,'0': normal operation;_'1': Mute IFF by short circuit of VGA1 input._Note: set TGATE_MIXER_IF to '0' for isolation from the IRM" "0,1" rbitfld.long 0x00 0.--3. " IF_CAL_CAP ,Current value applied to IF_CAL_CAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x3 line.long 0x00 "RF_IFF_RESULT_REG,Not retained" rbitfld.long 0x00 0.--3. " IF_CAL_CAP_RD ,IF calibration result capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x74++0x3 line.long 0x00 "RF_IO_CTRL_REG,IO control register" bitfld.long 0x00 12.--14. " RFIO_TX_TUNE_CAP_TRIM_TX ,Trims the TX tuning cap for TX mode._Step = 320fF._0: Minimum cap (all caps off)__7: Maximum cap (all caps on)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " RFIO_RX_TUNE_CAP_TRIM_TX ,Trims the RX tuning cap for TX mode._Step = 20fF._0: Minimum cap (all caps off)__15: Maximum cap (all caps on)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--6. " RFIO_TX_TUNE_CAP_TRIM_RX ,Trims the TX tuning cap for RX mode._Step = 320fF._0: Minimum cap (all caps off)__7: Maximum cap (all caps on)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " RFIO_RX_TUNE_CAP_TRIM_RX ,Trims the RX tuning cap for RX mode._Step = 20fF._0: Minimum cap (all caps off)__15: Maximum cap (all caps on)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "RF_IRQ_CTRL_REG,IRQ clear register" bitfld.long 0x00 0. " EO_CAL_CLEAR ,Writing any value to this bit clears eo_cal interrupt." "0,1" group.long 0x8++0x3 line.long 0x00 "RF_LDO_STATUS_REG,Read out value of LDO enables" rbitfld.long 0x00 3. " ADPLLDIG_LDO_ZERO_EN_RD ,ADPLLDIG LDO zero enable bit" "0,1" rbitfld.long 0x00 2. " ADPLLDIG_LDO_EN_RD ,ADPLLDIG LDO enable bit" "0,1" rbitfld.long 0x00 1. " RADIO_LDO_ZERO_EN_RD ,Radio LDO zero enable bit" "0,1" textline " " rbitfld.long 0x00 0. " RADIO_LDO_EN_RD ,Radio LDO enable bit" "0,1" group.long 0x58++0x3 line.long 0x00 "RF_LDO_VREF_SEL_REG,Vref sel control register" bitfld.long 0x00 10. " RF_LDO_ADPLLDIG_VREF_SEL ," "0,1" bitfld.long 0x00 9. " RF_LDO_DCO_VREF_SEL ," "0,1" bitfld.long 0x00 8. " RF_LDO_DTC_VREF_SEL ," "0,1" textline " " bitfld.long 0x00 7. " RF_LDO_TDC_VREF_SEL ," "0,1" bitfld.long 0x00 6. " RF_LDO_IFADC_VREF_SEL ," "0,1" bitfld.long 0x00 5. " RF_LDO_IFF_VREF_SEL ," "0,1" textline " " bitfld.long 0x00 4. " RF_LDO_MIX_VREF_SEL ," "0,1" bitfld.long 0x00 3. " RF_LDO_LNA_VREF_SEL ," "0,1" bitfld.long 0x00 2. " RF_LDO_PA_VREF_SEL ," "0,1" textline " " bitfld.long 0x00 1. " RF_LDO_RFIO_VREF_SEL ," "0,1" bitfld.long 0x00 0. " RF_LDO_RADIO_VREF_SEL ," "0,1" group.long 0x78++0x3 line.long 0x00 "RF_LNA_CTRL1_REG,LNA control register" bitfld.long 0x00 20.--24. " LNA_TRIM_GAIN4_HP ,High performance LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 1 and lna_gain_sel > 3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " LNA_TRIM_GAIN3_HP ,High performance LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 1 and lna_gain_sel = 3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " LNA_TRIM_GAIN2_HP ,High performance LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 1 and lna_gain_sel = 2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " LNA_TRIM_GAIN1_HP ,High performance LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 1 and lna_gain_sel = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_TRIM_GAIN0_HP ,High performance LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 1 and lna_gain_sel = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "RF_LNA_CTRL2_REG,LNA control register" bitfld.long 0x00 20.--24. " LNA_TRIM_GAIN4_LP ,Low power LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel > 3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " LNA_TRIM_GAIN3_LP ,Low power LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " LNA_TRIM_GAIN2_LP ,Low power LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5.--9. " LNA_TRIM_GAIN1_LP ,Low power LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_TRIM_GAIN0_LP ,Low power LNA gm trim bias settings for CN_00: Lowest gm trim_10: Nominal gm trim_1F: Highest gm trim_(Used as gm trim bias value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x3 line.long 0x00 "RF_LNA_CTRL3_REG,LNA control register" bitfld.long 0x00 24.--25. " LNA_SPARE ,Spare bits for LNA" "0,1,2,3" bitfld.long 0x00 20.--21. " LNA_MODE_GAIN4_LP ,Low power LNA mode setting_(Used as lna_mode value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel > 3)" "0,1,2,3" bitfld.long 0x00 16.--17. " LNA_MODE_GAIN3_LP ,Low power LNA mode setting_(Used as lna_mode value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 3)" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " LNA_MODE_GAIN2_LP ,Low power LNA mode setting_(Used as lna_mode value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 2)" "0,1,2,3" bitfld.long 0x00 8.--9. " LNA_MODE_GAIN1_LP ,Low power LNA mode setting_(Used as lna_mode value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 1)" "0,1,2,3" bitfld.long 0x00 4.--5. " LNA_MODE_GAIN0_LP ,Low power LNA mode setting_(Used as lna_mode value if RF_ATTR_REG[LNA_PWR_MODE] = 0 and lna_gain_sel = 0)" "0,1,2,3" textline " " bitfld.long 0x00 0.--2. " LNA_TRIM_CASC ,Trims the cascode voltages._0: lower voltage__7: higher voltage" "0,1,2,3,4,5,6,7" group.long 0x64++0x3 line.long 0x00 "RF_MIXER_CTRL1_REG,Mixer control register" bitfld.long 0x00 30. " MIXER_IP2_DAC_EXTEND ,Controls the slope of the IP2 DACs for the 3 LSBs_0: DAC slope normal_1: DAC slope doubled" "0,1" bitfld.long 0x00 24.--29. " MIXER_IP2_DAC_IP_TRIM ,Trims the IP DAC._Step = 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 0_Step = 2* 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 1_0: Lowest voltage__63: Highest voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MIXER_IP2_DAC_IN_TRIM ,Trims the IN DAC._Step = 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 0_Step = 2* 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 1_0: Lowest voltage__63: Highest voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " MIXER_IP2_DAC_QP_TRIM ,Trims the QP DAC._Step = 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 0_Step = 2* 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 1_0: Lowest voltage__63: Highest voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MIXER_IP2_DAC_QN_TRIM ,Trims the QN DAC._Step = 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 0_Step = 2* 3.9mV (LSB) for MIXER_IP2_DAC_EXTEND = 1_0: Lowest voltage__63: Highest voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x68++0x3 line.long 0x00 "RF_MIXER_CTRL2_REG,Mixer control register" bitfld.long 0x00 24.--27. " MIX_SPARE ,Spare for the Mixer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " MIX_CAL_SELECT ,0: use IF_CAL_CAP_1M/2M_SET1, depending on mode. MIX_CAL_CAP_WR is added as offset._1: use MIX_CAL_CAP_WR directly" "0,1" bitfld.long 0x00 8.--11. " MIX_CAL_CAP_WR_2M ,External value for calibration of mixer pole capacitance for 2M mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " MIX_CAL_CAP_WR_1M ,External value for calibration of mixer pole capacitance for 1M mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C++0x3 line.long 0x00 "RF_MIX_CAL_CAP_STAT_REG,Current CAL_CAP value applied to the Mixer" rbitfld.long 0x00 0.--3. " MIX_CAL_CAP_RD ,The reset value should be equal to the reset value of RF_IFF_CC_SET_REG[RF_IFF_CC_1M_SET1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "RF_OVERRULE_REG,Overrule register" bitfld.long 0x00 2.--3. " RX_EN_OVR ,Overrule RX_EN_'b01: disabled._'b1x: enabled._'b00: normal function" "0,1,2,3" bitfld.long 0x00 0.--1. " TX_EN_OVR ,Overrule TX_EN_'b01: disabled._'b1x: enabled._'b00: normal function" "0,1,2,3" group.long 0x4C++0x3 line.long 0x00 "RF_PA_CTRL_REG,PA control register" bitfld.long 0x00 8.--9. " PA_RAMP_STEP_SPEED ,00 no ramping_01 ramp step 125 ns_10 ramp step 250 ns_11 ramp step 500 ns" "0,1,2,3" bitfld.long 0x00 3.--5. " TRIM_DUTY_NEG ,Trims the duty-cycle (current starving) resistor at the nmos side_0: lowest resistance (shorted, fastest falling edge)__7: max resistance (slowest falling edge)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TRIM_DUTY_POS ,Trims the duty-cycle (current starving) resistor at the pmos side_0: lowest resistance (shorted, fastest rising edge)__7: max resistance (slowest rising edge)" "0,1,2,3,4,5,6,7" group.long 0x4++0x3 line.long 0x00 "RF_RADIO_INIT_REG,Radio initialization register" bitfld.long 0x00 24. " RADIO_INIT_AUTOCLEAR ,LDO mode_0: Clear ADPLLDIG_LDO_EN from FW._1: Auto-clear ADPLLDIG_LDO_EN on radio_busy negedge if there is no package in IFS" "0,1" bitfld.long 0x00 17. " ADPLLDIG_HCLK_DIS ,Disable adplldig hclk._0: Do nothing_1: Disable_(It is auto-cleared when ADPLLDIG_HCLK_EN is set to 1)_Remark: Since ADPLLDIG_HCLK_EN has higher priority over ADPLLDIG_HCLK_DIS, ADPLLDIG_HCLK_DIS bit-field cannot be set to 1 with _SetBits()_ commands, which access the two bit-fields at the same time. To be able to ADPLLDIG_HCLK_DIS bit-field to 1, _SetByte()_ command should be used" "0,1" bitfld.long 0x00 16. " RADIO_REGS_RDY ,ADPLLDIG regs loading status bit_(Auto-clear to 0 at phy_busy pos-edge or when ADPLLDIG LDO is off)_0: Loading preferred values is not finished._1: Loading preferred values is finished" "0,1" textline " " bitfld.long 0x00 9. " ADPLLDIG_HCLK_EN ,Enable adplldig hclk._0: Disable_1: Enable_(It is auto-cleared when ADPLLDIG_HCLK_DIS is set to 1)" "0,1" bitfld.long 0x00 8. " ADPLLDIG_HRESET_N ,Reset Adplldig register file_0: Reset state._1: Reset is released" "0,1" bitfld.long 0x00 5. " ADPLLDIG_LDO_EN_WR ,ADPLLDIG LDO EN overrule value" "0,1" textline " " bitfld.long 0x00 4. " ADPLLDIG_LDO_EN_SEL ,Select ADPLLDIG_LDO_EN_WR" "0,1" bitfld.long 0x00 3. " ADPLLDIG_LDO_EN ,ADPLLDIG LDO enable bit" "0,1" bitfld.long 0x00 2. " RADIO_LDO_EN_WR ,Radio LDO EN overrule value" "0,1" textline " " bitfld.long 0x00 1. " RADIO_LDO_EN_SEL ,Select RADIO_LDO_EN_WR" "0,1" bitfld.long 0x00 0. " RADIO_LDO_EN ,Radio LDO enable bit" "0,1" group.long 0xA4++0x3 line.long 0x00 "RF_RDP_CTRL_REG,Exposed radio mode control register" bitfld.long 0x00 4.--5. " RDP_MOD_RATE ,0: The input selected with RDP_MOD_SEL2 is sampled with 32 MHz_1: The input selected with RDP_MOD_SEL2 is sampled with 16 MHz_2: The input selected with RDP_MOD_SEL2 is sampled with 8 MHz_3: Reserved" "0,1,2,3" bitfld.long 0x00 2.--3. " RDP_MOD_SEL2 ,0: Normal mode - Do not use the RDP_DATA_IN[31:0] signals_1: Exposed radio mode - Use the RDP_DATA[15:0] as modulated input_2: Exposed radio mode - Use the RDP_DATA[31:16] as modulated input_3: Reserved" "0,1,2,3" bitfld.long 0x00 1. " RDP_MOD_SEL1 ,Provide TX data via GPIOs for exposed radio mode_0: Normal operation - TX data from CMAC_1: Exposed radio mode - TX data from RDP_TX_DATA and RDP_TX_DATA_VALID" "0,1" textline " " bitfld.long 0x00 0. " RDP_RFCU_SEL ,Provide rx_en/tx_en via GPIOs for exposed radio mode_0: Normal operation - tx_en/rx_en from CMAC_1: Exposed radio mode - tx_en/rx_en from RDP_RX_EN and RDP_TX_EN" "0,1" group.long 0x1C++0x3 line.long 0x00 "RF_REF_OSC_REG," hexmask.long.word 0x00 6.--14. 1. " CNT_CLK ,number of clock pulses corresponding to the value of CNT_RO" bitfld.long 0x00 0.--5. " CNT_RO ,number of reference oscillator periods that need to be counted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x3 line.long 0x00 "RF_RFCU_CTRL_REG,RFCU control register" bitfld.long 0x00 0. " RF_RFCU_CLK_DIV ,Divide the RFCU clock by 2._0: 16 MHz_1: 8 MHz (default)" "0,1" group.long 0x18++0x3 line.long 0x00 "RF_SCAN_FEEDBACK_REG,scan feedback register" group.long 0x30++0x3 line.long 0x00 "RF_SPARE_REG,Spare register for radio" bitfld.long 0x00 28. " RF_SPARE_IN_EN ,Enable reading of the spare inputs from radio" "0,1" rbitfld.long 0x00 24.--27. " RF_SPARE_IN ,Spare inputs from radio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " RF_SPARE_BITS_HV ,Spare bits for High voltage" textline " " hexmask.long.word 0x00 0.--15. 1. " RF_SPARE_BITS ,Spare bits" width 0x0B tree.end tree "RFCU_POWER" base ad:0x40020200 width 24. group.long 0x180++0x3 line.long 0x00 "RF_ALWAYS_EN1_REG," bitfld.long 0x00 31. " ALW_EN_ADPLLDIG_EN ," "0,1" bitfld.long 0x00 30. " ALW_EN_ADPLLDIG_RST ," "0,1" bitfld.long 0x00 29. " ALW_EN_ADPLL_CLK_EN ," "0,1" textline " " bitfld.long 0x00 28. " ALW_EN_ADPLL_DCO_EN ," "0,1" bitfld.long 0x00 27. " ALW_EN_ADC_EN ," "0,1" bitfld.long 0x00 26. " ALW_EN_ADC_CLK_EN ," "0,1" textline " " bitfld.long 0x00 25. " ALW_EN_IFF_BIAS_SH_OPEN ," "0,1" bitfld.long 0x00 24. " ALW_EN_IFF_EN ," "0,1" bitfld.long 0x00 23. " ALW_EN_MIX_BIAS_SH_OPEN ," "0,1" textline " " bitfld.long 0x00 22. " ALW_EN_MIX_EN ," "0,1" bitfld.long 0x00 21. " ALW_EN_LNA_CGM_EN ," "0,1" bitfld.long 0x00 20. " ALW_EN_LNA_CORE_EN ," "0,1" textline " " bitfld.long 0x00 19. " ALW_EN_PA_EN ," "0,1" bitfld.long 0x00 18. " ALW_EN_PA_RAMP_EN ," "0,1" bitfld.long 0x00 17. " ALW_EN_RFIO_BIAS_SH_OPEN ," "0,1" textline " " bitfld.long 0x00 16. " ALW_EN_RFIO_BIAS_EN ," "0,1" bitfld.long 0x00 15. " ALW_EN_RFIO_TX_HARM_EN ," "0,1" bitfld.long 0x00 14. " ALW_EN_RFIO_TX_EN ," "0,1" textline " " bitfld.long 0x00 13. " ALW_EN_RFIO_RX_EN ," "0,1" bitfld.long 0x00 12. " ALW_EN_ADPLLDIG_LDO_LP ," "0,1" bitfld.long 0x00 11. " ALW_EN_ADPLLDIG_LDO_ACTIVERDY ," "0,1" textline " " bitfld.long 0x00 10. " ALW_EN_LNA_LDO_ZERO ," "0,1" bitfld.long 0x00 9. " ALW_EN_LDO_ZERO_EN ," "0,1" bitfld.long 0x00 8. " ALW_EN_ADPLL_DCO_LDO_EN ," "0,1" textline " " bitfld.long 0x00 7. " ALW_EN_ADPLL_DTC_LDO_EN ," "0,1" bitfld.long 0x00 6. " ALW_EN_ADPLL_TDC_LDO_EN ," "0,1" bitfld.long 0x00 5. " ALW_EN_IFFADC_LDO_EN ," "0,1" textline " " bitfld.long 0x00 4. " ALW_EN_IFF_LDO_EN ," "0,1" bitfld.long 0x00 3. " ALW_EN_MIX_LDO_EN ," "0,1" bitfld.long 0x00 2. " ALW_EN_LNA_LDO_EN ," "0,1" textline " " bitfld.long 0x00 1. " ALW_EN_PA_LDO_EN ," "0,1" bitfld.long 0x00 0. " ALW_EN_RFIO_LDO_EN ," "0,1" group.long 0x184++0x3 line.long 0x00 "RF_ALWAYS_EN2_REG," bitfld.long 0x00 14. " ALW_EN_SPARE5 ," "0,1" bitfld.long 0x00 13. " ALW_EN_SPARE4 ," "0,1" bitfld.long 0x00 12. " ALW_EN_SPARE3 ," "0,1" textline " " bitfld.long 0x00 11. " ALW_EN_SPARE2 ," "0,1" bitfld.long 0x00 10. " ALW_EN_SPARE1 ," "0,1" bitfld.long 0x00 9. " ALW_EN_ADPLL_RDY_FOR_DIV ," "0,1" textline " " bitfld.long 0x00 8. " ALW_EN_PHY_RDY4BS ," "0,1" bitfld.long 0x00 7. " ALW_EN_DEM_SIGDETECT_EN ," "0,1" bitfld.long 0x00 6. " ALW_EN_DEM_AGC_UNFREEZE_EN ," "0,1" textline " " bitfld.long 0x00 5. " ALW_EN_DEM_DC_PARCAL_EN ," "0,1" bitfld.long 0x00 4. " ALW_EN_DEM_EN ," "0,1" bitfld.long 0x00 3. " ALW_EN_CAL_EN ," "0,1" textline " " bitfld.long 0x00 2. " ALW_EN_ADPLL_LOBUF_PA_EN ," "0,1" bitfld.long 0x00 1. " ALW_EN_ADPLL_PAIN_EN ," "0,1" bitfld.long 0x00 0. " ALW_EN_ADPLLDIG_RX_EN ," "0,1" group.long 0x124++0x3 line.long 0x00 "RF_CNTRL_TIMER_10_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x128++0x3 line.long 0x00 "RF_CNTRL_TIMER_11_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_tx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_tx/eo_tx." group.long 0x12C++0x3 line.long 0x00 "RF_CNTRL_TIMER_12_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x130++0x3 line.long 0x00 "RF_CNTRL_TIMER_13_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x134++0x3 line.long 0x00 "RF_CNTRL_TIMER_14_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x138++0x3 line.long 0x00 "RF_CNTRL_TIMER_15_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x13C++0x3 line.long 0x00 "RF_CNTRL_TIMER_16_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x140++0x3 line.long 0x00 "RF_CNTRL_TIMER_17_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x144++0x3 line.long 0x00 "RF_CNTRL_TIMER_18_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x148++0x3 line.long 0x00 "RF_CNTRL_TIMER_19_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x100++0x3 line.long 0x00 "RF_CNTRL_TIMER_1_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx" hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/so_tx." group.long 0x14C++0x3 line.long 0x00 "RF_CNTRL_TIMER_20_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x150++0x3 line.long 0x00 "RF_CNTRL_TIMER_21_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x154++0x3 line.long 0x00 "RF_CNTRL_TIMER_22_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x158++0x3 line.long 0x00 "RF_CNTRL_TIMER_23_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x15C++0x3 line.long 0x00 "RF_CNTRL_TIMER_24_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x160++0x3 line.long 0x00 "RF_CNTRL_TIMER_25_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x164++0x3 line.long 0x00 "RF_CNTRL_TIMER_26_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x168++0x3 line.long 0x00 "RF_CNTRL_TIMER_27_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x16C++0x3 line.long 0x00 "RF_CNTRL_TIMER_28_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x170++0x3 line.long 0x00 "RF_CNTRL_TIMER_29_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x104++0x3 line.long 0x00 "RF_CNTRL_TIMER_2_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/so_tx." group.long 0x174++0x3 line.long 0x00 "RF_CNTRL_TIMER_30_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x178++0x3 line.long 0x00 "RF_CNTRL_TIMER_31_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x108++0x3 line.long 0x00 "RF_CNTRL_TIMER_3_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/so_tx." group.long 0x10C++0x3 line.long 0x00 "RF_CNTRL_TIMER_4_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x110++0x3 line.long 0x00 "RF_CNTRL_TIMER_5_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x114++0x3 line.long 0x00 "RF_CNTRL_TIMER_6_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x118++0x3 line.long 0x00 "RF_CNTRL_TIMER_7_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_tx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_tx/eo_tx." group.long 0x11C++0x3 line.long 0x00 "RF_CNTRL_TIMER_8_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x120++0x3 line.long 0x00 "RF_CNTRL_TIMER_9_REG," hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,Offset w.r.t. end switch instant eo_rx/eo_tx." hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,Offset w.r.t. start switch instant so_rx/eo_tx." group.long 0x0++0x3 line.long 0x00 "RF_ENABLE_CONFIG0_REG," bitfld.long 0x00 5.--9. " RFIO_LDO_EN_DCF_TX ,DCF timer for rfio_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_LDO_EN_DCF_RX ,DCF timer for rfio_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "RF_ENABLE_CONFIG10_REG," bitfld.long 0x00 5.--9. " LNA_LDO_ZERO_DCF_TX ,DCF timer for lna_ldo_zero in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_LDO_ZERO_DCF_RX ,DCF timer for lna_ldo_zero in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x3 line.long 0x00 "RF_ENABLE_CONFIG11_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_LDO_ACTIVERDY_DCF_TX ,DCF timer for adplldig_ldo_activerdy in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_LDO_ACTIVERDY_DCF_RX ,DCF timer for adplldig_ldo_activerdy in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "RF_ENABLE_CONFIG12_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_LDO_LP_DCF_TX ,DCF timer for adplldig_ldo_lp in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_LDO_LP_DCF_RX ,DCF timer for adplldig_ldo_lp in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x34++0x3 line.long 0x00 "RF_ENABLE_CONFIG13_REG," bitfld.long 0x00 5.--9. " RFIO_RX_EN_DCF_TX ,DCF timer for rfio_rx_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_RX_EN_DCF_RX ,DCF timer for rfio_rx_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x3 line.long 0x00 "RF_ENABLE_CONFIG14_REG," bitfld.long 0x00 5.--9. " RFIO_TX_EN_DCF_TX ,DCF timer for rfio_tx_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_TX_EN_DCF_RX ,DCF timer for rfio_tx_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3C++0x3 line.long 0x00 "RF_ENABLE_CONFIG15_REG," bitfld.long 0x00 5.--9. " RFIO_TX_HARM_EN_DCF_TX ,DCF timer for rfio_tx_harm_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_TX_HARM_EN_DCF_RX ,DCF timer for rfio_tx_harm_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x3 line.long 0x00 "RF_ENABLE_CONFIG16_REG," bitfld.long 0x00 5.--9. " RFIO_BIAS_EN_DCF_TX ,DCF timer for rfio_bias_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_BIAS_EN_DCF_RX ,DCF timer for rfio_bias_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x44++0x3 line.long 0x00 "RF_ENABLE_CONFIG17_REG," bitfld.long 0x00 5.--9. " RFIO_BIAS_SH_OPEN_DCF_TX ,DCF timer for rfio_bias_sh_open in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RFIO_BIAS_SH_OPEN_DCF_RX ,DCF timer for rfio_bias_sh_open in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x48++0x3 line.long 0x00 "RF_ENABLE_CONFIG18_REG," bitfld.long 0x00 5.--9. " PA_RAMP_EN_DCF_TX ,DCF timer for pa_ramp_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PA_RAMP_EN_DCF_RX ,DCF timer for pa_ramp_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x3 line.long 0x00 "RF_ENABLE_CONFIG19_REG," bitfld.long 0x00 5.--9. " PA_EN_DCF_TX ,DCF timer for pa_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PA_EN_DCF_RX ,DCF timer for pa_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4++0x3 line.long 0x00 "RF_ENABLE_CONFIG1_REG," bitfld.long 0x00 5.--9. " PA_LDO_EN_DCF_TX ,DCF timer for pa_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PA_LDO_EN_DCF_RX ,DCF timer for pa_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x3 line.long 0x00 "RF_ENABLE_CONFIG20_REG," bitfld.long 0x00 5.--9. " LNA_CORE_EN_DCF_TX ,DCF timer for lna_core_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_CORE_EN_DCF_RX ,DCF timer for lna_core_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x3 line.long 0x00 "RF_ENABLE_CONFIG21_REG," bitfld.long 0x00 5.--9. " LNA_CGM_EN_DCF_TX ,DCF timer for lna_cgm_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_CGM_EN_DCF_RX ,DCF timer for lna_cgm_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x3 line.long 0x00 "RF_ENABLE_CONFIG22_REG," bitfld.long 0x00 5.--9. " MIX_EN_DCF_TX ,DCF timer for mix_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MIX_EN_DCF_RX ,DCF timer for mix_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x3 line.long 0x00 "RF_ENABLE_CONFIG23_REG," bitfld.long 0x00 5.--9. " MIX_BIAS_SH_OPEN_DCF_TX ,DCF timer for mix_bias_sh_open in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MIX_BIAS_SH_OPEN_DCF_RX ,DCF timer for mix_bias_sh_open in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x60++0x3 line.long 0x00 "RF_ENABLE_CONFIG24_REG," bitfld.long 0x00 5.--9. " IFF_EN_DCF_TX ,DCF timer for iff_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IFF_EN_DCF_RX ,DCF timer for iff_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x64++0x3 line.long 0x00 "RF_ENABLE_CONFIG25_REG," bitfld.long 0x00 5.--9. " IFF_BIAS_SH_OPEN_DCF_TX ,DCF timer for iff_bias_sh_open in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IFF_BIAS_SH_OPEN_DCF_RX ,DCF timer for iff_bias_sh_open in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68++0x3 line.long 0x00 "RF_ENABLE_CONFIG26_REG," bitfld.long 0x00 5.--9. " ADC_CLK_EN_DCF_TX ,DCF timer for adc_clk_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADC_CLK_EN_DCF_RX ,DCF timer for adc_clk_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6C++0x3 line.long 0x00 "RF_ENABLE_CONFIG27_REG," bitfld.long 0x00 5.--9. " ADC_EN_DCF_TX ,DCF timer for adc_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADC_EN_DCF_RX ,DCF timer for adc_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x3 line.long 0x00 "RF_ENABLE_CONFIG28_REG," bitfld.long 0x00 5.--9. " ADPLL_DCO_EN_DCF_TX ,DCF timer for adpll_dco_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_DCO_EN_DCF_RX ,DCF timer for adpll_dco_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x3 line.long 0x00 "RF_ENABLE_CONFIG29_REG," bitfld.long 0x00 5.--9. " ADPLL_CLK_EN_DCF_TX ,DCF timer for adpll_clk_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_CLK_EN_DCF_RX ,DCF timer for adpll_clk_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8++0x3 line.long 0x00 "RF_ENABLE_CONFIG2_REG," bitfld.long 0x00 5.--9. " LNA_LDO_EN_DCF_TX ,DCF timer for lna_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LNA_LDO_EN_DCF_RX ,DCF timer for lna_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x78++0x3 line.long 0x00 "RF_ENABLE_CONFIG30_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_RST_DCF_TX ,DCF timer for adplldig_rst in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_RST_DCF_RX ,DCF timer for adplldig_rst in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "RF_ENABLE_CONFIG31_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_EN_DCF_TX ,DCF timer for adplldig_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_EN_DCF_RX ,DCF timer for adplldig_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x3 line.long 0x00 "RF_ENABLE_CONFIG32_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_RX_EN_DCF_TX ,DCF timer for adplldig_rx_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_RX_EN_DCF_RX ,DCF timer for adplldig_rx_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x3 line.long 0x00 "RF_ENABLE_CONFIG33_REG," bitfld.long 0x00 5.--9. " ADPLLDIG_PAIN_EN_DCF_TX ,DCF timer for adplldig_pain_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLLDIG_PAIN_EN_DCF_RX ,DCF timer for adplldig_pain_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x3 line.long 0x00 "RF_ENABLE_CONFIG34_REG," bitfld.long 0x00 5.--9. " ADPLL_LOBUF_PA_EN_DCF_TX ,DCF timer for adpll_lobuf_pa_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_LOBUF_PA_EN_DCF_RX ,DCF timer for adpll_lobuf_pa_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x3 line.long 0x00 "RF_ENABLE_CONFIG35_REG," bitfld.long 0x00 5.--9. " CAL_EN_DCF_TX ,DCF timer for cal_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " CAL_EN_DCF_RX ,DCF timer for cal_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x90++0x3 line.long 0x00 "RF_ENABLE_CONFIG36_REG," bitfld.long 0x00 5.--9. " DEM_EN_DCF_TX ,DCF timer for dem_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEM_EN_DCF_RX ,DCF timer for dem_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x94++0x3 line.long 0x00 "RF_ENABLE_CONFIG37_REG," bitfld.long 0x00 5.--9. " SPARE_DEM_DC_PARCAL_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEM_DC_PARCAL_EN_DCF_RX ,DCF timer for DC partial Calibration enable in rx mode. It is OR'd with the relevant register bit that enables the partial calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x98++0x3 line.long 0x00 "RF_ENABLE_CONFIG38_REG," bitfld.long 0x00 5.--9. " SPARE_DEM_AGC_UNFREEZE_EN_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEM_AGC_UNFREEZE_EN_DCF_RX ,DCF timer for unfreezing the AGC in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x9C++0x3 line.long 0x00 "RF_ENABLE_CONFIG39_REG," bitfld.long 0x00 5.--9. " SPARE_DEM_SIGDETECT_EN_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEM_SIGDETECT_EN_DCF_RX ,DCF timer for enabling the signal_detect in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC++0x3 line.long 0x00 "RF_ENABLE_CONFIG3_REG," bitfld.long 0x00 5.--9. " MIX_LDO_EN_DCF_TX ,DCF timer for mix_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MIX_LDO_EN_DCF_RX ,DCF timer for mix_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA0++0x3 line.long 0x00 "RF_ENABLE_CONFIG40_REG," bitfld.long 0x00 5.--9. " PHY_RDY4BS_DCF_TX ,DCF timer for PHY_RDY4BS in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PHY_RDY4BS_DCF_RX ,DCF timer for PHY_RDY4BS in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA4++0x3 line.long 0x00 "RF_ENABLE_CONFIG41_REG," bitfld.long 0x00 5.--9. " ADPLL_RDY_FOR_DIV_DCF_TX ,_Ready for the Dividers_ DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_RDY_FOR_DIV_DCF_RX ,_Ready for the Dividers_ DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA8++0x3 line.long 0x00 "RF_ENABLE_CONFIG42_REG," bitfld.long 0x00 5.--9. " SPARE1_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SPARE1_DCF_RX ,Spare DCF timer in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x3 line.long 0x00 "RF_ENABLE_CONFIG43_REG," bitfld.long 0x00 5.--9. " SPARE2_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SPARE2_DCF_RX ,Spare DCF timer in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB0++0x3 line.long 0x00 "RF_ENABLE_CONFIG44_REG," bitfld.long 0x00 5.--9. " SPARE3_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SPARE3_DCF_RX ,Spare DCF timer in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB4++0x3 line.long 0x00 "RF_ENABLE_CONFIG45_REG," bitfld.long 0x00 5.--9. " SPARE4_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SPARE4_DCF_RX ,Spare DCF timer in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB8++0x3 line.long 0x00 "RF_ENABLE_CONFIG46_REG," bitfld.long 0x00 5.--9. " SPARE5_DCF_TX ,Spare DCF timer in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SPARE5_DCF_RX ,Spare DCF timer in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10++0x3 line.long 0x00 "RF_ENABLE_CONFIG4_REG," bitfld.long 0x00 5.--9. " IFF_LDO_EN_DCF_TX ,DCF timer for iff_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IFF_LDO_EN_DCF_RX ,DCF timer for iff_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x3 line.long 0x00 "RF_ENABLE_CONFIG5_REG," bitfld.long 0x00 5.--9. " IFFADC_LDO_EN_DCF_TX ,DCF timer for iffadc_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IFFADC_LDO_EN_DCF_RX ,DCF timer for iffadc_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x3 line.long 0x00 "RF_ENABLE_CONFIG6_REG," bitfld.long 0x00 5.--9. " ADPLL_TDC_LDO_EN_DCF_TX ,DCF timer for adpll_tdc_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_TDC_LDO_EN_DCF_RX ,DCF timer for adpll_tdc_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x3 line.long 0x00 "RF_ENABLE_CONFIG7_REG," bitfld.long 0x00 5.--9. " ADPLL_DTC_LDO_EN_DCF_TX ,DCF timer for adpll_dtc_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_DTC_LDO_EN_DCF_RX ,DCF timer for adpll_dtc_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x3 line.long 0x00 "RF_ENABLE_CONFIG8_REG," bitfld.long 0x00 5.--9. " ADPLL_DCO_LDO_EN_DCF_TX ,DCF timer for adpll_dco_ldo_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " ADPLL_DCO_LDO_EN_DCF_RX ,DCF timer for adpll_dco_ldo_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x24++0x3 line.long 0x00 "RF_ENABLE_CONFIG9_REG," bitfld.long 0x00 5.--9. " LDO_ZERO_EN_DCF_TX ,DCF timer for ldo_zero_en in tx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " LDO_ZERO_EN_DCF_RX ,DCF timer for ldo_zero_en in rx mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x188++0x3 line.long 0x00 "RF_PORT_EN_REG," bitfld.long 0x00 9. " RF_PORT4_TX ,Enable port by TX, timing according RF_CNTRL_TIMER_31_REG" "0,1" bitfld.long 0x00 8. " RF_PORT4_RX ,Enable port by RX, timing according RF_CNTRL_TIMER_31_REG" "0,1" bitfld.long 0x00 7. " RF_PORT3_TX ,Enable port by TX, timing according RF_CNTRL_TIMER_30_REG" "0,1" textline " " bitfld.long 0x00 6. " RF_PORT3_RX ,Enable port by RX, timing according RF_CNTRL_TIMER_30_REG" "0,1" bitfld.long 0x00 5. " RF_PORT2_TX ,Enable port by TX, timing according RF_CNTRL_TIMER_29_REG" "0,1" bitfld.long 0x00 4. " RF_PORT2_RX ,Enable port by RX, timing according RF_CNTRL_TIMER_29_REG" "0,1" textline " " bitfld.long 0x00 3. " RF_PORT1_TX ,Enable port by TX, timing according RF_CNTRL_TIMER_28_REG" "0,1" bitfld.long 0x00 2. " RF_PORT1_RX ,Enable port by RX, timing according RF_CNTRL_TIMER_28_REG" "0,1" bitfld.long 0x00 1. " RF_PORT0_TX ,Enable port by TX, timing according RF_CNTRL_TIMER_27_REG" "0,1" textline " " bitfld.long 0x00 0. " RF_PORT0_RX ,Enable port by RX, timing according RF_CNTRL_TIMER_27_REG" "0,1" group.long 0x18C++0x3 line.long 0x00 "RF_PORT_POL_REG," bitfld.long 0x00 4. " RF_PORT4_POL ,Inverts polarity of RF_PORT" "0,1" bitfld.long 0x00 3. " RF_PORT3_POL ,Inverts polarity of RF_PORT" "0,1" bitfld.long 0x00 2. " RF_PORT2_POL ,Inverts polarity of RF_PORT" "0,1" textline " " bitfld.long 0x00 1. " RF_PORT1_POL ,Inverts polarity of RF_PORT" "0,1" bitfld.long 0x00 0. " RF_PORT0_POL ,Inverts polarity of RF_PORT" "0,1" width 0x0B tree.end tree "RFMON" base ad:0x50040600 width 20. group.long 0x4++0x3 line.long 0x00 "RFMON_ADDR_REG,AHB master start address" hexmask.long 0x00 2.--31. 1. " RFMON_ADDR ,It is the bits [31:2] of base address that is used by the AHB master interface of the controller. Defines the AHB address from where the controller will start to stores data. The bits [1:0] of the address are considered always 0" group.long 0x10++0x3 line.long 0x00 "RFMON_CRV_ADDR_REG,AHB master current address" hexmask.long 0x00 2.--31. 1. " RFMON_CRV_ADDR ,It is the bits [31:2] of AHB address that will be used by the controller in the next memory access. The bits [1:0] are always 0" group.long 0x14++0x3 line.long 0x00 "RFMON_CRV_LEN_REG,The remaining data to be transferred" hexmask.long.tbyte 0x00 0.--16. 1. " RFMON_CRV_LEN ,Indicates the number of words (minus 1) that remain to be transfered" group.long 0x0++0x3 line.long 0x00 "RFMON_CTRL_REG,Control register" bitfld.long 0x00 2. " RFMON_BREQ_FORCE ,Write this bit with 1, when the required throughput for the transferring of the captured data is close to the capacity of the system bus/memory. The controller will be aggressive in the usage of the bus. The availability of the bus will be affected for the remaining masters." "0,1" bitfld.long 0x00 1. " RFMON_CIRC_EN ,Write with 1 to enable the circular mode.In circular mode the controller continuously writes data in to the memory until to be disabled by the software. The data are transferred in the circular buffer in the memory, which is defined by the RFMON_ADDR_REG and the RFMON_LEN_REG registers. The disabling of the controller is realized by writing the RFMON_PACK_EN with 0" "0,1" bitfld.long 0x00 0. " RFMON_PACK_EN ,Starts the capturing of the data from the test bus_0 : There is no capturing of data._1 : The controller captures data._Should be written with 1 in order to start the acquisition of data._If the controller is not in circular mode (RFMON_CIRC_EN = 0) and after capturing a predefined number of words (RFMON_LEN), this bit will be auto cleared._In circular mode (RFMON_CIRC_EN = 1) the RFMON_PACK_EN remains 1 until to be cleared by the software.__Note:_Please check bug2522A_018 (DEM 16Msps data need 16MHz RFCU clock)._Also check bug2522A_019 (ADPLL RFMON metastability issue. Need to run with xtal32M to be safe, and use correct setting for polarity inversion bit)" "0,1" group.long 0x8++0x3 line.long 0x00 "RFMON_LEN_REG,Data length register" hexmask.long.tbyte 0x00 0.--16. 1. " RFMON_LEN ,The number of words (minus one) that should be captured" group.long 0xC++0x3 line.long 0x00 "RFMON_STAT_REG,Status register" bitfld.long 0x00 1. " RFMON_OFLOW_STK ,Indicates that during the transfer of the data, at least one overflow has detected to the fifo._0 : The transfer completed without overflows._1 : At least one overflow occured in the fifo._Write 1 to clear this bit." "0,1" rbitfld.long 0x00 0. " RFMON_ACTIVE ,Indicates the state of the controller._0 : The controller is idle._1 : The controller is active. The capturing process and/or the dma activity is in progress._The controller will be activated (RFMON_ACTIVE == 1), when RFMON_PACK_EN will be written with 1. Will return to inactive state, after the end of the capturing process (RFMON_PACK_EN==0) and the completion of the transfer of all of the data to the memory." "0,1" width 0x0B tree.end tree "RTC" base ad:0x50000400 width 28. group.long 0x18++0x3 line.long 0x00 "RTC_ALARM_ENABLE_REG,RTC Alarm Enable Register" bitfld.long 0x00 5. " RTC_ALARM_MNTH_EN ,Alarm on month enable. Enable to trigger alarm when data specified in Calendar Alarm Register (M_T and M_U) has been reached" "0,1" bitfld.long 0x00 4. " RTC_ALARM_DATE_EN ,Alarm on date enable. Enable to trigger alarm when data specified in Calendar Alarm Register (D_T and D_U) has been reached" "0,1" bitfld.long 0x00 3. " RTC_ALARM_HOUR_EN ,Alarm on hour enable. Enable to trigger alarm when data specified in Time Alarm Register (PM, HR_T and HR_U) has been reached" "0,1" textline " " bitfld.long 0x00 2. " RTC_ALARM_MIN_EN ,Alarm on minute enable. Enable to trigger alarm when data specified in Time Alarm Register (M_T and M_U) has been reached" "0,1" bitfld.long 0x00 1. " RTC_ALARM_SEC_EN ,Alarm on second enable. Enable to trigger alarm when data specified in Time Alarm Register (S_T and S_U) has been reached" "0,1" bitfld.long 0x00 0. " RTC_ALARM_HOS_EN ,Alarm on hundredths of a second enable. Enable to trigger alarm when data specified in Time Alarm Register (H_T and H_U) has been reached" "0,1" group.long 0x14++0x3 line.long 0x00 "RTC_CALENDAR_ALARM_REG,RTC Calendar Alram Register" bitfld.long 0x00 12.--13. " RTC_CAL_D_T ,Date tens. Represented in BCD digit (0-3)" "0,1,2,3" bitfld.long 0x00 8.--11. " RTC_CAL_D_U ,Date units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " RTC_CAL_M_T ,Month tens. Represented in BCD digit (0-1)" "0,1" textline " " bitfld.long 0x00 3.--6. " RTC_CAL_M_U ,Month units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "RTC_CALENDAR_REG,RTC Calendar Register" bitfld.long 0x00 31. " RTC_CAL_CH ,The value in this register has altered since last read. Read and clear" "0,1" bitfld.long 0x00 28.--29. " RTC_CAL_C_T ,Century tens. Represented in BCD digit (1-2)" "0,1,2,3" bitfld.long 0x00 24.--27. " RTC_CAL_C_U ,Century units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " RTC_CAL_Y_T ,Year tens. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RTC_CAL_Y_U ,Year units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--13. " RTC_CAL_D_T ,Date tens. Represented in BCD digit (0-3)" "0,1,2,3" textline " " bitfld.long 0x00 8.--11. " RTC_CAL_D_U ,Date units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " RTC_CAL_M_T ,Month tens. Represented in BCD digit (0-1)" "0,1" bitfld.long 0x00 3.--6. " RTC_CAL_M_U ,Month units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--2. " RTC_DAY ,Day of the week (arbitrary) units. Represented in BCD digit (0-7)" "0,1,2,3,4,5,6,7" group.long 0x0++0x3 line.long 0x00 "RTC_CONTROL_REG,RTC Control Register" bitfld.long 0x00 1. " RTC_CAL_DISABLE ,When this field is set high the RTC stops incrementing the calendar value" "0,1" bitfld.long 0x00 0. " RTC_TIME_DISABLE ,When this field is set high the RTC stops incrementing the time value" "0,1" group.long 0x80++0x3 line.long 0x00 "RTC_EVENT_CTRL_REG,RTC Event Control Register" bitfld.long 0x00 1. " RTC_PDC_EVENT_EN ,0 = Event to PDC is disabled. No clear any pending event_1 = Even to PDC is enabled" "0,1" bitfld.long 0x00 0. " RTC_MOTOR_EVENT_EN ,0 = Event to Motor is disabled_1 = Event to Motor is enabled" "0,1" group.long 0x1C++0x3 line.long 0x00 "RTC_EVENT_FLAGS_REG,RTC Event Flags Register" rbitfld.long 0x00 6. " RTC_EVENT_ALRM ,Alarm event flag. Indicate that alarm event occurred since the last reset" "0,1" rbitfld.long 0x00 5. " RTC_EVENT_MNTH ,Month rolls over event flag. Indicate that month rolls over event occurred since the last reset" "0,1" rbitfld.long 0x00 4. " RTC_EVENT_DATE ,Date rolls over event flag. Indicate that date rolls over event occurred since the last reset" "0,1" textline " " rbitfld.long 0x00 3. " RTC_EVENT_HOUR ,Hour rolls over event flag. Indicate that hour rolls over event occurred since the last reset" "0,1" rbitfld.long 0x00 2. " RTC_EVENT_MIN ,Minute rolls over event flag. Indicate that minute rolls over event occurred since the last reset" "0,1" rbitfld.long 0x00 1. " RTC_EVENT_SEC ,Second rolls over event flag. Indicate that second rolls over event occurred since the last reset" "0,1" textline " " rbitfld.long 0x00 0. " RTC_EVENT_HOS ,Hundredths of a second event flag. Indicate that hundredths of a second rolls over event occurred since the last reset" "0,1" group.long 0x4++0x3 line.long 0x00 "RTC_HOUR_MODE_REG,RTC Hour Mode Register" bitfld.long 0x00 0. " RTC_HMS ,When this field is set high the RTC operates in 12 hour clock mode; otherwise, times are in 24 hour clock format" "0,1" group.long 0x24++0x3 line.long 0x00 "RTC_INTERRUPT_DISABLE_REG,RTC Interrupt Disable Register" bitfld.long 0x00 6. " RTC_ALRM_INT_DIS ,Interrupt on alarm disable. Disable to issue the interrupt when alarm event occurred" "0,1" bitfld.long 0x00 5. " RTC_MNTH_INT_DIS ,Interrupt on month disable. Disable to issue the interrupt when month event occurred" "0,1" bitfld.long 0x00 4. " RTC_DATE_INT_DIS ,Interrupt on date disable. Disable to issue the interrupt when date event occurred" "0,1" textline " " bitfld.long 0x00 3. " RTC_HOUR_INT_DIS ,IInterrupt on hour disable. Disable to issue the interrupt when hour event occurred" "0,1" bitfld.long 0x00 2. " RTC_MIN_INT_DIS ,Interrupt on minute disable. Disable to issue the interrupt when minute event occurred" "0,1" bitfld.long 0x00 1. " RTC_SEC_INT_DIS ,Interrupt on second disable. Disable to issue the interrupt when second event occurred" "0,1" textline " " bitfld.long 0x00 0. " RTC_HOS_INT_DIS ,Interrupt on hundredths of a second disable. Disable to issue the interrupt when hundredths of a second event occurred" "0,1" group.long 0x20++0x3 line.long 0x00 "RTC_INTERRUPT_ENABLE_REG,RTC Interrupt Enable Register" bitfld.long 0x00 6. " RTC_ALRM_INT_EN ,Interrupt on alarm enable. Enable to issue the interrupt when alarm event occurred" "0,1" bitfld.long 0x00 5. " RTC_MNTH_INT_EN ,Interrupt on month enable. Enable to issue the interrupt when month event occurred" "0,1" bitfld.long 0x00 4. " RTC_DATE_INT_EN ,Interrupt on date enable. Enable to issue the interrupt when date event occurred" "0,1" textline " " bitfld.long 0x00 3. " RTC_HOUR_INT_EN ,Interrupt on hour enable. Enable to issue the interrupt when hour event occurred" "0,1" bitfld.long 0x00 2. " RTC_MIN_INT_EN ,Interrupt on minute enable. Enable to issue the interrupt when minute event occurred" "0,1" bitfld.long 0x00 1. " RTC_SEC_INT_EN ,Interrupt on second enable. Enable to issue the interrupt when second event occurred" "0,1" textline " " bitfld.long 0x00 0. " RTC_HOS_INT_EN ,Interrupt on hundredths of a second enable. Enable to issue the interrupt when hundredths of a second event occurred" "0,1" group.long 0x28++0x3 line.long 0x00 "RTC_INTERRUPT_MASK_REG,RTC Interrupt Mask Register" rbitfld.long 0x00 6. " RTC_ALRM_INT_MSK ,Mask alarm interrupt. It can be cleared (set) by setting corresponding bit (ALRM) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" rbitfld.long 0x00 5. " RTC_MNTH_INT_MSK ,IMask month interrupt. It can be cleared (set) by setting corresponding bit (MNTH) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" rbitfld.long 0x00 4. " RTC_DATE_INT_MSK ,Mask date interrupt. It can be cleared (set) by setting corresponding bit (DATE) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" textline " " rbitfld.long 0x00 3. " RTC_HOUR_INT_MSK ,IMask hour interrupt. It can be cleared (set) by setting corresponding bit (HOUR) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" rbitfld.long 0x00 2. " RTC_MIN_INT_MSK ,IMask minute interrupt. It can be cleared (set) by setting corresponding bit (MIN) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" rbitfld.long 0x00 1. " RTC_SEC_INT_MSK ,IMask second interrupt. It can be cleared (set) by setting corresponding bit (SEC) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" textline " " rbitfld.long 0x00 0. " RTC_HOS_INT_MSK ,Mask hundredths of a second interrupt. It can be cleared (set) by setting corresponding bit (HOS) in Interrupt Enable Register (Interrupt Disable Register)" "0,1" group.long 0x30++0x3 line.long 0x00 "RTC_KEEP_RTC_REG,RTC Keep RTC Register" bitfld.long 0x00 0. " RTC_KEEP ,Keep RTC. When high, the time and calendar registers and any other registers which directly affect or are affected by the time and calendar registers are NOT reset when software reset is applied. When low, the software reset will reset every register except the keep RTC and control registers" "0,1" group.long 0x90++0x3 line.long 0x00 "RTC_MOTOR_EVENT_CNT_REG,RTC Motor Event Counter Register" hexmask.long.word 0x00 0.--11. 1. " RTC_MOTOR_EVENT_CNT ,It gives the current value of the Motor event counter (0 to RTC_MOTOR_EVENT_PERIOD)" group.long 0x84++0x3 line.long 0x00 "RTC_MOTOR_EVENT_PERIOD_REG,RTC Motor Event Period Register" hexmask.long.word 0x00 0.--11. 1. " RTC_MOTOR_EVENT_PERIOD ,RTC wil send an event to motor (if RTC_MOTOR_EVENT_EN=1) every (RTC_MOTOR_EVENT_PERIOD+1)*10ms" group.long 0x8C++0x3 line.long 0x00 "RTC_PDC_EVENT_CLEAR_REG,RTC PDC Event Clear Register" rbitfld.long 0x00 0. " PDC_EVENT_CLEAR ,On read, PDC event is cleared" "0,1" group.long 0x94++0x3 line.long 0x00 "RTC_PDC_EVENT_CNT_REG,RTC PDC Event Counter Register" hexmask.long.word 0x00 0.--12. 1. " RTC_PDC_EVENT_CNT ,It gives the current value of the PDC event counter (0 to RTC_PDC_EVENT_PERIOD)" group.long 0x88++0x3 line.long 0x00 "RTC_PDC_EVENT_PERIOD_REG,RTC PDC Event Period Register" hexmask.long.word 0x00 0.--12. 1. " RTC_PDC_EVENT_PERIOD ,RTC wil send an event to PDC (if RTC_PDC_EVENT_EN=1) every (RTC_PDC_EVENT_PERIOD+1)*10ms" group.long 0x2C++0x3 line.long 0x00 "RTC_STATUS_REG,RTC Status Register" rbitfld.long 0x00 3. " RTC_VALID_CAL_ALM ,Valid Calendar Alarm. If cleared then indicates that invalid entry occurred when writing to Calendar Alarm Register" "0,1" rbitfld.long 0x00 2. " RTC_VALID_TIME_ALM ,Valid Time Alarm. If cleared then indicates that invalid entry occurred when writing to Time Alarm Register" "0,1" rbitfld.long 0x00 1. " RTC_VALID_CAL ,Valid Calendar. If cleared then indicates that invalid entry occurred when writing to Calendar Register" "0,1" textline " " rbitfld.long 0x00 0. " RTC_VALID_TIME ,Valid Time. If cleared then indicates that invalid entry occurred when writing to Time Register" "0,1" group.long 0x10++0x3 line.long 0x00 "RTC_TIME_ALARM_REG,RTC Time Alarm Register" bitfld.long 0x00 30. " RTC_TIME_PM ,In 12 hour clock mode, indicates PM when set" "0,1" bitfld.long 0x00 28.--29. " RTC_TIME_HR_T ,Hours tens. Represented in BCD digit (0-2)" "0,1,2,3" bitfld.long 0x00 24.--27. " RTC_TIME_HR_U ,Hours units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--22. " RTC_TIME_M_T ,Minutes tens. Represented in BCD digit (0-5)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " RTC_TIME_M_U ,Minutes units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " RTC_TIME_S_T ,Seconds tens. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--11. " RTC_TIME_S_U ,Seconds units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RTC_TIME_H_T ,Hundredths of a second tens. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RTC_TIME_H_U ,Hundredths of a second units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x3 line.long 0x00 "RTC_TIME_REG,RTC Time Register" bitfld.long 0x00 31. " RTC_TIME_CH ,The value in this register has altered since last read. Read and clear" "0,1" bitfld.long 0x00 30. " RTC_TIME_PM ,In 12 hour clock mode, indicates PM when set" "0,1" bitfld.long 0x00 28.--29. " RTC_TIME_HR_T ,Hours tens. Represented in BCD digit (0-2)" "0,1,2,3" textline " " bitfld.long 0x00 24.--27. " RTC_TIME_HR_U ,Hours units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--22. " RTC_TIME_M_T ,Minutes tens. Represented in BCD digit (0-5)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " RTC_TIME_M_U ,Minutes units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--14. " RTC_TIME_S_T ,Seconds tens. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " RTC_TIME_S_U ,Seconds units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RTC_TIME_H_T ,Hundredths of a second tens. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " RTC_TIME_H_U ,Hundredths of a second units. Represented in BCD digit (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "SDADC" base ad:0x50020800 width 21. group.long 0x14++0x3 line.long 0x00 "SDADC_CLEAR_INT_REG,Sigma Delta ADC Clear Interrupt Register" hexmask.long.word 0x00 0.--15. 1. " SDADC_CLR_INT ,Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0." group.long 0x0++0x3 line.long 0x00 "SDADC_CTRL_REG,Sigma Delta ADC Control Register" bitfld.long 0x00 17. " SDADC_DMA_EN ,0: DMA functionality disabled_1: DMA functionality enabled" "0,1" bitfld.long 0x00 16. " SDADC_MINT ,0: Disable (mask) SDADC_ADC_INT._1: Enable SDADC_ADC_INT to ICU" "0,1" rbitfld.long 0x00 15. " SDADC_INT ,1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to SDADC_CLEAR_INT_REG" "0,1" textline " " rbitfld.long 0x00 14. " SDADC_LDO_OK ,1: Internal LDO is ready for use" "0,1" bitfld.long 0x00 13. " SDADC_VREF_SEL ,0: Internal bandgap reference._1: External reference" "0,1" bitfld.long 0x00 12. " SDADC_CONT ,0: Manual ADC mode, a single result will be generated after setting the SDADC_START bit._1: Continuous ADC mode, new ADC results will be constantly stored in SDADC_RESULT_REG. Still SDADC_START has to be set to start the execution. Wait for SDADC_START to become zero after clearing the SDADC_CONT bit to stop the continuous mode" "0,1" textline " " bitfld.long 0x00 10.--11. " SDADC_OSR ,Oversample Rate_0: 128x_1: 256x_2: 512x_3: 1024x" "0,1,2,3" bitfld.long 0x00 9. " SDADC_SE ,0: Differential mode_1: Single ended mode (Input selection negative side is ignored)" "0,1" bitfld.long 0x00 6.--8. " SDADC_INN_SEL ,Input selection of negative side._0: ADC0 / P1[09]_1: ADC1 / P0[25]_2: ADC2 / P0[08]_3: ADC3 / P0[09]_4: ADC4 / P1[14]_5: ADC5 / P1[20]_6: ADC6 / P1[21]_7: ADC7 / P1[22]" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 2.--5. " SDADC_INP_SEL ,Input selection of positive side._0: ADC0 / P1[09]_1: ADC1 / P0[25]_2: ADC2 / P0[08]_3: ADC3 / P0[09]_4: ADC4 / P1[14]_5: ADC5 / P1[20]_6: ADC6 / P1[21]_7: ADC7 / P1[22]_8: VBAT (via 4x attenuator, INN connected to ground)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " SDADC_START ,0: ADC conversion ready._1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the SDADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero" "0,1" bitfld.long 0x00 0. " SDADC_EN ,0: LDO is off and ADC is disabled._1: LDO, bias currents and modulator are enabled" "0,1" group.long 0xC++0x3 line.long 0x00 "SDADC_GAIN_CORR_REG,Sigma Delta ADC Gain Correction Register" hexmask.long.word 0x00 0.--9. 1. " SDADC_GAIN_CORR ,Gain adjust" group.long 0x10++0x3 line.long 0x00 "SDADC_OFFS_CORR_REG,Sigma Delta ADC Offset Correction Register" hexmask.long.word 0x00 0.--9. 1. " SDADC_OFFS_CORR ,Offset adjust" group.long 0x18++0x3 line.long 0x00 "SDADC_RESULT_REG,Sigma Delta ADC Result Register" hexmask.long.word 0x00 0.--15. 1. " SDADC_VAL ,Returns up to 16 bits linear value of the last AD conversion. The effective resolution depends on the OSR used" group.long 0x8++0x3 line.long 0x00 "SDADC_TEST_REG,Sigma Delta ADC Test Register" bitfld.long 0x00 11.--15. " SDADC_GAIN_SEL_INIT ,ADC 'attenuator' in analogue, digital filter default 4/5 (not adjustable)._5x'1': 5/5_4x'1': 4/5 (default)_3x'1': 3/5_2x'1': 2/5_1x'1': 1/5_Order of '0' and '1' don't care, they are being rotated using DEM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SDADC_CORR_ORDER ,Gain/offset correction order:_0: First gain, second offset_1: First offset, second gain" "0,1" bitfld.long 0x00 8.--9. " SDADC_OTA_BIAS ,OTA bias current:_0: 2x_1: 1x (default)_2: 0.5x_3: 0.25x" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " SDADC_CLK_FREQ ,0: 250 kHz_1: 500 kHz_2: 1 MHz (default)_3: 2 MHz" "0,1,2,3" bitfld.long 0x00 5. " SDADC_LDO_TEST ,1: Connects LDO output to testbus" "0,1" bitfld.long 0x00 4. " SDADC_LDO_SMPL_DIS ,1: Disables automatic LDO sample and hold" "0,1" textline " " bitfld.long 0x00 3. " SDADC_OPMODE ,0: IADC (default)_1: DS ADC (continuous bitstream output, one initial reset at start, dig filter disabled)" "0,1" bitfld.long 0x00 1. " SDADC_DEM_DIS ,1: Disables Dynamic Element Matching in the input circuit" "0,1" bitfld.long 0x00 0. " SDADC_CHOP_DIS ,1: Disables chopper stabilisation" "0,1" width 0x0B tree.end tree "SMOTOR" base ad:0x50030E00 width 26. group.long 0x80++0x3 line.long 0x00 "CMD_TABLE_BASE,Base address of the command table" hexmask.long 0x00 0.--31. 1. " CMD_TABLE_BASE_X ,Dummy field for register test generation" group.long 0x4++0x3 line.long 0x00 "PG0_CTRL_REG,Pattern generator 0 control register" bitfld.long 0x00 15. " GENEND_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 14. " GENSTART_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 13. " PG_START_MODE ,0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command_1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command" "0,1" textline " " bitfld.long 0x00 12. " PG_MODE ,0 = Flex mode_1 = Pair mode" "0,1" bitfld.long 0x00 11. " SIG3_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 10. " SIG2_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" textline " " bitfld.long 0x00 9. " SIG1_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 8. " SIG0_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 6.--7. " OUT3_SIG ,Selects which signal is routed to the output" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " OUT2_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 2.--3. " OUT1_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 0.--1. " OUT0_SIG ,Selects which signal is routed to the output" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "PG1_CTRL_REG,Pattern generator 1 control register" bitfld.long 0x00 15. " GENEND_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 14. " GENSTART_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 13. " PG_START_MODE ,0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command_1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command" "0,1" textline " " bitfld.long 0x00 12. " PG_MODE ,0 = Flex mode_1 = Pair mode" "0,1" bitfld.long 0x00 11. " SIG3_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 10. " SIG2_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" textline " " bitfld.long 0x00 9. " SIG1_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 8. " SIG0_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 6.--7. " OUT3_SIG ,Selects which signal is routed to the output" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " OUT2_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 2.--3. " OUT1_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 0.--1. " OUT0_SIG ,Selects which signal is routed to the output" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "PG2_CTRL_REG,Pattern generator 2 control register" bitfld.long 0x00 15. " GENEND_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 14. " GENSTART_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 13. " PG_START_MODE ,0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command_1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command" "0,1" textline " " bitfld.long 0x00 12. " PG_MODE ,0 = Flex mode_1 = Pair mode" "0,1" bitfld.long 0x00 11. " SIG3_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 10. " SIG2_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" textline " " bitfld.long 0x00 9. " SIG1_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 8. " SIG0_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 6.--7. " OUT3_SIG ,Selects which signal is routed to the output" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " OUT2_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 2.--3. " OUT1_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 0.--1. " OUT0_SIG ,Selects which signal is routed to the output" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "PG3_CTRL_REG,Pattern generator 3 control register" bitfld.long 0x00 15. " GENEND_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 14. " GENSTART_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 13. " PG_START_MODE ,0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command_1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command" "0,1" textline " " bitfld.long 0x00 12. " PG_MODE ,0 = Flex mode_1 = Pair mode" "0,1" bitfld.long 0x00 11. " SIG3_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 10. " SIG2_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" textline " " bitfld.long 0x00 9. " SIG1_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 8. " SIG0_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 6.--7. " OUT3_SIG ,Selects which signal is routed to the output" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " OUT2_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 2.--3. " OUT1_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 0.--1. " OUT0_SIG ,Selects which signal is routed to the output" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "PG4_CTRL_REG,Pattern generator 4 control register" bitfld.long 0x00 15. " GENEND_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 14. " GENSTART_IRQ_EN ,Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 13. " PG_START_MODE ,0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command_1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command" "0,1" textline " " bitfld.long 0x00 12. " PG_MODE ,0 = Flex mode_1 = Pair mode" "0,1" bitfld.long 0x00 11. " SIG3_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 10. " SIG2_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" textline " " bitfld.long 0x00 9. " SIG1_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 8. " SIG0_EN ,0 = Signal disabled_1 = Signal enabled" "0,1" bitfld.long 0x00 6.--7. " OUT3_SIG ,Selects which signal is routed to the output" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " OUT2_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 2.--3. " OUT1_SIG ,Selects which signal is routed to the output" "0,1,2,3" bitfld.long 0x00 0.--1. " OUT0_SIG ,Selects which signal is routed to the output" "0,1,2,3" group.long 0x20++0x3 line.long 0x00 "SMOTOR_CMD_FIFO_REG,Motor control command FIFO register" hexmask.long.word 0x00 0.--15. 1. " SMOTOR_CMD_FIFO ,Writing to this address will push a command into the command FIFO" group.long 0x24++0x3 line.long 0x00 "SMOTOR_CMD_READ_PTR_REG,Command read pointer register" rbitfld.long 0x00 0.--5. " SMOTOR_CMD_READ_PTR ,Pointer to the next command to be popped from the FIFO. The command at SMOTOR_CMD_READ_PTR-1 is the last command that has been popped from the FIFO into its corresponding PG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x28++0x3 line.long 0x00 "SMOTOR_CMD_WRITE_PTR_REG,Command write pointer register" bitfld.long 0x00 0.--5. " SMOTOR_CMD_WRITE_PTR ,Pointer to the location in the FIFO where the next command will be pushed at. The last command pushed to the FIFO is at SMOTOR_CMD_WRITE_PTR - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x0++0x3 line.long 0x00 "SMOTOR_CTRL_REG,Motor control register" bitfld.long 0x00 28. " TRIG_RTC_EVENT_EN ,0 = RTC event does not trigger command pop_1 = RTC even triggers command pop" "0,1" bitfld.long 0x00 27. " MC_LP_CLK_TRIG_EN ,0 = Divided sleep clock does not trigger command pop_1 = Divided sleep clock triggers command pop" "0,1" bitfld.long 0x00 26. " SMOTOR_THRESHOLD_IRQ_EN ,IRQ in the event of the FIFO level (write pointer - read pointer) reaching, or is below the threshold determined by SMOTOR_THRESHOLD._0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" textline " " bitfld.long 0x00 21.--25. " SMOTOR_THRESHOLD ,Determines the FIFO level (write pointer - read pointer) at or below which and IRQ can be triggered using SMOTOR_THRESHOLD_IRQ_EN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " SMOTOR_FIFO_UNR_IRQ_EN ,IRQ in the event of FIFO underrun:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 19. " SMOTOR_FIFO_OVF_IRQ_EN ,IRQ in the event of FIFO overflow:_0 = IRQ is disabled_1 = IRQ is enabled" "0,1" textline " " bitfld.long 0x00 18. " SMOTOR_GENEND_IRQ_EN ,IRQ in the event a pattern generator (configured to do so through its corresponding GENEND_IRQ_EN bit) has ended generating a pattern:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" bitfld.long 0x00 17. " SMOTOR_GENSTART_IRQ_EN ,IRQ in the event a pattern generator (configured to do so through its corresponding GENSTART_IRQ_EN bit) has just started generating a pattern:_0 = Interrupt requests disabled_1 = Interrupt requests enabled" "0,1" hexmask.long.word 0x00 7.--16. 1. " SMOTOR_MOI ,Idle time of a PG after generating a waveform. A PG will remain busy for the last signal's MOI to finish" textline " " bitfld.long 0x00 1.--6. " CYCLIC_SIZE ,Depth of the cyclic buffer, only valid if CYCLIC_MODE is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " CYCLIC_MODE ,Determines operation mode of command FIFO:_0 = Normal FIFO mode_1 = Cyclic buffer mode, CYCLIC_SIZE determines buffer depth" "0,1" group.long 0x30++0x3 line.long 0x00 "SMOTOR_IRQ_CLEAR_REG,Motor control IRQ clear register" bitfld.long 0x00 4. " THRESHOLD_IRQ_CLEAR ,Clears the THRESHOLD_IRQ_STATUS bit" "0,1" bitfld.long 0x00 3. " FIFO_UNR_IRQ_CLEAR ,Clears the FIFO_UNR_IRQ_STATUS bit" "0,1" bitfld.long 0x00 2. " FIFO_OVF_IRQ_CLEAR ,Clears the FIFO_OVF_IRQ_STATUS bit" "0,1" textline " " bitfld.long 0x00 1. " GENEND_IRQ_CLEAR ,Clears the GENEND_IRQ_CLEAR bit" "0,1" bitfld.long 0x00 0. " GENSTART_IRQ_CLEAR ,Clears the GENSTART_IRQ_CLEAR bit" "0,1" group.long 0x2C++0x3 line.long 0x00 "SMOTOR_STATUS_REG,Motor controller status register" rbitfld.long 0x00 9. " PG4_BUSY ,Tells whether the PG is busy/generating a waveform" "0,1" rbitfld.long 0x00 8. " PG3_BUSY ,Tells whether the PG is busy/generating a waveform" "0,1" rbitfld.long 0x00 7. " PG2_BUSY ,Tells whether the PG is busy/generating a waveform" "0,1" textline " " rbitfld.long 0x00 6. " PG1_BUSY ,Tells whether the PG is busy/generating a waveform" "0,1" rbitfld.long 0x00 5. " PG0_BUSY ,Tells whether the PG is busy/generating a waveform" "0,1" rbitfld.long 0x00 4. " THRESHOLD_IRQ_STATUS ,Tells whether the THRESHOLD_IRQ fired. Can be cleared with corresponding _CLEAR bit" "0,1" textline " " rbitfld.long 0x00 3. " FIFO_UNR_IRQ_STATUS ,Tells whether the FIFO_UNR_IRQ fired. Can be cleared with corresponding _CLEAR bit" "0,1" rbitfld.long 0x00 2. " FIFO_OVF_IRQ_STATUS ,Tells whether the FIFO_OVF_IRQ fired. Can be cleared with corresponding _CLEAR bit" "0,1" rbitfld.long 0x00 1. " GENEND_IRQ_STATUS ,Tells whether the GENEND_IRQ fired. Can be cleared with corresponding _CLEAR bit" "0,1" textline " " rbitfld.long 0x00 0. " GENSTART_IRQ_STATUS ,Tells whether the GENSTART_IRQ fired. Can be cleared with corresponding _CLEAR bit" "0,1" group.long 0x18++0x3 line.long 0x00 "SMOTOR_TRIGGER_REG,Motor controller trigger register" bitfld.long 0x00 5. " PG4_START ,Writing 1 to this bit will start PG4 in manual mode" "0,1" bitfld.long 0x00 4. " PG3_START ,Writing 1 to this bit will start PG3 in manual mode" "0,1" bitfld.long 0x00 3. " PG2_START ,Writing 1 to this bit will start PG2 in manual mode" "0,1" textline " " bitfld.long 0x00 2. " PG1_START ,Writing 1 to this bit will start PG1 in manual mode" "0,1" bitfld.long 0x00 1. " PG0_START ,Writing 1 to this bit will start PG0 in manual mode" "0,1" bitfld.long 0x00 0. " POP_CMD ,Writing 1 will pop one or more commands from the command buffer into its corresponding pattern generator" "0,1" group.long 0x40++0x3 line.long 0x00 "WAVETABLE_BASE,Base address of the wavetable" bitfld.long 0x00 24.--28. " WAVETABLE_BASE_X_B3 ,Dummy bitfield for register test generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " WAVETABLE_BASE_X_B2 ,Dummy bitfield for register test generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " WAVETABLE_BASE_X_B1 ,Dummy bitfield for register test generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " WAVETABLE_BASE_X_B0 ,Dummy bitfield for register test generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "SNC" base ad:0x50020C00 width 18. group.long 0x0++0x3 line.long 0x00 "SNC_CTRL_REG,Sensor Node Control Register" bitfld.long 0x00 8. " SNC_IRQ_ACK ,When set, the specific bit-field auto-clears the SNC_IRQ_EN field, if the latter is already set. By this way, the IRQ line towards either the CM33 and/or the PDC is cleared. Hence, the CM33 should set this bit-field as soon as it captures the interrupt from the Sensor Node._Note: Any SW writes to this bit-field will be discarded if the SNC_IRQ_EN bit-field is not set. It is finally noted that the SNC_IRQ_ACK bit-field is also auto-clear and it is de-asserted together with SNC_IRQ_EN" "0,1" bitfld.long 0x00 6.--7. " SNC_IRQ_CONFIG ,The specific bit-field determines if the IRQ line of the Sensor Node will be routed towards either the host processor (CM33) or the Power Domains Controller (PDC), or to both of them, according to the following configuration:_0x0 = Neither the CM33 nor the PDC are triggered, both IRQ lines are low regardless of the value of SNC_IRQ_EN bit-field._0x1 = CM33 should be triggered, provided that SNC_IRQ_EN is set_0x2 = PDC should be triggered, provided that SNC_IRQ_EN is set_0x3 = Both CM33 and PDC should be triggered, provided that SNC_IRQ_EN is set_Note: It must be noted that the specific bit-field is locked after set the SNC_IRQ_EN field of the same register. Hence, the SNC IRQ configuration cannot be changed after the IRQ bit-field is set and before the IRQ is acknowledged (by CM33). It is also noted that after having set SNC_IRQ_EN via SW, the specific bit-field can be de-asserted only by setting the SNC_IRQ_ACK bit-field (see also the description of this bit-field, also residing in SNC_CTRL_REG)" "0,1,2,3" bitfld.long 0x00 5. " SNC_IRQ_EN ,When set, the specific bit-field may generate a (level-sensitive) IRQ to trigger either the host processor (CM33) or the Power Domains Controller (PDC) or both, depending on the configuration set in the SNC_IRQ_CONFIG bit-field of SNC_CTRL_REG. As soon as the SNC_IRQ_EN is set, it can be cleared only by setting the SNC_IRQ_ACK bit-field" "0,1" textline " " bitfld.long 0x00 4. " SNC_BRANCH_LOOP_INIT ,When set, it clears the value of the counter used in the Sensor Node's branch command (COBR), when performing an iterative branch of up to 128 times. This bit-field is auto-cleared with the next SNC clock" "0,1" bitfld.long 0x00 3. " SNC_RESET ,This is the Sensor Node Controller's synchronous clear bit-field. When set, it resets the state of the Sensor Node Controller and sets back its program counter (SNC_PC_REG) to the programmed base address, as determined by SNC_BASE_REG register (located in memory controller). This bit-field is auto-cleared with the next SNC clock._Note: Setting this bit-field may interrupt the Sensor Node's regular execution and any command currently being exeucuted may be abnormally terminated" "0,1" bitfld.long 0x00 2. " BUS_ERROR_DETECT_EN ,When set, it enables the detection of system bus errors that may occur in case a non-mapped address is used by the Sensor Node controller, when performing a register access._Note: In case of a bus error detection, the Sensor Node will set to '1' the BUS_ERROR_STATUS bit-field of SNC_STATUS_REG and will continue normally to the next command" "0,1" textline " " bitfld.long 0x00 1. " SNC_SW_CTRL ,When set, this bit-field bypasses the enable of Sensor Node that comes from the PDC. In this mode, the Sensor Node can be started and stopped via the SNC_EN bit-field of SNC_CTRL_REG._Note: This mode is suggested to be used for debugging purposes. ?lso, the base address of the Sensor Node should have been programmed to the target value, before this bit-field is set" "0,1" bitfld.long 0x00 0. " SNC_EN ,Sensor Node Controller's enable bit-field. When set, it may activate the Sensor Node, provided that the SNC_SW_CTRL bit-field is also set. If not, then the specific bit-field is not effective and Sensor Node's actual enable is controller by the Power Domains Controller (PDC)._Note: When SNC_SW_CTRL bit-field is set, the Sensor Node is controlled by the user. Thus, in that mode, it can be started and stopped by setting and resetting the SNC_EN field. When SNC_EN is reset, the Sensor Node will first complete the last on-going command before being halted" "0,1" group.long 0x8++0x3 line.long 0x00 "SNC_LP_TIMER_REG,Sensor Node Low-Power Timer Register" hexmask.long.byte 0x00 0.--7. 1. " LP_TIMER ,This bit-field returns the current value of the Sensor Node's 8-bit timer, running with the low-power clock and may be used for debugging purposes. The specific timer is used to implement a delay of up to 256 ticks of the low-power clock" group.long 0xC++0x3 line.long 0x00 "SNC_PC_REG,Sensor Node Program Counter" hexmask.long.tbyte 0x00 2.--18. 1. " PC_REG ,This bit-field returns the Sensor Node's program counter bits [18:2], which at the same time is the program counter's offset from the starting address of SYSRAM (0x20.000.000), and it is can be set by the user, as soon as Sensor Node has been stopped._The 13 MSBs of the program counter are tied to '0x400', since the Sensor Node always executes from SYSRAM, while its 2 LSBs are always tied to '0', since memory accesses are always of 32-bit._NOTE: The Sensor Node can be stopped by clearing the SNC_EN bit-field of SNC_CTRL_REG and provided that the Power Domains Controller (PDC) is bypassed. The latter can be done by setting to '1' the SNC_SW_CTRL bit-field of SNC_CTRL_REG" group.long 0x10++0x3 line.long 0x00 "SNC_R1_REG,Sensor Node core - Operand 1 Register" hexmask.long 0x00 0.--31. 1. " R1_REG ,Returns the current value of the first 32-bit of the last SNC command executed" group.long 0x14++0x3 line.long 0x00 "SNC_R2_REG,Sensor Node core - Operand 2 Register" hexmask.long 0x00 0.--31. 1. " R2_REG ,Returns the current value of the second 32-bit word of the last SNC command executed. This is useful for the SNC commands composed by two 32-bit words" group.long 0x4++0x3 line.long 0x00 "SNC_STATUS_REG,Sensor Node Status Register" rbitfld.long 0x00 6. " SNC_PC_LOADED ,0 : Sensor node's program counter is controlled by the Sensor Node's FSM, incemented by 4 after the fetching of each 32-bit command word._1 : Sensor node's program counter is loaded with a new value. The assertion of this signal requires the Sensor Node to have been first stopped, so the user must first check that the SNC_IS_STOPPED bit-field of this register is asserted, before writing the program counter. The SNC_PC_LOADED bit-field is auto-clear and it is reset to '0' as soon as the user has re-started the Sensor Node._Note: To start and stop the Sensor Node manually, the SNC_SW_CTRL and SNC_EN bit-fields of SNC_CTRL_REG must have been set by the user. This mode of operation is bypassing the Power Domains Controller and it is to be used for debugging purposes" "0,1" rbitfld.long 0x00 5. " SNC_IS_STOPPED ,0 : Sensor Node is operational and its FSM is running._1 : Sensor Node is stopped and its FSM is halted.To leave this state, the SNC_EN bit-field of SNC_CTRL_REG must be set, provided that the SNC_SW_CTRL bit-field of the same register is also set. This mode is used for debugging purposes, bypassing the enable of SNC coming from the Power Domains Controller._Note: The SNC_PC_REG register can be modified by SW if and only if the SNC_IS_STOPPED bit is set. Otherwise, the writes to SNC_PC_REG are discarded" "0,1" rbitfld.long 0x00 4. " HARD_FAULT_STATUS ,0 : No opcode error has occurred, Sensor Node continues normally._1 : An opcode error has occurred. Sensor Node will continue its execution, but will set also the specific bit-field to '1', for debugging purposes._Note: After being set, this bit-field will be cleared only when the Sensor Node is re-initialized, by starting again from its base address. The latter can happen either by activating the SNC_RESET bit-field of SNC_CTRL_REG or by stopping and starting again the Sensor Node. This is possible only when the PDC is bypassed, so when the Sensor Node is controlled by SNC_EN and SNC_SW_CTRL bit-fields of SNC_CTRL_REG" "0,1" textline " " rbitfld.long 0x00 3. " BUS_ERROR_STATUS ,0 : No system bus error detected, Sensor Node continues normally_1 : Bus error occurred. Sensor Node will continue, but it will also set the specific flag, which can be used for debugging purposes._Note: This bit-field will be reset to '0' only when the Sensor Node is re-initialized, by starting again from its base address" "0,1" rbitfld.long 0x00 2. " SNC_DONE_STATUS ,0 : Sensor Node has not yet completed the target program's execution._1 : Sensor Node has completed the targer program's execution. Together with the update of the status bit, a pulse is also generated to notify the PDC that the Sensor Node is done._Note: This bit-field is set only when the _SLP_ (sleep) command is executed, which should be issued after the completion of all pending tasks of the Sensor Node. It will be reset to '0' only when the Sensor Node re-starts, by executing from the base address._This can be done by either toggling (de-asserting and re-asserting again) the SNC_EN bit-field of SNC_CTRL_REG, if the SNC is controlled by SW, or by just re-setting the SNC state via the SNC_RESET bit-field of the same register" "0,1" bitfld.long 0x00 1. " GR_FLAG ,Sensor Node's 'GR' (greater) flag. It can be modified either by the Sensor Node's core (by executing an _RDCGR_ command) or by the Sensor Node's microcode, when the latter directly modifies the specific bit-field of SNC_STATUS_REG._When the Sensor Node's FSM is in its initial state (which may happen either by switching-on the PD_COM power domain or by resetting the Sensor Node via SNC_CTRL_REG.SNC_RESET), the specific bit-field is kept to '0', for initialization purposes._When the Sensor Node is stopped and then reset, the Sensor Node's FSM is not in its initial state and in that case, the GR_FLAG bit-field should be reset by the user (if the application needs this to be initialized to '0'). Otherwise, it can be left as it is, until being updated by the Sensor Node itself (upon executing an _RDCGR_ command)._In general, however, this bit-field should not be modified by either the host processor (CM33) or the CMAC processor (CM0+), and especially when the Sensor Node is enabled and operational" "0,1" textline " " bitfld.long 0x00 0. " EQ_FLAG ,Sensor Node's 'EQ' (equalhigh) flag. It can be modified either by the Sensor Node's core (by executing an _RDCBI_ command) or by the Sensor Node's microcode, when the latter directly modifies the specific bit-field of SNC_STATUS_REG._When the Sensor Node's FSM is in its initial state (which may happen either by switching-on the PD_COM power domain or by resetting the Sensor Node via SNC_CTRL_REG.SNC_RESET), the specific bit-field is kept to '0', for initialization purposes._When the Sensor Node is stopped and then reset, the Sensor Node's FSM is not in its initial state and in that case, the EQ_FLAG bit-field should be reset by the user (if the application needs this to be initialized to '0'). Otherwise, it can be left as it is, until being updated by the Sensor Node itself (upon executing an _RDCBI_ command)._In general, however, this bit-field should not be modified by either the host processor (CM33) or the CMAC processor (CM0+), and especially when the Sensor Node is enabled and operational" "0,1" group.long 0x18++0x3 line.long 0x00 "SNC_TMP1_REG,Sensor Node core - Temporary Register 1" hexmask.long 0x00 0.--31. 1. " TMP1_REG ,Returns the current value of the Sensor Node's first temporary register. To be used for debugging purposes" group.long 0x1C++0x3 line.long 0x00 "SNC_TMP2_REG,Sensor Node core - Temporary Register 2" hexmask.long 0x00 0.--31. 1. " TMP2_REG ,Returns the current value of the Sensor Node's second temporary register. To be used for debugging purposes" width 0x0B tree.end tree "SPI" base ad:0x50020300 width 19. group.long 0x8++0x3 line.long 0x00 "SPI_CLEAR_INT_REG,SPI clear interrupt register" hexmask.long 0x00 0.--31. 1. " SPI_CLEAR_INT ,Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT]_Reading returns 0." group.long 0x0++0x3 line.long 0x00 "SPI_CTRL_REG,SPI control register 0" bitfld.long 0x00 25. " SPI_TX_FIFO_NOTFULL_MASK ,When 1, SPI Interrupt is generated when TX fifo is not full" "0,1" bitfld.long 0x00 24. " SPI_DMA_TXREQ_MODE ,In case SPI_FIFO_MODE=3_0 = DMA TX request is generated when transaction is finished_1 = DMA TX request is generated when tx buffer is free" "0,1" rbitfld.long 0x00 23. " SPI_TX_FIFO_EMPTY ,0 = Trasmit fifo is not empty_1 = Trasmit fifo is empty" "0,1" textline " " rbitfld.long 0x00 22. " SPI_RX_FIFO_FULL ,0 = Receive fifo is not full_1 = Receive fifo is full" "0,1" rbitfld.long 0x00 21. " SPI_RX_FIFO_EMPTY ,0 = Receive fifo is not empty_1 = Receive fifo is empty" "0,1" bitfld.long 0x00 20. " SPI_9BIT_VAL ,Determines the value of the first bit in 9 bits SPI mode." "0,1" textline " " rbitfld.long 0x00 19. " SPI_BUSY ,0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPI_CTRL_REG[SPI_INT_BIT] can be used to distinguish between these situations._1 = The SPI is busy with a transfer." "0,1" bitfld.long 0x00 18. " SPI_PRIORITY ,0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge._1 = The SPI has high priority, DMA request signals remain_active until the FIFOS are filled/emptied, so the DMA holds the AHB bus." "0,1" bitfld.long 0x00 16.--17. " SPI_FIFO_MODE ,0 = TX-FIFO and RX-FIFO used (Bidirectional mode)._1 = RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control_2 = TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control_3 = No FIFOs used (backwards compatible mode)" "0,1,2,3" textline " " bitfld.long 0x00 15. " SPI_EN_CTRL ,0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care._1 = SPI_EN pin enabled in slave mode." "0,1" bitfld.long 0x00 14. " SPI_MINT ,0 = Disable SPI_INT_BIT to ICU_1 = Enable SPI_INT_BIT to ICU" "0,1" rbitfld.long 0x00 13. " SPI_INT_BIT ,0 = RX Register or FIFO is empty._1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG." "0,1" textline " " rbitfld.long 0x00 12. " SPI_DI ,Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)" "0,1" rbitfld.long 0x00 11. " SPI_TXH ,0 = TX-FIFO is not full, data can be written._1 = TX-FIFO is full, data can not be written." "0,1" bitfld.long 0x00 10. " SPI_FORCE_DO ,0 = normal operation_1 = Force SPIDO output level to value of SPI_DO." "0,1" textline " " bitfld.long 0x00 8.--9. " SPI_WORD ,00 = 8 bits mode_01 = 16 bit mode_10 = 32 bits mode_11 = 9 bits mode. Only valid in master mode." "0,1,2,3" bitfld.long 0x00 7. " SPI_RST ,0 = normal operation_1 = Reset SPI. Same function as SPI_ON except that internal clock remain active." "0,1" bitfld.long 0x00 6. " SPI_SMN ,Master/slave mode_0 = Master_1 = Slave" "0,1" textline " " bitfld.long 0x00 5. " SPI_DO ,Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1" "0,1" bitfld.long 0x00 3.--4. " SPI_CLK ,Select SPI_CLK clock output frequency in master mode:_00 = SPI_CLK / 8_01 = SPI_CLK / 4_10 = SPI_CLK / 2_11 = SPI_CLK / 14" "0,1,2,3" bitfld.long 0x00 2. " SPI_POL ,Select SPI_CLK polarity._0 = SPI_CLK is initially low._1 = SPI_CLK is initially high." "0,1" textline " " bitfld.long 0x00 1. " SPI_PHA ,Select SPI_CLK phase. See functional timing diagrams in SPI chapter" "0,1" bitfld.long 0x00 0. " SPI_ON ,0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty._1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI_RX_TX_REG,SPI RX/TX register0" hexmask.long 0x00 0.--31. 1. " SPI_DATA ,Write: SPI_TX_REG output register 0 (TX-FIFO)_Read: SPI_RX_REG input register 0 (RX-FIFO)_In 8 or 9 bits mode bits 31 to 8 are not used, they contain old data._In 16 bits mode bits 31 to 16 are not used, they contain old data." width 0x0B tree.end tree "SPI2" base ad:0x50020400 width 20. group.long 0x8++0x3 line.long 0x00 "SPI2_CLEAR_INT_REG,SPI clear interrupt register" hexmask.long 0x00 0.--31. 1. " SPI_CLEAR_INT ,Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT]_Reading returns 0." group.long 0x0++0x3 line.long 0x00 "SPI2_CTRL_REG,SPI control register 0" bitfld.long 0x00 25. " SPI_TX_FIFO_NOTFULL_MASK ,When 1, SPI Interrupt is generated when TX fifo is not full" "0,1" bitfld.long 0x00 24. " SPI_DMA_TXREQ_MODE ,In case SPI_FIFO_MODE=3_0 = DMA TX request is generated when transaction is finished_1 = DMA TX request is generated when tx buffer is free" "0,1" rbitfld.long 0x00 23. " SPI_TX_FIFO_EMPTY ,0 = Trasmit fifo is not empty_1 = Trasmit fifo is empty" "0,1" textline " " rbitfld.long 0x00 22. " SPI_RX_FIFO_FULL ,0 = Receive fifo is not full_1 = Receive fifo is full" "0,1" rbitfld.long 0x00 21. " SPI_RX_FIFO_EMPTY ,0 = Receive fifo is not empty_1 = Receive fifo is empty" "0,1" bitfld.long 0x00 20. " SPI_9BIT_VAL ,Determines the value of the first bit in 9 bits SPI mode." "0,1" textline " " rbitfld.long 0x00 19. " SPI_BUSY ,0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPI_CTRL_REG[SPI_INT_BIT] can be used to distinguish between these situations._1 = The SPI is busy with a transfer." "0,1" bitfld.long 0x00 18. " SPI_PRIORITY ,0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge._1 = The SPI has high priority, DMA request signals remain_active until the FIFOS are filled/emptied, so the DMA holds the AHB bus." "0,1" bitfld.long 0x00 16.--17. " SPI_FIFO_MODE ,0 = TX-FIFO and RX-FIFO used (Bidirectional mode)._1 = RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control_2 = TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control_3 = No FIFOs used (backwards compatible mode)" "0,1,2,3" textline " " bitfld.long 0x00 15. " SPI_EN_CTRL ,0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care._1 = SPI_EN pin enabled in slave mode." "0,1" bitfld.long 0x00 14. " SPI_MINT ,0 = Disable SPI_INT_BIT to ICU_1 = Enable SPI_INT_BIT to ICU" "0,1" rbitfld.long 0x00 13. " SPI_INT_BIT ,0 = RX Register or FIFO is empty._1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG." "0,1" textline " " rbitfld.long 0x00 12. " SPI_DI ,Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)" "0,1" rbitfld.long 0x00 11. " SPI_TXH ,0 = TX-FIFO is not full, data can be written._1 = TX-FIFO is full, data can not be written." "0,1" bitfld.long 0x00 10. " SPI_FORCE_DO ,0 = normal operation_1 = Force SPIDO output level to value of SPI_DO." "0,1" textline " " bitfld.long 0x00 8.--9. " SPI_WORD ,00 = 8 bits mode_01 = 16 bit mode_10 = 32 bits mode_11 = 9 bits mode. Only valid in master mode." "0,1,2,3" bitfld.long 0x00 7. " SPI_RST ,0 = normal operation_1 = Reset SPI. Same function as SPI_ON except that internal clock remain active." "0,1" bitfld.long 0x00 6. " SPI_SMN ,Master/slave mode_0 = Master_1 = Slave" "0,1" textline " " bitfld.long 0x00 5. " SPI_DO ,Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1" "0,1" bitfld.long 0x00 3.--4. " SPI_CLK ,Select SPI_CLK clock output frequency in master mode:_00 = SPI_CLK / 8_01 = SPI_CLK / 4_10 = SPI_CLK / 2_11 = SPI_CLK / 14" "0,1,2,3" bitfld.long 0x00 2. " SPI_POL ,Select SPI_CLK polarity._0 = SPI_CLK is initially low._1 = SPI_CLK is initially high." "0,1" textline " " bitfld.long 0x00 1. " SPI_PHA ,Select SPI_CLK phase. See functional timing diagrams in SPI chapter" "0,1" bitfld.long 0x00 0. " SPI_ON ,0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty._1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI2_RX_TX_REG,SPI RX/TX register0" hexmask.long 0x00 0.--31. 1. " SPI_DATA ,Write: SPI_TX_REG output register 0 (TX-FIFO)_Read: SPI_RX_REG input register 0 (RX-FIFO)_In 8 or 9 bits mode bits 31 to 8 are not used, they contain old data._In 16 bits mode bits 31 to 16 are not used, they contain old data." width 0x0B tree.end tree "SYS_WDOG" base ad:0x50000700 width 19. group.long 0x4++0x3 line.long 0x00 "WATCHDOG_CTRL_REG,Watchdog control register" rbitfld.long 0x00 3. " WRITE_BUSY ,0 = A new WATCHDOG_REG[WDOG_VAL] can be written._1 = No new WATCHDOG_REG[WDOG_VAL] can be written._Note: It takes some time before the programmed WDOG_VAL is updated in the (independent) Watchdog timer. During this time it is not possible to write a new value to WATCHDOG_REG[WDOG_VAL]" "0,1" bitfld.long 0x00 2. " WDOG_FREEZE_EN ,0 = Watchdog timer can not be frozen when NMI_RST=0._1 = Watchdog timer can be frozen/resumed using_SET_FREEZE_REG[FRZ_WDOG]/_RESET_FREEZE_REG[FRZ_WDOG] when NMI_RST=0" "0,1" bitfld.long 0x00 0. " NMI_RST ,0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <= -16. Timer can be frozen/resumed using_SET_FREEZE_REG[FRZ_WDOG]/_RESET_FREEZE_REG[FRZ_WDOG]._1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software._Note that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset._The watchdog is always frozen when the Cortex-M33 is halted in DEBUG State." "0,1" group.long 0x0++0x3 line.long 0x00 "WATCHDOG_REG,Watchdog timer register" hexmask.long.tbyte 0x00 14.--31. 1. " WDOG_WEN ,Bit [31:14] = 0 = Write enable for Watchdog timer_else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away." bitfld.long 0x00 13. " WDOG_VAL_NEG ,0 = Watchdog timer value is positive._1 = Watchdog timer value is negative." "0,1" hexmask.long.word 0x00 0.--12. 1. " WDOG_VAL ,Write: Watchdog timer reload value. Note that all bits [31-14] must be 0 to reload this register._Read: Actual Watchdog timer value. Decremented by 1 every ~10 msec (RC32K) or ~29 msec(RCX)._Bit 13 indicates a negative counter value. 2, 1, 0, 3FFF16, 3FFE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions:_If WATCHDOG_CTRL_REG[NMI_RST] = 0 then_ If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt)_ if WDOG_VAL =3FF016 -> WDOG reset -> reload 1FFF16_If WATCHDOG_CTRL_REG[NMI_RST] = 1 then_ if WDOG_VAL <= 0 -> WDOG reset -> reload 1FFF16_Note 1: The programmed value WDOG_VAL is updated in the (independent) Watchdog timer at the 2nd next RC32K or RCX clock tick._Note 2: Select RC32K or RCX with CLK_RCX_REG[RCX_ENABLE]. The RC32K is selected by default" width 0x0B tree.end tree "TIMER" base ad:0x50010200 width 28. group.long 0x20++0x3 line.long 0x00 "TIMER_CAPTURE_GPIO1_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO1 ,Gives the Capture time for event on GPIO1" group.long 0x24++0x3 line.long 0x00 "TIMER_CAPTURE_GPIO2_REG,Timer value for event on GPIO2" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO2 ,Gives the Capture time for event on GPIO2" group.long 0x3C++0x3 line.long 0x00 "TIMER_CAPTURE_GPIO3_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO3 ,Gives the Capture time for event on GPIO3" group.long 0x40++0x3 line.long 0x00 "TIMER_CAPTURE_GPIO4_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO4 ,Gives the Capture time for event on GPIO4" group.long 0x44++0x3 line.long 0x00 "TIMER_CLEAR_GPIO_EVENT_REG,Timer clear gpio event register" bitfld.long 0x00 3. " TIM_CLEAR_GPIO4_EVENT ,1 = Clear GPIO4 event. Return always 0" "0,1" bitfld.long 0x00 2. " TIM_CLEAR_GPIO3_EVENT ,1 = Clear GPIO3 event. Return always 0" "0,1" bitfld.long 0x00 1. " TIM_CLEAR_GPIO2_EVENT ,1 = Clear GPIO2 event. Return always 0" "0,1" textline " " bitfld.long 0x00 0. " TIM_CLEAR_GPIO1_EVENT ,1 = Clear GPIO1 event. Return always 0" "0,1" group.long 0x48++0x3 line.long 0x00 "TIMER_CLEAR_IRQ_REG,Timer clear interrupt" bitfld.long 0x00 0. " TIM_CLEAR_IRQ ,Write any value clear interrupt" "0,1" group.long 0x0++0x3 line.long 0x00 "TIMER_CTRL_REG,Timer control register" bitfld.long 0x00 14. " TIM_CAP_GPIO4_IRQ_EN ,0 = Event on GPIO4 does not create a CAPTIM interrrupt_1 = Event on GPIO4 creates a CAPTIM interrrupt" "0,1" bitfld.long 0x00 13. " TIM_CAP_GPIO3_IRQ_EN ,0 = Event on GPIO3 does not create a CAPTIM interrrupt_1 = Event on GPIO3 creates a CAPTIM interrrupt" "0,1" bitfld.long 0x00 12. " TIM_CAP_GPIO2_IRQ_EN ,0 = Event on GPIO2 does not create a CAPTIM interrrupt_1 = Event on GPIO2 creates a CAPTIM interrrupt" "0,1" textline " " bitfld.long 0x00 11. " TIM_CAP_GPIO1_IRQ_EN ,0 = Event on GPIO1 does not create a CAPTIM interrrupt_1 = Event on GPIO1 creates a CAPTIM interrrupt" "0,1" bitfld.long 0x00 10. " TIM_IN4_EVENT_FALL_EN ,Event input 4 edge type_1 = falling edge_0 = rising edge" "0,1" bitfld.long 0x00 9. " TIM_IN3_EVENT_FALL_EN ,Event input 3 edge type_1 = falling edge_0 = rising edge" "0,1" textline " " bitfld.long 0x00 8. " TIM_CLK_EN ,Timer clock enable_1 = clock enabled_0 = clock disabled" "0,1" bitfld.long 0x00 7. " TIM_SYS_CLK_EN ,Select clock_1 = Timer uses the DIVN clock_0 = Timer uses the lp clock" "0,1" bitfld.long 0x00 6. " TIM_FREE_RUN_MODE_EN ,Valid when timer counts up, if it is '1' timer does not zero when reaches to reload value. it becomes zero only when it reaches the max value" "0,1" textline " " bitfld.long 0x00 5. " TIM_IRQ_EN ,Interrupt mask_1 = timer IRQ is unmasked_0 = timer IRQ is masked" "0,1" bitfld.long 0x00 4. " TIM_IN2_EVENT_FALL_EN ,Event input 2 edge type_1 = falling edge_0 = rising edge" "0,1" bitfld.long 0x00 3. " TIM_IN1_EVENT_FALL_EN ,Event input 1 edge type_1 = falling edge_0 = rising edge" "0,1" textline " " bitfld.long 0x00 2. " TIM_COUNT_DOWN_EN ,Timer count direction_1 = down_0 = up" "0,1" bitfld.long 0x00 1. " TIM_ONESHOT_MODE_EN ,Timer mode_1 = One shot enabled_0 = Counter enabled" "0,1" bitfld.long 0x00 0. " TIM_EN ,Timer enable_1 = On_0 = Off" "0,1" group.long 0xC++0x3 line.long 0x00 "TIMER_GPIO1_CONF_REG,Timer gpio1 selection" bitfld.long 0x00 0.--5. " TIM_GPIO1_CONF ,Select one of the 32 GPIOs as IN1, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x3 line.long 0x00 "TIMER_GPIO2_CONF_REG,Timer gpio2 selection" bitfld.long 0x00 0.--5. " TIM_GPIO2_CONF ,Select one of the 32 GPIOs as IN2, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x34++0x3 line.long 0x00 "TIMER_GPIO3_CONF_REG,Timer gpio3 selection" bitfld.long 0x00 0.--5. " TIM_GPIO3_CONF ,Select one of the 32 GPIOs as IN3, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x3 line.long 0x00 "TIMER_GPIO4_CONF_REG,Timer gpio4 selection" bitfld.long 0x00 0.--5. " TIM_GPIO4_CONF ,Select one of the 32 GPIOs as IN4, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "TIMER_PRESCALER_REG,Timer prescaler value" bitfld.long 0x00 0.--4. " TIM_PRESCALER ,Defines the timer count frequency. CLOCK frequency / (TIM_PRESCALER+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "TIMER_PRESCALER_VAL_REG,Timer prescaler counter valuew" rbitfld.long 0x00 0.--4. " TIM_PRESCALER_VAL ,Gives the current prescaler counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "TIMER_PWM_DC_REG,Timer pwm dc register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_DC ,Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1)" group.long 0x2C++0x3 line.long 0x00 "TIMER_PWM_FREQ_REG,Timer pwm frequency register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_FREQ ,Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)_Timer clock is clock after prescaler" group.long 0x14++0x3 line.long 0x00 "TIMER_RELOAD_REG,Timer reload value and Delay in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_RELOAD ,Reload or max value in timer mode, Delay phase duration in oneshot mode. Actual delay is the register value plus synchronization time (3 clock cycles)" group.long 0x18++0x3 line.long 0x00 "TIMER_SHOTWIDTH_REG,Timer Shot duration in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_SHOTWIDTH ,Shot phase duration in oneshot mode" group.long 0x8++0x3 line.long 0x00 "TIMER_STATUS_REG,Timer status register" rbitfld.long 0x00 7. " TIM_GPIO4_EVENT_PENDING ,When 1, GPIO4 event is pending" "0,1" rbitfld.long 0x00 6. " TIM_GPIO3_EVENT_PENDING ,When 1, GPIO3 event is pending" "0,1" rbitfld.long 0x00 5. " TIM_GPIO2_EVENT_PENDING ,When 1, GPIO2 event is pending" "0,1" textline " " rbitfld.long 0x00 4. " TIM_GPIO1_EVENT_PENDING ,When 1, GPIO1 event is pending." "0,1" rbitfld.long 0x00 2.--3. " TIM_ONESHOT_PHASE ,OneShot phase_0 = Wait for event_1 = Delay phase_2 = Start Shot_3 = Shot phase" "0,1,2,3" rbitfld.long 0x00 1. " TIM_IN2_STATE ,Gives the logic level of the IN1" "0,1" textline " " rbitfld.long 0x00 0. " TIM_IN1_STATE ,Gives the logic level of the IN2" "0,1" group.long 0x4++0x3 line.long 0x00 "TIMER_TIMER_VAL_REG,Timer counter value" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_TIMER_VALUE ,Gives the current timer value" width 0x0B tree.end tree "TIMER2" base ad:0x50010300 width 26. group.long 0x20++0x3 line.long 0x00 "TIMER2_CAPTURE_GPIO1_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO1 ,Gives the Capture time for event on GPIO1" group.long 0x24++0x3 line.long 0x00 "TIMER2_CAPTURE_GPIO2_REG,Timer value for event on GPIO2" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO2 ,Gives the Capture time for event on GPIO2" group.long 0x34++0x3 line.long 0x00 "TIMER2_CLEAR_IRQ_REG,Timer clear interrupt" bitfld.long 0x00 0. " TIM_CLEAR_IRQ ,Write any value clear interrupt" "0,1" group.long 0x0++0x3 line.long 0x00 "TIMER2_CTRL_REG,Timer control register" bitfld.long 0x00 8. " TIM_CLK_EN ,Timer clock enable_1 = clock enabled_0 = clock disabled" "0,1" bitfld.long 0x00 7. " TIM_SYS_CLK_EN ,Select clock_1 = Timer uses the DIVN clock_0 = Timer uses the lp clock" "0,1" bitfld.long 0x00 6. " TIM_FREE_RUN_MODE_EN ,Valid when timer counts up, if it is '1' timer does not zero when reaches to reload value. it becomes zero only when it reaches the max value" "0,1" textline " " bitfld.long 0x00 5. " TIM_IRQ_EN ,Interrupt mask_1 = timer IRQ is unmasked_0 = timer IRQ is masked" "0,1" bitfld.long 0x00 4. " TIM_IN2_EVENT_FALL_EN ,Event input 2 edge type_1 = falling edge_0 = rising edge" "0,1" bitfld.long 0x00 3. " TIM_IN1_EVENT_FALL_EN ,Event input 1 edge type_1 = falling edge_0 = rising edge" "0,1" textline " " bitfld.long 0x00 2. " TIM_COUNT_DOWN_EN ,Timer count direction_1 = down_0 = up" "0,1" bitfld.long 0x00 1. " TIM_ONESHOT_MODE_EN ,Timer mode_1 = One shot enabled_0 = Counter enabled" "0,1" bitfld.long 0x00 0. " TIM_EN ,Timer enable_1 = On_0 = Off" "0,1" group.long 0xC++0x3 line.long 0x00 "TIMER2_GPIO1_CONF_REG,Timer gpio1 selection" bitfld.long 0x00 0.--5. " TIM_GPIO1_CONF ,Select one of the 32 GPIOs as IN1, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x3 line.long 0x00 "TIMER2_GPIO2_CONF_REG,Timer gpio2 selection" bitfld.long 0x00 0.--5. " TIM_GPIO2_CONF ,Select one of the 32 GPIOs as IN2, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "TIMER2_PRESCALER_REG,Timer prescaler value" bitfld.long 0x00 0.--4. " TIM_PRESCALER ,Defines the timer count frequency. CLOCK frequency / (TIM_PRESCALER+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "TIMER2_PRESCALER_VAL_REG,Timer prescaler counter valuew" rbitfld.long 0x00 0.--4. " TIM_PRESCALER_VAL ,Gives the current prescaler counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "TIMER2_PWM_DC_REG,Timer pwm dc register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_DC ,Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1)" group.long 0x2C++0x3 line.long 0x00 "TIMER2_PWM_FREQ_REG,Timer pwm frequency register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_FREQ ,Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)_Timer clock is clock after prescaler" group.long 0x14++0x3 line.long 0x00 "TIMER2_RELOAD_REG,Timer reload value and Delay in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_RELOAD ,Reload or max value in timer mode, Delay phase duration in oneshot mode. Actual delay is the register value plus synchronization time (3 clock cycles)" group.long 0x18++0x3 line.long 0x00 "TIMER2_SHOTWIDTH_REG,Timer Shot duration in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_SHOTWIDTH ,Shot phase duration in oneshot mode" group.long 0x8++0x3 line.long 0x00 "TIMER2_STATUS_REG,Timer status register" rbitfld.long 0x00 2.--3. " TIM_ONESHOT_PHASE ,OneShot phase_0 = Wait for event_1 = Delay phase_2 = Start Shot_3 = Shot phase" "0,1,2,3" rbitfld.long 0x00 1. " TIM_IN2_STATE ,Gives the logic level of the IN1" "0,1" rbitfld.long 0x00 0. " TIM_IN1_STATE ,Gives the logic level of the IN2" "0,1" group.long 0x4++0x3 line.long 0x00 "TIMER2_TIMER_VAL_REG,Timer counter value" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_TIMER_VALUE ,Gives the current timer value" width 0x0B tree.end tree "TIMER3" base ad:0x50040A00 width 26. group.long 0x20++0x3 line.long 0x00 "TIMER3_CAPTURE_GPIO1_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO1 ,Gives the Capture time for event on GPIO1" group.long 0x24++0x3 line.long 0x00 "TIMER3_CAPTURE_GPIO2_REG,Timer value for event on GPIO2" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO2 ,Gives the Capture time for event on GPIO2" group.long 0x34++0x3 line.long 0x00 "TIMER3_CLEAR_IRQ_REG,Timer clear interrupt" bitfld.long 0x00 0. " TIM_CLEAR_IRQ ,Write any value clear interrupt" "0,1" group.long 0x0++0x3 line.long 0x00 "TIMER3_CTRL_REG,Timer control register" bitfld.long 0x00 8. " TIM_CLK_EN ,Timer clock enable_1 = clock enabled_0 = clock disabled" "0,1" bitfld.long 0x00 7. " TIM_SYS_CLK_EN ,Select clock_1 = Timer uses the DIVN clock_0 = Timer uses the lp clock" "0,1" bitfld.long 0x00 6. " TIM_FREE_RUN_MODE_EN ,Valid when timer counts up, if it is '1' timer does not zero when reaches to reload value. it becomes zero only when it reaches the max value" "0,1" textline " " bitfld.long 0x00 5. " TIM_IRQ_EN ,Interrupt mask_1 = timer IRQ is unmasked_0 = timer IRQ is masked" "0,1" bitfld.long 0x00 4. " TIM_IN2_EVENT_FALL_EN ,Event input 2 edge type_1 = falling edge_0 = rising edge" "0,1" bitfld.long 0x00 3. " TIM_IN1_EVENT_FALL_EN ,Event input 1 edge type_1 = falling edge_0 = rising edge" "0,1" textline " " bitfld.long 0x00 2. " TIM_COUNT_DOWN_EN ,Timer count direction_1 = down_0 = up" "0,1" bitfld.long 0x00 0. " TIM_EN ,Timer enable_1 = On_0 = Off" "0,1" group.long 0xC++0x3 line.long 0x00 "TIMER3_GPIO1_CONF_REG,Timer gpio1 selection" bitfld.long 0x00 0.--5. " TIM_GPIO1_CONF ,Select one of the 32 GPIOs as IN1, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x3 line.long 0x00 "TIMER3_GPIO2_CONF_REG,Timer gpio2 selection" bitfld.long 0x00 0.--5. " TIM_GPIO2_CONF ,Select one of the 32 GPIOs as IN2, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "TIMER3_PRESCALER_REG,Timer prescaler value" bitfld.long 0x00 0.--4. " TIM_PRESCALER ,Defines the timer count frequency. CLOCK frequency / (TIM_PRESCALER+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "TIMER3_PRESCALER_VAL_REG,Timer prescaler counter valuew" rbitfld.long 0x00 0.--4. " TIM_PRESCALER_VAL ,Gives the current prescaler counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "TIMER3_PWM_DC_REG,Timer pwm dc register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_DC ,Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1)" group.long 0x2C++0x3 line.long 0x00 "TIMER3_PWM_FREQ_REG,Timer pwm frequency register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_FREQ ,Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)_Timer clock is clock after prescaler" group.long 0x14++0x3 line.long 0x00 "TIMER3_RELOAD_REG,Timer reload value and Delay in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_RELOAD ,Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles)" group.long 0x8++0x3 line.long 0x00 "TIMER3_STATUS_REG,Timer status register" rbitfld.long 0x00 2.--3. " TIM_ONESHOT_PHASE ,OneShot phase_0 = Wait for event_1 = Delay phase_2 = Start Shot_3 = Shot phase" "0,1,2,3" rbitfld.long 0x00 1. " TIM_IN2_STATE ,Gives the logic level of the IN1" "0,1" rbitfld.long 0x00 0. " TIM_IN1_STATE ,Gives the logic level of the IN2" "0,1" group.long 0x4++0x3 line.long 0x00 "TIMER3_TIMER_VAL_REG,Timer counter value" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_TIMER_VALUE ,Gives the current timer value" width 0x0B tree.end tree "TIMER4" base ad:0x50040B00 width 26. group.long 0x20++0x3 line.long 0x00 "TIMER4_CAPTURE_GPIO1_REG,Timer value for event on GPIO1" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO1 ,Gives the Capture time for event on GPIO1" group.long 0x24++0x3 line.long 0x00 "TIMER4_CAPTURE_GPIO2_REG,Timer value for event on GPIO2" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_CAPTURE_GPIO2 ,Gives the Capture time for event on GPIO2" group.long 0x34++0x3 line.long 0x00 "TIMER4_CLEAR_IRQ_REG,Timer clear interrupt" bitfld.long 0x00 0. " TIM_CLEAR_IRQ ,Write any value clear interrupt" "0,1" group.long 0x0++0x3 line.long 0x00 "TIMER4_CTRL_REG,Timer control register" bitfld.long 0x00 8. " TIM_CLK_EN ,Timer clock enable_1 = clock enabled_0 = clock disabled" "0,1" bitfld.long 0x00 7. " TIM_SYS_CLK_EN ,Select clock_1 = Timer uses the DIVN clock_0 = Timer uses the lp clock" "0,1" bitfld.long 0x00 6. " TIM_FREE_RUN_MODE_EN ,Valid when timer counts up, if it is '1' timer does not zero when reaches to reload value. it becomes zero only when it reaches the max value" "0,1" textline " " bitfld.long 0x00 5. " TIM_IRQ_EN ,Interrupt mask_1 = timer IRQ is unmasked_0 = timer IRQ is masked" "0,1" bitfld.long 0x00 4. " TIM_IN2_EVENT_FALL_EN ,Event input 2 edge type_1 = falling edge_0 = rising edge" "0,1" bitfld.long 0x00 3. " TIM_IN1_EVENT_FALL_EN ,Event input 1 edge type_1 = falling edge_0 = rising edge" "0,1" textline " " bitfld.long 0x00 2. " TIM_COUNT_DOWN_EN ,Timer count direction_1 = down_0 = up" "0,1" bitfld.long 0x00 0. " TIM_EN ,Timer enable_1 = On_0 = Off" "0,1" group.long 0xC++0x3 line.long 0x00 "TIMER4_GPIO1_CONF_REG,Timer gpio1 selection" bitfld.long 0x00 0.--5. " TIM_GPIO1_CONF ,Select one of the 32 GPIOs as IN1, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x3 line.long 0x00 "TIMER4_GPIO2_CONF_REG,Timer gpio2 selection" bitfld.long 0x00 0.--5. " TIM_GPIO2_CONF ,Select one of the 32 GPIOs as IN2, Valid value 0-32. 1 for the first gpio, 32 for the last gpio. 0 Disable input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x3 line.long 0x00 "TIMER4_PRESCALER_REG,Timer prescaler value" bitfld.long 0x00 0.--4. " TIM_PRESCALER ,Defines the timer count frequency. CLOCK frequency / (TIM_PRESCALER+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x3 line.long 0x00 "TIMER4_PRESCALER_VAL_REG,Timer prescaler counter valuew" rbitfld.long 0x00 0.--4. " TIM_PRESCALER_VAL ,Gives the current prescaler counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x3 line.long 0x00 "TIMER4_PWM_DC_REG,Timer pwm dc register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_DC ,Defines the PWM duty cycle. TIM_PWM_DC / ( TIM_PWM_FREQ+1)" group.long 0x2C++0x3 line.long 0x00 "TIMER4_PWM_FREQ_REG,Timer pwm frequency register" hexmask.long.word 0x00 0.--15. 1. " TIM_PWM_FREQ ,Defines the PWM frequency. Timer clock frequency / (TIM_PWM_FREQ+1)_Timer clock is clock after prescaler" group.long 0x14++0x3 line.long 0x00 "TIMER4_RELOAD_REG,Timer reload value and Delay in shot mode" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_RELOAD ,Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles)" group.long 0x8++0x3 line.long 0x00 "TIMER4_STATUS_REG,Timer status register" rbitfld.long 0x00 2.--3. " TIM_ONESHOT_PHASE ,OneShot phase_0 = Wait for event_1 = Delay phase_2 = Start Shot_3 = Shot phase" "0,1,2,3" rbitfld.long 0x00 1. " TIM_IN2_STATE ,Gives the logic level of the IN1" "0,1" rbitfld.long 0x00 0. " TIM_IN1_STATE ,Gives the logic level of the IN2" "0,1" group.long 0x4++0x3 line.long 0x00 "TIMER4_TIMER_VAL_REG,Timer counter value" hexmask.long.tbyte 0x00 0.--23. 1. " TIM_TIMER_VALUE ,Gives the current timer value" width 0x0B tree.end tree "TRNG" base ad:0x50040C00 width 18. group.long 0x0++0x3 line.long 0x00 "TRNG_CTRL_REG,TRNG control register" bitfld.long 0x00 0. " TRNG_ENABLE ,0: Disable the TRNG_1: Enable the TRNG this signal is ignored when the FIFO is full" "0,1" group.long 0x4++0x3 line.long 0x00 "TRNG_FIFOLVL_REG,TRNG FIFO level register" rbitfld.long 0x00 5. " TRNG_FIFOFULL ,1:FIFO full indication. This bit is cleared if the FIFO is read" "0,1" rbitfld.long 0x00 0.--4. " TRNG_FIFOLVL ,Number of 32 bit words of random data in the FIFO (max 31) until the FIFO is full. When it is 0 and TRNG_FIFOFULL is 1, it means the FIFO is full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8++0x3 line.long 0x00 "TRNG_VER_REG,TRNG Version register" hexmask.long.byte 0x00 24.--31. 1. " TRNG_MAJ ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " TRNG_MIN ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " TRNG_SVN ,SVN revision number" width 0x0B tree.end tree "UART" base ad:0x50020000 width 22. group.long 0xFC++0x3 line.long 0x00 "UART_CTR_REG,Component Type Register" hexmask.long 0x00 0.--31. 1. " UART_CTR ,Component Type Register" group.long 0xC0++0x3 line.long 0x00 "UART_DLF_REG,Divisor Latch Fraction Register" bitfld.long 0x00 0.--3. " UART_DLF ,The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "UART_DMASA_REG,DMA Software Acknowledge" bitfld.long 0x00 0. " UART_DMASA ,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit" "0,1" group.long 0xA4++0x3 line.long 0x00 "UART_HTX_REG,Halt TX" bitfld.long 0x00 0. " UART_HALT_TX ,This register is use to halt transmissions, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled._0 = Halt TX disabled_1 = Halt TX enabled_Note, if FIFOs are not enabled, the setting of the halt TX register has no effect on operation." "0,1" group.long 0x4++0x3 line.long 0x00 "UART_IER_DLH_REG,Interrupt Enable Register" bitfld.long 0x00 7. " PTIME_DLH7 ,Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[7] of the 8 bit DLH register." "0,1" bitfld.long 0x00 5.--6. " DLH6_5 ,Divisor Latch (High): Bit[6:5] of the 8 bit DLH register" "0,1,2,3" bitfld.long 0x00 4. " ELCOLR_DLH4 ,Interrupt Enable Register: (read only) ELCOLR, this bit controls the method for clearing the status in the LSR register. This is applicable only for Overrun Error, Parity Error, Framing Error, and Break Interrupt status bits._Always 0 = LSR status bits are cleared either on reading Rx FIFO (RBR Read) or On reading LSR register._Divisor Latch (High): Bit[4] of the 8 bit DLH register" "0,1" textline " " bitfld.long 0x00 3. " EDSSI_DLH3 ,Interrupt Enable Register: reserved_Divisor Latch (High): Bit[3] of the 8 bit DLH register" "0,1" bitfld.long 0x00 2. " ELSI_DLH2 ,Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[2] of the 8 bit DLH register." "0,1" bitfld.long 0x00 1. " ETBEI_DLH1 ,Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled _Divisor Latch (High): Bit[1] of the 8 bit DLH register." "0,1" textline " " bitfld.long 0x00 0. " ERBFI_DLH0 ,Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[0] of the 8 bit DLH register." "0,1" group.long 0x8++0x3 line.long 0x00 "UART_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register" hexmask.long.byte 0x00 0.--7. 1. " IIR_FCR ,On Read Interrupt Identification Register :_Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled._00 = disabled._11 = enabled._Bits[5:4],Reserved_Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types:_0001 = no interrupt pending._0010 = THR empty._0100 = received data available._0110 = receiver line status._0111 = busy detect._1100 = character timeout._On Write FIFO Control Register_Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full_Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full_Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1_Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset." group.long 0xC++0x3 line.long 0x00 "UART_LCR_REG,Line Control Register" bitfld.long 0x00 7. " UART_DLAB ,Divisor Latch Access Bit._This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART._This bit must be cleared after initial baud rate setup in order to access other registers." "0,1" bitfld.long 0x00 6. " UART_BC ,Break Control Bit._This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared." "0,1" bitfld.long 0x00 4. " UART_EPS ,Even Parity Select. Writeable only when UART is not busy (USR[0] is zero)._This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked." "0,1" textline " " bitfld.long 0x00 3. " UART_PEN ,Parity Enable. Writeable only when UART is not busy (USR[0] is zero)_This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively._0 = parity disabled_1 = parity enabled" "0,1" bitfld.long 0x00 2. " UART_STOP ,Number of stop bits._This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data._If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit._0 = 1 stop bit_1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit" "0,1" bitfld.long 0x00 0.--1. " UART_DLS ,Data Length Select._This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows:_00 = 5 bits_01 = 6 bits_10 = 7 bits_11 = 8 bits" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "UART_LSR_REG,Line Status Register" rbitfld.long 0x00 7. " UART_RFE ,Receiver FIFO Error bit._This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO._0 = no error in RX FIFO_1 = error in RX FIFO_This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO." "0,1" rbitfld.long 0x00 6. " UART_TEMT ,Transmitter Empty bit._If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty." "0,1" rbitfld.long 0x00 5. " UART_THRE ,Transmit Holding Register Empty bit._If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty._This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting." "0,1" textline " " rbitfld.long 0x00 4. " UART_BI ,Break Interrupt bit._This is used to indicate the detection of a break sequence on the serial input data._It is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits._In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO._Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read." "0,1" rbitfld.long 0x00 3. " UART_FE ,Framing Error bit._This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data._In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO._When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no framing error_1 = framing error_Reading the LSR clears the FE bit." "0,1" rbitfld.long 0x00 2. " UART_PE ,Parity Error bit._This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set._In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO._It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no parity error_1 = parity error_Reading the LSR clears the PE bit." "0,1" textline " " rbitfld.long 0x00 1. " UART_OE ,Overrun error bit._This is used to indicate the occurrence of an overrun error._This occurs if a new data character was received before the previous data was read._In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost._0 = no overrun error_1 = overrun error_Reading the LSR clears the OE bit." "0,1" rbitfld.long 0x00 0. " UART_DR ,Data Ready bit._This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO._0 = no data ready_1 = data ready_This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode." "0,1" group.long 0x10++0x3 line.long 0x00 "UART_MCR_REG,Modem Control Register" bitfld.long 0x00 4. " UART_LB ,LoopBack Bit._This is used to put the UART into a diagnostic mode for test purposes._If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally._If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line." "0,1" group.long 0x0++0x3 line.long 0x00 "UART_RBR_THR_DLL_REG,Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " RBR_THR_DLL ,Receive Buffer Register: (RBR)._This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur._Transmit Holding Register: (THR)_This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost._Divisor Latch (Low): (DLL)_This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)_Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data._Divisor Latch (Low): (DLH) (Note: This register is placed in UART_IER_DLH_REG with offset 0x4)_Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)._Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data" group.long 0x84++0x3 line.long 0x00 "UART_RFL_REG,Receive FIFO Level" rbitfld.long 0x00 0.--4. " UART_RECEIVE_FIFO_LEVEL ,Receive FIFO Level._This is indicates the number of data entries in the receive FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x90++0x3 line.long 0x00 "UART_SBCR_REG,Shadow Break Control Register" bitfld.long 0x00 0. " UART_SHADOW_BREAK_CONTROL ,Shadow Break Control Bit._This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device._If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART_SCR_REG,Scratchpad Register" hexmask.long.byte 0x00 0.--7. 1. " UART_SCRATCH_PAD ,This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl." group.long 0x94++0x3 line.long 0x00 "UART_SDMAM_REG,Shadow DMA Mode" bitfld.long 0x00 0. " UART_SHADOW_DMA_MODE ,Shadow DMA Mode._This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals._0 = mode 0_1 = mode 1" "0,1" group.long 0x98++0x3 line.long 0x00 "UART_SFE_REG,Shadow FIFO Enable" bitfld.long 0x00 0. " UART_SHADOW_FIFO_ENABLE ,Shadow FIFO Enable._This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset." "0,1" group.long 0x30++0x3 line.long 0x00 "UART_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x58++0x3 line.long 0x00 "UART_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x5C++0x3 line.long 0x00 "UART_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x60++0x3 line.long 0x00 "UART_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x64++0x3 line.long 0x00 "UART_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x68++0x3 line.long 0x00 "UART_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x6C++0x3 line.long 0x00 "UART_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x34++0x3 line.long 0x00 "UART_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x38++0x3 line.long 0x00 "UART_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x3C++0x3 line.long 0x00 "UART_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x40++0x3 line.long 0x00 "UART_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x44++0x3 line.long 0x00 "UART_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x48++0x3 line.long 0x00 "UART_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x4C++0x3 line.long 0x00 "UART_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x50++0x3 line.long 0x00 "UART_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x54++0x3 line.long 0x00 "UART_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x88++0x3 line.long 0x00 "UART_SRR_REG,Software Reset Register" bitfld.long 0x00 2. " UART_XFR ,XMIT FIFO Reset._This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 1. " UART_RFR ,RCVR FIFO Reset._This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty._Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 0. " UART_UR ,UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset." "0,1" group.long 0x9C++0x3 line.long 0x00 "UART_SRT_REG,Shadow RCVR Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_RCVR_TRIGGER ,Shadow RCVR Trigger._This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated._This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported:_00 = 1 character in the FIFO_01 = FIFO ? full_10 = FIFO ? full_11 = FIFO 2 less than full" "0,1,2,3" group.long 0xA0++0x3 line.long 0x00 "UART_STET_REG,Shadow TX Empty Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_TX_EMPTY_TRIGGER ,Shadow TX Empty Trigger._This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated._This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported:_00 = FIFO empty_01 = 2 characters in the FIFO_10 = FIFO ? full_11 = FIFO ? full" "0,1,2,3" group.long 0x80++0x3 line.long 0x00 "UART_TFL_REG,Transmit FIFO Level" rbitfld.long 0x00 0.--4. " UART_TRANSMIT_FIFO_LEVEL ,Transmit FIFO Level._This is indicates the number of data entries in the transmit FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF8++0x3 line.long 0x00 "UART_UCV_REG,Component Version" hexmask.long 0x00 0.--31. 1. " UART_UCV ,Component Version" group.long 0x7C++0x3 line.long 0x00 "UART_USR_REG,UART Status register" rbitfld.long 0x00 4. " UART_RFF ,Receive FIFO Full._This is used to indicate that the receive FIFO is completely full._0 = Receive FIFO not full_1 = Receive FIFO Full_This bit is cleared when the RX FIFO is no longer full." "0,1" rbitfld.long 0x00 3. " UART_RFNE ,Receive FIFO Not Empty._This is used to indicate that the receive FIFO contains one or more entries._0 = Receive FIFO is empty_1 = Receive FIFO is not empty_This bit is cleared when the RX FIFO is empty." "0,1" rbitfld.long 0x00 2. " UART_TFE ,Transmit FIFO Empty._This is used to indicate that the transmit FIFO is completely empty._0 = Transmit FIFO is not empty_1 = Transmit FIFO is empty_This bit is cleared when the TX FIFO is no longer empty." "0,1" textline " " rbitfld.long 0x00 1. " UART_TFNF ,Transmit FIFO Not Full._This is used to indicate that the transmit FIFO in not full._0 = Transmit FIFO is full_1 = Transmit FIFO is not full_This bit is cleared when the TX FIFO is full." "0,1" rbitfld.long 0x00 0. " UART_BUSY ,UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the uart is idle or inactive._0 = uart is idle or inactive_1 =uart is busy (actively transferring data)_Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock" "0,1" width 0x0B tree.end tree "UART2" base ad:0x50020100 width 23. group.long 0xFC++0x3 line.long 0x00 "UART2_CTR_REG,Component Type Register" hexmask.long 0x00 0.--31. 1. " UART_CTR ,Component Type Register" group.long 0xC0++0x3 line.long 0x00 "UART2_DLF_REG,Divisor Latch Fraction Register" bitfld.long 0x00 0.--3. " UART_DLF ,The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "UART2_DMASA_REG,DMA Software Acknowledge" bitfld.long 0x00 0. " UART_DMASA ,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit" "0,1" group.long 0xA4++0x3 line.long 0x00 "UART2_HTX_REG,Halt TX" bitfld.long 0x00 0. " UART_HALT_TX ,This register is use to halt transmissions, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled._0 = Halt TX disabled_1 = Halt TX enabled_Note, if FIFOs are not enabled, the setting of the halt TX register has no effect on operation." "0,1" group.long 0x4++0x3 line.long 0x00 "UART2_IER_DLH_REG,Interrupt Enable Register" bitfld.long 0x00 7. " PTIME_DLH7 ,Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled _Divisor Latch (High): Bit[7] of the 8 bit DLH register." "0,1" bitfld.long 0x00 5.--6. " DLH6_5 ,Divisor Latch (High): Bit[6:5] of the 8 bit DLH register" "0,1,2,3" bitfld.long 0x00 4. " ELCOLR_DLH4 ,Interrupt Enable Register: ELCOLR (read only), this bit controls the method for clearing the status in the LSR register. This is applicable only for Overrun Error, Parity Error, Framing Error, and Break Interrupt status bits._0 = LSR status bits are cleared either on reading Rx FIFO (RBR Read) or On reading LSR register._Divisor Latch (High): Bit[4] of the 8 bit DLH register" "0,1" textline " " bitfld.long 0x00 3. " EDSSI_DLH3 ,Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[3] of the 8 bit DLH register" "0,1" bitfld.long 0x00 2. " ELSI_DLH2 ,Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[2] of the 8 bit DLH register." "0,1" bitfld.long 0x00 1. " ETBEI_DLH1 ,Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled _Divisor Latch (High): Bit[1] of the 8 bit DLH register." "0,1" textline " " bitfld.long 0x00 0. " ERBFI_DLH0 ,Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[0] of the 8 bit DLH register." "0,1" group.long 0x8++0x3 line.long 0x00 "UART2_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register" hexmask.long.byte 0x00 0.--7. 1. " IIR_FCR ,On Read Interrupt Identification Register :_Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled._Bits[5:4],Reserved_Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types:0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout._On Write FIFO Control Register_Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full_Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full_Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1_Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset." group.long 0xCC++0x3 line.long 0x00 "UART2_LCR_EXT,Line Extended Control Register" bitfld.long 0x00 3. " UART_TRANSMIT_MODE ,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers._1 = In this mode of operation, Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The user needs to ensure that the THR/STHR register is written correctly for address/data._Address: 9th bit is set to 1,_Data : 9th bit is set to 0._Note: Transmit address register (TAR) is not applicable in this mode of operation._0 = In this mode of operation, Transmit Holding Register (THR) and Shadow Transmit Holding register (STHR) are 8-bit wide. The user needs to program the address into Transmit Address Register (TAR) and data into the THR/STHR register. SEND_ADDR bit is used as a control knob to indicate the uart on when to send the address" "0,1" bitfld.long 0x00 2. " UART_SEND_ADDR ,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode._1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what is being programmed in 'Transmit Address Register'._0 = 9-bit character will be transmitted with 9-th bit set to 0 and the remaining 8-bits will be taken from the TXFIFO which is programmed through 8-bit wide THR/STHR register._Note:_1. This bit is auto-cleared by the hardware, after sending out the address character. User is not expected to program this bit to 0._2. This field is applicable only when DLS_E bit is set to 1 and TRANSMIT_MODE is set to 0" "0,1" bitfld.long 0x00 1. " UART_ADDR_MATCH ,Address Match Mode.This bit is used to enable the address match feature during receive._1 = Address match mode; uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with what is programmed in 'Receive Address Match Register'. If match is found, then sub-sequent characters will be treated as valid data and DW_apb_uart starts receiving data._0 = Normal mode; DW_apb_uart will start to receive the data and 9-bit character will be formed and written into the receive RXFIFO. User is responsible to read the data and differentiate b/n address and data._Note: This field is applicable only when DLS_E is set to 1" "0,1" textline " " bitfld.long 0x00 0. " UART_DLS_E ,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers" "0,1" group.long 0xC++0x3 line.long 0x00 "UART2_LCR_REG,Line Control Register" bitfld.long 0x00 7. " UART_DLAB ,Divisor Latch Access Bit._This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART._This bit must be cleared after initial baud rate setup in order to access other registers." "0,1" bitfld.long 0x00 6. " UART_BC ,Break Control Bit._This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared" "0,1" bitfld.long 0x00 5. " UART_SP ,Stick Parity. (writeable only when UART is not busy USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN, EPS and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0. If PEN and Stick Parity are set to 1 and EPS is a logic 0, then parity bit is transmitted and checked as a logic 1. If this bit is set to 0, Stick Parity is disabled." "0,1" textline " " bitfld.long 0x00 4. " UART_EPS ,Even Parity Select. Writeable only when UART is not busy (USR[0] is zero)._This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked." "0,1" bitfld.long 0x00 3. " UART_PEN ,Parity Enable. Writeable only when UART is not busy (USR[0] is zero)_This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively._0 = parity disabled_1 = parity enabled" "0,1" bitfld.long 0x00 2. " UART_STOP ,Number of stop bits._This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data._If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit._0 = 1 stop bit_1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit" "0,1" textline " " bitfld.long 0x00 0.--1. " UART_DLS ,Data Length Select._This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows:_00 = 5 bits_01 = 6 bits_10 = 7 bits_11 = 8 bits" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "UART2_LSR_REG,Line Status Register" rbitfld.long 0x00 8. " UART_ADDR_RCVD ,Address Received Bit._If 9Bit data mode (LCR_EXT[0]=1) is enabled, this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data._1 = Indicates the character is address._0 = Indicates the character is data._In the FIFO mode, since the 9th bit is associated with a character received, it is revealed when the character with the 9th bit set to 1 is at the top of the FIFO._Reading the LSR clears the 9BIT._Note: User needs to ensure that interrupt gets cleared (reading LSR register) before the next address byte arrives. If there is a delay in clearing the interrupt, then Software will not be able to distinguish between multiple address related interrupt." "0,1" rbitfld.long 0x00 7. " UART_RFE ,Receiver FIFO Error bit._This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO._0 = no error in RX FIFO_1 = error in RX FIFO_This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO." "0,1" rbitfld.long 0x00 6. " UART_TEMT ,Transmitter Empty bit._If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty." "0,1" textline " " rbitfld.long 0x00 5. " UART_THRE ,Transmit Holding Register Empty bit._If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty._This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting." "0,1" rbitfld.long 0x00 4. " UART_BI ,Break Interrupt bit._This is used to indicate the detection of a break sequence on the serial input data._If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits._In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO._Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read." "0,1" rbitfld.long 0x00 3. " UART_FE ,Framing Error bit._This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data._In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO._When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no framing error_1 = framing error_Reading the LSR clears the FE bit." "0,1" textline " " rbitfld.long 0x00 2. " UART_PE ,Parity Error bit._This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set._In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO._It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no parity error_1 = parity error_Reading the LSR clears the PE bit." "0,1" rbitfld.long 0x00 1. " UART_OE ,Overrun error bit._This is used to indicate the occurrence of an overrun error._This occurs if a new data character was received before the previous data was read._In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost._0 = no overrun error_1 = overrun error_Reading the LSR clears the OE bit." "0,1" rbitfld.long 0x00 0. " UART_DR ,Data Ready bit._This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO._0 = no data ready_1 = data ready_This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode." "0,1" group.long 0x10++0x3 line.long 0x00 "UART2_MCR_REG,Modem Control Register" bitfld.long 0x00 5. " UART_AFCE ,Auto Flow Control Enable._When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in _Auto Flow Control_._0 = Auto Flow Control Mode disabled_1 = Auto Flow Control Mode enabled" "0,1" bitfld.long 0x00 4. " UART_LB ,LoopBack Bit._This is used to put the UART into a diagnostic mode for test purposes._Data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n) are looped back to the inputs, internally" "0,1" bitfld.long 0x00 1. " UART_RTS ,Request to Send._This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data._When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low._Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input." "0,1" group.long 0x18++0x3 line.long 0x00 "UART2_MSR_REG,Modem Status Register" rbitfld.long 0x00 4. " UART_CTS ,Clear to Send._This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl._0 = cts_n input is de-asserted (logic 1)_1 = cts_n input is asserted (logic 0)_In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS)." "0,1" rbitfld.long 0x00 0. " UART_DCTS ,Delta Clear to Send._This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read._0 = no change on cts_n since last read of MSR_1 = change on cts_n since last read of MSR_Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS)._Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted." "0,1" group.long 0xC4++0x3 line.long 0x00 "UART2_RAR_REG,Receive Address Register" hexmask.long.byte 0x00 0.--7. 1. " UART_RAR ,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0 will be treated as data byte until the next address byte is received._Note:_- This register is applicable only when 'ADDR_MATCH'(LCR_EXT[1] and 'DLS_E' (LCR_EXT[0]) bits are set to 1._RAR should be programmed only when UART is not busy" group.long 0x0++0x3 line.long 0x00 "UART2_RBR_THR_DLL_REG,Receive Buffer Register" bitfld.long 0x00 8. " RBR_THR_9BIT ,When 9BIT_DATA_EN, On read :Receive Buffer bit 8 - On write Transmit Buffer bit 8 when LCR_EXT[3]=1" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RBR_THR_DLL ,Receive Buffer Register: (RBR)._This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur._Transmit Holding Register: (THR)_This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost._Divisor Latch (Low): (DLL)_This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)_Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data._Divisor Latch (Low): (DLH) (Note: This register is placed in UART_IER_DLH_REG with offset 0x4)_Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)._Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data" group.long 0x84++0x3 line.long 0x00 "UART2_RFL_REG,Receive FIFO Level" rbitfld.long 0x00 0.--4. " UART_RECEIVE_FIFO_LEVEL ,Receive FIFO Level._This is indicates the number of data entries in the receive FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x90++0x3 line.long 0x00 "UART2_SBCR_REG,Shadow Break Control Register" bitfld.long 0x00 0. " UART_SHADOW_BREAK_CONTROL ,Shadow Break Control Bit._This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device._If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART2_SCR_REG,Scratchpad Register" hexmask.long.byte 0x00 0.--7. 1. " UART_SCRATCH_PAD ,This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl." group.long 0x94++0x3 line.long 0x00 "UART2_SDMAM_REG,Shadow DMA Mode" bitfld.long 0x00 0. " UART_SHADOW_DMA_MODE ,Shadow DMA Mode._This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals._0 = mode 0_1 = mode 1" "0,1" group.long 0x98++0x3 line.long 0x00 "UART2_SFE_REG,Shadow FIFO Enable" bitfld.long 0x00 0. " UART_SHADOW_FIFO_ENABLE ,Shadow FIFO Enable._This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset." "0,1" group.long 0x30++0x3 line.long 0x00 "UART2_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x58++0x3 line.long 0x00 "UART2_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x5C++0x3 line.long 0x00 "UART2_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x60++0x3 line.long 0x00 "UART2_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x64++0x3 line.long 0x00 "UART2_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x68++0x3 line.long 0x00 "UART2_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x6C++0x3 line.long 0x00 "UART2_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x34++0x3 line.long 0x00 "UART2_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x38++0x3 line.long 0x00 "UART2_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x3C++0x3 line.long 0x00 "UART2_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x40++0x3 line.long 0x00 "UART2_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x44++0x3 line.long 0x00 "UART2_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x48++0x3 line.long 0x00 "UART2_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x4C++0x3 line.long 0x00 "UART2_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x50++0x3 line.long 0x00 "UART2_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x54++0x3 line.long 0x00 "UART2_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x88++0x3 line.long 0x00 "UART2_SRR_REG,Software Reset Register" bitfld.long 0x00 2. " UART_XFR ,XMIT FIFO Reset._This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 1. " UART_RFR ,RCVR FIFO Reset._This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty._Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 0. " UART_UR ,UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset." "0,1" group.long 0x8C++0x3 line.long 0x00 "UART2_SRTS_REG,Shadow Request to Send" bitfld.long 0x00 0. " UART_SHADOW_REQUEST_TO_SEND ,Shadow Request to Send._This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to_performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data._When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high._In Auto Flow Control, (active MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold)._Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input." "0,1" group.long 0x9C++0x3 line.long 0x00 "UART2_SRT_REG,Shadow RCVR Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_RCVR_TRIGGER ,Shadow RCVR Trigger._This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated._This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported:_00 = 1 character in the FIFO_01 = FIFO ? full_10 = FIFO ? full_11 = FIFO 2 less than full" "0,1,2,3" group.long 0xA0++0x3 line.long 0x00 "UART2_STET_REG,Shadow TX Empty Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_TX_EMPTY_TRIGGER ,Shadow TX Empty Trigger._This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated._This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported:_00 = FIFO empty_01 = 2 characters in the FIFO_10 = FIFO ? full_11 = FIFO ? full" "0,1,2,3" group.long 0xC8++0x3 line.long 0x00 "UART2_TAR_REG,Transmit Address Register" hexmask.long.byte 0x00 0.--7. 1. " UART_TAR ,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled, then uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR' (LCR_EXT[2]) bit is set to 1._Note:_- This register is used only to send the address. The normal data should be sent by programming THR register._- Once the address is started to send on the DW_apb_uart serial lane, then 'SEND_ADDR' bit will be auto-cleared by the hardware" group.long 0x80++0x3 line.long 0x00 "UART2_TFL_REG,Transmit FIFO Level" rbitfld.long 0x00 0.--4. " UART_TRANSMIT_FIFO_LEVEL ,Transmit FIFO Level._This is indicates the number of data entries in the transmit FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF8++0x3 line.long 0x00 "UART2_UCV_REG,Component Version" hexmask.long 0x00 0.--31. 1. " UART_UCV ,Component Version" group.long 0x7C++0x3 line.long 0x00 "UART2_USR_REG,UART Status register" rbitfld.long 0x00 4. " UART_RFF ,Receive FIFO Full._This is used to indicate that the receive FIFO is completely full._0 = Receive FIFO not full_1 = Receive FIFO Full_This bit is cleared when the RX FIFO is no longer full." "0,1" rbitfld.long 0x00 3. " UART_RFNE ,Receive FIFO Not Empty._This is used to indicate that the receive FIFO contains one or more entries._0 = Receive FIFO is empty_1 = Receive FIFO is not empty_This bit is cleared when the RX FIFO is empty." "0,1" rbitfld.long 0x00 2. " UART_TFE ,Transmit FIFO Empty._This is used to indicate that the transmit FIFO is completely empty._0 = Transmit FIFO is not empty_1 = Transmit FIFO is empty_This bit is cleared when the TX FIFO is no longer empty." "0,1" textline " " rbitfld.long 0x00 1. " UART_TFNF ,Transmit FIFO Not Full._This is used to indicate that the transmit FIFO in not full._0 = Transmit FIFO is full_1 = Transmit FIFO is not full_This bit is cleared when the TX FIFO is full." "0,1" rbitfld.long 0x00 0. " UART_BUSY ,UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock" "0,1" width 0x0B tree.end tree "UART3" base ad:0x50020200 width 23. group.long 0x1C++0x3 line.long 0x00 "UART3_CONFIG_REG,ISO7816 Config Register" bitfld.long 0x00 3.--7. " ISO7816_SCRATCH_PAD ,This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " ISO7816_ENABLE ,0 : Normal Uart_1 : ISO7816 Enabled" "0,1" bitfld.long 0x00 1. " ISO7816_ERR_SIG_EN ,0 : Error Signal feature disabled_1 : Error Signal feature enabled" "0,1" textline " " bitfld.long 0x00 0. " ISO7816_CONVENTION ,0 : Direct convention_1 : Inverse convention" "0,1" group.long 0xE0++0x3 line.long 0x00 "UART3_CTRL_REG,ISO7816 Control Register" bitfld.long 0x00 11. " ISO7816_AUTO_GT ,0 : uart sends when tx data is available_1 : uart sends new character after guard time" "0,1" bitfld.long 0x00 10. " ISO7816_ERR_TX_VALUE_IRQMASK ,0 : ERR_TX_VALUE IRQ is masked_1 : ERR_TX_VALUE IRQ is enabled" "0,1" bitfld.long 0x00 9. " ISO7816_ERR_TX_TIME_IRQMASK ,0 : ERR_TX_TIME IRQ is masked_1 : ERR_TX_TIME IRQ is enabled" "0,1" textline " " bitfld.long 0x00 8. " ISO7816_TIM_EXPIRED_IRQMASK ,0 : timer expired IRQ is masked_1 : timer expired IRQ is enabled" "0,1" rbitfld.long 0x00 7. " ISO7816_CLK_STATUS ,0 : iso7816 clock is stopped_1 : iso7816 clock is running" "0,1" bitfld.long 0x00 6. " ISO7816_CLK_LEVEL ,0 : iso7816 clock level low when stopped_1 : iso7816 clock level high when stopped" "0,1" textline " " bitfld.long 0x00 5. " ISO7816_CLK_EN ,0 : iso7816 clock disabled_1 : iso7816 clock enabled" "0,1" bitfld.long 0x00 0.--4. " ISO7816_CLK_DIV ,ISO7816 clk freq = sclk/(2*(ISO7816_CLK_DIV+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xFC++0x3 line.long 0x00 "UART3_CTR_REG,Component Type Register" hexmask.long 0x00 0.--31. 1. " UART_CTR ,Component Type Register" group.long 0xC0++0x3 line.long 0x00 "UART3_DLF_REG,Divisor Latch Fraction Register" bitfld.long 0x00 0.--3. " UART_DLF ,The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "UART3_DMASA_REG,DMA Software Acknowledge" bitfld.long 0x00 0. " UART_DMASA ,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit" "0,1" group.long 0xE8++0x3 line.long 0x00 "UART3_ERR_CTRL_REG,ISO7816 Error Signal Control Register" bitfld.long 0x00 4.--8. " ISO7816_ERR_PULSE_WIDTH ,When Error Signal feature is enable and receive mode, it gives the width of the error signal in 1/16etu" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " ISO7816_ERR_PULSE_OFFSET ,When Error Signal feature is enable and receive mode, it gives the offset of the error signal in 1/16etu from the 9.6etu" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "UART3_HTX_REG,Halt TX" bitfld.long 0x00 0. " UART_HALT_TX ,This register is use to halt transmissions, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled._0 = Halt TX disabled_1 = Halt TX enabled_Note, if FIFOs are not enabled, the setting of the halt TX register has no effect on operation." "0,1" group.long 0x4++0x3 line.long 0x00 "UART3_IER_DLH_REG,Interrupt Enable Register" bitfld.long 0x00 7. " PTIME_DLH7 ,Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled _Divisor Latch (High): Bit[7] of the 8 bit DLH register." "0,1" bitfld.long 0x00 5.--6. " DLH6_5 ,Divisor Latch (High): Bit[6:5] of the 8 bit DLH register" "0,1,2,3" bitfld.long 0x00 4. " ELCOLR_DLH4 ,Interrupt Enable Register: ELCOLR (read only), this bit controls the method for clearing the status in the LSR register. This is applicable only for Overrun Error, Parity Error, Framing Error, and Break Interrupt status bits._0 = LSR status bits are cleared either on reading Rx FIFO (RBR Read) or On reading LSR register._Divisor Latch (High): Bit[4] of the 8 bit DLH register" "0,1" textline " " bitfld.long 0x00 3. " EDSSI_DLH3 ,Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[3] of the 8 bit DLH register" "0,1" bitfld.long 0x00 2. " ELSI_DLH2 ,Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[2] of the 8 bit DLH register." "0,1" bitfld.long 0x00 1. " ETBEI_DLH1 ,Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled _Divisor Latch (High): Bit[1] of the 8 bit DLH register." "0,1" textline " " bitfld.long 0x00 0. " ERBFI_DLH0 ,Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled_Divisor Latch (High): Bit[0] of the 8 bit DLH register." "0,1" group.long 0x8++0x3 line.long 0x00 "UART3_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register" hexmask.long.byte 0x00 0.--7. 1. " IIR_FCR ,On Read Interrupt Identification Register :_Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled._Bits[5:4],Reserved_Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types:0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout._On Write FIFO Control Register_Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full_Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full_Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1_Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit._Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset." group.long 0xEC++0x3 line.long 0x00 "UART3_IRQ_STATUS_REG,ISO7816 Interrupt Status Register" bitfld.long 0x00 2. " ISO7816_ERR_TX_VALUE_IRQ ,On read_1 : : If error signal is enabled and in transmit mode, module generates IRQ when receiver does not receive correctly the character_On Write_1 : Clear IRQ" "0,1" bitfld.long 0x00 1. " ISO7816_ERR_TX_TIME_IRQ ,On read_1 : If error signal is enabled and in transmit mode, module generates IRQ when it checks the error signal_On Write_1 : Clear IRQ" "0,1" rbitfld.long 0x00 0. " ISO7816_TIM_EXPIRED_IRQ ,On read_1 : when Timer is expired. Timer has to be disabled to clear the IRQ. When sclk is lower than pclk then this bit has to be checked if it's cleared before return form the IRQ Handler" "0,1" group.long 0xCC++0x3 line.long 0x00 "UART3_LCR_EXT,Line Extended Control Register" bitfld.long 0x00 3. " UART_TRANSMIT_MODE ,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers._1 = In this mode of operation, Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The user needs to ensure that the THR/STHR register is written correctly for address/data._Address: 9th bit is set to 1,_Data : 9th bit is set to 0._Note: Transmit address register (TAR) is not applicable in this mode of operation._0 = In this mode of operation, Transmit Holding Register (THR) and Shadow Transmit Holding register (STHR) are 8-bit wide. The user needs to program the address into Transmit Address Register (TAR) and data into the THR/STHR register. SEND_ADDR bit is used as a control knob to indicate the uart on when to send the address" "0,1" bitfld.long 0x00 2. " UART_SEND_ADDR ,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode._1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what is being programmed in 'Transmit Address Register'._0 = 9-bit character will be transmitted with 9-th bit set to 0 and the remaining 8-bits will be taken from the TXFIFO which is programmed through 8-bit wide THR/STHR register._Note:_1. This bit is auto-cleared by the hardware, after sending out the address character. User is not expected to program this bit to 0._2. This field is applicable only when DLS_E bit is set to 1 and TRANSMIT_MODE is set to 0" "0,1" bitfld.long 0x00 1. " UART_ADDR_MATCH ,Address Match Mode.This bit is used to enable the address match feature during receive._1 = Address match mode; uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with what is programmed in 'Receive Address Match Register'. If match is found, then sub-sequent characters will be treated as valid data and DW_apb_uart starts receiving data._0 = Normal mode; DW_apb_uart will start to receive the data and 9-bit character will be formed and written into the receive RXFIFO. User is responsible to read the data and differentiate b/n address and data._Note: This field is applicable only when DLS_E is set to 1" "0,1" textline " " bitfld.long 0x00 0. " UART_DLS_E ,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers" "0,1" group.long 0xC++0x3 line.long 0x00 "UART3_LCR_REG,Line Control Register" bitfld.long 0x00 7. " UART_DLAB ,Divisor Latch Access Bit._This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART._This bit must be cleared after initial baud rate setup in order to access other registers." "0,1" bitfld.long 0x00 6. " UART_BC ,Break Control Bit._This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared" "0,1" bitfld.long 0x00 5. " UART_SP ,Stick Parity. (writeable only when UART is not busy USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN, EPS and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0. If PEN and Stick Parity are set to 1 and EPS is a logic 0, then parity bit is transmitted and checked as a logic 1. If this bit is set to 0, Stick Parity is disabled." "0,1" textline " " bitfld.long 0x00 4. " UART_EPS ,Even Parity Select. Writeable only when UART is not busy (USR[0] is zero)._This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked." "0,1" bitfld.long 0x00 3. " UART_PEN ,Parity Enable. Writeable only when UART is not busy (USR[0] is zero)_This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively._0 = parity disabled_1 = parity enabled" "0,1" bitfld.long 0x00 2. " UART_STOP ,Number of stop bits._This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data._If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit._0 = 1 stop bit_1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit" "0,1" textline " " bitfld.long 0x00 0.--1. " UART_DLS ,Data Length Select._This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows:_00 = 5 bits_01 = 6 bits_10 = 7 bits_11 = 8 bits" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "UART3_LSR_REG,Line Status Register" rbitfld.long 0x00 8. " UART_ADDR_RCVD ,Address Received Bit._If 9Bit data mode (LCR_EXT[0]=1) is enabled, this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data._1 = Indicates the character is address._0 = Indicates the character is data._In the FIFO mode, since the 9th bit is associated with a character received, it is revealed when the character with the 9th bit set to 1 is at the top of the FIFO._Reading the LSR clears the 9BIT._Note: User needs to ensure that interrupt gets cleared (reading LSR register) before the next address byte arrives. If there is a delay in clearing the interrupt, then Software will not be able to distinguish between multiple address related interrupt." "0,1" rbitfld.long 0x00 7. " UART_RFE ,Receiver FIFO Error bit._This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO._0 = no error in RX FIFO_1 = error in RX FIFO_This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO." "0,1" rbitfld.long 0x00 6. " UART_TEMT ,Transmitter Empty bit._If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty." "0,1" textline " " rbitfld.long 0x00 5. " UART_THRE ,Transmit Holding Register Empty bit._If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty._This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting." "0,1" rbitfld.long 0x00 4. " UART_BI ,Break Interrupt bit._This is used to indicate the detection of a break sequence on the serial input data._If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits._In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO._Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read." "0,1" rbitfld.long 0x00 3. " UART_FE ,Framing Error bit._This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data._In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO._When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no framing error_1 = framing error_Reading the LSR clears the FE bit." "0,1" textline " " rbitfld.long 0x00 2. " UART_PE ,Parity Error bit._This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set._In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO._It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4])._0 = no parity error_1 = parity error_Reading the LSR clears the PE bit." "0,1" rbitfld.long 0x00 1. " UART_OE ,Overrun error bit._This is used to indicate the occurrence of an overrun error._This occurs if a new data character was received before the previous data was read._In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost._0 = no overrun error_1 = overrun error_Reading the LSR clears the OE bit." "0,1" rbitfld.long 0x00 0. " UART_DR ,Data Ready bit._This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO._0 = no data ready_1 = data ready_This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode." "0,1" group.long 0x10++0x3 line.long 0x00 "UART3_MCR_REG,Modem Control Register" bitfld.long 0x00 5. " UART_AFCE ,Auto Flow Control Enable._When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in _Auto Flow Control_._0 = Auto Flow Control Mode disabled_1 = Auto Flow Control Mode enabled" "0,1" bitfld.long 0x00 4. " UART_LB ,LoopBack Bit._This is used to put the UART into a diagnostic mode for test purposes._Data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n) are looped back to the inputs, internally" "0,1" bitfld.long 0x00 1. " UART_RTS ,Request to Send._This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data._When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low._Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input." "0,1" group.long 0x18++0x3 line.long 0x00 "UART3_MSR_REG,Modem Status Register" rbitfld.long 0x00 4. " UART_CTS ,Clear to Send._This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl._0 = cts_n input is de-asserted (logic 1)_1 = cts_n input is asserted (logic 0)_In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS)." "0,1" rbitfld.long 0x00 0. " UART_DCTS ,Delta Clear to Send._This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read._0 = no change on cts_n since last read of MSR_1 = change on cts_n since last read of MSR_Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS)._Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted." "0,1" group.long 0xC4++0x3 line.long 0x00 "UART3_RAR_REG,Receive Address Register" hexmask.long.byte 0x00 0.--7. 1. " UART_RAR ,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0 will be treated as data byte until the next address byte is received._Note:_- This register is applicable only when 'ADDR_MATCH'(LCR_EXT[1] and 'DLS_E' (LCR_EXT[0]) bits are set to 1._RAR should be programmed only when UART is not busy" group.long 0x0++0x3 line.long 0x00 "UART3_RBR_THR_DLL_REG,Receive Buffer Register" bitfld.long 0x00 8. " RBR_THR_9BIT ,When 9BIT_DATA_EN, On read :Receive Buffer bit 8 - On write Transmit Buffer bit 8 when LCR_EXT[3]=1" "0,1" hexmask.long.byte 0x00 0.--7. 1. " RBR_THR_DLL ,Receive Buffer Register: (RBR)._This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur._Transmit Holding Register: (THR)_This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost._Divisor Latch (Low): (DLL)_This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)_Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data._Divisor Latch (Low): (DLH) (Note: This register is placed in UART_IER_DLH_REG with offset 0x4)_Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock frequency divided by sixteen times the value of the baud rate divisor, as follows:_baud rate = (serial clock freq) / (16 * divisor)._Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data" group.long 0x84++0x3 line.long 0x00 "UART3_RFL_REG,Receive FIFO Level" rbitfld.long 0x00 0.--4. " UART_RECEIVE_FIFO_LEVEL ,Receive FIFO Level._This is indicates the number of data entries in the receive FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x90++0x3 line.long 0x00 "UART3_SBCR_REG,Shadow Break Control Register" bitfld.long 0x00 0. " UART_SHADOW_BREAK_CONTROL ,Shadow Break Control Bit._This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device._If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared" "0,1" group.long 0x94++0x3 line.long 0x00 "UART3_SDMAM_REG,Shadow DMA Mode" bitfld.long 0x00 0. " UART_SHADOW_DMA_MODE ,Shadow DMA Mode._This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals._0 = mode 0_1 = mode 1" "0,1" group.long 0x98++0x3 line.long 0x00 "UART3_SFE_REG,Shadow FIFO Enable" bitfld.long 0x00 0. " UART_SHADOW_FIFO_ENABLE ,Shadow FIFO Enable._This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset." "0,1" group.long 0x30++0x3 line.long 0x00 "UART3_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x58++0x3 line.long 0x00 "UART3_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x5C++0x3 line.long 0x00 "UART3_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x60++0x3 line.long 0x00 "UART3_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x64++0x3 line.long 0x00 "UART3_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x68++0x3 line.long 0x00 "UART3_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x6C++0x3 line.long 0x00 "UART3_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x34++0x3 line.long 0x00 "UART3_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x38++0x3 line.long 0x00 "UART3_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x3C++0x3 line.long 0x00 "UART3_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x40++0x3 line.long 0x00 "UART3_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x44++0x3 line.long 0x00 "UART3_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x48++0x3 line.long 0x00 "UART3_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x4C++0x3 line.long 0x00 "UART3_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x50++0x3 line.long 0x00 "UART3_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x54++0x3 line.long 0x00 "UART3_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " SRBR_STHRX ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost." group.long 0x88++0x3 line.long 0x00 "UART3_SRR_REG,Software Reset Register" bitfld.long 0x00 2. " UART_XFR ,XMIT FIFO Reset._This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 1. " UART_RFR ,RCVR FIFO Reset._This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty._Note that this bit is 'self-clearing'. It is not necessary to clear this bit." "0,1" bitfld.long 0x00 0. " UART_UR ,UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset." "0,1" group.long 0x8C++0x3 line.long 0x00 "UART3_SRTS_REG,Shadow Request to Send" bitfld.long 0x00 0. " UART_SHADOW_REQUEST_TO_SEND ,Shadow Request to Send._This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to_performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data._When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high._In Auto Flow Control, (active MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold)._Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input." "0,1" group.long 0x9C++0x3 line.long 0x00 "UART3_SRT_REG,Shadow RCVR Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_RCVR_TRIGGER ,Shadow RCVR Trigger._This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated._This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported:_00 = 1 character in the FIFO_01 = FIFO ? full_10 = FIFO ? full_11 = FIFO 2 less than full" "0,1,2,3" group.long 0xA0++0x3 line.long 0x00 "UART3_STET_REG,Shadow TX Empty Trigger" bitfld.long 0x00 0.--1. " UART_SHADOW_TX_EMPTY_TRIGGER ,Shadow TX Empty Trigger._This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated._This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported:_00 = FIFO empty_01 = 2 characters in the FIFO_10 = FIFO ? full_11 = FIFO ? full" "0,1,2,3" group.long 0xC8++0x3 line.long 0x00 "UART3_TAR_REG,Transmit Address Register" hexmask.long.byte 0x00 0.--7. 1. " UART_TAR ,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled, then uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR' (LCR_EXT[2]) bit is set to 1._Note:_- This register is used only to send the address. The normal data should be sent by programming THR register._- Once the address is started to send on the DW_apb_uart serial lane, then 'SEND_ADDR' bit will be auto-cleared by the hardware" group.long 0x80++0x3 line.long 0x00 "UART3_TFL_REG,Transmit FIFO Level" rbitfld.long 0x00 0.--4. " UART_TRANSMIT_FIFO_LEVEL ,Transmit FIFO Level._This is indicates the number of data entries in the transmit FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x3 line.long 0x00 "UART3_TIMER_REG,ISO7816 Timer Register" bitfld.long 0x00 17. " ISO7816_TIM_MODE ,0 : Timer will count up to max value then stops. Timer has to be disabled and enabled again to restart. Timer is clocked with the ISO7816 clock_1 : Timer will count guard time. ISO7816_TIM_MAX has to be 16*GuardTime-1" "0,1" bitfld.long 0x00 16. " ISO7816_TIM_EN ,0 : Timer is disabled_1 : Timer is enabled" "0,1" hexmask.long.word 0x00 0.--15. 1. " ISO7816_TIM_MAX ,On write : timer will count from 0 to ISO7816_TIM_MAX_On read : gives the current timer value" group.long 0xF8++0x3 line.long 0x00 "UART3_UCV_REG,Component Version" hexmask.long 0x00 0.--31. 1. " UART_UCV ,Component Version" group.long 0x7C++0x3 line.long 0x00 "UART3_USR_REG,UART Status register" rbitfld.long 0x00 4. " UART_RFF ,Receive FIFO Full._This is used to indicate that the receive FIFO is completely full._0 = Receive FIFO not full_1 = Receive FIFO Full_This bit is cleared when the RX FIFO is no longer full." "0,1" rbitfld.long 0x00 3. " UART_RFNE ,Receive FIFO Not Empty._This is used to indicate that the receive FIFO contains one or more entries._0 = Receive FIFO is empty_1 = Receive FIFO is not empty_This bit is cleared when the RX FIFO is empty." "0,1" rbitfld.long 0x00 2. " UART_TFE ,Transmit FIFO Empty._This is used to indicate that the transmit FIFO is completely empty._0 = Transmit FIFO is not empty_1 = Transmit FIFO is empty_This bit is cleared when the TX FIFO is no longer empty." "0,1" textline " " rbitfld.long 0x00 1. " UART_TFNF ,Transmit FIFO Not Full._This is used to indicate that the transmit FIFO in not full._0 = Transmit FIFO is full_1 = Transmit FIFO is not full_This bit is cleared when the TX FIFO is full." "0,1" rbitfld.long 0x00 0. " UART_BUSY ,UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock" "0,1" width 0x0B tree.end tree "USB" base ad:0x50040000 width 22. group.long 0x20++0x3 line.long 0x00 "USB_ALTEV_REG,Alternate Event Register" bitfld.long 0x00 7. " USB_RESUME ,Resume_Resume signalling is detected on the USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND), and a non IDLE signal is present on the USB, indicating that this device should begin it's wake-up sequence and enter Operational state. This bit is cleared when the register is read." "0,1" bitfld.long 0x00 6. " USB_RESET ,Reset_This bit is set to 1, when 2.5 us of SEO have been detected on the upstream port. In response, the functional state should be reset (NFS in the NFSR register is set to RESET), where it must remain for at least 100 us. The functional state can then return to Operational state. This bit is cleared when the register is read" "0,1" bitfld.long 0x00 5. " USB_SD5 ,Suspend Detect 5 ms_This bit is set to 1 after 5 ms of IDLE have been detected on the upstream port, indicating that this device is permitted to perform a remote wake-up operation. The resume may be initiated under firmware control by writing the resume value to the NFSR register. This bit is cleared when the register is read." "0,1" textline " " bitfld.long 0x00 4. " USB_SD3 ,Suspend Detect 3 ms_This bit is set to 1 after 3 ms of IDLE have been detected on the upstream port, indicating that the device should be suspended. The suspend occurs under firmware control by writing the suspend value to the Node Functional State (NFSR) register. This bit is cleared when the register is read." "0,1" bitfld.long 0x00 3. " USB_EOP ,End of Packet_A valid EOP sequence was been detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read." "0,1" group.long 0x24++0x3 line.long 0x00 "USB_ALTMSK_REG,Alternate Mask Register" bitfld.long 0x00 7. " USB_M_RESUME ,A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled._Same Bit Definition as ALTEV Register" "0,1" bitfld.long 0x00 6. " USB_M_RESET ,Same Bit Definition as ALTEV Register" "0,1" bitfld.long 0x00 5. " USB_M_SD5 ,Same Bit Definition as ALTEV Register" "0,1" textline " " bitfld.long 0x00 4. " USB_M_SD3 ,Same Bit Definition as ALTEV Register" "0,1" bitfld.long 0x00 3. " USB_M_EOP ,Same Bit Definition as ALTEV Register" "0,1" group.long 0x1A8++0x3 line.long 0x00 "USB_CHARGER_CTRL_REG,USB Charger Control Register" bitfld.long 0x00 5. " IDM_SINK_ON ,0 = Disable_1 = Enable the Idm_sink to USBm" "0,1" bitfld.long 0x00 4. " IDP_SINK_ON ,0 = Disable_1 = Enable the Idp_sink to USBp" "0,1" bitfld.long 0x00 3. " VDM_SRC_ON ,0 = Disable_1 = Enable Vdm_src to USBm and USB_DCP_DET status bit" "0,1" textline " " bitfld.long 0x00 2. " VDP_SRC_ON ,0 = Disable_1 = Enable the Vdp_src to USB_CHG_DET status bit" "0,1" bitfld.long 0x00 1. " IDP_SRC_ON ,0 = Disable_1 = Enable the Idp_src and Rdm_dwn" "0,1" bitfld.long 0x00 0. " USB_CHARGE_ON ,0 = Disable USB charger detect circuit._1 = Enable USB charger detect circuit" "0,1" group.long 0x1AC++0x3 line.long 0x00 "USB_CHARGER_STAT_REG,USB Charger Status Register" rbitfld.long 0x00 5. " USB_DM_VAL2 ,0 = USBm <2.3V_1 = USBm >2.5V" "0,1" rbitfld.long 0x00 4. " USB_DP_VAL2 ,0: USBp < 2.3V_1: USBp > 2.5V" "0,1" rbitfld.long 0x00 3. " USB_DM_VAL ,0 = USBm < 0.8V_1 = USBm > 1.5V (PS2 or Proprietary Charger)" "0,1" textline " " rbitfld.long 0x00 2. " USB_DP_VAL ,0 = USBp < 0.8V_1 = USBp > 1.5V" "0,1" rbitfld.long 0x00 1. " USB_CHG_DET ,0 = Standard downstream or nothing connected._1 = Charging Downstream Port (CDP) or Dedicated Charging" "0,1" rbitfld.long 0x00 0. " USB_DCP_DET ,0 = Charging downstream port is detected._1 = Dedicated charger is detected._Control bit VDM_SRC_ON must be set to validate this status bit._Note: This register shows the actual status" "0,1" group.long 0x1A0++0x3 line.long 0x00 "USB_DMA_CTRL_REG,USB DMA control register" bitfld.long 0x00 6. " USB_DMA_EN ,0 = USB DMA control off. (Normal operation)_1 = USB_DMA on. DMA channels 0 and 1 are connected by_USB Endpoint according bits USB_DMA_TX and USB_DMA_RX" "0,1" bitfld.long 0x00 3.--5. " USB_DMA_TX ,000 = DMA channels 1 is connected Tx USB Endpoint 1_001 = DMA channels 1 is connected Tx USB Endpoint 3_010 = DMA channels 1 is connected Tx USB Endpoint 5_100, 1xx = Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " USB_DMA_RX ,000 = DMA channels 0 is connected Rx USB Endpoint 2_001 = DMA channels 0 is connected Rx USB Endpoint 4_010 = DMA channels 0 is connected Rx USB Endpoint 6_100, 1xx = Reserved" "0,1,2,3,4,5,6,7" group.long 0x90++0x3 line.long 0x00 "USB_EP0_NAK_REG,EP0 INNAK and OUTNAK Register" rbitfld.long 0x00 1. " USB_EP0_OUTNAK ,End point 0 OUT NAK_This bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read." "0,1" rbitfld.long 0x00 0. " USB_EP0_INNAK ,End point 0 IN NAK_This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an IN token. This bit is cleared when the register is read." "0,1" group.long 0x80++0x3 line.long 0x00 "USB_EPC0_REG,Endpoint Control 0 Register" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_- The transmit FIFO is enabled and an IN token is received._- The receive FIFO is enabled and an OUT token is received._Note: A SETUP token does not cause a STALL handshake to be generated when this bit is set._Upon transmitting the STALL handshake, the RX_LAST and the TX_DONE bits in the respective Receive/Transmit Status registers are set to 1." "0,1" bitfld.long 0x00 6. " USB_DEF ,Default Address_When set to 1, the device responds to the default address regardless of the contents of FAR6-0/EP03-0 fields. When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared to 0._This bit aids in the transition from default address to assigned address. The transition from the default address 00000000000b to an address assigned during bus enumeration may not occur in the middle of the SET_ADDRESS control sequence. This is necessary to complete the control sequence. However, the address must change immediately after this sequence finishes in order to avoid errors when another control sequence immediately follows the SET_ADDRESS command._On USB reset, the firmware has 10 ms for set-up, and should write 8016 to the FAR register and 0016 to the EPC0 register. On receipt of a SET_ADDRESS command, the firmware must write 4016 to the EPC0 register and (8016 or ) to the FAR register. It must then queue a zero length IN packet to complete the status phase of the SET_ADDRESS control sequence." "0,1" rbitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This field holds the 4-bit Endpoint address. For Endpoint 0, these bits are hardwired to 0000b. Writing a 1 to any of the EP bits is ignored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "USB_EPC1_REG,Endpoint Control Register 1" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "USB_EPC2_REG,Endpoint Control Register 2" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC0++0x3 line.long 0x00 "USB_EPC3_REG,Endpoint Control Register 3" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD0++0x3 line.long 0x00 "USB_EPC4_REG,Endpoint Control Register 4" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE0++0x3 line.long 0x00 "USB_EPC5_REG,Endpoint Control Register 5" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF0++0x3 line.long 0x00 "USB_EPC6_REG,Endpoint Control Register 6" bitfld.long 0x00 7. " USB_STALL ,Stall_Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions:_The transmit FIFO is enabled and an IN token is received._The receive FIFO is enabled and an OUT token is received._Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token" "0,1" bitfld.long 0x00 5. " USB_ISO ,Isochronous_When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers." "0,1" bitfld.long 0x00 4. " USB_EP_EN ,Endpoint Enable_When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus." "0,1" textline " " bitfld.long 0x00 0.--3. " USB_EP ,Endpoint Address_This 4-bit field holds the endpoint address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "USB_FAR_REG,Function Address Register" bitfld.long 0x00 7. " USB_AD_EN ,Address Enable_When set to 1, USB address field bits 6-0 are used in address comparison_When cleared to 0, the device does not respond to any token on the USB bus._Note: If the DEF bit in the Endpoint Control 0 register is set, Endpoint 0 responds to the default address." "0,1" hexmask.long.byte 0x00 0.--6. 1. " USB_AD ,Address_This field holds the 7-bit function address used to transmit and receive all tokens addressed to this device." group.long 0x48++0x3 line.long 0x00 "USB_FNH_REG,Frame Number High Byte Register" rbitfld.long 0x00 7. " USB_MF ,Missed SOF Flag_This flag is set to 1, when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. This bit is set by the hardware and is cleared by reading the FNH register." "0,1" rbitfld.long 0x00 6. " USB_UL ,Unlock Flag_This bit indicates that at least two frames were received without an expected frame number, or that no valid SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN. This bit is set by the hardware and is cleared by reading the FNH register." "0,1" rbitfld.long 0x00 5. " USB_RFC ,Reset Frame Count_Writing a 1 to this bit resets the frame number to 00016, after which this bit clears itself to 0 again. This bit always reads 0." "0,1" textline " " rbitfld.long 0x00 0.--2. " USB_FN_10_8 ,Frame Number_This 3-bit field contains the three most significant bits (MSB) of the current frame number, received in the last SOF packet. If a valid frame number is not received within 12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change, the frame number is incremented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next frame number from a valid SOF packet._If the frame number low byte was read by firmware before reading the FNH register, the user actually reads the contents of a buffer register which holds the value of the three frame number bits of this register when the low byte was read. Therefore, the correct sequence to read the frame number is: FNL, FNH. Read operations to the FNH register, without first reading the Frame Number Low Byte (FNL) register directly, read the actual value of the three MSBs of the frame number." "0,1,2,3,4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "USB_FNL_REG,Frame Number Low Byte Register" hexmask.long.byte 0x00 0.--7. 1. " USB_FN ,The Frame Number Low Byte Register holds the low byte of the frame number. To ensure consistency, reading this low byte causes the three frame number bits in the FNH register to be locked until this register is read. The correct sequence to read the frame number is: FNL, FNH." group.long 0x40++0x3 line.long 0x00 "USB_FWEV_REG,FIFO Warning Event Register" rbitfld.long 0x00 4.--6. " USB_RXWARN31 ,Receive Warning n: 3:1_The bit n is set to 1 when the respective receive endpoint FIFO reaches the warning limit, as specified by the RFWL bits of the respective EPCx register. This bit is cleared when the warning condition is cleared by either reading data from the FIFO or when the FIFO is flushed." "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " USB_TXWARN31 ,Transmit Warning n: 3:1_The bit n is set to 1 when the respective transmit endpoint FIFO reaches the warning limit, as specified by the TFWL bits of the respective TXCn register, and transmission from the respective endpoint is enabled. This bit is cleared when the warning condition is cleared by either writing new data to the FIFO when the FIFO is flushed, or when transmission is done, as indicated by the TX_DONE bit in the TXSn register." "0,1,2,3,4,5,6,7" group.long 0x44++0x3 line.long 0x00 "USB_FWMSK_REG,FIFO Warning Mask Register" bitfld.long 0x00 4.--6. " USB_M_RXWARN31 ,The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " USB_M_TXWARN31 ,The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register" "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x00 "USB_MAEV_REG,Main Event Register" bitfld.long 0x00 11. " USB_CH_EV ,USB Charger event_This bit is set if one of the bits in USB_CHARGER_STAT_REG[2-0] change. This bit is cleared to 0 when if USB_CHARGER_STAT_REG is read." "0,1" bitfld.long 0x00 10. " USB_EP0_NAK ,Endpoint 0 NAK Event_This bit is an OR of EP0_NAK_REG[EP0_OUTNAK] and EP0_NAK_REG[EP0_INNAK] bits. USB_EP0_NAK is cleared to 0 when EP0_NAK_REG is read." "0,1" bitfld.long 0x00 9. " USB_EP0_RX ,Endpoint 0 Receive Event_This bit is a copy of the RXS0[RX_LAST] and is cleared to 0 when this RXS0 register is read._Note: Since Endpoint 0 implements a store and forward principle, an overrun condition for FIFO0 cannot occur" "0,1" textline " " bitfld.long 0x00 8. " USB_EP0_TX ,Endpoint 0 Transmit Event_This bit is a copy of the TXS0[TX_DONE] bit and is cleared to 0 when the TXS0 register is read._Note: Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur." "0,1" bitfld.long 0x00 7. " USB_INTR ,Master Interrupt Enable_This bit is hardwired to 0 in the Main Event (MAEV) register; bit 7 in the Main Mask (MAMSK) register is the Master Interrupt Enable." "0,1" bitfld.long 0x00 6. " USB_RX_EV ,Receive Event_This bit is set to 1 if any of the unmasked bits in the Receive Event (RXEV) register is set to 1. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared to 0 when all of the RX_LAST bits in each Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared to 0." "0,1" textline " " bitfld.long 0x00 5. " USB_ULD ,Unlocked/Locked Detected_This bit is set to 1, when the frame timer has either entered unlocked condition from a locked condition, or has re-entered a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH or FNL) register. This bit is cleared to 0 when the register is read." "0,1" bitfld.long 0x00 4. " USB_NAK ,Negative Acknowledge Event_This bit indicates that one of the unmasked NAK Event (NAKEV) register bits has been set to 1. This bit is cleared to 0 when the NAKEV register is read." "0,1" bitfld.long 0x00 3. " USB_FRAME ,Frame Event_This bit is set to 1, if the frame counter is updated with a new value. This can be due to the receipt of a valid SOF packet on the USB or to an artificial update if the frame counter was unlocked or a frame was missed. This bit is cleared to 0 when the register is read." "0,1" textline " " bitfld.long 0x00 2. " USB_TX_EV ,Transmit Event_This bit is set to 1, if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOn or TXUNDRNn) is set to 1. Therefore, it indicates that an IN transaction has been completed. This bit is cleared to 0 when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSn) register are cleared to 0." "0,1" bitfld.long 0x00 1. " USB_ALT ,Alternate Event_This bit indicates that one of the unmasked ALTEV register bits has been set to 1. This bit is cleared to 0 by reading the ALTEV register." "0,1" bitfld.long 0x00 0. " USB_WARN ,Warning Event_This bit indicates that one of the unmasked bits in the FIFO Warning Event (FWEV) register has been set to 1. This bit is cleared to 0 by reading the FWEV register." "0,1" group.long 0x1C++0x3 line.long 0x00 "USB_MAMSK_REG,Main Mask Register" bitfld.long 0x00 11. " USB_M_CH_EV ,The Main Mask Register masks out events reported in the MAEV registers. A bit set to 1, enables the interrupts for the respective event in the MAEV register. If the corresponding bit is cleared to 0, interrupt generation for this event is disabled. Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 10. " USB_M_EP0_NAK ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 9. " USB_M_EP0_RX ,Same Bit Definition as MAEV Register" "0,1" textline " " bitfld.long 0x00 8. " USB_M_EP0_TX ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 7. " USB_M_INTR ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 6. " USB_M_RX_EV ,Same Bit Definition as MAEV Register" "0,1" textline " " bitfld.long 0x00 5. " USB_M_ULD ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 4. " USB_M_NAK ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 3. " USB_M_FRAME ,Same Bit Definition as MAEV Register" "0,1" textline " " bitfld.long 0x00 2. " USB_M_TX_EV ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 1. " USB_M_ALT ,Same Bit Definition as MAEV Register" "0,1" bitfld.long 0x00 0. " USB_M_WARN ,Same Bit Definition as MAEV Register" "0,1" group.long 0x0++0x3 line.long 0x00 "USB_MCTRL_REG,Main Control Register)" bitfld.long 0x00 4. " LSMODE ,Low Speed Mode_This bit enables USB 1.5 Mbit/s low speed and swaps D+ and D- pull-up resistors. Changing speed may only be done if USBEN is set to 0._Also D+ and D- rise and fall times are adjusted according to the USB specification." "0,1" bitfld.long 0x00 3. " USB_NAT ,Node Attached_This bit indicates that this node is ready to be detected as attached to USB. When cleared to 0 the transceiver forces SE0 on the USB port to prevent the hub (to which this node is connected to) from detecting an attach event. After reset or when the USB node is disabled, this bit is cleared to 0 to give the device time before it must respond to commands. After this bit has been set to 1, the device no longer drives the USB and should be ready to receive Reset signalling from the hub._Note: This bit can only be set is USBEN is '1'" "0,1" bitfld.long 0x00 1. " USB_DBG ,Debug Mode._When this bit is set, the following registers are writable: Main Event (MAEV), Alternate Event (ALTEV), NAK Event (NAKEV), Transmit Status and Receive Status. Setting the DBG bit forces the node into a locked state. The node states can be read out of the transceiver diagnostic register (XCVDIAG) at location 0xFF6802 by setting the DIAG bit in the Test Control register (UTR)._Note: The operation of CoR bits is not effected by entering Debug mode) Note: This bit can only be set is USBEN is '1'" "0,1" textline " " bitfld.long 0x00 0. " USBEN ,USB EnableSetting this bit to 1 enables the Full/Low Speed USB node. If the USBEN bit is cleared to 0, the USB is disabled and the 48 MHz clock within the USB node is stopped. In addition, all USB registers are set to their reset state._Note that the transceiver forces SE0 on the bus to prevent the hub to detected the USB node, when it is disabled (not attached)._The USBEN bit is cleared to 0 after reset" "0,1" group.long 0x38++0x3 line.long 0x00 "USB_NAKEV_REG,NAK Event Register" rbitfld.long 0x00 4.--6. " USB_OUT31 ,OUT n: 3:1_The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1 and EP_EN in the EPCx register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read." "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " USB_IN31 ,IN n: 3:1_The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token. This bit is cleared when the register is read." "0,1,2,3,4,5,6,7" group.long 0x3C++0x3 line.long 0x00 "USB_NAKMSK_REG,NAK Mask Register" bitfld.long 0x00 4.--6. " USB_M_OUT31 ,When set and the corresponding bit in the NAKEV register is set, the NAK bit in the MAEV register is set. When cleared, the corresponding bit in the NAKEV register does not cause NAK to be set. Same Bit Definition as NAKEV Register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " USB_M_IN31 ,Same Bit Definition as NAKEV Register" "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x00 "USB_NFSR_REG,Node Functional State Register" bitfld.long 0x00 0.--1. " USB_NFS ,The Node Functional State Register reports and controls the current functional state of the USB node._00: NodeReset._This is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be cleared by software on entry to this state. On exit, DEF should be reset so the device responds to the default address._01: NodeResume_In this state, resume signalling is generated. This state should be entered by firmware to initiate a remote wake-up sequence by the device. The node must remain in this state for at least 1 ms and no more than 15 ms._10: NodeOperational_This is the normal operational state. In this state the node is configured for operation on the USB bus._11: NodeSuspend_Suspend state should be entered by firmware on detection of a Suspend event while in Operational state. While in Suspend state, the transceivers operate in their low-power suspend mode. All endpoint controllers and the bits TX_EN, LAST and RX_EN are reset, while all other internal states are frozen. On detection of bus activity, the RESUME bit in the ALTEV register is set. In response, software can cause entry to NodeOperational state." "0,1,2,3" group.long 0x9C++0x3 line.long 0x00 "USB_RXC0_REG,Receive Command 0 Register" bitfld.long 0x00 3. " USB_FLUSH ,Flush_Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. This bit is cleared to 0 on reset. This bit is equivalent to FLUSH in the TXC0 register." "0,1" bitfld.long 0x00 2. " USB_IGN_SETUP ,Ignore SETUP Tokens_When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address." "0,1" bitfld.long 0x00 1. " USB_IGN_OUT ,Ignore OUT Tokens_When this bit is set to 1, the endpoint ignores any OUT tokens directed to its configured address." "0,1" textline " " bitfld.long 0x00 0. " USB_RX_EN ,Receive Enable_OUT packet reception is disabled after every data packet is received, or when a STALL handshake is returned in response to an OUT token. A 1 must be written to this bit to re-enable data reception. Reception of SETUP packets is always enabled. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet is received with no other intervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and returns an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP packet, it must not generate a handshake. This allows recovery from a condition where the ACK of the first SETUP token was lost by the host." "0,1" group.long 0xBC++0x3 line.long 0x00 "USB_RXC1_REG,Receive Command Register 1" bitfld.long 0x00 5.--6. " USB_RFWL ,Receive FIFO Warning Limit_These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] :_00: RFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed." "0,1" bitfld.long 0x00 2. " USB_IGN_SETUP ,Ignore SETUP Tokens_When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address." "0,1" textline " " bitfld.long 0x00 0. " USB_RX_EN ,Receive Enable_OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated." "0,1" group.long 0xDC++0x3 line.long 0x00 "USB_RXC2_REG,Receive Command Register 2" bitfld.long 0x00 5.--6. " USB_RFWL ,Receive FIFO Warning Limit_These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] :_00: RFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed." "0,1" bitfld.long 0x00 2. " USB_IGN_SETUP ,Ignore SETUP Tokens_When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address." "0,1" textline " " bitfld.long 0x00 0. " USB_RX_EN ,Receive Enable_OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated." "0,1" group.long 0xFC++0x3 line.long 0x00 "USB_RXC3_REG,Receive Command Register 3" bitfld.long 0x00 5.--6. " USB_RFWL ,Receive FIFO Warning Limit_These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] :_00: RFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed." "0,1" bitfld.long 0x00 2. " USB_IGN_SETUP ,Ignore SETUP Tokens_When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address." "0,1" textline " " bitfld.long 0x00 0. " USB_RX_EN ,Receive Enable_OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated." "0,1" group.long 0x94++0x3 line.long 0x00 "USB_RXD0_REG,Receive Data 0 Register" hexmask.long.byte 0x00 0.--7. 1. " USB_RXFD ,Receive FIFO Data Byte_The firmware should expect to read only the packet payload data. The PID and CRC16 are removed from the incoming data stream automatically._In TEST mode this register allow read/write access." group.long 0xB4++0x3 line.long 0x00 "USB_RXD1_REG,Receive Data Register,1" hexmask.long.byte 0x00 0.--7. 1. " USB_RXFD ,Receive FIFO Data Byte_The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine._In TEST mode this register allow read/write access via the core bus." group.long 0xD4++0x3 line.long 0x00 "USB_RXD2_REG,Receive Data Register 2" hexmask.long.byte 0x00 0.--7. 1. " USB_RXFD ,Receive FIFO Data Byte_The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine._In TEST mode this register allow read/write access via the core bus." group.long 0xF4++0x3 line.long 0x00 "USB_RXD3_REG,Receive Data Register 3" hexmask.long.byte 0x00 0.--7. 1. " USB_RXFD ,Receive FIFO Data Byte_The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine._In TEST mode this register allow read/write access via the core bus." group.long 0x30++0x3 line.long 0x00 "USB_RXEV_REG,Receive Event Register" rbitfld.long 0x00 4.--6. " USB_RXOVRRN31 ,Receive Overrun n: 3:1_The bit n is set to 1 in the event of an overrun condition in the corresponding receive FIFO n. They are cleared to 0 when the register is read. The firmware must check the respective RX_ERR bits that packets received for the other receive endpoints (EP2, EP4 and EP6, ) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual FIFO depth)." "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " USB_RXFIFO31 ,Receive FIFO n: 3:1_The bit n is set to 1 whenever either RX_ERR or RX_LAST in the respective Receive Status register (RXSn) is set to 1. Reading the corresponding RXSn register automatically clears these bits.The CoR function is disabled, when the Freeze signal is asserted.The USB node discards all packets for Endpoint 0 received with errors. This is necessary in case of retransmission due to media errors, ensuring that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be tied up, holding corrupted data and unable to receive a retransmission of the same packet._If data streaming is used for the receive endpoints (EP2, EP4 and EP6, EP8) the firmware must check the respective RX_ERR bits to ensure the packets received are not corrupted by errors." "0,1,2,3,4,5,6,7" group.long 0x34++0x3 line.long 0x00 "USB_RXMSK_REG,Receive Mask Register" bitfld.long 0x00 4.--6. " USB_M_RXOVRRN31 ,The Receive Mask Register is used to select the bits of the RXEV registers, which causes the RX_EV bit in the MAEV register to be set to 1. When set to 1 and the corresponding bit in the RXEV register is set to 1, RX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the RXEV register does not cause RX_EV to be set to1. Same Bit Definition as RXEV Register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " USB_M_RXFIFO31 ,Same Bit Definition as RXEV Register" "0,1,2,3,4,5,6,7" group.long 0x98++0x3 line.long 0x00 "USB_RXS0_REG,Receive Status 0 Register" rbitfld.long 0x00 6. " USB_SETUP ,Setup_This bit indicates that the setup packet has been received. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read." "0,1" rbitfld.long 0x00 5. " USB_TOGGLE_RX0 ,Toggle_This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read." "0,1" rbitfld.long 0x00 4. " USB_RX_LAST ,Receive Last Bytes_This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read." "0,1" textline " " rbitfld.long 0x00 0.--3. " USB_RCOUNT ,Receive Count_This 4-bit field contains the number of bytes presently in the RX FIFO. This number is never larger than 8 for Endpoint 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "USB_RXS1_REG,Receive Status Register 1" hexmask.long.byte 0x00 8.--14. 1. " USB_RXCOUNT ,it contains the number of bytes presently in the endpoint receive FIFO (range 0..64)" rbitfld.long 0x00 7. " USB_RX_ERR ,Receive Error_When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO." "0,1" rbitfld.long 0x00 6. " USB_SETUP ,Setup_This bit indicates that the setup packet has been received. It is cleared when this register is read." "0,1" textline " " rbitfld.long 0x00 5. " USB_TOGGLE_RX ,Toggle_The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID._For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint._This bit is reset to 0 by reading the RXSn register." "0,1" rbitfld.long 0x00 4. " USB_RX_LAST ,Receive Last_This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read." "0,1" rbitfld.long 0x00 0.--3. " USB_RCOUNT ,Receive Counter_This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD8++0x3 line.long 0x00 "USB_RXS2_REG,Receive Status Register 2" hexmask.long.byte 0x00 8.--14. 1. " USB_RXCOUNT ,it contains the number of bytes presently in the endpoint receive FIFO (range 0..64)" rbitfld.long 0x00 7. " USB_RX_ERR ,Receive Error_When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO." "0,1" rbitfld.long 0x00 6. " USB_SETUP ,Setup_This bit indicates that the setup packet has been received. It is cleared when this register is read." "0,1" textline " " rbitfld.long 0x00 5. " USB_TOGGLE_RX ,Toggle_The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID._For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint._This bit is reset to 0 by reading the RXSn register." "0,1" rbitfld.long 0x00 4. " USB_RX_LAST ,Receive Last_This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read." "0,1" rbitfld.long 0x00 0.--3. " USB_RCOUNT ,Receive Counter_This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF8++0x3 line.long 0x00 "USB_RXS3_REG,Receive Status Register 3" hexmask.long.byte 0x00 8.--14. 1. " USB_RXCOUNT ,it contains the number of bytes presently in the endpoint receive FIFO (range 0..64)" rbitfld.long 0x00 7. " USB_RX_ERR ,Receive Error_When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO." "0,1" rbitfld.long 0x00 6. " USB_SETUP ,Setup_This bit indicates that the setup packet has been received. It is cleared when this register is read." "0,1" textline " " rbitfld.long 0x00 5. " USB_TOGGLE_RX ,Toggle_The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID._For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint._This bit is reset to 0 by reading the RXSn register." "0,1" rbitfld.long 0x00 4. " USB_RX_LAST ,Receive Last_This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read." "0,1" rbitfld.long 0x00 0.--3. " USB_RCOUNT ,Receive Counter_This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x3 line.long 0x00 "USB_TCR_REG,Transceiver configuration Register" bitfld.long 0x00 5.--7. " USB_VADJ ,Reference Voltage/ Threshold voltage AdjustControls the single-ended receiver threshold._Shall not be modified unless instructed by Dialog Semiconductor_Only enabled if USB_UTR_REG[7] = 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " USB_CADJ ,Transmitter Current Adjust_Controls the driver edge rate control current._Shall not be modified unless instructed by Dialog Semiconductor_Only enabled if USB_UTR_REG[7] = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x3 line.long 0x00 "USB_TXC0_REG,Transmit command 0 Register" bitfld.long 0x00 4. " USB_IGN_IN ,Ignore IN Tokens_When this bit is set to 1, the endpoint will ignore any IN tokens directed to its configured address." "0,1" bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using the FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. It is equivalent to the FLUSH bit in the RXC0 register." "0,1" bitfld.long 0x00 2. " USB_TOGGLE_TX0 ,Toggle_This bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. This bit is not altered by the hardware." "0,1" textline " " bitfld.long 0x00 0. " USB_TX_EN ,Transmission Enable_This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet, or a STALL handshake, in response to an IN token. It must be set to 1 by firmware to start packet transmission. The RX_EN bit in the Receive Command 0 (RXC0) register takes precedence over this bit; i.e. if RX_EN is set, TX_EN bit is ignored until RX_EN is reset._Zero length packets are indicated by setting this bit without writing any data to the FIFO." "0,1" group.long 0xAC++0x3 line.long 0x00 "USB_TXC1_REG,Transmit Command Register 1" bitfld.long 0x00 7. " USB_IGN_ISOMSK ,Ignore ISO Mask_This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset." "0,1" bitfld.long 0x00 5.--6. " USB_TFWL ,Transmit FIFO Warning Limit_These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set)._TFWL[1:0] :_00: TFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 4. " USB_RFF ,Refill FIFO_Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware." "0,1" textline " " bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware." "0,1" bitfld.long 0x00 2. " USB_TOGGLE_TX ,Toggle_The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used._For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated._For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers; I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID." "0,1" bitfld.long 0x00 1. " USB_LAST ,Last Byte_Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO._The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit." "0,1" textline " " bitfld.long 0x00 0. " USB_TX_EN ,Transmission Enable_This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission." "0,1" group.long 0xCC++0x3 line.long 0x00 "USB_TXC2_REG,Transmit Command Register 2" bitfld.long 0x00 7. " USB_IGN_ISOMSK ,Ignore ISO Mask_This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset." "0,1" bitfld.long 0x00 5.--6. " USB_TFWL ,Transmit FIFO Warning Limit_These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set)._TFWL[1:0] :_00: TFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 4. " USB_RFF ,Refill FIFO_Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware." "0,1" textline " " bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware." "0,1" bitfld.long 0x00 2. " USB_TOGGLE_TX ,Toggle_The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used._For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated._For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers; I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID." "0,1" bitfld.long 0x00 1. " USB_LAST ,Last Byte_Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO._The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit." "0,1" textline " " bitfld.long 0x00 0. " USB_TX_EN ,Transmission Enable_This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission." "0,1" group.long 0xEC++0x3 line.long 0x00 "USB_TXC3_REG,Transmit Command Register 3" bitfld.long 0x00 7. " USB_IGN_ISOMSK ,Ignore ISO Mask_This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset." "0,1" bitfld.long 0x00 5.--6. " USB_TFWL ,Transmit FIFO Warning Limit_These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set)._TFWL[1:0] :_00: TFWL disabled_01: Less than 5 bytes remaining in FIFO_10: Less than 9 bytes remaining in FIFO_11: Less than 17 bytes remaining in FIFO" "0,1,2,3" bitfld.long 0x00 4. " USB_RFF ,Refill FIFO_Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware." "0,1" textline " " bitfld.long 0x00 3. " USB_FLUSH ,Flush FIFO_Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware." "0,1" bitfld.long 0x00 2. " USB_TOGGLE_TX ,Toggle_The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used._For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated._For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers; I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID." "0,1" bitfld.long 0x00 1. " USB_LAST ,Last Byte_Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO._The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit." "0,1" textline " " bitfld.long 0x00 0. " USB_TX_EN ,Transmission Enable_This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission." "0,1" group.long 0x84++0x3 line.long 0x00 "USB_TXD0_REG,Transmit Data 0 Register" hexmask.long.byte 0x00 0.--7. 1. " USB_TXFD ,Transmit FIFO Data Byte_The firmware is expected to write only the packet payload data. The PID and CRC16 are created automatically." group.long 0xA4++0x3 line.long 0x00 "USB_TXD1_REG,Transmit Data Register 1" hexmask.long.byte 0x00 0.--7. 1. " USB_TXFD ,Transmit FIFO Data Byte_The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream._In TEST mode this register allow read/write access via the core bus." group.long 0xC4++0x3 line.long 0x00 "USB_TXD2_REG,Transmit Data Register 2" hexmask.long.byte 0x00 0.--7. 1. " USB_TXFD ,Transmit FIFO Data Byte_The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream._In TEST mode this register allow read/write access via the core bus." group.long 0xE4++0x3 line.long 0x00 "USB_TXD3_REG,Transmit Data Register 3" hexmask.long.byte 0x00 0.--7. 1. " USB_TXFD ,Transmit FIFO Data Byte_The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream._In TEST mode this register allow read/write access via the core bus." group.long 0x28++0x3 line.long 0x00 "USB_TXEV_REG,Transmit Event Register" rbitfld.long 0x00 4.--6. " USB_TXUDRRN31 ,Transmit Underrun n: 3:1_The bit n is a copy of the respective TX_URUN bit from the corresponding Transmit Status register (TXSn). Whenever any of the Transmit FIFOs underflows, the respective TXUDRRN bit is set to 1. These bits are cleared to 0 when the corresponding Transmit Status register is read" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " USB_TXFIFO31 ,Transmit FIFO n: 3:1_The bit n is a copy of the TX_DONE bit from the corresponding Transmit Status register (TXSn). A bit is set to 1 when the IN transaction for the corresponding transmit endpoint n has been completed. These bits are cleared to 0 when the corresponding TXSn register is read." "0,1,2,3,4,5,6,7" group.long 0x2C++0x3 line.long 0x00 "USB_TXMSK_REG,Transmit Mask Register" bitfld.long 0x00 4.--6. " USB_M_TXUDRRN31 ,The Transmit Mask Register is used to select the bits of the TXEV registers, which causes the TX_EV bit in the MAEV register to be set to 1. When a bit is set to 1 and the corresponding bit in the TXEV register is set to 1, the TX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the TXEV register does not cause TX_EV to be set to 1. Same Bit Definition as TXEV Register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " USB_M_TXFIFO31 ,Same Bit Definition as TXEV Register" "0,1,2,3,4,5,6,7" group.long 0x88++0x3 line.long 0x00 "USB_TXS0_REG,Transmit Status 0 Register" rbitfld.long 0x00 6. " USB_ACK_STAT ,Acknowledge Status_This bit indicates the status, as received from the host, of the ACK for the packet previously sent. This bit is to be interpreted when TX_DONE is set to 1. It is set to 1, when an ACK is received; otherwise, it remains cleared. This bit is also cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 5. " USB_TX_DONE ,Transmission Done_When set to 1, this bit indicates that a packet has completed transmission. It is cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 0.--4. " USB_TCOUNT ,Transmission Count_This 5-bit field indicates the number of empty bytes available in the FIFO. This field is never larger than 8 for Endpoint 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA8++0x3 line.long 0x00 "USB_TXS1_REG,Transmit Status Register 1" rbitfld.long 0x00 7. " USB_TX_URUN ,Transmit FIFO Underrun_This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 6. " USB_ACK_STAT ,Acknowledge Status_This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received; otherwise, it is cleared to 0._For ISO operation, this bit is set if a frame number LSB match (see IGN_ISOMSK bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set._This bit is also cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 5. " USB_TX_DONE ,Transmission Done_When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set:_A data packet completed transmission in response to an IN token with non-ISO operation._The endpoint sent a STALL handshake in response to an IN token_A scheduled ISO frame was transmitted or discarded._This bit is cleared to 0 when this register is read." "0,1" textline " " rbitfld.long 0x00 0.--4. " USB_TCOUNT ,Transmission Count_This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x3 line.long 0x00 "USB_TXS2_REG,Transmit Status Register 2" rbitfld.long 0x00 7. " USB_TX_URUN ,Transmit FIFO Underrun_This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 6. " USB_ACK_STAT ,Acknowledge Status_This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received; otherwise, it is cleared to 0._For ISO operation, this bit is set if a frame number LSB match (see IGN_ISOMSK bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set._This bit is also cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 5. " USB_TX_DONE ,Transmission Done_When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set:_A data packet completed transmission in response to an IN token with non-ISO operation._The endpoint sent a STALL handshake in response to an IN token_A scheduled ISO frame was transmitted or discarded._This bit is cleared to 0 when this register is read." "0,1" textline " " rbitfld.long 0x00 0.--4. " USB_TCOUNT ,Transmission Count_This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE8++0x3 line.long 0x00 "USB_TXS3_REG,Transmit Status Register 3" rbitfld.long 0x00 7. " USB_TX_URUN ,Transmit FIFO Underrun_This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 6. " USB_ACK_STAT ,Acknowledge Status_This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used._For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received; otherwise, it is cleared to 0._For ISO operation, this bit is set if a frame number LSB match (see IGN_ISOMSK bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set._This bit is also cleared to 0, when this register is read." "0,1" rbitfld.long 0x00 5. " USB_TX_DONE ,Transmission Done_When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set:_A data packet completed transmission in response to an IN token with non-ISO operation._The endpoint sent a STALL handshake in response to an IN token_A scheduled ISO frame was transmitted or discarded._This bit is cleared to 0 when this register is read." "0,1" textline " " rbitfld.long 0x00 0.--4. " USB_TCOUNT ,Transmission Count_This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC++0x3 line.long 0x00 "USB_UTR_REG,USB test Register (for test purpose only)" bitfld.long 0x00 7. " USB_DIAG ,Diagnostic enable_'0': Normal operational._'1': Access to the USB_XCVDIAG_REG and USB_TCR_REG enabled. For diagnostic purposes only" "0,1" bitfld.long 0x00 6. " USB_NCRC ,No CRC16_When this bit is set to 1, all packets transmitted by the Full/Low Speed USB node are sent without a trailing CRC16. Receive operations are unaffected. This mode is used to check that CRC errors can be detected by other nodes. For diagnostic purposes only" "0,1" bitfld.long 0x00 5. " USB_SF ,Short Frame_Enables the Frame timer to lock and track, short, non-compliant USB frame sizes. The Short Frame bit should not be set during normal operation. For test purposes only" "0,1" textline " " bitfld.long 0x00 0.--4. " USB_UTR_RES ,Reserved. Must be kept to '0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x3 line.long 0x00 "USB_UX20CDR_REG,Transceiver 2.0 Configuration and Diagnostics Register(for test purpose only)" rbitfld.long 0x00 7. " RPU_TEST7 ,Test bit" "0,1" bitfld.long 0x00 6. " RPU_TEST_SW2 ,0: Closes SW2 switch to reduced pull-up resistor connected to the USB_Dp and USB_Dm._1: Opens SW2 switch resistor connected to the USB_Dp and USB_Dm (independent of the VBus state)" "0,1" bitfld.long 0x00 5. " RPU_TEST_SW1 ,0: Enable the pull-up resistor on USB_Dp (SW1 closed)_1: Disable the pull-up resistor on USB_Dp (SW1 open) (Independent of the VBus state)" "0,1" textline " " bitfld.long 0x00 4. " RPU_TEST_EN ,Pull-Up Resistor Test Enable_0: Normal operation_1: Enables the test features controlled by RPU_TEST_SW1, RPU_TEST_SW1DM and RPU_TEST_SW2" "0,1" bitfld.long 0x00 2. " RPU_TEST_SW1DM ,0: Enable the pull-up resistor on USB_Dm (SW1DM closed)_1: Disable the pull-up resistor on USB_Dm (SW1DM open) (Independent of the VBus state)" "0,1" bitfld.long 0x00 1. " RPU_RCDELAY ,Test bit, must be kept 0" "0,1" textline " " bitfld.long 0x00 0. " RPU_SSPROTEN ,Test bit, must be kept 0" "0,1" group.long 0x4++0x3 line.long 0x00 "USB_XCVDIAG_REG,Transceiver diagnostic Register (for test purpose only)" rbitfld.long 0x00 7. " USB_VPIN ,With Bit0 = 1 this bit shows the level of the USB_Dp receive data from transceiver; i.e. D+ <= VSE." "0,1" rbitfld.long 0x00 6. " USB_VMIN ,With Bit0 = 1 this bit shows the level USB_Dm receive data from transceiver; i.e. D- <= VSE." "0,1" rbitfld.long 0x00 5. " USB_RCV ,With Bit0 = 1 this bit shows the differential level of the receive comparator." "0,1" textline " " bitfld.long 0x00 3. " USB_XCV_TXEN ,With Bit0 = 1, this bit enables test Bits 2,1. Must be kept to '0' for normal operation" "0,1" bitfld.long 0x00 2. " USB_XCV_TXN ,With Bit3,0 = 1, this bit sets USB_Dm to a high level, independent of LSMODE selection" "0,1" bitfld.long 0x00 1. " USB_XCV_TXP ,With Bit3,0 = 1, this bit sets USB_Dp to a high level, independent of LSMODE selection" "0,1" textline " " bitfld.long 0x00 0. " USB_XCV_TEST ,Enable USB_XCVDIAG_REG_0: Normal operation, test bits disabled_1: Enable test bits 7,6,5,3,2,1" "0,1" width 0x0B tree.end tree "WAKEUP" base ad:0x50000100 width 22. group.long 0x48++0x3 line.long 0x00 "WKUP_CLEAR_P0_REG,Clear event register for P0 and P1" hexmask.long 0x00 0.--31. 1. " WKUP_CLEAR_P0 ,Clear latched value of the GPIOs P0 when corresponding bit is 1" group.long 0x4C++0x3 line.long 0x00 "WKUP_CLEAR_P1_REG,Clear event register for P2" hexmask.long.tbyte 0x00 0.--22. 1. " WKUP_CLEAR_P1 ,Clear latched value of the GPIOs P1 when corresponding bit is 1" group.long 0x0++0x3 line.long 0x00 "WKUP_CTRL_REG,Control register for the wakeup counter" bitfld.long 0x00 7. " WKUP_ENABLE_IRQ ,0: no interrupt will be enabled_1: if you have an event an IRQ will be generated" "0,1" bitfld.long 0x00 6. " WKUP_SFT_KEYHIT ,0 = no effect_1 = emulate key hit. First make this bit 0 before any new key hit can be sensed." "0,1" bitfld.long 0x00 0.--5. " WKUP_DEB_VALUE ,Wakeup debounce time. If set to 0, no debouncing will be done._Debounce time: N*1 ms. N =1..63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x28++0x3 line.long 0x00 "WKUP_POL_P0_REG,select the sesitivity polarity for each P0 input" hexmask.long 0x00 0.--31. 1. " WKUP_POL_P0 ,0: enabled input P0_xx will give an event if that input goes high_1: enabled input P0_xx will give an event if that input goes low" group.long 0x2C++0x3 line.long 0x00 "WKUP_POL_P1_REG,select the sesitivity polarity for each P1 input" hexmask.long.tbyte 0x00 0.--22. 1. " WKUP_POL_P1 ,0: enabled input P1_xx will give an event if that input goes high_1: enabled input P1_xx will give an event if that input goes low" group.long 0x8++0x3 line.long 0x00 "WKUP_RESET_IRQ_REG,Reset wakeup interrupt" hexmask.long.word 0x00 0.--15. 1. " WKUP_IRQ_RST ,writing any value to this register will reset the interrupt. reading always returns 0." group.long 0x14++0x3 line.long 0x00 "WKUP_SELECT_P0_REG,select which inputs from P0 port can trigger wkup counter" hexmask.long 0x00 0.--31. 1. " WKUP_SELECT_P0 ,0: input P0_xx is not enabled for wakeup event_1: input P0_xx is enabled for wakeup event" group.long 0x18++0x3 line.long 0x00 "WKUP_SELECT_P1_REG,select which inputs from P1 port can trigger wkup counter" hexmask.long.tbyte 0x00 0.--22. 1. " WKUP_SELECT_P1 ,0: input P1_xx is not enabled for wakeup event_1: input P1_xx is enabled for wakeup event" group.long 0x54++0x3 line.long 0x00 "WKUP_SEL_GPIO_P0_REG,select which inputs from P0 port can trigger interrupt" hexmask.long 0x00 0.--31. 1. " WKUP_SEL_GPIO_P0 ,0: input P0_xx is not enabled for GPIO interrupt_1: input P0_xx is enabled for GPIO interrupt" group.long 0x58++0x3 line.long 0x00 "WKUP_SEL_GPIO_P1_REG,select which inputs from P1 port can trigger interrupt" hexmask.long.tbyte 0x00 0.--22. 1. " WKUP_SEL_GPIO_P1 ,0: input P1_xx is not enabled for GPIO interrupt_1: input P1_xx is enabled for GPIO interrupt" group.long 0x3C++0x3 line.long 0x00 "WKUP_STATUS_P0_REG,Event status register for P0 and P1" hexmask.long 0x00 0.--31. 1. " WKUP_STAT_P0 ,Contains the latched value of any toggle of the GPIOs Port P0. WKUP_STAT_P0[0] -> P0_00" group.long 0x40++0x3 line.long 0x00 "WKUP_STATUS_P1_REG,Event status register for P2" hexmask.long.tbyte 0x00 0.--22. 1. " WKUP_STAT_P1 ,Contains the latched value of any toggle of the GPIOs Port P1 WKUP_STATUS_1[0] -> P1_00" width 0x0B tree.end tree.end textline ""