; --------------------------------------------------------------------------------
; @Title: tbd.
; @Props:
; @Author: -
; @Changelog: 
; @Manufacturer: 
; @Doc: 
; @Core: 
; @Chip: 
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: per8500c.per 5580 2014-09-17 13:23:46Z jerzy $
munging.le
width 7.
tree.open "L1 Configuration Registers"
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register"
;bitfld.long  0. 31. "WID0123 ,Way 0 Instruction Disable" "0,1"
;bitfld.long  0. 30. ",Way 1 Instruction Disable" "0,1"
;bitfld.long  0. 29. ",Way 2 Instruction Disable" "0,1"
;bitfld.long  0. 28. ",Way 3 Instruction Disable" "0,1"
;bitfld.long  0. 27. "  WDD0123 ,Way 0 Data Disable" "0,1"
;bitfld.long  0. 26. ",Way 1 Data Disable" "0,1"
;bitfld.long  0. 25. ",Way 2 Data Disable" "0,1"
;bitfld.long  0. 24. ",Way 3 Data Disable" "0,1"
;bitfld.long  0. 23. "  AWDD ,Additional Ways Data Disable" "0,1"
;bitfld.long  0. 22. "  AWID ,Additional Ways Instruction Disable" "0,1"
;Textline "               "
bitfld.long  0. 16. "DCPE ,Cache Parity Enable" "0,1"
bitfld.long  0. 15. "  DPEIE ,Parity Error Injection Enable" "0,1"
bitfld.long  0. 11. "  DCSLC ,Cache Snoop Lock Clear" "0,1"
bitfld.long  0. 10. "  DCUL ,Cache Unable to Lock" "0,1"
bitfld.long  0.  9. "  DCLO ,Cache Lock Overflow" "0,1"
bitfld.long  0.  8. "  DCLFC ,Cache Lock Bits Flush Clear" "0,1"
;bitfld.long  0.  2. "  CABT ,Cache Operation Aborted" "0,1"
bitfld.long  0.  1. "  DCFI ,Cache Flush Invalidate" "0,1"
bitfld.long  0.  0. "  DCE ,Cache Enable" "0,1"
group spr:1011.--1011. "L1CSR1, L1 Cache Configuration & Status Register 1"
LINE.LONG 0. "L1CSR1,L1 Cache Configuration & Status Register 1"
;bitfld.long  0. 31. "WID0,Way 0 Instruction Disable"
;bitfld.long  0. 30. "WID1,Way 1 Instruction Disable"
;bitfld.long  0. 29. "WID2,Way 2 Instruction Disable"
;bitfld.long  0. 28. "WID3,Way 3 Instruction Disable"
;bitfld.long  0. 27. "WDD0,Way 0 Data Disable" "0,1"
;bitfld.long  0. 26. "WDD1,Way 1 Data Disable" "0,1"
;bitfld.long  0. 25. "WDD2,Way 2 Data Disable" "0,1"
;bitfld.long  0. 24. "WDD3,Way 3 Data Disable" "0,1"
;bitfld.long  0. 23. "AWID,Additional Ways Data Disable" "0,1"
;bitfld.long  0. 22. "AWID,Additional Ways Instruction Disable" "0,1"
bitfld.long  0. 16. "ICPE ,Cache Parity Enable" "0,1"
bitfld.long  0. 15. "  IPEIE ,Parity Error Injection Enable" "0,1"
bitfld.long  0. 11. "  ICSLC ,Cache Snoop Lock Clear" "0,1"
bitfld.long  0. 10. "  ICUL ,Cache Unable to Lock" "0,1"
bitfld.long  0.  9. "  ICLO ,Cache Lock Overflow" "0,1"
bitfld.long  0.  8. "  ICLFC ,Cache Lock Bits Flush Clear" "0,1"
;bitfld.long  0.  2. "CABT,Cache Operation Aborted" "0,1"
bitfld.long  0.  1. "  ICFI ,Cache Flush Invalidate" "0,1"
bitfld.long  0.  0. "  ICE ,Cache Enable" "0,1"
rgroup spr:515.--515. "L1CFG0, L1 Cache Configuration Register 0 (r/o)"
LINE.Long  0. "L1CFG0,L1 Cache Configuration Register 0"
bitfld.long  0.  30.--31. "CARCH ,Cache Architecture" "Harvard,Unified,res (10),res (11)"
bitfld.long  0.  29. "    CWPA ,Cache Way Partitioning Available" "0,1"
bitfld.long  0.  28. "  CFAHA ,Cache Flush All by Hardware Available" "0,1"
bitfld.long  0.  27. "  CFISWA ,Cache flush/inval by Set and Way Available" "0,1"
bitfld.long   0. 23.--24. "  DCBSIZE ,Cache Line Size" "32 bytes,64 bytes, res(10),res(11)"
Textline "              "
bitfld.long   0. 21.--22. "  DCREPL ,Cache Replacement Policy" "True LRU,pseudo LRU,pseudo round-robin,res(11)"
bitfld.long   0. 20. " DCLA  ,Cache Lockung APU Available" "0,1"
bitfld.long   0. 19. "  DCPA   ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  DCNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
;hexmask.byte  3. 00.--07. 1. "  DCSIZE  , Cache Size (0x20=32KB)"
bitfld.long   0. 04.--05.    "  DCSIZE , Cache Size" "8 KB,16 KB,32 KB,64 KB "
rgroup spr:516.--516. "L1CFG0, L1 Cache Configuration Register 1"
LINE.Long  0. "L1CFG1,L1 Cache Configuration Register 1 (r/o)"
bitfld.long   0. 23.--24. "ICBSIZE ,Cache Line Size" "32 Bytes,64 Bytes, res(10),res(11)"
Textline "              "
bitfld.long   0. 21.--22. "  ICREPL ,Cache Replacement Policy" "True LRU,pseudo LRU,pseudo round-robin,res(11)"
bitfld.long   0. 20. " ICLA ,Cache Lockung APU Available" "0,1"
bitfld.long   0. 19. "   ICPA   ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  ICNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
;hexmask.byte  3. 00.--07. 1. "  ICSIZE , Cache Size (0x20=32KB)"
bitfld.long   0. 04.--05.    "  ICSIZE , Cache Size" "8 KB,16 KB,32 KB,64 KB "
tree.end
sif (CPU()=="MPC8560")||(CPU()=="MPC8540")||(CPU()=="MPC8555E")||(CPU()=="MPC8541E")
tree.open "L2 Cache/SRAM Configuration Register"
base ANC:iobase.address()
GROUP.long 0x00020000++0x03
line.LONG 0x0 "L2CTL,L2 Control Register"
bitfld.long  0. 31.           "L2E  ,L2 Cache Enable" "0,1" 
bitfld.long  0. 30.           "  L2I   ,L2 Flash Invalidate" "0,1" 
bitfld.long  0. 28.--29.      "  L2SIZ ,L2 SRAM Size" "64 KByte,128 KByte,256 KByte,512 KByte" 
bitfld.long  0. 26.--27.      "  L2BLKSIZ ,L2 cache/memory-mapped SRAM block size" "64 KByte,128 KByte,256 KByte,512 KByte" 
TEXTLINE "              "
bitfld.long  0. 22.           "  L2DO ,L2 Data Only" "0,1" 
bitfld.long  0. 21.           "  L2IO  ,L2 Instruction Only" "0,1" 
bitfld.long  0. 20.           "  L2PMEXTDIS ,Memory-mapped SRAM external access disable" "0,1" 
bitfld.long  0. 19.           "  L2INTDIS ,Cache read intervention disable" "0,1" 
bitfld.long  0. 16.--18.      "  L2SRAM ,L2 block assignment" "1x Cache,1x SRAM,1x Cache + 1x SRAM,2x SRAM,?..." 
TEXTLINE "              "
bitfld.long  0. 13.           "  L2LO ,L2 cache lock overflow" "0,1" 
bitfld.long  0. 12.           "  L2SLC ,L2 snoop lock clear" "0,1" 
bitfld.long  0. 10.           "  L2LFR ,L2 cache lock bits flash reset" "0,1" 
bitfld.long  0. 08.--09.      "  L2LFRID ,L2 cache lock bits flash reset select instruction or data" "not used,data locks,instr locks,data+instr"
tree.end
endif
sif (CPU()=="MPC8533")||(CPU()=="MPC8535")||(CPU()=="MPC8536")||(CPU()=="MPC8543")||(CPU()=="MPC8544")||(CPU()=="MPC8545")||(CPU()=="MPC8547")||(CPU()=="MPC8548")||(CPU()=="MPC8567")||(CPU()=="MPC8568")||(CPU()=="MPC8569")||(CPU()=="MPC8572")||(CPU()=="P1011")||(CPU()=="P1012")||(CPU()=="P1013")||(CPU()=="P1020")||(CPU()=="P1021")||(CPU()=="P1022")||(CPU()=="P2010")||(CPU()=="P2020")
tree.open "L2 Cache/SRAM Configuration Register"
base ANC:iobase.address()
GROUP.long 0x00020000++0x03
line.LONG 0x0 "L2CTL,L2 Control Register"
bitfld.long  0. 31.           "L2E  ,L2 Cache Enable" "0,1" 
bitfld.long  0. 30.           "  L2I   ,L2 Flash Invalidate" "0,1" 
bitfld.long  0. 28.--29.      "  L2SIZ ,L2 SRAM Size" "res.,256 KByte,512 KByte,1024 KByte" 
TEXTLINE "              "
bitfld.long  0. 22.           "  L2DO ,L2 Data Only" "0,1" 
bitfld.long  0. 21.           "  L2IO  ,L2 Instruction Only" "0,1" 
bitfld.long  0. 20.           "  L2PMEXTDIS ,Memory-mapped SRAM external access disable" "0,1" 
bitfld.long  0. 19.           "  L2INTDIS ,Cache read intervention disable" "0,1" 
bitfld.long  0. 16.--18.      "  L2SRAM ,L2 SRAM configuration" "none,1,1/2,2/2,1/4,2/4,1/8,2/8" 
TEXTLINE "              "
bitfld.long  0. 13.           "  L2LO ,L2 cache lock overflow" "0,1" 
bitfld.long  0. 12.           "  L2SLC ,L2 snoop lock clear" "0,1" 
bitfld.long  0. 10.           "  L2LFR ,L2 cache lock bits flash reset" "0,1" 
bitfld.long  0. 08.--09.      "  L2LFRID ,L2 cache lock bits flash reset select instruction or data" "not used,data locks,instr locks,data+instr"
bitfld.long  0. 03.           "  L2STASHDIS ,L2 stash allocate disable" "0,1" 
bitfld.long  0. 00.--01.      "  L2STASH ,L2 stash configuration" "none,way 4-7,way 6-7,way 7"
tree.end
endif
sif (CPU()=="P4080")
tree.open "L2 Cache Configuration Registers"
group spr:1017.++0 "L2CSR0,L2 Cache Control and Status Register 0"
LINE.LONG 0. "L2CSR0,L2 Cache Control and Status Register 0"
bitfld.long 0. 31.        "L2E   ,L2 cache enable" "0,1"
bitfld.long 0. 30.      "  L2PE  ,L2 data parity generation and checking enable" "0,1"
bitfld.long 0. 26.--28. "  L2WP  ,L2 instruction/data way partitioning" "unpartitioned,1 instr - 7 data,2 instr - 6 data,3 instr - 5 data,4 instr - 4 data,5 instr - 3 data,6 instr - 2 data,7 instr - 1 data"
TEXTLINE "              "
bitfld.long 0. 21.      "  L2FI  ,L2 cache flash invalidate" "0,1"
bitfld.long 0. 20.      "  L2IO  ,L2 cache instruction only" "0,1"
bitfld.long 0. 16.      "  L2DO  ,L2 cache data only" "0,1"
bitfld.long 0. 12.--13. "  L2REP ,L2 line replacement algorithm" "SPLRU,res.,SPLPU,PLRU"
TEXTLINE "              "
bitfld.long 0. 11.      "  L2FL  ,L2 cache flush" "0,1"
bitfld.long 0. 10.      "  L2LFC ,L2 cache lock flash clear" "0,1"
bitfld.long 0. 07.      "  L2LOA ,L2 cache lock overflow allocate" "0,1"
bitfld.long 0. 05.      "  L2LO  ,L2 cache lock overflow" "0,1"
Textline ""
group spr:1018.++0 "L2CSR1,L2 Cache Control and Status Register 1"
LINE.LONG 0. "L2CSR1,L2 Cache Control and Status Register 1"
Textline ""
group spr:519.++0 "L2CFG0,L2 Configuration Register"
LINE.LONG 0. "L2CFG0,L2 Configuration Register"
tree.end
endif
Textline "             "