; --------------------------------------------------------------------------------
; @Title: e200 core CACHE registers
; @Author: rweiss
; @Chiplist: ANDORRA, BOLERO, BOLERO256K, BOLERO3M, COBRA55, COBRA90, COPPERHEAD, 
;   CORAL, DIAMONDBACK, FADO, KOMODO, LANCE, LEOPARD, MAMBA, MOCCASIN, MONACO, 
;   MPC5510, MPC5514, MPC5515, MPC5516, MPC5517, MPC5533, MPC5534, MPC5553, 
;   MPC5554, MPC5561, MPC5565, MPC5566, MPC5567, MPC55XX, MPC5601D, MPC5601P, 
;   MPC5602B, MPC5602C, MPC5602D, MPC5602P, MPC5603B, MPC5603C, MPC5603P, 
;   MPC5604B, MPC5604C, MPC5604E, MPC5604P, MPC5605B, MPC5606B, MPC5606S, 
;   MPC5607B, MPC5632M, MPC5633M, MPC5634M, MPC5642A, MPC5643L, MPC5644A, 
;   MPC5644A-V2, MPC5644B, MPC5644C, MPC5645B, MPC5645C, MPC5645S, MPC5646B, 
;   MPC5646C, MPC5668G, MPC5673K, MPC5674F, MPC5674F-V2, MPC5674K, MPC5675K, 
;   MPC5676R, MPC5770TV, MPC5777C, PICTUS, PICTUS256, PICTUS256K, PXD1005, 
;   PXD1010, PXD2020, PXN2020, PXN2120, PXR4030, PXR4040, PXS2005, PXS2010, 
;   PXS3010, PXS3015, PXS3020, PXSERIES, RAINBOW, SALSA, SPC560B40, SPC560B44, 
;   SPC560B50, SPC560B54, SPC560B60, SPC560B64, SPC560C40, SPC560C44, SPC560C50, 
;   SPC560D30, SPC560D40, SPC560P34, SPC560P40, SPC560P44, SPC560P50, SPC560S, 
;   SPC563M54, SPC563M60, SPC563M64, SPC564A70, SPC564A80, SPC564A80-V2, 
;   SPC564B64, SPC564B70, SPC564B74, SPC56AP60, SPC56EC64, SPC56EC70, SPC56EC74, 
;   SPC56EL60, SPC56EL70, SPC56HK60, SPC56HK64, SPC56HK70, SPECTRUM, TAIPAN, 
;   TIGER, VIPER
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: per5500c.per 6985 2016-06-08 15:49:29Z psurmacki $
munging.le
width 10.
tree.open "Cache Configuration Registers"
group spr:515.--515. "L1CFG0,L1 Cache Configuration Register 0"
LINE.Long  0. "L1CFG0,L1 Cache Configuration Register 0"
sif (STRING.MID(CPU(),1.,5.)=="PC567")||(STRING.MID(CPU(),0.,6.)=="MPC555")||(STRING.MID(CPU(),0.,6.)=="MPC556")||(STRING.MID(CPU(),2.,3.)=="571")||(CPU()=="MPC5668")||(CPU()=="MPC5668G")||CPUIS(MPC5777C)
bitfld.long  0.  30.--31. "CARCH ,Cache Architecture" "Harvard,Unified,res (10),res (11)"
bitfld.long  0.  29. "            CWPA ,Cache Way Partitioning Available" "0,1"
bitfld.long  0.  28. "  CFAHA ,Cache Flush All by Hardware Available" "0,1"
bitfld.long  0.  27. "  CFISWA ,Cache flush/inval by Set and Way Available" "0,1"
bitfld.long   0. 23.--24. "  CBSIZE ,Cache Line Size" "32 bytes,64 bytes, res(10),res(11)"
TEXTLINE "                 "
bitfld.long   0. 21.--22. "  CREPL ,Cache Replacement Policy" "True LRU,pseudo LRU,pseudo round-robin,FIFO"
bitfld.long   0. 20. "  CLA  ,Cache Locking APU Available" "0,1"
bitfld.long   0. 19. "  CPA   ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  CNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.long   0. 04.--05.    "  CSIZE  , Cache Size" "8 KB,16 KB,32 KB,64 KB "
endif
sif (STRING.MID(CPU(),1.,5.)=="PC567")||(STRING.MID(CPU(),1.,5.)=="PC564")||(STRING.MID(CPU(),0.,6.)=="SPC564")||(STRING.MID(CPU(),0.,6.)=="SPC56E")||CPUIS(MPC5777C)
group spr:516.--516. "L1CFG1,L1 Cache Configuration Register 1"
LINE.Long  0. "L1CFG1,L1 Cache Configuration Register 1"
bitfld.long  0.  30.--31. "CARCH ,Cache Architecture" "Harvard,Unified,res (10),res (11)"
bitfld.long  0.  29. "            CWPA ,Cache Way Partitioning Available" "0,1"
bitfld.long  0.  28. "  CFAHA ,Cache Flush All by Hardware Available" "0,1"
bitfld.long  0.  27. "  CFISWA ,Cache flush/inval by Set and Way Available" "0,1"
bitfld.long   0. 23.--24. "  CBSIZE ,Cache Line Size" "32 bytes,64 bytes, res(10),res(11)"
TEXTLINE "                 "
bitfld.long   0. 21.--22. "  CREPL ,Cache Replacement Policy" "True LRU,pseudo LRU,pseudo round-robin,FIFO"
bitfld.long   0. 20. "  CLA  ,Cache Locking APU Available" "0,1"
bitfld.long   0. 19. "  CPA   ,Cache Parity Available" "0,1"
bitfld.long   0. 11.--13. "  CNWAY  , Cache Number of Ways" "1,2,3,4,5,6,7,8"
bitfld.long   0. 04.--05.    "  CSIZE  , Cache Size" "8 KB,16 KB,32 KB,64 KB "
endif
tree.end
sif (STRING.MID(CPU(),0.,6.)=="MPC555")||(STRING.MID(CPU(),0.,6.)=="MPC556")||(STRING.MID(CPU(),2.,3.)=="571")||(CPU()=="MPC5668")||(CPU()=="MPC5668G")
tree.open "Unified Cache Control Registers"
sif (CPU()=="MPC5561")||(CPU()=="MPC5566")||string.mid(CPU(),2.,3.)=="571"||(CPU()=="MPC5668")||(CPU()=="MPC5668G")
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register"
bitfld.long  0. 31. "WID0123 ,Way 0 Instruction Disable" "0,1"
bitfld.long  0. 30. ",Way 1 Instruction Disable" "0,1"
bitfld.long  0. 29. ",Way 2 Instruction Disable" "0,1"
bitfld.long  0. 28. ",Way 3 Instruction Disable" "0,1"
bitfld.long  0. 27. " WDD0123 ,Way 0 Data Disable" "0,1"
bitfld.long  0. 26. ",Way 1 Data Disable" "0,1"
bitfld.long  0. 25. ",Way 2 Data Disable" "0,1"
bitfld.long  0. 24. ",Way 3 Data Disable" "0,1"
bitfld.long  0. 23. "  AWID  ,Additional Ways Instruction Disable" "0,1"
bitfld.long  0. 22. "  AWDD ,Additional Ways Data Disable" "0,1"
bitfld.long  0. 21. "  WAM  ,Way Access Mode" "0,1"
bitfld.long  0. 20. "  CWM  ,Cache Write Mode" "WT,CB"
TEXTLINE "                   "
bitfld.long  0. 19. "DPB     ,Disable Push Buffer" "0,1"
bitfld.long  0. 18. "    DSB     ,Disable Store Buffer" "0,1"
bitfld.long  0. 17. "     DSTRM ,Disable Streaming" "0,1 "
bitfld.long  0. 16. " CPE  ,Cache Parity Enable" "0,1"
TEXTLINE "                   "
bitfld.long  0. 10. "CUL     ,Cache Unable to Lock" "0,1"
bitfld.long  0.  9. "    CLO     ,Cache Lock Overflow" "0,1"
bitfld.long  0.  8. "     CLFC  ,Cache Lock Bits Flush Clear" "0,1"
bitfld.long  0.  4. "  CORG ,Cache Organization" "0,1"
bitfld.long  0.  2. "  CABT ,Cache Operation Aborted" "0,1"
sif (CPU()=="MPC5566")
bitfld.long  0.  1. "  CINV ,Cache Flush Invalidate" "0,1"
else
bitfld.long  0.  1. "  CFI  ,Cache Flush Invalidate" "0,1"
endif
bitfld.long  0.  0. "  CE   ,Cache Enable" "0,1"
else
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register"
bitfld.long  0. 31. "WID0123 ,Way 0 Instruction Disable" "0,1"
bitfld.long  0. 30. ",Way 1 Instruction Disable" "0,1"
bitfld.long  0. 29. ",Way 2 Instruction Disable" "0,1"
bitfld.long  0. 28. ",Way 3 Instruction Disable" "0,1"
bitfld.long  0. 27. " WDD0123 ,Way 0 Data Disable" "0,1"
bitfld.long  0. 26. ",Way 1 Data Disable" "0,1"
bitfld.long  0. 25. ",Way 2 Data Disable" "0,1"
bitfld.long  0. 24. ",Way 3 Data Disable" "0,1"
bitfld.long  0. 23. "  AWID  ,Additional Ways Instruction Disable" "0,1"
bitfld.long  0. 22. "  AWDD ,Additional Ways Data Disable" "0,1"
bitfld.long  0. 20. "  CWM  ,Cache Write Mode" "WT,CB"
TEXTLINE "                   "
bitfld.long  0. 19. "DPB     ,Disable Push Buffer" "0,1"
bitfld.long  0. 18. "    DSB     ,Disable Store Buffer" "0,1"
bitfld.long  0. 17. "     DSTRM ,Disable Streaming" "0,1 "
bitfld.long  0. 16. " CPE  ,Cache Parity Enable" "0,1"
TEXTLINE "                   "
bitfld.long  0. 10. "CUL     ,Cache Unable to Lock" "0,1"
bitfld.long  0.  9. "    CLO     ,Cache Lock Overflow" "0,1"
bitfld.long  0.  8. "     CLFC  ,Cache Lock Bits Flush Clear" "0,1"
bitfld.long  0.  2. "  CABT ,Cache Operation Aborted" "0,1"
bitfld.long  0.  1. "  CFI  ,Cache Flush Invalidate" "0,1"
bitfld.long  0.  0. "  CE   ,Cache Enable" "0,1"
endif
group spr:1016.--1016. "L1FINV0,L1 Cache Flush / Invalidate Register"
LINE.long 0. "L1FINV0,L1FINV0,L1 Cache Flush / Invalidate Register"
bitfld.long  0. 24.--26.    "CWAY ,Cache Way Select" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0. 05.--11. 1. "  CSET ,Cache Set Select"
bitfld.long  0. 00.--01.    "  CCMD ,Cache Command" "invalidate w/o flushing,flush if dirty and valid,flush&invalid. if dirty and valid,res."
tree.end
endif
sif (STRING.MID(CPU(),1.,5.)=="PC567")||(STRING.MID(CPU(),1.,5.)=="PC56H")||CPUIS(MPC5777C)
tree.open "Data Cache Control Registers"
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register 0"
bitfld.long  0. 31.      "WID0123  ,Way 0 Instruction Disable" "0,1"
bitfld.long  0. 30.      ",Way 1 Instruction Disable" "0,1"
bitfld.long  0. 29.      ",Way 2 Instruction Disable" "0,1"
bitfld.long  0. 28.      ",Way 3 Instruction Disable" "0,1"
bitfld.long  0. 27.      " WDD0123  ,Way 0 Data Disable" "0,1"
bitfld.long  0. 26.      ",Way 1 Data Disable" "0,1"
bitfld.long  0. 25.      ",Way 2 Data Disable" "0,1"
bitfld.long  0. 24.      ",Way 3 Data Disable" "0,1"
TEXTLINE "                 "
bitfld.long  0. 20.      "  DCWM   ,Cache Write Mode" "WT,CB"
bitfld.long  0. 18.--19. "  DCWA    ,Data Cache Write Allocation Policy" "disabled,CB write miss,CB/WT write miss,reserved"
TEXTLINE "                 "
bitfld.long  0. 16.      "  DCECE   ,Data Cache Error Checking Enable" "0,1"
bitfld.long  0. 15.      "  DCPEI   ,Data Cache Parity Error Injection" "0,1"
bitfld.long  0. 12.--13. "  DCEDT ,Data Cache Error Detection Type" "PAR,EDC,res,res"
TEXTLINE "                 "
bitfld.long  0. 11.      "  DCSLC   ,Data Cache Snoop Lock Clear" "0,1"
bitfld.long  0. 10.      "  DCUL    ,Data Cache Unable to Lock" "0,1"
bitfld.long  0. 09.      "  DCLO    ,Data Cache Lock Overflow" "0,1"
bitfld.long  0. 08.      "  DCLFC   ,Data Cache Lock Bits Flash Clear" "0,1"
bitfld.long  0. 07.      "  DCLOA   ,Data Cache Lock Overflow Allocate" "0,1"
TEXTLINE "                 "
bitfld.long  0. 05.--06. "  DCEA  ,Data Cache Error Action" "MCK,COR,res,res"
bitfld.long  0. 03.      "  DCBZ32  ,Data Cache dcba, dcbz operation length" "0,1"
bitfld.long  0. 02.      "  DCABT   ,Data Cache Operation Aborted" "0,1"
bitfld.long  0. 01.      "  DCINV   ,Data Cache Invalidate" "0,1"
bitfld.long  0. 00.      "  DCE     ,Data Cache Enable" "0,1"
group spr:1016.--1016. "L1FINV0,L1 Cache Flush / Invalidate Register 0"
LINE.long 0. "L1FINV0,L1FINV0,L1 Cache Flush / Invalidate Register 0"
bitfld.long  0. 24.--26.    "CWAY ,Cache Way Select" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0. 05.--11. 1. "  CSET ,Cache Set Select"
bitfld.long  0. 00.--01.    "  CCMD ,Cache Command" "invalidate w/o flushing,flush if dirty and valid,flush&invalid. if dirty and valid,res."
tree.end
tree.open "Instruction Cache Control Registers"
group spr:1011.--1011. "L1CSR1, L1 Cache Configuration & Status Register 1"
LINE.LONG 0. "L1CSR1,L1 Cache Configuration & Status Register 1"
bitfld.long  0. 16.        "ICECE   ,Instruction Cache Error Checking Enable" "0,1"
bitfld.long  0. 15.      "  ICEI    ,Instruction Cache Error Injection Enable" "0,1"
bitfld.long  0. 12.--13. "  ICEDT ,Instruction Cache Error Detection Type" "PAR,EDC,res,res"
TEXTLINE "                 "
bitfld.long  0. 10.      "  ICUL    ,Instruction Cache Unable to Lock" "0,1"
bitfld.long  0. 09.      "  ICLO    ,Instruction Cache Lock Overflow" "0,1"
bitfld.long  0. 08.      "  ICLFC   ,Instruction Cache Lock Bits Flash Clear" "0,1"
bitfld.long  0. 07.      "  ICLOA   ,Instruction Cache Lock Overflow Allocate" "0,1"
TEXTLINE "                 "
bitfld.long  0. 05.--06. "  ICEA  ,Instruction Cache Error Action" "MCK,COR,res,res"
bitfld.long  0. 02.      "  ICABT   ,Instruction Cache Operation Aborted" "0,1"
bitfld.long  0. 01.      "  ICINV   ,Instruction Cache Invalidate" "0,1"
bitfld.long  0. 00.      "  ICE     ,Instruction Cache Enable" "0,1"
group spr:959.--959. "L1FINV1,L1 Cache Flush / Invalidate Register 1"
LINE.long 0. "L1FINV1,L1FINV1,L1 Cache Flush / Invalidate Register 1"
bitfld.long  0. 24.--26.    "CWAY ,Cache Way Select" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0. 05.--11. 1. "  CSET ,Cache Set Select"
bitfld.long  0. 00.--01.    "  CCMD ,Cache Command" "invalidate w/o flushing,flush if dirty and valid,flush&invalid. if dirty and valid,res."
tree.end
endif
sif (STRING.MID(CPU(),1.,5.)=="PC564")||(STRING.MID(CPU(),0.,6.)=="SPC56E")
tree.open "Instruction Cache Control Registers"
group spr:1010.--1010. "L1CSR0, L1 Cache Configuration & Status Register 0"
LINE.LONG 0. "L1CSR0,L1 Cache Configuration & Status Register 0"
bitfld.long  0. 31. "WID0123 ,Way 0 Instruction Disable" "0,1"
bitfld.long  0. 30. ",Way 1 Instruction Disable" "0,1"
bitfld.long  0. 29. ",Way 2 Instruction Disable" "0,1"
bitfld.long  0. 28. ",Way 3 Instruction Disable" "0,1"
group spr:1011.--1011. "L1CSR1, L1 Cache Configuration & Status Register 1"
LINE.LONG 0. "L1CSR1,L1 Cache Configuration & Status Register 1"
bitfld.long  0. 16.        "ICECE   ,Instruction Cache Error Checking Enable" "0,1"
bitfld.long  0. 15.      "  ICEI    ,Instruction Cache Parity Error Injection Enable" "0,1"
bitfld.long  0. 12.--13. "  ICEDT ,Instruction Cache Error Detection Type" "PAR,EDC,res,res"
TEXTLINE "                 "
bitfld.long  0. 10.      "  ICUL    ,Instruction Cache Unable to Lock" "0,1"
bitfld.long  0. 09.      "  ICLO    ,Instruction Cache Lock Overflow" "0,1"
bitfld.long  0. 08.      "  ICLFC   ,Instruction Cache Lock Bits Flash Clear" "0,1"
bitfld.long  0. 07.      "  ICLOA   ,Instruction Cache Lock Overflow Allocate" "0,1"
TEXTLINE "                 "
bitfld.long  0. 05.--06. "  ICEA  ,Instruction Cache Error Action" "MCK,COR,res,res"
bitfld.long  0. 04.      "  ICORG   ,Instruction Cache Organization" "0,1"
bitfld.long  0. 02.      "  ICABT   ,Instruction Cache Operation Aborted" "0,1"
bitfld.long  0. 01.      "  ICINV   ,Instruction Cache Invalidate" "0,1"
bitfld.long  0. 00.      "  ICE     ,Instruction Cache Enable" "0,1"
group spr:959.--959. "L1FINV1,L1 Cache Flush / Invalidate Register 1"
LINE.long 0. "L1FINV1,L1FINV1,L1 Cache Flush / Invalidate Register 1"
bitfld.long  0. 24.--26.    "CWAY ,Cache Way Select" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0. 05.--11. 1. "  CSET ,Cache Set Select"
bitfld.long  0. 00.--01.    "  CCMD ,Cache Command" "invalidate w/o flushing,flush if dirty and valid,flush&invalid. if dirty and valid,res."
tree.end
endif
TEXTLINE "             "